bcm53xx: use two upstream USB bcma patches
[openwrt/openwrt.git] / target / linux / bcm53xx / patches-4.4 / 197-USB-bcma-add-USB-3.0-support.patch
1 From 121ec6539abedbc0e975cf35f48ee044b323e4c3 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
3 Date: Tue, 16 Jun 2015 17:14:26 +0200
4 Subject: [PATCH v3 5/6] usb: bcma: add USB 3.0 support
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
8
9 Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
10 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
11 ---
12 drivers/usb/host/bcma-hcd.c | 225 ++++++++++++++++++++++++++++++++++++++++++++
13 1 file changed, 225 insertions(+)
14
15 --- a/drivers/usb/host/bcma-hcd.c
16 +++ b/drivers/usb/host/bcma-hcd.c
17 @@ -29,6 +29,7 @@
18 #include <linux/of_gpio.h>
19 #include <linux/usb/ehci_pdriver.h>
20 #include <linux/usb/ohci_pdriver.h>
21 +#include <linux/usb/xhci_pdriver.h>
22
23 MODULE_AUTHOR("Hauke Mehrtens");
24 MODULE_DESCRIPTION("Common USB driver for BCMA Bus");
25 @@ -38,6 +39,7 @@ struct bcma_hcd_device {
26 struct bcma_device *core;
27 struct platform_device *ehci_dev;
28 struct platform_device *ohci_dev;
29 + struct platform_device *xhci_dev;
30 struct gpio_desc *gpio_desc;
31 };
32
33 @@ -245,6 +247,10 @@ static const struct usb_ehci_pdata ehci_
34 static const struct usb_ohci_pdata ohci_pdata = {
35 };
36
37 +static const struct usb_xhci_pdata xhci_pdata = {
38 + .usb3_fake_doorbell = 1
39 +};
40 +
41 static struct platform_device *bcma_hcd_create_pdev(struct bcma_device *dev,
42 const char *name, u32 addr,
43 const void *data,
44 @@ -338,6 +344,216 @@ err_unregister_ohci_dev:
45 return err;
46 }
47
48 +static bool bcma_wait_reg(struct bcma_bus *bus, void __iomem *addr, u32 mask,
49 + u32 value, int timeout)
50 +{
51 + unsigned long deadline = jiffies + timeout;
52 + u32 val;
53 +
54 + do {
55 + val = readl(addr);
56 + if ((val & mask) == value)
57 + return true;
58 + cpu_relax();
59 + udelay(10);
60 + } while (!time_after_eq(jiffies, deadline));
61 +
62 + pr_err("Timeout waiting for register %p\n", addr);
63 +
64 + return false;
65 +}
66 +
67 +static void bcma_hcd_usb30_phy_init(struct bcma_hcd_device *bcma_hcd)
68 +{
69 + struct bcma_device *core = bcma_hcd->core;
70 + struct bcma_bus *bus = core->bus;
71 + struct bcma_chipinfo *chipinfo = &bus->chipinfo;
72 + struct bcma_drv_cc_b *ccb = &bus->drv_cc_b;
73 + struct bcma_device *arm_core;
74 + void __iomem *dmu = NULL;
75 + u32 cru_straps_ctrl;
76 +
77 + if (chipinfo->id != BCMA_CHIP_ID_BCM4707 &&
78 + chipinfo->id != BCMA_CHIP_ID_BCM53018)
79 + return;
80 +
81 + arm_core = bcma_find_core(bus, BCMA_CORE_ARMCA9);
82 + if (!arm_core)
83 + return;
84 +
85 + dmu = ioremap_nocache(arm_core->addr_s[0], 0x1000);
86 + if (!dmu)
87 + goto out;
88 +
89 + /* Check strapping of PCIE/USB3 SEL */
90 + cru_straps_ctrl = ioread32(dmu + 0x2a0);
91 + if ((cru_straps_ctrl & 0x10) == 0)
92 + goto out;
93 +
94 + /* Perform USB3 system soft reset */
95 + bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
96 +
97 + /* Enable MDIO. Setting MDCDIV as 26 */
98 + iowrite32(0x0000009a, ccb->mii + 0x000);
99 + udelay(2);
100 +
101 + switch (chipinfo->id) {
102 + case BCMA_CHIP_ID_BCM4707:
103 + if (chipinfo->rev == 4) {
104 + /* For NS-B0, USB3 PLL Block */
105 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
106 + iowrite32(0x587e8000, ccb->mii + 0x004);
107 +
108 + /* Clear ana_pllSeqStart */
109 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
110 + iowrite32(0x58061000, ccb->mii + 0x004);
111 +
112 + /* CMOS Divider ratio to 25 */
113 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
114 + iowrite32(0x582a6400, ccb->mii + 0x004);
115 +
116 + /* Asserting PLL Reset */
117 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
118 + iowrite32(0x582ec000, ccb->mii + 0x004);
119 +
120 + /* Deaaserting PLL Reset */
121 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
122 + iowrite32(0x582e8000, ccb->mii + 0x004);
123 +
124 + /* Deasserting USB3 system reset */
125 + bcma_awrite32(core, BCMA_RESET_CTL, 0);
126 +
127 + /* Set ana_pllSeqStart */
128 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
129 + iowrite32(0x58069000, ccb->mii + 0x004);
130 +
131 + /* RXPMD block */
132 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
133 + iowrite32(0x587e8020, ccb->mii + 0x004);
134 +
135 + /* CDR int loop locking BW to 1 */
136 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
137 + iowrite32(0x58120049, ccb->mii + 0x004);
138 +
139 + /* CDR int loop acquisition BW to 1 */
140 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
141 + iowrite32(0x580e0049, ccb->mii + 0x004);
142 +
143 + /* CDR prop loop BW to 1 */
144 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
145 + iowrite32(0x580a005c, ccb->mii + 0x004);
146 +
147 + /* Waiting MII Mgt interface idle */
148 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
149 + } else {
150 + /* PLL30 block */
151 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
152 + iowrite32(0x587e8000, ccb->mii + 0x004);
153 +
154 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
155 + iowrite32(0x582a6400, ccb->mii + 0x004);
156 +
157 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
158 + iowrite32(0x587e80e0, ccb->mii + 0x004);
159 +
160 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
161 + iowrite32(0x580a009c, ccb->mii + 0x004);
162 +
163 + /* Enable SSC */
164 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
165 + iowrite32(0x587e8040, ccb->mii + 0x004);
166 +
167 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
168 + iowrite32(0x580a21d3, ccb->mii + 0x004);
169 +
170 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
171 + iowrite32(0x58061003, ccb->mii + 0x004);
172 +
173 + /* Waiting MII Mgt interface idle */
174 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
175 +
176 + /* Deasserting USB3 system reset */
177 + bcma_awrite32(core, BCMA_RESET_CTL, 0);
178 + }
179 + break;
180 + case BCMA_CHIP_ID_BCM53018:
181 + /* USB3 PLL Block */
182 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
183 + iowrite32(0x587e8000, ccb->mii + 0x004);
184 +
185 + /* Assert Ana_Pllseq start */
186 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
187 + iowrite32(0x58061000, ccb->mii + 0x004);
188 +
189 + /* Assert CML Divider ratio to 26 */
190 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
191 + iowrite32(0x582a6400, ccb->mii + 0x004);
192 +
193 + /* Asserting PLL Reset */
194 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
195 + iowrite32(0x582ec000, ccb->mii + 0x004);
196 +
197 + /* Deaaserting PLL Reset */
198 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
199 + iowrite32(0x582e8000, ccb->mii + 0x004);
200 +
201 + /* Waiting MII Mgt interface idle */
202 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
203 +
204 + /* Deasserting USB3 system reset */
205 + bcma_awrite32(core, BCMA_RESET_CTL, 0);
206 +
207 + /* PLL frequency monitor enable */
208 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
209 + iowrite32(0x58069000, ccb->mii + 0x004);
210 +
211 + /* PIPE Block */
212 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
213 + iowrite32(0x587e8060, ccb->mii + 0x004);
214 +
215 + /* CMPMAX & CMPMINTH setting */
216 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
217 + iowrite32(0x580af30d, ccb->mii + 0x004);
218 +
219 + /* DEGLITCH MIN & MAX setting */
220 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
221 + iowrite32(0x580e6302, ccb->mii + 0x004);
222 +
223 + /* TXPMD block */
224 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
225 + iowrite32(0x587e8040, ccb->mii + 0x004);
226 +
227 + /* Enabling SSC */
228 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
229 + iowrite32(0x58061003, ccb->mii + 0x004);
230 +
231 + /* Waiting MII Mgt interface idle */
232 + bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
233 +
234 + break;
235 + }
236 +out:
237 + if (dmu)
238 + iounmap(dmu);
239 +}
240 +
241 +static int bcma_hcd_usb30_init(struct bcma_hcd_device *bcma_hcd)
242 +{
243 + struct bcma_device *core = bcma_hcd->core;
244 +
245 + bcma_core_enable(core, 0);
246 +
247 + bcma_hcd_usb30_phy_init(bcma_hcd);
248 +
249 + bcma_hcd->xhci_dev = bcma_hcd_create_pdev(core, "xhci-hcd", core->addr,
250 + &xhci_pdata,
251 + sizeof(xhci_pdata));
252 + if (IS_ERR(bcma_hcd->ohci_dev))
253 + return PTR_ERR(bcma_hcd->ohci_dev);
254 +
255 + return 0;
256 +}
257 +
258 static int bcma_hcd_probe(struct bcma_device *core)
259 {
260 int err;
261 @@ -364,6 +580,11 @@ static int bcma_hcd_probe(struct bcma_de
262 if (err)
263 return err;
264 break;
265 + case BCMA_CORE_NS_USB30:
266 + err = bcma_hcd_usb30_init(usb_dev);
267 + if (err)
268 + return err;
269 + break;
270 default:
271 return -ENODEV;
272 }
273 @@ -377,11 +598,14 @@ static void bcma_hcd_remove(struct bcma_
274 struct bcma_hcd_device *usb_dev = bcma_get_drvdata(dev);
275 struct platform_device *ohci_dev = usb_dev->ohci_dev;
276 struct platform_device *ehci_dev = usb_dev->ehci_dev;
277 + struct platform_device *xhci_dev = usb_dev->xhci_dev;
278
279 if (ohci_dev)
280 platform_device_unregister(ohci_dev);
281 if (ehci_dev)
282 platform_device_unregister(ehci_dev);
283 + if (xhci_dev)
284 + platform_device_unregister(xhci_dev);
285
286 bcma_core_disable(dev, 0);
287 }
288 @@ -418,6 +642,7 @@ static int bcma_hcd_resume(struct bcma_d
289 static const struct bcma_device_id bcma_hcd_table[] = {
290 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_USB20_HOST, BCMA_ANY_REV, BCMA_ANY_CLASS),
291 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_USB20, BCMA_ANY_REV, BCMA_ANY_CLASS),
292 + BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_USB30, BCMA_ANY_REV, BCMA_ANY_CLASS),
293 {},
294 };
295 MODULE_DEVICE_TABLE(bcma, bcma_hcd_table);