target/linux/bcm53xx/patches-4.4/197-USB-bcma-add-USB-3.0-support.patch

   1 From 121ec6539abedbc0e975cf35f48ee044b323e4c3 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
   3 Date: Tue, 16 Jun 2015 17:14:26 +0200
   4 Subject: [PATCH v3 5/6] usb: bcma: add USB 3.0 support
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
  10 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
  11 ---
  12  drivers/usb/host/bcma-hcd.c | 225 ++++++++++++++++++++++++++++++++++++++++++++
  13  1 file changed, 225 insertions(+)
  14
  15 --- a/drivers/usb/host/bcma-hcd.c
  16 +++ b/drivers/usb/host/bcma-hcd.c
  17 @@ -30,6 +30,7 @@
  18  #include <linux/of_platform.h>
  19  #include <linux/usb/ehci_pdriver.h>
  20  #include <linux/usb/ohci_pdriver.h>
  21 +#include <linux/usb/xhci_pdriver.h>
  22
  23  MODULE_AUTHOR("Hauke Mehrtens");
  24  MODULE_DESCRIPTION("Common USB driver for BCMA Bus");
  25 @@ -42,6 +43,7 @@ struct bcma_hcd_device {
  26         struct bcma_device *core;
  27         struct platform_device *ehci_dev;
  28         struct platform_device *ohci_dev;
  29 +       struct platform_device *xhci_dev;
  30         struct gpio_desc *gpio_desc;
  31  };
  32
  33 @@ -319,6 +321,10 @@ static const struct usb_ehci_pdata ehci_
  34  static const struct usb_ohci_pdata ohci_pdata = {
  35  };
  36
  37 +static const struct usb_xhci_pdata xhci_pdata = {
  38 +       .usb3_fake_doorbell = 1
  39 +};
  40 +
  41  static struct platform_device *bcma_hcd_create_pdev(struct bcma_device *dev,
  42                                                     const char *name, u32 addr,
  43                                                     const void *data,
  44 @@ -412,6 +418,150 @@ err_unregister_ohci_dev:
  45         return err;
  46  }
  47
  48 +static bool bcma_wait_reg(struct bcma_bus *bus, void __iomem *addr, u32 mask,
  49 +                         u32 value, int timeout)
  50 +{
  51 +       unsigned long deadline = jiffies + timeout;
  52 +       u32 val;
  53 +
  54 +       do {
  55 +               val = readl(addr);
  56 +               if ((val & mask) == value)
  57 +                       return true;
  58 +               cpu_relax();
  59 +               udelay(10);
  60 +       } while (!time_after_eq(jiffies, deadline));
  61 +
  62 +       pr_err("Timeout waiting for register %p\n", addr);
  63 +
  64 +       return false;
  65 +}
  66 +
  67 +static void bcma_hcd_usb30_phy_init(struct bcma_hcd_device *bcma_hcd)
  68 +{
  69 +       struct bcma_device *core = bcma_hcd->core;
  70 +       struct bcma_bus *bus = core->bus;
  71 +       struct bcma_chipinfo *chipinfo = &bus->chipinfo;
  72 +       struct bcma_drv_cc_b *ccb = &bus->drv_cc_b;
  73 +       struct bcma_device *arm_core;
  74 +       void __iomem *dmu = NULL;
  75 +       u32 cru_straps_ctrl;
  76 +
  77 +       if (chipinfo->id != BCMA_CHIP_ID_BCM4707 &&
  78 +           chipinfo->id != BCMA_CHIP_ID_BCM47094 &&
  79 +           chipinfo->id != BCMA_CHIP_ID_BCM53018)
  80 +               return;
  81 +
  82 +       arm_core = bcma_find_core(bus, BCMA_CORE_ARMCA9);
  83 +       if (!arm_core)
  84 +               return;
  85 +
  86 +       dmu = ioremap_nocache(arm_core->addr_s[0], 0x1000);
  87 +       if (!dmu)
  88 +               goto out;
  89 +
  90 +       /* Check strapping of PCIE/USB3 SEL */
  91 +       cru_straps_ctrl = ioread32(dmu + 0x2a0);
  92 +       if ((cru_straps_ctrl & 0x10) == 0)
  93 +               goto out;
  94 +
  95 +       /* Perform USB3 system soft reset */
  96 +       bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
  97 +
  98 +       /* Enable MDIO. Setting MDCDIV as 26  */
  99 +       iowrite32(0x0000009a, ccb->mii + 0x000);
 100 +       udelay(2);
 101 +
 102 +       if (chipinfo->id == BCMA_CHIP_ID_BCM53018 ||
 103 +           (chipinfo->id == BCMA_CHIP_ID_BCM4707 && (chipinfo->rev == 4 || chipinfo->rev == 6)) ||
 104 +           chipinfo->id == BCMA_CHIP_ID_BCM47094) {
 105 +                       /* For NS-B0, USB3 PLL Block */
 106 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 107 +                       iowrite32(0x587e8000, ccb->mii + 0x004);
 108 +
 109 +                       /* Clear ana_pllSeqStart */
 110 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 111 +                       iowrite32(0x58061000, ccb->mii + 0x004);
 112 +
 113 +                       /* CMOS Divider ratio to 25 */
 114 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 115 +                       iowrite32(0x582a6400, ccb->mii + 0x004);
 116 +
 117 +                       /* Asserting PLL Reset */
 118 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 119 +                       iowrite32(0x582ec000, ccb->mii + 0x004);
 120 +
 121 +                       /* Deaaserting PLL Reset */
 122 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 123 +                       iowrite32(0x582e8000, ccb->mii + 0x004);
 124 +
 125 +                       /* Waiting MII Mgt interface idle */
 126 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 127 +
 128 +                       /* Deasserting USB3 system reset */
 129 +                       bcma_awrite32(core, BCMA_RESET_CTL, 0);
 130 +
 131 +                       /* PLL frequency monitor enable */
 132 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 133 +                       iowrite32(0x58069000, ccb->mii + 0x004);
 134 +
 135 +                       /* PIPE Block */
 136 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 137 +                       iowrite32(0x587e8060, ccb->mii + 0x004);
 138 +
 139 +                       /* CMPMAX & CMPMINTH setting */
 140 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 141 +                       iowrite32(0x580af30d, ccb->mii + 0x004);
 142 +
 143 +                       /* DEGLITCH MIN & MAX setting */
 144 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 145 +                       iowrite32(0x580e6302, ccb->mii + 0x004);
 146 +
 147 +                       /* TXPMD block */
 148 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 149 +                       iowrite32(0x587e8040, ccb->mii + 0x004);
 150 +
 151 +                       /* Enabling SSC */
 152 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 153 +                       iowrite32(0x58061003, ccb->mii + 0x004);
 154 +
 155 +                       /* Waiting MII Mgt interface idle */
 156 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 157 +       } else if (chipinfo->id == BCMA_CHIP_ID_BCM4707) {
 158 +                       /* PLL30 block */
 159 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 160 +                       iowrite32(0x587e8000, ccb->mii + 0x004);
 161 +
 162 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 163 +                       iowrite32(0x582a6400, ccb->mii + 0x004);
 164 +
 165 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 166 +                       iowrite32(0x587e80e0, ccb->mii + 0x004);
 167 +
 168 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 169 +                       iowrite32(0x580a009c, ccb->mii + 0x004);
 170 +
 171 +                       /* Enable SSC */
 172 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 173 +                       iowrite32(0x587e8040, ccb->mii + 0x004);
 174 +
 175 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 176 +                       iowrite32(0x580a21d3, ccb->mii + 0x004);
 177 +
 178 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 179 +                       iowrite32(0x58061003, ccb->mii + 0x004);
 180 +
 181 +                       /* Waiting MII Mgt interface idle */
 182 +                       bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
 183 +
 184 +                       /* Deasserting USB3 system reset */
 185 +                       bcma_awrite32(core, BCMA_RESET_CTL, 0);
 186 +       }
 187 +out:
 188 +       if (dmu)
 189 +               iounmap(dmu);
 190 +}
 191 +
 192  static int bcma_hcd_usb30_init(struct bcma_hcd_device *bcma_hcd)
 193  {
 194         struct bcma_device *core = bcma_hcd->core;
 195 @@ -419,6 +569,14 @@ static int bcma_hcd_usb30_init(struct bc
 196
 197         bcma_core_enable(core, 0);
 198
 199 +       bcma_hcd_usb30_phy_init(bcma_hcd);
 200 +
 201 +       bcma_hcd->xhci_dev = bcma_hcd_create_pdev(core, "xhci-hcd", core->addr,
 202 +                                                 &xhci_pdata,
 203 +                                                 sizeof(xhci_pdata));
 204 +       if (IS_ERR(bcma_hcd->ohci_dev))
 205 +               return PTR_ERR(bcma_hcd->ohci_dev);
 206 +
 207         of_platform_default_populate(dev->of_node, NULL, dev);
 208
 209         return 0;
 210 @@ -471,11 +629,14 @@ static void bcma_hcd_remove(struct bcma_
 211         struct bcma_hcd_device *usb_dev = bcma_get_drvdata(dev);
 212         struct platform_device *ohci_dev = usb_dev->ohci_dev;
 213         struct platform_device *ehci_dev = usb_dev->ehci_dev;
 214 +       struct platform_device *xhci_dev = usb_dev->xhci_dev;
 215
 216         if (ohci_dev)
 217                 platform_device_unregister(ohci_dev);
 218         if (ehci_dev)
 219                 platform_device_unregister(ehci_dev);
 220 +       if (xhci_dev)
 221 +               platform_device_unregister(xhci_dev);
 222
 223         bcma_core_disable(dev, 0);
 224  }