projects / openwrt / openwrt.git / blob
? search:


4aad6868f3c8a9f41e233d5e7139042a85bbb66f
[openwrt/openwrt.git] / target / linux / bcm53xx / patches-4.4 / 800-Revert-PCI-iproc-Add-PAXC-interface-support.patch
1 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
2 Subject: [PATCH] Revert "PCI: iproc: Add PAXC interface support"
3 MIME-Version: 1.0
4 Content-Type: text/plain; charset=UTF-8
5 Content-Transfer-Encoding: 8bit
6
7 Adding PAXC support fixed all "invalid BAR" firmware bug messages but
8 also broke finding extra buses and attached devices. This affected
9 e.g. Netgear R8000 which has 2 (out of 3) BCM43602 cards connected to
10 the 2nd "PCIe Gen 2" controller. None of them is detected with PAXC
11 code.
12
13 This reverts commit 943ebae781f519ecfecbfa1b997f15f59116e41d.
14
15 Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
16 ---
17 drivers/pci/host/pcie-iproc-platform.c | 24 +---
18 drivers/pci/host/pcie-iproc.c | 202 ++++++---------------------------
19 drivers/pci/host/pcie-iproc.h | 19 ----
20 3 files changed, 40 insertions(+), 205 deletions(-)
21
22 --- a/drivers/pci/host/pcie-iproc-platform.c
23 +++ b/drivers/pci/host/pcie-iproc-platform.c
24 @@ -26,21 +26,8 @@
25
26 #include "pcie-iproc.h"
27
28 -static const struct of_device_id iproc_pcie_of_match_table[] = {
29 - {
30 - .compatible = "brcm,iproc-pcie",
31 - .data = (int *)IPROC_PCIE_PAXB,
32 - }, {
33 - .compatible = "brcm,iproc-pcie-paxc",
34 - .data = (int *)IPROC_PCIE_PAXC,
35 - },
36 - { /* sentinel */ }
37 -};
38 -MODULE_DEVICE_TABLE(of, iproc_pcie_of_match_table);
39 -
40 static int iproc_pcie_pltfm_probe(struct platform_device *pdev)
41 {
42 - const struct of_device_id *of_id;
43 struct iproc_pcie *pcie;
44 struct device_node *np = pdev->dev.of_node;
45 struct resource reg;
46 @@ -48,16 +35,11 @@ static int iproc_pcie_pltfm_probe(struct
47 LIST_HEAD(res);
48 int ret;
49
50 - of_id = of_match_device(iproc_pcie_of_match_table, &pdev->dev);
51 - if (!of_id)
52 - return -EINVAL;
53 -
54 pcie = devm_kzalloc(&pdev->dev, sizeof(struct iproc_pcie), GFP_KERNEL);
55 if (!pcie)
56 return -ENOMEM;
57
58 pcie->dev = &pdev->dev;
59 - pcie->type = (enum iproc_pcie_type)of_id->data;
60 platform_set_drvdata(pdev, pcie);
61
62 ret = of_address_to_resource(np, 0, &reg);
63 @@ -133,6 +115,12 @@ static int iproc_pcie_pltfm_remove(struc
64 return iproc_pcie_remove(pcie);
65 }
66
67 +static const struct of_device_id iproc_pcie_of_match_table[] = {
68 + { .compatible = "brcm,iproc-pcie", },
69 + { /* sentinel */ }
70 +};
71 +MODULE_DEVICE_TABLE(of, iproc_pcie_of_match_table);
72 +
73 static struct platform_driver iproc_pcie_pltfm_driver = {
74 .driver = {
75 .name = "iproc-pcie",
76 --- a/drivers/pci/host/pcie-iproc.c
77 +++ b/drivers/pci/host/pcie-iproc.c
78 @@ -30,16 +30,20 @@
79
80 #include "pcie-iproc.h"
81
82 +#define CLK_CONTROL_OFFSET 0x000
83 #define EP_PERST_SOURCE_SELECT_SHIFT 2
84 #define EP_PERST_SOURCE_SELECT BIT(EP_PERST_SOURCE_SELECT_SHIFT)
85 #define EP_MODE_SURVIVE_PERST_SHIFT 1
86 #define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT)
87 #define RC_PCIE_RST_OUTPUT_SHIFT 0
88 #define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT)
89 -#define PAXC_RESET_MASK 0x7f
90
91 +#define CFG_IND_ADDR_OFFSET 0x120
92 #define CFG_IND_ADDR_MASK 0x00001ffc
93
94 +#define CFG_IND_DATA_OFFSET 0x124
95 +
96 +#define CFG_ADDR_OFFSET 0x1f8
97 #define CFG_ADDR_BUS_NUM_SHIFT 20
98 #define CFG_ADDR_BUS_NUM_MASK 0x0ff00000
99 #define CFG_ADDR_DEV_NUM_SHIFT 15
100 @@ -51,8 +55,12 @@
101 #define CFG_ADDR_CFG_TYPE_SHIFT 0
102 #define CFG_ADDR_CFG_TYPE_MASK 0x00000003
103
104 +#define CFG_DATA_OFFSET 0x1fc
105 +
106 +#define SYS_RC_INTX_EN 0x330
107 #define SYS_RC_INTX_MASK 0xf
108
109 +#define PCIE_LINK_STATUS_OFFSET 0xf0c
110 #define PCIE_PHYLINKUP_SHIFT 3
111 #define PCIE_PHYLINKUP BIT(PCIE_PHYLINKUP_SHIFT)
112 #define PCIE_DL_ACTIVE_SHIFT 2
113 @@ -63,54 +71,12 @@
114 #define OARR_SIZE_CFG_SHIFT 1
115 #define OARR_SIZE_CFG BIT(OARR_SIZE_CFG_SHIFT)
116
117 -#define MAX_NUM_OB_WINDOWS 2
118 -#define MAX_NUM_PAXC_PF 4
119 -
120 -#define IPROC_PCIE_REG_INVALID 0xffff
121 +#define OARR_LO(window) (0xd20 + (window) * 8)
122 +#define OARR_HI(window) (0xd24 + (window) * 8)
123 +#define OMAP_LO(window) (0xd40 + (window) * 8)
124 +#define OMAP_HI(window) (0xd44 + (window) * 8)
125
126 -enum iproc_pcie_reg {
127 - IPROC_PCIE_CLK_CTRL = 0,
128 - IPROC_PCIE_CFG_IND_ADDR,
129 - IPROC_PCIE_CFG_IND_DATA,
130 - IPROC_PCIE_CFG_ADDR,
131 - IPROC_PCIE_CFG_DATA,
132 - IPROC_PCIE_INTX_EN,
133 - IPROC_PCIE_OARR_LO,
134 - IPROC_PCIE_OARR_HI,
135 - IPROC_PCIE_OMAP_LO,
136 - IPROC_PCIE_OMAP_HI,
137 - IPROC_PCIE_LINK_STATUS,
138 -};
139 -
140 -/* iProc PCIe PAXB registers */
141 -static const u16 iproc_pcie_reg_paxb[] = {
142 - [IPROC_PCIE_CLK_CTRL] = 0x000,
143 - [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
144 - [IPROC_PCIE_CFG_IND_DATA] = 0x124,
145 - [IPROC_PCIE_CFG_ADDR] = 0x1f8,
146 - [IPROC_PCIE_CFG_DATA] = 0x1fc,
147 - [IPROC_PCIE_INTX_EN] = 0x330,
148 - [IPROC_PCIE_OARR_LO] = 0xd20,
149 - [IPROC_PCIE_OARR_HI] = 0xd24,
150 - [IPROC_PCIE_OMAP_LO] = 0xd40,
151 - [IPROC_PCIE_OMAP_HI] = 0xd44,
152 - [IPROC_PCIE_LINK_STATUS] = 0xf0c,
153 -};
154 -
155 -/* iProc PCIe PAXC v1 registers */
156 -static const u16 iproc_pcie_reg_paxc[] = {
157 - [IPROC_PCIE_CLK_CTRL] = 0x000,
158 - [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,
159 - [IPROC_PCIE_CFG_IND_DATA] = 0x1f4,
160 - [IPROC_PCIE_CFG_ADDR] = 0x1f8,
161 - [IPROC_PCIE_CFG_DATA] = 0x1fc,
162 - [IPROC_PCIE_INTX_EN] = IPROC_PCIE_REG_INVALID,
163 - [IPROC_PCIE_OARR_LO] = IPROC_PCIE_REG_INVALID,
164 - [IPROC_PCIE_OARR_HI] = IPROC_PCIE_REG_INVALID,
165 - [IPROC_PCIE_OMAP_LO] = IPROC_PCIE_REG_INVALID,
166 - [IPROC_PCIE_OMAP_HI] = IPROC_PCIE_REG_INVALID,
167 - [IPROC_PCIE_LINK_STATUS] = IPROC_PCIE_REG_INVALID,
168 -};
169 +#define MAX_NUM_OB_WINDOWS 2
170
171 static inline struct iproc_pcie *iproc_data(struct pci_bus *bus)
172 {
173 @@ -125,65 +91,6 @@ static inline struct iproc_pcie *iproc_d
174 return pcie;
175 }
176
177 -static inline bool iproc_pcie_reg_is_invalid(u16 reg_offset)
178 -{
179 - return !!(reg_offset == IPROC_PCIE_REG_INVALID);
180 -}
181 -
182 -static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie,
183 - enum iproc_pcie_reg reg)
184 -{
185 - return pcie->reg_offsets[reg];
186 -}
187 -
188 -static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie,
189 - enum iproc_pcie_reg reg)
190 -{
191 - u16 offset = iproc_pcie_reg_offset(pcie, reg);
192 -
193 - if (iproc_pcie_reg_is_invalid(offset))
194 - return 0;
195 -
196 - return readl(pcie->base + offset);
197 -}
198 -
199 -static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie,
200 - enum iproc_pcie_reg reg, u32 val)
201 -{
202 - u16 offset = iproc_pcie_reg_offset(pcie, reg);
203 -
204 - if (iproc_pcie_reg_is_invalid(offset))
205 - return;
206 -
207 - writel(val, pcie->base + offset);
208 -}
209 -
210 -static inline void iproc_pcie_ob_write(struct iproc_pcie *pcie,
211 - enum iproc_pcie_reg reg,
212 - unsigned window, u32 val)
213 -{
214 - u16 offset = iproc_pcie_reg_offset(pcie, reg);
215 -
216 - if (iproc_pcie_reg_is_invalid(offset))
217 - return;
218 -
219 - writel(val, pcie->base + offset + (window * 8));
220 -}
221 -
222 -static inline bool iproc_pcie_device_is_valid(struct iproc_pcie *pcie,
223 - unsigned int slot,
224 - unsigned int fn)
225 -{
226 - if (slot > 0)
227 - return false;
228 -
229 - /* PAXC can only support limited number of functions */
230 - if (pcie->type == IPROC_PCIE_PAXC && fn >= MAX_NUM_PAXC_PF)
231 - return false;
232 -
233 - return true;
234 -}
235 -
236 /**
237 * Note access to the configuration registers are protected at the higher layer
238 * by 'pci_lock' in drivers/pci/access.c
239 @@ -197,34 +104,28 @@ static void __iomem *iproc_pcie_map_cfg_
240 unsigned fn = PCI_FUNC(devfn);
241 unsigned busno = bus->number;
242 u32 val;
243 - u16 offset;
244 -
245 - if (!iproc_pcie_device_is_valid(pcie, slot, fn))
246 - return NULL;
247
248 /* root complex access */
249 if (busno == 0) {
250 - iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR,
251 - where & CFG_IND_ADDR_MASK);
252 - offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_IND_DATA);
253 - if (iproc_pcie_reg_is_invalid(offset))
254 + if (slot >= 1)
255 return NULL;
256 - else
257 - return (pcie->base + offset);
258 + writel(where & CFG_IND_ADDR_MASK,
259 + pcie->base + CFG_IND_ADDR_OFFSET);
260 + return (pcie->base + CFG_IND_DATA_OFFSET);
261 }
262
263 + if (fn > 1)
264 + return NULL;
265 +
266 /* EP device access */
267 val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
268 (slot << CFG_ADDR_DEV_NUM_SHIFT) |
269 (fn << CFG_ADDR_FUNC_NUM_SHIFT) |
270 (where & CFG_ADDR_REG_NUM_MASK) |
271 (1 & CFG_ADDR_CFG_TYPE_MASK);
272 - iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val);
273 - offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA);
274 - if (iproc_pcie_reg_is_invalid(offset))
275 - return NULL;
276 - else
277 - return (pcie->base + offset);
278 + writel(val, pcie->base + CFG_ADDR_OFFSET);
279 +
280 + return (pcie->base + CFG_DATA_OFFSET);
281 }
282
283 static struct pci_ops iproc_pcie_ops = {
284 @@ -237,29 +138,18 @@ static void iproc_pcie_reset(struct ipro
285 {
286 u32 val;
287
288 - if (pcie->type == IPROC_PCIE_PAXC) {
289 - val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
290 - val &= ~PAXC_RESET_MASK;
291 - iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
292 - udelay(100);
293 - val |= PAXC_RESET_MASK;
294 - iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
295 - udelay(100);
296 - return;
297 - }
298 -
299 /*
300 * Select perst_b signal as reset source. Put the device into reset,
301 * and then bring it out of reset
302 */
303 - val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
304 + val = readl(pcie->base + CLK_CONTROL_OFFSET);
305 val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST &
306 ~RC_PCIE_RST_OUTPUT;
307 - iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
308 + writel(val, pcie->base + CLK_CONTROL_OFFSET);
309 udelay(250);
310
311 val |= RC_PCIE_RST_OUTPUT;
312 - iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
313 + writel(val, pcie->base + CLK_CONTROL_OFFSET);
314 msleep(100);
315 }
316
317 @@ -270,14 +160,7 @@ static int iproc_pcie_check_link(struct
318 u16 pos, link_status;
319 bool link_is_active = false;
320
321 - /*
322 - * PAXC connects to emulated endpoint devices directly and does not
323 - * have a Serdes. Therefore skip the link detection logic here.
324 - */
325 - if (pcie->type == IPROC_PCIE_PAXC)
326 - return 0;
327 -
328 - val = iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS);
329 + val = readl(pcie->base + PCIE_LINK_STATUS_OFFSET);
330 if (!(val & PCIE_PHYLINKUP) || !(val & PCIE_DL_ACTIVE)) {
331 dev_err(pcie->dev, "PHY or data link is INACTIVE!\n");
332 return -ENODEV;
333 @@ -338,7 +221,7 @@ static int iproc_pcie_check_link(struct
334
335 static void iproc_pcie_enable(struct iproc_pcie *pcie)
336 {
337 - iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, SYS_RC_INTX_MASK);
338 + writel(SYS_RC_INTX_MASK, pcie->base + SYS_RC_INTX_EN);
339 }
340
341 /**
342 @@ -389,15 +272,11 @@ static int iproc_pcie_setup_ob(struct ip
343 axi_addr -= ob->axi_offset;
344
345 for (i = 0; i < MAX_NUM_OB_WINDOWS; i++) {
346 - iproc_pcie_ob_write(pcie, IPROC_PCIE_OARR_LO, i,
347 - lower_32_bits(axi_addr) | OARR_VALID |
348 - (ob->set_oarr_size ? 1 : 0));
349 - iproc_pcie_ob_write(pcie, IPROC_PCIE_OARR_HI, i,
350 - upper_32_bits(axi_addr));
351 - iproc_pcie_ob_write(pcie, IPROC_PCIE_OMAP_LO, i,
352 - lower_32_bits(pci_addr));
353 - iproc_pcie_ob_write(pcie, IPROC_PCIE_OMAP_HI, i,
354 - upper_32_bits(pci_addr));
355 + writel(lower_32_bits(axi_addr) | OARR_VALID |
356 + (ob->set_oarr_size ? 1 : 0), pcie->base + OARR_LO(i));
357 + writel(upper_32_bits(axi_addr), pcie->base + OARR_HI(i));
358 + writel(lower_32_bits(pci_addr), pcie->base + OMAP_LO(i));
359 + writel(upper_32_bits(pci_addr), pcie->base + OMAP_HI(i));
360
361 size -= ob->window_size;
362 if (size == 0)
363 @@ -481,19 +360,6 @@ int iproc_pcie_setup(struct iproc_pcie *
364 goto err_exit_phy;
365 }
366
367 - switch (pcie->type) {
368 - case IPROC_PCIE_PAXB:
369 - pcie->reg_offsets = iproc_pcie_reg_paxb;
370 - break;
371 - case IPROC_PCIE_PAXC:
372 - pcie->reg_offsets = iproc_pcie_reg_paxc;
373 - break;
374 - default:
375 - dev_err(pcie->dev, "incompatible iProc PCIe interface\n");
376 - ret = -EINVAL;
377 - goto err_power_off_phy;
378 - }
379 -
380 iproc_pcie_reset(pcie);
381
382 if (pcie->need_ob_cfg) {
383 --- a/drivers/pci/host/pcie-iproc.h
384 +++ b/drivers/pci/host/pcie-iproc.h
385 @@ -15,20 +15,6 @@
386 #define _PCIE_IPROC_H
387
388 /**
389 - * iProc PCIe interface type
390 - *
391 - * PAXB is the wrapper used in root complex that can be connected to an
392 - * external endpoint device.
393 - *
394 - * PAXC is the wrapper used in root complex dedicated for internal emulated
395 - * endpoint devices.
396 - */
397 -enum iproc_pcie_type {
398 - IPROC_PCIE_PAXB = 0,
399 - IPROC_PCIE_PAXC,
400 -};
401 -
402 -/**
403 * iProc PCIe outbound mapping
404 * @set_oarr_size: indicates the OARR size bit needs to be set
405 * @axi_offset: offset from the AXI address to the internal address used by
406 @@ -45,10 +31,7 @@ struct iproc_msi;
407
408 /**
409 * iProc PCIe device
410 - *
411 * @dev: pointer to device data structure
412 - * @type: iProc PCIe interface type
413 - * @reg_offsets: register offsets
414 * @base: PCIe host controller I/O register base
415 * @base_addr: PCIe host controller register base physical address
416 * @sysdata: Per PCI controller data (ARM-specific)
417 @@ -61,8 +44,6 @@ struct iproc_msi;
418 */
419 struct iproc_pcie {
420 struct device *dev;
421 - enum iproc_pcie_type type;
422 - const u16 *reg_offsets;
423 void __iomem *base;
424 phys_addr_t base_addr;
425 #ifdef CONFIG_ARM
OpenWrt Source Repository