target/linux/bcm53xx/patches-4.9/300-ARM-BCM5301X-Disable-MMU-and-Dcache-during-decompres.patch

   1 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
   2 Date: Wed, 24 Sep 2014 22:14:07 +0200
   3 Subject: [PATCH] ARM: BCM5301X: Disable MMU and Dcache during decompression
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   7
   8 Broadcom devices have broken CFE (bootloader) that leaves hardware in an
   9 invalid state. It causes problems with booting Linux. On Northstar
  10 devices kernel was randomly hanging in ~25% of tries during early init.
  11 Hangs used to happen at random places in the start_kernel. On BCM53573
  12 kernel doesn't even seem to start booting.
  13
  14 To workaround this problem we need to do following very early:
  15 1) Clear 2 following bits in the SCTLR register:
  16 #define CR_M    (1 << 0)        /* MMU enable */
  17 #define CR_C    (1 << 2)        /* Dcache enable */
  18 2) Flush the whole D-cache
  19 3) Disable L2 cache
  20
  21 Unfortunately this patch is not upstreamable as it does above things
  22 unconditionally. We can't check if we are running on Broadcom platform
  23 in any safe way and doing such hacks with ARCH_MULTI_V7 is unacceptable
  24 as it could break other devices support.
  25
  26 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
  27 ---
  28
  29 --- a/arch/arm/boot/compressed/Makefile
  30 +++ b/arch/arm/boot/compressed/Makefile
  31 @@ -31,6 +31,11 @@ ifeq ($(CONFIG_ARCH_ACORN),y)
  32  OBJS           += ll_char_wr.o font.o
  33  endif
  34
  35 +ifeq ($(CONFIG_ARCH_BCM_5301X),y)
  36 +OBJS           += head-bcm_5301x-mpcore.o
  37 +OBJS           += cache-v7-min.o
  38 +endif
  39 +
  40  ifeq ($(CONFIG_ARCH_SA1100),y)
  41  OBJS           += head-sa1100.o
  42  endif
  43 --- /dev/null
  44 +++ b/arch/arm/boot/compressed/head-bcm_5301x-mpcore.S
  45 @@ -0,0 +1,37 @@
  46 +/*
  47 + *
  48 + * Platform specific tweaks.  This is merged into head.S by the linker.
  49 + *
  50 + */
  51 +
  52 +#include <linux/linkage.h>
  53 +#include <asm/assembler.h>
  54 +#include <asm/cp15.h>
  55 +
  56 +               .section        ".start", "ax"
  57 +
  58 +/*
  59 + * This code section is spliced into the head code by the linker
  60 + */
  61 +
  62 +__plat_uncompress_start:
  63 +
  64 +       @ Preserve r8/r7 i.e. kernel entry values
  65 +       mov     r12, r8
  66 +
  67 +       @ Clear MMU enable and Dcache enable bits
  68 +       mrc     p15, 0, r0, c1, c0, 0           @ Read SCTLR
  69 +       bic     r0, #CR_C|CR_M
  70 +       mcr     p15, 0, r0, c1, c0, 0           @ Write SCTLR
  71 +       nop
  72 +
  73 +       @ Call the cache invalidation routine
  74 +       bl      v7_flush_dcache_all
  75 +       nop
  76 +       mov     r0,#0
  77 +       ldr     r3, =0x19022000                 @ L2 cache controller, control reg
  78 +       str     r0, [r3, #0x100]                @ Disable L2 cache
  79 +       nop
  80 +
  81 +       @ Restore
  82 +       mov     r8, r12
  83 --- a/arch/arm/boot/compressed/cache-v7-min.S
  84 +++ b/arch/arm/boot/compressed/cache-v7-min.S
  85 @@ -12,6 +12,7 @@
  86
  87  #include <linux/linkage.h>
  88  #include <linux/init.h>
  89 +#include <asm/assembler.h>
  90
  91         __INIT
  92
  93 @@ -63,7 +64,7 @@ loop2:
  94   ARM(  orr     r11, r11, r9, lsl r2    )       @ factor index number into r11
  95   THUMB(        lsl     r6, r9, r2              )
  96   THUMB(        orr     r11, r11, r6            )       @ factor index number into r11
  97 -       mcr     p15, 0, r11, c7, c14, 2         @ clean & invalidate by set/way
  98 +       mcr     p15, 0, r11, c7, c6, 2          @ clean & invalidate by set/way
  99         subs    r9, r9, #1                      @ decrement the index
 100         bge     loop2
 101         subs    r4, r4, #1                      @ decrement the way