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finally move buildroot-ng to trunk
[openwrt/openwrt.git] / target / linux / brcm-2.4 / patches / 001-bcm47xx.patch
1 diff -urN linux.old/arch/mips/bcm947xx/bcmsrom.c linux.dev/arch/mips/bcm947xx/bcmsrom.c
2 --- linux.old/arch/mips/bcm947xx/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
3 +++ linux.dev/arch/mips/bcm947xx/bcmsrom.c 2006-10-02 21:19:59.000000000 +0200
4 @@ -0,0 +1,1212 @@
5 +/*
6 + * Misc useful routines to access NIC SROM/OTP .
7 + *
8 + * Copyright 2006, Broadcom Corporation
9 + * All Rights Reserved.
10 + *
11 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15 + * $Id: bcmsrom.c,v 1.1.1.14 2006/04/15 01:28:25 michael Exp $
16 + */
17 +
18 +#include <typedefs.h>
19 +#include <bcmdefs.h>
20 +#include <osl.h>
21 +#include <bcmutils.h>
22 +#include <bcmsrom.h>
23 +#include <bcmdevs.h>
24 +#include <bcmendian.h>
25 +#include <sbpcmcia.h>
26 +#include <pcicfg.h>
27 +#include <sbutils.h>
28 +#include <bcmnvram.h>
29 +
30 +/* debug/trace */
31 +#if defined(WLTEST)
32 +#define BS_ERROR(args) printf args
33 +#else
34 +#define BS_ERROR(args)
35 +#endif /* BCMDBG_ERR || WLTEST */
36 +
37 +#define VARS_MAX 4096 /* should be reduced */
38 +
39 +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
40 +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
41 +
42 +static int initvars_srom_pci(void *sbh, void *curmap, char **vars, uint *count);
43 +static int initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, uint *count);
44 +static int initvars_flash_sb(void *sbh, char **vars, uint *count);
45 +static int srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt, char **vars, uint *count);
46 +static int sprom_cmd_pcmcia(osl_t *osh, uint8 cmd);
47 +static int sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data);
48 +static int sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data);
49 +static int sprom_read_pci(osl_t *osh, uint16 *sprom, uint wordoff, uint16 *buf, uint nwords,
50 + bool check_crc);
51 +
52 +static int initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count);
53 +static int initvars_flash(osl_t *osh, char **vp, uint len, char *devpath);
54 +
55 +/*
56 + * Initialize local vars from the right source for this platform.
57 + * Return 0 on success, nonzero on error.
58 + */
59 +int
60 +srom_var_init(void *sbh, uint bustype, void *curmap, osl_t *osh, char **vars, uint *count)
61 +{
62 + ASSERT(bustype == BUSTYPE(bustype));
63 + if (vars == NULL || count == NULL)
64 + return (0);
65 +
66 + switch (BUSTYPE(bustype)) {
67 + case SB_BUS:
68 + case JTAG_BUS:
69 + return initvars_flash_sb(sbh, vars, count);
70 +
71 + case PCI_BUS:
72 + ASSERT(curmap); /* can not be NULL */
73 + return initvars_srom_pci(sbh, curmap, vars, count);
74 +
75 + case PCMCIA_BUS:
76 + return initvars_cis_pcmcia(sbh, osh, vars, count);
77 +
78 +
79 + default:
80 + ASSERT(0);
81 + }
82 + return (-1);
83 +}
84 +
85 +/* support only 16-bit word read from srom */
86 +int
87 +srom_read(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
88 +{
89 + void *srom;
90 + uint i, off, nw;
91 +
92 + ASSERT(bustype == BUSTYPE(bustype));
93 +
94 + /* check input - 16-bit access only */
95 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
96 + return 1;
97 +
98 + off = byteoff / 2;
99 + nw = nbytes / 2;
100 +
101 + if (BUSTYPE(bustype) == PCI_BUS) {
102 + if (!curmap)
103 + return 1;
104 + srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
105 + if (sprom_read_pci(osh, srom, off, buf, nw, FALSE))
106 + return 1;
107 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
108 + for (i = 0; i < nw; i++) {
109 + if (sprom_read_pcmcia(osh, (uint16)(off + i), (uint16*)(buf + i)))
110 + return 1;
111 + }
112 + } else {
113 + return 1;
114 + }
115 +
116 + return 0;
117 +}
118 +
119 +/* support only 16-bit word write into srom */
120 +int
121 +srom_write(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
122 +{
123 + uint16 *srom;
124 + uint i, nw, crc_range;
125 + uint16 image[SPROM_SIZE];
126 + uint8 crc;
127 + volatile uint32 val32;
128 +
129 + ASSERT(bustype == BUSTYPE(bustype));
130 +
131 + /* check input - 16-bit access only */
132 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
133 + return 1;
134 +
135 + /* Are we writing the whole thing at once? */
136 + if ((byteoff == 0) &&
137 + ((nbytes == SPROM_SIZE) ||
138 + (nbytes == (SPROM_CRC_RANGE * 2)) ||
139 + (nbytes == (SROM4_WORDS * 2)))) {
140 + crc_range = nbytes;
141 + bcopy((void*)buf, (void*)image, nbytes);
142 + nw = nbytes / 2;
143 + } else {
144 + if ((BUSTYPE(bustype) == PCMCIA_BUS) || (BUSTYPE(bustype) == SDIO_BUS))
145 + crc_range = SPROM_SIZE;
146 + else
147 + crc_range = SPROM_CRC_RANGE * 2; /* Tentative */
148 +
149 + nw = crc_range / 2;
150 + /* read first 64 words from srom */
151 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
152 + return 1;
153 + if (image[SROM4_SIGN] == SROM4_SIGNATURE) {
154 + crc_range = SROM4_WORDS;
155 + nw = crc_range / 2;
156 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
157 + return 1;
158 + }
159 + /* make changes */
160 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
161 + }
162 +
163 + /* calculate crc */
164 + htol16_buf(image, crc_range);
165 + crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
166 + ltoh16_buf(image, crc_range);
167 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
168 +
169 + if (BUSTYPE(bustype) == PCI_BUS) {
170 + srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
171 + /* enable writes to the SPROM */
172 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
173 + val32 |= SPROM_WRITEEN;
174 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
175 + bcm_mdelay(WRITE_ENABLE_DELAY);
176 + /* write srom */
177 + for (i = 0; i < nw; i++) {
178 + W_REG(osh, &srom[i], image[i]);
179 + bcm_mdelay(WRITE_WORD_DELAY);
180 + }
181 + /* disable writes to the SPROM */
182 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 &
183 + ~SPROM_WRITEEN);
184 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
185 + /* enable writes to the SPROM */
186 + if (sprom_cmd_pcmcia(osh, SROM_WEN))
187 + return 1;
188 + bcm_mdelay(WRITE_ENABLE_DELAY);
189 + /* write srom */
190 + for (i = 0; i < nw; i++) {
191 + sprom_write_pcmcia(osh, (uint16)(i), image[i]);
192 + bcm_mdelay(WRITE_WORD_DELAY);
193 + }
194 + /* disable writes to the SPROM */
195 + if (sprom_cmd_pcmcia(osh, SROM_WDS))
196 + return 1;
197 + } else {
198 + return 1;
199 + }
200 +
201 + bcm_mdelay(WRITE_ENABLE_DELAY);
202 + return 0;
203 +}
204 +
205 +
206 +static int
207 +srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt, char **vars, uint *count)
208 +{
209 + char eabuf[32];
210 + char *vp, *base;
211 + uint8 *cis, tup, tlen, sromrev = 1;
212 + int i, j;
213 + uint varsize;
214 + bool ag_init = FALSE;
215 + uint32 w32;
216 +
217 + ASSERT(vars);
218 + ASSERT(count);
219 +
220 + base = vp = MALLOC(osh, VARS_MAX);
221 + ASSERT(vp);
222 + if (!vp)
223 + return -2;
224 +
225 + while (ciscnt--) {
226 + cis = *pcis++;
227 + i = 0;
228 + do {
229 + tup = cis[i++];
230 + tlen = cis[i++];
231 + if ((i + tlen) >= CIS_SIZE)
232 + break;
233 +
234 + switch (tup) {
235 + case CISTPL_MANFID:
236 + vp += sprintf(vp, "manfid=%d", (cis[i + 1] << 8) + cis[i]);
237 + vp++;
238 + vp += sprintf(vp, "prodid=%d", (cis[i + 3] << 8) + cis[i + 2]);
239 + vp++;
240 + break;
241 +
242 + case CISTPL_FUNCE:
243 + switch (cis[i]) {
244 + case LAN_NID:
245 + ASSERT(cis[i + 1] == 6);
246 + bcm_ether_ntoa((struct ether_addr *)&cis[i + 2], eabuf);
247 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
248 + vp++;
249 + break;
250 + case 1: /* SDIO Extended Data */
251 + vp += sprintf(vp, "sdmaxblk=%d",
252 + (cis[i + 13] << 8) | cis[i + 12]);
253 + vp++;
254 + break;
255 + }
256 + break;
257 +
258 + case CISTPL_CFTABLE:
259 + vp += sprintf(vp, "regwindowsz=%d", (cis[i + 7] << 8) | cis[i + 6]);
260 + vp++;
261 + break;
262 +
263 + case CISTPL_BRCM_HNBU:
264 + switch (cis[i]) {
265 + case HNBU_SROMREV:
266 + sromrev = cis[i + 1];
267 + break;
268 +
269 + case HNBU_CHIPID:
270 + vp += sprintf(vp, "vendid=%d", (cis[i + 2] << 8) +
271 + cis[i + 1]);
272 + vp++;
273 + vp += sprintf(vp, "devid=%d", (cis[i + 4] << 8) +
274 + cis[i + 3]);
275 + vp++;
276 + if (tlen == 7) {
277 + vp += sprintf(vp, "chiprev=%d",
278 + (cis[i + 6] << 8) + cis[i + 5]);
279 + vp++;
280 + }
281 + break;
282 +
283 + case HNBU_BOARDREV:
284 + vp += sprintf(vp, "boardrev=%d", cis[i + 1]);
285 + vp++;
286 + break;
287 +
288 + case HNBU_AA:
289 + vp += sprintf(vp, "aa2g=%d", cis[i + 1]);
290 + vp++;
291 + break;
292 +
293 + case HNBU_AG:
294 + vp += sprintf(vp, "ag0=%d", cis[i + 1]);
295 + vp++;
296 + ag_init = TRUE;
297 + break;
298 +
299 + case HNBU_CC:
300 + ASSERT(sromrev == 1);
301 + vp += sprintf(vp, "cc=%d", cis[i + 1]);
302 + vp++;
303 + break;
304 +
305 + case HNBU_PAPARMS:
306 + if (tlen == 2) {
307 + ASSERT(sromrev == 1);
308 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 1]);
309 + vp++;
310 + } else if (tlen >= 9) {
311 + if (tlen == 10) {
312 + ASSERT(sromrev == 2);
313 + vp += sprintf(vp, "opo=%d", cis[i + 9]);
314 + vp++;
315 + } else
316 + ASSERT(tlen == 9);
317 +
318 + for (j = 0; j < 3; j++) {
319 + vp += sprintf(vp, "pa0b%d=%d", j,
320 + (cis[i + (j * 2) + 2] << 8) +
321 + cis[i + (j * 2) + 1]);
322 + vp++;
323 + }
324 + vp += sprintf(vp, "pa0itssit=%d", cis[i + 7]);
325 + vp++;
326 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 8]);
327 + vp++;
328 + } else
329 + ASSERT(tlen >= 9);
330 + break;
331 +
332 + case HNBU_OEM:
333 + ASSERT(sromrev == 1);
334 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
335 + cis[i + 1], cis[i + 2],
336 + cis[i + 3], cis[i + 4],
337 + cis[i + 5], cis[i + 6],
338 + cis[i + 7], cis[i + 8]);
339 + vp++;
340 + break;
341 +
342 + case HNBU_BOARDFLAGS:
343 + w32 = (cis[i + 2] << 8) + cis[i + 1];
344 + if (tlen == 5)
345 + w32 |= (cis[i + 4] << 24) + (cis[i + 3] << 16);
346 + vp += sprintf(vp, "boardflags=0x%x", w32);
347 + vp++;
348 + break;
349 +
350 + case HNBU_LEDS:
351 + if (cis[i + 1] != 0xff) {
352 + vp += sprintf(vp, "ledbh0=%d", cis[i + 1]);
353 + vp++;
354 + }
355 + if (cis[i + 2] != 0xff) {
356 + vp += sprintf(vp, "ledbh1=%d", cis[i + 2]);
357 + vp++;
358 + }
359 + if (cis[i + 3] != 0xff) {
360 + vp += sprintf(vp, "ledbh2=%d", cis[i + 3]);
361 + vp++;
362 + }
363 + if (cis[i + 4] != 0xff) {
364 + vp += sprintf(vp, "ledbh3=%d", cis[i + 4]);
365 + vp++;
366 + }
367 + break;
368 +
369 + case HNBU_CCODE:
370 + {
371 + char str[3];
372 + ASSERT(sromrev > 1);
373 + str[0] = cis[i + 1];
374 + str[1] = cis[i + 2];
375 + str[2] = 0;
376 + vp += sprintf(vp, "ccode=%s", str);
377 + vp++;
378 + vp += sprintf(vp, "cctl=0x%x", cis[i + 3]);
379 + vp++;
380 + break;
381 + }
382 +
383 + case HNBU_CCKPO:
384 + ASSERT(sromrev > 2);
385 + vp += sprintf(vp, "cckpo=0x%x",
386 + (cis[i + 2] << 8) | cis[i + 1]);
387 + vp++;
388 + break;
389 +
390 + case HNBU_OFDMPO:
391 + ASSERT(sromrev > 2);
392 + vp += sprintf(vp, "ofdmpo=0x%x",
393 + (cis[i + 4] << 24) |
394 + (cis[i + 3] << 16) |
395 + (cis[i + 2] << 8) |
396 + cis[i + 1]);
397 + vp++;
398 + break;
399 + }
400 + break;
401 +
402 + }
403 + i += tlen;
404 + } while (tup != 0xff);
405 + }
406 +
407 + /* Set the srom version */
408 + vp += sprintf(vp, "sromrev=%d", sromrev);
409 + vp++;
410 +
411 + /* if there is no antenna gain field, set default */
412 + if (ag_init == FALSE) {
413 + ASSERT(sromrev == 1);
414 + vp += sprintf(vp, "ag0=%d", 0xff);
415 + vp++;
416 + }
417 +
418 + /* final nullbyte terminator */
419 + *vp++ = '\0';
420 + varsize = (uint)(vp - base);
421 +
422 + ASSERT((vp - base) < VARS_MAX);
423 +
424 + if (varsize == VARS_MAX) {
425 + *vars = base;
426 + } else {
427 + vp = MALLOC(osh, varsize);
428 + ASSERT(vp);
429 + if (vp)
430 + bcopy(base, vp, varsize);
431 + MFREE(osh, base, VARS_MAX);
432 + *vars = vp;
433 + if (!vp) {
434 + *count = 0;
435 + return -2;
436 + }
437 + }
438 + *count = varsize;
439 +
440 + return (0);
441 +}
442 +
443 +
444 +/* set PCMCIA sprom command register */
445 +static int
446 +sprom_cmd_pcmcia(osl_t *osh, uint8 cmd)
447 +{
448 + uint8 status = 0;
449 + uint wait_cnt = 1000;
450 +
451 + /* write sprom command register */
452 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_CS, &cmd, 1);
453 +
454 + /* wait status */
455 + while (wait_cnt--) {
456 + OSL_PCMCIA_READ_ATTR(osh, SROM_CS, &status, 1);
457 + if (status & SROM_DONE)
458 + return 0;
459 + }
460 +
461 + return 1;
462 +}
463 +
464 +/* read a word from the PCMCIA srom */
465 +static int
466 +sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data)
467 +{
468 + uint8 addr_l, addr_h, data_l, data_h;
469 +
470 + addr_l = (uint8)((addr * 2) & 0xff);
471 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
472 +
473 + /* set address */
474 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
475 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
476 +
477 + /* do read */
478 + if (sprom_cmd_pcmcia(osh, SROM_READ))
479 + return 1;
480 +
481 + /* read data */
482 + data_h = data_l = 0;
483 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAH, &data_h, 1);
484 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAL, &data_l, 1);
485 +
486 + *data = (data_h << 8) | data_l;
487 + return 0;
488 +}
489 +
490 +/* write a word to the PCMCIA srom */
491 +static int
492 +sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data)
493 +{
494 + uint8 addr_l, addr_h, data_l, data_h;
495 +
496 + addr_l = (uint8)((addr * 2) & 0xff);
497 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
498 + data_l = (uint8)(data & 0xff);
499 + data_h = (uint8)((data >> 8) & 0xff);
500 +
501 + /* set address */
502 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
503 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
504 +
505 + /* write data */
506 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAH, &data_h, 1);
507 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAL, &data_l, 1);
508 +
509 + /* do write */
510 + return sprom_cmd_pcmcia(osh, SROM_WRITE);
511 +}
512 +
513 +/*
514 + * Read in and validate sprom.
515 + * Return 0 on success, nonzero on error.
516 + */
517 +static int
518 +sprom_read_pci(osl_t *osh, uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
519 +{
520 + int err = 0;
521 + uint i;
522 +
523 + /* read the sprom */
524 + for (i = 0; i < nwords; i++)
525 + buf[i] = R_REG(osh, &sprom[wordoff + i]);
526 +
527 + if (check_crc) {
528 + /* fixup the endianness so crc8 will pass */
529 + htol16_buf(buf, nwords * 2);
530 + if (hndcrc8((uint8*)buf, nwords * 2, CRC8_INIT_VALUE) != CRC8_GOOD_VALUE)
531 + err = 1;
532 + /* now correct the endianness of the byte array */
533 + ltoh16_buf(buf, nwords * 2);
534 + }
535 +
536 + return err;
537 +}
538 +
539 +/*
540 +* Create variable table from memory.
541 +* Return 0 on success, nonzero on error.
542 +*/
543 +static int
544 +initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count)
545 +{
546 + int c = (int)(end - start);
547 +
548 + /* do it only when there is more than just the null string */
549 + if (c > 1) {
550 + char *vp = MALLOC(osh, c);
551 + ASSERT(vp);
552 + if (!vp)
553 + return BCME_NOMEM;
554 + bcopy(start, vp, c);
555 + *vars = vp;
556 + *count = c;
557 + }
558 + else {
559 + *vars = NULL;
560 + *count = 0;
561 + }
562 +
563 + return 0;
564 +}
565 +
566 +/*
567 + * Find variables with <devpath> from flash. 'base' points to the beginning
568 + * of the table upon enter and to the end of the table upon exit when success.
569 + * Return 0 on success, nonzero on error.
570 + */
571 +static int
572 +initvars_flash(osl_t *osh, char **base, uint len, char *devpath)
573 +{
574 + char *vp = *base;
575 + char *flash;
576 + int err;
577 + char *s;
578 + uint l, dl, copy_len;
579 +
580 + /* allocate memory and read in flash */
581 + if (!(flash = MALLOC(osh, NVRAM_SPACE)))
582 + return BCME_NOMEM;
583 + if ((err = nvram_getall(flash, NVRAM_SPACE)))
584 + goto exit;
585 +
586 + /* grab vars with the <devpath> prefix in name */
587 + dl = strlen(devpath);
588 + for (s = flash; s && *s; s += l + 1) {
589 + l = strlen(s);
590 +
591 + /* skip non-matching variable */
592 + if (strncmp(s, devpath, dl))
593 + continue;
594 +
595 + /* is there enough room to copy? */
596 + copy_len = l - dl + 1;
597 + if (len < copy_len) {
598 + err = BCME_BUFTOOSHORT;
599 + goto exit;
600 + }
601 +
602 + /* no prefix, just the name=value */
603 + strcpy(vp, &s[dl]);
604 + vp += copy_len;
605 + len -= copy_len;
606 + }
607 +
608 + /* add null string as terminator */
609 + if (len < 1) {
610 + err = BCME_BUFTOOSHORT;
611 + goto exit;
612 + }
613 + *vp++ = '\0';
614 +
615 + *base = vp;
616 +
617 +exit: MFREE(osh, flash, NVRAM_SPACE);
618 + return err;
619 +}
620 +
621 +/*
622 + * Initialize nonvolatile variable table from flash.
623 + * Return 0 on success, nonzero on error.
624 + */
625 +static int
626 +initvars_flash_sb(void *sbh, char **vars, uint *count)
627 +{
628 + osl_t *osh = sb_osh(sbh);
629 + char devpath[SB_DEVPATH_BUFSZ];
630 + char *vp, *base;
631 + int err;
632 +
633 + ASSERT(vars);
634 + ASSERT(count);
635 +
636 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
637 + return err;
638 +
639 + base = vp = MALLOC(osh, VARS_MAX);
640 + ASSERT(vp);
641 + if (!vp)
642 + return BCME_NOMEM;
643 +
644 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
645 + goto err;
646 +
647 + err = initvars_table(osh, base, vp, vars, count);
648 +
649 +err: MFREE(osh, base, VARS_MAX);
650 + return err;
651 +}
652 +
653 +#ifdef WLTEST
654 +char mfgsromvars[256];
655 +char *defaultsromvars = "il0macaddr=00:11:22:33:44:51\0"
656 + "et0macaddr=00:11:22:33:44:52\0"
657 + "et1macaddr=00:11:22:33:44:53\0"
658 + "boardtype=0xffff\0"
659 + "boardrev=0x10\0"
660 + "boardflags=8\0"
661 + "sromrev=2\0"
662 + "aa2g=3";
663 +#define MFGSROM_DEFVARSLEN 147 /* default srom len */
664 +#endif /* WL_TEST */
665 +
666 +/*
667 + * Initialize nonvolatile variable table from sprom.
668 + * Return 0 on success, nonzero on error.
669 + */
670 +static int
671 +initvars_srom_pci(void *sbh, void *curmap, char **vars, uint *count)
672 +{
673 + uint16 w, *b;
674 + uint8 sromrev = 0;
675 + struct ether_addr ea;
676 + char eabuf[32];
677 + uint32 w32;
678 + int woff, i;
679 + char *vp, *base;
680 + osl_t *osh = sb_osh(sbh);
681 + bool flash = FALSE;
682 + char name[SB_DEVPATH_BUFSZ+16], *value;
683 + char devpath[SB_DEVPATH_BUFSZ];
684 + int err;
685 +
686 + /*
687 + * Apply CRC over SROM content regardless SROM is present or not,
688 + * and use variable <devpath>sromrev's existance in flash to decide
689 + * if we should return an error when CRC fails or read SROM variables
690 + * from flash.
691 + */
692 + b = MALLOC(osh, SROM_MAX);
693 + ASSERT(b);
694 + if (!b)
695 + return -2;
696 +
697 + err = sprom_read_pci(osh, (void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b,
698 + 64, TRUE);
699 + if (err == 0) {
700 + /* srom is good and is rev < 4 */
701 + /* top word of sprom contains version and crc8 */
702 + sromrev = b[63] & 0xff;
703 + /* bcm4401 sroms misprogrammed */
704 + if (sromrev == 0x10)
705 + sromrev = 1;
706 + } else if (b[SROM4_SIGN] == SROM4_SIGNATURE) {
707 + /* If sromrev >= 4, read more */
708 + err = sprom_read_pci(osh, (void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b,
709 + SROM4_WORDS, TRUE);
710 + sromrev = b[SROM4_WORDS - 1] & 0xff;
711 + }
712 +
713 + if (err) {
714 +#ifdef WLTEST
715 + BS_ERROR(("SROM Crc Error, so see if we could use a default\n"));
716 + w32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
717 + if (w32 & SPROM_OTPIN_USE) {
718 + BS_ERROR(("srom crc failed with OTP, use default vars....\n"));
719 + vp = base = mfgsromvars;
720 + if (sb_chip(sbh) == BCM4311_CHIP_ID) {
721 + BS_ERROR(("setting the devid to be 4311\n"));
722 + vp += sprintf(vp, "devid=0x4311");
723 + vp++;
724 + }
725 + bcopy(defaultsromvars, vp, MFGSROM_DEFVARSLEN);
726 + vp += MFGSROM_DEFVARSLEN;
727 + goto varsdone;
728 + } else {
729 + BS_ERROR(("srom crc failed with SPROM....\n"));
730 +#endif /* WLTEST */
731 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
732 + return err;
733 + sprintf(name, "%ssromrev", devpath);
734 + if (!(value = getvar(NULL, name)))
735 + return (-1);
736 + sromrev = (uint8)bcm_strtoul(value, NULL, 0);
737 + flash = TRUE;
738 +#ifdef WLTEST
739 + }
740 +#endif /* WLTEST */
741 + }
742 +
743 + /* srom version check */
744 + if (sromrev > 4)
745 + return (-2);
746 +
747 + ASSERT(vars);
748 + ASSERT(count);
749 +
750 + base = vp = MALLOC(osh, VARS_MAX);
751 + ASSERT(vp);
752 + if (!vp)
753 + return -2;
754 +
755 + /* read variables from flash */
756 + if (flash) {
757 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
758 + goto err;
759 + goto varsdone;
760 + }
761 +
762 + vp += sprintf(vp, "sromrev=%d", sromrev);
763 + vp++;
764 +
765 + if (sromrev >= 4) {
766 + uint path, pathbase;
767 + const uint pathbases[MAX_PATH] = {SROM4_PATH0, SROM4_PATH1,
768 + SROM4_PATH2, SROM4_PATH3};
769 +
770 + vp += sprintf(vp, "boardrev=%d", b[SROM4_BREV]);
771 + vp++;
772 +
773 + vp += sprintf(vp, "boardflags=%d", (b[SROM4_BFL1] << 16) | b[SROM4_BFL0]);
774 + vp++;
775 +
776 + vp += sprintf(vp, "boardflags2=%d", (b[SROM4_BFL3] << 16) | b[SROM4_BFL2]);
777 + vp++;
778 +
779 + /* The macaddr */
780 + ea.octet[0] = (b[SROM4_MACHI] >> 8) & 0xff;
781 + ea.octet[1] = b[SROM4_MACHI] & 0xff;
782 + ea.octet[2] = (b[SROM4_MACMID] >> 8) & 0xff;
783 + ea.octet[3] = b[SROM4_MACMID] & 0xff;
784 + ea.octet[4] = (b[SROM4_MACLO] >> 8) & 0xff;
785 + ea.octet[5] = b[SROM4_MACLO] & 0xff;
786 + bcm_ether_ntoa(&ea, eabuf);
787 + vp += sprintf(vp, "macaddr=%s", eabuf);
788 + vp++;
789 +
790 + w = b[SROM4_CCODE];
791 + if (w == 0)
792 + vp += sprintf(vp, "ccode=");
793 + else
794 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
795 + vp++;
796 + vp += sprintf(vp, "regrev=%d", b[SROM4_REGREV]);
797 + vp++;
798 +
799 + w = b[SROM4_LEDBH10];
800 + if ((w != 0) && (w != 0xffff)) {
801 + /* ledbh0 */
802 + vp += sprintf(vp, "ledbh0=%d", (w & 0xff));
803 + vp++;
804 +
805 + /* ledbh1 */
806 + vp += sprintf(vp, "ledbh1=%d", (w >> 8) & 0xff);
807 + vp++;
808 + }
809 + w = b[SROM4_LEDBH32];
810 + if ((w != 0) && (w != 0xffff)) {
811 + /* ledbh2 */
812 + vp += sprintf(vp, "ledbh2=%d", w & 0xff);
813 + vp++;
814 +
815 + /* ledbh3 */
816 + vp += sprintf(vp, "ledbh3=%d", (w >> 8) & 0xff);
817 + vp++;
818 + }
819 + /* LED Powersave duty cycle (oncount >> 24) (offcount >> 8) */
820 + w = b[SROM4_LEDDC];
821 + w32 = ((uint32)((unsigned char)(w >> 8) & 0xff) << 24) | /* oncount */
822 + ((uint32)((unsigned char)(w & 0xff)) << 8); /* offcount */
823 + vp += sprintf(vp, "leddc=%d", w32);
824 + vp++;
825 +
826 + w = b[SROM4_AA];
827 + vp += sprintf(vp, "aa2g=%d", w & SROM4_AA2G_MASK);
828 + vp++;
829 + vp += sprintf(vp, "aa5g=%d", w >> SROM4_AA5G_SHIFT);
830 + vp++;
831 +
832 + w = b[SROM4_AG10];
833 + vp += sprintf(vp, "ag0=%d", w & 0xff);
834 + vp++;
835 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
836 + vp++;
837 + w = b[SROM4_AG32];
838 + vp += sprintf(vp, "ag2=%d", w & 0xff);
839 + vp++;
840 + vp += sprintf(vp, "ag3=%d", (w >> 8) & 0xff);
841 + vp++;
842 +
843 + /* Fixed power indices when power control is disabled */
844 + for (i = 0; i < 2; i++) {
845 + w = b[SROM4_TXPID2G + i];
846 + vp += sprintf(vp, "txpid2ga%d=%d", 2 * i, w & 0xff);
847 + vp++;
848 + vp += sprintf(vp, "txpid2ga%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
849 + vp++;
850 + w = b[SROM4_TXPID5G + i];
851 + vp += sprintf(vp, "txpid5ga%d=%d", 2 * i, w & 0xff);
852 + vp++;
853 + vp += sprintf(vp, "txpid5ga%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
854 + vp++;
855 + w = b[SROM4_TXPID5GL + i];
856 + vp += sprintf(vp, "txpid5gla%d=%d", 2 * i, w & 0xff);
857 + vp++;
858 + vp += sprintf(vp, "txpid5gla%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
859 + vp++;
860 + w = b[SROM4_TXPID5GH + i];
861 + vp += sprintf(vp, "txpid5gha%d=%d", 2 * i, w & 0xff);
862 + vp++;
863 + vp += sprintf(vp, "txpid5gha%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
864 + vp++;
865 + }
866 +
867 + /* Per path variables */
868 + for (path = 0; path < MAX_PATH; path++) {
869 + pathbase = pathbases[path];
870 + w = b[pathbase + SROM4_2G_ITT_MAXP];
871 + vp += sprintf(vp, "itt2ga%d=%d", path, w >> B2G_ITT_SHIFT);
872 + vp++;
873 + vp += sprintf(vp, "maxp2ga%d=%d", path, w & B2G_MAXP_MASK);
874 + vp++;
875 +
876 + for (i = 0; i < 4; i++) {
877 + vp += sprintf(vp, "pa2gw%da%d=%d", i, path,
878 + b[pathbase + SROM4_2G_PA + i]);
879 + vp++;
880 + }
881 +
882 + w = b[pathbase + SROM4_5G_ITT_MAXP];
883 + vp += sprintf(vp, "itt5ga%d=%d", path, w >> B5G_ITT_SHIFT);
884 + vp++;
885 + vp += sprintf(vp, "maxp5ga%d=%d", path, w & B5G_MAXP_MASK);
886 + vp++;
887 +
888 + w = b[pathbase + SROM4_5GLH_MAXP];
889 + vp += sprintf(vp, "maxp5lga%d=%d", path, w >> B5GL_MAXP_SHIFT);
890 + vp++;
891 + vp += sprintf(vp, "maxp5gha%d=%d", path, w & B5GH_MAXP_MASK);
892 + vp++;
893 +
894 + for (i = 0; i < 4; i++) {
895 + vp += sprintf(vp, "pa5gw%da%d=%d", i, path,
896 + b[pathbase + SROM4_5G_PA + i]);
897 + vp++;
898 + vp += sprintf(vp, "pa5glw%da%d=%d", i, path,
899 + b[pathbase + SROM4_5GL_PA + i]);
900 + vp++;
901 + vp += sprintf(vp, "pa5hgw%da%d=%d", i, path,
902 + b[pathbase + SROM4_5GH_PA + i]);
903 + vp++;
904 + }
905 + }
906 +
907 + vp += sprintf(vp, "cck2gpo=%d", b[SROM4_2G_CCKPO]);
908 + vp++;
909 +
910 + w32 = ((uint32)b[SROM4_2G_OFDMPO + 1] << 16) | b[SROM4_2G_OFDMPO];
911 + vp += sprintf(vp, "ofdm2gpo=%d", w32);
912 + vp++;
913 +
914 + w32 = ((uint32)b[SROM4_5G_OFDMPO + 1] << 16) | b[SROM4_5G_OFDMPO];
915 + vp += sprintf(vp, "ofdm5gpo=%d", w32);
916 + vp++;
917 +
918 + w32 = ((uint32)b[SROM4_5GL_OFDMPO + 1] << 16) | b[SROM4_5GL_OFDMPO];
919 + vp += sprintf(vp, "ofdm5glpo=%d", w32);
920 + vp++;
921 +
922 + w32 = ((uint32)b[SROM4_5GH_OFDMPO + 1] << 16) | b[SROM4_5GH_OFDMPO];
923 + vp += sprintf(vp, "ofdm5ghpo=%d", w32);
924 + vp++;
925 +
926 + for (i = 0; i < 8; i++) {
927 + vp += sprintf(vp, "mcs2gpo%d=%d", i, b[SROM4_2G_MCSPO]);
928 + vp++;
929 + vp += sprintf(vp, "mcs5gpo%d=%d", i, b[SROM4_5G_MCSPO]);
930 + vp++;
931 + vp += sprintf(vp, "mcs5glpo%d=%d", i, b[SROM4_5GL_MCSPO]);
932 + vp++;
933 + vp += sprintf(vp, "mcs5ghpo%d=%d", i, b[SROM4_5GH_MCSPO]);
934 + vp++;
935 + }
936 +
937 + vp += sprintf(vp, "ccdpo%d=%d", i, b[SROM4_CCDPO]);
938 + vp++;
939 + vp += sprintf(vp, "stbcpo%d=%d", i, b[SROM4_STBCPO]);
940 + vp++;
941 + vp += sprintf(vp, "bw40po%d=%d", i, b[SROM4_BW40PO]);
942 + vp++;
943 + vp += sprintf(vp, "bwduppo%d=%d", i, b[SROM4_BWDUPPO]);
944 + vp++;
945 +
946 + goto done;
947 + }
948 + if (sromrev >= 3) {
949 + /* New section takes over the 3th hardware function space */
950 +
951 + /* Words 22+23 are 11a (mid) ofdm power offsets */
952 + w32 = ((uint32)b[23] << 16) | b[22];
953 + vp += sprintf(vp, "ofdmapo=%d", w32);
954 + vp++;
955 +
956 + /* Words 24+25 are 11a (low) ofdm power offsets */
957 + w32 = ((uint32)b[25] << 16) | b[24];
958 + vp += sprintf(vp, "ofdmalpo=%d", w32);
959 + vp++;
960 +
961 + /* Words 26+27 are 11a (high) ofdm power offsets */
962 + w32 = ((uint32)b[27] << 16) | b[26];
963 + vp += sprintf(vp, "ofdmahpo=%d", w32);
964 + vp++;
965 +
966 + /* LED Powersave duty cycle (oncount >> 24) (offcount >> 8) */
967 + w32 = ((uint32)((unsigned char)(b[21] >> 8) & 0xff) << 24) | /* oncount */
968 + ((uint32)((unsigned char)(b[21] & 0xff)) << 8); /* offcount */
969 + vp += sprintf(vp, "leddc=%d", w32);
970 +
971 + vp++;
972 + }
973 +
974 + if (sromrev >= 2) {
975 + /* New section takes over the 4th hardware function space */
976 +
977 + /* Word 29 is max power 11a high/low */
978 + w = b[29];
979 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
980 + vp++;
981 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
982 + vp++;
983 +
984 + /* Words 30-32 set the 11alow pa settings,
985 + * 33-35 are the 11ahigh ones.
986 + */
987 + for (i = 0; i < 3; i++) {
988 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
989 + vp++;
990 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
991 + vp++;
992 + }
993 + w = b[59];
994 + if (w == 0)
995 + vp += sprintf(vp, "ccode=");
996 + else
997 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
998 + vp++;
999 +
1000 + }
1001 +
1002 + /* parameter section of sprom starts at byte offset 72 */
1003 + woff = 72/2;
1004 +
1005 + /* first 6 bytes are il0macaddr */
1006 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1007 + ea.octet[1] = b[woff] & 0xff;
1008 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1009 + ea.octet[3] = b[woff+1] & 0xff;
1010 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1011 + ea.octet[5] = b[woff+2] & 0xff;
1012 + woff += 3;
1013 + bcm_ether_ntoa(&ea, eabuf);
1014 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
1015 + vp++;
1016 +
1017 + /* next 6 bytes are et0macaddr */
1018 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1019 + ea.octet[1] = b[woff] & 0xff;
1020 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1021 + ea.octet[3] = b[woff+1] & 0xff;
1022 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1023 + ea.octet[5] = b[woff+2] & 0xff;
1024 + woff += 3;
1025 + bcm_ether_ntoa(&ea, eabuf);
1026 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
1027 + vp++;
1028 +
1029 + /* next 6 bytes are et1macaddr */
1030 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1031 + ea.octet[1] = b[woff] & 0xff;
1032 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1033 + ea.octet[3] = b[woff+1] & 0xff;
1034 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1035 + ea.octet[5] = b[woff+2] & 0xff;
1036 + woff += 3;
1037 + bcm_ether_ntoa(&ea, eabuf);
1038 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
1039 + vp++;
1040 +
1041 + /*
1042 + * Enet phy settings one or two singles or a dual
1043 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
1044 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
1045 + * Bit 14 : Mdio for enet0
1046 + * Bit 15 : Mdio for enet1
1047 + */
1048 + w = b[woff];
1049 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
1050 + vp++;
1051 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
1052 + vp++;
1053 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
1054 + vp++;
1055 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
1056 + vp++;
1057 +
1058 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
1059 + w = b[46];
1060 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
1061 + vp++;
1062 +
1063 + if (sromrev > 1)
1064 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
1065 + else
1066 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
1067 + vp++;
1068 +
1069 + vp += sprintf(vp, "aa2g=%d", (w >> 12) & 0x3);
1070 + vp++;
1071 +
1072 + vp += sprintf(vp, "aa5g=%d", (w >> 14) & 0x3);
1073 + vp++;
1074 +
1075 + /* Words 47-49 set the (wl) pa settings */
1076 + woff = 47;
1077 +
1078 + for (i = 0; i < 3; i++) {
1079 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
1080 + vp++;
1081 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
1082 + vp++;
1083 + }
1084 +
1085 + /*
1086 + * Words 50-51 set the customer-configured wl led behavior.
1087 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
1088 + * LED behavior values defined in wlioctl.h .
1089 + */
1090 + w = b[50];
1091 + if ((w != 0) && (w != 0xffff)) {
1092 + /* ledbh0 */
1093 + vp += sprintf(vp, "ledbh0=%d", (w & 0xff));
1094 + vp++;
1095 +
1096 + /* ledbh1 */
1097 + vp += sprintf(vp, "ledbh1=%d", (w >> 8) & 0xff);
1098 + vp++;
1099 + }
1100 + w = b[51];
1101 + if ((w != 0) && (w != 0xffff)) {
1102 + /* ledbh2 */
1103 + vp += sprintf(vp, "ledbh2=%d", w & 0xff);
1104 + vp++;
1105 +
1106 + /* ledbh */
1107 + vp += sprintf(vp, "ledbh3=%d", (w >> 8) & 0xff);
1108 + vp++;
1109 + }
1110 +
1111 + /* Word 52 is max power 0/1 */
1112 + w = b[52];
1113 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
1114 + vp++;
1115 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
1116 + vp++;
1117 +
1118 + /* Word 56 is idle tssi target 0/1 */
1119 + w = b[56];
1120 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
1121 + vp++;
1122 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
1123 + vp++;
1124 +
1125 + /* Word 57 is boardflags, if not programmed make it zero */
1126 + w32 = (uint32)b[57];
1127 + if (w32 == 0xffff) w32 = 0;
1128 + if (sromrev > 1) {
1129 + /* Word 28 is the high bits of boardflags */
1130 + w32 |= (uint32)b[28] << 16;
1131 + }
1132 + vp += sprintf(vp, "boardflags=%d", w32);
1133 + vp++;
1134 +
1135 + /* Word 58 is antenna gain 0/1 */
1136 + w = b[58];
1137 + vp += sprintf(vp, "ag0=%d", w & 0xff);
1138 + vp++;
1139 +
1140 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
1141 + vp++;
1142 +
1143 + if (sromrev == 1) {
1144 + /* set the oem string */
1145 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
1146 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
1147 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
1148 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
1149 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
1150 + vp++;
1151 + } else if (sromrev == 2) {
1152 + /* Word 60 OFDM tx power offset from CCK level */
1153 + /* OFDM Power Offset - opo */
1154 + vp += sprintf(vp, "opo=%d", b[60] & 0xff);
1155 + vp++;
1156 + } else {
1157 + /* Word 60: cck power offsets */
1158 + vp += sprintf(vp, "cckpo=%d", b[60]);
1159 + vp++;
1160 +
1161 + /* Words 61+62: 11g ofdm power offsets */
1162 + w32 = ((uint32)b[62] << 16) | b[61];
1163 + vp += sprintf(vp, "ofdmgpo=%d", w32);
1164 + vp++;
1165 + }
1166 +
1167 + /* final nullbyte terminator */
1168 +done: *vp++ = '\0';
1169 +
1170 + ASSERT((vp - base) <= VARS_MAX);
1171 +
1172 +varsdone:
1173 + err = initvars_table(osh, base, vp, vars, count);
1174 +
1175 +err:
1176 +#ifdef WLTEST
1177 + if (base != mfgsromvars)
1178 +#endif
1179 + MFREE(osh, base, VARS_MAX);
1180 + MFREE(osh, b, SROM_MAX);
1181 + return err;
1182 +}
1183 +
1184 +/*
1185 + * Read the cis and call parsecis to initialize the vars.
1186 + * Return 0 on success, nonzero on error.
1187 + */
1188 +static int
1189 +initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, uint *count)
1190 +{
1191 + uint8 *cis = NULL;
1192 + int rc;
1193 + uint data_sz;
1194 +
1195 + data_sz = (sb_pcmciarev(sbh) == 1) ? (SPROM_SIZE * 2) : CIS_SIZE;
1196 +
1197 + if ((cis = MALLOC(osh, data_sz)) == NULL)
1198 + return (-2);
1199 +
1200 + if (sb_pcmciarev(sbh) == 1) {
1201 + if (srom_read(PCMCIA_BUS, (void *)NULL, osh, 0, data_sz, (uint16 *)cis)) {
1202 + MFREE(osh, cis, data_sz);
1203 + return (-1);
1204 + }
1205 + /* fix up endianess for 16-bit data vs 8-bit parsing */
1206 + ltoh16_buf((uint16 *)cis, data_sz);
1207 + } else
1208 + OSL_PCMCIA_READ_ATTR(osh, 0, cis, data_sz);
1209 +
1210 + rc = srom_parsecis(osh, &cis, 1, vars, count);
1211 +
1212 + MFREE(osh, cis, data_sz);
1213 +
1214 + return (rc);
1215 +}
1216 +
1217 diff -urN linux.old/arch/mips/bcm947xx/bcmutils.c linux.dev/arch/mips/bcm947xx/bcmutils.c
1218 --- linux.old/arch/mips/bcm947xx/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
1219 +++ linux.dev/arch/mips/bcm947xx/bcmutils.c 2006-10-02 21:19:59.000000000 +0200
1220 @@ -0,0 +1,247 @@
1221 +/*
1222 + * Misc useful OS-independent routines.
1223 + *
1224 + * Copyright 2006, Broadcom Corporation
1225 + * All Rights Reserved.
1226 + *
1227 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1228 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1229 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1230 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1231 + * $Id: bcmutils.c,v 1.1.1.12 2006/02/27 03:43:16 honor Exp $
1232 + */
1233 +
1234 +#include <typedefs.h>
1235 +#include <bcmdefs.h>
1236 +#include <stdarg.h>
1237 +#include <bcmutils.h>
1238 +#include <osl.h>
1239 +#include <sbutils.h>
1240 +#include <bcmnvram.h>
1241 +#include <bcmendian.h>
1242 +#include <bcmdevs.h>
1243 +
1244 +unsigned char bcm_ctype[] = {
1245 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
1246 + _BCM_C, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C,
1247 + _BCM_C, /* 8-15 */
1248 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
1249 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
1250 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
1251 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
1252 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
1253 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
1254 + _BCM_P, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X,
1255 + _BCM_U|_BCM_X, _BCM_U, /* 64-71 */
1256 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
1257 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
1258 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
1259 + _BCM_P, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X,
1260 + _BCM_L|_BCM_X, _BCM_L, /* 96-103 */
1261 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
1262 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
1263 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
1264 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 128-143 */
1265 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 144-159 */
1266 + _BCM_S|_BCM_SP, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
1267 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, /* 160-175 */
1268 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
1269 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, /* 176-191 */
1270 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U,
1271 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, /* 192-207 */
1272 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_P, _BCM_U, _BCM_U, _BCM_U,
1273 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_L, /* 208-223 */
1274 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L,
1275 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, /* 224-239 */
1276 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_P, _BCM_L, _BCM_L, _BCM_L,
1277 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L /* 240-255 */
1278 +};
1279 +
1280 +
1281 +ulong
1282 +bcm_strtoul(char *cp, char **endp, uint base)
1283 +{
1284 + ulong result, value;
1285 + bool minus;
1286 +
1287 + minus = FALSE;
1288 +
1289 + while (bcm_isspace(*cp))
1290 + cp++;
1291 +
1292 + if (cp[0] == '+')
1293 + cp++;
1294 + else if (cp[0] == '-') {
1295 + minus = TRUE;
1296 + cp++;
1297 + }
1298 +
1299 + if (base == 0) {
1300 + if (cp[0] == '0') {
1301 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
1302 + base = 16;
1303 + cp = &cp[2];
1304 + } else {
1305 + base = 8;
1306 + cp = &cp[1];
1307 + }
1308 + } else
1309 + base = 10;
1310 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
1311 + cp = &cp[2];
1312 + }
1313 +
1314 + result = 0;
1315 +
1316 + while (bcm_isxdigit(*cp) &&
1317 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
1318 + result = result*base + value;
1319 + cp++;
1320 + }
1321 +
1322 + if (minus)
1323 + result = (ulong)(result * -1);
1324 +
1325 + if (endp)
1326 + *endp = (char *)cp;
1327 +
1328 + return (result);
1329 +}
1330 +
1331 +uchar
1332 +bcm_toupper(uchar c)
1333 +{
1334 + if (bcm_islower(c))
1335 + c -= 'a'-'A';
1336 + return (c);
1337 +}
1338 +
1339 +char*
1340 +bcm_ether_ntoa(struct ether_addr *ea, char *buf)
1341 +{
1342 + sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x",
1343 + ea->octet[0]&0xff, ea->octet[1]&0xff, ea->octet[2]&0xff,
1344 + ea->octet[3]&0xff, ea->octet[4]&0xff, ea->octet[5]&0xff);
1345 + return (buf);
1346 +}
1347 +
1348 +
1349 +/*
1350 + * Search the name=value vars for a specific one and return its value.
1351 + * Returns NULL if not found.
1352 + */
1353 +char*
1354 +getvar(char *vars, char *name)
1355 +{
1356 + char *s;
1357 + int len;
1358 +
1359 + len = strlen(name);
1360 +
1361 + /* first look in vars[] */
1362 + for (s = vars; s && *s;) {
1363 + /* CSTYLED */
1364 + if ((memcmp(s, name, len) == 0) && (s[len] == '='))
1365 + return (&s[len+1]);
1366 +
1367 + while (*s++)
1368 + ;
1369 + }
1370 +
1371 + /* then query nvram */
1372 + return (nvram_get(name));
1373 +}
1374 +
1375 +/*
1376 + * Search the vars for a specific one and return its value as
1377 + * an integer. Returns 0 if not found.
1378 + */
1379 +int
1380 +getintvar(char *vars, char *name)
1381 +{
1382 + char *val;
1383 +
1384 + if ((val = getvar(vars, name)) == NULL)
1385 + return (0);
1386 +
1387 + return (bcm_strtoul(val, NULL, 0));
1388 +}
1389 +
1390 +
1391 +/*******************************************************************************
1392 + * crc8
1393 + *
1394 + * Computes a crc8 over the input data using the polynomial:
1395 + *
1396 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
1397 + *
1398 + * The caller provides the initial value (either CRC8_INIT_VALUE
1399 + * or the previous returned value) to allow for processing of
1400 + * discontiguous blocks of data. When generating the CRC the
1401 + * caller is responsible for complementing the final return value
1402 + * and inserting it into the byte stream. When checking, a final
1403 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
1404 + *
1405 + * Reference: Dallas Semiconductor Application Note 27
1406 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
1407 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
1408 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
1409 + *
1410 + * ****************************************************************************
1411 + */
1412 +
1413 +static uint8 crc8_table[256] = {
1414 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
1415 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
1416 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
1417 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
1418 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
1419 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
1420 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
1421 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
1422 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
1423 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
1424 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
1425 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
1426 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
1427 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
1428 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
1429 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
1430 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
1431 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
1432 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
1433 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
1434 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
1435 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
1436 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
1437 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
1438 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
1439 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
1440 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
1441 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
1442 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
1443 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
1444 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
1445 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
1446 +};
1447 +
1448 +#define CRC_INNER_LOOP(n, c, x) \
1449 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
1450 +
1451 +uint8
1452 +hndcrc8(
1453 + uint8 *pdata, /* pointer to array of data to process */
1454 + uint nbytes, /* number of input data bytes to process */
1455 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
1456 +)
1457 +{
1458 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
1459 + * to avoid the undefined and unnecessary (uint8 >> 8) operation.
1460 + */
1461 + while (nbytes-- > 0)
1462 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
1463 +
1464 + return crc;
1465 +}
1466 +
1467 +
1468 diff -urN linux.old/arch/mips/bcm947xx/cfe_env.c linux.dev/arch/mips/bcm947xx/cfe_env.c
1469 --- linux.old/arch/mips/bcm947xx/cfe_env.c 1970-01-01 01:00:00.000000000 +0100
1470 +++ linux.dev/arch/mips/bcm947xx/cfe_env.c 2006-10-02 21:19:59.000000000 +0200
1471 @@ -0,0 +1,234 @@
1472 +/*
1473 + * NVRAM variable manipulation (Linux kernel half)
1474 + *
1475 + * Copyright 2001-2003, Broadcom Corporation
1476 + * All Rights Reserved.
1477 + *
1478 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1479 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1480 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1481 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1482 + *
1483 + * $Id$
1484 + */
1485 +
1486 +#include <linux/config.h>
1487 +#include <linux/init.h>
1488 +#include <linux/module.h>
1489 +#include <linux/kernel.h>
1490 +#include <linux/string.h>
1491 +#include <asm/io.h>
1492 +#include <asm/uaccess.h>
1493 +
1494 +#include <typedefs.h>
1495 +#include <osl.h>
1496 +#include <bcmendian.h>
1497 +#include <bcmutils.h>
1498 +
1499 +#define NVRAM_SIZE (0x1ff0)
1500 +static char _nvdata[NVRAM_SIZE] __initdata;
1501 +static char _valuestr[256] __initdata;
1502 +
1503 +/*
1504 + * TLV types. These codes are used in the "type-length-value"
1505 + * encoding of the items stored in the NVRAM device (flash or EEPROM)
1506 + *
1507 + * The layout of the flash/nvram is as follows:
1508 + *
1509 + * <type> <length> <data ...> <type> <length> <data ...> <type_end>
1510 + *
1511 + * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
1512 + * The "length" field marks the length of the data section, not
1513 + * including the type and length fields.
1514 + *
1515 + * Environment variables are stored as follows:
1516 + *
1517 + * <type_env> <length> <flags> <name> = <value>
1518 + *
1519 + * If bit 0 (low bit) is set, the length is an 8-bit value.
1520 + * If bit 0 (low bit) is clear, the length is a 16-bit value
1521 + *
1522 + * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
1523 + * indicates the size of the length field.
1524 + *
1525 + * Flags are from the constants below:
1526 + *
1527 + */
1528 +#define ENV_LENGTH_16BITS 0x00 /* for low bit */
1529 +#define ENV_LENGTH_8BITS 0x01
1530 +
1531 +#define ENV_TYPE_USER 0x80
1532 +
1533 +#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
1534 +#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
1535 +
1536 +/*
1537 + * The actual TLV types we support
1538 + */
1539 +
1540 +#define ENV_TLV_TYPE_END 0x00
1541 +#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
1542 +
1543 +/*
1544 + * Environment variable flags
1545 + */
1546 +
1547 +#define ENV_FLG_NORMAL 0x00 /* normal read/write */
1548 +#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
1549 +#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
1550 +
1551 +#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
1552 +#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
1553 +
1554 +
1555 +/* *********************************************************************
1556 + * _nvram_read(buffer,offset,length)
1557 + *
1558 + * Read data from the NVRAM device
1559 + *
1560 + * Input parameters:
1561 + * buffer - destination buffer
1562 + * offset - offset of data to read
1563 + * length - number of bytes to read
1564 + *
1565 + * Return value:
1566 + * number of bytes read, or <0 if error occured
1567 + ********************************************************************* */
1568 +static int
1569 +_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
1570 +{
1571 + int i;
1572 + if (offset > NVRAM_SIZE)
1573 + return -1;
1574 +
1575 + for ( i = 0; i < length; i++) {
1576 + buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
1577 + }
1578 + return length;
1579 +}
1580 +
1581 +
1582 +static char*
1583 +_strnchr(const char *dest,int c,size_t cnt)
1584 +{
1585 + while (*dest && (cnt > 0)) {
1586 + if (*dest == c) return (char *) dest;
1587 + dest++;
1588 + cnt--;
1589 + }
1590 + return NULL;
1591 +}
1592 +
1593 +
1594 +
1595 +/*
1596 + * Core support API: Externally visible.
1597 + */
1598 +
1599 +/*
1600 + * Get the value of an NVRAM variable
1601 + * @param name name of variable to get
1602 + * @return value of variable or NULL if undefined
1603 + */
1604 +
1605 +char*
1606 +cfe_env_get(unsigned char *nv_buf, char* name)
1607 +{
1608 + int size;
1609 + unsigned char *buffer;
1610 + unsigned char *ptr;
1611 + unsigned char *envval;
1612 + unsigned int reclen;
1613 + unsigned int rectype;
1614 + int offset;
1615 + int flg;
1616 +
1617 + size = NVRAM_SIZE;
1618 + buffer = &_nvdata[0];
1619 +
1620 + ptr = buffer;
1621 + offset = 0;
1622 +
1623 + /* Read the record type and length */
1624 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1625 + goto error;
1626 + }
1627 +
1628 + while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
1629 +
1630 + /* Adjust pointer for TLV type */
1631 + rectype = *(ptr);
1632 + offset++;
1633 + size--;
1634 +
1635 + /*
1636 + * Read the length. It can be either 1 or 2 bytes
1637 + * depending on the code
1638 + */
1639 + if (rectype & ENV_LENGTH_8BITS) {
1640 + /* Read the record type and length - 8 bits */
1641 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1642 + goto error;
1643 + }
1644 + reclen = *(ptr);
1645 + size--;
1646 + offset++;
1647 + }
1648 + else {
1649 + /* Read the record type and length - 16 bits, MSB first */
1650 + if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
1651 + goto error;
1652 + }
1653 + reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
1654 + size -= 2;
1655 + offset += 2;
1656 + }
1657 +
1658 + if (reclen > size)
1659 + break; /* should not happen, bad NVRAM */
1660 +
1661 + switch (rectype) {
1662 + case ENV_TLV_TYPE_ENV:
1663 + /* Read the TLV data */
1664 + if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
1665 + goto error;
1666 + flg = *ptr++;
1667 + envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
1668 + if (envval) {
1669 + *envval++ = '\0';
1670 + memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
1671 + _valuestr[(reclen-1)-(envval-ptr)] = '\0';
1672 +#if 0
1673 + printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
1674 +#endif
1675 + if(!strcmp(ptr, name)){
1676 + return _valuestr;
1677 + }
1678 + if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
1679 + return _valuestr;
1680 + }
1681 + break;
1682 +
1683 + default:
1684 + /* Unknown TLV type, skip it. */
1685 + break;
1686 + }
1687 +
1688 + /*
1689 + * Advance to next TLV
1690 + */
1691 +
1692 + size -= (int)reclen;
1693 + offset += reclen;
1694 +
1695 + /* Read the next record type */
1696 + ptr = buffer;
1697 + if (_nvram_read(nv_buf, ptr,offset,1) != 1)
1698 + goto error;
1699 + }
1700 +
1701 +error:
1702 + return NULL;
1703 +
1704 +}
1705 +
1706 diff -urN linux.old/arch/mips/bcm947xx/compressed/Makefile linux.dev/arch/mips/bcm947xx/compressed/Makefile
1707 --- linux.old/arch/mips/bcm947xx/compressed/Makefile 1970-01-01 01:00:00.000000000 +0100
1708 +++ linux.dev/arch/mips/bcm947xx/compressed/Makefile 2006-10-02 21:19:59.000000000 +0200
1709 @@ -0,0 +1,33 @@
1710 +#
1711 +# Makefile for Broadcom BCM947XX boards
1712 +#
1713 +# Copyright 2001-2003, Broadcom Corporation
1714 +# All Rights Reserved.
1715 +#
1716 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1717 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1718 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1719 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1720 +#
1721 +# $Id: Makefile,v 1.2 2005/04/02 12:12:57 wbx Exp $
1722 +#
1723 +
1724 +OBJCOPY_ARGS = -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
1725 +SYSTEM ?= $(TOPDIR)/vmlinux
1726 +
1727 +all: vmlinuz
1728 +
1729 +# Don't build dependencies, this may die if $(CC) isn't gcc
1730 +dep:
1731 +
1732 +# Create a gzipped version named vmlinuz for compatibility
1733 +vmlinuz: piggy
1734 + gzip -c9 $< > $@
1735 +
1736 +piggy: $(SYSTEM)
1737 + $(OBJCOPY) $(OBJCOPY_ARGS) $< $@
1738 +
1739 +mrproper: clean
1740 +
1741 +clean:
1742 + rm -f vmlinuz piggy
1743 diff -urN linux.old/arch/mips/bcm947xx/export.c linux.dev/arch/mips/bcm947xx/export.c
1744 --- linux.old/arch/mips/bcm947xx/export.c 1970-01-01 01:00:00.000000000 +0100
1745 +++ linux.dev/arch/mips/bcm947xx/export.c 2006-10-02 21:19:59.000000000 +0200
1746 @@ -0,0 +1,65 @@
1747 +#include <linux/module.h>
1748 +
1749 +#define _export(n) \
1750 + void n(void); \
1751 + EXPORT_SYMBOL(n);
1752 +
1753 +_export(bcm947xx_sbh)
1754 +
1755 +_export(sb_attach)
1756 +_export(sb_kattach)
1757 +_export(sb_boardtype)
1758 +_export(sb_boardvendor)
1759 +_export(sb_btcgpiowar)
1760 +_export(sb_bus)
1761 +_export(sb_chip)
1762 +_export(sb_chiprev)
1763 +_export(sb_chipcrev)
1764 +_export(sb_chippkg)
1765 +_export(sb_clkctl_clk)
1766 +_export(sb_clkctl_fast_pwrup_delay)
1767 +_export(sb_clkctl_init)
1768 +_export(sb_clkctl_xtal)
1769 +_export(sb_core_disable)
1770 +_export(sb_core_reset)
1771 +_export(sb_core_tofixup)
1772 +_export(sb_coreflags)
1773 +_export(sb_coreflagshi)
1774 +_export(sb_coreidx)
1775 +_export(sb_corerev)
1776 +_export(sb_coreunit)
1777 +_export(sb_detach)
1778 +_export(sb_deviceremoved)
1779 +_export(sb_gpiosetcore)
1780 +_export(sb_gpiocontrol)
1781 +_export(sb_gpioled)
1782 +_export(sb_gpioin)
1783 +_export(sb_gpioout)
1784 +_export(sb_gpioouten)
1785 +_export(sb_gpiotimerval)
1786 +_export(sb_iscoreup)
1787 +_export(sb_pci_setup)
1788 +_export(sb_pcirev)
1789 +_export(sb_pcmcia_init)
1790 +_export(sb_pcmciarev)
1791 +_export(sb_register_intr_callback)
1792 +_export(sb_setcore)
1793 +_export(sb_war16165)
1794 +_export(sb_osh)
1795 +
1796 +_export(getvar)
1797 +_export(getintvar)
1798 +_export(bcm_strtoul)
1799 +_export(bcm_ctype)
1800 +_export(bcm_toupper)
1801 +_export(bcm_ether_ntoa)
1802 +
1803 +_export(nvram_get)
1804 +_export(nvram_getall)
1805 +_export(nvram_set)
1806 +_export(nvram_unset)
1807 +_export(nvram_commit)
1808 +
1809 +_export(srom_read)
1810 +_export(srom_write)
1811 +
1812 diff -urN linux.old/arch/mips/bcm947xx/generic/int-handler.S linux.dev/arch/mips/bcm947xx/generic/int-handler.S
1813 --- linux.old/arch/mips/bcm947xx/generic/int-handler.S 1970-01-01 01:00:00.000000000 +0100
1814 +++ linux.dev/arch/mips/bcm947xx/generic/int-handler.S 2006-10-02 21:19:59.000000000 +0200
1815 @@ -0,0 +1,51 @@
1816 +/*
1817 + * Generic interrupt handler for Broadcom MIPS boards
1818 + *
1819 + * Copyright 2004, Broadcom Corporation
1820 + * All Rights Reserved.
1821 + *
1822 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1823 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1824 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1825 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1826 + *
1827 + * $Id: int-handler.S,v 1.1 2005/03/16 13:50:00 wbx Exp $
1828 + */
1829 +
1830 +#include <linux/config.h>
1831 +
1832 +#include <asm/asm.h>
1833 +#include <asm/mipsregs.h>
1834 +#include <asm/regdef.h>
1835 +#include <asm/stackframe.h>
1836 +
1837 +/*
1838 + * MIPS IRQ Source
1839 + * -------- ------
1840 + * 0 Software (ignored)
1841 + * 1 Software (ignored)
1842 + * 2 Combined hardware interrupt (hw0)
1843 + * 3 Hardware
1844 + * 4 Hardware
1845 + * 5 Hardware
1846 + * 6 Hardware
1847 + * 7 R4k timer
1848 + */
1849 +
1850 + .text
1851 + .set noreorder
1852 + .set noat
1853 + .align 5
1854 + NESTED(brcmIRQ, PT_SIZE, sp)
1855 + SAVE_ALL
1856 + CLI
1857 + .set at
1858 + .set noreorder
1859 +
1860 + jal brcm_irq_dispatch
1861 + move a0, sp
1862 +
1863 + j ret_from_irq
1864 + nop
1865 +
1866 + END(brcmIRQ)
1867 diff -urN linux.old/arch/mips/bcm947xx/generic/irq.c linux.dev/arch/mips/bcm947xx/generic/irq.c
1868 --- linux.old/arch/mips/bcm947xx/generic/irq.c 1970-01-01 01:00:00.000000000 +0100
1869 +++ linux.dev/arch/mips/bcm947xx/generic/irq.c 2006-10-02 21:19:59.000000000 +0200
1870 @@ -0,0 +1,130 @@
1871 +/*
1872 + * Generic interrupt control functions for Broadcom MIPS boards
1873 + *
1874 + * Copyright 2004, Broadcom Corporation
1875 + * All Rights Reserved.
1876 + *
1877 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1878 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1879 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1880 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1881 + *
1882 + * $Id: irq.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
1883 + */
1884 +
1885 +#include <linux/config.h>
1886 +#include <linux/init.h>
1887 +#include <linux/kernel.h>
1888 +#include <linux/types.h>
1889 +#include <linux/interrupt.h>
1890 +#include <linux/irq.h>
1891 +
1892 +#include <asm/irq.h>
1893 +#include <asm/mipsregs.h>
1894 +#include <asm/gdb-stub.h>
1895 +
1896 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
1897 +
1898 +extern asmlinkage void brcmIRQ(void);
1899 +extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
1900 +
1901 +void
1902 +brcm_irq_dispatch(struct pt_regs *regs)
1903 +{
1904 + u32 cause;
1905 +
1906 + cause = read_c0_cause() &
1907 + read_c0_status() &
1908 + CAUSEF_IP;
1909 +
1910 +#ifdef CONFIG_KERNPROF
1911 + change_c0_status(cause | 1, 1);
1912 +#else
1913 + clear_c0_status(cause);
1914 +#endif
1915 +
1916 + if (cause & CAUSEF_IP7)
1917 + do_IRQ(7, regs);
1918 + if (cause & CAUSEF_IP2)
1919 + do_IRQ(2, regs);
1920 + if (cause & CAUSEF_IP3)
1921 + do_IRQ(3, regs);
1922 + if (cause & CAUSEF_IP4)
1923 + do_IRQ(4, regs);
1924 + if (cause & CAUSEF_IP5)
1925 + do_IRQ(5, regs);
1926 + if (cause & CAUSEF_IP6)
1927 + do_IRQ(6, regs);
1928 +}
1929 +
1930 +static void
1931 +enable_brcm_irq(unsigned int irq)
1932 +{
1933 + if (irq < 8)
1934 + set_c0_status(1 << (irq + 8));
1935 + else
1936 + set_c0_status(IE_IRQ0);
1937 +}
1938 +
1939 +static void
1940 +disable_brcm_irq(unsigned int irq)
1941 +{
1942 + if (irq < 8)
1943 + clear_c0_status(1 << (irq + 8));
1944 + else
1945 + clear_c0_status(IE_IRQ0);
1946 +}
1947 +
1948 +static void
1949 +ack_brcm_irq(unsigned int irq)
1950 +{
1951 + /* Already done in brcm_irq_dispatch */
1952 +}
1953 +
1954 +static unsigned int
1955 +startup_brcm_irq(unsigned int irq)
1956 +{
1957 + enable_brcm_irq(irq);
1958 +
1959 + return 0; /* never anything pending */
1960 +}
1961 +
1962 +static void
1963 +end_brcm_irq(unsigned int irq)
1964 +{
1965 + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
1966 + enable_brcm_irq(irq);
1967 +}
1968 +
1969 +static struct hw_interrupt_type brcm_irq_type = {
1970 + typename: "MIPS",
1971 + startup: startup_brcm_irq,
1972 + shutdown: disable_brcm_irq,
1973 + enable: enable_brcm_irq,
1974 + disable: disable_brcm_irq,
1975 + ack: ack_brcm_irq,
1976 + end: end_brcm_irq,
1977 + NULL
1978 +};
1979 +
1980 +void __init
1981 +init_IRQ(void)
1982 +{
1983 + int i;
1984 +
1985 + for (i = 0; i < NR_IRQS; i++) {
1986 + irq_desc[i].status = IRQ_DISABLED;
1987 + irq_desc[i].action = 0;
1988 + irq_desc[i].depth = 1;
1989 + irq_desc[i].handler = &brcm_irq_type;
1990 + }
1991 +
1992 + set_except_vector(0, brcmIRQ);
1993 + change_c0_status(ST0_IM, ALLINTS);
1994 +
1995 +#ifdef CONFIG_REMOTE_DEBUG
1996 + printk("Breaking into debugger...\n");
1997 + set_debug_traps();
1998 + breakpoint();
1999 +#endif
2000 +}
2001 diff -urN linux.old/arch/mips/bcm947xx/generic/Makefile linux.dev/arch/mips/bcm947xx/generic/Makefile
2002 --- linux.old/arch/mips/bcm947xx/generic/Makefile 1970-01-01 01:00:00.000000000 +0100
2003 +++ linux.dev/arch/mips/bcm947xx/generic/Makefile 2006-10-02 21:26:29.000000000 +0200
2004 @@ -0,0 +1,16 @@
2005 +#
2006 +# Makefile for the BCM947xx specific kernel interface routines
2007 +# under Linux.
2008 +#
2009 +EXTRA_CFLAGS += -fno-delayed-branch
2010 +
2011 +.S.s:
2012 + $(CPP) $(AFLAGS) $< -o $*.s
2013 +.S.o:
2014 + $(CC) $(AFLAGS) -c $< -o $*.o
2015 +
2016 +O_TARGET := brcm.o
2017 +
2018 +obj-y := int-handler.o irq.o
2019 +
2020 +include $(TOPDIR)/Rules.make
2021 diff -urN linux.old/arch/mips/bcm947xx/gpio.c linux.dev/arch/mips/bcm947xx/gpio.c
2022 --- linux.old/arch/mips/bcm947xx/gpio.c 1970-01-01 01:00:00.000000000 +0100
2023 +++ linux.dev/arch/mips/bcm947xx/gpio.c 2006-10-02 21:19:59.000000000 +0200
2024 @@ -0,0 +1,159 @@
2025 +/*
2026 + * GPIO char driver
2027 + *
2028 + * Copyright 2005, Broadcom Corporation
2029 + * All Rights Reserved.
2030 + *
2031 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2032 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2033 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2034 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2035 + *
2036 + * $Id$
2037 + */
2038 +
2039 +#include <linux/module.h>
2040 +#include <linux/init.h>
2041 +#include <linux/fs.h>
2042 +#include <linux/miscdevice.h>
2043 +#include <asm/uaccess.h>
2044 +
2045 +#include <typedefs.h>
2046 +#include <osl.h>
2047 +#include <bcmutils.h>
2048 +#include <sbutils.h>
2049 +#include <bcmdevs.h>
2050 +
2051 +static sb_t *gpio_sbh;
2052 +static int gpio_major;
2053 +static devfs_handle_t gpio_dir;
2054 +static struct {
2055 + char *name;
2056 + devfs_handle_t handle;
2057 +} gpio_file[] = {
2058 + { "in", NULL },
2059 + { "out", NULL },
2060 + { "outen", NULL },
2061 + { "control", NULL }
2062 +};
2063 +
2064 +static int
2065 +gpio_open(struct inode *inode, struct file * file)
2066 +{
2067 + if (MINOR(inode->i_rdev) > ARRAYSIZE(gpio_file))
2068 + return -ENODEV;
2069 +
2070 + MOD_INC_USE_COUNT;
2071 + return 0;
2072 +}
2073 +
2074 +static int
2075 +gpio_release(struct inode *inode, struct file * file)
2076 +{
2077 + MOD_DEC_USE_COUNT;
2078 + return 0;
2079 +}
2080 +
2081 +static ssize_t
2082 +gpio_read(struct file *file, char *buf, size_t count, loff_t *ppos)
2083 +{
2084 + u32 val;
2085 +
2086 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
2087 + case 0:
2088 + val = sb_gpioin(gpio_sbh);
2089 + break;
2090 + case 1:
2091 + val = sb_gpioout(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2092 + break;
2093 + case 2:
2094 + val = sb_gpioouten(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2095 + break;
2096 + case 3:
2097 + val = sb_gpiocontrol(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2098 + break;
2099 + default:
2100 + return -ENODEV;
2101 + }
2102 +
2103 + if (put_user(val, (u32 *) buf))
2104 + return -EFAULT;
2105 +
2106 + return sizeof(val);
2107 +}
2108 +
2109 +static ssize_t
2110 +gpio_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
2111 +{
2112 + u32 val;
2113 +
2114 + if (get_user(val, (u32 *) buf))
2115 + return -EFAULT;
2116 +
2117 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
2118 + case 0:
2119 + return -EACCES;
2120 + case 1:
2121 + sb_gpioout(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2122 + break;
2123 + case 2:
2124 + sb_gpioouten(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2125 + break;
2126 + case 3:
2127 + sb_gpiocontrol(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2128 + break;
2129 + default:
2130 + return -ENODEV;
2131 + }
2132 +
2133 + return sizeof(val);
2134 +}
2135 +
2136 +static struct file_operations gpio_fops = {
2137 + owner: THIS_MODULE,
2138 + open: gpio_open,
2139 + release: gpio_release,
2140 + read: gpio_read,
2141 + write: gpio_write,
2142 +};
2143 +
2144 +static int __init
2145 +gpio_init(void)
2146 +{
2147 + int i;
2148 +
2149 + if (!(gpio_sbh = sb_kattach()))
2150 + return -ENODEV;
2151 +
2152 + sb_gpiosetcore(gpio_sbh);
2153 +
2154 + if ((gpio_major = devfs_register_chrdev(0, "gpio", &gpio_fops)) < 0)
2155 + return gpio_major;
2156 +
2157 + gpio_dir = devfs_mk_dir(NULL, "gpio", NULL);
2158 +
2159 + for (i = 0; i < ARRAYSIZE(gpio_file); i++) {
2160 + gpio_file[i].handle = devfs_register(gpio_dir,
2161 + gpio_file[i].name,
2162 + DEVFS_FL_DEFAULT, gpio_major, i,
2163 + S_IFCHR | S_IRUGO | S_IWUGO,
2164 + &gpio_fops, NULL);
2165 + }
2166 +
2167 + return 0;
2168 +}
2169 +
2170 +static void __exit
2171 +gpio_exit(void)
2172 +{
2173 + int i;
2174 +
2175 + for (i = 0; i < ARRAYSIZE(gpio_file); i++)
2176 + devfs_unregister(gpio_file[i].handle);
2177 + devfs_unregister(gpio_dir);
2178 + devfs_unregister_chrdev(gpio_major, "gpio");
2179 + sb_detach(gpio_sbh);
2180 +}
2181 +
2182 +module_init(gpio_init);
2183 +module_exit(gpio_exit);
2184 diff -urN linux.old/arch/mips/bcm947xx/hndchipc.c linux.dev/arch/mips/bcm947xx/hndchipc.c
2185 --- linux.old/arch/mips/bcm947xx/hndchipc.c 1970-01-01 01:00:00.000000000 +0100
2186 +++ linux.dev/arch/mips/bcm947xx/hndchipc.c 2006-10-02 21:19:59.000000000 +0200
2187 @@ -0,0 +1,158 @@
2188 +/*
2189 + * BCM47XX support code for some chipcommon (old extif) facilities (uart)
2190 + *
2191 + * Copyright 2006, Broadcom Corporation
2192 + * All Rights Reserved.
2193 + *
2194 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2195 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2196 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2197 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2198 + *
2199 + * $Id: hndchipc.c,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
2200 + */
2201 +
2202 +#include <typedefs.h>
2203 +#include <bcmdefs.h>
2204 +#include <osl.h>
2205 +#include <bcmutils.h>
2206 +#include <sbutils.h>
2207 +#include <bcmdevs.h>
2208 +#include <bcmnvram.h>
2209 +#include <sbconfig.h>
2210 +#include <sbextif.h>
2211 +#include <sbchipc.h>
2212 +#include <hndcpu.h>
2213 +
2214 +/*
2215 + * Returns TRUE if an external UART exists at the given base
2216 + * register.
2217 + */
2218 +static bool
2219 +BCMINITFN(serial_exists)(osl_t *osh, uint8 *regs)
2220 +{
2221 + uint8 save_mcr, status1;
2222 +
2223 + save_mcr = R_REG(osh, &regs[UART_MCR]);
2224 + W_REG(osh, &regs[UART_MCR], UART_MCR_LOOP | 0x0a);
2225 + status1 = R_REG(osh, &regs[UART_MSR]) & 0xf0;
2226 + W_REG(osh, &regs[UART_MCR], save_mcr);
2227 +
2228 + return (status1 == 0x90);
2229 +}
2230 +
2231 +/*
2232 + * Initializes UART access. The callback function will be called once
2233 + * per found UART.
2234 + */
2235 +void
2236 +BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base,
2237 + uint reg_shift))
2238 +{
2239 + osl_t *osh;
2240 + void *regs;
2241 + ulong base;
2242 + uint irq;
2243 + int i, n;
2244 +
2245 + osh = sb_osh(sbh);
2246 +
2247 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
2248 + extifregs_t *eir = (extifregs_t *) regs;
2249 + sbconfig_t *sb;
2250 +
2251 + /* Determine external UART register base */
2252 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
2253 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(osh, &sb->sbadmatch1)));
2254 +
2255 + /* Determine IRQ */
2256 + irq = sb_irq(sbh);
2257 +
2258 + /* Disable GPIO interrupt initially */
2259 + W_REG(osh, &eir->gpiointpolarity, 0);
2260 + W_REG(osh, &eir->gpiointmask, 0);
2261 +
2262 + /* Search for external UARTs */
2263 + n = 2;
2264 + for (i = 0; i < 2; i++) {
2265 + regs = (void *) REG_MAP(base + (i * 8), 8);
2266 + if (serial_exists(osh, regs)) {
2267 + /* Set GPIO 1 to be the external UART IRQ */
2268 + W_REG(osh, &eir->gpiointmask, 2);
2269 + /* XXXDetermine external UART clock */
2270 + if (add)
2271 + add(regs, irq, 13500000, 0);
2272 + }
2273 + }
2274 +
2275 + /* Add internal UART if enabled */
2276 + if (R_REG(osh, &eir->corecontrol) & CC_UE)
2277 + if (add)
2278 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
2279 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
2280 + chipcregs_t *cc = (chipcregs_t *) regs;
2281 + uint32 rev, cap, pll, baud_base, div;
2282 +
2283 + /* Determine core revision and capabilities */
2284 + rev = sb_corerev(sbh);
2285 + cap = R_REG(osh, &cc->capabilities);
2286 + pll = cap & CAP_PLL_MASK;
2287 +
2288 + /* Determine IRQ */
2289 + irq = sb_irq(sbh);
2290 +
2291 + if (pll == PLL_TYPE1) {
2292 + /* PLL clock */
2293 + baud_base = sb_clock_rate(pll,
2294 + R_REG(osh, &cc->clockcontrol_n),
2295 + R_REG(osh, &cc->clockcontrol_m2));
2296 + div = 1;
2297 + } else {
2298 + /* Fixed ALP clock */
2299 + if (rev >= 11 && rev != 15) {
2300 + baud_base = 20000000;
2301 + div = 1;
2302 + /* Set the override bit so we don't divide it */
2303 + W_REG(osh, &cc->corecontrol, CC_UARTCLKO);
2304 + }
2305 + /* Internal backplane clock */
2306 + else if (rev >= 3) {
2307 + baud_base = sb_clock(sbh);
2308 + div = 2; /* Minimum divisor */
2309 + W_REG(osh, &cc->clkdiv,
2310 + ((R_REG(osh, &cc->clkdiv) & ~CLKD_UART) | div));
2311 + }
2312 + /* Fixed internal backplane clock */
2313 + else {
2314 + baud_base = 88000000;
2315 + div = 48;
2316 + }
2317 +
2318 + /* Clock source depends on strapping if UartClkOverride is unset */
2319 + if ((rev > 0) &&
2320 + ((R_REG(osh, &cc->corecontrol) & CC_UARTCLKO) == 0)) {
2321 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
2322 + /* Internal divided backplane clock */
2323 + baud_base /= div;
2324 + } else {
2325 + /* Assume external clock of 1.8432 MHz */
2326 + baud_base = 1843200;
2327 + }
2328 + }
2329 + }
2330 +
2331 + /* Add internal UARTs */
2332 + n = cap & CAP_UARTS_MASK;
2333 + for (i = 0; i < n; i++) {
2334 + /* Register offset changed after revision 0 */
2335 + if (rev)
2336 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
2337 + else
2338 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
2339 +
2340 + if (add)
2341 + add(regs, irq, baud_base, 0);
2342 + }
2343 + }
2344 +}
2345 +
2346 diff -urN linux.old/arch/mips/bcm947xx/include/bcm4710.h linux.dev/arch/mips/bcm947xx/include/bcm4710.h
2347 --- linux.old/arch/mips/bcm947xx/include/bcm4710.h 1970-01-01 01:00:00.000000000 +0100
2348 +++ linux.dev/arch/mips/bcm947xx/include/bcm4710.h 2006-10-02 21:19:59.000000000 +0200
2349 @@ -0,0 +1,91 @@
2350 +/*
2351 + * BCM4710 address space map and definitions
2352 + * Think twice before adding to this file, this is not the kitchen sink
2353 + * These definitions are not guaranteed for all 47xx chips, only the 4710
2354 + *
2355 + * Copyright 2004, Broadcom Corporation
2356 + * All Rights Reserved.
2357 + *
2358 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2359 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2360 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2361 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2362 + *
2363 + * $Id: bcm4710.h,v 1.3 2004/09/27 07:23:30 tallest Exp $
2364 + */
2365 +
2366 +#ifndef _bcm4710_h_
2367 +#define _bcm4710_h_
2368 +
2369 +/* Address map */
2370 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
2371 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
2372 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
2373 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
2374 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
2375 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
2376 +
2377 +/* Core register space */
2378 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
2379 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
2380 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
2381 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
2382 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
2383 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
2384 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
2385 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
2386 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
2387 +
2388 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
2389 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
2390 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
2391 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
2392 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
2393 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
2394 +
2395 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
2396 +
2397 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
2398 +
2399 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
2400 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
2401 +
2402 +#define SBFLAG_PCI 0
2403 +#define SBFLAG_ENET0 1
2404 +#define SBFLAG_ILINE20 2
2405 +#define SBFLAG_CODEC 3
2406 +#define SBFLAG_USB 4
2407 +#define SBFLAG_EXTIF 5
2408 +#define SBFLAG_ENET1 6
2409 +
2410 +#ifdef CONFIG_HWSIM
2411 +#define BCM4710_TRACE(trval) do { *((int *)0xa0000f18) = (trval); } while (0)
2412 +#else
2413 +#define BCM4710_TRACE(trval)
2414 +#endif
2415 +
2416 +
2417 +/* BCM94702 CPCI -ExtIF used for LocalBus devs */
2418 +
2419 +#define BCM94702_CPCI_RESET_ADDR BCM4710_EXTIF
2420 +#define BCM94702_CPCI_BOARDID_ADDR (BCM4710_EXTIF | 0x4000)
2421 +#define BCM94702_CPCI_DOC_ADDR (BCM4710_EXTIF | 0x6000)
2422 +#define BCM94702_DOC_ADDR BCM94702_CPCI_DOC_ADDR
2423 +#define BCM94702_CPCI_LED_ADDR (BCM4710_EXTIF | 0xc000)
2424 +#define BCM94702_CPCI_NVRAM_ADDR (BCM4710_EXTIF | 0xe000)
2425 +#define BCM94702_CPCI_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
2426 +#define BCM94702_CPCI_TOD_REG_BASE (BCM94702_CPCI_NVRAM_ADDR | 0x1ff0)
2427 +
2428 +#define LED_REG(x) \
2429 + (*(volatile unsigned char *) (KSEG1ADDR(BCM94702_CPCI_LED_ADDR) + (x)))
2430 +
2431 +/*
2432 + * Reset function implemented in PLD. Read or write should trigger hard reset
2433 + */
2434 +#define SYS_HARD_RESET() \
2435 + { for (;;) \
2436 + *( (volatile unsigned char *)\
2437 + KSEG1ADDR(BCM94702_CPCI_RESET_ADDR) ) = 0x80; \
2438 + }
2439 +
2440 +#endif /* _bcm4710_h_ */
2441 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdefs.h linux.dev/arch/mips/bcm947xx/include/bcmdefs.h
2442 --- linux.old/arch/mips/bcm947xx/include/bcmdefs.h 1970-01-01 01:00:00.000000000 +0100
2443 +++ linux.dev/arch/mips/bcm947xx/include/bcmdefs.h 2006-10-02 21:19:59.000000000 +0200
2444 @@ -0,0 +1,106 @@
2445 +/*
2446 + * Misc system wide definitions
2447 + *
2448 + * Copyright 2006, Broadcom Corporation
2449 + * All Rights Reserved.
2450 + *
2451 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2452 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2453 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2454 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2455 + * $Id: bcmdefs.h,v 1.1.1.3 2006/04/08 06:13:39 honor Exp $
2456 + */
2457 +
2458 +#ifndef _bcmdefs_h_
2459 +#define _bcmdefs_h_
2460 +
2461 +/*
2462 + * One doesn't need to include this file explicitly, gets included automatically if
2463 + * typedefs.h is included.
2464 + */
2465 +
2466 +/* Reclaiming text and data :
2467 + * The following macros specify special linker sections that can be reclaimed
2468 + * after a system is considered 'up'.
2469 + */
2470 +#if defined(__GNUC__) && defined(BCMRECLAIM)
2471 +extern bool bcmreclaimed;
2472 +#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data
2473 +#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn
2474 +#else /* #if defined(__GNUC__) && defined(BCMRECLAIM) */
2475 +#define BCMINITDATA(_data) _data
2476 +#define BCMINITFN(_fn) _fn
2477 +#define bcmreclaimed 0
2478 +#endif /* #if defined(__GNUC__) && defined(BCMRECLAIM) */
2479 +
2480 +/* Reclaim uninit functions if BCMNODOWN is defined */
2481 +/* and if they are not already removed by -gc-sections */
2482 +#ifdef BCMNODOWN
2483 +#define BCMUNINITFN(_fn) BCMINITFN(_fn)
2484 +#else
2485 +#define BCMUNINITFN(_fn) _fn
2486 +#endif
2487 +
2488 +#ifdef BCMRECLAIM
2489 +#define CONST
2490 +#else
2491 +#define CONST const
2492 +#endif /* BCMRECLAIM */
2493 +
2494 +/* Compatibility with old-style BCMRECLAIM */
2495 +#define BCMINIT(_id) _id
2496 +
2497 +
2498 +/* Put some library data/code into ROM to reduce RAM requirements */
2499 +#if defined(__GNUC__) && defined(BCMROMOFFLOAD)
2500 +#define BCMROMDATA(_data) __attribute__ ((__section__ (".datarom." #_data))) _data
2501 +#define BCMROMFN(_fn) __attribute__ ((__section__ (".textrom." #_fn))) _fn
2502 +#else
2503 +#define BCMROMDATA(_data) _data
2504 +#define BCMROMFN(_fn) _fn
2505 +#endif
2506 +
2507 +/* Bus types */
2508 +#define SB_BUS 0 /* Silicon Backplane */
2509 +#define PCI_BUS 1 /* PCI target */
2510 +#define PCMCIA_BUS 2 /* PCMCIA target */
2511 +#define SDIO_BUS 3 /* SDIO target */
2512 +#define JTAG_BUS 4 /* JTAG */
2513 +#define NO_BUS 0xFF /* Bus that does not support R/W REG */
2514 +
2515 +/* Allows optimization for single-bus support */
2516 +#ifdef BCMBUSTYPE
2517 +#define BUSTYPE(bus) (BCMBUSTYPE)
2518 +#else
2519 +#define BUSTYPE(bus) (bus)
2520 +#endif
2521 +
2522 +/* Defines for DMA Address Width - Shared between OSL and HNDDMA */
2523 +#define DMADDR_MASK_32 0x0 /* Address mask for 32-bits */
2524 +#define DMADDR_MASK_30 0xc0000000 /* Address mask for 30-bits */
2525 +#define DMADDR_MASK_0 0xffffffff /* Address mask for 0-bits (hi-part) */
2526 +
2527 +#define DMADDRWIDTH_30 30 /* 30-bit addressing capability */
2528 +#define DMADDRWIDTH_32 32 /* 32-bit addressing capability */
2529 +#define DMADDRWIDTH_63 63 /* 64-bit addressing capability */
2530 +#define DMADDRWIDTH_64 64 /* 64-bit addressing capability */
2531 +
2532 +/* packet headroom necessary to accomodate the largest header in the system, (i.e TXOFF).
2533 + * By doing, we avoid the need to allocate an extra buffer for the header when bridging to WL.
2534 + * There is a compile time check in wlc.c which ensure that this value is at least as big
2535 + * as TXOFF. This value is used in dma_rxfill (hnddma.c).
2536 + */
2537 +#define BCMEXTRAHDROOM 160
2538 +
2539 +/* Headroom required for dongle-to-host communication. Packets allocated
2540 + * locally in the dongle (e.g. for CDC ioctls or RNDIS messages) should
2541 + * leave this much room in front for low-level message headers which may
2542 + * be needed to get across the dongle bus to the host. (These messages
2543 + * don't go over the network, so room for the full WL header above would
2544 + * be a waste.)
2545 + */
2546 +#define BCMDONGLEHDRSZ 8
2547 +
2548 +
2549 +
2550 +#endif /* _bcmdefs_h_ */
2551 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs1.h linux.dev/arch/mips/bcm947xx/include/bcmdevs1.h
2552 --- linux.old/arch/mips/bcm947xx/include/bcmdevs1.h 1970-01-01 01:00:00.000000000 +0100
2553 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs1.h 2006-10-02 21:19:59.000000000 +0200
2554 @@ -0,0 +1,391 @@
2555 +/*
2556 + * Broadcom device-specific manifest constants.
2557 + *
2558 + * Copyright 2005, Broadcom Corporation
2559 + * All Rights Reserved.
2560 + *
2561 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2562 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2563 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2564 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2565 + * $Id$
2566 + */
2567 +
2568 +#ifndef _BCMDEVS_H
2569 +#define _BCMDEVS_H
2570 +
2571 +
2572 +/* Known PCI vendor Id's */
2573 +#define VENDOR_EPIGRAM 0xfeda
2574 +#define VENDOR_BROADCOM 0x14e4
2575 +#define VENDOR_3COM 0x10b7
2576 +#define VENDOR_NETGEAR 0x1385
2577 +#define VENDOR_DIAMOND 0x1092
2578 +#define VENDOR_DELL 0x1028
2579 +#define VENDOR_HP 0x0e11
2580 +#define VENDOR_APPLE 0x106b
2581 +
2582 +/* PCI Device Id's */
2583 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
2584 +#define BCM4211_DEVICE_ID 0x4211
2585 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
2586 +#define BCM4231_DEVICE_ID 0x4231
2587 +
2588 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
2589 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
2590 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
2591 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
2592 +
2593 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
2594 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
2595 +
2596 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
2597 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
2598 +
2599 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
2600 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
2601 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
2602 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
2603 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
2604 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
2605 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
2606 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
2607 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
2608 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
2609 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
2610 +
2611 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
2612 +
2613 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
2614 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
2615 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
2616 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
2617 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
2618 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
2619 +
2620 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
2621 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
2622 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
2623 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
2624 +
2625 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
2626 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
2627 +
2628 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
2629 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
2630 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
2631 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
2632 +
2633 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
2634 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
2635 +#define BCM4306_D11G_ID2 0x4325
2636 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
2637 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
2638 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
2639 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
2640 +
2641 +#define BCM4309_PKG_ID 1 /* 4309 package id */
2642 +
2643 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
2644 +#define BCM4303_PKG_ID 2 /* 4303 package id */
2645 +
2646 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
2647 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
2648 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
2649 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
2650 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
2651 +
2652 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
2653 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
2654 +
2655 +
2656 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
2657 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
2658 +
2659 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
2660 +
2661 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
2662 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
2663 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
2664 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
2665 +
2666 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
2667 +
2668 +/* Address map */
2669 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
2670 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
2671 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
2672 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
2673 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
2674 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
2675 +
2676 +/* Core register space */
2677 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
2678 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
2679 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
2680 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
2681 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
2682 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
2683 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
2684 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
2685 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
2686 +
2687 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
2688 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
2689 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
2690 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
2691 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
2692 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
2693 +
2694 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
2695 +
2696 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
2697 +
2698 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
2699 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
2700 +
2701 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
2702 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
2703 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
2704 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
2705 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
2706 +
2707 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
2708 +
2709 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
2710 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
2711 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
2712 +
2713 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
2714 +
2715 +/* PCMCIA vendor Id's */
2716 +
2717 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
2718 +
2719 +/* SDIO vendor Id's */
2720 +#define VENDOR_BROADCOM_SDIO 0x00BF
2721 +
2722 +
2723 +/* boardflags */
2724 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
2725 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
2726 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
2727 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
2728 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
2729 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
2730 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
2731 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
2732 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
2733 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
2734 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
2735 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
2736 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
2737 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
2738 +
2739 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
2740 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
2741 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
2742 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
2743 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
2744 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
2745 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
2746 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
2747 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
2748 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
2749 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
2750 +
2751 +/* Bus types */
2752 +#define SB_BUS 0 /* Silicon Backplane */
2753 +#define PCI_BUS 1 /* PCI target */
2754 +#define PCMCIA_BUS 2 /* PCMCIA target */
2755 +#define SDIO_BUS 3 /* SDIO target */
2756 +#define JTAG_BUS 4 /* JTAG */
2757 +
2758 +/* Allows optimization for single-bus support */
2759 +#ifdef BCMBUSTYPE
2760 +#define BUSTYPE(bus) (BCMBUSTYPE)
2761 +#else
2762 +#define BUSTYPE(bus) (bus)
2763 +#endif
2764 +
2765 +/* power control defines */
2766 +#define PLL_DELAY 150 /* us pll on delay */
2767 +#define FREF_DELAY 200 /* us fref change delay */
2768 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
2769 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
2770 +
2771 +/* Reference Board Types */
2772 +
2773 +#define BU4710_BOARD 0x0400
2774 +#define VSIM4710_BOARD 0x0401
2775 +#define QT4710_BOARD 0x0402
2776 +
2777 +#define BU4610_BOARD 0x0403
2778 +#define VSIM4610_BOARD 0x0404
2779 +
2780 +#define BU4307_BOARD 0x0405
2781 +#define BCM94301CB_BOARD 0x0406
2782 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
2783 +#define BCM94301MP_BOARD 0x0407
2784 +#define BCM94307MP_BOARD 0x0408
2785 +#define BCMAP4307_BOARD 0x0409
2786 +
2787 +#define BU4309_BOARD 0x040a
2788 +#define BCM94309CB_BOARD 0x040b
2789 +#define BCM94309MP_BOARD 0x040c
2790 +#define BCM4309AP_BOARD 0x040d
2791 +
2792 +#define BCM94302MP_BOARD 0x040e
2793 +
2794 +#define VSIM4310_BOARD 0x040f
2795 +#define BU4711_BOARD 0x0410
2796 +#define BCM94310U_BOARD 0x0411
2797 +#define BCM94310AP_BOARD 0x0412
2798 +#define BCM94310MP_BOARD 0x0414
2799 +
2800 +#define BU4306_BOARD 0x0416
2801 +#define BCM94306CB_BOARD 0x0417
2802 +#define BCM94306MP_BOARD 0x0418
2803 +
2804 +#define BCM94710D_BOARD 0x041a
2805 +#define BCM94710R1_BOARD 0x041b
2806 +#define BCM94710R4_BOARD 0x041c
2807 +#define BCM94710AP_BOARD 0x041d
2808 +
2809 +
2810 +#define BU2050_BOARD 0x041f
2811 +
2812 +
2813 +#define BCM94309G_BOARD 0x0421
2814 +
2815 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
2816 +
2817 +#define BU4704_BOARD 0x0423
2818 +#define BU4702_BOARD 0x0424
2819 +
2820 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
2821 +
2822 +#define BU4317_BOARD 0x0426
2823 +
2824 +
2825 +#define BCM94702MN_BOARD 0x0428
2826 +
2827 +/* BCM4702 1U CompactPCI Board */
2828 +#define BCM94702CPCI_BOARD 0x0429
2829 +
2830 +/* BCM4702 with BCM95380 VLAN Router */
2831 +#define BCM95380RR_BOARD 0x042a
2832 +
2833 +/* cb4306 with SiGe PA */
2834 +#define BCM94306CBSG_BOARD 0x042b
2835 +
2836 +/* mp4301 with 2050 radio */
2837 +#define BCM94301MPL_BOARD 0x042c
2838 +
2839 +/* cb4306 with SiGe PA */
2840 +#define PCSG94306_BOARD 0x042d
2841 +
2842 +/* bu4704 with sdram */
2843 +#define BU4704SD_BOARD 0x042e
2844 +
2845 +/* Dual 11a/11g Router */
2846 +#define BCM94704AGR_BOARD 0x042f
2847 +
2848 +/* 11a-only minipci */
2849 +#define BCM94308MP_BOARD 0x0430
2850 +
2851 +
2852 +
2853 +/* BCM94317 boards */
2854 +#define BCM94317CB_BOARD 0x0440
2855 +#define BCM94317MP_BOARD 0x0441
2856 +#define BCM94317PCMCIA_BOARD 0x0442
2857 +#define BCM94317SDIO_BOARD 0x0443
2858 +
2859 +#define BU4712_BOARD 0x0444
2860 +#define BU4712SD_BOARD 0x045d
2861 +#define BU4712L_BOARD 0x045f
2862 +
2863 +/* BCM4712 boards */
2864 +#define BCM94712AP_BOARD 0x0445
2865 +#define BCM94712P_BOARD 0x0446
2866 +
2867 +/* BCM4318 boards */
2868 +#define BU4318_BOARD 0x0447
2869 +#define CB4318_BOARD 0x0448
2870 +#define MPG4318_BOARD 0x0449
2871 +#define MP4318_BOARD 0x044a
2872 +#define SD4318_BOARD 0x044b
2873 +
2874 +/* BCM63XX boards */
2875 +#define BCM96338_BOARD 0x6338
2876 +#define BCM96345_BOARD 0x6345
2877 +#define BCM96348_BOARD 0x6348
2878 +
2879 +/* Another mp4306 with SiGe */
2880 +#define BCM94306P_BOARD 0x044c
2881 +
2882 +/* CF-like 4317 modules */
2883 +#define BCM94317CF_BOARD 0x044d
2884 +
2885 +/* mp4303 */
2886 +#define BCM94303MP_BOARD 0x044e
2887 +
2888 +/* mpsgh4306 */
2889 +#define BCM94306MPSGH_BOARD 0x044f
2890 +
2891 +/* BRCM 4306 w/ Front End Modules */
2892 +#define BCM94306MPM 0x0450
2893 +#define BCM94306MPL 0x0453
2894 +
2895 +/* 4712agr */
2896 +#define BCM94712AGR_BOARD 0x0451
2897 +
2898 +/* The real CF 4317 board */
2899 +#define CFI4317_BOARD 0x0452
2900 +
2901 +/* pcmcia 4303 */
2902 +#define PC4303_BOARD 0x0454
2903 +
2904 +/* 5350K */
2905 +#define BCM95350K_BOARD 0x0455
2906 +
2907 +/* 5350R */
2908 +#define BCM95350R_BOARD 0x0456
2909 +
2910 +/* 4306mplna */
2911 +#define BCM94306MPLNA_BOARD 0x0457
2912 +
2913 +/* 4320 boards */
2914 +#define BU4320_BOARD 0x0458
2915 +#define BU4320S_BOARD 0x0459
2916 +#define BCM94320PH_BOARD 0x045a
2917 +
2918 +/* 4306mph */
2919 +#define BCM94306MPH_BOARD 0x045b
2920 +
2921 +/* 4306pciv */
2922 +#define BCM94306PCIV_BOARD 0x045c
2923 +
2924 +#define BU4712SD_BOARD 0x045d
2925 +
2926 +#define BCM94320PFLSH_BOARD 0x045e
2927 +
2928 +#define BU4712L_BOARD 0x045f
2929 +#define BCM94712LGR_BOARD 0x0460
2930 +#define BCM94320R_BOARD 0x0461
2931 +
2932 +#define BU5352_BOARD 0x0462
2933 +
2934 +#define BCM94318MPGH_BOARD 0x0463
2935 +
2936 +
2937 +#define BCM95352GR_BOARD 0x0467
2938 +
2939 +/* bcm95351agr */
2940 +#define BCM95351AGR_BOARD 0x0470
2941 +
2942 +/* # of GPIO pins */
2943 +#define GPIO_NUMPINS 16
2944 +
2945 +#endif /* _BCMDEVS_H */
2946 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs.h linux.dev/arch/mips/bcm947xx/include/bcmdevs.h
2947 --- linux.old/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
2948 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs.h 2006-10-02 21:19:59.000000000 +0200
2949 @@ -0,0 +1,369 @@
2950 +/*
2951 + * Broadcom device-specific manifest constants.
2952 + *
2953 + * Copyright 2006, Broadcom Corporation
2954 + * All Rights Reserved.
2955 + *
2956 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2957 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2958 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2959 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2960 + * $Id: bcmdevs.h,v 1.1.1.17 2006/04/15 01:29:08 michael Exp $
2961 + */
2962 +
2963 +#ifndef _BCMDEVS_H
2964 +#define _BCMDEVS_H
2965 +
2966 +#include "bcm4710.h"
2967 +
2968 +/* Known PCI vendor Id's */
2969 +#define VENDOR_EPIGRAM 0xfeda
2970 +#define VENDOR_BROADCOM 0x14e4
2971 +#define VENDOR_3COM 0x10b7
2972 +#define VENDOR_NETGEAR 0x1385
2973 +#define VENDOR_DIAMOND 0x1092
2974 +#define VENDOR_DELL 0x1028
2975 +#define VENDOR_HP 0x0e11
2976 +#define VENDOR_APPLE 0x106b
2977 +
2978 +/* PCI Device Id's */
2979 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
2980 +#define BCM4211_DEVICE_ID 0x4211
2981 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
2982 +#define BCM4231_DEVICE_ID 0x4231
2983 +
2984 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
2985 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
2986 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
2987 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
2988 +
2989 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
2990 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
2991 +
2992 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
2993 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
2994 +
2995 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
2996 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
2997 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
2998 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
2999 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
3000 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
3001 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
3002 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
3003 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
3004 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
3005 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
3006 +#define BCM47XX_ATA100_ID 0x471d /* 47xx parallel ATA */
3007 +#define BCM47XX_SATAXOR_ID 0x471e /* 47xx serial ATA & XOR DMA */
3008 +#define BCM47XX_GIGETH_ID 0x471f /* 47xx GbE (5700) */
3009 +
3010 +#define BCM47XX_SMBUS_EMU_ID 0x47fe /* 47xx emulated SMBus device */
3011 +#define BCM47XX_XOR_EMU_ID 0x47ff /* 47xx emulated XOR engine */
3012 +
3013 +#define BCM4710_CHIP_ID 0x4710 /* 4710 chipid returned by sb_chip() */
3014 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
3015 +
3016 +#define BCM4402_CHIP_ID 0x4402 /* 4402 chipid */
3017 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
3018 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
3019 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
3020 +
3021 +#define BCM4306_CHIP_ID 0x4306 /* 4306 chipcommon chipid */
3022 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
3023 +#define BCM4306_D11G_ID2 0x4325
3024 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
3025 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
3026 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
3027 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
3028 +
3029 +#define BCM4309_PKG_ID 1 /* 4309 package id */
3030 +
3031 +#define BCM4311_CHIP_ID 0x4311 /* 4311 PCIe 802.11a/b/g */
3032 +#define BCM4311_D11G_ID 0x4311 /* 4311 802.11b/g id */
3033 +#define BCM4311_D11DUAL_ID 0x4312 /* 4311 802.11a/b/g id */
3034 +#define BCM4311_D11A_ID 0x4313 /* 4311 802.11a id */
3035 +
3036 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
3037 +#define BCM4303_PKG_ID 2 /* 4303 package id */
3038 +
3039 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
3040 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
3041 +
3042 +#define BCM4704_CHIP_ID 0x4704 /* 4704 chipcommon chipid */
3043 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
3044 +
3045 +#define BCM4318_CHIP_ID 0x4318 /* 4318 chip common chipid */
3046 +#define BCM4318_D11G_ID 0x4318 /* 4318 802.11b/g id */
3047 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 802.11a/b/g id */
3048 +#define BCM4318_D11A_ID 0x431a /* 4318 802.11a id */
3049 +
3050 +#define BCM4321_CHIP_ID 0x4321 /* 4321 chip common chipid */
3051 +#define BCM4321_D11N_ID 0x4328 /* 4321 802.11n dualband id */
3052 +#define BCM4321_D11N2G_ID 0x4329 /* 4321 802.11n 2.4Hgz band id */
3053 +#define BCM4321_D11N5G_ID 0x432a /* 4321 802.11n 5Ghz band id */
3054 +
3055 +#define BCM4331_CHIP_ID 0x4331 /* 4331 chip common chipid */
3056 +#define BCM4331_D11N2G_ID 0x4330 /* 4331 802.11n 2.4Ghz band id */
3057 +#define BCM4331_D11N_ID 0x4331 /* 4331 802.11n dualband id */
3058 +#define BCM4331_D11N5G_ID 0x4332 /* 4331 802.11n 5Ghz band id */
3059 +
3060 +#define HDLSIM5350_PKG_ID 1 /* HDL simulator package id for a 5350 */
3061 +#define HDLSIM_PKG_ID 14 /* HDL simulator package id */
3062 +#define HWSIM_PKG_ID 15 /* Hardware simulator package id */
3063 +
3064 +#define BCM4712_CHIP_ID 0x4712 /* 4712 chipcommon chipid */
3065 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
3066 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
3067 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
3068 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
3069 +
3070 +#define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */
3071 +#define BCM5350_CHIP_ID 0x5350 /* bcm5350 chipcommon chipid */
3072 +#define BCM5352_CHIP_ID 0x5352 /* bcm5352 chipcommon chipid */
3073 +
3074 +#define BCM4320_CHIP_ID 0x4320 /* bcm4320 chipcommon chipid */
3075 +
3076 +#define BCM4328_CHIP_ID 0x4328 /* bcm4328 chipcommon chipid */
3077 +
3078 +#define FPGA_JTAGM_ID 0x43f0 /* FPGA jtagm device id */
3079 +#define BCM43XX_JTAGM_ID 0x43f1 /* 43xx jtagm device id */
3080 +#define BCM43XXOLD_JTAGM_ID 0x4331 /* 43xx old jtagm device id */
3081 +
3082 +#define SDIOH_FPGA_ID 0x43f2 /* sdio host fpga */
3083 +#define SDIOD_FPGA_ID 0x43f4 /* sdio device fpga */
3084 +
3085 +#define MIMO_FPGA_ID 0x43f8 /* FPGA mimo minimacphy device id */
3086 +
3087 +#define BCM4785_CHIP_ID 0x4785 /* 4785 chipcommon chipid */
3088 +
3089 +/* PCMCIA vendor Id's */
3090 +
3091 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
3092 +
3093 +/* SDIO vendor Id's */
3094 +#define VENDOR_BROADCOM_SDIO 0x00BF
3095 +
3096 +
3097 +/* boardflags */
3098 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
3099 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
3100 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
3101 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
3102 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
3103 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
3104 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
3105 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
3106 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
3107 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
3108 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
3109 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
3110 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
3111 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
3112 +
3113 +/* boardflags2 */
3114 +#define BFL2_RXBB_INT_REG_DIS 0x00000001 /* This board has an external rxbb regulator */
3115 +#define BFL2_SSWITCH_AVAIL 0x00000002 /* This board has a superswitch for > 2 antennas */
3116 +#define BFL2_TXPWRCTRL_EN 0x00000004 /* This board permits TX Power Control to be enabled */
3117 +
3118 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
3119 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
3120 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
3121 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
3122 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
3123 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
3124 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
3125 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
3126 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
3127 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
3128 +
3129 +/* power control defines */
3130 +#define PLL_DELAY 150 /* us pll on delay */
3131 +#define FREF_DELAY 200 /* us fref change delay */
3132 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
3133 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
3134 +
3135 +/* Reference Board Types */
3136 +
3137 +#define BU4710_BOARD 0x0400
3138 +#define VSIM4710_BOARD 0x0401
3139 +#define QT4710_BOARD 0x0402
3140 +
3141 +#define BU4309_BOARD 0x040a
3142 +#define BCM94309CB_BOARD 0x040b
3143 +#define BCM94309MP_BOARD 0x040c
3144 +#define BCM4309AP_BOARD 0x040d
3145 +
3146 +#define BCM94302MP_BOARD 0x040e
3147 +
3148 +#define BU4306_BOARD 0x0416
3149 +#define BCM94306CB_BOARD 0x0417
3150 +#define BCM94306MP_BOARD 0x0418
3151 +
3152 +#define BCM94710D_BOARD 0x041a
3153 +#define BCM94710R1_BOARD 0x041b
3154 +#define BCM94710R4_BOARD 0x041c
3155 +#define BCM94710AP_BOARD 0x041d
3156 +
3157 +#define BU2050_BOARD 0x041f
3158 +
3159 +
3160 +#define BCM94309G_BOARD 0x0421
3161 +
3162 +#define BU4704_BOARD 0x0423
3163 +#define BU4702_BOARD 0x0424
3164 +
3165 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
3166 +
3167 +
3168 +#define BCM94702MN_BOARD 0x0428
3169 +
3170 +/* BCM4702 1U CompactPCI Board */
3171 +#define BCM94702CPCI_BOARD 0x0429
3172 +
3173 +/* BCM4702 with BCM95380 VLAN Router */
3174 +#define BCM95380RR_BOARD 0x042a
3175 +
3176 +/* cb4306 with SiGe PA */
3177 +#define BCM94306CBSG_BOARD 0x042b
3178 +
3179 +/* cb4306 with SiGe PA */
3180 +#define PCSG94306_BOARD 0x042d
3181 +
3182 +/* bu4704 with sdram */
3183 +#define BU4704SD_BOARD 0x042e
3184 +
3185 +/* Dual 11a/11g Router */
3186 +#define BCM94704AGR_BOARD 0x042f
3187 +
3188 +/* 11a-only minipci */
3189 +#define BCM94308MP_BOARD 0x0430
3190 +
3191 +
3192 +
3193 +#define BU4712_BOARD 0x0444
3194 +#define BU4712SD_BOARD 0x045d
3195 +#define BU4712L_BOARD 0x045f
3196 +
3197 +/* BCM4712 boards */
3198 +#define BCM94712AP_BOARD 0x0445
3199 +#define BCM94712P_BOARD 0x0446
3200 +
3201 +/* BCM4318 boards */
3202 +#define BU4318_BOARD 0x0447
3203 +#define CB4318_BOARD 0x0448
3204 +#define MPG4318_BOARD 0x0449
3205 +#define MP4318_BOARD 0x044a
3206 +#define SD4318_BOARD 0x044b
3207 +
3208 +/* BCM63XX boards */
3209 +#define BCM96338_BOARD 0x6338
3210 +#define BCM96348_BOARD 0x6348
3211 +
3212 +/* Another mp4306 with SiGe */
3213 +#define BCM94306P_BOARD 0x044c
3214 +
3215 +/* mp4303 */
3216 +#define BCM94303MP_BOARD 0x044e
3217 +
3218 +/* mpsgh4306 */
3219 +#define BCM94306MPSGH_BOARD 0x044f
3220 +
3221 +/* BRCM 4306 w/ Front End Modules */
3222 +#define BCM94306MPM 0x0450
3223 +#define BCM94306MPL 0x0453
3224 +
3225 +/* 4712agr */
3226 +#define BCM94712AGR_BOARD 0x0451
3227 +
3228 +/* pcmcia 4303 */
3229 +#define PC4303_BOARD 0x0454
3230 +
3231 +/* 5350K */
3232 +#define BCM95350K_BOARD 0x0455
3233 +
3234 +/* 5350R */
3235 +#define BCM95350R_BOARD 0x0456
3236 +
3237 +/* 4306mplna */
3238 +#define BCM94306MPLNA_BOARD 0x0457
3239 +
3240 +/* 4320 boards */
3241 +#define BU4320_BOARD 0x0458
3242 +#define BU4320S_BOARD 0x0459
3243 +#define BCM94320PH_BOARD 0x045a
3244 +
3245 +/* 4306mph */
3246 +#define BCM94306MPH_BOARD 0x045b
3247 +
3248 +/* 4306pciv */
3249 +#define BCM94306PCIV_BOARD 0x045c
3250 +
3251 +#define BU4712SD_BOARD 0x045d
3252 +
3253 +#define BCM94320PFLSH_BOARD 0x045e
3254 +
3255 +#define BU4712L_BOARD 0x045f
3256 +#define BCM94712LGR_BOARD 0x0460
3257 +#define BCM94320R_BOARD 0x0461
3258 +
3259 +#define BU5352_BOARD 0x0462
3260 +
3261 +#define BCM94318MPGH_BOARD 0x0463
3262 +
3263 +#define BU4311_BOARD 0x0464
3264 +#define BCM94311MC_BOARD 0x0465
3265 +#define BCM94311MCAG_BOARD 0x0466
3266 +
3267 +#define BCM95352GR_BOARD 0x0467
3268 +
3269 +/* bcm95351agr */
3270 +#define BCM95351AGR_BOARD 0x0470
3271 +
3272 +/* bcm94704mpcb */
3273 +#define BCM94704MPCB_BOARD 0x0472
3274 +
3275 +/* 4785 boards */
3276 +#define BU4785_BOARD 0x0478
3277 +
3278 +/* 4321 boards */
3279 +#define BU4321_BOARD 0x046b
3280 +#define BU4321E_BOARD 0x047c
3281 +#define MP4321_BOARD 0x046c
3282 +#define CB2_4321_BOARD 0x046d
3283 +#define MC4321_BOARD 0x046e
3284 +
3285 +/* # of GPIO pins */
3286 +#define GPIO_NUMPINS 16
3287 +
3288 +/* radio ID codes */
3289 +#define NORADIO_ID 0xe4f5
3290 +#define NORADIO_IDCODE 0x4e4f5246
3291 +
3292 +#define BCM2050_ID 0x2050
3293 +#define BCM2050_IDCODE 0x02050000
3294 +#define BCM2050A0_IDCODE 0x1205017f
3295 +#define BCM2050A1_IDCODE 0x2205017f
3296 +#define BCM2050R8_IDCODE 0x8205017f
3297 +
3298 +#define BCM2055_ID 0x2055
3299 +#define BCM2055_IDCODE 0x02055000
3300 +#define BCM2055A0_IDCODE 0x1205517f
3301 +
3302 +#define BCM2060_ID 0x2060
3303 +#define BCM2060_IDCODE 0x02060000
3304 +#define BCM2060WW_IDCODE 0x1206017f
3305 +
3306 +#define BCM2062_ID 0x2062
3307 +#define BCM2062_IDCODE 0x02062000
3308 +#define BCM2062A0_IDCODE 0x0206217f
3309 +
3310 +/* parts of an idcode: */
3311 +#define IDCODE_MFG_MASK 0x00000fff
3312 +#define IDCODE_MFG_SHIFT 0
3313 +#define IDCODE_ID_MASK 0x0ffff000
3314 +#define IDCODE_ID_SHIFT 12
3315 +#define IDCODE_REV_MASK 0xf0000000
3316 +#define IDCODE_REV_SHIFT 28
3317 +
3318 +#endif /* _BCMDEVS_H */
3319 diff -urN linux.old/arch/mips/bcm947xx/include/bcmendian.h linux.dev/arch/mips/bcm947xx/include/bcmendian.h
3320 --- linux.old/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
3321 +++ linux.dev/arch/mips/bcm947xx/include/bcmendian.h 2006-10-02 21:19:59.000000000 +0200
3322 @@ -0,0 +1,198 @@
3323 +/*
3324 + * local version of endian.h - byte order defines
3325 + *
3326 + * Copyright 2006, Broadcom Corporation
3327 + * All Rights Reserved.
3328 + *
3329 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3330 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3331 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3332 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3333 + *
3334 + * $Id: bcmendian.h,v 1.1.1.10 2006/02/27 03:43:16 honor Exp $
3335 +*/
3336 +
3337 +#ifndef _BCMENDIAN_H_
3338 +#define _BCMENDIAN_H_
3339 +
3340 +#include <typedefs.h>
3341 +
3342 +/* Byte swap a 16 bit value */
3343 +#define BCMSWAP16(val) \
3344 + ((uint16)(\
3345 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
3346 + (((uint16)(val) & (uint16)0xff00U) >> 8)))
3347 +
3348 +/* Byte swap a 32 bit value */
3349 +#define BCMSWAP32(val) \
3350 + ((uint32)(\
3351 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
3352 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
3353 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
3354 + (((uint32)(val) & (uint32)0xff000000UL) >> 24)))
3355 +
3356 +/* 2 Byte swap a 32 bit value */
3357 +#define BCMSWAP32BY16(val) \
3358 + ((uint32)(\
3359 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
3360 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16)))
3361 +
3362 +
3363 +static INLINE uint16
3364 +bcmswap16(uint16 val)
3365 +{
3366 + return BCMSWAP16(val);
3367 +}
3368 +
3369 +static INLINE uint32
3370 +bcmswap32(uint32 val)
3371 +{
3372 + return BCMSWAP32(val);
3373 +}
3374 +
3375 +static INLINE uint32
3376 +bcmswap32by16(uint32 val)
3377 +{
3378 + return BCMSWAP32BY16(val);
3379 +}
3380 +
3381 +/* buf - start of buffer of shorts to swap */
3382 +/* len - byte length of buffer */
3383 +static INLINE void
3384 +bcmswap16_buf(uint16 *buf, uint len)
3385 +{
3386 + len = len/2;
3387 +
3388 + while (len--) {
3389 + *buf = bcmswap16(*buf);
3390 + buf++;
3391 + }
3392 +}
3393 +
3394 +#ifndef hton16
3395 +#ifndef IL_BIGENDIAN
3396 +#define HTON16(i) BCMSWAP16(i)
3397 +#define hton16(i) bcmswap16(i)
3398 +#define hton32(i) bcmswap32(i)
3399 +#define ntoh16(i) bcmswap16(i)
3400 +#define ntoh32(i) bcmswap32(i)
3401 +#define ltoh16(i) (i)
3402 +#define ltoh32(i) (i)
3403 +#define htol16(i) (i)
3404 +#define htol32(i) (i)
3405 +#else
3406 +#define HTON16(i) (i)
3407 +#define hton16(i) (i)
3408 +#define hton32(i) (i)
3409 +#define ntoh16(i) (i)
3410 +#define ntoh32(i) (i)
3411 +#define ltoh16(i) bcmswap16(i)
3412 +#define ltoh32(i) bcmswap32(i)
3413 +#define htol16(i) bcmswap16(i)
3414 +#define htol32(i) bcmswap32(i)
3415 +#endif /* IL_BIGENDIAN */
3416 +#endif /* hton16 */
3417 +
3418 +#ifndef IL_BIGENDIAN
3419 +#define ltoh16_buf(buf, i)
3420 +#define htol16_buf(buf, i)
3421 +#else
3422 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
3423 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
3424 +#endif /* IL_BIGENDIAN */
3425 +
3426 +/*
3427 +* store 16-bit value to unaligned little endian byte array.
3428 +*/
3429 +static INLINE void
3430 +htol16_ua_store(uint16 val, uint8 *bytes)
3431 +{
3432 + bytes[0] = val&0xff;
3433 + bytes[1] = val>>8;
3434 +}
3435 +
3436 +/*
3437 +* store 32-bit value to unaligned little endian byte array.
3438 +*/
3439 +static INLINE void
3440 +htol32_ua_store(uint32 val, uint8 *bytes)
3441 +{
3442 + bytes[0] = val&0xff;
3443 + bytes[1] = (val>>8)&0xff;
3444 + bytes[2] = (val>>16)&0xff;
3445 + bytes[3] = val>>24;
3446 +}
3447 +
3448 +/*
3449 +* store 16-bit value to unaligned network(big) endian byte array.
3450 +*/
3451 +static INLINE void
3452 +hton16_ua_store(uint16 val, uint8 *bytes)
3453 +{
3454 + bytes[1] = val&0xff;
3455 + bytes[0] = val>>8;
3456 +}
3457 +
3458 +/*
3459 +* store 32-bit value to unaligned network(big) endian byte array.
3460 +*/
3461 +static INLINE void
3462 +hton32_ua_store(uint32 val, uint8 *bytes)
3463 +{
3464 + bytes[3] = val&0xff;
3465 + bytes[2] = (val>>8)&0xff;
3466 + bytes[1] = (val>>16)&0xff;
3467 + bytes[0] = val>>24;
3468 +}
3469 +
3470 +/*
3471 +* load 16-bit value from unaligned little endian byte array.
3472 +*/
3473 +static INLINE uint16
3474 +ltoh16_ua(void *bytes)
3475 +{
3476 + return (((uint8*)bytes)[1]<<8)+((uint8 *)bytes)[0];
3477 +}
3478 +
3479 +/*
3480 +* load 32-bit value from unaligned little endian byte array.
3481 +*/
3482 +static INLINE uint32
3483 +ltoh32_ua(void *bytes)
3484 +{
3485 + return (((uint8*)bytes)[3]<<24)+(((uint8*)bytes)[2]<<16)+
3486 + (((uint8*)bytes)[1]<<8)+((uint8*)bytes)[0];
3487 +}
3488 +
3489 +/*
3490 +* load 16-bit value from unaligned big(network) endian byte array.
3491 +*/
3492 +static INLINE uint16
3493 +ntoh16_ua(void *bytes)
3494 +{
3495 + return (((uint8*)bytes)[0]<<8)+((uint8*)bytes)[1];
3496 +}
3497 +
3498 +/*
3499 +* load 32-bit value from unaligned big(network) endian byte array.
3500 +*/
3501 +static INLINE uint32
3502 +ntoh32_ua(void *bytes)
3503 +{
3504 + return (((uint8*)bytes)[0]<<24)+(((uint8*)bytes)[1]<<16)+
3505 + (((uint8*)bytes)[2]<<8)+((uint8*)bytes)[3];
3506 +}
3507 +
3508 +#define ltoh_ua(ptr) (\
3509 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
3510 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
3511 + (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
3512 +)
3513 +
3514 +#define ntoh_ua(ptr) (\
3515 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
3516 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
3517 + (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
3518 +)
3519 +
3520 +#endif /* _BCMENDIAN_H_ */
3521 diff -urN linux.old/arch/mips/bcm947xx/include/bcmnvram.h linux.dev/arch/mips/bcm947xx/include/bcmnvram.h
3522 --- linux.old/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
3523 +++ linux.dev/arch/mips/bcm947xx/include/bcmnvram.h 2006-10-02 21:19:59.000000000 +0200
3524 @@ -0,0 +1,159 @@
3525 +/*
3526 + * NVRAM variable manipulation
3527 + *
3528 + * Copyright 2006, Broadcom Corporation
3529 + * All Rights Reserved.
3530 + *
3531 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3532 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3533 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3534 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3535 + *
3536 + * $Id: bcmnvram.h,v 1.17 2006/03/02 12:33:44 honor Exp $
3537 + */
3538 +
3539 +#ifndef _bcmnvram_h_
3540 +#define _bcmnvram_h_
3541 +
3542 +#ifndef _LANGUAGE_ASSEMBLY
3543 +
3544 +#include <typedefs.h>
3545 +#include <bcmdefs.h>
3546 +
3547 +struct nvram_header {
3548 + uint32 magic;
3549 + uint32 len;
3550 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
3551 + uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
3552 + uint32 config_ncdl; /* ncdl values for memc */
3553 +};
3554 +
3555 +struct nvram_tuple {
3556 + char *name;
3557 + char *value;
3558 + struct nvram_tuple *next;
3559 +};
3560 +
3561 +/*
3562 + * Initialize NVRAM access. May be unnecessary or undefined on certain
3563 + * platforms.
3564 + */
3565 +extern int nvram_init(void *sbh);
3566 +
3567 +/*
3568 + * Disable NVRAM access. May be unnecessary or undefined on certain
3569 + * platforms.
3570 + */
3571 +extern void nvram_exit(void *sbh);
3572 +
3573 +/*
3574 + * Get the value of an NVRAM variable. The pointer returned may be
3575 + * invalid after a set.
3576 + * @param name name of variable to get
3577 + * @return value of variable or NULL if undefined
3578 + */
3579 +extern char * nvram_get(const char *name);
3580 +
3581 +/*
3582 + * Read the reset GPIO value from the nvram and set the GPIO
3583 + * as input
3584 + */
3585 +extern int BCMINITFN(nvram_resetgpio_init)(void *sbh);
3586 +extern int BCMINITFN(nvram_gpio_init)(const char *name, void *sbh);
3587 +extern int BCMINITFN(nvram_gpio_set)(const char *name, void *sbh, int type);
3588 +
3589 +/*
3590 + * Get the value of an NVRAM variable.
3591 + * @param name name of variable to get
3592 + * @return value of variable or NUL if undefined
3593 + */
3594 +#define nvram_safe_get(name) (nvram_get(name) ? : "")
3595 +
3596 +#define nvram_safe_unset(name) ({ \
3597 + if(nvram_get(name)) \
3598 + nvram_unset(name); \
3599 +})
3600 +
3601 +#define nvram_safe_set(name, value) ({ \
3602 + if(!nvram_get(name) || strcmp(nvram_get(name), value)) \
3603 + nvram_set(name, value); \
3604 +})
3605 +
3606 +/*
3607 + * Match an NVRAM variable.
3608 + * @param name name of variable to match
3609 + * @param match value to compare against value of variable
3610 + * @return TRUE if variable is defined and its value is string equal
3611 + * to match or FALSE otherwise
3612 + */
3613 +static INLINE int
3614 +nvram_match(char *name, char *match) {
3615 + const char *value = nvram_get(name);
3616 + return (value && !strcmp(value, match));
3617 +}
3618 +
3619 +/*
3620 + * Inversely match an NVRAM variable.
3621 + * @param name name of variable to match
3622 + * @param match value to compare against value of variable
3623 + * @return TRUE if variable is defined and its value is not string
3624 + * equal to invmatch or FALSE otherwise
3625 + */
3626 +static INLINE int
3627 +nvram_invmatch(char *name, char *invmatch) {
3628 + const char *value = nvram_get(name);
3629 + return (value && strcmp(value, invmatch));
3630 +}
3631 +
3632 +/*
3633 + * Set the value of an NVRAM variable. The name and value strings are
3634 + * copied into private storage. Pointers to previously set values
3635 + * may become invalid. The new value may be immediately
3636 + * retrieved but will not be permanently stored until a commit.
3637 + * @param name name of variable to set
3638 + * @param value value of variable
3639 + * @return 0 on success and errno on failure
3640 + */
3641 +extern int nvram_set(const char *name, const char *value);
3642 +
3643 +/*
3644 + * Unset an NVRAM variable. Pointers to previously set values
3645 + * remain valid until a set.
3646 + * @param name name of variable to unset
3647 + * @return 0 on success and errno on failure
3648 + * NOTE: use nvram_commit to commit this change to flash.
3649 + */
3650 +extern int nvram_unset(const char *name);
3651 +
3652 +/*
3653 + * Commit NVRAM variables to permanent storage. All pointers to values
3654 + * may be invalid after a commit.
3655 + * NVRAM values are undefined after a commit.
3656 + * @return 0 on success and errno on failure
3657 + */
3658 +extern int nvram_commit(void);
3659 +
3660 +/*
3661 + * Get all NVRAM variables (format name=value\0 ... \0\0).
3662 + * @param buf buffer to store variables
3663 + * @param count size of buffer in bytes
3664 + * @return 0 on success and errno on failure
3665 + */
3666 +extern int nvram_getall(char *buf, int count);
3667 +
3668 +extern int file2nvram(char *filename, char *varname);
3669 +extern int nvram2file(char *varname, char *filename);
3670 +
3671 +#endif /* _LANGUAGE_ASSEMBLY */
3672 +
3673 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
3674 +#define NVRAM_CLEAR_MAGIC 0x0
3675 +#define NVRAM_INVALID_MAGIC 0xFFFFFFFF
3676 +#define NVRAM_VERSION 1
3677 +#define NVRAM_HEADER_SIZE 20
3678 +#define NVRAM_SPACE 0x8000
3679 +
3680 +#define NVRAM_MAX_VALUE_LEN 255
3681 +#define NVRAM_MAX_PARAM_LEN 64
3682 +
3683 +#endif /* _bcmnvram_h_ */
3684 diff -urN linux.old/arch/mips/bcm947xx/include/bcmsrom.h linux.dev/arch/mips/bcm947xx/include/bcmsrom.h
3685 --- linux.old/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
3686 +++ linux.dev/arch/mips/bcm947xx/include/bcmsrom.h 2006-10-02 21:19:59.000000000 +0200
3687 @@ -0,0 +1,108 @@
3688 +/*
3689 + * Misc useful routines to access NIC local SROM/OTP .
3690 + *
3691 + * Copyright 2006, Broadcom Corporation
3692 + * All Rights Reserved.
3693 + *
3694 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3695 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3696 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3697 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3698 + *
3699 + * $Id: bcmsrom.h,v 1.1.1.13 2006/04/15 01:29:08 michael Exp $
3700 + */
3701 +
3702 +#ifndef _bcmsrom_h_
3703 +#define _bcmsrom_h_
3704 +
3705 +/* Maximum srom: 4 Kilobits == 512 bytes */
3706 +#define SROM_MAX 512
3707 +
3708 +/* SROM Rev 4: Reallocate the software part of the srom to accomodate
3709 + * MIMO features. It assumes up to two PCIE functions and 440 bytes
3710 + * of useable srom i.e. the useable storage in chips with OTP that
3711 + * implements hardware redundancy.
3712 + */
3713 +
3714 +#define SROM4_WORDS 220
3715 +
3716 +#define SROM4_SIGN 32
3717 +#define SROM4_SIGNATURE 0x5372
3718 +
3719 +#define SROM4_BREV 33
3720 +
3721 +#define SROM4_BFL0 34
3722 +#define SROM4_BFL1 35
3723 +#define SROM4_BFL2 36
3724 +#define SROM4_BFL3 37
3725 +
3726 +#define SROM4_MACHI 38
3727 +#define SROM4_MACMID 39
3728 +#define SROM4_MACLO 40
3729 +
3730 +#define SROM4_CCODE 41
3731 +#define SROM4_REGREV 42
3732 +
3733 +#define SROM4_LEDBH10 43
3734 +#define SROM4_LEDBH32 44
3735 +
3736 +#define SROM4_LEDDC 45
3737 +
3738 +#define SROM4_AA 46
3739 +#define SROM4_AA2G_MASK 0x00ff
3740 +#define SROM4_AA2G_SHIFT 0
3741 +#define SROM4_AA5G_MASK 0xff00
3742 +#define SROM4_AA5G_SHIFT 8
3743 +
3744 +#define SROM4_AG10 47
3745 +#define SROM4_AG32 48
3746 +
3747 +#define SROM4_TXPID2G 49
3748 +#define SROM4_TXPID5G 51
3749 +#define SROM4_TXPID5GL 53
3750 +#define SROM4_TXPID5GH 55
3751 +
3752 +/* Per-path fields */
3753 +#define MAX_PATH 4
3754 +#define SROM4_PATH0 64
3755 +#define SROM4_PATH1 87
3756 +#define SROM4_PATH2 110
3757 +#define SROM4_PATH3 133
3758 +
3759 +#define SROM4_2G_ITT_MAXP 0
3760 +#define SROM4_2G_PA 1
3761 +#define SROM4_5G_ITT_MAXP 5
3762 +#define SROM4_5GLH_MAXP 6
3763 +#define SROM4_5G_PA 7
3764 +#define SROM4_5GL_PA 11
3765 +#define SROM4_5GH_PA 15
3766 +
3767 +/* Fields in the ITT_MAXP and 5GLH_MAXP words */
3768 +#define B2G_MAXP_MASK 0xff
3769 +#define B2G_ITT_SHIFT 8
3770 +#define B5G_MAXP_MASK 0xff
3771 +#define B5G_ITT_SHIFT 8
3772 +#define B5GH_MAXP_MASK 0xff
3773 +#define B5GL_MAXP_SHIFT 8
3774 +
3775 +/* All the miriad power offsets */
3776 +#define SROM4_2G_CCKPO 156
3777 +#define SROM4_2G_OFDMPO 157
3778 +#define SROM4_5G_OFDMPO 159
3779 +#define SROM4_5GL_OFDMPO 161
3780 +#define SROM4_5GH_OFDMPO 163
3781 +#define SROM4_2G_MCSPO 165
3782 +#define SROM4_5G_MCSPO 173
3783 +#define SROM4_5GL_MCSPO 181
3784 +#define SROM4_5GH_MCSPO 189
3785 +#define SROM4_CCDPO 197
3786 +#define SROM4_STBCPO 198
3787 +#define SROM4_BW40PO 199
3788 +#define SROM4_BWDUPPO 200
3789 +
3790 +extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, uint *count);
3791 +
3792 +extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
3793 +extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
3794 +
3795 +#endif /* _bcmsrom_h_ */
3796 diff -urN linux.old/arch/mips/bcm947xx/include/bcmutils.h linux.dev/arch/mips/bcm947xx/include/bcmutils.h
3797 --- linux.old/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
3798 +++ linux.dev/arch/mips/bcm947xx/include/bcmutils.h 2006-10-02 21:19:59.000000000 +0200
3799 @@ -0,0 +1,433 @@
3800 +/*
3801 + * Misc useful os-independent macros and functions.
3802 + *
3803 + * Copyright 2006, Broadcom Corporation
3804 + * All Rights Reserved.
3805 + *
3806 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3807 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3808 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3809 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3810 + * $Id: bcmutils.h,v 1.1.1.16 2006/04/08 06:13:39 honor Exp $
3811 + */
3812 +
3813 +#ifndef _bcmutils_h_
3814 +#define _bcmutils_h_
3815 +
3816 +/* ** driver-only section ** */
3817 +#ifdef BCMDRIVER
3818 +
3819 +#define _BCM_U 0x01 /* upper */
3820 +#define _BCM_L 0x02 /* lower */
3821 +#define _BCM_D 0x04 /* digit */
3822 +#define _BCM_C 0x08 /* cntrl */
3823 +#define _BCM_P 0x10 /* punct */
3824 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
3825 +#define _BCM_X 0x40 /* hex digit */
3826 +#define _BCM_SP 0x80 /* hard space (0x20) */
3827 +
3828 +#define GPIO_PIN_NOTDEFINED 0x20 /* Pin not defined */
3829 +
3830 +extern unsigned char bcm_ctype[];
3831 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
3832 +
3833 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
3834 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
3835 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
3836 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
3837 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
3838 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
3839 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
3840 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
3841 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
3842 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
3843 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
3844 +
3845 +/*
3846 + * Spin at most 'us' microseconds while 'exp' is true.
3847 + * Caller should explicitly test 'exp' when this completes
3848 + * and take appropriate error action if 'exp' is still true.
3849 + */
3850 +#define SPINWAIT(exp, us) { \
3851 + uint countdown = (us) + 9; \
3852 + while ((exp) && (countdown >= 10)) {\
3853 + OSL_DELAY(10); \
3854 + countdown -= 10; \
3855 + } \
3856 +}
3857 +
3858 +struct ether_addr {
3859 + uint8 octet[6];
3860 +} __attribute__((packed));
3861 +
3862 +/* string */
3863 +extern uchar bcm_toupper(uchar c);
3864 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
3865 +extern char *bcmstrstr(char *haystack, char *needle);
3866 +extern char *bcmstrcat(char *dest, const char *src);
3867 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
3868 +/* ethernet address */
3869 +extern char *bcm_ether_ntoa(struct ether_addr *ea, char *buf);
3870 +/* variable access */
3871 +extern char *getvar(char *vars, char *name);
3872 +extern int getintvar(char *vars, char *name);
3873 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
3874 +#ifdef BCMPERFSTATS
3875 +extern void bcm_perf_enable(void);
3876 +extern void bcmstats(char *fmt);
3877 +extern void bcmlog(char *fmt, uint a1, uint a2);
3878 +extern void bcmdumplog(char *buf, int size);
3879 +extern int bcmdumplogent(char *buf, uint idx);
3880 +#else
3881 +#define bcm_perf_enable()
3882 +#define bcmstats(fmt)
3883 +#define bcmlog(fmt, a1, a2)
3884 +#define bcmdumplog(buf, size) *buf = '\0'
3885 +#define bcmdumplogent(buf, idx) -1
3886 +#endif /* BCMPERFSTATS */
3887 +extern char *bcm_nvram_vars(uint *length);
3888 +extern int bcm_nvram_cache(void *sbh);
3889 +
3890 +/* Support for sharing code across in-driver iovar implementations.
3891 + * The intent is that a driver use this structure to map iovar names
3892 + * to its (private) iovar identifiers, and the lookup function to
3893 + * find the entry. Macros are provided to map ids and get/set actions
3894 + * into a single number space for a switch statement.
3895 + */
3896 +
3897 +/* iovar structure */
3898 +typedef struct bcm_iovar {
3899 + const char *name; /* name for lookup and display */
3900 + uint16 varid; /* id for switch */
3901 + uint16 flags; /* driver-specific flag bits */
3902 + uint16 type; /* base type of argument */
3903 + uint16 minlen; /* min length for buffer vars */
3904 +} bcm_iovar_t;
3905 +
3906 +/* varid definitions are per-driver, may use these get/set bits */
3907 +
3908 +/* IOVar action bits for id mapping */
3909 +#define IOV_GET 0 /* Get an iovar */
3910 +#define IOV_SET 1 /* Set an iovar */
3911 +
3912 +/* Varid to actionid mapping */
3913 +#define IOV_GVAL(id) ((id)*2)
3914 +#define IOV_SVAL(id) (((id)*2)+IOV_SET)
3915 +#define IOV_ISSET(actionid) ((actionid & IOV_SET) == IOV_SET)
3916 +
3917 +/* flags are per-driver based on driver attributes */
3918 +
3919 +/* Base type definitions */
3920 +#define IOVT_VOID 0 /* no value (implictly set only) */
3921 +#define IOVT_BOOL 1 /* any value ok (zero/nonzero) */
3922 +#define IOVT_INT8 2 /* integer values are range-checked */
3923 +#define IOVT_UINT8 3 /* unsigned int 8 bits */
3924 +#define IOVT_INT16 4 /* int 16 bits */
3925 +#define IOVT_UINT16 5 /* unsigned int 16 bits */
3926 +#define IOVT_INT32 6 /* int 32 bits */
3927 +#define IOVT_UINT32 7 /* unsigned int 32 bits */
3928 +#define IOVT_BUFFER 8 /* buffer is size-checked as per minlen */
3929 +
3930 +extern const bcm_iovar_t *bcm_iovar_lookup(const bcm_iovar_t *table, const char *name);
3931 +extern int bcm_iovar_lencheck(const bcm_iovar_t *table, void *arg, int len, bool set);
3932 +
3933 +#endif /* #ifdef BCMDRIVER */
3934 +
3935 +/* ** driver/apps-shared section ** */
3936 +
3937 +#define BCME_STRLEN 64 /* Max string length for BCM errors */
3938 +#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
3939 +
3940 +
3941 +/*
3942 + * error codes could be added but the defined ones shouldn't be changed/deleted
3943 + * these error codes are exposed to the user code
3944 + * when ever a new error code is added to this list
3945 + * please update errorstring table with the related error string and
3946 + * update osl files with os specific errorcode map
3947 +*/
3948 +
3949 +#define BCME_OK 0 /* Success */
3950 +#define BCME_ERROR -1 /* Error generic */
3951 +#define BCME_BADARG -2 /* Bad Argument */
3952 +#define BCME_BADOPTION -3 /* Bad option */
3953 +#define BCME_NOTUP -4 /* Not up */
3954 +#define BCME_NOTDOWN -5 /* Not down */
3955 +#define BCME_NOTAP -6 /* Not AP */
3956 +#define BCME_NOTSTA -7 /* Not STA */
3957 +#define BCME_BADKEYIDX -8 /* BAD Key Index */
3958 +#define BCME_RADIOOFF -9 /* Radio Off */
3959 +#define BCME_NOTBANDLOCKED -10 /* Not band locked */
3960 +#define BCME_NOCLK -11 /* No Clock */
3961 +#define BCME_BADRATESET -12 /* BAD Rate valueset */
3962 +#define BCME_BADBAND -13 /* BAD Band */
3963 +#define BCME_BUFTOOSHORT -14 /* Buffer too short */
3964 +#define BCME_BUFTOOLONG -15 /* Buffer too long */
3965 +#define BCME_BUSY -16 /* Busy */
3966 +#define BCME_NOTASSOCIATED -17 /* Not Associated */
3967 +#define BCME_BADSSIDLEN -18 /* Bad SSID len */
3968 +#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel */
3969 +#define BCME_BADCHAN -20 /* Bad Channel */
3970 +#define BCME_BADADDR -21 /* Bad Address */
3971 +#define BCME_NORESOURCE -22 /* Not Enough Resources */
3972 +#define BCME_UNSUPPORTED -23 /* Unsupported */
3973 +#define BCME_BADLEN -24 /* Bad length */
3974 +#define BCME_NOTREADY -25 /* Not Ready */
3975 +#define BCME_EPERM -26 /* Not Permitted */
3976 +#define BCME_NOMEM -27 /* No Memory */
3977 +#define BCME_ASSOCIATED -28 /* Associated */
3978 +#define BCME_RANGE -29 /* Not In Range */
3979 +#define BCME_NOTFOUND -30 /* Not Found */
3980 +#define BCME_WME_NOT_ENABLED -31 /* WME Not Enabled */
3981 +#define BCME_TSPEC_NOTFOUND -32 /* TSPEC Not Found */
3982 +#define BCME_ACM_NOTSUPPORTED -33 /* ACM Not Supported */
3983 +#define BCME_NOT_WME_ASSOCIATION -34 /* Not WME Association */
3984 +#define BCME_SDIO_ERROR -35 /* SDIO Bus Error */
3985 +#define BCME_DONGLE_DOWN -36 /* Dongle Not Accessible */
3986 +#define BCME_LAST BCME_DONGLE_DOWN
3987 +
3988 +/* These are collection of BCME Error strings */
3989 +#define BCMERRSTRINGTABLE { \
3990 + "OK", \
3991 + "Undefined error", \
3992 + "Bad Argument", \
3993 + "Bad Option", \
3994 + "Not up", \
3995 + "Not down", \
3996 + "Not AP", \
3997 + "Not STA", \
3998 + "Bad Key Index", \
3999 + "Radio Off", \
4000 + "Not band locked", \
4001 + "No clock", \
4002 + "Bad Rate valueset", \
4003 + "Bad Band", \
4004 + "Buffer too short", \
4005 + "Buffer too long", \
4006 + "Busy", \
4007 + "Not Associated", \
4008 + "Bad SSID len", \
4009 + "Out of Range Channel", \
4010 + "Bad Channel", \
4011 + "Bad Address", \
4012 + "Not Enough Resources", \
4013 + "Unsupported", \
4014 + "Bad length", \
4015 + "Not Ready", \
4016 + "Not Permitted", \
4017 + "No Memory", \
4018 + "Associated", \
4019 + "Not In Range", \
4020 + "Not Found", \
4021 + "WME Not Enabled", \
4022 + "TSPEC Not Found", \
4023 + "ACM Not Supported", \
4024 + "Not WME Association", \
4025 + "SDIO Bus Error", \
4026 + "Dongle Not Accessible" \
4027 +}
4028 +
4029 +#ifndef ABS
4030 +#define ABS(a) (((a) < 0)?-(a):(a))
4031 +#endif /* ABS */
4032 +
4033 +#ifndef MIN
4034 +#define MIN(a, b) (((a) < (b))?(a):(b))
4035 +#endif /* MIN */
4036 +
4037 +#ifndef MAX
4038 +#define MAX(a, b) (((a) > (b))?(a):(b))
4039 +#endif /* MAX */
4040 +
4041 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
4042 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
4043 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
4044 +#define ISPOWEROF2(x) ((((x)-1)&(x)) == 0)
4045 +#define VALID_MASK(mask) !((mask) & ((mask) + 1))
4046 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
4047 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
4048 +
4049 +/* bit map related macros */
4050 +#ifndef setbit
4051 +#ifndef NBBY /* the BSD family defines NBBY */
4052 +#define NBBY 8 /* 8 bits per byte */
4053 +#endif /* #ifndef NBBY */
4054 +#define setbit(a, i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
4055 +#define clrbit(a, i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
4056 +#define isset(a, i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
4057 +#define isclr(a, i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
4058 +#endif /* setbit */
4059 +
4060 +#define NBITS(type) (sizeof(type) * 8)
4061 +#define NBITVAL(nbits) (1 << (nbits))
4062 +#define MAXBITVAL(nbits) ((1 << (nbits)) - 1)
4063 +#define NBITMASK(nbits) MAXBITVAL(nbits)
4064 +#define MAXNBVAL(nbyte) MAXBITVAL((nbyte) * 8)
4065 +
4066 +/* basic mux operation - can be optimized on several architectures */
4067 +#define MUX(pred, true, false) ((pred) ? (true) : (false))
4068 +
4069 +/* modulo inc/dec - assumes x E [0, bound - 1] */
4070 +#define MODDEC(x, bound) MUX((x) == 0, (bound) - 1, (x) - 1)
4071 +#define MODINC(x, bound) MUX((x) == (bound) - 1, 0, (x) + 1)
4072 +
4073 +/* modulo inc/dec, bound = 2^k */
4074 +#define MODDEC_POW2(x, bound) (((x) - 1) & ((bound) - 1))
4075 +#define MODINC_POW2(x, bound) (((x) + 1) & ((bound) - 1))
4076 +
4077 +/* modulo add/sub - assumes x, y E [0, bound - 1] */
4078 +#define MODADD(x, y, bound) \
4079 + MUX((x) + (y) >= (bound), (x) + (y) - (bound), (x) + (y))
4080 +#define MODSUB(x, y, bound) \
4081 + MUX(((int)(x)) - ((int)(y)) < 0, (x) - (y) + (bound), (x) - (y))
4082 +
4083 +/* module add/sub, bound = 2^k */
4084 +#define MODADD_POW2(x, y, bound) (((x) + (y)) & ((bound) - 1))
4085 +#define MODSUB_POW2(x, y, bound) (((x) - (y)) & ((bound) - 1))
4086 +
4087 +/* crc defines */
4088 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
4089 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
4090 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
4091 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
4092 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
4093 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
4094 +
4095 +/* bcm_format_flags() bit description structure */
4096 +typedef struct bcm_bit_desc {
4097 + uint32 bit;
4098 + char* name;
4099 +} bcm_bit_desc_t;
4100 +
4101 +/* tag_ID/length/value_buffer tuple */
4102 +typedef struct bcm_tlv {
4103 + uint8 id;
4104 + uint8 len;
4105 + uint8 data[1];
4106 +} bcm_tlv_t;
4107 +
4108 +/* Check that bcm_tlv_t fits into the given buflen */
4109 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
4110 +
4111 +/* buffer length for ethernet address from bcm_ether_ntoa() */
4112 +#define ETHER_ADDR_STR_LEN 18 /* 18-bytes of Ethernet address buffer length */
4113 +
4114 +/* unaligned load and store macros */
4115 +#ifdef IL_BIGENDIAN
4116 +static INLINE uint32
4117 +load32_ua(uint8 *a)
4118 +{
4119 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
4120 +}
4121 +
4122 +static INLINE void
4123 +store32_ua(uint8 *a, uint32 v)
4124 +{
4125 + a[0] = (v >> 24) & 0xff;
4126 + a[1] = (v >> 16) & 0xff;
4127 + a[2] = (v >> 8) & 0xff;
4128 + a[3] = v & 0xff;
4129 +}
4130 +
4131 +static INLINE uint16
4132 +load16_ua(uint8 *a)
4133 +{
4134 + return ((a[0] << 8) | a[1]);
4135 +}
4136 +
4137 +static INLINE void
4138 +store16_ua(uint8 *a, uint16 v)
4139 +{
4140 + a[0] = (v >> 8) & 0xff;
4141 + a[1] = v & 0xff;
4142 +}
4143 +
4144 +#else
4145 +
4146 +static INLINE uint32
4147 +load32_ua(uint8 *a)
4148 +{
4149 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
4150 +}
4151 +
4152 +static INLINE void
4153 +store32_ua(uint8 *a, uint32 v)
4154 +{
4155 + a[3] = (v >> 24) & 0xff;
4156 + a[2] = (v >> 16) & 0xff;
4157 + a[1] = (v >> 8) & 0xff;
4158 + a[0] = v & 0xff;
4159 +}
4160 +
4161 +static INLINE uint16
4162 +load16_ua(uint8 *a)
4163 +{
4164 + return ((a[1] << 8) | a[0]);
4165 +}
4166 +
4167 +static INLINE void
4168 +store16_ua(uint8 *a, uint16 v)
4169 +{
4170 + a[1] = (v >> 8) & 0xff;
4171 + a[0] = v & 0xff;
4172 +}
4173 +
4174 +#endif /* IL_BIGENDIAN */
4175 +
4176 +/* externs */
4177 +/* crc */
4178 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
4179 +extern uint16 hndcrc16(uint8 *p, uint nbytes, uint16 crc);
4180 +extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc);
4181 +/* format/print */
4182 +extern void printfbig(char *buf);
4183 +
4184 +/* IE parsing */
4185 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
4186 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
4187 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
4188 +
4189 +/* bcmerror */
4190 +extern const char *bcmerrorstr(int bcmerror);
4191 +
4192 +/* multi-bool data type: set of bools, mbool is true if any is set */
4193 +typedef uint32 mbool;
4194 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
4195 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
4196 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
4197 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
4198 +
4199 +/* power conversion */
4200 +extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
4201 +extern uint8 bcm_mw_to_qdbm(uint16 mw);
4202 +
4203 +/* generic datastruct to help dump routines */
4204 +struct fielddesc {
4205 + char *nameandfmt;
4206 + uint32 offset;
4207 + uint32 len;
4208 +};
4209 +
4210 +/* Buffer structure for collecting string-formatted data
4211 +* using bcm_bprintf() API.
4212 +* Use bcm_binit() to initialize before use
4213 +*/
4214 +struct bcmstrbuf
4215 +{
4216 + char *buf; /* pointer to current position in origbuf */
4217 + uint size; /* current (residual) size in bytes */
4218 + char *origbuf; /* unmodified pointer to orignal buffer */
4219 + uint origsize; /* unmodified orignal buffer size in bytes */
4220 +};
4221 +
4222 +extern void bcm_binit(struct bcmstrbuf *b, char *buf, uint size);
4223 +extern int bcm_bprintf(struct bcmstrbuf *b, const char *fmt, ...);
4224 +
4225 +typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
4226 +extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str,
4227 + char *buf, uint32 bufsize);
4228 +
4229 +extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
4230 +extern uint bcm_bitcount(uint8 *bitmap, uint bytelength);
4231 +
4232 +#endif /* _bcmutils_h_ */
4233 diff -urN linux.old/arch/mips/bcm947xx/include/hndcpu.h linux.dev/arch/mips/bcm947xx/include/hndcpu.h
4234 --- linux.old/arch/mips/bcm947xx/include/hndcpu.h 1970-01-01 01:00:00.000000000 +0100
4235 +++ linux.dev/arch/mips/bcm947xx/include/hndcpu.h 2006-10-02 21:19:59.000000000 +0200
4236 @@ -0,0 +1,28 @@
4237 +/*
4238 + * HND SiliconBackplane MIPS/ARM cores software interface.
4239 + *
4240 + * Copyright 2006, Broadcom Corporation
4241 + * All Rights Reserved.
4242 + *
4243 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4244 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4245 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4246 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4247 + *
4248 + * $Id: hndcpu.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
4249 + */
4250 +
4251 +#ifndef _hndcpu_h_
4252 +#define _hndcpu_h_
4253 +
4254 +#if defined(mips)
4255 +#include <hndmips.h>
4256 +#elif defined(__ARM_ARCH_4T__)
4257 +#include <hndarm.h>
4258 +#endif
4259 +
4260 +extern uint sb_irq(sb_t *sbh);
4261 +extern uint32 sb_cpu_clock(sb_t *sbh);
4262 +extern void sb_cpu_wait(void);
4263 +
4264 +#endif /* _hndcpu_h_ */
4265 diff -urN linux.old/arch/mips/bcm947xx/include/hndmips.h linux.dev/arch/mips/bcm947xx/include/hndmips.h
4266 --- linux.old/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
4267 +++ linux.dev/arch/mips/bcm947xx/include/hndmips.h 2006-10-02 21:19:59.000000000 +0200
4268 @@ -0,0 +1,45 @@
4269 +/*
4270 + * HND SiliconBackplane MIPS core software interface.
4271 + *
4272 + * Copyright 2006, Broadcom Corporation
4273 + * All Rights Reserved.
4274 + *
4275 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4276 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4277 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4278 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4279 + *
4280 + * $Id: hndmips.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
4281 + */
4282 +
4283 +#ifndef _hndmips_h_
4284 +#define _hndmips_h_
4285 +
4286 +extern void sb_mips_init(sb_t *sbh, uint shirq_map_base);
4287 +extern bool sb_mips_setclock(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
4288 +extern void enable_pfc(uint32 mode);
4289 +extern uint32 sb_memc_get_ncdl(sb_t *sbh);
4290 +
4291 +#if defined(BCMPERFSTATS)
4292 +/* enable counting - exclusive version. Only one set of counters allowed at a time */
4293 +extern void hndmips_perf_instrcount_enable(void);
4294 +extern void hndmips_perf_icachecount_enable(void);
4295 +extern void hndmips_perf_dcachecount_enable(void);
4296 +/* start and stop counting */
4297 +#define hndmips_perf_start01() \
4298 + MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) | 0x80008000)
4299 +#define hndmips_perf_stop01() \
4300 + MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) & ~0x80008000)
4301 +/* retrieve coutners - counters *decrement* */
4302 +#define hndmips_perf_read0() -(long)(MFC0(C0_PERFORMANCE, 0))
4303 +#define hndmips_perf_read1() -(long)(MFC0(C0_PERFORMANCE, 1))
4304 +#define hndmips_perf_read2() -(long)(MFC0(C0_PERFORMANCE, 2))
4305 +/* enable counting - modular version. Each counters can be enabled separately. */
4306 +extern void hndmips_perf_icache_hit_enable(void);
4307 +extern void hndmips_perf_icache_miss_enable(void);
4308 +extern uint32 hndmips_perf_read_instrcount(void);
4309 +extern uint32 hndmips_perf_read_cache_miss(void);
4310 +extern uint32 hndmips_perf_read_cache_hit(void);
4311 +#endif /* defined(BCMINTERNAL) || defined (BCMPERFSTATS) */
4312 +
4313 +#endif /* _hndmips_h_ */
4314 diff -urN linux.old/arch/mips/bcm947xx/include/hndpci.h linux.dev/arch/mips/bcm947xx/include/hndpci.h
4315 --- linux.old/arch/mips/bcm947xx/include/hndpci.h 1970-01-01 01:00:00.000000000 +0100
4316 +++ linux.dev/arch/mips/bcm947xx/include/hndpci.h 2006-10-02 21:19:59.000000000 +0200
4317 @@ -0,0 +1,30 @@
4318 +/*
4319 + * HND SiliconBackplane PCI core software interface.
4320 + *
4321 + * $Id: hndpci.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
4322 + * Copyright 2006, Broadcom Corporation
4323 + * All Rights Reserved.
4324 + *
4325 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4326 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4327 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4328 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4329 + */
4330 +
4331 +#ifndef _hndpci_h_
4332 +#define _hndpci_h_
4333 +
4334 +extern int sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4335 + int len);
4336 +extern int extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4337 + int len);
4338 +extern int sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4339 + int len);
4340 +extern int extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4341 + int len);
4342 +extern void sbpci_ban(uint16 core);
4343 +extern int sbpci_init(sb_t *sbh);
4344 +extern int sbpci_init_pci(sb_t *sbh);
4345 +extern void sbpci_check(sb_t *sbh);
4346 +
4347 +#endif /* _hndpci_h_ */
4348 diff -urN linux.old/arch/mips/bcm947xx/include/linuxver.h linux.dev/arch/mips/bcm947xx/include/linuxver.h
4349 --- linux.old/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
4350 +++ linux.dev/arch/mips/bcm947xx/include/linuxver.h 2006-10-02 21:19:59.000000000 +0200
4351 @@ -0,0 +1,417 @@
4352 +/*
4353 + * Linux-specific abstractions to gain some independence from linux kernel versions.
4354 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
4355 + *
4356 + * Copyright 2006, Broadcom Corporation
4357 + * All Rights Reserved.
4358 + *
4359 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4360 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4361 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4362 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4363 + *
4364 + * $Id: linuxver.h,v 1.1.1.10 2006/02/27 03:43:16 honor Exp $
4365 + */
4366 +
4367 +#ifndef _linuxver_h_
4368 +#define _linuxver_h_
4369 +
4370 +#include <linux/config.h>
4371 +#include <linux/version.h>
4372 +
4373 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0))
4374 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
4375 +#ifdef __UNDEF_NO_VERSION__
4376 +#undef __NO_VERSION__
4377 +#else
4378 +#define __NO_VERSION__
4379 +#endif
4380 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0) */
4381 +
4382 +#if defined(MODULE) && defined(MODVERSIONS)
4383 +#include <linux/modversions.h>
4384 +#endif
4385 +
4386 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 0)
4387 +#include <linux/moduleparam.h>
4388 +#endif
4389 +
4390 +
4391 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)
4392 +#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
4393 +#define module_param_string(_name_, _string_, _size_, _perm_) \
4394 + MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
4395 +#endif
4396 +
4397 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
4398 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 9))
4399 +#include <linux/malloc.h>
4400 +#else
4401 +#include <linux/slab.h>
4402 +#endif
4403 +
4404 +#include <linux/types.h>
4405 +#include <linux/init.h>
4406 +#include <linux/mm.h>
4407 +#include <linux/string.h>
4408 +#include <linux/pci.h>
4409 +#include <linux/interrupt.h>
4410 +#include <linux/netdevice.h>
4411 +#include <asm/io.h>
4412 +
4413 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
4414 +#include <linux/workqueue.h>
4415 +#else
4416 +#include <linux/tqueue.h>
4417 +#ifndef work_struct
4418 +#define work_struct tq_struct
4419 +#endif
4420 +#ifndef INIT_WORK
4421 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
4422 +#endif
4423 +#ifndef schedule_work
4424 +#define schedule_work(_work) schedule_task((_work))
4425 +#endif
4426 +#ifndef flush_scheduled_work
4427 +#define flush_scheduled_work() flush_scheduled_tasks()
4428 +#endif
4429 +#endif /* LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41) */
4430 +
4431 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
4432 +/* Some distributions have their own 2.6.x compatibility layers */
4433 +#ifndef IRQ_NONE
4434 +typedef void irqreturn_t;
4435 +#define IRQ_NONE
4436 +#define IRQ_HANDLED
4437 +#define IRQ_RETVAL(x)
4438 +#endif
4439 +#else
4440 +typedef irqreturn_t(*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
4441 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0) */
4442 +
4443 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
4444 +
4445 +#include <pcmcia/version.h>
4446 +#include <pcmcia/cs_types.h>
4447 +#include <pcmcia/cs.h>
4448 +#include <pcmcia/cistpl.h>
4449 +#include <pcmcia/cisreg.h>
4450 +#include <pcmcia/ds.h>
4451 +
4452 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 69))
4453 +/* In 2.5 (as of 2.5.69 at least) there is a cs_error exported which
4454 + * does this, but it's not in 2.4 so we do our own for now.
4455 + */
4456 +static inline void
4457 +cs_error(client_handle_t handle, int func, int ret)
4458 +{
4459 + error_info_t err = { func, ret };
4460 + CardServices(ReportError, handle, &err);
4461 +}
4462 +#endif
4463 +
4464 +#endif /* CONFIG_PCMCIA */
4465 +
4466 +#ifndef __exit
4467 +#define __exit
4468 +#endif
4469 +#ifndef __devexit
4470 +#define __devexit
4471 +#endif
4472 +#ifndef __devinit
4473 +#define __devinit __init
4474 +#endif
4475 +#ifndef __devinitdata
4476 +#define __devinitdata
4477 +#endif
4478 +#ifndef __devexit_p
4479 +#define __devexit_p(x) x
4480 +#endif
4481 +
4482 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0))
4483 +
4484 +#define pci_get_drvdata(dev) (dev)->sysdata
4485 +#define pci_set_drvdata(dev, value) (dev)->sysdata = (value)
4486 +
4487 +/*
4488 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
4489 + */
4490 +
4491 +struct pci_device_id {
4492 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
4493 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
4494 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
4495 + unsigned long driver_data; /* Data private to the driver */
4496 +};
4497 +
4498 +struct pci_driver {
4499 + struct list_head node;
4500 + char *name;
4501 + const struct pci_device_id *id_table; /* NULL if wants all devices */
4502 + int (*probe)(struct pci_dev *dev,
4503 + const struct pci_device_id *id); /* New device inserted */
4504 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug
4505 + * capable driver)
4506 + */
4507 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
4508 + void (*resume)(struct pci_dev *dev); /* Device woken up */
4509 +};
4510 +
4511 +#define MODULE_DEVICE_TABLE(type, name)
4512 +#define PCI_ANY_ID (~0)
4513 +
4514 +/* compatpci.c */
4515 +#define pci_module_init pci_register_driver
4516 +extern int pci_register_driver(struct pci_driver *drv);
4517 +extern void pci_unregister_driver(struct pci_driver *drv);
4518 +
4519 +#endif /* PCI registration */
4520 +
4521 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18))
4522 +#ifdef MODULE
4523 +#define module_init(x) int init_module(void) { return x(); }
4524 +#define module_exit(x) void cleanup_module(void) { x(); }
4525 +#else
4526 +#define module_init(x) __initcall(x);
4527 +#define module_exit(x) __exitcall(x);
4528 +#endif
4529 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18) */
4530 +
4531 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 48))
4532 +#define list_for_each(pos, head) \
4533 + for (pos = (head)->next; pos != (head); pos = pos->next)
4534 +#endif
4535 +
4536 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 13))
4537 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
4538 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 44))
4539 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
4540 +#endif
4541 +
4542 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 23))
4543 +#define pci_enable_device(dev) do { } while (0)
4544 +#endif
4545 +
4546 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 14))
4547 +#define net_device device
4548 +#endif
4549 +
4550 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 42))
4551 +
4552 +/*
4553 + * DMA mapping
4554 + *
4555 + * See linux/Documentation/DMA-mapping.txt
4556 + */
4557 +
4558 +#ifndef PCI_DMA_TODEVICE
4559 +#define PCI_DMA_TODEVICE 1
4560 +#define PCI_DMA_FROMDEVICE 2
4561 +#endif
4562 +
4563 +typedef u32 dma_addr_t;
4564 +
4565 +/* Pure 2^n version of get_order */
4566 +static inline int get_order(unsigned long size)
4567 +{
4568 + int order;
4569 +
4570 + size = (size-1) >> (PAGE_SHIFT-1);
4571 + order = -1;
4572 + do {
4573 + size >>= 1;
4574 + order++;
4575 + } while (size);
4576 + return order;
4577 +}
4578 +
4579 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
4580 + dma_addr_t *dma_handle)
4581 +{
4582 + void *ret;
4583 + int gfp = GFP_ATOMIC | GFP_DMA;
4584 +
4585 + ret = (void *)__get_free_pages(gfp, get_order(size));
4586 +
4587 + if (ret != NULL) {
4588 + memset(ret, 0, size);
4589 + *dma_handle = virt_to_bus(ret);
4590 + }
4591 + return ret;
4592 +}
4593 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
4594 + void *vaddr, dma_addr_t dma_handle)
4595 +{
4596 + free_pages((unsigned long)vaddr, get_order(size));
4597 +}
4598 +#ifdef ILSIM
4599 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
4600 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
4601 +#else
4602 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
4603 +#define pci_unmap_single(cookie, address, size, dir)
4604 +#endif
4605 +
4606 +#endif /* DMA mapping */
4607 +
4608 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 43))
4609 +
4610 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
4611 +#define netif_down(dev) do { (dev)->start = 0; } while (0)
4612 +
4613 +/* pcmcia-cs provides its own netdevice compatibility layer */
4614 +#ifndef _COMPAT_NETDEVICE_H
4615 +
4616 +/*
4617 + * SoftNet
4618 + *
4619 + * For pre-softnet kernels we need to tell the upper layer not to
4620 + * re-enter start_xmit() while we are in there. However softnet
4621 + * guarantees not to enter while we are in there so there is no need
4622 + * to do the netif_stop_queue() dance unless the transmit queue really
4623 + * gets stuck. This should also improve performance according to tests
4624 + * done by Aman Singla.
4625 + */
4626 +
4627 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
4628 +#define netif_wake_queue(dev) \
4629 + do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while (0)
4630 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
4631 +
4632 +static inline void netif_start_queue(struct net_device *dev)
4633 +{
4634 + dev->tbusy = 0;
4635 + dev->interrupt = 0;
4636 + dev->start = 1;
4637 +}
4638 +
4639 +#define netif_queue_stopped(dev) (dev)->tbusy
4640 +#define netif_running(dev) (dev)->start
4641 +
4642 +#endif /* _COMPAT_NETDEVICE_H */
4643 +
4644 +#define netif_device_attach(dev) netif_start_queue(dev)
4645 +#define netif_device_detach(dev) netif_stop_queue(dev)
4646 +
4647 +/* 2.4.x renamed bottom halves to tasklets */
4648 +#define tasklet_struct tq_struct
4649 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
4650 +{
4651 + queue_task(tasklet, &tq_immediate);
4652 + mark_bh(IMMEDIATE_BH);
4653 +}
4654 +
4655 +static inline void tasklet_init(struct tasklet_struct *tasklet,
4656 + void (*func)(unsigned long),
4657 + unsigned long data)
4658 +{
4659 + tasklet->next = NULL;
4660 + tasklet->sync = 0;
4661 + tasklet->routine = (void (*)(void *))func;
4662 + tasklet->data = (void *)data;
4663 +}
4664 +#define tasklet_kill(tasklet) { do{} while (0); }
4665 +
4666 +/* 2.4.x introduced del_timer_sync() */
4667 +#define del_timer_sync(timer) del_timer(timer)
4668 +
4669 +#else
4670 +
4671 +#define netif_down(dev)
4672 +
4673 +#endif /* SoftNet */
4674 +
4675 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3))
4676 +
4677 +/*
4678 + * Emit code to initialise a tq_struct's routine and data pointers
4679 + */
4680 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
4681 + do { \
4682 + (_tq)->routine = _routine; \
4683 + (_tq)->data = _data; \
4684 + } while (0)
4685 +
4686 +/*
4687 + * Emit code to initialise all of a tq_struct
4688 + */
4689 +#define INIT_TQUEUE(_tq, _routine, _data) \
4690 + do { \
4691 + INIT_LIST_HEAD(&(_tq)->list); \
4692 + (_tq)->sync = 0; \
4693 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
4694 + } while (0)
4695 +
4696 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3) */
4697 +
4698 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 6))
4699 +
4700 +/* Power management related routines */
4701 +
4702 +static inline int
4703 +pci_save_state(struct pci_dev *dev, u32 *buffer)
4704 +{
4705 + int i;
4706 + if (buffer) {
4707 + for (i = 0; i < 16; i++)
4708 + pci_read_config_dword(dev, i * 4, &buffer[i]);
4709 + }
4710 + return 0;
4711 +}
4712 +
4713 +static inline int
4714 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
4715 +{
4716 + int i;
4717 +
4718 + if (buffer) {
4719 + for (i = 0; i < 16; i++)
4720 + pci_write_config_dword(dev, i * 4, buffer[i]);
4721 + }
4722 + /*
4723 + * otherwise, write the context information we know from bootup.
4724 + * This works around a problem where warm-booting from Windows
4725 + * combined with a D3(hot)->D0 transition causes PCI config
4726 + * header data to be forgotten.
4727 + */
4728 + else {
4729 + for (i = 0; i < 6; i ++)
4730 + pci_write_config_dword(dev,
4731 + PCI_BASE_ADDRESS_0 + (i * 4),
4732 + pci_resource_start(dev, i));
4733 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
4734 + }
4735 + return 0;
4736 +}
4737 +
4738 +#endif /* PCI power management */
4739 +
4740 +/* Old cp0 access macros deprecated in 2.4.19 */
4741 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 19))
4742 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
4743 +#endif
4744 +
4745 +/* Module refcount handled internally in 2.6.x */
4746 +#ifndef SET_MODULE_OWNER
4747 +#define SET_MODULE_OWNER(dev) do {} while (0)
4748 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
4749 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
4750 +#else
4751 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
4752 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
4753 +#endif
4754 +
4755 +#ifndef SET_NETDEV_DEV
4756 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
4757 +#endif
4758 +
4759 +#ifndef HAVE_FREE_NETDEV
4760 +#define free_netdev(dev) kfree(dev)
4761 +#endif
4762 +
4763 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
4764 +/* struct packet_type redefined in 2.6.x */
4765 +#define af_packet_priv data
4766 +#endif
4767 +
4768 +#endif /* _linuxver_h_ */
4769 diff -urN linux.old/arch/mips/bcm947xx/include/mipsinc.h linux.dev/arch/mips/bcm947xx/include/mipsinc.h
4770 --- linux.old/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
4771 +++ linux.dev/arch/mips/bcm947xx/include/mipsinc.h 2006-10-02 21:19:59.000000000 +0200
4772 @@ -0,0 +1,541 @@
4773 +/*
4774 + * HND Run Time Environment for standalone MIPS programs.
4775 + *
4776 + * Copyright 2006, Broadcom Corporation
4777 + * All Rights Reserved.
4778 + *
4779 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4780 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4781 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4782 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4783 + *
4784 + * $Id: mipsinc.h,v 1.1.1.5 2006/02/27 03:43:16 honor Exp $
4785 + */
4786 +
4787 +#ifndef _MISPINC_H
4788 +#define _MISPINC_H
4789 +
4790 +
4791 +/* MIPS defines */
4792 +
4793 +#ifdef _LANGUAGE_ASSEMBLY
4794 +
4795 +/*
4796 + * Symbolic register names for 32 bit ABI
4797 + */
4798 +#define zero $0 /* wired zero */
4799 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
4800 +#define v0 $2 /* return value */
4801 +#define v1 $3
4802 +#define a0 $4 /* argument registers */
4803 +#define a1 $5
4804 +#define a2 $6
4805 +#define a3 $7
4806 +#define t0 $8 /* caller saved */
4807 +#define t1 $9
4808 +#define t2 $10
4809 +#define t3 $11
4810 +#define t4 $12
4811 +#define t5 $13
4812 +#define t6 $14
4813 +#define t7 $15
4814 +#define s0 $16 /* callee saved */
4815 +#define s1 $17
4816 +#define s2 $18
4817 +#define s3 $19
4818 +#define s4 $20
4819 +#define s5 $21
4820 +#define s6 $22
4821 +#define s7 $23
4822 +#define t8 $24 /* caller saved */
4823 +#define t9 $25
4824 +#define jp $25 /* PIC jump register */
4825 +#define k0 $26 /* kernel scratch */
4826 +#define k1 $27
4827 +#define gp $28 /* global pointer */
4828 +#define sp $29 /* stack pointer */
4829 +#define fp $30 /* frame pointer */
4830 +#define s8 $30 /* same like fp! */
4831 +#define ra $31 /* return address */
4832 +
4833 +
4834 +/* CP0 Registers */
4835 +
4836 +#define C0_INX $0
4837 +#define C0_RAND $1
4838 +#define C0_TLBLO0 $2
4839 +#define C0_TLBLO C0_TLBLO0
4840 +#define C0_TLBLO1 $3
4841 +#define C0_CTEXT $4
4842 +#define C0_PGMASK $5
4843 +#define C0_WIRED $6
4844 +#define C0_BADVADDR $8
4845 +#define C0_COUNT $9
4846 +#define C0_TLBHI $10
4847 +#define C0_COMPARE $11
4848 +#define C0_SR $12
4849 +#define C0_STATUS C0_SR
4850 +#define C0_CAUSE $13
4851 +#define C0_EPC $14
4852 +#define C0_PRID $15
4853 +#define C0_CONFIG $16
4854 +#define C0_LLADDR $17
4855 +#define C0_WATCHLO $18
4856 +#define C0_WATCHHI $19
4857 +#define C0_XCTEXT $20
4858 +#define C0_DIAGNOSTIC $22
4859 +#define C0_BROADCOM C0_DIAGNOSTIC
4860 +#define C0_PERFORMANCE $25
4861 +#define C0_ECC $26
4862 +#define C0_CACHEERR $27
4863 +#define C0_TAGLO $28
4864 +#define C0_TAGHI $29
4865 +#define C0_ERREPC $30
4866 +#define C0_DESAVE $31
4867 +
4868 +/*
4869 + * LEAF - declare leaf routine
4870 + */
4871 +#define LEAF(symbol) \
4872 + .globl symbol; \
4873 + .align 2; \
4874 + .type symbol, @function; \
4875 + .ent symbol, 0; \
4876 +symbol: .frame sp, 0, ra
4877 +
4878 +/*
4879 + * END - mark end of function
4880 + */
4881 +#define END(function) \
4882 + .end function; \
4883 + .size function, . - function
4884 +
4885 +#define _ULCAST_
4886 +
4887 +#define MFC0_SEL(dst, src, sel) \
4888 + .word\t(0x40000000 | ((dst) << 16) | ((src) << 11) | (sel))
4889 +
4890 +
4891 +#define MTC0_SEL(dst, src, sel) \
4892 + .word\t(0x40800000 | ((dst) << 16) | ((src) << 11) | (sel))
4893 +
4894 +#else
4895 +
4896 +/*
4897 + * The following macros are especially useful for __asm__
4898 + * inline assembler.
4899 + */
4900 +#ifndef __STR
4901 +#define __STR(x) #x
4902 +#endif
4903 +#ifndef STR
4904 +#define STR(x) __STR(x)
4905 +#endif
4906 +
4907 +#define _ULCAST_ (unsigned long)
4908 +
4909 +
4910 +/* CP0 Registers */
4911 +
4912 +#define C0_INX 0 /* CP0: TLB Index */
4913 +#define C0_RAND 1 /* CP0: TLB Random */
4914 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
4915 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
4916 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
4917 +#define C0_CTEXT 4 /* CP0: Context */
4918 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
4919 +#define C0_WIRED 6 /* CP0: TLB Wired */
4920 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
4921 +#define C0_COUNT 9 /* CP0: Count */
4922 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
4923 +#define C0_COMPARE 11 /* CP0: Compare */
4924 +#define C0_SR 12 /* CP0: Processor Status */
4925 +#define C0_STATUS C0_SR /* CP0: Processor Status */
4926 +#define C0_CAUSE 13 /* CP0: Exception Cause */
4927 +#define C0_EPC 14 /* CP0: Exception PC */
4928 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
4929 +#define C0_CONFIG 16 /* CP0: Config */
4930 +#define C0_LLADDR 17 /* CP0: LLAddr */
4931 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
4932 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
4933 +#define C0_XCTEXT 20 /* CP0: XContext */
4934 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
4935 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
4936 +#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
4937 +#define C0_ECC 26 /* CP0: ECC */
4938 +#define C0_CACHEERR 27 /* CP0: CacheErr */
4939 +#define C0_TAGLO 28 /* CP0: TagLo */
4940 +#define C0_TAGHI 29 /* CP0: TagHi */
4941 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
4942 +#define C0_DESAVE 31 /* CP0: DebugSave */
4943 +
4944 +#endif /* _LANGUAGE_ASSEMBLY */
4945 +
4946 +/*
4947 + * Memory segments (32bit kernel mode addresses)
4948 + */
4949 +#undef KUSEG
4950 +#undef KSEG0
4951 +#undef KSEG1
4952 +#undef KSEG2
4953 +#undef KSEG3
4954 +#define KUSEG 0x00000000
4955 +#define KSEG0 0x80000000
4956 +#define KSEG1 0xa0000000
4957 +#define KSEG2 0xc0000000
4958 +#define KSEG3 0xe0000000
4959 +#define PHYSADDR_MASK 0x1fffffff
4960 +
4961 +/*
4962 + * Map an address to a certain kernel segment
4963 + */
4964 +#undef PHYSADDR
4965 +#undef KSEG0ADDR
4966 +#undef KSEG1ADDR
4967 +#undef KSEG2ADDR
4968 +#undef KSEG3ADDR
4969 +
4970 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
4971 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
4972 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
4973 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
4974 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
4975 +
4976 +
4977 +#ifndef Index_Invalidate_I
4978 +/*
4979 + * Cache Operations
4980 + */
4981 +#define Index_Invalidate_I 0x00
4982 +#define Index_Writeback_Inv_D 0x01
4983 +#define Index_Invalidate_SI 0x02
4984 +#define Index_Writeback_Inv_SD 0x03
4985 +#define Index_Load_Tag_I 0x04
4986 +#define Index_Load_Tag_D 0x05
4987 +#define Index_Load_Tag_SI 0x06
4988 +#define Index_Load_Tag_SD 0x07
4989 +#define Index_Store_Tag_I 0x08
4990 +#define Index_Store_Tag_D 0x09
4991 +#define Index_Store_Tag_SI 0x0A
4992 +#define Index_Store_Tag_SD 0x0B
4993 +#define Create_Dirty_Excl_D 0x0d
4994 +#define Create_Dirty_Excl_SD 0x0f
4995 +#define Hit_Invalidate_I 0x10
4996 +#define Hit_Invalidate_D 0x11
4997 +#define Hit_Invalidate_SI 0x12
4998 +#define Hit_Invalidate_SD 0x13
4999 +#define Fill_I 0x14
5000 +#define Hit_Writeback_Inv_D 0x15
5001 + /* 0x16 is unused */
5002 +#define Hit_Writeback_Inv_SD 0x17
5003 +#define R5K_Page_Invalidate_S 0x17
5004 +#define Hit_Writeback_I 0x18
5005 +#define Hit_Writeback_D 0x19
5006 + /* 0x1a is unused */
5007 +#define Hit_Writeback_SD 0x1b
5008 + /* 0x1c is unused */
5009 + /* 0x1e is unused */
5010 +#define Hit_Set_Virtual_SI 0x1e
5011 +#define Hit_Set_Virtual_SD 0x1f
5012 +#endif /* !Index_Invalidate_I */
5013 +
5014 +
5015 +/*
5016 + * R4x00 interrupt enable / cause bits
5017 + */
5018 +#define IE_SW0 (_ULCAST_(1) << 8)
5019 +#define IE_SW1 (_ULCAST_(1) << 9)
5020 +#define IE_IRQ0 (_ULCAST_(1) << 10)
5021 +#define IE_IRQ1 (_ULCAST_(1) << 11)
5022 +#define IE_IRQ2 (_ULCAST_(1) << 12)
5023 +#define IE_IRQ3 (_ULCAST_(1) << 13)
5024 +#define IE_IRQ4 (_ULCAST_(1) << 14)
5025 +#define IE_IRQ5 (_ULCAST_(1) << 15)
5026 +
5027 +#ifndef ST0_UM
5028 +/*
5029 + * Bitfields in the mips32 cp0 status register
5030 + */
5031 +#define ST0_IE 0x00000001
5032 +#define ST0_EXL 0x00000002
5033 +#define ST0_ERL 0x00000004
5034 +#define ST0_UM 0x00000010
5035 +#define ST0_SWINT0 0x00000100
5036 +#define ST0_SWINT1 0x00000200
5037 +#define ST0_HWINT0 0x00000400
5038 +#define ST0_HWINT1 0x00000800
5039 +#define ST0_HWINT2 0x00001000
5040 +#define ST0_HWINT3 0x00002000
5041 +#define ST0_HWINT4 0x00004000
5042 +#define ST0_HWINT5 0x00008000
5043 +#define ST0_IM 0x0000ff00
5044 +#define ST0_NMI 0x00080000
5045 +#define ST0_SR 0x00100000
5046 +#define ST0_TS 0x00200000
5047 +#define ST0_BEV 0x00400000
5048 +#define ST0_RE 0x02000000
5049 +#define ST0_RP 0x08000000
5050 +#define ST0_CU 0xf0000000
5051 +#define ST0_CU0 0x10000000
5052 +#define ST0_CU1 0x20000000
5053 +#define ST0_CU2 0x40000000
5054 +#define ST0_CU3 0x80000000
5055 +#endif /* !ST0_UM */
5056 +
5057 +
5058 +/*
5059 + * Bitfields in the mips32 cp0 cause register
5060 + */
5061 +#define C_EXC 0x0000007c
5062 +#define C_EXC_SHIFT 2
5063 +#define C_INT 0x0000ff00
5064 +#define C_INT_SHIFT 8
5065 +#define C_SW0 (_ULCAST_(1) << 8)
5066 +#define C_SW1 (_ULCAST_(1) << 9)
5067 +#define C_IRQ0 (_ULCAST_(1) << 10)
5068 +#define C_IRQ1 (_ULCAST_(1) << 11)
5069 +#define C_IRQ2 (_ULCAST_(1) << 12)
5070 +#define C_IRQ3 (_ULCAST_(1) << 13)
5071 +#define C_IRQ4 (_ULCAST_(1) << 14)
5072 +#define C_IRQ5 (_ULCAST_(1) << 15)
5073 +#define C_WP 0x00400000
5074 +#define C_IV 0x00800000
5075 +#define C_CE 0x30000000
5076 +#define C_CE_SHIFT 28
5077 +#define C_BD 0x80000000
5078 +
5079 +/* Values in C_EXC */
5080 +#define EXC_INT 0
5081 +#define EXC_TLBM 1
5082 +#define EXC_TLBL 2
5083 +#define EXC_TLBS 3
5084 +#define EXC_AEL 4
5085 +#define EXC_AES 5
5086 +#define EXC_IBE 6
5087 +#define EXC_DBE 7
5088 +#define EXC_SYS 8
5089 +#define EXC_BPT 9
5090 +#define EXC_RI 10
5091 +#define EXC_CU 11
5092 +#define EXC_OV 12
5093 +#define EXC_TR 13
5094 +#define EXC_WATCH 23
5095 +#define EXC_MCHK 24
5096 +
5097 +
5098 +/*
5099 + * Bits in the cp0 config register.
5100 + */
5101 +#define CONF_CM_CACHABLE_NO_WA 0
5102 +#define CONF_CM_CACHABLE_WA 1
5103 +#define CONF_CM_UNCACHED 2
5104 +#define CONF_CM_CACHABLE_NONCOHERENT 3
5105 +#define CONF_CM_CACHABLE_CE 4
5106 +#define CONF_CM_CACHABLE_COW 5
5107 +#define CONF_CM_CACHABLE_CUW 6
5108 +#define CONF_CM_CACHABLE_ACCELERATED 7
5109 +#define CONF_CM_CMASK 7
5110 +#define CONF_CU (_ULCAST_(1) << 3)
5111 +#define CONF_DB (_ULCAST_(1) << 4)
5112 +#define CONF_IB (_ULCAST_(1) << 5)
5113 +#define CONF_SE (_ULCAST_(1) << 12)
5114 +#ifndef CONF_BE /* duplicate in mipsregs.h */
5115 +#define CONF_BE (_ULCAST_(1) << 15)
5116 +#endif
5117 +#define CONF_SC (_ULCAST_(1) << 17)
5118 +#define CONF_AC (_ULCAST_(1) << 23)
5119 +#define CONF_HALT (_ULCAST_(1) << 25)
5120 +#ifndef CONF_M /* duplicate in mipsregs.h */
5121 +#define CONF_M (_ULCAST_(1) << 31)
5122 +#endif
5123 +
5124 +
5125 +/*
5126 + * Bits in the cp0 config register select 1.
5127 + */
5128 +#define CONF1_FP 0x00000001 /* FPU present */
5129 +#define CONF1_EP 0x00000002 /* EJTAG present */
5130 +#define CONF1_CA 0x00000004 /* mips16 implemented */
5131 +#define CONF1_WR 0x00000008 /* Watch registers present */
5132 +#define CONF1_PC 0x00000010 /* Performance counters present */
5133 +#define CONF1_DA_SHIFT 7 /* D$ associativity */
5134 +#define CONF1_DA_MASK 0x00000380
5135 +#define CONF1_DA_BASE 1
5136 +#define CONF1_DL_SHIFT 10 /* D$ line size */
5137 +#define CONF1_DL_MASK 0x00001c00
5138 +#define CONF1_DL_BASE 2
5139 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */
5140 +#define CONF1_DS_MASK 0x0000e000
5141 +#define CONF1_DS_BASE 64
5142 +#define CONF1_IA_SHIFT 16 /* I$ associativity */
5143 +#define CONF1_IA_MASK 0x00070000
5144 +#define CONF1_IA_BASE 1
5145 +#define CONF1_IL_SHIFT 19 /* I$ line size */
5146 +#define CONF1_IL_MASK 0x00380000
5147 +#define CONF1_IL_BASE 2
5148 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
5149 +#define CONF1_IS_MASK 0x01c00000
5150 +#define CONF1_IS_BASE 64
5151 +#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
5152 +#define CONF1_MS_SHIFT 25
5153 +
5154 +/* PRID register */
5155 +#define PRID_COPT_MASK 0xff000000
5156 +#define PRID_COMP_MASK 0x00ff0000
5157 +#define PRID_IMP_MASK 0x0000ff00
5158 +#define PRID_REV_MASK 0x000000ff
5159 +
5160 +#define PRID_COMP_LEGACY 0x000000
5161 +#define PRID_COMP_MIPS 0x010000
5162 +#define PRID_COMP_BROADCOM 0x020000
5163 +#define PRID_COMP_ALCHEMY 0x030000
5164 +#define PRID_COMP_SIBYTE 0x040000
5165 +#define PRID_IMP_BCM4710 0x4000
5166 +#define PRID_IMP_BCM3302 0x9000
5167 +#define PRID_IMP_BCM3303 0x9100
5168 +
5169 +#define PRID_IMP_UNKNOWN 0xff00
5170 +
5171 +#define BCM330X(id) \
5172 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == \
5173 + (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) || \
5174 + ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == \
5175 + (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
5176 +
5177 +/* Bits in C0_BROADCOM */
5178 +#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
5179 +#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
5180 +#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
5181 +#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
5182 +#define BRCM_CLF_ENABLE 0x00100000 /* Enable cache line first feature */
5183 +
5184 +/* PreFetch Cache aka Read Ahead Cache */
5185 +
5186 +#define PFC_CR0 0xff400000 /* control reg 0 */
5187 +#define PFC_CR1 0xff400004 /* control reg 1 */
5188 +
5189 +/* PFC operations */
5190 +#define PFC_I 0x00000001 /* Enable PFC use for instructions */
5191 +#define PFC_D 0x00000002 /* Enable PFC use for data */
5192 +#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
5193 +#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
5194 +#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
5195 +#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
5196 +#define PFC_DPF 0x00000040 /* Enable directional prefetching */
5197 +#define PFC_FLUSH 0x00000100 /* Flush the PFC */
5198 +#define PFC_BRR 0x40000000 /* Bus error indication */
5199 +#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
5200 +
5201 +/* Handy defaults */
5202 +#define PFC_DISABLED 0
5203 +#define PFC_AUTO 0xffffffff /* auto select the default mode */
5204 +#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
5205 +#define PFC_INST_NOPF (PFC_I | PFC_CINV)
5206 +#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
5207 +#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
5208 +#define PFC_I_AND_D (PFC_INST | PFC_DATA)
5209 +#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
5210 +
5211 +#ifndef _LANGUAGE_ASSEMBLY
5212 +
5213 +/*
5214 + * Macros to access the system control coprocessor
5215 + */
5216 +
5217 +#define MFC0(source, sel) \
5218 +({ \
5219 + int __res; \
5220 + __asm__ __volatile__(" \
5221 + .set\tnoreorder; \
5222 + .set\tnoat; \
5223 + .word\t"STR(0x40010000 | ((source) << 11) | (sel))"; \
5224 + move\t%0, $1; \
5225 + .set\tat; \
5226 + .set\treorder" \
5227 + :"=r" (__res) \
5228 + : \
5229 + :"$1"); \
5230 + __res; \
5231 +})
5232 +
5233 +#define MTC0(source, sel, value) \
5234 +do { \
5235 + __asm__ __volatile__(" \
5236 + .set\tnoreorder; \
5237 + .set\tnoat; \
5238 + move\t$1, %z0; \
5239 + .word\t"STR(0x40810000 | ((source) << 11) | (sel))"; \
5240 + .set\tat; \
5241 + .set\treorder" \
5242 + : \
5243 + :"jr" (value) \
5244 + :"$1"); \
5245 +} while (0)
5246 +
5247 +#define get_c0_count() \
5248 +({ \
5249 + int __res; \
5250 + __asm__ __volatile__(" \
5251 + .set\tnoreorder; \
5252 + .set\tnoat; \
5253 + mfc0\t%0, $9; \
5254 + .set\tat; \
5255 + .set\treorder" \
5256 + :"=r" (__res)); \
5257 + __res; \
5258 +})
5259 +
5260 +static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
5261 +{
5262 + uint lsz, sets, ways;
5263 +
5264 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
5265 + if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
5266 + lsz = CONF1_IL_BASE << lsz;
5267 + sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
5268 + ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
5269 + *size = lsz * sets * ways;
5270 + *lsize = lsz;
5271 +}
5272 +
5273 +static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
5274 +{
5275 + uint lsz, sets, ways;
5276 +
5277 + /* Data Cache Size = Associativity * Line Size * Sets Per Way */
5278 + if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
5279 + lsz = CONF1_DL_BASE << lsz;
5280 + sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
5281 + ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
5282 + *size = lsz * sets * ways;
5283 + *lsize = lsz;
5284 +}
5285 +
5286 +#define cache_op(base, op) \
5287 + __asm__ __volatile__(" \
5288 + .set noreorder; \
5289 + .set mips3; \
5290 + cache %1, (%0); \
5291 + .set mips0; \
5292 + .set reorder" \
5293 + : \
5294 + : "r" (base), \
5295 + "i" (op));
5296 +
5297 +#define cache_unroll4(base, delta, op) \
5298 + __asm__ __volatile__(" \
5299 + .set noreorder; \
5300 + .set mips3; \
5301 + cache %1, 0(%0); \
5302 + cache %1, delta(%0); \
5303 + cache %1, (2 * delta)(%0); \
5304 + cache %1, (3 * delta)(%0); \
5305 + .set mips0; \
5306 + .set reorder" \
5307 + : \
5308 + : "r" (base), \
5309 + "i" (op));
5310 +
5311 +#endif /* !_LANGUAGE_ASSEMBLY */
5312 +
5313 +#endif /* _MISPINC_H */
5314 diff -urN linux.old/arch/mips/bcm947xx/include/osl.h linux.dev/arch/mips/bcm947xx/include/osl.h
5315 --- linux.old/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
5316 +++ linux.dev/arch/mips/bcm947xx/include/osl.h 2006-10-02 21:19:59.000000000 +0200
5317 @@ -0,0 +1,179 @@
5318 +#ifndef __osl_h
5319 +#define __osl_h
5320 +
5321 +#include <linux/delay.h>
5322 +#include <typedefs.h>
5323 +#include <linuxver.h>
5324 +#include <bcmutils.h>
5325 +#include <pcicfg.h>
5326 +
5327 +#define ASSERT(n)
5328 +
5329 +/* Pkttag flag should be part of public information */
5330 +struct osl_pubinfo {
5331 + bool pkttag;
5332 + uint pktalloced; /* Number of allocated packet buffers */
5333 +};
5334 +
5335 +struct osl_info {
5336 + struct osl_pubinfo pub;
5337 + uint magic;
5338 + void *pdev;
5339 + uint malloced;
5340 + uint failed;
5341 + void *dbgmem_list;
5342 +};
5343 +
5344 +typedef struct osl_info osl_t;
5345 +
5346 +#define PCI_CFG_RETRY 10
5347 +
5348 +/* map/unmap direction */
5349 +#define DMA_TX 1 /* TX direction for DMA */
5350 +#define DMA_RX 2 /* RX direction for DMA */
5351 +
5352 +#define AND_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) & (v))
5353 +#define OR_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) | (v))
5354 +#define SET_REG(osh, r, mask, val) W_REG((osh), (r), ((R_REG((osh), r) & ~(mask)) | (val)))
5355 +
5356 +/* bcopy, bcmp, and bzero */
5357 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
5358 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
5359 +#define bzero(b, len) memset((b), '\0', (len))
5360 +
5361 +/* uncached virtual address */
5362 +#ifdef mips
5363 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
5364 +#include <asm/addrspace.h>
5365 +#else
5366 +#define OSL_UNCACHED(va) (va)
5367 +#endif /* mips */
5368 +
5369 +
5370 +#ifndef IL_BIGENDIAN
5371 +#define R_REG(osh, r) (\
5372 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
5373 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
5374 + readl((volatile uint32*)(r)) \
5375 +)
5376 +#define W_REG(osh, r, v) do { \
5377 + switch (sizeof(*(r))) { \
5378 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
5379 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
5380 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
5381 + } \
5382 +} while (0)
5383 +#else /* IL_BIGENDIAN */
5384 +#define R_REG(osh, r) ({ \
5385 + __typeof(*(r)) __osl_v; \
5386 + switch (sizeof(*(r))) { \
5387 + case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
5388 + case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
5389 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
5390 + } \
5391 + __osl_v; \
5392 +})
5393 +#define W_REG(osh, r, v) do { \
5394 + switch (sizeof(*(r))) { \
5395 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
5396 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
5397 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
5398 + } \
5399 +} while (0)
5400 +#endif /* IL_BIGENDIAN */
5401 +
5402 +/* dereference an address that may cause a bus exception */
5403 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
5404 +#include <asm/paccess.h>
5405 +
5406 +/* map/unmap physical to virtual I/O */
5407 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
5408 +#define REG_UNMAP(va) iounmap((void *)(va))
5409 +
5410 +/* shared (dma-able) memory access macros */
5411 +#define R_SM(r) *(r)
5412 +#define W_SM(r, v) (*(r) = (v))
5413 +#define BZERO_SM(r, len) memset((r), '\0', (len))
5414 +
5415 +#define MALLOC(osh, size) kmalloc((size), GFP_ATOMIC)
5416 +#define MFREE(osh, addr, size) kfree((addr))
5417 +#define MALLOCED(osh) (0)
5418 +
5419 +#define osl_delay OSL_DELAY
5420 +static inline void OSL_DELAY(uint usec)
5421 +{
5422 + uint d;
5423 +
5424 + while (usec > 0) {
5425 + d = MIN(usec, 1000);
5426 + udelay(d);
5427 + usec -= d;
5428 + }
5429 +}
5430 +
5431 +static inline void
5432 +bcm_mdelay(uint ms)
5433 +{
5434 + uint i;
5435 +
5436 + for (i = 0; i < ms; i++) {
5437 + OSL_DELAY(1000);
5438 + }
5439 +}
5440 +
5441 +
5442 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size)
5443 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size)
5444 +
5445 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
5446 + osl_pci_read_config((osh), (offset), (size))
5447 +
5448 +static inline uint32
5449 +osl_pci_read_config(osl_t *osh, uint offset, uint size)
5450 +{
5451 + uint val;
5452 + uint retry = PCI_CFG_RETRY;
5453 +
5454 + do {
5455 + pci_read_config_dword(osh->pdev, offset, &val);
5456 + if (val != 0xffffffff)
5457 + break;
5458 + } while (retry--);
5459 +
5460 + return (val);
5461 +}
5462 +
5463 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
5464 + osl_pci_write_config((osh), (offset), (size), (val))
5465 +static inline void
5466 +osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
5467 +{
5468 + uint retry = PCI_CFG_RETRY;
5469 +
5470 + do {
5471 + pci_write_config_dword(osh->pdev, offset, val);
5472 + if (offset != PCI_BAR0_WIN)
5473 + break;
5474 + if (osl_pci_read_config(osh, offset, size) == val)
5475 + break;
5476 + } while (retry--);
5477 +}
5478 +
5479 +
5480 +/* return bus # for the pci device pointed by osh->pdev */
5481 +#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
5482 +static inline uint
5483 +osl_pci_bus(osl_t *osh)
5484 +{
5485 + return ((struct pci_dev *)osh->pdev)->bus->number;
5486 +}
5487 +
5488 +/* return slot # for the pci device pointed by osh->pdev */
5489 +#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
5490 +static inline uint
5491 +osl_pci_slot(osl_t *osh)
5492 +{
5493 + return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn);
5494 +}
5495 +
5496 +#endif
5497 diff -urN linux.old/arch/mips/bcm947xx/include/pcicfg.h linux.dev/arch/mips/bcm947xx/include/pcicfg.h
5498 --- linux.old/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
5499 +++ linux.dev/arch/mips/bcm947xx/include/pcicfg.h 2006-10-02 21:19:59.000000000 +0200
5500 @@ -0,0 +1,495 @@
5501 +/*
5502 + * pcicfg.h: PCI configuration constants and structures.
5503 + *
5504 + * Copyright 2006, Broadcom Corporation
5505 + * All Rights Reserved.
5506 + *
5507 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5508 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5509 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5510 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5511 + *
5512 + * $Id: pcicfg.h,v 1.1.1.11 2006/04/08 06:13:40 honor Exp $
5513 + */
5514 +
5515 +#ifndef _h_pcicfg_
5516 +#define _h_pcicfg_
5517 +
5518 +/* The following inside ifndef's so we don't collide with NTDDK.H */
5519 +#ifndef PCI_MAX_BUS
5520 +#define PCI_MAX_BUS 0x100
5521 +#endif
5522 +#ifndef PCI_MAX_DEVICES
5523 +#define PCI_MAX_DEVICES 0x20
5524 +#endif
5525 +#ifndef PCI_MAX_FUNCTION
5526 +#define PCI_MAX_FUNCTION 0x8
5527 +#endif
5528 +
5529 +#ifndef PCI_INVALID_VENDORID
5530 +#define PCI_INVALID_VENDORID 0xffff
5531 +#endif
5532 +#ifndef PCI_INVALID_DEVICEID
5533 +#define PCI_INVALID_DEVICEID 0xffff
5534 +#endif
5535 +
5536 +
5537 +/* Convert between bus-slot-function-register and config addresses */
5538 +
5539 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
5540 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
5541 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
5542 +#define PCICFG_OFF_SHIFT 0 /* Register shift */
5543 +
5544 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
5545 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
5546 +#define PCICFG_FUN_MASK 7 /* Function mask */
5547 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
5548 +
5549 +#define PCI_CONFIG_ADDR(b, s, f, o) \
5550 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
5551 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
5552 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
5553 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
5554 +
5555 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
5556 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
5557 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
5558 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
5559 +
5560 +/* PCIE Config space accessing MACROS */
5561 +
5562 +#define PCIECFG_BUS_SHIFT 24 /* Bus shift */
5563 +#define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */
5564 +#define PCIECFG_FUN_SHIFT 16 /* Function shift */
5565 +#define PCIECFG_OFF_SHIFT 0 /* Register shift */
5566 +
5567 +#define PCIECFG_BUS_MASK 0xff /* Bus mask */
5568 +#define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */
5569 +#define PCIECFG_FUN_MASK 7 /* Function mask */
5570 +#define PCIECFG_OFF_MASK 0x3ff /* Register mask */
5571 +
5572 +#define PCIE_CONFIG_ADDR(b, s, f, o) \
5573 + ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
5574 + | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
5575 + | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
5576 + | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
5577 +
5578 +#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
5579 +#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
5580 +#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
5581 +#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
5582 +
5583 +/* The actual config space */
5584 +
5585 +#define PCI_BAR_MAX 6
5586 +
5587 +#define PCI_ROM_BAR 8
5588 +
5589 +#define PCR_RSVDA_MAX 2
5590 +
5591 +/* Bits in PCI bars' flags */
5592 +
5593 +#define PCIBAR_FLAGS 0xf
5594 +#define PCIBAR_IO 0x1
5595 +#define PCIBAR_MEM1M 0x2
5596 +#define PCIBAR_MEM64 0x4
5597 +#define PCIBAR_PREFETCH 0x8
5598 +#define PCIBAR_MEM32_MASK 0xFFFFFF80
5599 +
5600 +/* pci config status reg has a bit to indicate that capability ptr is present */
5601 +
5602 +#define PCI_CAPPTR_PRESENT 0x0010
5603 +
5604 +typedef struct _pci_config_regs {
5605 + unsigned short vendor;
5606 + unsigned short device;
5607 + unsigned short command;
5608 + unsigned short status;
5609 + unsigned char rev_id;
5610 + unsigned char prog_if;
5611 + unsigned char sub_class;
5612 + unsigned char base_class;
5613 + unsigned char cache_line_size;
5614 + unsigned char latency_timer;
5615 + unsigned char header_type;
5616 + unsigned char bist;
5617 + unsigned long base[PCI_BAR_MAX];
5618 + unsigned long cardbus_cis;
5619 + unsigned short subsys_vendor;
5620 + unsigned short subsys_id;
5621 + unsigned long baserom;
5622 + unsigned long rsvd_a[PCR_RSVDA_MAX];
5623 + unsigned char int_line;
5624 + unsigned char int_pin;
5625 + unsigned char min_gnt;
5626 + unsigned char max_lat;
5627 + unsigned char dev_dep[192];
5628 +} pci_config_regs;
5629 +
5630 +#define SZPCR (sizeof (pci_config_regs))
5631 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
5632 +
5633 +/* A structure for the config registers is nice, but in most
5634 + * systems the config space is not memory mapped, so we need
5635 + * filed offsetts. :-(
5636 + */
5637 +#define PCI_CFG_VID 0
5638 +#define PCI_CFG_DID 2
5639 +#define PCI_CFG_CMD 4
5640 +#define PCI_CFG_STAT 6
5641 +#define PCI_CFG_REV 8
5642 +#define PCI_CFG_PROGIF 9
5643 +#define PCI_CFG_SUBCL 0xa
5644 +#define PCI_CFG_BASECL 0xb
5645 +#define PCI_CFG_CLSZ 0xc
5646 +#define PCI_CFG_LATTIM 0xd
5647 +#define PCI_CFG_HDR 0xe
5648 +#define PCI_CFG_BIST 0xf
5649 +#define PCI_CFG_BAR0 0x10
5650 +#define PCI_CFG_BAR1 0x14
5651 +#define PCI_CFG_BAR2 0x18
5652 +#define PCI_CFG_BAR3 0x1c
5653 +#define PCI_CFG_BAR4 0x20
5654 +#define PCI_CFG_BAR5 0x24
5655 +#define PCI_CFG_CIS 0x28
5656 +#define PCI_CFG_SVID 0x2c
5657 +#define PCI_CFG_SSID 0x2e
5658 +#define PCI_CFG_ROMBAR 0x30
5659 +#define PCI_CFG_CAPPTR 0x34
5660 +#define PCI_CFG_INT 0x3c
5661 +#define PCI_CFG_PIN 0x3d
5662 +#define PCI_CFG_MINGNT 0x3e
5663 +#define PCI_CFG_MAXLAT 0x3f
5664 +
5665 +#ifdef __NetBSD__
5666 +#undef PCI_CLASS_DISPLAY
5667 +#undef PCI_CLASS_MEMORY
5668 +#undef PCI_CLASS_BRIDGE
5669 +#undef PCI_CLASS_INPUT
5670 +#undef PCI_CLASS_DOCK
5671 +#endif /* __NetBSD__ */
5672 +
5673 +/* Classes and subclasses */
5674 +
5675 +typedef enum {
5676 + PCI_CLASS_OLD = 0,
5677 + PCI_CLASS_DASDI,
5678 + PCI_CLASS_NET,
5679 + PCI_CLASS_DISPLAY,
5680 + PCI_CLASS_MMEDIA,
5681 + PCI_CLASS_MEMORY,
5682 + PCI_CLASS_BRIDGE,
5683 + PCI_CLASS_COMM,
5684 + PCI_CLASS_BASE,
5685 + PCI_CLASS_INPUT,
5686 + PCI_CLASS_DOCK,
5687 + PCI_CLASS_CPU,
5688 + PCI_CLASS_SERIAL,
5689 + PCI_CLASS_INTELLIGENT = 0xe,
5690 + PCI_CLASS_SATELLITE,
5691 + PCI_CLASS_CRYPT,
5692 + PCI_CLASS_DSP,
5693 + PCI_CLASS_XOR = 0xfe
5694 +} pci_classes;
5695 +
5696 +typedef enum {
5697 + PCI_DASDI_SCSI,
5698 + PCI_DASDI_IDE,
5699 + PCI_DASDI_FLOPPY,
5700 + PCI_DASDI_IPI,
5701 + PCI_DASDI_RAID,
5702 + PCI_DASDI_OTHER = 0x80
5703 +} pci_dasdi_subclasses;
5704 +
5705 +typedef enum {
5706 + PCI_NET_ETHER,
5707 + PCI_NET_TOKEN,
5708 + PCI_NET_FDDI,
5709 + PCI_NET_ATM,
5710 + PCI_NET_OTHER = 0x80
5711 +} pci_net_subclasses;
5712 +
5713 +typedef enum {
5714 + PCI_DISPLAY_VGA,
5715 + PCI_DISPLAY_XGA,
5716 + PCI_DISPLAY_3D,
5717 + PCI_DISPLAY_OTHER = 0x80
5718 +} pci_display_subclasses;
5719 +
5720 +typedef enum {
5721 + PCI_MMEDIA_VIDEO,
5722 + PCI_MMEDIA_AUDIO,
5723 + PCI_MMEDIA_PHONE,
5724 + PCI_MEDIA_OTHER = 0x80
5725 +} pci_mmedia_subclasses;
5726 +
5727 +typedef enum {
5728 + PCI_MEMORY_RAM,
5729 + PCI_MEMORY_FLASH,
5730 + PCI_MEMORY_OTHER = 0x80
5731 +} pci_memory_subclasses;
5732 +
5733 +typedef enum {
5734 + PCI_BRIDGE_HOST,
5735 + PCI_BRIDGE_ISA,
5736 + PCI_BRIDGE_EISA,
5737 + PCI_BRIDGE_MC,
5738 + PCI_BRIDGE_PCI,
5739 + PCI_BRIDGE_PCMCIA,
5740 + PCI_BRIDGE_NUBUS,
5741 + PCI_BRIDGE_CARDBUS,
5742 + PCI_BRIDGE_RACEWAY,
5743 + PCI_BRIDGE_OTHER = 0x80
5744 +} pci_bridge_subclasses;
5745 +
5746 +typedef enum {
5747 + PCI_COMM_UART,
5748 + PCI_COMM_PARALLEL,
5749 + PCI_COMM_MULTIUART,
5750 + PCI_COMM_MODEM,
5751 + PCI_COMM_OTHER = 0x80
5752 +} pci_comm_subclasses;
5753 +
5754 +typedef enum {
5755 + PCI_BASE_PIC,
5756 + PCI_BASE_DMA,
5757 + PCI_BASE_TIMER,
5758 + PCI_BASE_RTC,
5759 + PCI_BASE_PCI_HOTPLUG,
5760 + PCI_BASE_OTHER = 0x80
5761 +} pci_base_subclasses;
5762 +
5763 +typedef enum {
5764 + PCI_INPUT_KBD,
5765 + PCI_INPUT_PEN,
5766 + PCI_INPUT_MOUSE,
5767 + PCI_INPUT_SCANNER,
5768 + PCI_INPUT_GAMEPORT,
5769 + PCI_INPUT_OTHER = 0x80
5770 +} pci_input_subclasses;
5771 +
5772 +typedef enum {
5773 + PCI_DOCK_GENERIC,
5774 + PCI_DOCK_OTHER = 0x80
5775 +} pci_dock_subclasses;
5776 +
5777 +typedef enum {
5778 + PCI_CPU_386,
5779 + PCI_CPU_486,
5780 + PCI_CPU_PENTIUM,
5781 + PCI_CPU_ALPHA = 0x10,
5782 + PCI_CPU_POWERPC = 0x20,
5783 + PCI_CPU_MIPS = 0x30,
5784 + PCI_CPU_COPROC = 0x40,
5785 + PCI_CPU_OTHER = 0x80
5786 +} pci_cpu_subclasses;
5787 +
5788 +typedef enum {
5789 + PCI_SERIAL_IEEE1394,
5790 + PCI_SERIAL_ACCESS,
5791 + PCI_SERIAL_SSA,
5792 + PCI_SERIAL_USB,
5793 + PCI_SERIAL_FIBER,
5794 + PCI_SERIAL_SMBUS,
5795 + PCI_SERIAL_OTHER = 0x80
5796 +} pci_serial_subclasses;
5797 +
5798 +typedef enum {
5799 + PCI_INTELLIGENT_I2O
5800 +} pci_intelligent_subclasses;
5801 +
5802 +typedef enum {
5803 + PCI_SATELLITE_TV,
5804 + PCI_SATELLITE_AUDIO,
5805 + PCI_SATELLITE_VOICE,
5806 + PCI_SATELLITE_DATA,
5807 + PCI_SATELLITE_OTHER = 0x80
5808 +} pci_satellite_subclasses;
5809 +
5810 +typedef enum {
5811 + PCI_CRYPT_NETWORK,
5812 + PCI_CRYPT_ENTERTAINMENT,
5813 + PCI_CRYPT_OTHER = 0x80
5814 +} pci_crypt_subclasses;
5815 +
5816 +typedef enum {
5817 + PCI_DSP_DPIO,
5818 + PCI_DSP_OTHER = 0x80
5819 +} pci_dsp_subclasses;
5820 +
5821 +typedef enum {
5822 + PCI_XOR_QDMA,
5823 + PCI_XOR_OTHER = 0x80
5824 +} pci_xor_subclasses;
5825 +
5826 +/* Header types */
5827 +typedef enum {
5828 + PCI_HEADER_NORMAL,
5829 + PCI_HEADER_BRIDGE,
5830 + PCI_HEADER_CARDBUS
5831 +} pci_header_types;
5832 +
5833 +
5834 +/* Overlay for a PCI-to-PCI bridge */
5835 +
5836 +#define PPB_RSVDA_MAX 2
5837 +#define PPB_RSVDD_MAX 8
5838 +
5839 +typedef struct _ppb_config_regs {
5840 + unsigned short vendor;
5841 + unsigned short device;
5842 + unsigned short command;
5843 + unsigned short status;
5844 + unsigned char rev_id;
5845 + unsigned char prog_if;
5846 + unsigned char sub_class;
5847 + unsigned char base_class;
5848 + unsigned char cache_line_size;
5849 + unsigned char latency_timer;
5850 + unsigned char header_type;
5851 + unsigned char bist;
5852 + unsigned long rsvd_a[PPB_RSVDA_MAX];
5853 + unsigned char prim_bus;
5854 + unsigned char sec_bus;
5855 + unsigned char sub_bus;
5856 + unsigned char sec_lat;
5857 + unsigned char io_base;
5858 + unsigned char io_lim;
5859 + unsigned short sec_status;
5860 + unsigned short mem_base;
5861 + unsigned short mem_lim;
5862 + unsigned short pf_mem_base;
5863 + unsigned short pf_mem_lim;
5864 + unsigned long pf_mem_base_hi;
5865 + unsigned long pf_mem_lim_hi;
5866 + unsigned short io_base_hi;
5867 + unsigned short io_lim_hi;
5868 + unsigned short subsys_vendor;
5869 + unsigned short subsys_id;
5870 + unsigned long rsvd_b;
5871 + unsigned char rsvd_c;
5872 + unsigned char int_pin;
5873 + unsigned short bridge_ctrl;
5874 + unsigned char chip_ctrl;
5875 + unsigned char diag_ctrl;
5876 + unsigned short arb_ctrl;
5877 + unsigned long rsvd_d[PPB_RSVDD_MAX];
5878 + unsigned char dev_dep[192];
5879 +} ppb_config_regs;
5880 +
5881 +
5882 +/* PCI CAPABILITY DEFINES */
5883 +#define PCI_CAP_POWERMGMTCAP_ID 0x01
5884 +#define PCI_CAP_MSICAP_ID 0x05
5885 +#define PCI_CAP_PCIECAP_ID 0x10
5886 +
5887 +/* Data structure to define the Message Signalled Interrupt facility
5888 + * Valid for PCI and PCIE configurations
5889 + */
5890 +typedef struct _pciconfig_cap_msi {
5891 + unsigned char capID;
5892 + unsigned char nextptr;
5893 + unsigned short msgctrl;
5894 + unsigned int msgaddr;
5895 +} pciconfig_cap_msi;
5896 +
5897 +/* Data structure to define the Power managment facility
5898 + * Valid for PCI and PCIE configurations
5899 + */
5900 +typedef struct _pciconfig_cap_pwrmgmt {
5901 + unsigned char capID;
5902 + unsigned char nextptr;
5903 + unsigned short pme_cap;
5904 + unsigned short pme_sts_ctrl;
5905 + unsigned char pme_bridge_ext;
5906 + unsigned char data;
5907 +} pciconfig_cap_pwrmgmt;
5908 +
5909 +/* Data structure to define the PCIE capability */
5910 +typedef struct _pciconfig_cap_pcie {
5911 + unsigned char capID;
5912 + unsigned char nextptr;
5913 + unsigned short pcie_cap;
5914 + unsigned int dev_cap;
5915 + unsigned short dev_ctrl;
5916 + unsigned short dev_status;
5917 + unsigned int link_cap;
5918 + unsigned short link_ctrl;
5919 + unsigned short link_status;
5920 +} pciconfig_cap_pcie;
5921 +
5922 +/* PCIE Enhanced CAPABILITY DEFINES */
5923 +#define PCIE_EXTCFG_OFFSET 0x100
5924 +#define PCIE_ADVERRREP_CAPID 0x0001
5925 +#define PCIE_VC_CAPID 0x0002
5926 +#define PCIE_DEVSNUM_CAPID 0x0003
5927 +#define PCIE_PWRBUDGET_CAPID 0x0004
5928 +
5929 +/* Header to define the PCIE specific capabilities in the extended config space */
5930 +typedef struct _pcie_enhanced_caphdr {
5931 + unsigned short capID;
5932 + unsigned short cap_ver : 4;
5933 + unsigned short next_ptr : 12;
5934 +} pcie_enhanced_caphdr;
5935 +
5936 +
5937 +/* Everything below is BRCM HND proprietary */
5938 +
5939 +
5940 +/* Brcm PCI configuration registers */
5941 +#define cap_list rsvd_a[0]
5942 +#define bar0_window dev_dep[0x80 - 0x40]
5943 +#define bar1_window dev_dep[0x84 - 0x40]
5944 +#define sprom_control dev_dep[0x88 - 0x40]
5945 +
5946 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
5947 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
5948 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
5949 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
5950 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
5951 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
5952 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
5953 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
5954 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address */
5955 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
5956 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
5957 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
5958 +
5959 +#define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */
5960 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
5961 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
5962 +#define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the
5963 + * 8KB window, so their address is the "regular"
5964 + * address plus 4K
5965 + */
5966 +#define PCI_BAR0_WINSZ 8192 /* bar0 window size */
5967 +
5968 +/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
5969 +#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */
5970 +#define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */
5971 +#define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */
5972 +
5973 +/* PCI_INT_STATUS */
5974 +#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
5975 +
5976 +/* PCI_INT_MASK */
5977 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
5978 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
5979 +#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
5980 +
5981 +/* PCI_SPROM_CONTROL */
5982 +#define SPROM_SZ_MSK 0x02 /* SPROM Size Mask */
5983 +#define SPROM_LOCKED 0x08 /* SPROM Locked */
5984 +#define SPROM_BLANK 0x04 /* indicating a blank SPROM */
5985 +#define SPROM_WRITEEN 0x10 /* SPROM write enable */
5986 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
5987 +#define SPROM_OTPIN_USE 0x80 /* device OTP In use */
5988 +
5989 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
5990 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
5991 +
5992 +/* PCI_CFG_CMD_STAT */
5993 +#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
5994 +
5995 +#endif /* _h_pcicfg_ */
5996 diff -urN linux.old/arch/mips/bcm947xx/include/sbchipc.h linux.dev/arch/mips/bcm947xx/include/sbchipc.h
5997 --- linux.old/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
5998 +++ linux.dev/arch/mips/bcm947xx/include/sbchipc.h 2006-10-02 21:19:59.000000000 +0200
5999 @@ -0,0 +1,516 @@
6000 +/*
6001 + * SiliconBackplane Chipcommon core hardware definitions.
6002 + *
6003 + * The chipcommon core provides chip identification, SB control,
6004 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
6005 + * gpio interface, extbus, and support for serial and parallel flashes.
6006 + *
6007 + * $Id: sbchipc.h,v 1.1.1.14 2006/04/15 01:29:08 michael Exp $
6008 + * Copyright 2006, Broadcom Corporation
6009 + * All Rights Reserved.
6010 + *
6011 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6012 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6013 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6014 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6015 + *
6016 + */
6017 +
6018 +#ifndef _SBCHIPC_H
6019 +#define _SBCHIPC_H
6020 +
6021 +
6022 +#ifndef _LANGUAGE_ASSEMBLY
6023 +
6024 +/* cpp contortions to concatenate w/arg prescan */
6025 +#ifndef PAD
6026 +#define _PADLINE(line) pad ## line
6027 +#define _XSTR(line) _PADLINE(line)
6028 +#define PAD _XSTR(__LINE__)
6029 +#endif /* PAD */
6030 +
6031 +typedef volatile struct {
6032 + uint32 chipid; /* 0x0 */
6033 + uint32 capabilities;
6034 + uint32 corecontrol; /* corerev >= 1 */
6035 + uint32 bist;
6036 +
6037 + /* OTP */
6038 + uint32 otpstatus; /* 0x10, corerev >= 10 */
6039 + uint32 otpcontrol;
6040 + uint32 otpprog;
6041 + uint32 PAD;
6042 +
6043 + /* Interrupt control */
6044 + uint32 intstatus; /* 0x20 */
6045 + uint32 intmask;
6046 + uint32 chipcontrol; /* 0x28, rev >= 11 */
6047 + uint32 chipstatus; /* 0x2c, rev >= 11 */
6048 +
6049 + /* Jtag Master */
6050 + uint32 jtagcmd; /* 0x30, rev >= 10 */
6051 + uint32 jtagir;
6052 + uint32 jtagdr;
6053 + uint32 jtagctrl;
6054 +
6055 + /* serial flash interface registers */
6056 + uint32 flashcontrol; /* 0x40 */
6057 + uint32 flashaddress;
6058 + uint32 flashdata;
6059 + uint32 PAD[1];
6060 +
6061 + /* Silicon backplane configuration broadcast control */
6062 + uint32 broadcastaddress; /* 0x50 */
6063 + uint32 broadcastdata;
6064 + uint32 PAD[2];
6065 +
6066 + /* gpio - cleared only by power-on-reset */
6067 + uint32 gpioin; /* 0x60 */
6068 + uint32 gpioout;
6069 + uint32 gpioouten;
6070 + uint32 gpiocontrol;
6071 + uint32 gpiointpolarity;
6072 + uint32 gpiointmask;
6073 + uint32 PAD[2];
6074 +
6075 + /* Watchdog timer */
6076 + uint32 watchdog; /* 0x80 */
6077 + uint32 PAD[1];
6078 +
6079 + /* GPIO based LED powersave registers corerev >= 16 */
6080 + uint32 gpiotimerval; /* 0x88 */
6081 + uint32 gpiotimeroutmask;
6082 +
6083 + /* clock control */
6084 + uint32 clockcontrol_n; /* 0x90 */
6085 + uint32 clockcontrol_sb; /* aka m0 */
6086 + uint32 clockcontrol_pci; /* aka m1 */
6087 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
6088 + uint32 clockcontrol_m3; /* cpu */
6089 + uint32 clkdiv; /* corerev >= 3 */
6090 + uint32 PAD[2];
6091 +
6092 + /* pll delay registers (corerev >= 4) */
6093 + uint32 pll_on_delay; /* 0xb0 */
6094 + uint32 fref_sel_delay;
6095 + uint32 slow_clk_ctl; /* 5 < corerev < 10 */
6096 + uint32 PAD[1];
6097 +
6098 + /* Instaclock registers (corerev >= 10) */
6099 + uint32 system_clk_ctl; /* 0xc0 */
6100 + uint32 clkstatestretch;
6101 + uint32 PAD[14];
6102 +
6103 + /* ExtBus control registers (corerev >= 3) */
6104 + uint32 pcmcia_config; /* 0x100 */
6105 + uint32 pcmcia_memwait;
6106 + uint32 pcmcia_attrwait;
6107 + uint32 pcmcia_iowait;
6108 + uint32 ide_config;
6109 + uint32 ide_memwait;
6110 + uint32 ide_attrwait;
6111 + uint32 ide_iowait;
6112 + uint32 prog_config;
6113 + uint32 prog_waitcount;
6114 + uint32 flash_config;
6115 + uint32 flash_waitcount;
6116 + uint32 PAD[44];
6117 +
6118 + /* Clock control and hardware workarounds */
6119 + uint32 clk_ctl_st;
6120 + uint32 hw_war;
6121 + uint32 PAD[70];
6122 +
6123 + /* uarts */
6124 + uint8 uart0data; /* 0x300 */
6125 + uint8 uart0imr;
6126 + uint8 uart0fcr;
6127 + uint8 uart0lcr;
6128 + uint8 uart0mcr;
6129 + uint8 uart0lsr;
6130 + uint8 uart0msr;
6131 + uint8 uart0scratch;
6132 + uint8 PAD[248]; /* corerev >= 1 */
6133 +
6134 + uint8 uart1data; /* 0x400 */
6135 + uint8 uart1imr;
6136 + uint8 uart1fcr;
6137 + uint8 uart1lcr;
6138 + uint8 uart1mcr;
6139 + uint8 uart1lsr;
6140 + uint8 uart1msr;
6141 + uint8 uart1scratch;
6142 +} chipcregs_t;
6143 +
6144 +#endif /* _LANGUAGE_ASSEMBLY */
6145 +
6146 +#define CC_CHIPID 0
6147 +#define CC_CAPABILITIES 4
6148 +#define CC_JTAGCMD 0x30
6149 +#define CC_JTAGIR 0x34
6150 +#define CC_JTAGDR 0x38
6151 +#define CC_JTAGCTRL 0x3c
6152 +#define CC_WATCHDOG 0x80
6153 +#define CC_CLKC_N 0x90
6154 +#define CC_CLKC_M0 0x94
6155 +#define CC_CLKC_M1 0x98
6156 +#define CC_CLKC_M2 0x9c
6157 +#define CC_CLKC_M3 0xa0
6158 +#define CC_CLKDIV 0xa4
6159 +#define CC_SYS_CLK_CTL 0xc0
6160 +#define CC_OTP 0x800
6161 +
6162 +/* chipid */
6163 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
6164 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
6165 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
6166 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
6167 +#define CID_PKG_SHIFT 20 /* Package Option shift */
6168 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
6169 +#define CID_CC_SHIFT 24
6170 +
6171 +/* capabilities */
6172 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
6173 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
6174 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
6175 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
6176 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
6177 +#define CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
6178 +#define CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */
6179 +#define CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */
6180 +#define CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */
6181 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
6182 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
6183 +#define CAP_PWR_CTL 0x00040000 /* Power control */
6184 +#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
6185 +#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
6186 +#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
6187 +#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
6188 +#define CAP_ROM 0x00800000 /* Internal boot rom active */
6189 +#define CAP_BKPLN64 0x08000000 /* 64-bit backplane */
6190 +
6191 +/* PLL type */
6192 +#define PLL_NONE 0x00000000
6193 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
6194 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
6195 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
6196 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
6197 +#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
6198 +#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
6199 +#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
6200 +
6201 +/* corecontrol */
6202 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
6203 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
6204 +
6205 +/* chipcontrol */
6206 +#define CHIPCTRL_4321A0_DEFAULT 0x3a4
6207 +#define CHIPCTRL_4321A1_DEFAULT 0x0a4
6208 +
6209 +/* Fields in the otpstatus register */
6210 +#define OTPS_PROGFAIL 0x80000000
6211 +#define OTPS_PROTECT 0x00000007
6212 +#define OTPS_HW_PROTECT 0x00000001
6213 +#define OTPS_SW_PROTECT 0x00000002
6214 +#define OTPS_CID_PROTECT 0x00000004
6215 +
6216 +/* Fields in the otpcontrol register */
6217 +#define OTPC_RECWAIT 0xff000000
6218 +#define OTPC_PROGWAIT 0x00ffff00
6219 +#define OTPC_PRW_SHIFT 8
6220 +#define OTPC_MAXFAIL 0x00000038
6221 +#define OTPC_VSEL 0x00000006
6222 +#define OTPC_SELVL 0x00000001
6223 +
6224 +/* Fields in otpprog */
6225 +#define OTPP_COL_MASK 0x000000ff
6226 +#define OTPP_ROW_MASK 0x0000ff00
6227 +#define OTPP_ROW_SHIFT 8
6228 +#define OTPP_READERR 0x10000000
6229 +#define OTPP_VALUE 0x20000000
6230 +#define OTPP_VALUE_SHIFT 29
6231 +#define OTPP_READ 0x40000000
6232 +#define OTPP_START 0x80000000
6233 +#define OTPP_BUSY 0x80000000
6234 +
6235 +/* jtagcmd */
6236 +#define JCMD_START 0x80000000
6237 +#define JCMD_BUSY 0x80000000
6238 +#define JCMD_PAUSE 0x40000000
6239 +#define JCMD0_ACC_MASK 0x0000f000
6240 +#define JCMD0_ACC_IRDR 0x00000000
6241 +#define JCMD0_ACC_DR 0x00001000
6242 +#define JCMD0_ACC_IR 0x00002000
6243 +#define JCMD0_ACC_RESET 0x00003000
6244 +#define JCMD0_ACC_IRPDR 0x00004000
6245 +#define JCMD0_ACC_PDR 0x00005000
6246 +#define JCMD0_IRW_MASK 0x00000f00
6247 +#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
6248 +#define JCMD_ACC_IRDR 0x00000000
6249 +#define JCMD_ACC_DR 0x00010000
6250 +#define JCMD_ACC_IR 0x00020000
6251 +#define JCMD_ACC_RESET 0x00030000
6252 +#define JCMD_ACC_IRPDR 0x00040000
6253 +#define JCMD_ACC_PDR 0x00050000
6254 +#define JCMD_IRW_MASK 0x00001f00
6255 +#define JCMD_IRW_SHIFT 8
6256 +#define JCMD_DRW_MASK 0x0000003f
6257 +
6258 +/* jtagctrl */
6259 +#define JCTRL_FORCE_CLK 4 /* Force clock */
6260 +#define JCTRL_EXT_EN 2 /* Enable external targets */
6261 +#define JCTRL_EN 1 /* Enable Jtag master */
6262 +
6263 +/* Fields in clkdiv */
6264 +#define CLKD_SFLASH 0x0f000000
6265 +#define CLKD_SFLASH_SHIFT 24
6266 +#define CLKD_OTP 0x000f0000
6267 +#define CLKD_OTP_SHIFT 16
6268 +#define CLKD_JTAG 0x00000f00
6269 +#define CLKD_JTAG_SHIFT 8
6270 +#define CLKD_UART 0x000000ff
6271 +
6272 +/* intstatus/intmask */
6273 +#define CI_GPIO 0x00000001 /* gpio intr */
6274 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
6275 +#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
6276 +
6277 +/* slow_clk_ctl */
6278 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
6279 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
6280 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
6281 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
6282 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
6283 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled,
6284 + * 0: LPO is enabled
6285 + */
6286 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock,
6287 + * 0: power logic control
6288 + */
6289 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors
6290 + * PLL clock disable requests from core
6291 + */
6292 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't
6293 + * disable crystal when appropriate
6294 + */
6295 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
6296 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
6297 +#define SCC_CD_SHIFT 16
6298 +
6299 +/* system_clk_ctl */
6300 +#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
6301 +#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
6302 +#define SYCC_FP 0x00000004 /* ForcePLLOn */
6303 +#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
6304 +#define SYCC_HR 0x00000010 /* Force HT */
6305 +#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
6306 +#define SYCC_CD_SHIFT 16
6307 +
6308 +/* gpiotimerval */
6309 +#define GPIO_ONTIME_SHIFT 16
6310 +
6311 +/* clockcontrol_n */
6312 +#define CN_N1_MASK 0x3f /* n1 control */
6313 +#define CN_N2_MASK 0x3f00 /* n2 control */
6314 +#define CN_N2_SHIFT 8
6315 +#define CN_PLLC_MASK 0xf0000 /* pll control */
6316 +#define CN_PLLC_SHIFT 16
6317 +
6318 +/* clockcontrol_sb/pci/uart */
6319 +#define CC_M1_MASK 0x3f /* m1 control */
6320 +#define CC_M2_MASK 0x3f00 /* m2 control */
6321 +#define CC_M2_SHIFT 8
6322 +#define CC_M3_MASK 0x3f0000 /* m3 control */
6323 +#define CC_M3_SHIFT 16
6324 +#define CC_MC_MASK 0x1f000000 /* mux control */
6325 +#define CC_MC_SHIFT 24
6326 +
6327 +/* N3M Clock control magic field values */
6328 +#define CC_F6_2 0x02 /* A factor of 2 in */
6329 +#define CC_F6_3 0x03 /* 6-bit fields like */
6330 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
6331 +#define CC_F6_5 0x09
6332 +#define CC_F6_6 0x11
6333 +#define CC_F6_7 0x21
6334 +
6335 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
6336 +
6337 +#define CC_MC_BYPASS 0x08
6338 +#define CC_MC_M1 0x04
6339 +#define CC_MC_M1M2 0x02
6340 +#define CC_MC_M1M2M3 0x01
6341 +#define CC_MC_M1M3 0x11
6342 +
6343 +/* Type 2 Clock control magic field values */
6344 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
6345 +#define CC_T2M2_BIAS 3 /* m2 bias */
6346 +
6347 +#define CC_T2MC_M1BYP 1
6348 +#define CC_T2MC_M2BYP 2
6349 +#define CC_T2MC_M3BYP 4
6350 +
6351 +/* Type 6 Clock control magic field values */
6352 +#define CC_T6_MMASK 1 /* bits of interest in m */
6353 +#define CC_T6_M0 120000000 /* sb clock for m = 0 */
6354 +#define CC_T6_M1 100000000 /* sb clock for m = 1 */
6355 +#define SB2MIPS_T6(sb) (2 * (sb))
6356 +
6357 +/* Common clock base */
6358 +#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
6359 +#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
6360 +
6361 +/* Clock control values for 200Mhz in 5350 */
6362 +#define CLKC_5350_N 0x0311
6363 +#define CLKC_5350_M 0x04020009
6364 +
6365 +/* Flash types in the chipcommon capabilities register */
6366 +#define FLASH_NONE 0x000 /* No flash */
6367 +#define SFLASH_ST 0x100 /* ST serial flash */
6368 +#define SFLASH_AT 0x200 /* Atmel serial flash */
6369 +#define PFLASH 0x700 /* Parallel flash */
6370 +
6371 +/* Bits in the ExtBus config registers */
6372 +#define CC_CFG_EN 0x0001 /* Enable */
6373 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
6374 +#define CC_CFG_EM_ASYNC 0x0000 /* Async/Parallel flash */
6375 +#define CC_CFG_EM_SYNC 0x0002 /* Synchronous */
6376 +#define CC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */
6377 +#define CC_CFG_EM_IDE 0x0006 /* IDE */
6378 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
6379 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
6380 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
6381 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
6382 +
6383 +/* ExtBus address space */
6384 +#define CC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */
6385 +#define CC_EB_PCMCIA_MEM 0x1a000000 /* PCMCIA 0 memory base address */
6386 +#define CC_EB_PCMCIA_IO 0x1a200000 /* PCMCIA 0 I/O base address */
6387 +#define CC_EB_PCMCIA_CFG 0x1a400000 /* PCMCIA 0 config base address */
6388 +#define CC_EB_IDE 0x1a800000 /* IDE memory base */
6389 +#define CC_EB_PCMCIA1_MEM 0x1a800000 /* PCMCIA 1 memory base address */
6390 +#define CC_EB_PCMCIA1_IO 0x1aa00000 /* PCMCIA 1 I/O base address */
6391 +#define CC_EB_PCMCIA1_CFG 0x1ac00000 /* PCMCIA 1 config base address */
6392 +#define CC_EB_PROGIF 0x1b000000 /* ProgIF Async/Sync base address */
6393 +
6394 +
6395 +/* Start/busy bit in flashcontrol */
6396 +#define SFLASH_OPCODE 0x000000ff
6397 +#define SFLASH_ACTION 0x00000700
6398 +#define SFLASH_START 0x80000000
6399 +#define SFLASH_BUSY SFLASH_START
6400 +
6401 +/* flashcontrol action codes */
6402 +#define SFLASH_ACT_OPONLY 0x0000 /* Issue opcode only */
6403 +#define SFLASH_ACT_OP1D 0x0100 /* opcode + 1 data byte */
6404 +#define SFLASH_ACT_OP3A 0x0200 /* opcode + 3 address bytes */
6405 +#define SFLASH_ACT_OP3A1D 0x0300 /* opcode + 3 addres & 1 data bytes */
6406 +#define SFLASH_ACT_OP3A4D 0x0400 /* opcode + 3 addres & 4 data bytes */
6407 +#define SFLASH_ACT_OP3A4X4D 0x0500 /* opcode + 3 addres, 4 don't care & 4 data bytes */
6408 +#define SFLASH_ACT_OP3A1X4D 0x0700 /* opcode + 3 addres, 1 don't care & 4 data bytes */
6409 +
6410 +/* flashcontrol action+opcodes for ST flashes */
6411 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
6412 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
6413 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
6414 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
6415 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
6416 +#define SFLASH_ST_PP 0x0302 /* Page Program */
6417 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
6418 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
6419 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
6420 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
6421 +
6422 +/* Status register bits for ST flashes */
6423 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
6424 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
6425 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
6426 +#define SFLASH_ST_BP_SHIFT 2
6427 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
6428 +
6429 +/* flashcontrol action+opcodes for Atmel flashes */
6430 +#define SFLASH_AT_READ 0x07e8
6431 +#define SFLASH_AT_PAGE_READ 0x07d2
6432 +#define SFLASH_AT_BUF1_READ
6433 +#define SFLASH_AT_BUF2_READ
6434 +#define SFLASH_AT_STATUS 0x01d7
6435 +#define SFLASH_AT_BUF1_WRITE 0x0384
6436 +#define SFLASH_AT_BUF2_WRITE 0x0387
6437 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
6438 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
6439 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
6440 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
6441 +#define SFLASH_AT_PAGE_ERASE 0x0281
6442 +#define SFLASH_AT_BLOCK_ERASE 0x0250
6443 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
6444 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
6445 +#define SFLASH_AT_BUF1_LOAD 0x0253
6446 +#define SFLASH_AT_BUF2_LOAD 0x0255
6447 +#define SFLASH_AT_BUF1_COMPARE 0x0260
6448 +#define SFLASH_AT_BUF2_COMPARE 0x0261
6449 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
6450 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
6451 +
6452 +/* Status register bits for Atmel flashes */
6453 +#define SFLASH_AT_READY 0x80
6454 +#define SFLASH_AT_MISMATCH 0x40
6455 +#define SFLASH_AT_ID_MASK 0x38
6456 +#define SFLASH_AT_ID_SHIFT 3
6457 +
6458 +/* OTP regions */
6459 +#define OTP_HW_REGION OTPS_HW_PROTECT
6460 +#define OTP_SW_REGION OTPS_SW_PROTECT
6461 +#define OTP_CID_REGION OTPS_CID_PROTECT
6462 +
6463 +/* OTP regions (Byte offsets from otp size) */
6464 +#define OTP_SWLIM_OFF (-8)
6465 +#define OTP_CIDBASE_OFF 0
6466 +#define OTP_CIDLIM_OFF 8
6467 +
6468 +/* Predefined OTP words (Word offset from otp size) */
6469 +#define OTP_BOUNDARY_OFF (-4)
6470 +#define OTP_HWSIGN_OFF (-3)
6471 +#define OTP_SWSIGN_OFF (-2)
6472 +#define OTP_CIDSIGN_OFF (-1)
6473 +
6474 +#define OTP_CID_OFF 0
6475 +#define OTP_PKG_OFF 1
6476 +#define OTP_FID_OFF 2
6477 +#define OTP_RSV_OFF 3
6478 +#define OTP_LIM_OFF 4
6479 +
6480 +#define OTP_SIGNATURE 0x578a
6481 +#define OTP_MAGIC 0x4e56
6482 +
6483 +/*
6484 + * These are the UART port assignments, expressed as offsets from the base
6485 + * register. These assignments should hold for any serial port based on
6486 + * a 8250, 16450, or 16550(A).
6487 + */
6488 +
6489 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
6490 +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
6491 +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
6492 +#define UART_IER 1 /* In/Out: Interrupt Enable Register (DLAB=0) */
6493 +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
6494 +#define UART_IIR 2 /* In: Interrupt Identity Register */
6495 +#define UART_FCR 2 /* Out: FIFO Control Register */
6496 +#define UART_LCR 3 /* Out: Line Control Register */
6497 +#define UART_MCR 4 /* Out: Modem Control Register */
6498 +#define UART_LSR 5 /* In: Line Status Register */
6499 +#define UART_MSR 6 /* In: Modem Status Register */
6500 +#define UART_SCR 7 /* I/O: Scratch Register */
6501 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
6502 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
6503 +#define UART_MCR_OUT2 0x08 /* MCR GPIO out 2 */
6504 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
6505 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
6506 +#define UART_LSR_RXRDY 0x01 /* Receiver ready */
6507 +#define UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */
6508 +
6509 +/* Interrupt Enable Register (IER) bits */
6510 +#define UART_IER_EDSSI 8 /* enable modem status interrupt */
6511 +#define UART_IER_ELSI 4 /* enable receiver line status interrupt */
6512 +#define UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */
6513 +#define UART_IER_ERBFI 1 /* enable data available interrupt */
6514 +
6515 +#endif /* _SBCHIPC_H */
6516 diff -urN linux.old/arch/mips/bcm947xx/include/sbconfig.h linux.dev/arch/mips/bcm947xx/include/sbconfig.h
6517 --- linux.old/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
6518 +++ linux.dev/arch/mips/bcm947xx/include/sbconfig.h 2006-10-02 21:19:59.000000000 +0200
6519 @@ -0,0 +1,369 @@
6520 +/*
6521 + * Broadcom SiliconBackplane hardware register definitions.
6522 + *
6523 + * Copyright 2006, Broadcom Corporation
6524 + * All Rights Reserved.
6525 + *
6526 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6527 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6528 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6529 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6530 + *
6531 + * $Id: sbconfig.h,v 1.1.1.11 2006/02/27 03:43:16 honor Exp $
6532 + */
6533 +
6534 +#ifndef _SBCONFIG_H
6535 +#define _SBCONFIG_H
6536 +
6537 +/* cpp contortions to concatenate w/arg prescan */
6538 +#ifndef PAD
6539 +#define _PADLINE(line) pad ## line
6540 +#define _XSTR(line) _PADLINE(line)
6541 +#define PAD _XSTR(__LINE__)
6542 +#endif
6543 +
6544 +/*
6545 + * SiliconBackplane Address Map.
6546 + * All regions may not exist on all chips.
6547 + */
6548 +#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
6549 +#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
6550 +#define SB_PCI_MEM_SZ (64 * 1024 * 1024)
6551 +#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
6552 +#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
6553 +#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
6554 +#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
6555 +
6556 +#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
6557 +#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
6558 +
6559 +#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
6560 +#define SB_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
6561 +#define SB_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
6562 +
6563 +#define SB_ROM 0x20000000 /* ARM ROM */
6564 +#define SB_SRAM2 0x80000000 /* ARM SRAM Region 2 */
6565 +#define SB_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */
6566 +#define SB_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */
6567 +
6568 +#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
6569 +#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
6570 +#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2
6571 + * (2 ZettaBytes), low 32 bits
6572 + */
6573 +#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2
6574 + * (2 ZettaBytes), high 32 bits
6575 + */
6576 +#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
6577 +#define SB_LED (SB_EXTIF_BASE + 0x00900000)
6578 +
6579 +
6580 +/* enumeration space related defs */
6581 +#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
6582 +#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
6583 +#define SB_MAXFUNCS 4 /* max. # functions per core */
6584 +#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
6585 +#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
6586 +
6587 +/* mips address */
6588 +#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
6589 +
6590 +/*
6591 + * Sonics Configuration Space Registers.
6592 + */
6593 +#define SBIPSFLAG 0x08
6594 +#define SBTPSFLAG 0x18
6595 +#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
6596 +#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
6597 +#define SBADMATCH3 0x60
6598 +#define SBADMATCH2 0x68
6599 +#define SBADMATCH1 0x70
6600 +#define SBIMSTATE 0x90
6601 +#define SBINTVEC 0x94
6602 +#define SBTMSTATELOW 0x98
6603 +#define SBTMSTATEHIGH 0x9c
6604 +#define SBBWA0 0xa0
6605 +#define SBIMCONFIGLOW 0xa8
6606 +#define SBIMCONFIGHIGH 0xac
6607 +#define SBADMATCH0 0xb0
6608 +#define SBTMCONFIGLOW 0xb8
6609 +#define SBTMCONFIGHIGH 0xbc
6610 +#define SBBCONFIG 0xc0
6611 +#define SBBSTATE 0xc8
6612 +#define SBACTCNFG 0xd8
6613 +#define SBFLAGST 0xe8
6614 +#define SBIDLOW 0xf8
6615 +#define SBIDHIGH 0xfc
6616 +
6617 +/* All the previous registers are above SBCONFIGOFF, but with Sonics 2.3, we have
6618 + * a few registers *below* that line. I think it would be very confusing to try
6619 + * and change the value of SBCONFIGOFF, so I'm definig them as absolute offsets here,
6620 + */
6621 +
6622 +#define SBIMERRLOGA 0xea8
6623 +#define SBIMERRLOG 0xeb0
6624 +#define SBTMPORTCONNID0 0xed8
6625 +#define SBTMPORTLOCK0 0xef8
6626 +
6627 +#ifndef _LANGUAGE_ASSEMBLY
6628 +
6629 +typedef volatile struct _sbconfig {
6630 + uint32 PAD[2];
6631 + uint32 sbipsflag; /* initiator port ocp slave flag */
6632 + uint32 PAD[3];
6633 + uint32 sbtpsflag; /* target port ocp slave flag */
6634 + uint32 PAD[11];
6635 + uint32 sbtmerrloga; /* (sonics >= 2.3) */
6636 + uint32 PAD;
6637 + uint32 sbtmerrlog; /* (sonics >= 2.3) */
6638 + uint32 PAD[3];
6639 + uint32 sbadmatch3; /* address match3 */
6640 + uint32 PAD;
6641 + uint32 sbadmatch2; /* address match2 */
6642 + uint32 PAD;
6643 + uint32 sbadmatch1; /* address match1 */
6644 + uint32 PAD[7];
6645 + uint32 sbimstate; /* initiator agent state */
6646 + uint32 sbintvec; /* interrupt mask */
6647 + uint32 sbtmstatelow; /* target state */
6648 + uint32 sbtmstatehigh; /* target state */
6649 + uint32 sbbwa0; /* bandwidth allocation table0 */
6650 + uint32 PAD;
6651 + uint32 sbimconfiglow; /* initiator configuration */
6652 + uint32 sbimconfighigh; /* initiator configuration */
6653 + uint32 sbadmatch0; /* address match0 */
6654 + uint32 PAD;
6655 + uint32 sbtmconfiglow; /* target configuration */
6656 + uint32 sbtmconfighigh; /* target configuration */
6657 + uint32 sbbconfig; /* broadcast configuration */
6658 + uint32 PAD;
6659 + uint32 sbbstate; /* broadcast state */
6660 + uint32 PAD[3];
6661 + uint32 sbactcnfg; /* activate configuration */
6662 + uint32 PAD[3];
6663 + uint32 sbflagst; /* current sbflags */
6664 + uint32 PAD[3];
6665 + uint32 sbidlow; /* identification */
6666 + uint32 sbidhigh; /* identification */
6667 +} sbconfig_t;
6668 +
6669 +#endif /* _LANGUAGE_ASSEMBLY */
6670 +
6671 +/* sbipsflag */
6672 +#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
6673 +#define SBIPS_INT1_SHIFT 0
6674 +#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
6675 +#define SBIPS_INT2_SHIFT 8
6676 +#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
6677 +#define SBIPS_INT3_SHIFT 16
6678 +#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
6679 +#define SBIPS_INT4_SHIFT 24
6680 +
6681 +/* sbtpsflag */
6682 +#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
6683 +#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
6684 +
6685 +/* sbtmerrlog */
6686 +#define SBTMEL_CM 0x00000007 /* command */
6687 +#define SBTMEL_CI 0x0000ff00 /* connection id */
6688 +#define SBTMEL_EC 0x0f000000 /* error code */
6689 +#define SBTMEL_ME 0x80000000 /* multiple error */
6690 +
6691 +/* sbimstate */
6692 +#define SBIM_PC 0xf /* pipecount */
6693 +#define SBIM_AP_MASK 0x30 /* arbitration policy */
6694 +#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
6695 +#define SBIM_AP_TS 0x10 /* use timesliaces only */
6696 +#define SBIM_AP_TK 0x20 /* use token only */
6697 +#define SBIM_AP_RSV 0x30 /* reserved */
6698 +#define SBIM_IBE 0x20000 /* inbanderror */
6699 +#define SBIM_TO 0x40000 /* timeout */
6700 +#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
6701 +#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
6702 +
6703 +/* sbtmstatelow */
6704 +#define SBTML_RESET 0x1 /* reset */
6705 +#define SBTML_REJ_MASK 0x6 /* reject */
6706 +#define SBTML_REJ_SHIFT 1
6707 +#define SBTML_CLK 0x10000 /* clock enable */
6708 +#define SBTML_FGC 0x20000 /* force gated clocks on */
6709 +#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
6710 +#define SBTML_PE 0x40000000 /* pme enable */
6711 +#define SBTML_BE 0x80000000 /* bist enable */
6712 +
6713 +/* sbtmstatehigh */
6714 +#define SBTMH_SERR 0x1 /* serror */
6715 +#define SBTMH_INT 0x2 /* interrupt */
6716 +#define SBTMH_BUSY 0x4 /* busy */
6717 +#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
6718 +#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
6719 +#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
6720 +#define SBTMH_GCR 0x20000000 /* gated clock request */
6721 +#define SBTMH_BISTF 0x40000000 /* bist failed */
6722 +#define SBTMH_BISTD 0x80000000 /* bist done */
6723 +
6724 +
6725 +/* sbbwa0 */
6726 +#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
6727 +#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
6728 +#define SBBWA_TAB1_SHIFT 16
6729 +
6730 +/* sbimconfiglow */
6731 +#define SBIMCL_STO_MASK 0x7 /* service timeout */
6732 +#define SBIMCL_RTO_MASK 0x70 /* request timeout */
6733 +#define SBIMCL_RTO_SHIFT 4
6734 +#define SBIMCL_CID_MASK 0xff0000 /* connection id */
6735 +#define SBIMCL_CID_SHIFT 16
6736 +
6737 +/* sbimconfighigh */
6738 +#define SBIMCH_IEM_MASK 0xc /* inband error mode */
6739 +#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
6740 +#define SBIMCH_TEM_SHIFT 4
6741 +#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
6742 +#define SBIMCH_BEM_SHIFT 6
6743 +
6744 +/* sbadmatch0 */
6745 +#define SBAM_TYPE_MASK 0x3 /* address type */
6746 +#define SBAM_AD64 0x4 /* reserved */
6747 +#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
6748 +#define SBAM_ADINT0_SHIFT 3
6749 +#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
6750 +#define SBAM_ADINT1_SHIFT 3
6751 +#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
6752 +#define SBAM_ADINT2_SHIFT 3
6753 +#define SBAM_ADEN 0x400 /* enable */
6754 +#define SBAM_ADNEG 0x800 /* negative decode */
6755 +#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
6756 +#define SBAM_BASE0_SHIFT 8
6757 +#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
6758 +#define SBAM_BASE1_SHIFT 12
6759 +#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
6760 +#define SBAM_BASE2_SHIFT 16
6761 +
6762 +/* sbtmconfiglow */
6763 +#define SBTMCL_CD_MASK 0xff /* clock divide */
6764 +#define SBTMCL_CO_MASK 0xf800 /* clock offset */
6765 +#define SBTMCL_CO_SHIFT 11
6766 +#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
6767 +#define SBTMCL_IF_SHIFT 18
6768 +#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
6769 +#define SBTMCL_IM_SHIFT 24
6770 +
6771 +/* sbtmconfighigh */
6772 +#define SBTMCH_BM_MASK 0x3 /* busy mode */
6773 +#define SBTMCH_RM_MASK 0x3 /* retry mode */
6774 +#define SBTMCH_RM_SHIFT 2
6775 +#define SBTMCH_SM_MASK 0x30 /* stop mode */
6776 +#define SBTMCH_SM_SHIFT 4
6777 +#define SBTMCH_EM_MASK 0x300 /* sb error mode */
6778 +#define SBTMCH_EM_SHIFT 8
6779 +#define SBTMCH_IM_MASK 0xc00 /* int mode */
6780 +#define SBTMCH_IM_SHIFT 10
6781 +
6782 +/* sbbconfig */
6783 +#define SBBC_LAT_MASK 0x3 /* sb latency */
6784 +#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
6785 +#define SBBC_MAX0_SHIFT 16
6786 +#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
6787 +#define SBBC_MAX1_SHIFT 20
6788 +
6789 +/* sbbstate */
6790 +#define SBBS_SRD 0x1 /* st reg disable */
6791 +#define SBBS_HRD 0x2 /* hold reg disable */
6792 +
6793 +/* sbidlow */
6794 +#define SBIDL_CS_MASK 0x3 /* config space */
6795 +#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
6796 +#define SBIDL_AR_SHIFT 3
6797 +#define SBIDL_SYNCH 0x40 /* sync */
6798 +#define SBIDL_INIT 0x80 /* initiator */
6799 +#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
6800 +#define SBIDL_MINLAT_SHIFT 8
6801 +#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
6802 +#define SBIDL_MAXLAT_SHIFT 12
6803 +#define SBIDL_FIRST 0x10000 /* this initiator is first */
6804 +#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
6805 +#define SBIDL_CW_SHIFT 18
6806 +#define SBIDL_TP_MASK 0xf00000 /* target ports */
6807 +#define SBIDL_TP_SHIFT 20
6808 +#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
6809 +#define SBIDL_IP_SHIFT 24
6810 +#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
6811 +#define SBIDL_RV_SHIFT 28
6812 +#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
6813 +#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
6814 +
6815 +/* sbidhigh */
6816 +#define SBIDH_RC_MASK 0x000f /* revision code */
6817 +#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
6818 +#define SBIDH_RCE_SHIFT 8
6819 +#define SBCOREREV(sbidh) \
6820 + ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
6821 +#define SBIDH_CC_MASK 0x8ff0 /* core code */
6822 +#define SBIDH_CC_SHIFT 4
6823 +#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
6824 +#define SBIDH_VC_SHIFT 16
6825 +
6826 +#define SB_COMMIT 0xfd8 /* update buffered registers value */
6827 +
6828 +/* vendor codes */
6829 +#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
6830 +
6831 +/* core codes */
6832 +#define SB_NODEV 0x700 /* Invalid coreid */
6833 +#define SB_CC 0x800 /* chipcommon core */
6834 +#define SB_ILINE20 0x801 /* iline20 core */
6835 +#define SB_SDRAM 0x803 /* sdram core */
6836 +#define SB_PCI 0x804 /* pci core */
6837 +#define SB_MIPS 0x805 /* mips core */
6838 +#define SB_ENET 0x806 /* enet mac core */
6839 +#define SB_CODEC 0x807 /* v90 codec core */
6840 +#define SB_USB 0x808 /* usb 1.1 host/device core */
6841 +#define SB_ADSL 0x809 /* ADSL core */
6842 +#define SB_ILINE100 0x80a /* iline100 core */
6843 +#define SB_IPSEC 0x80b /* ipsec core */
6844 +#define SB_PCMCIA 0x80d /* pcmcia core */
6845 +#define SB_SDIOD SB_PCMCIA /* pcmcia core has sdio device */
6846 +#define SB_SOCRAM 0x80e /* internal memory core */
6847 +#define SB_MEMC 0x80f /* memc sdram core */
6848 +#define SB_EXTIF 0x811 /* external interface core */
6849 +#define SB_D11 0x812 /* 802.11 MAC core */
6850 +#define SB_MIPS33 0x816 /* mips3302 core */
6851 +#define SB_USB11H 0x817 /* usb 1.1 host core */
6852 +#define SB_USB11D 0x818 /* usb 1.1 device core */
6853 +#define SB_USB20H 0x819 /* usb 2.0 host core */
6854 +#define SB_USB20D 0x81a /* usb 2.0 device core */
6855 +#define SB_SDIOH 0x81b /* sdio host core */
6856 +#define SB_ROBO 0x81c /* roboswitch core */
6857 +#define SB_ATA100 0x81d /* parallel ATA core */
6858 +#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
6859 +#define SB_GIGETH 0x81f /* gigabit ethernet core */
6860 +#define SB_PCIE 0x820 /* pci express core */
6861 +#define SB_MIMO 0x821 /* MIMO phy core */
6862 +#define SB_SRAMC 0x822 /* SRAM controller core */
6863 +#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
6864 +#define SB_ARM11 0x824 /* ARM 1176 core */
6865 +#define SB_ARM7 0x825 /* ARM 7tdmi core */
6866 +
6867 +#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
6868 +
6869 +/* Not really related to Silicon Backplane, but a couple of software
6870 + * conventions for the use the flash space:
6871 + */
6872 +
6873 +/* Minumum amount of flash we support */
6874 +#define FLASH_MIN 0x00020000 /* Minimum flash size */
6875 +
6876 +/* A boot/binary may have an embedded block that describes its size */
6877 +#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
6878 +#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
6879 +#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
6880 +#define BISZ_TXTST_IDX 1 /* 1: text start */
6881 +#define BISZ_TXTEND_IDX 2 /* 2: text start */
6882 +#define BISZ_DATAST_IDX 3 /* 3: text start */
6883 +#define BISZ_DATAEND_IDX 4 /* 4: text start */
6884 +#define BISZ_BSSST_IDX 5 /* 5: text start */
6885 +#define BISZ_BSSEND_IDX 6 /* 6: text start */
6886 +#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
6887 +
6888 +#endif /* _SBCONFIG_H */
6889 diff -urN linux.old/arch/mips/bcm947xx/include/sbextif.h linux.dev/arch/mips/bcm947xx/include/sbextif.h
6890 --- linux.old/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
6891 +++ linux.dev/arch/mips/bcm947xx/include/sbextif.h 2006-10-02 21:19:59.000000000 +0200
6892 @@ -0,0 +1,243 @@
6893 +/*
6894 + * Hardware-specific External Interface I/O core definitions
6895 + * for the BCM47xx family of SiliconBackplane-based chips.
6896 + *
6897 + * The External Interface core supports a total of three external chip selects
6898 + * supporting external interfaces. One of the external chip selects is
6899 + * used for Flash, one is used for PCMCIA, and the other may be
6900 + * programmed to support either a synchronous interface or an
6901 + * asynchronous interface. The asynchronous interface can be used to
6902 + * support external devices such as UARTs and the BCM2019 Bluetooth
6903 + * baseband processor.
6904 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
6905 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
6906 + *
6907 + * Copyright 2006, Broadcom Corporation
6908 + * All Rights Reserved.
6909 + *
6910 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6911 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6912 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6913 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6914 + *
6915 + * $Id: sbextif.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
6916 + */
6917 +
6918 +#ifndef _SBEXTIF_H
6919 +#define _SBEXTIF_H
6920 +
6921 +/* external interface address space */
6922 +#define EXTIF_PCMCIA_MEMBASE(x) (x)
6923 +#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
6924 +#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
6925 +#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
6926 +#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
6927 +
6928 +/* cpp contortions to concatenate w/arg prescan */
6929 +#ifndef PAD
6930 +#define _PADLINE(line) pad ## line
6931 +#define _XSTR(line) _PADLINE(line)
6932 +#define PAD _XSTR(__LINE__)
6933 +#endif /* PAD */
6934 +
6935 +/*
6936 + * The multiple instances of output and output enable registers
6937 + * are present to allow driver software for multiple cores to control
6938 + * gpio outputs without needing to share a single register pair.
6939 + */
6940 +struct gpiouser {
6941 + uint32 out;
6942 + uint32 outen;
6943 +};
6944 +#define NGPIOUSER 5
6945 +
6946 +typedef volatile struct {
6947 + uint32 corecontrol;
6948 + uint32 extstatus;
6949 + uint32 PAD[2];
6950 +
6951 + /* pcmcia control registers */
6952 + uint32 pcmcia_config;
6953 + uint32 pcmcia_memwait;
6954 + uint32 pcmcia_attrwait;
6955 + uint32 pcmcia_iowait;
6956 +
6957 + /* programmable interface control registers */
6958 + uint32 prog_config;
6959 + uint32 prog_waitcount;
6960 +
6961 + /* flash control registers */
6962 + uint32 flash_config;
6963 + uint32 flash_waitcount;
6964 + uint32 PAD[4];
6965 +
6966 + uint32 watchdog;
6967 +
6968 + /* clock control */
6969 + uint32 clockcontrol_n;
6970 + uint32 clockcontrol_sb;
6971 + uint32 clockcontrol_pci;
6972 + uint32 clockcontrol_mii;
6973 + uint32 PAD[3];
6974 +
6975 + /* gpio */
6976 + uint32 gpioin;
6977 + struct gpiouser gpio[NGPIOUSER];
6978 + uint32 PAD;
6979 + uint32 ejtagouten;
6980 + uint32 gpiointpolarity;
6981 + uint32 gpiointmask;
6982 + uint32 PAD[153];
6983 +
6984 + uint8 uartdata;
6985 + uint8 PAD[3];
6986 + uint8 uartimer;
6987 + uint8 PAD[3];
6988 + uint8 uartfcr;
6989 + uint8 PAD[3];
6990 + uint8 uartlcr;
6991 + uint8 PAD[3];
6992 + uint8 uartmcr;
6993 + uint8 PAD[3];
6994 + uint8 uartlsr;
6995 + uint8 PAD[3];
6996 + uint8 uartmsr;
6997 + uint8 PAD[3];
6998 + uint8 uartscratch;
6999 + uint8 PAD[3];
7000 +} extifregs_t;
7001 +
7002 +/* corecontrol */
7003 +#define CC_UE (1 << 0) /* uart enable */
7004 +
7005 +/* extstatus */
7006 +#define ES_EM (1 << 0) /* endian mode (ro) */
7007 +#define ES_EI (1 << 1) /* external interrupt pin (ro) */
7008 +#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
7009 +
7010 +/* gpio bit mask */
7011 +#define GPIO_BIT0 (1 << 0)
7012 +#define GPIO_BIT1 (1 << 1)
7013 +#define GPIO_BIT2 (1 << 2)
7014 +#define GPIO_BIT3 (1 << 3)
7015 +#define GPIO_BIT4 (1 << 4)
7016 +#define GPIO_BIT5 (1 << 5)
7017 +#define GPIO_BIT6 (1 << 6)
7018 +#define GPIO_BIT7 (1 << 7)
7019 +
7020 +
7021 +/* pcmcia/prog/flash_config */
7022 +#define CF_EN (1 << 0) /* enable */
7023 +#define CF_EM_MASK 0xe /* mode */
7024 +#define CF_EM_SHIFT 1
7025 +#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
7026 +#define CF_EM_SYNC 0x2 /* synchronous mode */
7027 +#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
7028 +#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
7029 +#define CF_BS (1 << 5) /* byteswap */
7030 +#define CF_CD_MASK 0xc0 /* clock divider */
7031 +#define CF_CD_SHIFT 6
7032 +#define CF_CD_DIV2 0x0 /* backplane/2 */
7033 +#define CF_CD_DIV3 0x40 /* backplane/3 */
7034 +#define CF_CD_DIV4 0x80 /* backplane/4 */
7035 +#define CF_CE (1 << 8) /* clock enable */
7036 +#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
7037 +
7038 +/* pcmcia_memwait */
7039 +#define PM_W0_MASK 0x3f /* waitcount0 */
7040 +#define PM_W1_MASK 0x1f00 /* waitcount1 */
7041 +#define PM_W1_SHIFT 8
7042 +#define PM_W2_MASK 0x1f0000 /* waitcount2 */
7043 +#define PM_W2_SHIFT 16
7044 +#define PM_W3_MASK 0x1f000000 /* waitcount3 */
7045 +#define PM_W3_SHIFT 24
7046 +
7047 +/* pcmcia_attrwait */
7048 +#define PA_W0_MASK 0x3f /* waitcount0 */
7049 +#define PA_W1_MASK 0x1f00 /* waitcount1 */
7050 +#define PA_W1_SHIFT 8
7051 +#define PA_W2_MASK 0x1f0000 /* waitcount2 */
7052 +#define PA_W2_SHIFT 16
7053 +#define PA_W3_MASK 0x1f000000 /* waitcount3 */
7054 +#define PA_W3_SHIFT 24
7055 +
7056 +/* pcmcia_iowait */
7057 +#define PI_W0_MASK 0x3f /* waitcount0 */
7058 +#define PI_W1_MASK 0x1f00 /* waitcount1 */
7059 +#define PI_W1_SHIFT 8
7060 +#define PI_W2_MASK 0x1f0000 /* waitcount2 */
7061 +#define PI_W2_SHIFT 16
7062 +#define PI_W3_MASK 0x1f000000 /* waitcount3 */
7063 +#define PI_W3_SHIFT 24
7064 +
7065 +/* prog_waitcount */
7066 +#define PW_W0_MASK 0x0000001f /* waitcount0 */
7067 +#define PW_W1_MASK 0x00001f00 /* waitcount1 */
7068 +#define PW_W1_SHIFT 8
7069 +#define PW_W2_MASK 0x001f0000 /* waitcount2 */
7070 +#define PW_W2_SHIFT 16
7071 +#define PW_W3_MASK 0x1f000000 /* waitcount3 */
7072 +#define PW_W3_SHIFT 24
7073 +
7074 +#define PW_W0 0x0000000c
7075 +#define PW_W1 0x00000a00
7076 +#define PW_W2 0x00020000
7077 +#define PW_W3 0x01000000
7078 +
7079 +/* flash_waitcount */
7080 +#define FW_W0_MASK 0x1f /* waitcount0 */
7081 +#define FW_W1_MASK 0x1f00 /* waitcount1 */
7082 +#define FW_W1_SHIFT 8
7083 +#define FW_W2_MASK 0x1f0000 /* waitcount2 */
7084 +#define FW_W2_SHIFT 16
7085 +#define FW_W3_MASK 0x1f000000 /* waitcount3 */
7086 +#define FW_W3_SHIFT 24
7087 +
7088 +/* watchdog */
7089 +#define WATCHDOG_CLOCK 48000000 /* Hz */
7090 +
7091 +/* clockcontrol_n */
7092 +#define CN_N1_MASK 0x3f /* n1 control */
7093 +#define CN_N2_MASK 0x3f00 /* n2 control */
7094 +#define CN_N2_SHIFT 8
7095 +
7096 +/* clockcontrol_sb/pci/mii */
7097 +#define CC_M1_MASK 0x3f /* m1 control */
7098 +#define CC_M2_MASK 0x3f00 /* m2 control */
7099 +#define CC_M2_SHIFT 8
7100 +#define CC_M3_MASK 0x3f0000 /* m3 control */
7101 +#define CC_M3_SHIFT 16
7102 +#define CC_MC_MASK 0x1f000000 /* mux control */
7103 +#define CC_MC_SHIFT 24
7104 +
7105 +/* Clock control default values */
7106 +#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
7107 +#define CC_DEF_100 0x04020011
7108 +#define CC_DEF_33 0x11030011
7109 +#define CC_DEF_25 0x11050011
7110 +
7111 +/* Clock control values for 125Mhz */
7112 +#define CC_125_N 0x0802
7113 +#define CC_125_M 0x04020009
7114 +#define CC_125_M25 0x11090009
7115 +#define CC_125_M33 0x11090005
7116 +
7117 +/* Clock control magic field values */
7118 +#define CC_F6_2 0x02 /* A factor of 2 in */
7119 +#define CC_F6_3 0x03 /* 6-bit fields like */
7120 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
7121 +#define CC_F6_5 0x09
7122 +#define CC_F6_6 0x11
7123 +#define CC_F6_7 0x21
7124 +
7125 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
7126 +
7127 +#define CC_MC_BYPASS 0x08
7128 +#define CC_MC_M1 0x04
7129 +#define CC_MC_M1M2 0x02
7130 +#define CC_MC_M1M2M3 0x01
7131 +#define CC_MC_M1M3 0x11
7132 +
7133 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
7134 +
7135 +#endif /* _SBEXTIF_H */
7136 diff -urN linux.old/arch/mips/bcm947xx/include/sbhndmips.h linux.dev/arch/mips/bcm947xx/include/sbhndmips.h
7137 --- linux.old/arch/mips/bcm947xx/include/sbhndmips.h 1970-01-01 01:00:00.000000000 +0100
7138 +++ linux.dev/arch/mips/bcm947xx/include/sbhndmips.h 2006-10-02 21:19:59.000000000 +0200
7139 @@ -0,0 +1,47 @@
7140 +/*
7141 + * Broadcom SiliconBackplane MIPS definitions
7142 + *
7143 + * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
7144 + * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
7145 + * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
7146 + * interface. The core revision is stored in the SB ID register in SB
7147 + * configuration space.
7148 + *
7149 + * Copyright 2006, Broadcom Corporation
7150 + * All Rights Reserved.
7151 + *
7152 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7153 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7154 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7155 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7156 + *
7157 + * $Id: sbhndmips.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
7158 + */
7159 +
7160 +#ifndef _sbhndmips_h_
7161 +#define _sbhndmips_h_
7162 +
7163 +#include <mipsinc.h>
7164 +
7165 +#ifndef _LANGUAGE_ASSEMBLY
7166 +
7167 +/* cpp contortions to concatenate w/arg prescan */
7168 +#ifndef PAD
7169 +#define _PADLINE(line) pad ## line
7170 +#define _XSTR(line) _PADLINE(line)
7171 +#define PAD _XSTR(__LINE__)
7172 +#endif /* PAD */
7173 +
7174 +typedef volatile struct {
7175 + uint32 corecontrol;
7176 + uint32 PAD[2];
7177 + uint32 biststatus;
7178 + uint32 PAD[4];
7179 + uint32 intstatus;
7180 + uint32 intmask;
7181 + uint32 timer;
7182 +} mipsregs_t;
7183 +
7184 +#endif /* _LANGUAGE_ASSEMBLY */
7185 +
7186 +#endif /* _sbhndmips_h_ */
7187 diff -urN linux.old/arch/mips/bcm947xx/include/sbmemc.h linux.dev/arch/mips/bcm947xx/include/sbmemc.h
7188 --- linux.old/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
7189 +++ linux.dev/arch/mips/bcm947xx/include/sbmemc.h 2006-10-02 21:19:59.000000000 +0200
7190 @@ -0,0 +1,147 @@
7191 +/*
7192 + * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
7193 + *
7194 + * Copyright 2006, Broadcom Corporation
7195 + * All Rights Reserved.
7196 + *
7197 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7198 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7199 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7200 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7201 + *
7202 + * $Id: sbmemc.h,v 1.6 2006/03/02 12:33:44 honor Exp $
7203 + */
7204 +
7205 +#ifndef _SBMEMC_H
7206 +#define _SBMEMC_H
7207 +
7208 +#ifdef _LANGUAGE_ASSEMBLY
7209 +
7210 +#define MEMC_CONTROL 0x00
7211 +#define MEMC_CONFIG 0x04
7212 +#define MEMC_REFRESH 0x08
7213 +#define MEMC_BISTSTAT 0x0c
7214 +#define MEMC_MODEBUF 0x10
7215 +#define MEMC_BKCLS 0x14
7216 +#define MEMC_PRIORINV 0x18
7217 +#define MEMC_DRAMTIM 0x1c
7218 +#define MEMC_INTSTAT 0x20
7219 +#define MEMC_INTMASK 0x24
7220 +#define MEMC_INTINFO 0x28
7221 +#define MEMC_NCDLCTL 0x30
7222 +#define MEMC_RDNCDLCOR 0x34
7223 +#define MEMC_WRNCDLCOR 0x38
7224 +#define MEMC_MISCDLYCTL 0x3c
7225 +#define MEMC_DQSGATENCDL 0x40
7226 +#define MEMC_SPARE 0x44
7227 +#define MEMC_TPADDR 0x48
7228 +#define MEMC_TPDATA 0x4c
7229 +#define MEMC_BARRIER 0x50
7230 +#define MEMC_CORE 0x54
7231 +
7232 +#else /* !_LANGUAGE_ASSEMBLY */
7233 +
7234 +/* Sonics side: MEMC core registers */
7235 +typedef volatile struct sbmemcregs {
7236 + uint32 control;
7237 + uint32 config;
7238 + uint32 refresh;
7239 + uint32 biststat;
7240 + uint32 modebuf;
7241 + uint32 bkcls;
7242 + uint32 priorinv;
7243 + uint32 dramtim;
7244 + uint32 intstat;
7245 + uint32 intmask;
7246 + uint32 intinfo;
7247 + uint32 reserved1;
7248 + uint32 ncdlctl;
7249 + uint32 rdncdlcor;
7250 + uint32 wrncdlcor;
7251 + uint32 miscdlyctl;
7252 + uint32 dqsgatencdl;
7253 + uint32 spare;
7254 + uint32 tpaddr;
7255 + uint32 tpdata;
7256 + uint32 barrier;
7257 + uint32 core;
7258 +} sbmemcregs_t;
7259 +
7260 +#endif /* _LANGUAGE_ASSEMBLY */
7261 +
7262 +/* MEMC Core Init values (OCP ID 0x80f) */
7263 +
7264 +/* For sdr: */
7265 +#define MEMC_SD_CONFIG_INIT 0x00048000
7266 +#define MEMC_SD_DRAMTIM2_INIT 0x000754d8
7267 +#define MEMC_SD_DRAMTIM3_INIT 0x000754da
7268 +#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
7269 +#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
7270 +#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
7271 +#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
7272 +#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
7273 +#define MEMC_SD_CONTROL_INIT0 0x00000002
7274 +#define MEMC_SD_CONTROL_INIT1 0x00000008
7275 +#define MEMC_SD_CONTROL_INIT2 0x00000004
7276 +#define MEMC_SD_CONTROL_INIT3 0x00000010
7277 +#define MEMC_SD_CONTROL_INIT4 0x00000001
7278 +#define MEMC_SD_MODEBUF_INIT 0x00000000
7279 +#define MEMC_SD_REFRESH_INIT 0x0000840f
7280 +
7281 +
7282 +/* This is for SDRM8X8X4 */
7283 +#define MEMC_SDR_INIT 0x0008
7284 +#define MEMC_SDR_MODE 0x32
7285 +#define MEMC_SDR_NCDL 0x00020032
7286 +#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
7287 +
7288 +/* For ddr: */
7289 +#define MEMC_CONFIG_INIT 0x00048000
7290 +#define MEMC_DRAMTIM2_INIT 0x000754d8
7291 +#define MEMC_DRAMTIM25_INIT 0x000754d9
7292 +#define MEMC_RDNCDLCOR_INIT 0x00000000
7293 +#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
7294 +#define MEMC_WRNCDLCOR_INIT 0x49351200
7295 +#define MEMC_1_WRNCDLCOR_INIT 0x14500200
7296 +#define MEMC_DQSGATENCDL_INIT 0x00030000
7297 +#define MEMC_MISCDLYCTL_INIT 0x21061c1b
7298 +#define MEMC_1_MISCDLYCTL_INIT 0x21021400
7299 +#define MEMC_NCDLCTL_INIT 0x00002001
7300 +#define MEMC_CONTROL_INIT0 0x00000002
7301 +#define MEMC_CONTROL_INIT1 0x00000008
7302 +#define MEMC_MODEBUF_INIT0 0x00004000
7303 +#define MEMC_CONTROL_INIT2 0x00000010
7304 +#define MEMC_MODEBUF_INIT1 0x00000100
7305 +#define MEMC_CONTROL_INIT3 0x00000010
7306 +#define MEMC_CONTROL_INIT4 0x00000008
7307 +#define MEMC_REFRESH_INIT 0x0000840f
7308 +#define MEMC_CONTROL_INIT5 0x00000004
7309 +#define MEMC_MODEBUF_INIT2 0x00000000
7310 +#define MEMC_CONTROL_INIT6 0x00000010
7311 +#define MEMC_CONTROL_INIT7 0x00000001
7312 +
7313 +
7314 +/* This is for DDRM16X16X2 */
7315 +#define MEMC_DDR_INIT 0x0009
7316 +#define MEMC_DDR_MODE 0x62
7317 +#define MEMC_DDR_NCDL 0x0005050a
7318 +#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
7319 +
7320 +/* mask for sdr/ddr calibration registers */
7321 +#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
7322 +#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
7323 +#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
7324 +
7325 +/* masks for miscdlyctl registers */
7326 +#define MEMC_MISC_SM_MASK 0x30000000
7327 +#define MEMC_MISC_SM_SHIFT 28
7328 +#define MEMC_MISC_SD_MASK 0x0f000000
7329 +#define MEMC_MISC_SD_SHIFT 24
7330 +
7331 +/* hw threshhold for calculating wr/rd for sdr memc */
7332 +#define MEMC_CD_THRESHOLD 128
7333 +
7334 +/* Low bit of init register says if memc is ddr or sdr */
7335 +#define MEMC_CONFIG_DDR 0x00000001
7336 +
7337 +#endif /* _SBMEMC_H */
7338 diff -urN linux.old/arch/mips/bcm947xx/include/sbpcie.h linux.dev/arch/mips/bcm947xx/include/sbpcie.h
7339 --- linux.old/arch/mips/bcm947xx/include/sbpcie.h 1970-01-01 01:00:00.000000000 +0100
7340 +++ linux.dev/arch/mips/bcm947xx/include/sbpcie.h 2006-10-02 21:19:59.000000000 +0200
7341 @@ -0,0 +1,200 @@
7342 +/*
7343 + * BCM43XX SiliconBackplane PCIE core hardware definitions.
7344 + *
7345 + * Copyright 2006, Broadcom Corporation
7346 + * All Rights Reserved.
7347 + *
7348 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7349 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7350 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7351 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7352 + *
7353 + * $Id: sbpcie.h,v 1.1.1.2 2006/02/27 03:43:16 honor Exp $
7354 + */
7355 +
7356 +#ifndef _SBPCIE_H
7357 +#define _SBPCIE_H
7358 +
7359 +/* cpp contortions to concatenate w/arg prescan */
7360 +#ifndef PAD
7361 +#define _PADLINE(line) pad ## line
7362 +#define _XSTR(line) _PADLINE(line)
7363 +#define PAD _XSTR(__LINE__)
7364 +#endif
7365 +
7366 +/* PCIE Enumeration space offsets */
7367 +#define PCIE_CORE_CONFIG_OFFSET 0x0
7368 +#define PCIE_FUNC0_CONFIG_OFFSET 0x400
7369 +#define PCIE_FUNC1_CONFIG_OFFSET 0x500
7370 +#define PCIE_FUNC2_CONFIG_OFFSET 0x600
7371 +#define PCIE_FUNC3_CONFIG_OFFSET 0x700
7372 +#define PCIE_SPROM_SHADOW_OFFSET 0x800
7373 +#define PCIE_SBCONFIG_OFFSET 0xE00
7374 +
7375 +/* PCIE Bar0 Address Mapping. Each function maps 16KB config space */
7376 +#define PCIE_DEV_BAR0_SIZE 0x4000
7377 +#define PCIE_BAR0_WINMAPCORE_OFFSET 0x0
7378 +#define PCIE_BAR0_EXTSPROM_OFFSET 0x1000
7379 +#define PCIE_BAR0_PCIECORE_OFFSET 0x2000
7380 +#define PCIE_BAR0_CCCOREREG_OFFSET 0x3000
7381 +
7382 +/* SB side: PCIE core and host control registers */
7383 +typedef struct sbpcieregs {
7384 + uint32 PAD[3];
7385 + uint32 biststatus; /* bist Status: 0x00C */
7386 + uint32 PAD[6];
7387 + uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */
7388 + uint32 PAD[54];
7389 + uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
7390 + uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */
7391 + uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */
7392 + uint32 PAD[4];
7393 +
7394 + /* pcie core supports in direct access to config space */
7395 + uint32 configaddr; /* pcie config space access: Address field: 0x120 */
7396 + uint32 configdata; /* pcie config space access: Data field: 0x124 */
7397 +
7398 + /* mdio access to serdes */
7399 + uint32 mdiocontrol; /* controls the mdio access: 0x128 */
7400 + uint32 mdiodata; /* Data to the mdio access: 0x12c */
7401 +
7402 + /* pcie protocol phy/dllp/tlp register access mechanism */
7403 + uint32 pcieaddr; /* address of the internal registeru: 0x130 */
7404 + uint32 pciedata; /* Data to/from the internal regsiter: 0x134 */
7405 +
7406 + uint32 PAD[434];
7407 + uint16 sprom[36]; /* SPROM shadow Area */
7408 +} sbpcieregs_t;
7409 +
7410 +/* SB to PCIE translation masks */
7411 +#define SBTOPCIE0_MASK 0xfc000000
7412 +#define SBTOPCIE1_MASK 0xfc000000
7413 +#define SBTOPCIE2_MASK 0xc0000000
7414 +
7415 +/* Access type bits (0:1) */
7416 +#define SBTOPCIE_MEM 0
7417 +#define SBTOPCIE_IO 1
7418 +#define SBTOPCIE_CFG0 2
7419 +#define SBTOPCIE_CFG1 3
7420 +
7421 +/* Prefetch enable bit 2 */
7422 +#define SBTOPCIE_PF 4
7423 +
7424 +/* Write Burst enable for memory write bit 3 */
7425 +#define SBTOPCIE_WR_BURST 8
7426 +
7427 +/* config access */
7428 +#define CONFIGADDR_FUNC_MASK 0x7000
7429 +#define CONFIGADDR_FUNC_SHF 12
7430 +#define CONFIGADDR_REG_MASK 0x0FFF
7431 +#define CONFIGADDR_REG_SHF 0
7432 +
7433 +/* PCIE protocol regs Indirect Address */
7434 +#define PCIEADDR_PROT_MASK 0x300
7435 +#define PCIEADDR_PROT_SHF 8
7436 +#define PCIEADDR_PL_TLP 0
7437 +#define PCIEADDR_PL_DLLP 1
7438 +#define PCIEADDR_PL_PLP 2
7439 +
7440 +/* PCIE protocol PHY diagnostic registers */
7441 +#define PCIE_PLP_MODEREG 0x200 /* Mode */
7442 +#define PCIE_PLP_STATUSREG 0x204 /* Status */
7443 +#define PCIE_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
7444 +#define PCIE_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */
7445 +#define PCIE_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */
7446 +#define PCIE_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
7447 +#define PCIE_PLP_ATTNREG 0x218 /* Attention */
7448 +#define PCIE_PLP_ATTNMASKREG 0x21C /* Attention Mask */
7449 +#define PCIE_PLP_RXERRCTR 0x220 /* Rx Error */
7450 +#define PCIE_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */
7451 +#define PCIE_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
7452 +#define PCIE_PLP_TESTCTRLREG 0x22C /* Test Control reg */
7453 +#define PCIE_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
7454 +#define PCIE_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
7455 +#define PCIE_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */
7456 +#define PCIE_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */
7457 +
7458 +/* PCIE protocol DLLP diagnostic registers */
7459 +#define PCIE_DLLP_LCREG 0x100 /* Link Control */
7460 +#define PCIE_DLLP_LSREG 0x104 /* Link Status */
7461 +#define PCIE_DLLP_LAREG 0x108 /* Link Attention */
7462 +#define PCIE_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
7463 +#define PCIE_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */
7464 +#define PCIE_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */
7465 +#define PCIE_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */
7466 +#define PCIE_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
7467 +#define PCIE_DLLP_LRREG 0x120 /* Link Replay */
7468 +#define PCIE_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */
7469 +#define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
7470 +#define PCIE_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */
7471 +#define PCIE_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */
7472 +#define PCIE_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */
7473 +#define PCIE_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */
7474 +#define PCIE_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
7475 +#define PCIE_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
7476 +#define PCIE_DLLP_ERRCTRREG 0x144 /* Error Counter */
7477 +#define PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
7478 +#define PCIE_DLLP_TESTREG 0x14C /* Test */
7479 +#define PCIE_DLLP_PKTBIST 0x150 /* Packet BIST */
7480 +
7481 +/* PCIE protocol TLP diagnostic registers */
7482 +#define PCIE_TLP_CONFIGREG 0x000 /* Configuration */
7483 +#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */
7484 +#define PCIE_TLP_WRDMAUPPER 0x010 /* Write DMA Upper Address */
7485 +#define PCIE_TLP_WRDMALOWER 0x014 /* Write DMA Lower Address */
7486 +#define PCIE_TLP_WRDMAREQ_LBEREG 0x018 /* Write DMA Len/ByteEn Req */
7487 +#define PCIE_TLP_RDDMAUPPER 0x01C /* Read DMA Upper Address */
7488 +#define PCIE_TLP_RDDMALOWER 0x020 /* Read DMA Lower Address */
7489 +#define PCIE_TLP_RDDMALENREG 0x024 /* Read DMA Len Req */
7490 +#define PCIE_TLP_MSIDMAUPPER 0x028 /* MSI DMA Upper Address */
7491 +#define PCIE_TLP_MSIDMALOWER 0x02C /* MSI DMA Lower Address */
7492 +#define PCIE_TLP_MSIDMALENREG 0x030 /* MSI DMA Len Req */
7493 +#define PCIE_TLP_SLVREQLENREG 0x034 /* Slave Request Len */
7494 +#define PCIE_TLP_FCINPUTSREQ 0x038 /* Flow Control Inputs */
7495 +#define PCIE_TLP_TXSMGRSREQ 0x03C /* Tx StateMachine and Gated Req */
7496 +#define PCIE_TLP_ADRACKCNTARBLEN 0x040 /* Address Ack XferCnt and ARB Len */
7497 +#define PCIE_TLP_DMACPLHDR0 0x044 /* DMA Completion Hdr 0 */
7498 +#define PCIE_TLP_DMACPLHDR1 0x048 /* DMA Completion Hdr 1 */
7499 +#define PCIE_TLP_DMACPLHDR2 0x04C /* DMA Completion Hdr 2 */
7500 +#define PCIE_TLP_DMACPLMISC0 0x050 /* DMA Completion Misc0 */
7501 +#define PCIE_TLP_DMACPLMISC1 0x054 /* DMA Completion Misc1 */
7502 +#define PCIE_TLP_DMACPLMISC2 0x058 /* DMA Completion Misc2 */
7503 +#define PCIE_TLP_SPTCTRLLEN 0x05C /* Split Controller Req len */
7504 +#define PCIE_TLP_SPTCTRLMSIC0 0x060 /* Split Controller Misc 0 */
7505 +#define PCIE_TLP_SPTCTRLMSIC1 0x064 /* Split Controller Misc 1 */
7506 +#define PCIE_TLP_BUSDEVFUNC 0x068 /* Bus/Device/Func */
7507 +#define PCIE_TLP_RESETCTR 0x06C /* Reset Counter */
7508 +#define PCIE_TLP_RTRYBUF 0x070 /* Retry Buffer value */
7509 +#define PCIE_TLP_TGTDEBUG1 0x074 /* Target Debug Reg1 */
7510 +#define PCIE_TLP_TGTDEBUG2 0x078 /* Target Debug Reg2 */
7511 +#define PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3 */
7512 +#define PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4 */
7513 +
7514 +/* MDIO control */
7515 +#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
7516 +#define MDIOCTL_DIVISOR_VAL 0x2
7517 +#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
7518 +#define MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
7519 +
7520 +/* MDIO Data */
7521 +#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */
7522 +#define MDIODATA_TA 0x00020000 /* Turnaround */
7523 +#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
7524 +#define MDIODATA_REGADDR_MASK 0x003c0000 /* Regaddr Mask */
7525 +#define MDIODATA_DEVADDR_SHF 22 /* Physmedia devaddr shift */
7526 +#define MDIODATA_DEVADDR_MASK 0x0fc00000 /* Physmedia devaddr Mask */
7527 +#define MDIODATA_WRITE 0x10000000 /* write Transaction */
7528 +#define MDIODATA_READ 0x20000000 /* Read Transaction */
7529 +#define MDIODATA_START 0x40000000 /* start of Transaction */
7530 +
7531 +/* MDIO devices (SERDES modules) */
7532 +#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
7533 +#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
7534 +#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
7535 +
7536 +/* SERDES registers */
7537 +#define SERDES_RX_TIMER1 2 /* Rx Timer1 */
7538 +#define SERDES_RX_CDR 6 /* CDR */
7539 +#define SERDES_RX_CDRBW 7 /* CDR BW */
7540 +
7541 +#endif /* _SBPCIE_H */
7542 diff -urN linux.old/arch/mips/bcm947xx/include/sbpci.h linux.dev/arch/mips/bcm947xx/include/sbpci.h
7543 --- linux.old/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
7544 +++ linux.dev/arch/mips/bcm947xx/include/sbpci.h 2006-10-02 21:19:59.000000000 +0200
7545 @@ -0,0 +1,114 @@
7546 +/*
7547 + * HND SiliconBackplane PCI core hardware definitions.
7548 + *
7549 + * Copyright 2006, Broadcom Corporation
7550 + * All Rights Reserved.
7551 + *
7552 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7553 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7554 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7555 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7556 + *
7557 + * $Id: sbpci.h,v 1.1.1.11 2006/02/27 03:43:16 honor Exp $
7558 + */
7559 +
7560 +#ifndef _sbpci_h_
7561 +#define _sbpci_h_
7562 +
7563 +#ifndef _LANGUAGE_ASSEMBLY
7564 +
7565 +/* cpp contortions to concatenate w/arg prescan */
7566 +#ifndef PAD
7567 +#define _PADLINE(line) pad ## line
7568 +#define _XSTR(line) _PADLINE(line)
7569 +#define PAD _XSTR(__LINE__)
7570 +#endif
7571 +
7572 +/* Sonics side: PCI core and host control registers */
7573 +typedef struct sbpciregs {
7574 + uint32 control; /* PCI control */
7575 + uint32 PAD[3];
7576 + uint32 arbcontrol; /* PCI arbiter control */
7577 + uint32 PAD[3];
7578 + uint32 intstatus; /* Interrupt status */
7579 + uint32 intmask; /* Interrupt mask */
7580 + uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
7581 + uint32 PAD[9];
7582 + uint32 bcastaddr; /* Sonics broadcast address */
7583 + uint32 bcastdata; /* Sonics broadcast data */
7584 + uint32 PAD[2];
7585 + uint32 gpioin; /* ro: gpio input (>=rev2) */
7586 + uint32 gpioout; /* rw: gpio output (>=rev2) */
7587 + uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
7588 + uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
7589 + uint32 PAD[36];
7590 + uint32 sbtopci0; /* Sonics to PCI translation 0 */
7591 + uint32 sbtopci1; /* Sonics to PCI translation 1 */
7592 + uint32 sbtopci2; /* Sonics to PCI translation 2 */
7593 + uint32 PAD[189];
7594 + uint32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */
7595 + uint16 sprom[36]; /* SPROM shadow Area */
7596 + uint32 PAD[46];
7597 +} sbpciregs_t;
7598 +
7599 +#endif /* _LANGUAGE_ASSEMBLY */
7600 +
7601 +/* PCI control */
7602 +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
7603 +#define PCI_RST 0x02 /* Value driven out to pin */
7604 +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
7605 +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
7606 +
7607 +/* PCI arbiter control */
7608 +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
7609 +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
7610 +/* ParkID - for PCI corerev >= 8 */
7611 +#define PCI_PARKID_MASK 0x1c /* Selects which agent is parked on an idle bus */
7612 +#define PCI_PARKID_SHIFT 2
7613 +#define PCI_PARKID_EXT0 0 /* External master 0 */
7614 +#define PCI_PARKID_EXT1 1 /* External master 1 */
7615 +#define PCI_PARKID_EXT2 2 /* External master 2 */
7616 +#define PCI_PARKID_INT 3 /* Internal master */
7617 +#define PCI_PARKID_LAST 4 /* Last active master */
7618 +
7619 +/* Interrupt status/mask */
7620 +#define PCI_INTA 0x01 /* PCI INTA# is asserted */
7621 +#define PCI_INTB 0x02 /* PCI INTB# is asserted */
7622 +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
7623 +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
7624 +#define PCI_PME 0x10 /* PCI PME# is asserted */
7625 +
7626 +/* (General) PCI/SB mailbox interrupts, two bits per pci function */
7627 +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
7628 +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
7629 +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
7630 +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
7631 +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
7632 +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
7633 +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
7634 +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
7635 +
7636 +/* Sonics broadcast address */
7637 +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
7638 +
7639 +/* Sonics to PCI translation types */
7640 +#define SBTOPCI0_MASK 0xfc000000
7641 +#define SBTOPCI1_MASK 0xfc000000
7642 +#define SBTOPCI2_MASK 0xc0000000
7643 +#define SBTOPCI_MEM 0
7644 +#define SBTOPCI_IO 1
7645 +#define SBTOPCI_CFG0 2
7646 +#define SBTOPCI_CFG1 3
7647 +#define SBTOPCI_PREF 0x4 /* prefetch enable */
7648 +#define SBTOPCI_BURST 0x8 /* burst enable */
7649 +#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
7650 +#define SBTOPCI_RC_READ 0x00 /* memory read */
7651 +#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
7652 +#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
7653 +
7654 +/* PCI core index in SROM shadow area */
7655 +#define SRSH_PI_OFFSET 0 /* first word */
7656 +#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
7657 +#define SRSH_PI_SHIFT 12 /* bit 15:12 */
7658 +
7659 +#endif /* _sbpci_h_ */
7660 diff -urN linux.old/arch/mips/bcm947xx/include/sbpcmcia.h linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h
7661 --- linux.old/arch/mips/bcm947xx/include/sbpcmcia.h 1970-01-01 01:00:00.000000000 +0100
7662 +++ linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h 2006-10-02 21:19:59.000000000 +0200
7663 @@ -0,0 +1,147 @@
7664 +/*
7665 + * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
7666 + *
7667 + * Copyright 2006, Broadcom Corporation
7668 + * All Rights Reserved.
7669 + *
7670 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7671 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7672 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7673 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7674 + *
7675 + * $Id: sbpcmcia.h,v 1.1.1.9 2006/02/27 03:43:16 honor Exp $
7676 + */
7677 +
7678 +#ifndef _SBPCMCIA_H
7679 +#define _SBPCMCIA_H
7680 +
7681 +
7682 +/* All the addresses that are offsets in attribute space are divided
7683 + * by two to account for the fact that odd bytes are invalid in
7684 + * attribute space and our read/write routines make the space appear
7685 + * as if they didn't exist. Still we want to show the original numbers
7686 + * as documented in the hnd_pcmcia core manual.
7687 + */
7688 +
7689 +/* PCMCIA Function Configuration Registers */
7690 +#define PCMCIA_FCR (0x700 / 2)
7691 +
7692 +#define FCR0_OFF 0
7693 +#define FCR1_OFF (0x40 / 2)
7694 +#define FCR2_OFF (0x80 / 2)
7695 +#define FCR3_OFF (0xc0 / 2)
7696 +
7697 +#define PCMCIA_FCR0 (0x700 / 2)
7698 +#define PCMCIA_FCR1 (0x740 / 2)
7699 +#define PCMCIA_FCR2 (0x780 / 2)
7700 +#define PCMCIA_FCR3 (0x7c0 / 2)
7701 +
7702 +/* Standard PCMCIA FCR registers */
7703 +
7704 +#define PCMCIA_COR 0
7705 +
7706 +#define COR_RST 0x80
7707 +#define COR_LEV 0x40
7708 +#define COR_IRQEN 0x04
7709 +#define COR_BLREN 0x01
7710 +#define COR_FUNEN 0x01
7711 +
7712 +
7713 +#define PCICIA_FCSR (2 / 2)
7714 +#define PCICIA_PRR (4 / 2)
7715 +#define PCICIA_SCR (6 / 2)
7716 +#define PCICIA_ESR (8 / 2)
7717 +
7718 +
7719 +#define PCM_MEMOFF 0x0000
7720 +#define F0_MEMOFF 0x1000
7721 +#define F1_MEMOFF 0x2000
7722 +#define F2_MEMOFF 0x3000
7723 +#define F3_MEMOFF 0x4000
7724 +
7725 +/* Memory base in the function fcr's */
7726 +#define MEM_ADDR0 (0x728 / 2)
7727 +#define MEM_ADDR1 (0x72a / 2)
7728 +#define MEM_ADDR2 (0x72c / 2)
7729 +
7730 +/* PCMCIA base plus Srom access in fcr0: */
7731 +#define PCMCIA_ADDR0 (0x072e / 2)
7732 +#define PCMCIA_ADDR1 (0x0730 / 2)
7733 +#define PCMCIA_ADDR2 (0x0732 / 2)
7734 +
7735 +#define MEM_SEG (0x0734 / 2)
7736 +#define SROM_CS (0x0736 / 2)
7737 +#define SROM_DATAL (0x0738 / 2)
7738 +#define SROM_DATAH (0x073a / 2)
7739 +#define SROM_ADDRL (0x073c / 2)
7740 +#define SROM_ADDRH (0x073e / 2)
7741 +
7742 +/* Values for srom_cs: */
7743 +#define SROM_IDLE 0
7744 +#define SROM_WRITE 1
7745 +#define SROM_READ 2
7746 +#define SROM_WEN 4
7747 +#define SROM_WDS 7
7748 +#define SROM_DONE 8
7749 +
7750 +/* CIS stuff */
7751 +
7752 +/* The CIS stops where the FCRs start */
7753 +#define CIS_SIZE PCMCIA_FCR
7754 +
7755 +/* Standard tuples we know about */
7756 +
7757 +#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
7758 +#define CISTPL_FUNCE 0x22 /* Function extensions */
7759 +#define CISTPL_CFTABLE 0x1b /* Config table entry */
7760 +
7761 +/* Function extensions for LANs */
7762 +
7763 +#define LAN_TECH 1 /* Technology type */
7764 +#define LAN_SPEED 2 /* Raw bit rate */
7765 +#define LAN_MEDIA 3 /* Transmission media */
7766 +#define LAN_NID 4 /* Node identification (aka MAC addr) */
7767 +#define LAN_CONN 5 /* Connector standard */
7768 +
7769 +
7770 +/* CFTable */
7771 +#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */
7772 +#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */
7773 +#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */
7774 +
7775 +/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
7776 + * take one for HNBU, and use "extensions" (a la FUNCE) within it.
7777 + */
7778 +
7779 +#define CISTPL_BRCM_HNBU 0x80
7780 +
7781 +/* Subtypes of BRCM_HNBU: */
7782 +
7783 +#define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */
7784 +#define HNBU_CHIPID 0x01 /* Two 16bit values: PCI vendor & device id */
7785 +#define HNBU_BOARDREV 0x02 /* One byte board revision */
7786 +#define HNBU_PAPARMS 0x03 /* PA parameters: 8 (sromrev == 1)
7787 + * or 9 (sromrev > 1) bytes
7788 + */
7789 +#define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */
7790 +#define HNBU_CC 0x05 /* Default country code (sromrev == 1) */
7791 +#define HNBU_AA 0x06 /* Antennas available */
7792 +#define HNBU_AG 0x07 /* Antenna gain */
7793 +#define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */
7794 +#define HNBU_LEDS 0x09 /* LED set */
7795 +#define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl)
7796 + * in rev 2
7797 + */
7798 +#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */
7799 +#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */
7800 +#define HNBU_GPIOTIMER 0x0d /* 2 bytes with on/off values in rev 3 */
7801 +
7802 +
7803 +/* sbtmstatelow */
7804 +#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */
7805 +#define SBTML_INT_EN 0x20000 /* enable sb interrupt */
7806 +
7807 +/* sbtmstatehigh */
7808 +#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */
7809 +
7810 +#endif /* _SBPCMCIA_H */
7811 diff -urN linux.old/arch/mips/bcm947xx/include/sbsdram.h linux.dev/arch/mips/bcm947xx/include/sbsdram.h
7812 --- linux.old/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
7813 +++ linux.dev/arch/mips/bcm947xx/include/sbsdram.h 2006-10-02 21:19:59.000000000 +0200
7814 @@ -0,0 +1,85 @@
7815 +/*
7816 + * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
7817 + *
7818 + * Copyright 2006, Broadcom Corporation
7819 + * All Rights Reserved.
7820 + *
7821 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7822 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7823 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7824 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7825 + *
7826 + * $Id: sbsdram.h,v 1.1.1.9 2006/03/02 13:03:52 honor Exp $
7827 + */
7828 +
7829 +#ifndef _SBSDRAM_H
7830 +#define _SBSDRAM_H
7831 +
7832 +#ifndef _LANGUAGE_ASSEMBLY
7833 +
7834 +/* Sonics side: SDRAM core registers */
7835 +typedef volatile struct sbsdramregs {
7836 + uint32 initcontrol; /* Generates external SDRAM initialization sequence */
7837 + uint32 config; /* Initializes external SDRAM mode register */
7838 + uint32 refresh; /* Controls external SDRAM refresh rate */
7839 + uint32 pad1;
7840 + uint32 pad2;
7841 +} sbsdramregs_t;
7842 +
7843 +/* SDRAM simulation */
7844 +#ifdef RAMSZ
7845 +#define SDRAMSZ RAMSZ
7846 +#else
7847 +#define SDRAMSZ (4 * 1024 * 1024)
7848 +#endif
7849 +
7850 +extern uchar sdrambuf[SDRAMSZ];
7851 +
7852 +#endif /* _LANGUAGE_ASSEMBLY */
7853 +
7854 +/* SDRAM initialization control (initcontrol) register bits */
7855 +#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
7856 +#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
7857 +#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
7858 +#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
7859 +#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
7860 +#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
7861 +#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
7862 +#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
7863 +#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
7864 +#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
7865 +#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
7866 +#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
7867 +#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
7868 +
7869 +/* SDRAM configuration (config) register bits */
7870 +#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
7871 +#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
7872 +#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
7873 +#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
7874 +#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
7875 +#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
7876 +
7877 +/* SDRAM refresh control (refresh) register bits */
7878 +#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
7879 +#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
7880 +
7881 +/* SDRAM Core default Init values (OCP ID 0x803) */
7882 +#define SDRAM_INIT MEM4MX16X2
7883 +#define SDRAM_CONFIG SDRAM_BURSTFULL
7884 +#define SDRAM_REFRESH SDRAM_REF(0x40)
7885 +
7886 +#define MEM1MX16 0x009 /* 2 MB */
7887 +#define MEM1MX16X2 0x409 /* 4 MB */
7888 +#define MEM2MX8X2 0x809 /* 4 MB */
7889 +#define MEM2MX8X4 0xc09 /* 8 MB */
7890 +#define MEM2MX32 0x439 /* 8 MB */
7891 +#define MEM4MX16 0x019 /* 8 MB */
7892 +#define MEM4MX16X2 0x419 /* 16 MB */
7893 +#define MEM8MX8X2 0x819 /* 16 MB */
7894 +#define MEM8MX16 0x829 /* 16 MB */
7895 +#define MEM4MX32 0x429 /* 16 MB */
7896 +#define MEM8MX8X4 0xc19 /* 32 MB */
7897 +#define MEM8MX16X2 0xc29 /* 32 MB */
7898 +
7899 +#endif /* _SBSDRAM_H */
7900 diff -urN linux.old/arch/mips/bcm947xx/include/sbsocram.h linux.dev/arch/mips/bcm947xx/include/sbsocram.h
7901 --- linux.old/arch/mips/bcm947xx/include/sbsocram.h 1970-01-01 01:00:00.000000000 +0100
7902 +++ linux.dev/arch/mips/bcm947xx/include/sbsocram.h 2006-10-02 21:19:59.000000000 +0200
7903 @@ -0,0 +1,64 @@
7904 +/*
7905 + * BCM47XX Sonics SiliconBackplane embedded ram core
7906 + *
7907 + * Copyright 2006, Broadcom Corporation
7908 + * All Rights Reserved.
7909 + *
7910 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7911 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7912 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7913 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7914 + *
7915 + * $Id: sbsocram.h,v 1.1.1.3 2006/02/27 03:43:16 honor Exp $
7916 + */
7917 +
7918 +#ifndef _SBSOCRAM_H
7919 +#define _SBSOCRAM_H
7920 +
7921 +#define SR_COREINFO 0x00
7922 +#define SR_BWALLOC 0x04
7923 +#define SR_BISTSTAT 0x0c
7924 +#define SR_BANKINDEX 0x10
7925 +#define SR_BANKSTBYCTL 0x14
7926 +
7927 +
7928 +#ifndef _LANGUAGE_ASSEMBLY
7929 +
7930 +/* Memcsocram core registers */
7931 +typedef volatile struct sbsocramregs {
7932 + uint32 coreinfo;
7933 + uint32 bwalloc;
7934 + uint32 PAD;
7935 + uint32 biststat;
7936 + uint32 bankidx;
7937 + uint32 standbyctrl;
7938 +} sbsocramregs_t;
7939 +
7940 +#endif
7941 +
7942 +/* Coreinfo register */
7943 +#define SRCI_PT_MASK 0x30000
7944 +#define SRCI_PT_SHIFT 16
7945 +
7946 +/* In corerev 0, the memory size is 2 to the power of the
7947 + * base plus 16 plus to the contents of the memsize field plus 1.
7948 + */
7949 +#define SRCI_MS0_MASK 0xf
7950 +#define SR_MS0_BASE 16
7951 +
7952 +/*
7953 + * In corerev 1 the bank size is 2 ^ the bank size field plus 14,
7954 + * the memory size is number of banks times bank size.
7955 + * The same applies to rom size.
7956 + */
7957 +#define SRCI_ROMNB_MASK 0xf000
7958 +#define SRCI_ROMNB_SHIFT 12
7959 +#define SRCI_ROMBSZ_MASK 0xf00
7960 +#define SRCI_ROMBSZ_SHIFT 8
7961 +#define SRCI_SRNB_MASK 0xf0
7962 +#define SRCI_SRNB_SHIFT 4
7963 +#define SRCI_SRBSZ_MASK 0xf
7964 +#define SRCI_SRBSZ_SHIFT 0
7965 +
7966 +#define SR_BSZ_BASE 14
7967 +#endif /* _SBSOCRAM_H */
7968 diff -urN linux.old/arch/mips/bcm947xx/include/sbutils.h linux.dev/arch/mips/bcm947xx/include/sbutils.h
7969 --- linux.old/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
7970 +++ linux.dev/arch/mips/bcm947xx/include/sbutils.h 2006-10-02 21:19:59.000000000 +0200
7971 @@ -0,0 +1,150 @@
7972 +/*
7973 + * Misc utility routines for accessing chip-specific features
7974 + * of Broadcom HNBU SiliconBackplane-based chips.
7975 + *
7976 + * Copyright 2006, Broadcom Corporation
7977 + * All Rights Reserved.
7978 + *
7979 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7980 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7981 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7982 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7983 + *
7984 + * $Id: sbutils.h,v 1.4 2006/04/08 07:12:42 honor Exp $
7985 + */
7986 +
7987 +#ifndef _sbutils_h_
7988 +#define _sbutils_h_
7989 +
7990 +/*
7991 + * Datastructure to export all chip specific common variables
7992 + * public (read-only) portion of sbutils handle returned by
7993 + * sb_attach()/sb_kattach()
7994 +*/
7995 +
7996 +struct sb_pub {
7997 +
7998 + uint bustype; /* SB_BUS, PCI_BUS */
7999 + uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE */
8000 + uint buscorerev; /* buscore rev */
8001 + uint buscoreidx; /* buscore index */
8002 + int ccrev; /* chip common core rev */
8003 + uint boardtype; /* board type */
8004 + uint boardvendor; /* board vendor */
8005 + uint chip; /* chip number */
8006 + uint chiprev; /* chip revision */
8007 + uint chippkg; /* chip package option */
8008 + uint sonicsrev; /* sonics backplane rev */
8009 +};
8010 +
8011 +typedef const struct sb_pub sb_t;
8012 +
8013 +/*
8014 + * Many of the routines below take an 'sbh' handle as their first arg.
8015 + * Allocate this by calling sb_attach(). Free it by calling sb_detach().
8016 + * At any one time, the sbh is logically focused on one particular sb core
8017 + * (the "current core").
8018 + * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
8019 + */
8020 +
8021 +#define SB_OSH NULL /* Use for sb_kattach when no osh is available */
8022 +/* exported externs */
8023 +extern sb_t *sb_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
8024 + void *sdh, char **vars, uint *varsz);
8025 +extern sb_t *sb_kattach(void);
8026 +extern void sb_detach(sb_t *sbh);
8027 +extern uint sb_chip(sb_t *sbh);
8028 +extern uint sb_chiprev(sb_t *sbh);
8029 +extern uint sb_chipcrev(sb_t *sbh);
8030 +extern uint sb_chippkg(sb_t *sbh);
8031 +extern uint sb_pcirev(sb_t *sbh);
8032 +extern bool sb_war16165(sb_t *sbh);
8033 +extern uint sb_pcmciarev(sb_t *sbh);
8034 +extern uint sb_boardvendor(sb_t *sbh);
8035 +extern uint sb_boardtype(sb_t *sbh);
8036 +extern uint sb_bus(sb_t *sbh);
8037 +extern uint sb_buscoretype(sb_t *sbh);
8038 +extern uint sb_buscorerev(sb_t *sbh);
8039 +extern uint sb_corelist(sb_t *sbh, uint coreid[]);
8040 +extern uint sb_coreid(sb_t *sbh);
8041 +extern uint sb_coreidx(sb_t *sbh);
8042 +extern uint sb_coreunit(sb_t *sbh);
8043 +extern uint sb_corevendor(sb_t *sbh);
8044 +extern uint sb_corerev(sb_t *sbh);
8045 +extern void *sb_osh(sb_t *sbh);
8046 +extern void sb_setosh(sb_t *sbh, osl_t *osh);
8047 +extern void *sb_coreregs(sb_t *sbh);
8048 +extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
8049 +extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
8050 +extern bool sb_iscoreup(sb_t *sbh);
8051 +extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
8052 +extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
8053 +extern int sb_corebist(sb_t *sbh);
8054 +extern void sb_commit(sb_t *sbh);
8055 +extern uint32 sb_base(uint32 admatch);
8056 +extern uint32 sb_size(uint32 admatch);
8057 +extern void sb_core_reset(sb_t *sbh, uint32 bits, uint32 resetbits);
8058 +extern void sb_core_tofixup(sb_t *sbh);
8059 +extern void sb_core_disable(sb_t *sbh, uint32 bits);
8060 +extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
8061 +extern uint32 sb_clock(sb_t *sbh);
8062 +extern void sb_pci_setup(sb_t *sbh, uint coremask);
8063 +extern void sb_pcmcia_init(sb_t *sbh);
8064 +extern void sb_watchdog(sb_t *sbh, uint ticks);
8065 +extern void *sb_gpiosetcore(sb_t *sbh);
8066 +extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8067 +extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8068 +extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8069 +extern uint32 sb_gpioin(sb_t *sbh);
8070 +extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8071 +extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8072 +extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
8073 +extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
8074 +extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
8075 +
8076 +extern void sb_clkctl_init(sb_t *sbh);
8077 +extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
8078 +extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
8079 +extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
8080 +extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn,
8081 + void *intrsenabled_fn, void *intr_arg);
8082 +extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to);
8083 +extern int sb_corepciid(sb_t *sbh, uint func, uint16 *pcivendor, uint16 *pcidevice,
8084 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif,
8085 + uint8 *pciheader);
8086 +extern uint sb_pcie_readreg(void *sbh, void* arg1, uint offset);
8087 +extern uint sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val);
8088 +extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val);
8089 +extern bool sb_backplane64(sb_t *sbh);
8090 +extern void sb_btcgpiowar(sb_t *sbh);
8091 +
8092 +
8093 +
8094 +
8095 +extern bool sb_deviceremoved(sb_t *sbh);
8096 +extern uint32 sb_socram_size(sb_t *sbh);
8097 +
8098 +/*
8099 +* Build device path. Path size must be >= SB_DEVPATH_BUFSZ.
8100 +* The returned path is NULL terminated and has trailing '/'.
8101 +* Return 0 on success, nonzero otherwise.
8102 +*/
8103 +extern int sb_devpath(sb_t *sbh, char *path, int size);
8104 +
8105 +/* clkctl xtal what flags */
8106 +#define XTAL 0x1 /* primary crystal oscillator (2050) */
8107 +#define PLL 0x2 /* main chip pll */
8108 +
8109 +/* clkctl clk mode */
8110 +#define CLK_FAST 0 /* force fast (pll) clock */
8111 +#define CLK_DYNAMIC 2 /* enable dynamic clock control */
8112 +
8113 +
8114 +/* GPIO usage priorities */
8115 +#define GPIO_DRV_PRIORITY 0 /* Driver */
8116 +#define GPIO_APP_PRIORITY 1 /* Application */
8117 +
8118 +/* device path */
8119 +#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
8120 +
8121 +#endif /* _sbutils_h_ */
8122 diff -urN linux.old/arch/mips/bcm947xx/include/sflash.h linux.dev/arch/mips/bcm947xx/include/sflash.h
8123 --- linux.old/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
8124 +++ linux.dev/arch/mips/bcm947xx/include/sflash.h 2006-10-02 21:19:59.000000000 +0200
8125 @@ -0,0 +1,36 @@
8126 +/*
8127 + * Broadcom SiliconBackplane chipcommon serial flash interface
8128 + *
8129 + * Copyright 2006, Broadcom Corporation
8130 + * All Rights Reserved.
8131 + *
8132 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8133 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8134 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8135 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8136 + *
8137 + * $Id: sflash.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
8138 + */
8139 +
8140 +#ifndef _sflash_h_
8141 +#define _sflash_h_
8142 +
8143 +#include <typedefs.h>
8144 +#include <sbchipc.h>
8145 +
8146 +struct sflash {
8147 + uint blocksize; /* Block size */
8148 + uint numblocks; /* Number of blocks */
8149 + uint32 type; /* Type */
8150 + uint size; /* Total size in bytes */
8151 +};
8152 +
8153 +/* Utility functions */
8154 +extern int sflash_poll(chipcregs_t *cc, uint offset);
8155 +extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
8156 +extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
8157 +extern int sflash_erase(chipcregs_t *cc, uint offset);
8158 +extern int sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
8159 +extern struct sflash * sflash_init(chipcregs_t *cc);
8160 +
8161 +#endif /* _sflash_h_ */
8162 diff -urN linux.old/arch/mips/bcm947xx/include/trxhdr.h linux.dev/arch/mips/bcm947xx/include/trxhdr.h
8163 --- linux.old/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
8164 +++ linux.dev/arch/mips/bcm947xx/include/trxhdr.h 2006-10-02 21:19:59.000000000 +0200
8165 @@ -0,0 +1,33 @@
8166 +/*
8167 + * TRX image file header format.
8168 + *
8169 + * Copyright 2005, Broadcom Corporation
8170 + * All Rights Reserved.
8171 + *
8172 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8173 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8174 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8175 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8176 + *
8177 + * $Id$
8178 + */
8179 +
8180 +#include <typedefs.h>
8181 +
8182 +#define TRX_MAGIC 0x30524448 /* "HDR0" */
8183 +#define TRX_VERSION 1
8184 +#define TRX_MAX_LEN 0x3A0000
8185 +#define TRX_NO_HEADER 1 /* Do not write TRX header */
8186 +#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
8187 +#define TRX_MAX_OFFSET 3
8188 +
8189 +struct trx_header {
8190 + uint32 magic; /* "HDR0" */
8191 + uint32 len; /* Length of file including header */
8192 + uint32 crc32; /* 32-bit CRC from flag_version to end of file */
8193 + uint32 flag_version; /* 0:15 flags, 16:31 version */
8194 + uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
8195 +};
8196 +
8197 +/* Compatibility */
8198 +typedef struct trx_header TRXHDR, *PTRXHDR;
8199 diff -urN linux.old/arch/mips/bcm947xx/include/typedefs.h linux.dev/arch/mips/bcm947xx/include/typedefs.h
8200 --- linux.old/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
8201 +++ linux.dev/arch/mips/bcm947xx/include/typedefs.h 2006-10-02 21:19:59.000000000 +0200
8202 @@ -0,0 +1,361 @@
8203 +/*
8204 + * Copyright 2006, Broadcom Corporation
8205 + * All Rights Reserved.
8206 + *
8207 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8208 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8209 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8210 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8211 + * $Id: typedefs.h,v 1.1.1.12 2006/04/08 06:13:40 honor Exp $
8212 + */
8213 +
8214 +#ifndef _TYPEDEFS_H_
8215 +#define _TYPEDEFS_H_
8216 +
8217 +
8218 +/* Define 'SITE_TYPEDEFS' in the compile to include a site specific
8219 + * typedef file "site_typedefs.h".
8220 + *
8221 + * If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs"
8222 + * section of this file makes inferences about the compile environment
8223 + * based on defined symbols and possibly compiler pragmas.
8224 + *
8225 + * Following these two sections is the "Default Typedefs"
8226 + * section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is
8227 + * defined. This section has a default set of typedefs and a few
8228 + * proprocessor symbols (TRUE, FALSE, NULL, ...).
8229 + */
8230 +
8231 +#ifdef SITE_TYPEDEFS
8232 +
8233 +/*
8234 + * Site Specific Typedefs
8235 + *
8236 + */
8237 +
8238 +#include "site_typedefs.h"
8239 +
8240 +#else
8241 +
8242 +/*
8243 + * Inferred Typedefs
8244 + *
8245 + */
8246 +
8247 +/* Infer the compile environment based on preprocessor symbols and pramas.
8248 + * Override type definitions as needed, and include configuration dependent
8249 + * header files to define types.
8250 + */
8251 +
8252 +#ifdef __cplusplus
8253 +
8254 +#define TYPEDEF_BOOL
8255 +#ifndef FALSE
8256 +#define FALSE false
8257 +#endif
8258 +#ifndef TRUE
8259 +#define TRUE true
8260 +#endif
8261 +
8262 +#else /* ! __cplusplus */
8263 +
8264 +#if defined(_WIN32)
8265 +
8266 +#define TYPEDEF_BOOL
8267 +typedef unsigned char bool; /* consistent w/BOOL */
8268 +
8269 +#endif /* _WIN32 */
8270 +
8271 +#endif /* ! __cplusplus */
8272 +
8273 +/* use the Windows ULONG_PTR type when compiling for 64 bit */
8274 +#if defined(_WIN64)
8275 +#include <basetsd.h>
8276 +#define TYPEDEF_UINTPTR
8277 +typedef ULONG_PTR uintptr;
8278 +#endif
8279 +
8280 +
8281 +#if defined(_MINOSL_)
8282 +#define _NEED_SIZE_T_
8283 +#endif
8284 +
8285 +#if defined(_NEED_SIZE_T_)
8286 +typedef long unsigned int size_t;
8287 +#endif
8288 +
8289 +#ifdef __DJGPP__
8290 +typedef long unsigned int size_t;
8291 +#endif /* __DJGPP__ */
8292 +
8293 +#ifdef _MSC_VER /* Microsoft C */
8294 +#define TYPEDEF_INT64
8295 +#define TYPEDEF_UINT64
8296 +typedef signed __int64 int64;
8297 +typedef unsigned __int64 uint64;
8298 +#endif
8299 +
8300 +#if defined(MACOSX)
8301 +#define TYPEDEF_BOOL
8302 +#endif
8303 +
8304 +#if defined(__NetBSD__)
8305 +#define TYPEDEF_ULONG
8306 +#endif
8307 +
8308 +
8309 +#if defined(linux)
8310 +#define TYPEDEF_UINT
8311 +#define TYPEDEF_USHORT
8312 +#define TYPEDEF_ULONG
8313 +#endif
8314 +
8315 +#if !defined(linux) && !defined(_WIN32) && !defined(_CFE_) && \
8316 + !defined(_HNDRTE_) && !defined(_MINOSL_) && !defined(__DJGPP__)
8317 +#define TYPEDEF_UINT
8318 +#define TYPEDEF_USHORT
8319 +#endif
8320 +
8321 +
8322 +/* Do not support the (u)int64 types with strict ansi for GNU C */
8323 +#if defined(__GNUC__) && defined(__STRICT_ANSI__)
8324 +#define TYPEDEF_INT64
8325 +#define TYPEDEF_UINT64
8326 +#endif
8327 +
8328 +/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
8329 + * for singned or unsigned
8330 + */
8331 +#if defined(__ICL)
8332 +
8333 +#define TYPEDEF_INT64
8334 +
8335 +#if defined(__STDC__)
8336 +#define TYPEDEF_UINT64
8337 +#endif
8338 +
8339 +#endif /* __ICL */
8340 +
8341 +#if !defined(_WIN32) && !defined(_CFE_) && !defined(_MINOSL_) && \
8342 + !defined(__DJGPP__)
8343 +
8344 +/* pick up ushort & uint from standard types.h */
8345 +#if defined(linux) && defined(__KERNEL__)
8346 +
8347 +#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
8348 +
8349 +#else
8350 +
8351 +#include <sys/types.h>
8352 +
8353 +#endif
8354 +
8355 +#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ && !__DJGPP__ */
8356 +
8357 +#if defined(MACOSX)
8358 +
8359 +#ifdef __BIG_ENDIAN__
8360 +#define IL_BIGENDIAN
8361 +#else
8362 +#ifdef IL_BIGENDIAN
8363 +#error "IL_BIGENDIAN was defined for a little-endian compile"
8364 +#endif
8365 +#endif /* __BIG_ENDIAN__ */
8366 +
8367 +#if !defined(__cplusplus)
8368 +
8369 +#if defined(__i386__)
8370 +typedef unsigned char bool;
8371 +#else
8372 +typedef unsigned int bool;
8373 +#endif
8374 +#define TYPE_BOOL 1
8375 +enum {
8376 + false = 0,
8377 + true = 1
8378 +};
8379 +
8380 +#if defined(KERNEL)
8381 +#include <IOKit/IOTypes.h>
8382 +#endif /* KERNEL */
8383 +
8384 +#endif /* __cplusplus */
8385 +
8386 +#endif /* MACOSX */
8387 +
8388 +
8389 +/* use the default typedefs in the next section of this file */
8390 +#define USE_TYPEDEF_DEFAULTS
8391 +
8392 +#endif /* SITE_TYPEDEFS */
8393 +
8394 +
8395 +/*
8396 + * Default Typedefs
8397 + *
8398 + */
8399 +
8400 +#ifdef USE_TYPEDEF_DEFAULTS
8401 +#undef USE_TYPEDEF_DEFAULTS
8402 +
8403 +#ifndef TYPEDEF_BOOL
8404 +typedef /* @abstract@ */ unsigned char bool;
8405 +#endif
8406 +
8407 +/* define uchar, ushort, uint, ulong */
8408 +
8409 +#ifndef TYPEDEF_UCHAR
8410 +typedef unsigned char uchar;
8411 +#endif
8412 +
8413 +#ifndef TYPEDEF_USHORT
8414 +typedef unsigned short ushort;
8415 +#endif
8416 +
8417 +#ifndef TYPEDEF_UINT
8418 +typedef unsigned int uint;
8419 +#endif
8420 +
8421 +#ifndef TYPEDEF_ULONG
8422 +typedef unsigned long ulong;
8423 +#endif
8424 +
8425 +/* define [u]int8/16/32/64, uintptr */
8426 +
8427 +#ifndef TYPEDEF_UINT8
8428 +typedef unsigned char uint8;
8429 +#endif
8430 +
8431 +#ifndef TYPEDEF_UINT16
8432 +typedef unsigned short uint16;
8433 +#endif
8434 +
8435 +#ifndef TYPEDEF_UINT32
8436 +typedef unsigned int uint32;
8437 +#endif
8438 +
8439 +#ifndef TYPEDEF_UINT64
8440 +typedef unsigned long long uint64;
8441 +#endif
8442 +
8443 +#ifndef TYPEDEF_UINTPTR
8444 +typedef unsigned int uintptr;
8445 +#endif
8446 +
8447 +#ifndef TYPEDEF_INT8
8448 +typedef signed char int8;
8449 +#endif
8450 +
8451 +#ifndef TYPEDEF_INT16
8452 +typedef signed short int16;
8453 +#endif
8454 +
8455 +#ifndef TYPEDEF_INT32
8456 +typedef signed int int32;
8457 +#endif
8458 +
8459 +#ifndef TYPEDEF_INT64
8460 +typedef signed long long int64;
8461 +#endif
8462 +
8463 +/* define float32/64, float_t */
8464 +
8465 +#ifndef TYPEDEF_FLOAT32
8466 +typedef float float32;
8467 +#endif
8468 +
8469 +#ifndef TYPEDEF_FLOAT64
8470 +typedef double float64;
8471 +#endif
8472 +
8473 +/*
8474 + * abstracted floating point type allows for compile time selection of
8475 + * single or double precision arithmetic. Compiling with -DFLOAT32
8476 + * selects single precision; the default is double precision.
8477 + */
8478 +
8479 +#ifndef TYPEDEF_FLOAT_T
8480 +
8481 +#if defined(FLOAT32)
8482 +typedef float32 float_t;
8483 +#else /* default to double precision floating point */
8484 +typedef float64 float_t;
8485 +#endif
8486 +
8487 +#endif /* TYPEDEF_FLOAT_T */
8488 +
8489 +/* define macro values */
8490 +
8491 +#ifndef FALSE
8492 +#define FALSE 0
8493 +#endif
8494 +
8495 +#ifndef TRUE
8496 +#define TRUE 1 /* TRUE */
8497 +#endif
8498 +
8499 +#ifndef NULL
8500 +#define NULL 0
8501 +#endif
8502 +
8503 +#ifndef OFF
8504 +#define OFF 0
8505 +#endif
8506 +
8507 +#ifndef ON
8508 +#define ON 1 /* ON = 1 */
8509 +#endif
8510 +
8511 +#define AUTO (-1) /* Auto = -1 */
8512 +
8513 +/* define PTRSZ, INLINE */
8514 +
8515 +#ifndef PTRSZ
8516 +#define PTRSZ sizeof(char*)
8517 +#endif
8518 +
8519 +#ifndef INLINE
8520 +
8521 +#ifdef _MSC_VER
8522 +
8523 +#define INLINE __inline
8524 +
8525 +#elif __GNUC__
8526 +
8527 +#define INLINE __inline__
8528 +
8529 +#else
8530 +
8531 +#define INLINE
8532 +
8533 +#endif /* _MSC_VER */
8534 +
8535 +#endif /* INLINE */
8536 +
8537 +#undef TYPEDEF_BOOL
8538 +#undef TYPEDEF_UCHAR
8539 +#undef TYPEDEF_USHORT
8540 +#undef TYPEDEF_UINT
8541 +#undef TYPEDEF_ULONG
8542 +#undef TYPEDEF_UINT8
8543 +#undef TYPEDEF_UINT16
8544 +#undef TYPEDEF_UINT32
8545 +#undef TYPEDEF_UINT64
8546 +#undef TYPEDEF_UINTPTR
8547 +#undef TYPEDEF_INT8
8548 +#undef TYPEDEF_INT16
8549 +#undef TYPEDEF_INT32
8550 +#undef TYPEDEF_INT64
8551 +#undef TYPEDEF_FLOAT32
8552 +#undef TYPEDEF_FLOAT64
8553 +#undef TYPEDEF_FLOAT_T
8554 +
8555 +#endif /* USE_TYPEDEF_DEFAULTS */
8556 +
8557 +/*
8558 + * Including the bcmdefs.h here, to make sure everyone including typedefs.h
8559 + * gets this automatically
8560 +*/
8561 +#include "bcmdefs.h"
8562 +
8563 +#endif /* _TYPEDEFS_H_ */
8564 diff -urN linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
8565 --- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
8566 +++ linux.dev/arch/mips/bcm947xx/Makefile 2006-10-02 21:26:08.000000000 +0200
8567 @@ -0,0 +1,17 @@
8568 +#
8569 +# Makefile for the BCM947xx specific kernel interface routines
8570 +# under Linux.
8571 +#
8572 +
8573 +EXTRA_CFLAGS+=-I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER -fno-delayed-branch
8574 +
8575 +O_TARGET := bcm947xx.o
8576 +
8577 +export-objs := export.o
8578 +obj-y := prom.o setup.o time.o sbmips.o gpio.o
8579 +obj-y += nvram.o nvram_linux.o sflash.o cfe_env.o
8580 +obj-y += sbutils.o bcmutils.o bcmsrom.o hndchipc.o
8581 +obj-$(CONFIG_PCI) += sbpci.o pcibios.o
8582 +obj-y += export.o
8583 +
8584 +include $(TOPDIR)/Rules.make
8585 diff -urN linux.old/arch/mips/bcm947xx/nvram.c linux.dev/arch/mips/bcm947xx/nvram.c
8586 --- linux.old/arch/mips/bcm947xx/nvram.c 1970-01-01 01:00:00.000000000 +0100
8587 +++ linux.dev/arch/mips/bcm947xx/nvram.c 2006-10-02 21:19:59.000000000 +0200
8588 @@ -0,0 +1,315 @@
8589 +/*
8590 + * NVRAM variable manipulation (common)
8591 + *
8592 + * Copyright 2004, Broadcom Corporation
8593 + * All Rights Reserved.
8594 + *
8595 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8596 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8597 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8598 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8599 + *
8600 + */
8601 +
8602 +#include <typedefs.h>
8603 +#include <osl.h>
8604 +#include <bcmendian.h>
8605 +#include <bcmnvram.h>
8606 +#include <bcmutils.h>
8607 +#include <sbsdram.h>
8608 +
8609 +extern struct nvram_tuple * BCMINIT(_nvram_realloc)(struct nvram_tuple *t, const char *name, const char *value);
8610 +extern void BCMINIT(_nvram_free)(struct nvram_tuple *t);
8611 +extern int BCMINIT(_nvram_read)(void *buf);
8612 +
8613 +char * BCMINIT(_nvram_get)(const char *name);
8614 +int BCMINIT(_nvram_set)(const char *name, const char *value);
8615 +int BCMINIT(_nvram_unset)(const char *name);
8616 +int BCMINIT(_nvram_getall)(char *buf, int count);
8617 +int BCMINIT(_nvram_commit)(struct nvram_header *header);
8618 +int BCMINIT(_nvram_init)(void);
8619 +void BCMINIT(_nvram_exit)(void);
8620 +
8621 +static struct nvram_tuple * BCMINITDATA(nvram_hash)[257];
8622 +static struct nvram_tuple * nvram_dead;
8623 +
8624 +/* Free all tuples. Should be locked. */
8625 +static void
8626 +BCMINITFN(nvram_free)(void)
8627 +{
8628 + uint i;
8629 + struct nvram_tuple *t, *next;
8630 +
8631 + /* Free hash table */
8632 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
8633 + for (t = BCMINIT(nvram_hash)[i]; t; t = next) {
8634 + next = t->next;
8635 + BCMINIT(_nvram_free)(t);
8636 + }
8637 + BCMINIT(nvram_hash)[i] = NULL;
8638 + }
8639 +
8640 + /* Free dead table */
8641 + for (t = nvram_dead; t; t = next) {
8642 + next = t->next;
8643 + BCMINIT(_nvram_free)(t);
8644 + }
8645 + nvram_dead = NULL;
8646 +
8647 + /* Indicate to per-port code that all tuples have been freed */
8648 + BCMINIT(_nvram_free)(NULL);
8649 +}
8650 +
8651 +/* String hash */
8652 +static INLINE uint
8653 +hash(const char *s)
8654 +{
8655 + uint hash = 0;
8656 +
8657 + while (*s)
8658 + hash = 31 * hash + *s++;
8659 +
8660 + return hash;
8661 +}
8662 +
8663 +/* (Re)initialize the hash table. Should be locked. */
8664 +static int
8665 +BCMINITFN(nvram_rehash)(struct nvram_header *header)
8666 +{
8667 + char buf[] = "0xXXXXXXXX", *name, *value, *end, *eq;
8668 +
8669 + /* (Re)initialize hash table */
8670 + BCMINIT(nvram_free)();
8671 +
8672 + /* Parse and set "name=value\0 ... \0\0" */
8673 + name = (char *) &header[1];
8674 + end = (char *) header + NVRAM_SPACE - 2;
8675 + end[0] = end[1] = '\0';
8676 + for (; *name; name = value + strlen(value) + 1) {
8677 + if (!(eq = strchr(name, '=')))
8678 + break;
8679 + *eq = '\0';
8680 + value = eq + 1;
8681 + BCMINIT(_nvram_set)(name, value);
8682 + *eq = '=';
8683 + }
8684 +
8685 + /* Set special SDRAM parameters */
8686 + if (!BCMINIT(_nvram_get)("sdram_init")) {
8687 + sprintf(buf, "0x%04X", (uint16)(header->crc_ver_init >> 16));
8688 + BCMINIT(_nvram_set)("sdram_init", buf);
8689 + }
8690 + if (!BCMINIT(_nvram_get)("sdram_config")) {
8691 + sprintf(buf, "0x%04X", (uint16)(header->config_refresh & 0xffff));
8692 + BCMINIT(_nvram_set)("sdram_config", buf);
8693 + }
8694 + if (!BCMINIT(_nvram_get)("sdram_refresh")) {
8695 + sprintf(buf, "0x%04X", (uint16)((header->config_refresh >> 16) & 0xffff));
8696 + BCMINIT(_nvram_set)("sdram_refresh", buf);
8697 + }
8698 + if (!BCMINIT(_nvram_get)("sdram_ncdl")) {
8699 + sprintf(buf, "0x%08X", header->config_ncdl);
8700 + BCMINIT(_nvram_set)("sdram_ncdl", buf);
8701 + }
8702 +
8703 + return 0;
8704 +}
8705 +
8706 +/* Get the value of an NVRAM variable. Should be locked. */
8707 +char *
8708 +BCMINITFN(_nvram_get)(const char *name)
8709 +{
8710 + uint i;
8711 + struct nvram_tuple *t;
8712 + char *value;
8713 +
8714 + if (!name)
8715 + return NULL;
8716 +
8717 + /* Hash the name */
8718 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
8719 +
8720 + /* Find the associated tuple in the hash table */
8721 + for (t = BCMINIT(nvram_hash)[i]; t && strcmp(t->name, name); t = t->next);
8722 +
8723 + value = t ? t->value : NULL;
8724 +
8725 + return value;
8726 +}
8727 +
8728 +/* Get the value of an NVRAM variable. Should be locked. */
8729 +int
8730 +BCMINITFN(_nvram_set)(const char *name, const char *value)
8731 +{
8732 + uint i;
8733 + struct nvram_tuple *t, *u, **prev;
8734 +
8735 + /* Hash the name */
8736 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
8737 +
8738 + /* Find the associated tuple in the hash table */
8739 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
8740 +
8741 + /* (Re)allocate tuple */
8742 + if (!(u = BCMINIT(_nvram_realloc)(t, name, value)))
8743 + return -12; /* -ENOMEM */
8744 +
8745 + /* Value reallocated */
8746 + if (t && t == u)
8747 + return 0;
8748 +
8749 + /* Move old tuple to the dead table */
8750 + if (t) {
8751 + *prev = t->next;
8752 + t->next = nvram_dead;
8753 + nvram_dead = t;
8754 + }
8755 +
8756 + /* Add new tuple to the hash table */
8757 + u->next = BCMINIT(nvram_hash)[i];
8758 + BCMINIT(nvram_hash)[i] = u;
8759 +
8760 + return 0;
8761 +}
8762 +
8763 +/* Unset the value of an NVRAM variable. Should be locked. */
8764 +int
8765 +BCMINITFN(_nvram_unset)(const char *name)
8766 +{
8767 + uint i;
8768 + struct nvram_tuple *t, **prev;
8769 +
8770 + if (!name)
8771 + return 0;
8772 +
8773 + /* Hash the name */
8774 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
8775 +
8776 + /* Find the associated tuple in the hash table */
8777 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
8778 +
8779 + /* Move it to the dead table */
8780 + if (t) {
8781 + *prev = t->next;
8782 + t->next = nvram_dead;
8783 + nvram_dead = t;
8784 + }
8785 +
8786 + return 0;
8787 +}
8788 +
8789 +/* Get all NVRAM variables. Should be locked. */
8790 +int
8791 +BCMINITFN(_nvram_getall)(char *buf, int count)
8792 +{
8793 + uint i;
8794 + struct nvram_tuple *t;
8795 + int len = 0;
8796 +
8797 + bzero(buf, count);
8798 +
8799 + /* Write name=value\0 ... \0\0 */
8800 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
8801 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
8802 + if ((count - len) > (strlen(t->name) + 1 + strlen(t->value) + 1))
8803 + len += sprintf(buf + len, "%s=%s", t->name, t->value) + 1;
8804 + else
8805 + break;
8806 + }
8807 + }
8808 +
8809 + return 0;
8810 +}
8811 +
8812 +/* Regenerate NVRAM. Should be locked. */
8813 +int
8814 +BCMINITFN(_nvram_commit)(struct nvram_header *header)
8815 +{
8816 + char *init, *config, *refresh, *ncdl;
8817 + char *ptr, *end;
8818 + int i;
8819 + struct nvram_tuple *t;
8820 + struct nvram_header tmp;
8821 + uint8 crc;
8822 +
8823 + /* Regenerate header */
8824 + header->magic = NVRAM_MAGIC;
8825 + header->crc_ver_init = (NVRAM_VERSION << 8);
8826 + if (!(init = BCMINIT(_nvram_get)("sdram_init")) ||
8827 + !(config = BCMINIT(_nvram_get)("sdram_config")) ||
8828 + !(refresh = BCMINIT(_nvram_get)("sdram_refresh")) ||
8829 + !(ncdl = BCMINIT(_nvram_get)("sdram_ncdl"))) {
8830 + header->crc_ver_init |= SDRAM_INIT << 16;
8831 + header->config_refresh = SDRAM_CONFIG;
8832 + header->config_refresh |= SDRAM_REFRESH << 16;
8833 + header->config_ncdl = 0;
8834 + } else {
8835 + header->crc_ver_init |= (bcm_strtoul(init, NULL, 0) & 0xffff) << 16;
8836 + header->config_refresh = bcm_strtoul(config, NULL, 0) & 0xffff;
8837 + header->config_refresh |= (bcm_strtoul(refresh, NULL, 0) & 0xffff) << 16;
8838 + header->config_ncdl = bcm_strtoul(ncdl, NULL, 0);
8839 + }
8840 +
8841 + /* Clear data area */
8842 + ptr = (char *) header + sizeof(struct nvram_header);
8843 + bzero(ptr, NVRAM_SPACE - sizeof(struct nvram_header));
8844 +
8845 + /* Leave space for a double NUL at the end */
8846 + end = (char *) header + NVRAM_SPACE - 2;
8847 +
8848 + /* Write out all tuples */
8849 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
8850 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
8851 + if ((ptr + strlen(t->name) + 1 + strlen(t->value) + 1) > end)
8852 + break;
8853 + ptr += sprintf(ptr, "%s=%s", t->name, t->value) + 1;
8854 + }
8855 + }
8856 +
8857 + /* End with a double NUL */
8858 + ptr += 2;
8859 +
8860 + /* Set new length */
8861 + header->len = ROUNDUP(ptr - (char *) header, 4);
8862 +
8863 + /* Little-endian CRC8 over the last 11 bytes of the header */
8864 + tmp.crc_ver_init = htol32(header->crc_ver_init);
8865 + tmp.config_refresh = htol32(header->config_refresh);
8866 + tmp.config_ncdl = htol32(header->config_ncdl);
8867 + crc = hndcrc8((char *) &tmp + 9, sizeof(struct nvram_header) - 9, CRC8_INIT_VALUE);
8868 +
8869 + /* Continue CRC8 over data bytes */
8870 + crc = hndcrc8((char *) &header[1], header->len - sizeof(struct nvram_header), crc);
8871 +
8872 + /* Set new CRC8 */
8873 + header->crc_ver_init |= crc;
8874 +
8875 + /* Reinitialize hash table */
8876 + return BCMINIT(nvram_rehash)(header);
8877 +}
8878 +
8879 +/* Initialize hash table. Should be locked. */
8880 +int
8881 +BCMINITFN(_nvram_init)(void)
8882 +{
8883 + struct nvram_header *header;
8884 + int ret;
8885 +
8886 + if (!(header = (struct nvram_header *) kmalloc(NVRAM_SPACE, GFP_ATOMIC))) {
8887 + return -12; /* -ENOMEM */
8888 + }
8889 +
8890 + if ((ret = BCMINIT(_nvram_read)(header)) == 0 &&
8891 + header->magic == NVRAM_MAGIC)
8892 + BCMINIT(nvram_rehash)(header);
8893 +
8894 + kfree(header);
8895 + return ret;
8896 +}
8897 +
8898 +/* Free hash table. Should be locked. */
8899 +void
8900 +BCMINITFN(_nvram_exit)(void)
8901 +{
8902 + BCMINIT(nvram_free)();
8903 +}
8904 diff -urN linux.old/arch/mips/bcm947xx/nvram_linux.c linux.dev/arch/mips/bcm947xx/nvram_linux.c
8905 --- linux.old/arch/mips/bcm947xx/nvram_linux.c 1970-01-01 01:00:00.000000000 +0100
8906 +++ linux.dev/arch/mips/bcm947xx/nvram_linux.c 2006-10-02 21:19:59.000000000 +0200
8907 @@ -0,0 +1,723 @@
8908 +/*
8909 + * NVRAM variable manipulation (Linux kernel half)
8910 + *
8911 + * Copyright 2006, Broadcom Corporation
8912 + * All Rights Reserved.
8913 + *
8914 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8915 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8916 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8917 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8918 + *
8919 + * $Id: nvram_linux.c,v 1.19 2006/04/08 07:12:42 honor Exp $
8920 + */
8921 +
8922 +#include <linux/config.h>
8923 +#include <linux/init.h>
8924 +#include <linux/module.h>
8925 +#include <linux/kernel.h>
8926 +#include <linux/string.h>
8927 +#include <linux/interrupt.h>
8928 +#include <linux/spinlock.h>
8929 +#include <linux/slab.h>
8930 +#include <linux/bootmem.h>
8931 +#include <linux/wrapper.h>
8932 +#include <linux/fs.h>
8933 +#include <linux/miscdevice.h>
8934 +#include <linux/mtd/mtd.h>
8935 +#include <asm/addrspace.h>
8936 +#include <asm/io.h>
8937 +#include <asm/uaccess.h>
8938 +
8939 +#include <typedefs.h>
8940 +#include <osl.h>
8941 +#include <bcmendian.h>
8942 +#include <bcmnvram.h>
8943 +#include <bcmutils.h>
8944 +#include <sbconfig.h>
8945 +#include <sbchipc.h>
8946 +#include <sbutils.h>
8947 +#include <hndmips.h>
8948 +#include <sflash.h>
8949 +
8950 +/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
8951 +static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
8952 +
8953 +#ifdef MODULE
8954 +
8955 +#define early_nvram_get(name) nvram_get(name)
8956 +
8957 +#else /* !MODULE */
8958 +
8959 +/* Global SB handle */
8960 +extern void *bcm947xx_sbh;
8961 +extern spinlock_t bcm947xx_sbh_lock;
8962 +
8963 +static int cfe_env;
8964 +extern char *cfe_env_get(char *nv_buf, const char *name);
8965 +
8966 +/* Convenience */
8967 +#define sbh bcm947xx_sbh
8968 +#define sbh_lock bcm947xx_sbh_lock
8969 +#define KB * 1024
8970 +#define MB * 1024 * 1024
8971 +
8972 +/* Probe for NVRAM header */
8973 +static void __init
8974 +early_nvram_init(void)
8975 +{
8976 + struct nvram_header *header;
8977 + chipcregs_t *cc;
8978 + struct sflash *info = NULL;
8979 + int i;
8980 + uint32 base, off, lim;
8981 + u32 *src, *dst;
8982 +
8983 + if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
8984 + base = KSEG1ADDR(SB_FLASH2);
8985 + switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
8986 + case PFLASH:
8987 + lim = SB_FLASH2_SZ;
8988 + break;
8989 +
8990 + case SFLASH_ST:
8991 + case SFLASH_AT:
8992 + if ((info = sflash_init(cc)) == NULL)
8993 + return;
8994 + lim = info->size;
8995 + break;
8996 +
8997 + case FLASH_NONE:
8998 + default:
8999 + return;
9000 + }
9001 + } else {
9002 + /* extif assumed, Stop at 4 MB */
9003 + base = KSEG1ADDR(SB_FLASH1);
9004 + lim = SB_FLASH1_SZ;
9005 + }
9006 +
9007 + /* XXX: hack for supporting the CFE environment stuff on WGT634U */
9008 + src = (u32 *) KSEG1ADDR(base + 8 * 1024 * 1024 - 0x2000);
9009 + dst = (u32 *) nvram_buf;
9010 + if ((lim == 0x02000000) && ((*src & 0xff00ff) == 0x000001)) {
9011 + printk("early_nvram_init: WGT634U NVRAM found.\n");
9012 +
9013 + for (i = 0; i < 0x1ff0; i++) {
9014 + if (*src == 0xFFFFFFFF)
9015 + break;
9016 + *dst++ = *src++;
9017 + }
9018 + cfe_env = 1;
9019 + return;
9020 + }
9021 +
9022 + off = FLASH_MIN;
9023 + while (off <= lim) {
9024 + /* Windowed flash access */
9025 + header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
9026 + if (header->magic == NVRAM_MAGIC)
9027 + goto found;
9028 + off <<= 1;
9029 + }
9030 +
9031 + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
9032 + header = (struct nvram_header *) KSEG1ADDR(base + 4 KB);
9033 + if (header->magic == NVRAM_MAGIC)
9034 + goto found;
9035 +
9036 + header = (struct nvram_header *) KSEG1ADDR(base + 1 KB);
9037 + if (header->magic == NVRAM_MAGIC)
9038 + goto found;
9039 +
9040 + printk("early_nvram_init: NVRAM not found\n");
9041 + return;
9042 +
9043 +found:
9044 + src = (u32 *) header;
9045 + dst = (u32 *) nvram_buf;
9046 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
9047 + *dst++ = *src++;
9048 + for (; i < header->len && i < NVRAM_SPACE; i += 4)
9049 + *dst++ = ltoh32(*src++);
9050 +}
9051 +
9052 +/* Early (before mm or mtd) read-only access to NVRAM */
9053 +static char * __init
9054 +early_nvram_get(const char *name)
9055 +{
9056 + char *var, *value, *end, *eq;
9057 +
9058 + if (!name)
9059 + return NULL;
9060 +
9061 + /* Too early? */
9062 + if (sbh == NULL)
9063 + return NULL;
9064 +
9065 + if (!nvram_buf[0])
9066 + early_nvram_init();
9067 +
9068 + if (cfe_env)
9069 + return cfe_env_get(nvram_buf, name);
9070 +
9071 + /* Look for name=value and return value */
9072 + var = &nvram_buf[sizeof(struct nvram_header)];
9073 + end = nvram_buf + sizeof(nvram_buf) - 2;
9074 + end[0] = end[1] = '\0';
9075 + for (; *var; var = value + strlen(value) + 1) {
9076 + if (!(eq = strchr(var, '=')))
9077 + break;
9078 + value = eq + 1;
9079 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
9080 + return value;
9081 + }
9082 +
9083 + return NULL;
9084 +}
9085 +
9086 +static int __init
9087 +early_nvram_getall(char *buf, int count)
9088 +{
9089 + char *var, *end;
9090 + int len = 0;
9091 +
9092 + /* Too early? */
9093 + if (sbh == NULL)
9094 + return -1;
9095 +
9096 + if (!nvram_buf[0])
9097 + early_nvram_init();
9098 +
9099 + bzero(buf, count);
9100 +
9101 + /* Write name=value\0 ... \0\0 */
9102 + var = &nvram_buf[sizeof(struct nvram_header)];
9103 + end = nvram_buf + sizeof(nvram_buf) - 2;
9104 + end[0] = end[1] = '\0';
9105 + for (; *var; var += strlen(var) + 1) {
9106 + if ((count - len) <= (strlen(var) + 1))
9107 + break;
9108 + len += sprintf(buf + len, "%s", var) + 1;
9109 + }
9110 +
9111 + return 0;
9112 +}
9113 +#endif /* !MODULE */
9114 +
9115 +extern char * _nvram_get(const char *name);
9116 +extern int _nvram_set(const char *name, const char *value);
9117 +extern int _nvram_unset(const char *name);
9118 +extern int _nvram_getall(char *buf, int count);
9119 +extern int _nvram_commit(struct nvram_header *header);
9120 +extern int _nvram_init(void *sbh);
9121 +extern void _nvram_exit(void);
9122 +
9123 +/* Globals */
9124 +static spinlock_t nvram_lock = SPIN_LOCK_UNLOCKED;
9125 +static struct semaphore nvram_sem;
9126 +static unsigned long nvram_offset = 0;
9127 +static int nvram_major = -1;
9128 +static devfs_handle_t nvram_handle = NULL;
9129 +static struct mtd_info *nvram_mtd = NULL;
9130 +
9131 +int
9132 +_nvram_read(char *buf)
9133 +{
9134 + struct nvram_header *header = (struct nvram_header *) buf;
9135 + size_t len;
9136 +
9137 + if (!nvram_mtd ||
9138 + MTD_READ(nvram_mtd, nvram_mtd->size - NVRAM_SPACE, NVRAM_SPACE, &len, buf) ||
9139 + len != NVRAM_SPACE ||
9140 + header->magic != NVRAM_MAGIC) {
9141 + /* Maybe we can recover some data from early initialization */
9142 + memcpy(buf, nvram_buf, NVRAM_SPACE);
9143 + }
9144 +
9145 + return 0;
9146 +}
9147 +
9148 +struct nvram_tuple *
9149 +_nvram_realloc(struct nvram_tuple *t, const char *name, const char *value)
9150 +{
9151 + if ((nvram_offset + strlen(value) + 1) > NVRAM_SPACE)
9152 + return NULL;
9153 +
9154 + if (!t) {
9155 + if (!(t = kmalloc(sizeof(struct nvram_tuple) + strlen(name) + 1, GFP_ATOMIC)))
9156 + return NULL;
9157 +
9158 + /* Copy name */
9159 + t->name = (char *) &t[1];
9160 + strcpy(t->name, name);
9161 +
9162 + t->value = NULL;
9163 + }
9164 +
9165 + /* Copy value */
9166 + if (!t->value || strcmp(t->value, value)) {
9167 + t->value = &nvram_buf[nvram_offset];
9168 + strcpy(t->value, value);
9169 + nvram_offset += strlen(value) + 1;
9170 + }
9171 +
9172 + return t;
9173 +}
9174 +
9175 +void
9176 +_nvram_free(struct nvram_tuple *t)
9177 +{
9178 + if (!t)
9179 + nvram_offset = 0;
9180 + else
9181 + kfree(t);
9182 +}
9183 +
9184 +int
9185 +nvram_set(const char *name, const char *value)
9186 +{
9187 + unsigned long flags;
9188 + int ret;
9189 + struct nvram_header *header;
9190 +
9191 + spin_lock_irqsave(&nvram_lock, flags);
9192 + if ((ret = _nvram_set(name, value))) {
9193 + /* Consolidate space and try again */
9194 + if ((header = kmalloc(NVRAM_SPACE, GFP_ATOMIC))) {
9195 + if (_nvram_commit(header) == 0)
9196 + ret = _nvram_set(name, value);
9197 + kfree(header);
9198 + }
9199 + }
9200 + spin_unlock_irqrestore(&nvram_lock, flags);
9201 +
9202 + return ret;
9203 +}
9204 +
9205 +char *
9206 +real_nvram_get(const char *name)
9207 +{
9208 + unsigned long flags;
9209 + char *value;
9210 +
9211 + spin_lock_irqsave(&nvram_lock, flags);
9212 + value = _nvram_get(name);
9213 + spin_unlock_irqrestore(&nvram_lock, flags);
9214 +
9215 + return value;
9216 +}
9217 +
9218 +char *
9219 +nvram_get(const char *name)
9220 +{
9221 + if (nvram_major >= 0)
9222 + return real_nvram_get(name);
9223 + else
9224 + return early_nvram_get(name);
9225 +}
9226 +
9227 +int
9228 +nvram_unset(const char *name)
9229 +{
9230 + unsigned long flags;
9231 + int ret;
9232 +
9233 + spin_lock_irqsave(&nvram_lock, flags);
9234 + ret = _nvram_unset(name);
9235 + spin_unlock_irqrestore(&nvram_lock, flags);
9236 +
9237 + return ret;
9238 +}
9239 +
9240 +static void
9241 +erase_callback(struct erase_info *done)
9242 +{
9243 + wait_queue_head_t *wait_q = (wait_queue_head_t *) done->priv;
9244 + wake_up(wait_q);
9245 +}
9246 +
9247 +int
9248 +nvram_commit(void)
9249 +{
9250 + char *buf;
9251 + size_t erasesize, len, magic_len;
9252 + unsigned int i;
9253 + int ret;
9254 + struct nvram_header *header;
9255 + unsigned long flags;
9256 + u_int32_t offset;
9257 + DECLARE_WAITQUEUE(wait, current);
9258 + wait_queue_head_t wait_q;
9259 + struct erase_info erase;
9260 + u_int32_t magic_offset = 0; /* Offset for writing MAGIC # */
9261 +
9262 + if (!nvram_mtd) {
9263 + printk("nvram_commit: NVRAM not found\n");
9264 + return -ENODEV;
9265 + }
9266 +
9267 + if (in_interrupt()) {
9268 + printk("nvram_commit: not committing in interrupt\n");
9269 + return -EINVAL;
9270 + }
9271 +
9272 + /* Backup sector blocks to be erased */
9273 + erasesize = ROUNDUP(NVRAM_SPACE, nvram_mtd->erasesize);
9274 + if (!(buf = kmalloc(erasesize, GFP_KERNEL))) {
9275 + printk("nvram_commit: out of memory\n");
9276 + return -ENOMEM;
9277 + }
9278 +
9279 + down(&nvram_sem);
9280 +
9281 + if ((i = erasesize - NVRAM_SPACE) > 0) {
9282 + offset = nvram_mtd->size - erasesize;
9283 + len = 0;
9284 + ret = MTD_READ(nvram_mtd, offset, i, &len, buf);
9285 + if (ret || len != i) {
9286 + printk("nvram_commit: read error ret = %d, len = %d/%d\n", ret, len, i);
9287 + ret = -EIO;
9288 + goto done;
9289 + }
9290 + header = (struct nvram_header *)(buf + i);
9291 + magic_offset = i + ((void *)&header->magic - (void *)header);
9292 + } else {
9293 + offset = nvram_mtd->size - NVRAM_SPACE;
9294 + magic_offset = ((void *)&header->magic - (void *)header);
9295 + header = (struct nvram_header *)buf;
9296 + }
9297 +
9298 + /* clear the existing magic # to mark the NVRAM as unusable
9299 + we can pull MAGIC bits low without erase */
9300 + header->magic = NVRAM_CLEAR_MAGIC; /* All zeros magic */
9301 +
9302 + /* Unlock sector blocks (for Intel 28F320C3B flash) , 20060309 */
9303 + if(nvram_mtd->unlock)
9304 + nvram_mtd->unlock(nvram_mtd, offset, nvram_mtd->erasesize);
9305 +
9306 + ret = MTD_WRITE(nvram_mtd, offset + magic_offset, sizeof(header->magic),
9307 + &magic_len, (char *)&header->magic);
9308 + if (ret || magic_len != sizeof(header->magic)) {
9309 + printk("nvram_commit: clear MAGIC error\n");
9310 + ret = -EIO;
9311 + goto done;
9312 + }
9313 +
9314 + header->magic = NVRAM_MAGIC; /* reset MAGIC before we regenerate the NVRAM,
9315 + otherwise we'll have an incorrect CRC */
9316 + /* Regenerate NVRAM */
9317 + spin_lock_irqsave(&nvram_lock, flags);
9318 + ret = _nvram_commit(header);
9319 + spin_unlock_irqrestore(&nvram_lock, flags);
9320 + if (ret)
9321 + goto done;
9322 +
9323 + /* Erase sector blocks */
9324 + init_waitqueue_head(&wait_q);
9325 + for (; offset < nvram_mtd->size - NVRAM_SPACE + header->len; offset += nvram_mtd->erasesize) {
9326 + erase.mtd = nvram_mtd;
9327 + erase.addr = offset;
9328 + erase.len = nvram_mtd->erasesize;
9329 + erase.callback = erase_callback;
9330 + erase.priv = (u_long) &wait_q;
9331 +
9332 + set_current_state(TASK_INTERRUPTIBLE);
9333 + add_wait_queue(&wait_q, &wait);
9334 +
9335 + /* Unlock sector blocks */
9336 + if (nvram_mtd->unlock)
9337 + nvram_mtd->unlock(nvram_mtd, offset, nvram_mtd->erasesize);
9338 +
9339 + if ((ret = MTD_ERASE(nvram_mtd, &erase))) {
9340 + set_current_state(TASK_RUNNING);
9341 + remove_wait_queue(&wait_q, &wait);
9342 + printk("nvram_commit: erase error\n");
9343 + goto done;
9344 + }
9345 +
9346 + /* Wait for erase to finish */
9347 + schedule();
9348 + remove_wait_queue(&wait_q, &wait);
9349 + }
9350 +
9351 + /* Write partition up to end of data area */
9352 + header->magic = NVRAM_INVALID_MAGIC; /* All ones magic */
9353 + offset = nvram_mtd->size - erasesize;
9354 + i = erasesize - NVRAM_SPACE + header->len;
9355 + ret = MTD_WRITE(nvram_mtd, offset, i, &len, buf);
9356 + if (ret || len != i) {
9357 + printk("nvram_commit: write error\n");
9358 + ret = -EIO;
9359 + goto done;
9360 + }
9361 +
9362 + /* Now mark the NVRAM in flash as "valid" by setting the correct
9363 + MAGIC # */
9364 + header->magic = NVRAM_MAGIC;
9365 + ret = MTD_WRITE(nvram_mtd, offset + magic_offset, sizeof(header->magic),
9366 + &magic_len, (char *)&header->magic);
9367 + if (ret || magic_len != sizeof(header->magic)) {
9368 + printk("nvram_commit: write MAGIC error\n");
9369 + ret = -EIO;
9370 + goto done;
9371 + }
9372 +
9373 + /*
9374 + * Reading a few bytes back here will put the device
9375 + * back to the correct mode on certain flashes */
9376 + offset = nvram_mtd->size - erasesize;
9377 + ret = MTD_READ(nvram_mtd, offset, 4, &len, buf);
9378 +
9379 + done:
9380 + up(&nvram_sem);
9381 + kfree(buf);
9382 +
9383 + return ret;
9384 +}
9385 +
9386 +int
9387 +nvram_getall(char *buf, int count)
9388 +{
9389 + unsigned long flags;
9390 + int ret;
9391 +
9392 + spin_lock_irqsave(&nvram_lock, flags);
9393 + if (nvram_major >= 0)
9394 + ret = _nvram_getall(buf, count);
9395 + else
9396 + ret = early_nvram_getall(buf, count);
9397 + spin_unlock_irqrestore(&nvram_lock, flags);
9398 +
9399 + return ret;
9400 +}
9401 +
9402 +
9403 +
9404 +
9405 +
9406 +
9407 +
9408 +/* User mode interface below */
9409 +
9410 +static ssize_t
9411 +dev_nvram_read(struct file *file, char *buf, size_t count, loff_t *ppos)
9412 +{
9413 + char tmp[100], *name = tmp, *value;
9414 + ssize_t ret;
9415 + unsigned long off;
9416 +
9417 + if (count > sizeof(tmp)) {
9418 + if (!(name = kmalloc(count, GFP_KERNEL)))
9419 + return -ENOMEM;
9420 + }
9421 +
9422 + if (copy_from_user(name, buf, count)) {
9423 + ret = -EFAULT;
9424 + goto done;
9425 + }
9426 +
9427 + if (*name == '\0') {
9428 + /* Get all variables */
9429 + ret = nvram_getall(name, count);
9430 + if (ret == 0) {
9431 + if (copy_to_user(buf, name, count)) {
9432 + ret = -EFAULT;
9433 + goto done;
9434 + }
9435 + ret = count;
9436 + }
9437 + } else {
9438 + if (!(value = nvram_get(name))) {
9439 + ret = 0;
9440 + goto done;
9441 + }
9442 +
9443 + /* Provide the offset into mmap() space */
9444 + off = (unsigned long) value - (unsigned long) nvram_buf;
9445 +
9446 + if (put_user(off, (unsigned long *) buf)) {
9447 + ret = -EFAULT;
9448 + goto done;
9449 + }
9450 +
9451 + ret = sizeof(unsigned long);
9452 + }
9453 +
9454 + flush_cache_all();
9455 +
9456 +done:
9457 + if (name != tmp)
9458 + kfree(name);
9459 +
9460 + return ret;
9461 +}
9462 +
9463 +static ssize_t
9464 +dev_nvram_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
9465 +{
9466 + char tmp[100], *name = tmp, *value;
9467 + ssize_t ret;
9468 +
9469 + if (count > sizeof(tmp)) {
9470 + if (!(name = kmalloc(count, GFP_KERNEL)))
9471 + return -ENOMEM;
9472 + }
9473 +
9474 + if (copy_from_user(name, buf, count)) {
9475 + ret = -EFAULT;
9476 + goto done;
9477 + }
9478 +
9479 + value = name;
9480 + name = strsep(&value, "=");
9481 + if (value)
9482 + ret = nvram_set(name, value) ? : count;
9483 + else
9484 + ret = nvram_unset(name) ? : count;
9485 +
9486 + done:
9487 + if (name != tmp)
9488 + kfree(name);
9489 +
9490 + return ret;
9491 +}
9492 +
9493 +static int
9494 +dev_nvram_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
9495 +{
9496 + if (cmd != NVRAM_MAGIC)
9497 + return -EINVAL;
9498 +
9499 + return nvram_commit();
9500 +}
9501 +
9502 +static int
9503 +dev_nvram_mmap(struct file *file, struct vm_area_struct *vma)
9504 +{
9505 + unsigned long offset = virt_to_phys(nvram_buf);
9506 +
9507 + if (remap_page_range(vma->vm_start, offset, vma->vm_end-vma->vm_start,
9508 + vma->vm_page_prot))
9509 + return -EAGAIN;
9510 +
9511 + return 0;
9512 +}
9513 +
9514 +static int
9515 +dev_nvram_open(struct inode *inode, struct file * file)
9516 +{
9517 + MOD_INC_USE_COUNT;
9518 + return 0;
9519 +}
9520 +
9521 +static int
9522 +dev_nvram_release(struct inode *inode, struct file * file)
9523 +{
9524 + MOD_DEC_USE_COUNT;
9525 + return 0;
9526 +}
9527 +
9528 +static struct file_operations dev_nvram_fops = {
9529 + owner: THIS_MODULE,
9530 + open: dev_nvram_open,
9531 + release: dev_nvram_release,
9532 + read: dev_nvram_read,
9533 + write: dev_nvram_write,
9534 + ioctl: dev_nvram_ioctl,
9535 + mmap: dev_nvram_mmap,
9536 +};
9537 +
9538 +static void
9539 +dev_nvram_exit(void)
9540 +{
9541 + int order = 0;
9542 + struct page *page, *end;
9543 +
9544 + if (nvram_handle)
9545 + devfs_unregister(nvram_handle);
9546 +
9547 + if (nvram_major >= 0)
9548 + devfs_unregister_chrdev(nvram_major, "nvram");
9549 +
9550 + if (nvram_mtd)
9551 + put_mtd_device(nvram_mtd);
9552 +
9553 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
9554 + order++;
9555 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
9556 + for (page = virt_to_page(nvram_buf); page <= end; page++)
9557 + mem_map_unreserve(page);
9558 +
9559 + _nvram_exit();
9560 +}
9561 +
9562 +static int __init
9563 +dev_nvram_init(void)
9564 +{
9565 + int order = 0, ret = 0;
9566 + struct page *page, *end;
9567 + unsigned int i;
9568 +
9569 + /* Allocate and reserve memory to mmap() */
9570 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
9571 + order++;
9572 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
9573 + for (page = virt_to_page(nvram_buf); page <= end; page++)
9574 + mem_map_reserve(page);
9575 +
9576 +#ifdef CONFIG_MTD
9577 + /* Find associated MTD device */
9578 + for (i = 0; i < MAX_MTD_DEVICES; i++) {
9579 + nvram_mtd = get_mtd_device(NULL, i);
9580 + if (nvram_mtd) {
9581 + if (!strcmp(nvram_mtd->name, "nvram") &&
9582 + nvram_mtd->size >= NVRAM_SPACE)
9583 + break;
9584 + put_mtd_device(nvram_mtd);
9585 + }
9586 + }
9587 + if (i >= MAX_MTD_DEVICES)
9588 + nvram_mtd = NULL;
9589 +#endif
9590 +
9591 + /* Initialize hash table lock */
9592 + spin_lock_init(&nvram_lock);
9593 +
9594 + /* Initialize commit semaphore */
9595 + init_MUTEX(&nvram_sem);
9596 +
9597 + /* Register char device */
9598 + if ((nvram_major = devfs_register_chrdev(0, "nvram", &dev_nvram_fops)) < 0) {
9599 + ret = nvram_major;
9600 + goto err;
9601 + }
9602 +
9603 + /* Initialize hash table */
9604 + _nvram_init(sbh);
9605 +
9606 + /* Create /dev/nvram handle */
9607 + nvram_handle = devfs_register(NULL, "nvram", DEVFS_FL_NONE, nvram_major, 0,
9608 + S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, &dev_nvram_fops, NULL);
9609 +
9610 + /* Set the SDRAM NCDL value into NVRAM if not already done */
9611 + if (getintvar(NULL, "sdram_ncdl") == 0) {
9612 + unsigned int ncdl;
9613 + char buf[] = "0x00000000";
9614 +
9615 + if ((ncdl = sb_memc_get_ncdl(sbh))) {
9616 + sprintf(buf, "0x%08x", ncdl);
9617 + nvram_set("sdram_ncdl", buf);
9618 + nvram_commit();
9619 + }
9620 + }
9621 +
9622 + return 0;
9623 +
9624 + err:
9625 + dev_nvram_exit();
9626 + return ret;
9627 +}
9628 +
9629 +module_init(dev_nvram_init);
9630 +module_exit(dev_nvram_exit);
9631 diff -urN linux.old/arch/mips/bcm947xx/pcibios.c linux.dev/arch/mips/bcm947xx/pcibios.c
9632 --- linux.old/arch/mips/bcm947xx/pcibios.c 1970-01-01 01:00:00.000000000 +0100
9633 +++ linux.dev/arch/mips/bcm947xx/pcibios.c 2006-10-02 21:22:56.000000000 +0200
9634 @@ -0,0 +1,380 @@
9635 +/*
9636 + * Low-Level PCI and SB support for BCM47xx (Linux support code)
9637 + *
9638 + * Copyright 2006, Broadcom Corporation
9639 + * All Rights Reserved.
9640 + *
9641 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9642 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9643 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9644 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9645 + *
9646 + * $Id: pcibios.c,v 1.1.1.9 2006/02/27 03:42:55 honor Exp $
9647 + */
9648 +
9649 +#include <linux/config.h>
9650 +#include <linux/types.h>
9651 +#include <linux/kernel.h>
9652 +#include <linux/sched.h>
9653 +#include <linux/pci.h>
9654 +#include <linux/init.h>
9655 +#include <linux/delay.h>
9656 +#include <asm/io.h>
9657 +#include <asm/irq.h>
9658 +#include <asm/paccess.h>
9659 +
9660 +#include <typedefs.h>
9661 +#include <osl.h>
9662 +#include <bcmutils.h>
9663 +#include <sbconfig.h>
9664 +#include <sbutils.h>
9665 +#include <hndpci.h>
9666 +#include <pcicfg.h>
9667 +#include <bcmdevs.h>
9668 +#include <bcmnvram.h>
9669 +
9670 +/* Global SB handle */
9671 +extern sb_t *bcm947xx_sbh;
9672 +extern spinlock_t bcm947xx_sbh_lock;
9673 +
9674 +/* Convenience */
9675 +#define sbh bcm947xx_sbh
9676 +#define sbh_lock bcm947xx_sbh_lock
9677 +
9678 +static int
9679 +sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
9680 +{
9681 + unsigned long flags;
9682 + int ret;
9683 +
9684 + spin_lock_irqsave(&sbh_lock, flags);
9685 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9686 + PCI_FUNC(dev->devfn), where, value, sizeof(*value));
9687 + spin_unlock_irqrestore(&sbh_lock, flags);
9688 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9689 +}
9690 +
9691 +static int
9692 +sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value)
9693 +{
9694 + unsigned long flags;
9695 + int ret;
9696 +
9697 + spin_lock_irqsave(&sbh_lock, flags);
9698 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9699 + PCI_FUNC(dev->devfn), where, value, sizeof(*value));
9700 + spin_unlock_irqrestore(&sbh_lock, flags);
9701 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9702 +}
9703 +
9704 +static int
9705 +sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
9706 +{
9707 + unsigned long flags;
9708 + int ret;
9709 +
9710 + spin_lock_irqsave(&sbh_lock, flags);
9711 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9712 + PCI_FUNC(dev->devfn), where, value, sizeof(*value));
9713 + spin_unlock_irqrestore(&sbh_lock, flags);
9714 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9715 +}
9716 +
9717 +static int
9718 +sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value)
9719 +{
9720 + unsigned long flags;
9721 + int ret;
9722 +
9723 + spin_lock_irqsave(&sbh_lock, flags);
9724 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9725 + PCI_FUNC(dev->devfn), where, &value, sizeof(value));
9726 + spin_unlock_irqrestore(&sbh_lock, flags);
9727 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9728 +}
9729 +
9730 +static int
9731 +sbpci_write_config_word(struct pci_dev *dev, int where, u16 value)
9732 +{
9733 + unsigned long flags;
9734 + int ret;
9735 +
9736 + spin_lock_irqsave(&sbh_lock, flags);
9737 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9738 + PCI_FUNC(dev->devfn), where, &value, sizeof(value));
9739 + spin_unlock_irqrestore(&sbh_lock, flags);
9740 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9741 +}
9742 +
9743 +static int
9744 +sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value)
9745 +{
9746 + unsigned long flags;
9747 + int ret;
9748 +
9749 + spin_lock_irqsave(&sbh_lock, flags);
9750 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9751 + PCI_FUNC(dev->devfn), where, &value, sizeof(value));
9752 + spin_unlock_irqrestore(&sbh_lock, flags);
9753 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9754 +}
9755 +
9756 +static struct pci_ops pcibios_ops = {
9757 + sbpci_read_config_byte,
9758 + sbpci_read_config_word,
9759 + sbpci_read_config_dword,
9760 + sbpci_write_config_byte,
9761 + sbpci_write_config_word,
9762 + sbpci_write_config_dword
9763 +};
9764 +
9765 +
9766 +void __init
9767 +pcibios_init(void)
9768 +{
9769 + ulong flags;
9770 +
9771 + if (!(sbh = sb_kattach()))
9772 + panic("sb_kattach failed");
9773 + spin_lock_init(&sbh_lock);
9774 +
9775 + spin_lock_irqsave(&sbh_lock, flags);
9776 + sbpci_init(sbh);
9777 + spin_unlock_irqrestore(&sbh_lock, flags);
9778 +
9779 + set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
9780 +
9781 + /* Scan the SB bus */
9782 + pci_scan_bus(0, &pcibios_ops, NULL);
9783 +
9784 +}
9785 +
9786 +char * __init
9787 +pcibios_setup(char *str)
9788 +{
9789 + if (!strncmp(str, "ban=", 4)) {
9790 + sbpci_ban(simple_strtoul(str + 4, NULL, 0));
9791 + return NULL;
9792 + }
9793 +
9794 + return (str);
9795 +}
9796 +
9797 +static u32 pci_iobase = 0x100;
9798 +static u32 pci_membase = SB_PCI_DMA;
9799 +
9800 +void __init
9801 +pcibios_fixup_bus(struct pci_bus *b)
9802 +{
9803 + struct list_head *ln;
9804 + struct pci_dev *d;
9805 + struct resource *res;
9806 + int pos, size;
9807 + u32 *base;
9808 + u8 irq;
9809 +
9810 + printk("PCI: Fixing up bus %d\n", b->number);
9811 +
9812 + /* Fix up SB */
9813 + if (b->number == 0) {
9814 + for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
9815 + d = pci_dev_b(ln);
9816 + /* Fix up interrupt lines */
9817 + pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
9818 + d->irq = irq + 2;
9819 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
9820 + }
9821 + }
9822 +
9823 + /* Fix up external PCI */
9824 + else {
9825 + for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
9826 + d = pci_dev_b(ln);
9827 + /* Fix up resource bases */
9828 + for (pos = 0; pos < 6; pos++) {
9829 + res = &d->resource[pos];
9830 + base = (res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase;
9831 + if (res->end) {
9832 + size = res->end - res->start + 1;
9833 + if (*base & (size - 1))
9834 + *base = (*base + size) & ~(size - 1);
9835 + res->start = *base;
9836 + res->end = res->start + size - 1;
9837 + *base += size;
9838 + pci_write_config_dword(d,
9839 + PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
9840 + }
9841 + /* Fix up PCI bridge BAR0 only */
9842 + if (b->number == 1 && PCI_SLOT(d->devfn) == 0)
9843 + break;
9844 + }
9845 + /* Fix up interrupt lines */
9846 + if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
9847 + d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
9848 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
9849 + }
9850 + }
9851 +}
9852 +
9853 +unsigned int
9854 +pcibios_assign_all_busses(void)
9855 +{
9856 + return 1;
9857 +}
9858 +
9859 +void
9860 +pcibios_align_resource(void *data, struct resource *res,
9861 + unsigned long size, unsigned long align)
9862 +{
9863 +}
9864 +
9865 +int
9866 +pcibios_enable_resources(struct pci_dev *dev)
9867 +{
9868 + u16 cmd, old_cmd;
9869 + int idx;
9870 + struct resource *r;
9871 +
9872 + /* External PCI only */
9873 + if (dev->bus->number == 0)
9874 + return 0;
9875 +
9876 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
9877 + old_cmd = cmd;
9878 + for (idx = 0; idx < 6; idx++) {
9879 + r = &dev->resource[idx];
9880 + if (r->flags & IORESOURCE_IO)
9881 + cmd |= PCI_COMMAND_IO;
9882 + if (r->flags & IORESOURCE_MEM)
9883 + cmd |= PCI_COMMAND_MEMORY;
9884 + }
9885 + if (dev->resource[PCI_ROM_RESOURCE].start)
9886 + cmd |= PCI_COMMAND_MEMORY;
9887 + if (cmd != old_cmd) {
9888 + printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
9889 + pci_write_config_word(dev, PCI_COMMAND, cmd);
9890 + }
9891 + return 0;
9892 +}
9893 +
9894 +int
9895 +pcibios_enable_device(struct pci_dev *dev, int mask)
9896 +{
9897 + ulong flags;
9898 + uint coreidx;
9899 + void *regs;
9900 +
9901 + /* External PCI device enable */
9902 + if (dev->bus->number != 0)
9903 + return pcibios_enable_resources(dev);
9904 +
9905 + /* These cores come out of reset enabled */
9906 + if (dev->device == SB_MIPS ||
9907 + dev->device == SB_MIPS33 ||
9908 + dev->device == SB_EXTIF ||
9909 + dev->device == SB_CC)
9910 + return 0;
9911 +
9912 + spin_lock_irqsave(&sbh_lock, flags);
9913 + coreidx = sb_coreidx(sbh);
9914 + regs = sb_setcoreidx(sbh, PCI_SLOT(dev->devfn));
9915 + if (!regs)
9916 + return PCIBIOS_DEVICE_NOT_FOUND;
9917 +
9918 + /*
9919 + * The USB core requires a special bit to be set during core
9920 + * reset to enable host (OHCI) mode. Resetting the SB core in
9921 + * pcibios_enable_device() is a hack for compatibility with
9922 + * vanilla usb-ohci so that it does not have to know about
9923 + * SB. A driver that wants to use the USB core in device mode
9924 + * should know about SB and should reset the bit back to 0
9925 + * after calling pcibios_enable_device().
9926 + */
9927 + if (sb_coreid(sbh) == SB_USB) {
9928 + sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
9929 + sb_core_reset(sbh, 1 << 29, 0);
9930 + }
9931 + /*
9932 + * USB 2.0 special considerations:
9933 + *
9934 + * 1. Since the core supports both OHCI and EHCI functions, it must
9935 + * only be reset once.
9936 + *
9937 + * 2. In addition to the standard SB reset sequence, the Host Control
9938 + * Register must be programmed to bring the USB core and various
9939 + * phy components out of reset.
9940 + */
9941 + else if (sb_coreid(sbh) == SB_USB20H) {
9942 + if (!sb_iscoreup(sbh)) {
9943 + sb_core_reset(sbh, 0, 0);
9944 + writel(0x7FF, (ulong)regs + 0x200);
9945 + udelay(1);
9946 + }
9947 + } else
9948 + sb_core_reset(sbh, 0, 0);
9949 +
9950 + sb_setcoreidx(sbh, coreidx);
9951 + spin_unlock_irqrestore(&sbh_lock, flags);
9952 +
9953 + return 0;
9954 +}
9955 +
9956 +void
9957 +pcibios_update_resource(struct pci_dev *dev, struct resource *root,
9958 + struct resource *res, int resource)
9959 +{
9960 + unsigned long where, size;
9961 + u32 reg;
9962 +
9963 + /* External PCI only */
9964 + if (dev->bus->number == 0)
9965 + return;
9966 +
9967 + where = PCI_BASE_ADDRESS_0 + (resource * 4);
9968 + size = res->end - res->start;
9969 + pci_read_config_dword(dev, where, &reg);
9970 + reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
9971 + pci_write_config_dword(dev, where, reg);
9972 +}
9973 +
9974 +static void __init
9975 +quirk_sbpci_bridge(struct pci_dev *dev)
9976 +{
9977 + if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
9978 + return;
9979 +
9980 + printk("PCI: Fixing up bridge\n");
9981 +
9982 + /* Enable PCI bridge bus mastering and memory space */
9983 + pci_set_master(dev);
9984 + pcibios_enable_resources(dev);
9985 +
9986 + /* Enable PCI bridge BAR1 prefetch and burst */
9987 + pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
9988 +}
9989 +
9990 +struct pci_fixup pcibios_fixups[] = {
9991 + { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge },
9992 + { 0 }
9993 +};
9994 +
9995 +/*
9996 + * If we set up a device for bus mastering, we need to check the latency
9997 + * timer as certain crappy BIOSes forget to set it properly.
9998 + */
9999 +unsigned int pcibios_max_latency = 255;
10000 +
10001 +void pcibios_set_master(struct pci_dev *dev)
10002 +{
10003 + u8 lat;
10004 + pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
10005 + if (lat < 16)
10006 + lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
10007 + else if (lat > pcibios_max_latency)
10008 + lat = pcibios_max_latency;
10009 + else
10010 + return;
10011 + printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
10012 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
10013 +}
10014 +
10015 diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.c
10016 --- linux.old/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
10017 +++ linux.dev/arch/mips/bcm947xx/prom.c 2006-10-02 21:19:59.000000000 +0200
10018 @@ -0,0 +1,41 @@
10019 +/*
10020 + * Early initialization code for BCM94710 boards
10021 + *
10022 + * Copyright 2004, Broadcom Corporation
10023 + * All Rights Reserved.
10024 + *
10025 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10026 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10027 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10028 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10029 + *
10030 + * $Id: prom.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
10031 + */
10032 +
10033 +#include <linux/config.h>
10034 +#include <linux/init.h>
10035 +#include <linux/kernel.h>
10036 +#include <linux/types.h>
10037 +#include <asm/bootinfo.h>
10038 +
10039 +void __init
10040 +prom_init(int argc, const char **argv)
10041 +{
10042 + unsigned long mem;
10043 +
10044 + mips_machgroup = MACH_GROUP_BRCM;
10045 + mips_machtype = MACH_BCM947XX;
10046 +
10047 + /* Figure out memory size by finding aliases */
10048 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
10049 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
10050 + *(unsigned long *)(prom_init))
10051 + break;
10052 + }
10053 + add_memory_region(0, mem, BOOT_MEM_RAM);
10054 +}
10055 +
10056 +void __init
10057 +prom_free_prom_memory(void)
10058 +{
10059 +}
10060 diff -urN linux.old/arch/mips/bcm947xx/sbmips.c linux.dev/arch/mips/bcm947xx/sbmips.c
10061 --- linux.old/arch/mips/bcm947xx/sbmips.c 1970-01-01 01:00:00.000000000 +0100
10062 +++ linux.dev/arch/mips/bcm947xx/sbmips.c 2006-10-02 21:19:59.000000000 +0200
10063 @@ -0,0 +1,1132 @@
10064 +/*
10065 + * BCM47XX Sonics SiliconBackplane MIPS core routines
10066 + *
10067 + * Copyright 2006, Broadcom Corporation
10068 + * All Rights Reserved.
10069 + *
10070 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10071 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10072 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10073 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10074 + *
10075 + * $Id: hndmips.c,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
10076 + */
10077 +
10078 +#include <typedefs.h>
10079 +#include <bcmdefs.h>
10080 +#include <osl.h>
10081 +#include <bcmutils.h>
10082 +#include <sbutils.h>
10083 +#include <bcmdevs.h>
10084 +#include <bcmnvram.h>
10085 +#include <sbconfig.h>
10086 +#include <sbextif.h>
10087 +#include <sbchipc.h>
10088 +#include <sbmemc.h>
10089 +#include <mipsinc.h>
10090 +#include <sbhndmips.h>
10091 +#include <hndcpu.h>
10092 +
10093 +/* sbipsflag register format, indexed by irq. */
10094 +static const uint32 sbips_int_mask[] = {
10095 + 0, /* placeholder */
10096 + SBIPS_INT1_MASK,
10097 + SBIPS_INT2_MASK,
10098 + SBIPS_INT3_MASK,
10099 + SBIPS_INT4_MASK
10100 +};
10101 +
10102 +static const uint32 sbips_int_shift[] = {
10103 + 0, /* placeholder */
10104 + SBIPS_INT1_SHIFT,
10105 + SBIPS_INT2_SHIFT,
10106 + SBIPS_INT3_SHIFT,
10107 + SBIPS_INT4_SHIFT
10108 +};
10109 +
10110 +/*
10111 + * Map SB cores sharing the MIPS hardware IRQ0 to virtual dedicated OS IRQs.
10112 + * Per-port BSP code is required to provide necessary translations between
10113 + * the shared MIPS IRQ and the virtual OS IRQs based on SB core flag.
10114 + *
10115 + * See sb_irq() for the mapping.
10116 + */
10117 +static uint shirq_map_base = 0;
10118 +
10119 +/* Returns the SB interrupt flag of the current core. */
10120 +static uint32
10121 +sb_getflag(sb_t *sbh)
10122 +{
10123 + osl_t *osh;
10124 + void *regs;
10125 + sbconfig_t *sb;
10126 +
10127 + osh = sb_osh(sbh);
10128 + regs = sb_coreregs(sbh);
10129 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10130 +
10131 + return (R_REG(osh, &sb->sbtpsflag) & SBTPS_NUM0_MASK);
10132 +}
10133 +
10134 +/*
10135 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
10136 + * 0 is returned.
10137 + */
10138 +uint
10139 +sb_irq(sb_t *sbh)
10140 +{
10141 + osl_t *osh;
10142 + uint idx;
10143 + void *regs;
10144 + sbconfig_t *sb;
10145 + uint32 flag, sbipsflag;
10146 + uint irq = 0;
10147 +
10148 + osh = sb_osh(sbh);
10149 + flag = sb_getflag(sbh);
10150 +
10151 + idx = sb_coreidx(sbh);
10152 +
10153 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
10154 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
10155 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10156 +
10157 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
10158 + sbipsflag = R_REG(osh, &sb->sbipsflag);
10159 + for (irq = 1; irq <= 4; irq++) {
10160 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
10161 + break;
10162 + }
10163 + if (irq == 5)
10164 + irq = 0;
10165 + }
10166 +
10167 + sb_setcoreidx(sbh, idx);
10168 +
10169 + return irq;
10170 +}
10171 +
10172 +/* Clears the specified MIPS IRQ. */
10173 +static void
10174 +BCMINITFN(sb_clearirq)(sb_t *sbh, uint irq)
10175 +{
10176 + osl_t *osh;
10177 + void *regs;
10178 + sbconfig_t *sb;
10179 +
10180 + osh = sb_osh(sbh);
10181 +
10182 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
10183 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
10184 + ASSERT(regs);
10185 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10186 +
10187 + if (irq == 0)
10188 + W_REG(osh, &sb->sbintvec, 0);
10189 + else
10190 + OR_REG(osh, &sb->sbipsflag, sbips_int_mask[irq]);
10191 +}
10192 +
10193 +/*
10194 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
10195 + * IRQ 0 may be assigned more than once.
10196 + *
10197 + * The old assignment to the specified core is removed first.
10198 + */
10199 +static void
10200 +BCMINITFN(sb_setirq)(sb_t *sbh, uint irq, uint coreid, uint coreunit)
10201 +{
10202 + osl_t *osh;
10203 + void *regs;
10204 + sbconfig_t *sb;
10205 + uint32 flag;
10206 + uint oldirq;
10207 +
10208 + osh = sb_osh(sbh);
10209 +
10210 + regs = sb_setcore(sbh, coreid, coreunit);
10211 + ASSERT(regs);
10212 + flag = sb_getflag(sbh);
10213 + oldirq = sb_irq(sbh);
10214 + if (oldirq)
10215 + sb_clearirq(sbh, oldirq);
10216 +
10217 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
10218 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
10219 + ASSERT(regs);
10220 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10221 +
10222 + if (!oldirq)
10223 + AND_REG(osh, &sb->sbintvec, ~(1 << flag));
10224 +
10225 + if (irq == 0)
10226 + OR_REG(osh, &sb->sbintvec, 1 << flag);
10227 + else {
10228 + flag <<= sbips_int_shift[irq];
10229 + ASSERT(!(flag & ~sbips_int_mask[irq]));
10230 + flag |= R_REG(osh, &sb->sbipsflag) & ~sbips_int_mask[irq];
10231 + W_REG(osh, &sb->sbipsflag, flag);
10232 + }
10233 +}
10234 +
10235 +/*
10236 + * Initializes clocks and interrupts. SB and NVRAM access must be
10237 + * initialized prior to calling.
10238 + *
10239 + * 'shirqmap' enables virtual dedicated OS IRQ mapping if non-zero.
10240 + */
10241 +void
10242 +BCMINITFN(sb_mips_init)(sb_t *sbh, uint shirqmap)
10243 +{
10244 + osl_t *osh;
10245 + ulong hz, ns, tmp;
10246 + extifregs_t *eir;
10247 + chipcregs_t *cc;
10248 + char *value;
10249 + uint irq;
10250 +
10251 + osh = sb_osh(sbh);
10252 +
10253 + /* Figure out current SB clock speed */
10254 + if ((hz = sb_clock(sbh)) == 0)
10255 + hz = 100000000;
10256 + ns = 1000000000 / hz;
10257 +
10258 + /* Setup external interface timing */
10259 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
10260 + /* Initialize extif so we can get to the LEDs and external UART */
10261 + W_REG(osh, &eir->prog_config, CF_EN);
10262 +
10263 + /* Set timing for the flash */
10264 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10265 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
10266 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
10267 + W_REG(osh, &eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
10268 +
10269 + /* Set programmable interface timing for external uart */
10270 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10271 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
10272 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
10273 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
10274 + W_REG(osh, &eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
10275 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
10276 + /* Set timing for the flash */
10277 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10278 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
10279 + tmp |= CEIL(120, ns); /* W0 = 120nS */
10280 + if ((sb_corerev(sbh) < 9) ||
10281 + (BCMINIT(sb_chip)(sbh) == 0x5365))
10282 + W_REG(osh, &cc->flash_waitcount, tmp);
10283 +
10284 + if ((sb_corerev(sbh) < 9) ||
10285 + ((sb_chip(sbh) == BCM5350_CHIP_ID) && sb_chiprev(sbh) == 0) ||
10286 + (BCMINIT(sb_chip)(sbh) == 0x5365)) {
10287 + W_REG(osh, &cc->pcmcia_memwait, tmp);
10288 + }
10289 +
10290 + /* Save shared IRQ mapping base */
10291 + shirq_map_base = shirqmap;
10292 + }
10293 +
10294 + /* Chip specific initialization */
10295 + switch (sb_chip(sbh)) {
10296 + case BCM4710_CHIP_ID:
10297 + /* Clear interrupt map */
10298 + for (irq = 0; irq <= 4; irq++)
10299 + sb_clearirq(sbh, irq);
10300 + sb_setirq(sbh, 0, SB_CODEC, 0);
10301 + sb_setirq(sbh, 0, SB_EXTIF, 0);
10302 + sb_setirq(sbh, 2, SB_ENET, 1);
10303 + sb_setirq(sbh, 3, SB_ILINE20, 0);
10304 + sb_setirq(sbh, 4, SB_PCI, 0);
10305 + ASSERT(eir);
10306 + value = nvram_get("et0phyaddr");
10307 + if (value && !strcmp(value, "31")) {
10308 + /* Enable internal UART */
10309 + W_REG(osh, &eir->corecontrol, CC_UE);
10310 + /* Give USB its own interrupt */
10311 + sb_setirq(sbh, 1, SB_USB, 0);
10312 + } else {
10313 + /* Disable internal UART */
10314 + W_REG(osh, &eir->corecontrol, 0);
10315 + /* Give Ethernet its own interrupt */
10316 + sb_setirq(sbh, 1, SB_ENET, 0);
10317 + sb_setirq(sbh, 0, SB_USB, 0);
10318 + }
10319 + break;
10320 + case BCM5350_CHIP_ID:
10321 + /* Clear interrupt map */
10322 + for (irq = 0; irq <= 4; irq++)
10323 + sb_clearirq(sbh, irq);
10324 + sb_setirq(sbh, 0, SB_CC, 0);
10325 + sb_setirq(sbh, 0, SB_MIPS33, 0);
10326 + sb_setirq(sbh, 1, SB_D11, 0);
10327 + sb_setirq(sbh, 2, SB_ENET, 0);
10328 + sb_setirq(sbh, 3, SB_PCI, 0);
10329 + sb_setirq(sbh, 4, SB_USB, 0);
10330 + break;
10331 + case BCM4785_CHIP_ID:
10332 + /* Reassign PCI to irq 4 */
10333 + sb_setirq(sbh, 4, SB_PCI, 0);
10334 + break;
10335 + }
10336 +}
10337 +
10338 +uint32
10339 +BCMINITFN(sb_cpu_clock)(sb_t *sbh)
10340 +{
10341 + extifregs_t *eir;
10342 + chipcregs_t *cc;
10343 + uint32 n, m;
10344 + uint idx;
10345 + uint32 pll_type, rate = 0;
10346 +
10347 + /* get index of the current core */
10348 + idx = sb_coreidx(sbh);
10349 + pll_type = PLL_TYPE1;
10350 +
10351 + /* switch to extif or chipc core */
10352 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
10353 + n = R_REG(osh, &eir->clockcontrol_n);
10354 + m = R_REG(osh, &eir->clockcontrol_sb);
10355 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
10356 + pll_type = R_REG(osh, &cc->capabilities) & CAP_PLL_MASK;
10357 + n = R_REG(osh, &cc->clockcontrol_n);
10358 + if ((pll_type == PLL_TYPE2) ||
10359 + (pll_type == PLL_TYPE4) ||
10360 + (pll_type == PLL_TYPE6) ||
10361 + (pll_type == PLL_TYPE7))
10362 + m = R_REG(osh, &cc->clockcontrol_m3);
10363 + else if (pll_type == PLL_TYPE5) {
10364 + rate = 200000000;
10365 + goto out;
10366 + }
10367 + else if (pll_type == PLL_TYPE3) {
10368 + if (sb_chip(sbh) == BCM5365_CHIP_ID) {
10369 + rate = 200000000;
10370 + goto out;
10371 + }
10372 + /* 5350 uses m2 to control mips */
10373 + else
10374 + m = R_REG(osh, &cc->clockcontrol_m2);
10375 + } else
10376 + m = R_REG(osh, &cc->clockcontrol_sb);
10377 + } else
10378 + goto out;
10379 +
10380 +
10381 + /* calculate rate */
10382 + if (BCMINIT(sb_chip)(sbh) == 0x5365)
10383 + rate = 100000000;
10384 + else
10385 + rate = sb_clock_rate(pll_type, n, m);
10386 +
10387 + if (pll_type == PLL_TYPE6)
10388 + rate = SB2MIPS_T6(rate);
10389 +
10390 +out:
10391 + /* switch back to previous core */
10392 + sb_setcoreidx(sbh, idx);
10393 +
10394 + return rate;
10395 +}
10396 +
10397 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
10398 +
10399 +static void
10400 +BCMINITFN(handler)(void)
10401 +{
10402 + __asm__(
10403 + ".set\tmips32\n\t"
10404 + "ssnop\n\t"
10405 + "ssnop\n\t"
10406 + /* Disable interrupts */
10407 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
10408 + "mfc0 $15, $12\n\t"
10409 + /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */
10410 + "li $14, -31746\n\t"
10411 + "and $15, $15, $14\n\t"
10412 + "mtc0 $15, $12\n\t"
10413 + "eret\n\t"
10414 + "nop\n\t"
10415 + "nop\n\t"
10416 + ".set\tmips0");
10417 +}
10418 +
10419 +/* The following MUST come right after handler() */
10420 +static void
10421 +BCMINITFN(afterhandler)(void)
10422 +{
10423 +}
10424 +
10425 +/*
10426 + * Set the MIPS, backplane and PCI clocks as closely as possible.
10427 + *
10428 + * MIPS clocks synchronization function has been moved from PLL in chipcommon
10429 + * core rev. 15 to a DLL inside the MIPS core in 4785.
10430 + */
10431 +bool
10432 +BCMINITFN(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
10433 +{
10434 + extifregs_t *eir = NULL;
10435 + chipcregs_t *cc = NULL;
10436 + mipsregs_t *mipsr = NULL;
10437 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, *clockcontrol_m2;
10438 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, orig_ratio_cfg;
10439 + uint32 pll_type, sync_mode;
10440 + uint ic_size, ic_lsize;
10441 + uint idx, i;
10442 +
10443 + /* PLL configuration: type 1 */
10444 + typedef struct {
10445 + uint32 mipsclock;
10446 + uint16 n;
10447 + uint32 sb;
10448 + uint32 pci33;
10449 + uint32 pci25;
10450 + } n3m_table_t;
10451 + static n3m_table_t BCMINITDATA(type1_table)[] = {
10452 + /* 96.000 32.000 24.000 */
10453 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 },
10454 + /* 100.000 33.333 25.000 */
10455 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 },
10456 + /* 104.000 31.200 24.960 */
10457 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 },
10458 + /* 108.000 32.400 24.923 */
10459 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 },
10460 + /* 112.000 32.000 24.889 */
10461 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 },
10462 + /* 115.200 32.000 24.000 */
10463 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 },
10464 + /* 120.000 30.000 24.000 */
10465 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 },
10466 + /* 124.800 31.200 24.960 */
10467 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 },
10468 + /* 128.000 32.000 24.000 */
10469 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 },
10470 + /* 132.000 33.000 24.750 */
10471 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 },
10472 + /* 136.000 32.640 24.727 */
10473 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 },
10474 + /* 140.000 30.000 24.706 */
10475 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 },
10476 + /* 144.000 30.857 24.686 */
10477 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 },
10478 + /* 150.857 33.000 24.000 */
10479 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 },
10480 + /* 152.000 32.571 24.000 */
10481 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 },
10482 + /* 156.000 31.200 24.960 */
10483 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 },
10484 + /* 160.000 32.000 24.000 */
10485 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 },
10486 + /* 163.200 32.640 24.727 */
10487 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 },
10488 + /* 168.000 32.000 24.889 */
10489 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 },
10490 + /* 176.000 33.000 24.000 */
10491 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 },
10492 + };
10493 +
10494 + /* PLL configuration: type 3 */
10495 + typedef struct {
10496 + uint32 mipsclock;
10497 + uint16 n;
10498 + uint32 m2; /* that is the clockcontrol_m2 */
10499 + } type3_table_t;
10500 + static type3_table_t type3_table[] = {
10501 + /* for 5350, mips clock is always double sb clock */
10502 + { 150000000, 0x311, 0x4020005 },
10503 + { 200000000, 0x311, 0x4020003 },
10504 + };
10505 +
10506 + /* PLL configuration: type 2, 4, 7 */
10507 + typedef struct {
10508 + uint32 mipsclock;
10509 + uint32 sbclock;
10510 + uint16 n;
10511 + uint32 sb;
10512 + uint32 pci33;
10513 + uint32 m2;
10514 + uint32 m3;
10515 + uint32 ratio_cfg;
10516 + uint32 ratio_parm;
10517 + uint32 d11_r1;
10518 + uint32 d11_r2;
10519 + } n4m_table_t;
10520 + static n4m_table_t BCMINITDATA(type2_table)[] = {
10521 + { 120000000, 60000000, 0x0303, 0x01000200, 0x01000600, 0x01000200, 0x05000200, 11,
10522 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10523 + { 150000000, 75000000, 0x0303, 0x01000100, 0x01000600, 0x01000100, 0x05000100, 11,
10524 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10525 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 8,
10526 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10527 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 11,
10528 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10529 + { 200000000, 100000000, 0x0303, 0x02010000, 0x02040001, 0x02010000, 0x06000001, 11,
10530 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10531 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11,
10532 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10533 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11,
10534 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10535 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11,
10536 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10537 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 8,
10538 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10539 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11,
10540 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10541 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 11,
10542 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10543 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 11,
10544 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10545 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8,
10546 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10547 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8,
10548 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10549 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11,
10550 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10551 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8,
10552 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10553 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11,
10554 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10555 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01010100, 0x05000100, 8,
10556 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10557 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01010100, 0x05000100, 11,
10558 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10559 + { 330000000, 132000000, 0x0903, 0x01000200, 0x00020200, 0x01010100, 0x05000100, 0,
10560 + 0, 10 /* ratio 4/10 */, 0x02520129 },
10561 + { 330000000, 146666666, 0x0903, 0x01010000, 0x00020200, 0x01010100, 0x05000100, 0,
10562 + 0, 9 /* ratio 4/9 */, 0x012a00a9 },
10563 + { 330000000, 165000000, 0x0903, 0x01000100, 0x00020200, 0x01010100, 0x05000100, 0,
10564 + 0, 8 /* ratio 4/8 */, 0x00aa0055 },
10565 + { 360000000, 120000000, 0x0a03, 0x01000300, 0x00010201, 0x01010200, 0x05000100, 0,
10566 + 0, 12 /* ratio 4/12 */, 0x04920492 },
10567 + { 360000000, 144000000, 0x0a03, 0x01000200, 0x00010201, 0x01010200, 0x05000100, 0,
10568 + 0, 10 /* ratio 4/10 */, 0x02520129 },
10569 + { 360000000, 160000000, 0x0a03, 0x01010000, 0x00010201, 0x01010200, 0x05000100, 0,
10570 + 0, 9 /* ratio 4/9 */, 0x012a00a9 },
10571 + { 360000000, 180000000, 0x0a03, 0x01000100, 0x00010201, 0x01010200, 0x05000100, 0,
10572 + 0, 8 /* ratio 4/8 */, 0x00aa0055 },
10573 + { 390000000, 130000000, 0x0b03, 0x01010100, 0x00020101, 0x01020100, 0x05000100, 0,
10574 + 0, 12 /* ratio 4/12 */, 0x04920492 },
10575 + { 390000000, 156000000, 0x0b03, 0x01000200, 0x00020101, 0x01020100, 0x05000100, 0,
10576 + 0, 10 /* ratio 4/10 */, 0x02520129 },
10577 + { 390000000, 173000000, 0x0b03, 0x01010000, 0x00020101, 0x01020100, 0x05000100, 0,
10578 + 0, 9 /* ratio 4/9 */, 0x012a00a9 },
10579 + { 390000000, 195000000, 0x0b03, 0x01000100, 0x00020101, 0x01020100, 0x05000100, 0,
10580 + 0, 8 /* ratio 4/8 */, 0x00aa0055 },
10581 + };
10582 + static n4m_table_t BCMINITDATA(type4_table)[] = {
10583 + { 120000000, 60000000, 0x0009, 0x11020009, 0x01030203, 0x11020009, 0x04000009, 11,
10584 + 0x0aaa0555 },
10585 + { 150000000, 75000000, 0x0009, 0x11050002, 0x01030203, 0x11050002, 0x04000005, 11,
10586 + 0x0aaa0555 },
10587 + { 192000000, 96000000, 0x0702, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11,
10588 + 0x0aaa0555 },
10589 + { 198000000, 99000000, 0x0603, 0x11020005, 0x11030011, 0x11020005, 0x04000005, 11,
10590 + 0x0aaa0555 },
10591 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11,
10592 + 0x0aaa0555 },
10593 + { 204000000, 102000000, 0x0c02, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10594 + 0x0aaa0555 },
10595 + { 208000000, 104000000, 0x0802, 0x11030002, 0x11090005, 0x11030002, 0x04000003, 11,
10596 + 0x0aaa0555 },
10597 + { 210000000, 105000000, 0x0209, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10598 + 0x0aaa0555 },
10599 + { 216000000, 108000000, 0x0111, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10600 + 0x0aaa0555 },
10601 + { 224000000, 112000000, 0x0205, 0x11030002, 0x02002103, 0x11030002, 0x04000003, 11,
10602 + 0x0aaa0555 },
10603 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x01030305, 0x04000005, 8,
10604 + 0x012a00a9 },
10605 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11,
10606 + 0x0aaa0555 },
10607 + { 240000000, 102857143, 0x0109, 0x04000021, 0x01050203, 0x11030021, 0x04000003, 13,
10608 + 0x254a14a9 },
10609 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 11,
10610 + 0x0aaa0555 },
10611 + { 252000000, 100800000, 0x0203, 0x04000009, 0x11050005, 0x02000209, 0x04000002, 9,
10612 + 0x02520129 },
10613 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11,
10614 + 0x0aaa0555 },
10615 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11,
10616 + 0x0aaa0555 },
10617 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 13,
10618 + 0x254a14a9 },
10619 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13,
10620 + 0x254a14a9 },
10621 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13,
10622 + 0x254a14a9 },
10623 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 9,
10624 + 0x02520129 },
10625 + { 300000000, 150000000, 0x0009, 0x04000005, 0x01030203, 0x04000005, 0x04000002, 11,
10626 + 0x0aaa0555 }
10627 + };
10628 + static n4m_table_t BCMINITDATA(type7_table)[] = {
10629 + { 183333333, 91666666, 0x0605, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11,
10630 + 0x0aaa0555 },
10631 + { 187500000, 93750000, 0x0a03, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11,
10632 + 0x0aaa0555 },
10633 + { 196875000, 98437500, 0x1003, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11,
10634 + 0x0aaa0555 },
10635 + { 200000000, 100000000, 0x0311, 0x04000011, 0x11030011, 0x04000009, 0x04000003, 11,
10636 + 0x0aaa0555 },
10637 + { 200000000, 100000000, 0x0311, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11,
10638 + 0x0aaa0555 },
10639 + { 206250000, 103125000, 0x1103, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11,
10640 + 0x0aaa0555 },
10641 + { 212500000, 106250000, 0x0c05, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10642 + 0x0aaa0555 },
10643 + { 215625000, 107812500, 0x1203, 0x11090009, 0x11050005, 0x11020005, 0x04000005, 11,
10644 + 0x0aaa0555 },
10645 + { 216666666, 108333333, 0x0805, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11,
10646 + 0x0aaa0555 },
10647 + { 225000000, 112500000, 0x0d03, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11,
10648 + 0x0aaa0555 },
10649 + { 233333333, 116666666, 0x0905, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11,
10650 + 0x0aaa0555 },
10651 + { 237500000, 118750000, 0x0e05, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11,
10652 + 0x0aaa0555 },
10653 + { 240000000, 120000000, 0x0b11, 0x11020009, 0x11210009, 0x11020009, 0x04000009, 11,
10654 + 0x0aaa0555 },
10655 + { 250000000, 125000000, 0x0f03, 0x11020003, 0x11210003, 0x11020003, 0x04000003, 11,
10656 + 0x0aaa0555 }
10657 + };
10658 +
10659 + ulong start, end, dst;
10660 + bool ret = FALSE;
10661 +
10662 + volatile uint32 *dll_ctrl = (volatile uint32 *)0xff400008;
10663 + volatile uint32 *dll_r1 = (volatile uint32 *)0xff400010;
10664 + volatile uint32 *dll_r2 = (volatile uint32 *)0xff400018;
10665 +
10666 + /* get index of the current core */
10667 + idx = sb_coreidx(sbh);
10668 + clockcontrol_m2 = NULL;
10669 +
10670 + /* switch to extif or chipc core */
10671 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
10672 + pll_type = PLL_TYPE1;
10673 + clockcontrol_n = &eir->clockcontrol_n;
10674 + clockcontrol_sb = &eir->clockcontrol_sb;
10675 + clockcontrol_pci = &eir->clockcontrol_pci;
10676 + clockcontrol_m2 = &cc->clockcontrol_m2;
10677 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
10678 + pll_type = R_REG(osh, &cc->capabilities) & CAP_PLL_MASK;
10679 + if (pll_type == PLL_TYPE6) {
10680 + clockcontrol_n = NULL;
10681 + clockcontrol_sb = NULL;
10682 + clockcontrol_pci = NULL;
10683 + } else {
10684 + clockcontrol_n = &cc->clockcontrol_n;
10685 + clockcontrol_sb = &cc->clockcontrol_sb;
10686 + clockcontrol_pci = &cc->clockcontrol_pci;
10687 + clockcontrol_m2 = &cc->clockcontrol_m2;
10688 + }
10689 + } else
10690 + goto done;
10691 +
10692 + if (pll_type == PLL_TYPE6) {
10693 + /* Silence compilers */
10694 + orig_n = orig_sb = orig_pci = 0;
10695 + } else {
10696 + /* Store the current clock register values */
10697 + orig_n = R_REG(osh, clockcontrol_n);
10698 + orig_sb = R_REG(osh, clockcontrol_sb);
10699 + orig_pci = R_REG(osh, clockcontrol_pci);
10700 + }
10701 +
10702 + if (pll_type == PLL_TYPE1) {
10703 + /* Keep the current PCI clock if not specified */
10704 + if (pciclock == 0) {
10705 + pciclock = sb_clock_rate(pll_type, R_REG(osh, clockcontrol_n),
10706 + R_REG(osh, clockcontrol_pci));
10707 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
10708 + }
10709 +
10710 + /* Search for the closest MIPS clock less than or equal to a preferred value */
10711 + for (i = 0; i < ARRAYSIZE(type1_table); i++) {
10712 + ASSERT(type1_table[i].mipsclock ==
10713 + sb_clock_rate(pll_type, type1_table[i].n,
10714 + type1_table[i].sb));
10715 + if (type1_table[i].mipsclock > mipsclock)
10716 + break;
10717 + }
10718 + if (i == 0) {
10719 + ret = FALSE;
10720 + goto done;
10721 + } else {
10722 + ret = TRUE;
10723 + i--;
10724 + }
10725 + ASSERT(type1_table[i].mipsclock <= mipsclock);
10726 +
10727 + /* No PLL change */
10728 + if ((orig_n == type1_table[i].n) &&
10729 + (orig_sb == type1_table[i].sb) &&
10730 + (orig_pci == type1_table[i].pci33))
10731 + goto done;
10732 +
10733 + /* Set the PLL controls */
10734 + W_REG(osh, clockcontrol_n, type1_table[i].n);
10735 + W_REG(osh, clockcontrol_sb, type1_table[i].sb);
10736 + if (pciclock == 25000000)
10737 + W_REG(osh, clockcontrol_pci, type1_table[i].pci25);
10738 + else
10739 + W_REG(osh, clockcontrol_pci, type1_table[i].pci33);
10740 +
10741 + /* Reset */
10742 + sb_watchdog(sbh, 1);
10743 + while (1);
10744 + } else if (pll_type == PLL_TYPE3) {
10745 + /* 5350 */
10746 + if (sb_chip(sbh) != BCM5365_CHIP_ID) {
10747 + /*
10748 + * Search for the closest MIPS clock less than or equal to
10749 + * a preferred value.
10750 + */
10751 + for (i = 0; i < ARRAYSIZE(type3_table); i++) {
10752 + if (type3_table[i].mipsclock > mipsclock)
10753 + break;
10754 + }
10755 + if (i == 0) {
10756 + ret = FALSE;
10757 + goto done;
10758 + } else {
10759 + ret = TRUE;
10760 + i--;
10761 + }
10762 + ASSERT(type3_table[i].mipsclock <= mipsclock);
10763 +
10764 + /* No PLL change */
10765 + orig_m2 = R_REG(osh, &cc->clockcontrol_m2);
10766 + if ((orig_n == type3_table[i].n) &&
10767 + (orig_m2 == type3_table[i].m2)) {
10768 + goto done;
10769 + }
10770 +
10771 + /* Set the PLL controls */
10772 + W_REG(osh, clockcontrol_n, type3_table[i].n);
10773 + W_REG(osh, clockcontrol_m2, type3_table[i].m2);
10774 +
10775 + /* Reset */
10776 + sb_watchdog(sbh, 1);
10777 + while (1);
10778 + }
10779 + } else if ((pll_type == PLL_TYPE2) ||
10780 + (pll_type == PLL_TYPE4) ||
10781 + (pll_type == PLL_TYPE6) ||
10782 + (pll_type == PLL_TYPE7)) {
10783 + n4m_table_t *table = NULL, *te;
10784 + uint tabsz = 0;
10785 +
10786 + ASSERT(cc);
10787 +
10788 + orig_mips = R_REG(osh, &cc->clockcontrol_m3);
10789 +
10790 + switch (pll_type) {
10791 + case PLL_TYPE6: {
10792 + uint32 new_mips = 0;
10793 +
10794 + ret = TRUE;
10795 + if (mipsclock <= SB2MIPS_T6(CC_T6_M1))
10796 + new_mips = CC_T6_MMASK;
10797 +
10798 + if (orig_mips == new_mips)
10799 + goto done;
10800 +
10801 + W_REG(osh, &cc->clockcontrol_m3, new_mips);
10802 + goto end_fill;
10803 + }
10804 + case PLL_TYPE2:
10805 + table = type2_table;
10806 + tabsz = ARRAYSIZE(type2_table);
10807 + break;
10808 + case PLL_TYPE4:
10809 + table = type4_table;
10810 + tabsz = ARRAYSIZE(type4_table);
10811 + break;
10812 + case PLL_TYPE7:
10813 + table = type7_table;
10814 + tabsz = ARRAYSIZE(type7_table);
10815 + break;
10816 + default:
10817 + ASSERT("No table for plltype" == NULL);
10818 + break;
10819 + }
10820 +
10821 + /* Store the current clock register values */
10822 + orig_m2 = R_REG(osh, &cc->clockcontrol_m2);
10823 + orig_ratio_parm = 0;
10824 + orig_ratio_cfg = 0;
10825 +
10826 + /* Look up current ratio */
10827 + for (i = 0; i < tabsz; i++) {
10828 + if ((orig_n == table[i].n) &&
10829 + (orig_sb == table[i].sb) &&
10830 + (orig_pci == table[i].pci33) &&
10831 + (orig_m2 == table[i].m2) &&
10832 + (orig_mips == table[i].m3)) {
10833 + orig_ratio_parm = table[i].ratio_parm;
10834 + orig_ratio_cfg = table[i].ratio_cfg;
10835 + break;
10836 + }
10837 + }
10838 +
10839 + /* Search for the closest MIPS clock greater or equal to a preferred value */
10840 + for (i = 0; i < tabsz; i++) {
10841 + ASSERT(table[i].mipsclock ==
10842 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
10843 + if ((mipsclock <= table[i].mipsclock) &&
10844 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
10845 + break;
10846 + }
10847 + if (i == tabsz) {
10848 + ret = FALSE;
10849 + goto done;
10850 + } else {
10851 + te = &table[i];
10852 + ret = TRUE;
10853 + }
10854 +
10855 + /* No PLL change */
10856 + if ((orig_n == te->n) &&
10857 + (orig_sb == te->sb) &&
10858 + (orig_pci == te->pci33) &&
10859 + (orig_m2 == te->m2) &&
10860 + (orig_mips == te->m3))
10861 + goto done;
10862 +
10863 + /* Set the PLL controls */
10864 + W_REG(osh, clockcontrol_n, te->n);
10865 + W_REG(osh, clockcontrol_sb, te->sb);
10866 + W_REG(osh, clockcontrol_pci, te->pci33);
10867 + W_REG(osh, &cc->clockcontrol_m2, te->m2);
10868 + W_REG(osh, &cc->clockcontrol_m3, te->m3);
10869 +
10870 + /* Set the chipcontrol bit to change mipsref to the backplane divider if needed */
10871 + if ((pll_type == PLL_TYPE7) && (te->sb != te->m2) &&
10872 + (sb_clock_rate(pll_type, te->n, te->m2) == 120000000))
10873 + W_REG(osh, &cc->chipcontrol,
10874 + R_REG(osh, &cc->chipcontrol) | 0x100);
10875 +
10876 + /* No ratio change */
10877 + if (sb_chip(sbh) != BCM4785_CHIP_ID) {
10878 + if (orig_ratio_parm == te->ratio_parm)
10879 + goto end_fill;
10880 + }
10881 +
10882 + /* Preload the code into the cache */
10883 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
10884 + if (sb_chip(sbh) == BCM4785_CHIP_ID) {
10885 + start = ((ulong) &&start_fill_4785) & ~(ic_lsize - 1);
10886 + end = ((ulong) &&end_fill_4785 + (ic_lsize - 1)) & ~(ic_lsize - 1);
10887 + }
10888 + else {
10889 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
10890 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
10891 + }
10892 + while (start < end) {
10893 + cache_op(start, Fill_I);
10894 + start += ic_lsize;
10895 + }
10896 +
10897 + /* Copy the handler */
10898 + start = (ulong) &handler;
10899 + end = (ulong) &afterhandler;
10900 + dst = KSEG1ADDR(0x180);
10901 + for (i = 0; i < (end - start); i += 4)
10902 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
10903 +
10904 + /* Preload the handler into the cache one line at a time */
10905 + for (i = 0; i < (end - start); i += ic_lsize)
10906 + cache_op(dst + i, Fill_I);
10907 +
10908 + /* Clear BEV bit */
10909 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
10910 +
10911 + /* Enable interrupts */
10912 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
10913 +
10914 + /* 4785 clock freq change procedures */
10915 + if (sb_chip(sbh) == BCM4785_CHIP_ID) {
10916 + start_fill_4785:
10917 + /* Switch to async */
10918 + MTC0(C0_BROADCOM, 4, (1 << 22));
10919 +
10920 + /* Set clock ratio in MIPS */
10921 + *dll_r1 = (*dll_r1 & 0xfffffff0) | (te->d11_r1 - 1);
10922 + *dll_r2 = te->d11_r2;
10923 +
10924 + /* Enable new settings in MIPS */
10925 + *dll_r1 = *dll_r1 | 0xc0000000;
10926 +
10927 + /* Set active cfg */
10928 + MTC0(C0_BROADCOM, 2, MFC0(C0_BROADCOM, 2) | (1 << 3) | 1);
10929 +
10930 + /* Fake soft reset (clock cfg registers not reset) */
10931 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | (1 << 2));
10932 +
10933 + /* Clear active cfg */
10934 + MTC0(C0_BROADCOM, 2, MFC0(C0_BROADCOM, 2) & ~(1 << 3));
10935 +
10936 + /* set watchdog timer */
10937 + W_REG(osh, &cc->watchdog, 20);
10938 + (void) R_REG(osh, &cc->chipid);
10939 +
10940 + /* wait for timer interrupt */
10941 + __asm__ __volatile__(
10942 + ".set\tmips3\n\t"
10943 + "sync\n\t"
10944 + "wait\n\t"
10945 + ".set\tmips0");
10946 + end_fill_4785:
10947 + while (1);
10948 + }
10949 + /* Generic clock freq change procedures */
10950 + else {
10951 + /* Enable MIPS timer interrupt */
10952 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
10953 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
10954 + ASSERT(mipsr);
10955 + W_REG(osh, &mipsr->intmask, 1);
10956 +
10957 + start_fill:
10958 + /* step 1, set clock ratios */
10959 + MTC0(C0_BROADCOM, 3, te->ratio_parm);
10960 + MTC0(C0_BROADCOM, 1, te->ratio_cfg);
10961 +
10962 + /* step 2: program timer intr */
10963 + W_REG(osh, &mipsr->timer, 100);
10964 + (void) R_REG(osh, &mipsr->timer);
10965 +
10966 + /* step 3, switch to async */
10967 + sync_mode = MFC0(C0_BROADCOM, 4);
10968 + MTC0(C0_BROADCOM, 4, 1 << 22);
10969 +
10970 + /* step 4, set cfg active */
10971 + MTC0(C0_BROADCOM, 2, (1 << 3) | 1);
10972 +
10973 + /* steps 5 & 6 */
10974 + __asm__ __volatile__(
10975 + ".set\tmips3\n\t"
10976 + "wait\n\t"
10977 + ".set\tmips0");
10978 +
10979 + /* step 7, clear cfg active */
10980 + MTC0(C0_BROADCOM, 2, 0);
10981 +
10982 + /* Additional Step: set back to orig sync mode */
10983 + MTC0(C0_BROADCOM, 4, sync_mode);
10984 +
10985 + /* step 8, fake soft reset */
10986 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | (1 << 2));
10987 +
10988 + end_fill:
10989 + /* set watchdog timer */
10990 + W_REG(osh, &cc->watchdog, 20);
10991 + (void) R_REG(osh, &cc->chipid);
10992 +
10993 + /* wait for timer interrupt */
10994 + __asm__ __volatile__(
10995 + ".set\tmips3\n\t"
10996 + "sync\n\t"
10997 + "wait\n\t"
10998 + ".set\tmips0");
10999 + while (1);
11000 + }
11001 + }
11002 +
11003 +done:
11004 + /* Enable 4785 DLL */
11005 + if (sb_chip(sbh) == BCM4785_CHIP_ID) {
11006 + uint32 tmp;
11007 +
11008 + /* set mask to 1e, enable DLL (bit 0) */
11009 + *dll_ctrl |= 0x0041e021;
11010 +
11011 + /* enable aggressive hardware mode */
11012 + *dll_ctrl |= 0x00000080;
11013 +
11014 + /* wait for lock flag to clear */
11015 + while ((*dll_ctrl & 0x2) == 0);
11016 +
11017 + /* clear sticky flags (clear on write 1) */
11018 + tmp = *dll_ctrl;
11019 + *dll_ctrl = tmp;
11020 +
11021 + /* set mask to 5b'10001 */
11022 + *dll_ctrl = (*dll_ctrl & 0xfffc1fff) | 0x00022000;
11023 +
11024 + /* enable sync mode */
11025 + MTC0(C0_BROADCOM, 4, MFC0(C0_BROADCOM, 4) & 0xfe3fffff);
11026 + (void)MFC0(C0_BROADCOM, 4);
11027 + }
11028 +
11029 + /* switch back to previous core */
11030 + sb_setcoreidx(sbh, idx);
11031 +
11032 + return ret;
11033 +}
11034 +
11035 +void
11036 +BCMINITFN(enable_pfc)(uint32 mode)
11037 +{
11038 + ulong start, end;
11039 + uint ic_size, ic_lsize;
11040 +
11041 + /* If auto then choose the correct mode for this
11042 + * platform, currently we only ever select one mode
11043 + */
11044 + if (mode == PFC_AUTO)
11045 + mode = PFC_INST;
11046 +
11047 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
11048 +
11049 + /* enable prefetch cache if available */
11050 + if (MFC0(C0_BROADCOM, 0) & BRCM_PFC_AVAIL) {
11051 + start = ((ulong) &&setpfc_start) & ~(ic_lsize - 1);
11052 + end = ((ulong) &&setpfc_end + (ic_lsize - 1)) & ~(ic_lsize - 1);
11053 +
11054 + /* Preload setpfc code into the cache one line at a time */
11055 + while (start < end) {
11056 + cache_op(start, Fill_I);
11057 + start += ic_lsize;
11058 + }
11059 +
11060 + /* Now set the pfc */
11061 + setpfc_start:
11062 + /* write range */
11063 + *(volatile uint32 *)PFC_CR1 = 0xffff0000;
11064 +
11065 + /* enable */
11066 + *(volatile uint32 *)PFC_CR0 = mode;
11067 + setpfc_end:
11068 + /* Compiler foder */
11069 + ic_size = 0;
11070 + }
11071 +}
11072 +
11073 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
11074 +uint32
11075 +BCMINITFN(sb_memc_get_ncdl)(sb_t *sbh)
11076 +{
11077 + osl_t *osh;
11078 + sbmemcregs_t *memc;
11079 + uint32 ret = 0;
11080 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
11081 + uint idx, rev;
11082 +
11083 + osh = sb_osh(sbh);
11084 +
11085 + idx = sb_coreidx(sbh);
11086 +
11087 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
11088 + if (memc == 0)
11089 + goto out;
11090 +
11091 + rev = sb_corerev(sbh);
11092 +
11093 + config = R_REG(osh, &memc->config);
11094 + wr = R_REG(osh, &memc->wrncdlcor);
11095 + rd = R_REG(osh, &memc->rdncdlcor);
11096 + misc = R_REG(osh, &memc->miscdlyctl);
11097 + dqsg = R_REG(osh, &memc->dqsgatencdl);
11098 +
11099 + rd &= MEMC_RDNCDLCOR_RD_MASK;
11100 + wr &= MEMC_WRNCDLCOR_WR_MASK;
11101 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
11102 +
11103 + if (config & MEMC_CONFIG_DDR) {
11104 + ret = (wr << 16) | (rd << 8) | dqsg;
11105 + } else {
11106 + if (rev > 0)
11107 + cd = rd;
11108 + else
11109 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
11110 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
11111 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
11112 + ret = (sm << 16) | (sd << 8) | cd;
11113 + }
11114 +
11115 +out:
11116 + /* switch back to previous core */
11117 + sb_setcoreidx(sbh, idx);
11118 +
11119 + return ret;
11120 +}
11121 +
11122 +#if defined(BCMPERFSTATS)
11123 +/*
11124 + * CP0 Register 25 supports 4 semi-independent 32bit performance counters.
11125 + * $25 select 0, 1, 2, and 3 are the counters. The counters *decrement* (who thought this one up?)
11126 + * $25 select 4 and 5 each contain 2-16bit control fields, one for each of the 4 counters
11127 + * $25 select 6 is the global perf control register.
11128 + */
11129 +/* enable and start instruction counting */
11130 +
11131 +void
11132 +hndmips_perf_instrcount_enable()
11133 +{
11134 + MTC0(C0_PERFORMANCE, 6, 0x80000200); /* global enable perf counters */
11135 + MTC0(C0_PERFORMANCE, 4,
11136 + 0x8044 | MFC0(C0_PERFORMANCE, 4)); /* enable instruction counting for counter 0 */
11137 + MTC0(C0_PERFORMANCE, 0, 0); /* zero counter zero */
11138 +}
11139 +
11140 +/* enable and start I$ hit and I$ miss counting */
11141 +void
11142 +hndmips_perf_icachecount_enable(void)
11143 +{
11144 + MTC0(C0_PERFORMANCE, 6, 0x80000218); /* enable I$ counting */
11145 + MTC0(C0_PERFORMANCE, 4, 0x80148018); /* count I$ hits in cntr 0 and misses in cntr 1 */
11146 + MTC0(C0_PERFORMANCE, 0, 0); /* zero counter 0 - # I$ hits */
11147 + MTC0(C0_PERFORMANCE, 1, 0); /* zero counter 1 - # I$ misses */
11148 +}
11149 +
11150 +/* enable and start D$ hit and I$ miss counting */
11151 +void
11152 +hndmips_perf_dcachecount_enable(void)
11153 +{
11154 + MTC0(C0_PERFORMANCE, 6, 0x80000211); /* enable D$ counting */
11155 + MTC0(C0_PERFORMANCE, 4, 0x80248028); /* count D$ hits in cntr 0 and misses in cntr 1 */
11156 + MTC0(C0_PERFORMANCE, 0, 0); /* zero counter 0 - # D$ hits */
11157 + MTC0(C0_PERFORMANCE, 1, 0); /* zero counter 1 - # D$ misses */
11158 +}
11159 +
11160 +void
11161 +hndmips_perf_icache_miss_enable()
11162 +{
11163 + MTC0(C0_PERFORMANCE, 4,
11164 + 0x80140000 | MFC0(C0_PERFORMANCE, 4)); /* enable cache misses counting for counter 1 */
11165 + MTC0(C0_PERFORMANCE, 1, 0); /* zero counter one */
11166 +}
11167 +
11168 +
11169 +void
11170 +hndmips_perf_icache_hit_enable()
11171 +{
11172 + MTC0(C0_PERFORMANCE, 5, 0x8018 | MFC0(C0_PERFORMANCE, 5));
11173 + /* enable cache hits counting for counter 2 */
11174 + MTC0(C0_PERFORMANCE, 2, 0); /* zero counter 2 */
11175 +}
11176 +
11177 +uint32
11178 +hndmips_perf_read_instrcount()
11179 +{
11180 + return -(long)(MFC0(C0_PERFORMANCE, 0));
11181 +}
11182 +
11183 +uint32
11184 +hndmips_perf_read_cache_miss()
11185 +{
11186 + return -(long)(MFC0(C0_PERFORMANCE, 1));
11187 +}
11188 +
11189 +uint32
11190 +hndmips_perf_read_cache_hit()
11191 +{
11192 + return -(long)(MFC0(C0_PERFORMANCE, 2));
11193 +}
11194 +
11195 +#endif /* BCMINTERNAL | BCMPERFSTATS */
11196 diff -urN linux.old/arch/mips/bcm947xx/sbpci.c linux.dev/arch/mips/bcm947xx/sbpci.c
11197 --- linux.old/arch/mips/bcm947xx/sbpci.c 1970-01-01 01:00:00.000000000 +0100
11198 +++ linux.dev/arch/mips/bcm947xx/sbpci.c 2006-10-02 21:19:59.000000000 +0200
11199 @@ -0,0 +1,768 @@
11200 +/*
11201 + * Low-Level PCI and SB support for BCM47xx
11202 + *
11203 + * Copyright 2006, Broadcom Corporation
11204 + * All Rights Reserved.
11205 + *
11206 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11207 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11208 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11209 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11210 + *
11211 + * $Id: hndpci.c,v 1.1.1.3 2006/04/08 06:13:39 honor Exp $
11212 + */
11213 +
11214 +#include <typedefs.h>
11215 +#include <osl.h>
11216 +#include <pcicfg.h>
11217 +#include <bcmdevs.h>
11218 +#include <sbconfig.h>
11219 +#include <bcmutils.h>
11220 +#include <sbutils.h>
11221 +#include <sbpci.h>
11222 +#include <bcmendian.h>
11223 +#include <bcmnvram.h>
11224 +#include <hndcpu.h>
11225 +#include <hndmips.h>
11226 +#include <hndpci.h>
11227 +
11228 +/* debug/trace */
11229 +#ifdef BCMDBG_PCI
11230 +#define PCI_MSG(args) printf args
11231 +#else
11232 +#define PCI_MSG(args)
11233 +#endif /* BCMDBG_PCI */
11234 +
11235 +/* Can free sbpci_init() memory after boot */
11236 +#ifndef linux
11237 +#define __init
11238 +#endif /* linux */
11239 +
11240 +/* Emulated configuration space */
11241 +typedef struct {
11242 + int n;
11243 + uint size0;
11244 + uint size1;
11245 + uint size2;
11246 + uint size3;
11247 +} sb_bar_cfg_t;
11248 +static pci_config_regs sb_config_regs[SB_MAXCORES];
11249 +static sb_bar_cfg_t sb_bar_cfg[SB_MAXCORES];
11250 +
11251 +/* Links to emulated and real PCI configuration spaces */
11252 +#define MAXFUNCS 2
11253 +typedef struct {
11254 + pci_config_regs *emu; /* emulated PCI config */
11255 + pci_config_regs *pci; /* real PCI config */
11256 + sb_bar_cfg_t *bar; /* region sizes */
11257 +} sb_pci_cfg_t;
11258 +static sb_pci_cfg_t sb_pci_cfg[SB_MAXCORES][MAXFUNCS];
11259 +
11260 +/* Special emulated config space for non-existing device */
11261 +static pci_config_regs sb_pci_null = { 0xffff, 0xffff };
11262 +
11263 +/* Banned cores */
11264 +static uint16 pci_ban[SB_MAXCORES] = { 0 };
11265 +static uint pci_banned = 0;
11266 +
11267 +/* CardBus mode */
11268 +static bool cardbus = FALSE;
11269 +
11270 +/* Disable PCI host core */
11271 +static bool pci_disabled = FALSE;
11272 +
11273 +/* Host bridge slot #, default to 0 */
11274 +static uint8 pci_hbslot = 0;
11275 +
11276 +/* Internal macros */
11277 +#define PCI_SLOTAD_MAP 16 /* SLOT<n> mapps to AD<n+16> */
11278 +#define PCI_HBSBCFG_REV 8 /* MIN. core rev. required to
11279 + * access host bridge PCI cfg space
11280 + * from SB
11281 + */
11282 +
11283 +/*
11284 + * Functions for accessing external PCI configuration space
11285 + */
11286 +
11287 +/* Assume one-hot slot wiring */
11288 +#define PCI_SLOT_MAX 16 /* Max. PCI Slots */
11289 +
11290 +static uint32
11291 +config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
11292 +{
11293 + uint coreidx;
11294 + sbpciregs_t *regs;
11295 + uint32 addr = 0;
11296 + osl_t *osh;
11297 +
11298 + /* CardBusMode supports only one device */
11299 + if (cardbus && dev > 1)
11300 + return 0;
11301 +
11302 + osh = sb_osh(sbh);
11303 +
11304 + coreidx = sb_coreidx(sbh);
11305 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
11306 +
11307 + /* Type 0 transaction */
11308 + if (bus == 1) {
11309 + /* Skip unwired slots */
11310 + if (dev < PCI_SLOT_MAX) {
11311 + uint32 win;
11312 +
11313 + /* Slide the PCI window to the appropriate slot */
11314 + win = (SBTOPCI_CFG0 | ((1 << (dev + PCI_SLOTAD_MAP)) & SBTOPCI1_MASK));
11315 + W_REG(osh, &regs->sbtopci1, win);
11316 + addr = SB_PCI_CFG |
11317 + ((1 << (dev + PCI_SLOTAD_MAP)) & ~SBTOPCI1_MASK) |
11318 + (func << PCICFG_FUN_SHIFT) |
11319 + (off & ~3);
11320 + }
11321 + } else {
11322 + /* Type 1 transaction */
11323 + W_REG(osh, &regs->sbtopci1, SBTOPCI_CFG1);
11324 + addr = SB_PCI_CFG |
11325 + (bus << PCICFG_BUS_SHIFT) |
11326 + (dev << PCICFG_SLOT_SHIFT) |
11327 + (func << PCICFG_FUN_SHIFT) |
11328 + (off & ~3);
11329 + }
11330 +
11331 + sb_setcoreidx(sbh, coreidx);
11332 +
11333 + return addr;
11334 +}
11335 +
11336 +/*
11337 + * Read host bridge PCI config registers from Silicon Backplane (>=rev8).
11338 + *
11339 + * It returns TRUE to indicate that access to the host bridge's pci config
11340 + * from SB is ok, and values in 'addr' and 'val' are valid.
11341 + *
11342 + * It can only read registers at multiple of 4-bytes. Callers must pick up
11343 + * needed bytes from 'val' based on 'off' value. Value in 'addr' reflects
11344 + * the register address where value in 'val' is read.
11345 + */
11346 +static bool
11347 +sb_pcihb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off,
11348 + uint32 **addr, uint32 *val)
11349 +{
11350 + sbpciregs_t *regs;
11351 + osl_t *osh;
11352 + uint coreidx;
11353 + bool ret = FALSE;
11354 +
11355 + /* sanity check */
11356 + ASSERT(bus == 1);
11357 + ASSERT(dev == pci_hbslot);
11358 + ASSERT(func == 0);
11359 +
11360 + osh = sb_osh(sbh);
11361 +
11362 + /* read pci config when core rev >= 8 */
11363 + coreidx = sb_coreidx(sbh);
11364 + regs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
11365 + if (regs && sb_corerev(sbh) >= PCI_HBSBCFG_REV) {
11366 + *addr = (uint32 *)&regs->pcicfg[func][off >> 2];
11367 + *val = R_REG(osh, *addr);
11368 + ret = TRUE;
11369 + }
11370 + sb_setcoreidx(sbh, coreidx);
11371 +
11372 + return ret;
11373 +}
11374 +
11375 +int
11376 +extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11377 +{
11378 + uint32 addr = 0, *reg = NULL, val;
11379 + int ret = 0;
11380 +
11381 + /*
11382 + * Set value to -1 when:
11383 + * flag 'pci_disabled' is true;
11384 + * value of 'addr' is zero;
11385 + * REG_MAP() fails;
11386 + * BUSPROBE() fails;
11387 + */
11388 + if (pci_disabled)
11389 + val = 0xffffffff;
11390 + else if (bus == 1 && dev == pci_hbslot && func == 0 &&
11391 + sb_pcihb_read_config(sbh, bus, dev, func, off, &reg, &val))
11392 + ;
11393 + else if (((addr = config_cmd(sbh, bus, dev, func, off)) == 0) ||
11394 + ((reg = (uint32 *)REG_MAP(addr, len)) == 0) ||
11395 + (BUSPROBE(val, reg) != 0))
11396 + val = 0xffffffff;
11397 +
11398 + PCI_MSG(("%s: 0x%x <= 0x%p(0x%x), len %d, off 0x%x, buf 0x%p\n",
11399 + __FUNCTION__, val, reg, addr, len, off, buf));
11400 +
11401 + val >>= 8 * (off & 3);
11402 + if (len == 4)
11403 + *((uint32 *) buf) = val;
11404 + else if (len == 2)
11405 + *((uint16 *) buf) = (uint16) val;
11406 + else if (len == 1)
11407 + *((uint8 *) buf) = (uint8) val;
11408 + else
11409 + ret = -1;
11410 +
11411 + if (reg && addr)
11412 + REG_UNMAP(reg);
11413 +
11414 + return ret;
11415 +}
11416 +
11417 +int
11418 +extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11419 +{
11420 + osl_t *osh;
11421 + uint32 addr = 0, *reg = NULL, val;
11422 + int ret = 0;
11423 +
11424 + osh = sb_osh(sbh);
11425 +
11426 + /*
11427 + * Ignore write attempt when:
11428 + * flag 'pci_disabled' is true;
11429 + * value of 'addr' is zero;
11430 + * REG_MAP() fails;
11431 + * BUSPROBE() fails;
11432 + */
11433 + if (pci_disabled)
11434 + return 0;
11435 + else if (bus == 1 && dev == pci_hbslot && func == 0 &&
11436 + sb_pcihb_read_config(sbh, bus, dev, func, off, &reg, &val))
11437 + ;
11438 + else if (((addr = config_cmd(sbh, bus, dev, func, off)) == 0) ||
11439 + ((reg = (uint32 *) REG_MAP(addr, len)) == 0) ||
11440 + (BUSPROBE(val, reg) != 0))
11441 + goto done;
11442 +
11443 + if (len == 4)
11444 + val = *((uint32 *) buf);
11445 + else if (len == 2) {
11446 + val &= ~(0xffff << (8 * (off & 3)));
11447 + val |= *((uint16 *) buf) << (8 * (off & 3));
11448 + } else if (len == 1) {
11449 + val &= ~(0xff << (8 * (off & 3)));
11450 + val |= *((uint8 *) buf) << (8 * (off & 3));
11451 + } else {
11452 + ret = -1;
11453 + goto done;
11454 + }
11455 +
11456 + PCI_MSG(("%s: 0x%x => 0x%p\n", __FUNCTION__, val, reg));
11457 +
11458 + W_REG(osh, reg, val);
11459 +
11460 +done:
11461 + if (reg && addr)
11462 + REG_UNMAP(reg);
11463 +
11464 + return ret;
11465 +}
11466 +
11467 +/*
11468 + * Must access emulated PCI configuration at these locations even when
11469 + * the real PCI config space exists and is accessible.
11470 + *
11471 + * PCI_CFG_VID (0x00)
11472 + * PCI_CFG_DID (0x02)
11473 + * PCI_CFG_PROGIF (0x09)
11474 + * PCI_CFG_SUBCL (0x0a)
11475 + * PCI_CFG_BASECL (0x0b)
11476 + * PCI_CFG_HDR (0x0e)
11477 + * PCI_CFG_INT (0x3c)
11478 + * PCI_CFG_PIN (0x3d)
11479 + */
11480 +#define FORCE_EMUCFG(off, len) \
11481 + ((off == PCI_CFG_VID) || (off == PCI_CFG_DID) || \
11482 + (off == PCI_CFG_PROGIF) || \
11483 + (off == PCI_CFG_SUBCL) || (off == PCI_CFG_BASECL) || \
11484 + (off == PCI_CFG_HDR) || \
11485 + (off == PCI_CFG_INT) || (off == PCI_CFG_PIN))
11486 +
11487 +/* Sync the emulation registers and the real PCI config registers. */
11488 +static void
11489 +sb_pcid_read_config(sb_t *sbh, uint coreidx, sb_pci_cfg_t *cfg,
11490 + uint off, uint len)
11491 +{
11492 + osl_t *osh;
11493 + uint oldidx;
11494 +
11495 + ASSERT(cfg);
11496 + ASSERT(cfg->emu);
11497 + ASSERT(cfg->pci);
11498 +
11499 + /* decide if real PCI config register access is necessary */
11500 + if (FORCE_EMUCFG(off, len))
11501 + return;
11502 +
11503 + osh = sb_osh(sbh);
11504 +
11505 + /* access to the real pci config space only when the core is up */
11506 + oldidx = sb_coreidx(sbh);
11507 + sb_setcoreidx(sbh, coreidx);
11508 + if (sb_iscoreup(sbh)) {
11509 + if (len == 4)
11510 + *(uint32 *)((ulong)cfg->emu + off) =
11511 + htol32(R_REG(osh, (uint32 *)((ulong)cfg->pci + off)));
11512 + else if (len == 2)
11513 + *(uint16 *)((ulong)cfg->emu + off) =
11514 + htol16(R_REG(osh, (uint16 *)((ulong)cfg->pci + off)));
11515 + else if (len == 1)
11516 + *(uint8 *)((ulong)cfg->emu + off) =
11517 + R_REG(osh, (uint8 *)((ulong)cfg->pci + off));
11518 + }
11519 + sb_setcoreidx(sbh, oldidx);
11520 +}
11521 +
11522 +static void
11523 +sb_pcid_write_config(sb_t *sbh, uint coreidx, sb_pci_cfg_t *cfg,
11524 + uint off, uint len)
11525 +{
11526 + osl_t *osh;
11527 + uint oldidx;
11528 +
11529 + ASSERT(cfg);
11530 + ASSERT(cfg->emu);
11531 + ASSERT(cfg->pci);
11532 +
11533 + osh = sb_osh(sbh);
11534 +
11535 + /* decide if real PCI config register access is necessary */
11536 + if (FORCE_EMUCFG(off, len))
11537 + return;
11538 +
11539 + /* access to the real pci config space only when the core is up */
11540 + oldidx = sb_coreidx(sbh);
11541 + sb_setcoreidx(sbh, coreidx);
11542 + if (sb_iscoreup(sbh)) {
11543 + if (len == 4)
11544 + W_REG(osh, (uint32 *)((ulong)cfg->pci + off),
11545 + ltoh32(*(uint32 *)((ulong)cfg->emu + off)));
11546 + else if (len == 2)
11547 + W_REG(osh, (uint16 *)((ulong)cfg->pci + off),
11548 + ltoh16(*(uint16 *)((ulong)cfg->emu + off)));
11549 + else if (len == 1)
11550 + W_REG(osh, (uint8 *)((ulong)cfg->pci + off),
11551 + *(uint8 *)((ulong)cfg->emu + off));
11552 + }
11553 + sb_setcoreidx(sbh, oldidx);
11554 +}
11555 +
11556 +/*
11557 + * Functions for accessing translated SB configuration space
11558 + */
11559 +static int
11560 +sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11561 +{
11562 + pci_config_regs *cfg;
11563 +
11564 + if (dev >= SB_MAXCORES || func >= MAXFUNCS || (off + len) > sizeof(pci_config_regs))
11565 + return -1;
11566 + cfg = sb_pci_cfg[dev][func].emu;
11567 +
11568 + ASSERT(ISALIGNED(off, len));
11569 + ASSERT(ISALIGNED((uintptr)buf, len));
11570 +
11571 + /* use special config space if the device does not exist */
11572 + if (!cfg)
11573 + cfg = &sb_pci_null;
11574 + /* sync emulation with real PCI config if necessary */
11575 + else if (sb_pci_cfg[dev][func].pci)
11576 + sb_pcid_read_config(sbh, dev, &sb_pci_cfg[dev][func], off, len);
11577 +
11578 + if (len == 4)
11579 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
11580 + else if (len == 2)
11581 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
11582 + else if (len == 1)
11583 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
11584 + else
11585 + return -1;
11586 +
11587 + return 0;
11588 +}
11589 +
11590 +static int
11591 +sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11592 +{
11593 + uint coreidx;
11594 + void *regs;
11595 + pci_config_regs *cfg;
11596 + osl_t *osh;
11597 + sb_bar_cfg_t *bar;
11598 +
11599 + if (dev >= SB_MAXCORES || func >= MAXFUNCS || (off + len) > sizeof(pci_config_regs))
11600 + return -1;
11601 + cfg = sb_pci_cfg[dev][func].emu;
11602 + if (!cfg)
11603 + return -1;
11604 +
11605 + ASSERT(ISALIGNED(off, len));
11606 + ASSERT(ISALIGNED((uintptr)buf, len));
11607 +
11608 + osh = sb_osh(sbh);
11609 +
11610 + /* Emulate BAR sizing */
11611 + if (off >= OFFSETOF(pci_config_regs, base[0]) &&
11612 + off <= OFFSETOF(pci_config_regs, base[3]) &&
11613 + len == 4 && *((uint32 *) buf) == ~0) {
11614 + coreidx = sb_coreidx(sbh);
11615 + if ((regs = sb_setcoreidx(sbh, dev))) {
11616 + bar = sb_pci_cfg[dev][func].bar;
11617 + /* Highest numbered address match register */
11618 + if (off == OFFSETOF(pci_config_regs, base[0]))
11619 + cfg->base[0] = ~(bar->size0 - 1);
11620 + else if (off == OFFSETOF(pci_config_regs, base[1]) && bar->n >= 1)
11621 + cfg->base[1] = ~(bar->size1 - 1);
11622 + else if (off == OFFSETOF(pci_config_regs, base[2]) && bar->n >= 2)
11623 + cfg->base[2] = ~(bar->size2 - 1);
11624 + else if (off == OFFSETOF(pci_config_regs, base[3]) && bar->n >= 3)
11625 + cfg->base[3] = ~(bar->size3 - 1);
11626 + }
11627 + sb_setcoreidx(sbh, coreidx);
11628 + }
11629 + else if (len == 4)
11630 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
11631 + else if (len == 2)
11632 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
11633 + else if (len == 1)
11634 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
11635 + else
11636 + return -1;
11637 +
11638 + /* sync emulation with real PCI config if necessary */
11639 + if (sb_pci_cfg[dev][func].pci)
11640 + sb_pcid_write_config(sbh, dev, &sb_pci_cfg[dev][func], off, len);
11641 +
11642 + return 0;
11643 +}
11644 +
11645 +int
11646 +sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11647 +{
11648 + if (bus == 0)
11649 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
11650 + else
11651 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
11652 +}
11653 +
11654 +int
11655 +sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11656 +{
11657 + if (bus == 0)
11658 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
11659 + else
11660 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
11661 +}
11662 +
11663 +void
11664 +sbpci_ban(uint16 core)
11665 +{
11666 + if (pci_banned < ARRAYSIZE(pci_ban))
11667 + pci_ban[pci_banned++] = core;
11668 +}
11669 +
11670 +/*
11671 + * Initiliaze PCI core. Return 0 after a successful initialization.
11672 + * Otherwise return -1 to indicate there is no PCI core and return 1
11673 + * to indicate PCI core is disabled.
11674 + */
11675 +int __init
11676 +sbpci_init_pci(sb_t *sbh)
11677 +{
11678 + uint chip, chiprev, chippkg, host;
11679 + uint32 boardflags;
11680 + sbpciregs_t *pci;
11681 + sbconfig_t *sb;
11682 + uint32 val;
11683 + int ret = 0;
11684 + char *hbslot;
11685 + osl_t *osh;
11686 +
11687 + chip = sb_chip(sbh);
11688 + chiprev = sb_chiprev(sbh);
11689 + chippkg = sb_chippkg(sbh);
11690 +
11691 + osh = sb_osh(sbh);
11692 +
11693 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) {
11694 + printk("PCI: no core\n");
11695 + pci_disabled = TRUE;
11696 + return -1;
11697 + }
11698 +
11699 + if ((chip == 0x4310) && (chiprev == 0))
11700 + pci_disabled = TRUE;
11701 +
11702 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
11703 +
11704 + boardflags = (uint32) getintvar(NULL, "boardflags");
11705 +
11706 + /*
11707 + * The 200-pin BCM4712 package does not bond out PCI. Even when
11708 + * PCI is bonded out, some boards may leave the pins
11709 + * floating.
11710 + */
11711 + if (((chip == BCM4712_CHIP_ID) &&
11712 + ((chippkg == BCM4712SMALL_PKG_ID) ||
11713 + (chippkg == BCM4712MID_PKG_ID))) ||
11714 + (boardflags & BFL_NOPCI))
11715 + pci_disabled = TRUE;
11716 +
11717 + /* Enable the core */
11718 + sb_core_reset(sbh, 0, 0);
11719 +
11720 + /*
11721 + * If the PCI core should not be touched (disabled, not bonded
11722 + * out, or pins floating), do not even attempt to access core
11723 + * registers. Otherwise, try to determine if it is in host
11724 + * mode.
11725 + */
11726 + if (pci_disabled)
11727 + host = 0;
11728 + else
11729 + host = !BUSPROBE(val, &pci->control);
11730 +
11731 + if (!host) {
11732 + ret = 1;
11733 +
11734 + /* Disable PCI interrupts in client mode */
11735 + W_REG(osh, &sb->sbintvec, 0);
11736 +
11737 + /* Disable the PCI bridge in client mode */
11738 + sbpci_ban(SB_PCI);
11739 + sb_core_disable(sbh, 0);
11740 +
11741 + printk("PCI: Disabled\n");
11742 + } else {
11743 + printk("PCI: Initializing host\n");
11744 +
11745 + /* Disable PCI SBReqeustTimeout for BCM4785 */
11746 + if (chip == BCM4785_CHIP_ID) {
11747 + AND_REG(osh, &sb->sbimconfiglow, ~0x00000070);
11748 + sb_commit(sbh);
11749 + }
11750 +
11751 + /* Reset the external PCI bus and enable the clock */
11752 + W_REG(osh, &pci->control, 0x5); /* enable the tristate drivers */
11753 + W_REG(osh, &pci->control, 0xd); /* enable the PCI clock */
11754 + OSL_DELAY(150); /* delay > 100 us */
11755 + W_REG(osh, &pci->control, 0xf); /* deassert PCI reset */
11756 + /* Use internal arbiter and park REQ/GRNT at external master 0 */
11757 + W_REG(osh, &pci->arbcontrol, PCI_INT_ARB);
11758 + OSL_DELAY(1); /* delay 1 us */
11759 + if (sb_corerev(sbh) >= 8) {
11760 + val = getintvar(NULL, "parkid");
11761 + ASSERT(val <= PCI_PARKID_LAST);
11762 + OR_REG(osh, &pci->arbcontrol, val << PCI_PARKID_SHIFT);
11763 + OSL_DELAY(1);
11764 + }
11765 +
11766 + /* Enable CardBusMode */
11767 + cardbus = getintvar(NULL, "cardbus") == 1;
11768 + if (cardbus) {
11769 + printk("PCI: Enabling CardBus\n");
11770 + /* GPIO 1 resets the CardBus device on bcm94710ap */
11771 + sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
11772 + sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
11773 + W_REG(osh, &pci->sprom[0], R_REG(osh, &pci->sprom[0]) | 0x400);
11774 + }
11775 +
11776 + /* 64 MB I/O access window */
11777 + W_REG(osh, &pci->sbtopci0, SBTOPCI_IO);
11778 + /* 64 MB configuration access window */
11779 + W_REG(osh, &pci->sbtopci1, SBTOPCI_CFG0);
11780 + /* 1 GB memory access window */
11781 + W_REG(osh, &pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
11782 +
11783 + /* Host bridge slot # nvram overwrite */
11784 + if ((hbslot = nvram_get("pcihbslot"))) {
11785 + pci_hbslot = bcm_strtoul(hbslot, NULL, 0);
11786 + ASSERT(pci_hbslot < PCI_MAX_DEVICES);
11787 + }
11788 +
11789 + /* Enable PCI bridge BAR0 prefetch and burst */
11790 + val = 6;
11791 + sbpci_write_config(sbh, 1, pci_hbslot, 0, PCI_CFG_CMD, &val, sizeof(val));
11792 +
11793 + /* Enable PCI interrupts */
11794 + W_REG(osh, &pci->intmask, PCI_INTA);
11795 + }
11796 +
11797 + return ret;
11798 +}
11799 +
11800 +/*
11801 + * Get the PCI region address and size information.
11802 + */
11803 +static void __init
11804 +sbpci_init_regions(sb_t *sbh, uint func, pci_config_regs *cfg, sb_bar_cfg_t *bar)
11805 +{
11806 + osl_t *osh;
11807 + uint16 coreid;
11808 + void *regs;
11809 + sbconfig_t *sb;
11810 + uint32 base;
11811 +
11812 + osh = sb_osh(sbh);
11813 + coreid = sb_coreid(sbh);
11814 + regs = sb_coreregs(sbh);
11815 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11816 +
11817 + switch (coreid) {
11818 + case SB_USB20H:
11819 + base = htol32(sb_base(R_REG(osh, &sb->sbadmatch0)));
11820 +
11821 + cfg->base[0] = func == 0 ? base : base + 0x800; /* OHCI/EHCI */
11822 + cfg->base[1] = 0;
11823 + cfg->base[2] = 0;
11824 + cfg->base[3] = 0;
11825 + cfg->base[4] = 0;
11826 + cfg->base[5] = 0;
11827 + bar->n = 1;
11828 + bar->size0 = func == 0 ? 0x200 : 0x100; /* OHCI/EHCI */
11829 + bar->size1 = 0;
11830 + bar->size2 = 0;
11831 + bar->size3 = 0;
11832 + break;
11833 + default:
11834 + cfg->base[0] = htol32(sb_base(R_REG(osh, &sb->sbadmatch0)));
11835 + cfg->base[1] = htol32(sb_base(R_REG(osh, &sb->sbadmatch1)));
11836 + cfg->base[2] = htol32(sb_base(R_REG(osh, &sb->sbadmatch2)));
11837 + cfg->base[3] = htol32(sb_base(R_REG(osh, &sb->sbadmatch3)));
11838 + cfg->base[4] = 0;
11839 + cfg->base[5] = 0;
11840 + bar->n = (R_REG(osh, &sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
11841 + bar->size0 = sb_size(R_REG(osh, &sb->sbadmatch0));
11842 + bar->size1 = sb_size(R_REG(osh, &sb->sbadmatch1));
11843 + bar->size2 = sb_size(R_REG(osh, &sb->sbadmatch2));
11844 + bar->size3 = sb_size(R_REG(osh, &sb->sbadmatch3));
11845 + break;
11846 + }
11847 +}
11848 +
11849 +/*
11850 + * Construct PCI config spaces for SB cores so that they
11851 + * can be accessed as if they were PCI devices.
11852 + */
11853 +static void __init
11854 +sbpci_init_cores(sb_t *sbh)
11855 +{
11856 + uint chiprev, coreidx, i;
11857 + sbconfig_t *sb;
11858 + pci_config_regs *cfg, *pci;
11859 + sb_bar_cfg_t *bar;
11860 + void *regs;
11861 + osl_t *osh;
11862 + uint16 vendor, device;
11863 + uint16 coreid;
11864 + uint8 class, subclass, progif;
11865 + uint dev;
11866 + uint8 header;
11867 + uint func;
11868 +
11869 + chiprev = sb_chiprev(sbh);
11870 + coreidx = sb_coreidx(sbh);
11871 +
11872 + osh = sb_osh(sbh);
11873 +
11874 + /* Scan the SB bus */
11875 + bzero(sb_config_regs, sizeof(sb_config_regs));
11876 + bzero(sb_bar_cfg, sizeof(sb_bar_cfg));
11877 + bzero(sb_pci_cfg, sizeof(sb_pci_cfg));
11878 + memset(&sb_pci_null, -1, sizeof(sb_pci_null));
11879 + cfg = sb_config_regs;
11880 + bar = sb_bar_cfg;
11881 + for (dev = 0; dev < SB_MAXCORES; dev ++) {
11882 + /* Check if the core exists */
11883 + if (!(regs = sb_setcoreidx(sbh, dev)))
11884 + continue;
11885 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11886 +
11887 + /* Check if this core is banned */
11888 + coreid = sb_coreid(sbh);
11889 + for (i = 0; i < pci_banned; i++)
11890 + if (coreid == pci_ban[i])
11891 + break;
11892 + if (i < pci_banned)
11893 + continue;
11894 +
11895 + for (func = 0; func < MAXFUNCS; ++func) {
11896 + /* Make sure we won't go beyond the limit */
11897 + if (cfg >= &sb_config_regs[SB_MAXCORES]) {
11898 + printk("PCI: too many emulated devices\n");
11899 + goto done;
11900 + }
11901 +
11902 + /* Convert core id to pci id */
11903 + if (sb_corepciid(sbh, func, &vendor, &device, &class, &subclass,
11904 + &progif, &header))
11905 + continue;
11906 +
11907 + /*
11908 + * Differentiate real PCI config from emulated.
11909 + * non zero 'pci' indicate there is a real PCI config space
11910 + * for this device.
11911 + */
11912 + switch (device) {
11913 + case BCM47XX_GIGETH_ID:
11914 + pci = (pci_config_regs *)((uint32)regs + 0x800);
11915 + break;
11916 + case BCM47XX_SATAXOR_ID:
11917 + pci = (pci_config_regs *)((uint32)regs + 0x400);
11918 + break;
11919 + case BCM47XX_ATA100_ID:
11920 + pci = (pci_config_regs *)((uint32)regs + 0x800);
11921 + break;
11922 + default:
11923 + pci = NULL;
11924 + break;
11925 + }
11926 + /* Supported translations */
11927 + cfg->vendor = htol16(vendor);
11928 + cfg->device = htol16(device);
11929 + cfg->rev_id = chiprev;
11930 + cfg->prog_if = progif;
11931 + cfg->sub_class = subclass;
11932 + cfg->base_class = class;
11933 + cfg->header_type = header;
11934 + sbpci_init_regions(sbh, func, cfg, bar);
11935 + /* Save core interrupt flag */
11936 + cfg->int_pin = R_REG(osh, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
11937 + /* Save core interrupt assignment */
11938 + cfg->int_line = sb_irq(sbh);
11939 + /* Indicate there is no SROM */
11940 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
11941 +
11942 + /* Point to the PCI config spaces */
11943 + sb_pci_cfg[dev][func].emu = cfg;
11944 + sb_pci_cfg[dev][func].pci = pci;
11945 + sb_pci_cfg[dev][func].bar = bar;
11946 + cfg ++;
11947 + bar ++;
11948 + }
11949 + }
11950 +
11951 +done:
11952 + sb_setcoreidx(sbh, coreidx);
11953 +}
11954 +
11955 +/*
11956 + * Initialize PCI core and construct PCI config spaces for SB cores.
11957 + * Must propagate sbpci_init_pci() return value to the caller to let
11958 + * them know the PCI core initialization status.
11959 + */
11960 +int __init
11961 +sbpci_init(sb_t *sbh)
11962 +{
11963 + int status = sbpci_init_pci(sbh);
11964 + sbpci_init_cores(sbh);
11965 + return status;
11966 +}
11967 +
11968 diff -urN linux.old/arch/mips/bcm947xx/sbutils.c linux.dev/arch/mips/bcm947xx/sbutils.c
11969 --- linux.old/arch/mips/bcm947xx/sbutils.c 1970-01-01 01:00:00.000000000 +0100
11970 +++ linux.dev/arch/mips/bcm947xx/sbutils.c 2006-10-02 21:19:59.000000000 +0200
11971 @@ -0,0 +1,3081 @@
11972 +/*
11973 + * Misc utility routines for accessing chip-specific features
11974 + * of the SiliconBackplane-based Broadcom chips.
11975 + *
11976 + * Copyright 2006, Broadcom Corporation
11977 + * All Rights Reserved.
11978 + *
11979 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11980 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11981 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11982 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11983 + * $Id: sbutils.c,v 1.10 2006/04/08 07:12:42 honor Exp $
11984 + */
11985 +
11986 +#include <typedefs.h>
11987 +#include <bcmdefs.h>
11988 +#include <osl.h>
11989 +#include <bcmutils.h>
11990 +#include <sbutils.h>
11991 +#include <bcmdevs.h>
11992 +#include <sbconfig.h>
11993 +#include <sbchipc.h>
11994 +#include <sbpci.h>
11995 +#include <sbpcie.h>
11996 +#include <pcicfg.h>
11997 +#include <sbpcmcia.h>
11998 +#include <sbextif.h>
11999 +#include <sbsocram.h>
12000 +#include <bcmsrom.h>
12001 +#ifdef __mips__
12002 +#include <mipsinc.h>
12003 +#endif /* __mips__ */
12004 +
12005 +/* debug/trace */
12006 +#define SB_ERROR(args)
12007 +
12008 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
12009 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
12010 +typedef bool (*sb_intrsenabled_t)(void *intr_arg);
12011 +
12012 +/* misc sb info needed by some of the routines */
12013 +typedef struct sb_info {
12014 +
12015 + struct sb_pub sb; /* back plane public state (must be first field) */
12016 +
12017 + void *osh; /* osl os handle */
12018 + void *sdh; /* bcmsdh handle */
12019 +
12020 + void *curmap; /* current regs va */
12021 + void *regs[SB_MAXCORES]; /* other regs va */
12022 +
12023 + uint curidx; /* current core index */
12024 + uint dev_coreid; /* the core provides driver functions */
12025 +
12026 + bool memseg; /* flag to toggle MEM_SEG register */
12027 +
12028 + uint gpioidx; /* gpio control core index */
12029 + uint gpioid; /* gpio control coretype */
12030 +
12031 + uint numcores; /* # discovered cores */
12032 + uint coreid[SB_MAXCORES]; /* id of each core */
12033 +
12034 + void *intr_arg; /* interrupt callback function arg */
12035 + sb_intrsoff_t intrsoff_fn; /* turns chip interrupts off */
12036 + sb_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
12037 + sb_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
12038 +
12039 +} sb_info_t;
12040 +
12041 +/* local prototypes */
12042 +static sb_info_t * sb_doattach(sb_info_t *si, uint devid, osl_t *osh, void *regs,
12043 + uint bustype, void *sdh, char **vars, uint *varsz);
12044 +static void sb_scan(sb_info_t *si);
12045 +static uint sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val);
12046 +static uint _sb_coreidx(sb_info_t *si);
12047 +static uint sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit);
12048 +static uint sb_pcidev2chip(uint pcidev);
12049 +static uint sb_chip2numcores(uint chip);
12050 +static bool sb_ispcie(sb_info_t *si);
12051 +static bool sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen);
12052 +static int sb_pci_fixcfg(sb_info_t *si);
12053 +
12054 +/* routines to access mdio slave device registers */
12055 +static int sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint readdr, uint val);
12056 +static void sb_war30841(sb_info_t *si);
12057 +
12058 +/* delay needed between the mdio control/ mdiodata register data access */
12059 +#define PR28829_DELAY() OSL_DELAY(10)
12060 +
12061 +/* size that can take bitfielddump */
12062 +#define BITFIELD_DUMP_SIZE 32
12063 +
12064 +/* global variable to indicate reservation/release of gpio's */
12065 +static uint32 sb_gpioreservation = 0;
12066 +
12067 +#define SB_INFO(sbh) (sb_info_t*)sbh
12068 +#define SET_SBREG(si, r, mask, val) \
12069 + W_SBREG((si), (r), ((R_SBREG((si), (r)) & ~(mask)) | (val)))
12070 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && \
12071 + ISALIGNED((x), SB_CORE_SIZE))
12072 +#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE))
12073 +#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
12074 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
12075 +#define BADIDX (SB_MAXCORES+1)
12076 +#define NOREV -1 /* Invalid rev */
12077 +
12078 +#define PCI(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCI))
12079 +#define PCIE(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCIE))
12080 +
12081 +/* sonicsrev */
12082 +#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
12083 +#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
12084 +
12085 +#define R_SBREG(si, sbr) sb_read_sbreg((si), (sbr))
12086 +#define W_SBREG(si, sbr, v) sb_write_sbreg((si), (sbr), (v))
12087 +#define AND_SBREG(si, sbr, v) W_SBREG((si), (sbr), (R_SBREG((si), (sbr)) & (v)))
12088 +#define OR_SBREG(si, sbr, v) W_SBREG((si), (sbr), (R_SBREG((si), (sbr)) | (v)))
12089 +
12090 +/*
12091 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
12092 + * after core switching to avoid invalid register accesss inside ISR.
12093 + */
12094 +#define INTR_OFF(si, intr_val) \
12095 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
12096 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
12097 +#define INTR_RESTORE(si, intr_val) \
12098 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
12099 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
12100 +
12101 +/* dynamic clock control defines */
12102 +#define LPOMINFREQ 25000 /* low power oscillator min */
12103 +#define LPOMAXFREQ 43000 /* low power oscillator max */
12104 +#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
12105 +#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
12106 +#define PCIMINFREQ 25000000 /* 25 MHz */
12107 +#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
12108 +
12109 +#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
12110 +#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
12111 +
12112 +/* different register spaces to access thr'u pcie indirect access */
12113 +#define PCIE_CONFIGREGS 1 /* Access to config space */
12114 +#define PCIE_PCIEREGS 2 /* Access to pcie registers */
12115 +
12116 +/* GPIO Based LED powersave defines */
12117 +#define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
12118 +#define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
12119 +
12120 +#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
12121 +
12122 +static uint32
12123 +sb_read_sbreg(sb_info_t *si, volatile uint32 *sbr)
12124 +{
12125 + uint8 tmp;
12126 + uint32 val, intr_val = 0;
12127 +
12128 +
12129 + /*
12130 + * compact flash only has 11 bits address, while we needs 12 bits address.
12131 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
12132 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
12133 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
12134 + */
12135 + if (si->memseg) {
12136 + INTR_OFF(si, intr_val);
12137 + tmp = 1;
12138 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12139 + sbr = (volatile uint32 *)((uintptr)sbr & ~(1 << 11)); /* mask out bit 11 */
12140 + }
12141 +
12142 + val = R_REG(si->osh, sbr);
12143 +
12144 + if (si->memseg) {
12145 + tmp = 0;
12146 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12147 + INTR_RESTORE(si, intr_val);
12148 + }
12149 +
12150 + return (val);
12151 +}
12152 +
12153 +static void
12154 +sb_write_sbreg(sb_info_t *si, volatile uint32 *sbr, uint32 v)
12155 +{
12156 + uint8 tmp;
12157 + volatile uint32 dummy;
12158 + uint32 intr_val = 0;
12159 +
12160 +
12161 + /*
12162 + * compact flash only has 11 bits address, while we needs 12 bits address.
12163 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
12164 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
12165 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
12166 + */
12167 + if (si->memseg) {
12168 + INTR_OFF(si, intr_val);
12169 + tmp = 1;
12170 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12171 + sbr = (volatile uint32 *)((uintptr)sbr & ~(1 << 11)); /* mask out bit 11 */
12172 + }
12173 +
12174 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
12175 +#ifdef IL_BIGENDIAN
12176 + dummy = R_REG(si->osh, sbr);
12177 + W_REG(si->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
12178 + dummy = R_REG(si->osh, sbr);
12179 + W_REG(si->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff));
12180 +#else
12181 + dummy = R_REG(si->osh, sbr);
12182 + W_REG(si->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff));
12183 + dummy = R_REG(si->osh, sbr);
12184 + W_REG(si->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
12185 +#endif /* IL_BIGENDIAN */
12186 + } else
12187 + W_REG(si->osh, sbr, v);
12188 +
12189 + if (si->memseg) {
12190 + tmp = 0;
12191 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12192 + INTR_RESTORE(si, intr_val);
12193 + }
12194 +}
12195 +
12196 +/*
12197 + * Allocate a sb handle.
12198 + * devid - pci device id (used to determine chip#)
12199 + * osh - opaque OS handle
12200 + * regs - virtual address of initial core registers
12201 + * bustype - pci/pcmcia/sb/sdio/etc
12202 + * vars - pointer to a pointer area for "environment" variables
12203 + * varsz - pointer to int to return the size of the vars
12204 + */
12205 +sb_t *
12206 +BCMINITFN(sb_attach)(uint devid, osl_t *osh, void *regs,
12207 + uint bustype, void *sdh, char **vars, uint *varsz)
12208 +{
12209 + sb_info_t *si;
12210 +
12211 + /* alloc sb_info_t */
12212 + if ((si = MALLOC(osh, sizeof (sb_info_t))) == NULL) {
12213 + SB_ERROR(("sb_attach: malloc failed! malloced %d bytes\n", MALLOCED(osh)));
12214 + return (NULL);
12215 + }
12216 +
12217 + if (sb_doattach(si, devid, osh, regs, bustype, sdh, vars, (uint*)varsz) == NULL) {
12218 + MFREE(osh, si, sizeof(sb_info_t));
12219 + return (NULL);
12220 + }
12221 +
12222 + return (sb_t *)si;
12223 +}
12224 +
12225 +/* Using sb_kattach depends on SB_BUS support, either implicit */
12226 +/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */
12227 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
12228 +
12229 +/* global kernel resource */
12230 +static sb_info_t ksi;
12231 +static bool ksi_attached = FALSE;
12232 +
12233 +/* generic kernel variant of sb_attach() */
12234 +sb_t *
12235 +BCMINITFN(sb_kattach)(void)
12236 +{
12237 + osl_t *osh = NULL;
12238 + uint32 *regs;
12239 +
12240 + if (!ksi_attached) {
12241 + uint32 cid;
12242 +
12243 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
12244 + cid = R_REG(osh, (uint32 *)regs);
12245 + if (((cid & CID_ID_MASK) == BCM4712_CHIP_ID) &&
12246 + ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) &&
12247 + ((cid & CID_REV_MASK) <= (3 << CID_REV_SHIFT))) {
12248 + uint32 *scc, val;
12249 +
12250 + scc = (uint32 *)((uchar*)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
12251 + val = R_REG(osh, scc);
12252 + SB_ERROR((" initial scc = 0x%x\n", val));
12253 + val |= SCC_SS_XTAL;
12254 + W_REG(osh, scc, val);
12255 + }
12256 +
12257 + if (sb_doattach(&ksi, BCM4710_DEVICE_ID, osh, (void*)regs,
12258 + SB_BUS, NULL, NULL, NULL) == NULL) {
12259 + return NULL;
12260 + }
12261 + else
12262 + ksi_attached = TRUE;
12263 + }
12264 +
12265 + return (sb_t *)&ksi;
12266 +}
12267 +#endif /* !BCMBUSTYPE || (BCMBUSTYPE == SB_BUS) */
12268 +
12269 +static sb_info_t *
12270 +BCMINITFN(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
12271 + uint bustype, void *sdh, char **vars, uint *varsz)
12272 +{
12273 + uint origidx;
12274 + chipcregs_t *cc;
12275 + sbconfig_t *sb;
12276 + uint32 w;
12277 +
12278 + ASSERT(GOODREGS(regs));
12279 +
12280 + bzero((uchar*)si, sizeof(sb_info_t));
12281 +
12282 + si->sb.buscoreidx = si->gpioidx = BADIDX;
12283 +
12284 + si->curmap = regs;
12285 + si->sdh = sdh;
12286 + si->osh = osh;
12287 +
12288 + /* check to see if we are a sb core mimic'ing a pci core */
12289 + if (bustype == PCI_BUS) {
12290 + if (OSL_PCI_READ_CONFIG(si->osh, PCI_SPROM_CONTROL, sizeof(uint32)) == 0xffffffff) {
12291 + SB_ERROR(("%s: incoming bus is PCI but it's a lie, switching to SB "
12292 + "devid:0x%x\n", __FUNCTION__, devid));
12293 + bustype = SB_BUS;
12294 + }
12295 + }
12296 +
12297 + si->sb.bustype = bustype;
12298 + if (si->sb.bustype != BUSTYPE(si->sb.bustype)) {
12299 + SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n",
12300 + si->sb.bustype, BUSTYPE(si->sb.bustype)));
12301 + return NULL;
12302 + }
12303 +
12304 + /* need to set memseg flag for CF card first before any sb registers access */
12305 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS)
12306 + si->memseg = TRUE;
12307 +
12308 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
12309 + if (BUSTYPE(si->sb.bustype) == PCI_BUS)
12310 + sb_clkctl_xtal(&si->sb, XTAL|PLL, ON);
12311 +
12312 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
12313 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32));
12314 + if (!GOODCOREADDR(w))
12315 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32), SB_ENUM_BASE);
12316 + }
12317 +
12318 + /* initialize current core index value */
12319 + si->curidx = _sb_coreidx(si);
12320 +
12321 + if (si->curidx == BADIDX) {
12322 + SB_ERROR(("sb_doattach: bad core index\n"));
12323 + return NULL;
12324 + }
12325 +
12326 + /* get sonics backplane revision */
12327 + sb = REGS2SB(si->curmap);
12328 + si->sb.sonicsrev = (R_SBREG(si, &sb->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
12329 +
12330 + /* keep and reuse the initial register mapping */
12331 + origidx = si->curidx;
12332 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
12333 + si->regs[origidx] = regs;
12334 +
12335 + /* is core-0 a chipcommon core? */
12336 + si->numcores = 1;
12337 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, 0);
12338 + if (sb_coreid(&si->sb) != SB_CC)
12339 + cc = NULL;
12340 +
12341 + /* determine chip id and rev */
12342 + if (cc) {
12343 + /* chip common core found! */
12344 + si->sb.chip = R_REG(si->osh, &cc->chipid) & CID_ID_MASK;
12345 + si->sb.chiprev = (R_REG(si->osh, &cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
12346 + si->sb.chippkg = (R_REG(si->osh, &cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
12347 + } else {
12348 + /* no chip common core -- must convert device id to chip id */
12349 + if ((si->sb.chip = sb_pcidev2chip(devid)) == 0) {
12350 + SB_ERROR(("sb_doattach: unrecognized device id 0x%04x\n", devid));
12351 + sb_setcoreidx(&si->sb, origidx);
12352 + return NULL;
12353 + }
12354 + }
12355 +
12356 + /* get chipcommon rev */
12357 + si->sb.ccrev = cc ? (int)sb_corerev(&si->sb) : NOREV;
12358 +
12359 + /* determine numcores */
12360 + if (cc && ((si->sb.ccrev == 4) || (si->sb.ccrev >= 6)))
12361 + si->numcores = (R_REG(si->osh, &cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
12362 + else
12363 + si->numcores = sb_chip2numcores(si->sb.chip);
12364 +
12365 + /* return to original core */
12366 + sb_setcoreidx(&si->sb, origidx);
12367 +
12368 + /* sanity checks */
12369 + ASSERT(si->sb.chip);
12370 +
12371 + /* scan for cores */
12372 + sb_scan(si);
12373 +
12374 + /* fixup necessary chip/core configurations */
12375 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
12376 + if (sb_pci_fixcfg(si)) {
12377 + SB_ERROR(("sb_doattach: sb_pci_fixcfg failed\n"));
12378 + return NULL;
12379 + }
12380 + }
12381 +
12382 + /* srom_var_init() depends on sb_scan() info */
12383 + if (srom_var_init(si, si->sb.bustype, si->curmap, si->osh, vars, varsz)) {
12384 + SB_ERROR(("sb_doattach: srom_var_init failed: bad srom\n"));
12385 + return (NULL);
12386 + }
12387 +
12388 + if (cc == NULL) {
12389 + /*
12390 + * The chip revision number is hardwired into all
12391 + * of the pci function config rev fields and is
12392 + * independent from the individual core revision numbers.
12393 + * For example, the "A0" silicon of each chip is chip rev 0.
12394 + * For PCMCIA we get it from the CIS instead.
12395 + */
12396 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
12397 + ASSERT(vars);
12398 + si->sb.chiprev = getintvar(*vars, "chiprev");
12399 + } else if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
12400 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_REV, sizeof(uint32));
12401 + si->sb.chiprev = w & 0xff;
12402 + } else
12403 + si->sb.chiprev = 0;
12404 + }
12405 +
12406 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
12407 + w = getintvar(*vars, "regwindowsz");
12408 + si->memseg = (w <= CFTABLE_REGWIN_2K) ? TRUE : FALSE;
12409 + }
12410 +
12411 + /* gpio control core is required */
12412 + if (!GOODIDX(si->gpioidx)) {
12413 + SB_ERROR(("sb_doattach: gpio control core not found\n"));
12414 + return NULL;
12415 + }
12416 +
12417 + /* get boardtype and boardrev */
12418 + switch (BUSTYPE(si->sb.bustype)) {
12419 + case PCI_BUS:
12420 + /* do a pci config read to get subsystem id and subvendor id */
12421 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_SVID, sizeof(uint32));
12422 + si->sb.boardvendor = w & 0xffff;
12423 + si->sb.boardtype = (w >> 16) & 0xffff;
12424 + break;
12425 +
12426 + case PCMCIA_BUS:
12427 + case SDIO_BUS:
12428 + si->sb.boardvendor = getintvar(*vars, "manfid");
12429 + si->sb.boardtype = getintvar(*vars, "prodid");
12430 + break;
12431 +
12432 + case SB_BUS:
12433 + case JTAG_BUS:
12434 + si->sb.boardvendor = VENDOR_BROADCOM;
12435 + if ((si->sb.boardtype = getintvar(NULL, "boardtype")) == 0)
12436 + si->sb.boardtype = 0xffff;
12437 + break;
12438 + }
12439 +
12440 + if (si->sb.boardtype == 0) {
12441 + SB_ERROR(("sb_doattach: unknown board type\n"));
12442 + ASSERT(si->sb.boardtype);
12443 + }
12444 +
12445 + /* setup the GPIO based LED powersave register */
12446 + if (si->sb.ccrev >= 16) {
12447 + if ((vars == NULL) || ((w = getintvar(*vars, "leddc")) == 0))
12448 + w = DEFAULT_GPIOTIMERVAL;
12449 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
12450 + }
12451 + if ((si->sb.chip == BCM4311_CHIP_ID) && (si->sb.chiprev <= 1)) {
12452 + /* set proper clk setup delays before forcing HT */
12453 + sb_clkctl_init((void *)si);
12454 + sb_corereg((void*)si, SB_CC_IDX, OFFSETOF(chipcregs_t, system_clk_ctl),
12455 + SYCC_HR, SYCC_HR);
12456 + }
12457 +
12458 +
12459 + return (si);
12460 +}
12461 +
12462 +uint
12463 +sb_coreid(sb_t *sbh)
12464 +{
12465 + sb_info_t *si;
12466 + sbconfig_t *sb;
12467 +
12468 + si = SB_INFO(sbh);
12469 + sb = REGS2SB(si->curmap);
12470 +
12471 + return ((R_SBREG(si, &sb->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
12472 +}
12473 +
12474 +uint
12475 +sb_coreidx(sb_t *sbh)
12476 +{
12477 + sb_info_t *si;
12478 +
12479 + si = SB_INFO(sbh);
12480 + return (si->curidx);
12481 +}
12482 +
12483 +/* return current index of core */
12484 +static uint
12485 +_sb_coreidx(sb_info_t *si)
12486 +{
12487 + sbconfig_t *sb;
12488 + uint32 sbaddr = 0;
12489 +
12490 + ASSERT(si);
12491 +
12492 + switch (BUSTYPE(si->sb.bustype)) {
12493 + case SB_BUS:
12494 + sb = REGS2SB(si->curmap);
12495 + sbaddr = sb_base(R_SBREG(si, &sb->sbadmatch0));
12496 + break;
12497 +
12498 + case PCI_BUS:
12499 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32));
12500 + break;
12501 +
12502 + case PCMCIA_BUS: {
12503 + uint8 tmp = 0;
12504 +
12505 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
12506 + sbaddr = (uint)tmp << 12;
12507 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
12508 + sbaddr |= (uint)tmp << 16;
12509 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
12510 + sbaddr |= (uint)tmp << 24;
12511 + break;
12512 + }
12513 +
12514 +#ifdef BCMJTAG
12515 + case JTAG_BUS:
12516 + sbaddr = (uint32)si->curmap;
12517 + break;
12518 +#endif /* BCMJTAG */
12519 +
12520 + default:
12521 + ASSERT(0);
12522 + }
12523 +
12524 + if (!GOODCOREADDR(sbaddr))
12525 + return BADIDX;
12526 +
12527 + return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE);
12528 +}
12529 +
12530 +uint
12531 +sb_corevendor(sb_t *sbh)
12532 +{
12533 + sb_info_t *si;
12534 + sbconfig_t *sb;
12535 +
12536 + si = SB_INFO(sbh);
12537 + sb = REGS2SB(si->curmap);
12538 +
12539 + return ((R_SBREG(si, &sb->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
12540 +}
12541 +
12542 +uint
12543 +sb_corerev(sb_t *sbh)
12544 +{
12545 + sb_info_t *si;
12546 + sbconfig_t *sb;
12547 + uint sbidh;
12548 +
12549 + si = SB_INFO(sbh);
12550 + sb = REGS2SB(si->curmap);
12551 + sbidh = R_SBREG(si, &sb->sbidhigh);
12552 +
12553 + return (SBCOREREV(sbidh));
12554 +}
12555 +
12556 +void *
12557 +sb_osh(sb_t *sbh)
12558 +{
12559 + sb_info_t *si;
12560 +
12561 + si = SB_INFO(sbh);
12562 + return si->osh;
12563 +}
12564 +
12565 +void
12566 +sb_setosh(sb_t *sbh, osl_t *osh)
12567 +{
12568 + sb_info_t *si;
12569 +
12570 + si = SB_INFO(sbh);
12571 + if (si->osh != NULL) {
12572 + SB_ERROR(("osh is already set....\n"));
12573 + ASSERT(!si->osh);
12574 + }
12575 + si->osh = osh;
12576 +}
12577 +
12578 +/* set/clear sbtmstatelow core-specific flags */
12579 +uint32
12580 +sb_coreflags(sb_t *sbh, uint32 mask, uint32 val)
12581 +{
12582 + sb_info_t *si;
12583 + sbconfig_t *sb;
12584 + uint32 w;
12585 +
12586 + si = SB_INFO(sbh);
12587 + sb = REGS2SB(si->curmap);
12588 +
12589 + ASSERT((val & ~mask) == 0);
12590 +
12591 + /* mask and set */
12592 + if (mask || val) {
12593 + w = (R_SBREG(si, &sb->sbtmstatelow) & ~mask) | val;
12594 + W_SBREG(si, &sb->sbtmstatelow, w);
12595 + }
12596 +
12597 + /* return the new value */
12598 + return (R_SBREG(si, &sb->sbtmstatelow));
12599 +}
12600 +
12601 +/* set/clear sbtmstatehigh core-specific flags */
12602 +uint32
12603 +sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val)
12604 +{
12605 + sb_info_t *si;
12606 + sbconfig_t *sb;
12607 + uint32 w;
12608 +
12609 + si = SB_INFO(sbh);
12610 + sb = REGS2SB(si->curmap);
12611 +
12612 + ASSERT((val & ~mask) == 0);
12613 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
12614 +
12615 + /* mask and set */
12616 + if (mask || val) {
12617 + w = (R_SBREG(si, &sb->sbtmstatehigh) & ~mask) | val;
12618 + W_SBREG(si, &sb->sbtmstatehigh, w);
12619 + }
12620 +
12621 + /* return the new value */
12622 + return (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
12623 +}
12624 +
12625 +/* Run bist on current core. Caller needs to take care of core-specific bist hazards */
12626 +int
12627 +sb_corebist(sb_t *sbh)
12628 +{
12629 + uint32 sblo;
12630 + sb_info_t *si;
12631 + sbconfig_t *sb;
12632 + int result = 0;
12633 +
12634 + si = SB_INFO(sbh);
12635 + sb = REGS2SB(si->curmap);
12636 +
12637 + sblo = R_SBREG(si, &sb->sbtmstatelow);
12638 + W_SBREG(si, &sb->sbtmstatelow, (sblo | SBTML_FGC | SBTML_BE));
12639 +
12640 + SPINWAIT(((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BISTD) == 0), 100000);
12641 +
12642 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BISTF)
12643 + result = BCME_ERROR;
12644 +
12645 + W_SBREG(si, &sb->sbtmstatelow, sblo);
12646 +
12647 + return result;
12648 +}
12649 +
12650 +bool
12651 +sb_iscoreup(sb_t *sbh)
12652 +{
12653 + sb_info_t *si;
12654 + sbconfig_t *sb;
12655 +
12656 + si = SB_INFO(sbh);
12657 + sb = REGS2SB(si->curmap);
12658 +
12659 + return ((R_SBREG(si, &sb->sbtmstatelow) &
12660 + (SBTML_RESET | SBTML_REJ_MASK | SBTML_CLK)) == SBTML_CLK);
12661 +}
12662 +
12663 +/*
12664 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
12665 + * switch back to the original core, and return the new value.
12666 + *
12667 + * When using the silicon backplane, no fidleing with interrupts or core switches are needed.
12668 + *
12669 + * Also, when using pci/pcie, we can optimize away the core switching for pci registers
12670 + * and (on newer pci cores) chipcommon registers.
12671 + */
12672 +static uint
12673 +sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val)
12674 +{
12675 + uint origidx = 0;
12676 + uint32 *r = NULL;
12677 + uint w;
12678 + uint intr_val = 0;
12679 + bool fast = FALSE;
12680 +
12681 + ASSERT(GOODIDX(coreidx));
12682 + ASSERT(regoff < SB_CORE_SIZE);
12683 + ASSERT((val & ~mask) == 0);
12684 +
12685 +#ifdef notyet
12686 + if (si->sb.bustype == SB_BUS) {
12687 + /* If internal bus, we can always get at everything */
12688 + fast = TRUE;
12689 + r = (uint32 *)((uchar *)si->regs[coreidx] + regoff);
12690 + } else if (si->sb.bustype == PCI_BUS) {
12691 + /* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
12692 +
12693 + if ((si->coreid[coreidx] == SB_CC) &&
12694 + ((si->sb.buscoretype == SB_PCIE) ||
12695 + (si->sb.buscorerev >= 13))) {
12696 + /* Chipc registers are mapped at 12KB */
12697 +
12698 + fast = TRUE;
12699 + r = (uint32 *)((char *)si->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
12700 + } else if (si->sb.buscoreidx == coreidx) {
12701 + /* pci registers are at either in the last 2KB of an 8KB window
12702 + * or, in pcie and pci rev 13 at 8KB
12703 + */
12704 + fast = TRUE;
12705 + if ((si->sb.buscoretype == SB_PCIE) ||
12706 + (si->sb.buscorerev >= 13))
12707 + r = (uint32 *)((char *)si->curmap +
12708 + PCI_16KB0_PCIREGS_OFFSET + regoff);
12709 + else
12710 + r = (uint32 *)((char *)si->curmap +
12711 + ((regoff >= SBCONFIGOFF) ?
12712 + PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
12713 + regoff);
12714 + }
12715 + }
12716 +#endif /* notyet */
12717 +
12718 + if (!fast) {
12719 + INTR_OFF(si, intr_val);
12720 +
12721 + /* save current core index */
12722 + origidx = sb_coreidx(&si->sb);
12723 +
12724 + /* switch core */
12725 + r = (uint32*) ((uchar*) sb_setcoreidx(&si->sb, coreidx) + regoff);
12726 + }
12727 + ASSERT(r);
12728 +
12729 + /* mask and set */
12730 + if (mask || val) {
12731 + if (regoff >= SBCONFIGOFF) {
12732 + w = (R_SBREG(si, r) & ~mask) | val;
12733 + W_SBREG(si, r, w);
12734 + } else {
12735 + w = (R_REG(si->osh, r) & ~mask) | val;
12736 + W_REG(si->osh, r, w);
12737 + }
12738 + }
12739 +
12740 + /* readback */
12741 + if (regoff >= SBCONFIGOFF)
12742 + w = R_SBREG(si, r);
12743 + else
12744 + w = R_REG(si->osh, r);
12745 +
12746 + if (!fast) {
12747 + /* restore core index */
12748 + if (origidx != coreidx)
12749 + sb_setcoreidx(&si->sb, origidx);
12750 +
12751 + INTR_RESTORE(si, intr_val);
12752 + }
12753 +
12754 + return (w);
12755 +}
12756 +
12757 +#define DWORD_ALIGN(x) (x & ~(0x03))
12758 +#define BYTE_POS(x) (x & 0x3)
12759 +#define WORD_POS(x) (x & 0x1)
12760 +
12761 +#define BYTE_SHIFT(x) (8 * BYTE_POS(x))
12762 +#define WORD_SHIFT(x) (16 * WORD_POS(x))
12763 +
12764 +#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
12765 +#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
12766 +
12767 +#define read_pci_cfg_byte(a) \
12768 + (BYTE_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xff)
12769 +
12770 +#define read_pci_cfg_write(a) \
12771 + (WORD_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xffff)
12772 +
12773 +
12774 +/* return TRUE if requested capability exists in the PCI config space */
12775 +static bool
12776 +sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen)
12777 +{
12778 + uint8 cap_id;
12779 + uint8 cap_ptr;
12780 + uint32 bufsize;
12781 + uint8 byte_val;
12782 +
12783 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
12784 + return FALSE;
12785 +
12786 + /* check for Header type 0 */
12787 + byte_val = read_pci_cfg_byte(PCI_CFG_HDR);
12788 + if ((byte_val & 0x7f) != PCI_HEADER_NORMAL)
12789 + return FALSE;
12790 +
12791 + /* check if the capability pointer field exists */
12792 + byte_val = read_pci_cfg_byte(PCI_CFG_STAT);
12793 + if (!(byte_val & PCI_CAPPTR_PRESENT))
12794 + return FALSE;
12795 +
12796 + cap_ptr = read_pci_cfg_byte(PCI_CFG_CAPPTR);
12797 + /* check if the capability pointer is 0x00 */
12798 + if (cap_ptr == 0x00)
12799 + return FALSE;
12800 +
12801 +
12802 + /* loop thr'u the capability list and see if the pcie capabilty exists */
12803 +
12804 + cap_id = read_pci_cfg_byte(cap_ptr);
12805 +
12806 + while (cap_id != req_cap_id) {
12807 + cap_ptr = read_pci_cfg_byte((cap_ptr+1));
12808 + if (cap_ptr == 0x00) break;
12809 + cap_id = read_pci_cfg_byte(cap_ptr);
12810 + }
12811 + if (cap_id != req_cap_id) {
12812 + return FALSE;
12813 + }
12814 + /* found the caller requested capability */
12815 + if ((buf != NULL) && (buflen != NULL)) {
12816 + bufsize = *buflen;
12817 + if (!bufsize) goto end;
12818 + *buflen = 0;
12819 + /* copy the cpability data excluding cap ID and next ptr */
12820 + cap_ptr += 2;
12821 + if ((bufsize + cap_ptr) > SZPCR)
12822 + bufsize = SZPCR - cap_ptr;
12823 + *buflen = bufsize;
12824 + while (bufsize--) {
12825 + *buf = read_pci_cfg_byte(cap_ptr);
12826 + cap_ptr++;
12827 + buf++;
12828 + }
12829 + }
12830 +end:
12831 + return TRUE;
12832 +}
12833 +
12834 +/* return TRUE if PCIE capability exists the pci config space */
12835 +static inline bool
12836 +sb_ispcie(sb_info_t *si)
12837 +{
12838 + return (sb_find_pci_capability(si, PCI_CAP_PCIECAP_ID, NULL, NULL));
12839 +}
12840 +
12841 +/* scan the sb enumerated space to identify all cores */
12842 +static void
12843 +BCMINITFN(sb_scan)(sb_info_t *si)
12844 +{
12845 + uint origidx;
12846 + uint i;
12847 + bool pci;
12848 + bool pcie;
12849 + uint pciidx;
12850 + uint pcieidx;
12851 + uint pcirev;
12852 + uint pcierev;
12853 +
12854 +
12855 + /* numcores should already be set */
12856 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
12857 +
12858 + /* save current core index */
12859 + origidx = sb_coreidx(&si->sb);
12860 +
12861 + si->sb.buscorerev = NOREV;
12862 + si->sb.buscoreidx = BADIDX;
12863 +
12864 + si->gpioidx = BADIDX;
12865 +
12866 + pci = pcie = FALSE;
12867 + pcirev = pcierev = NOREV;
12868 + pciidx = pcieidx = BADIDX;
12869 +
12870 + for (i = 0; i < si->numcores; i++) {
12871 + sb_setcoreidx(&si->sb, i);
12872 + si->coreid[i] = sb_coreid(&si->sb);
12873 +
12874 + if (si->coreid[i] == SB_PCI) {
12875 + pciidx = i;
12876 + pcirev = sb_corerev(&si->sb);
12877 + pci = TRUE;
12878 + } else if (si->coreid[i] == SB_PCIE) {
12879 + pcieidx = i;
12880 + pcierev = sb_corerev(&si->sb);
12881 + pcie = TRUE;
12882 + } else if (si->coreid[i] == SB_PCMCIA) {
12883 + si->sb.buscorerev = sb_corerev(&si->sb);
12884 + si->sb.buscoretype = si->coreid[i];
12885 + si->sb.buscoreidx = i;
12886 + }
12887 + }
12888 + if (pci && pcie) {
12889 + if (sb_ispcie(si))
12890 + pci = FALSE;
12891 + else
12892 + pcie = FALSE;
12893 + }
12894 + if (pci) {
12895 + si->sb.buscoretype = SB_PCI;
12896 + si->sb.buscorerev = pcirev;
12897 + si->sb.buscoreidx = pciidx;
12898 + } else if (pcie) {
12899 + si->sb.buscoretype = SB_PCIE;
12900 + si->sb.buscorerev = pcierev;
12901 + si->sb.buscoreidx = pcieidx;
12902 + }
12903 +
12904 + /*
12905 + * Find the gpio "controlling core" type and index.
12906 + * Precedence:
12907 + * - if there's a chip common core - use that
12908 + * - else if there's a pci core (rev >= 2) - use that
12909 + * - else there had better be an extif core (4710 only)
12910 + */
12911 + if (GOODIDX(sb_findcoreidx(si, SB_CC, 0))) {
12912 + si->gpioidx = sb_findcoreidx(si, SB_CC, 0);
12913 + si->gpioid = SB_CC;
12914 + } else if (PCI(si) && (si->sb.buscorerev >= 2)) {
12915 + si->gpioidx = si->sb.buscoreidx;
12916 + si->gpioid = SB_PCI;
12917 + } else if (sb_findcoreidx(si, SB_EXTIF, 0)) {
12918 + si->gpioidx = sb_findcoreidx(si, SB_EXTIF, 0);
12919 + si->gpioid = SB_EXTIF;
12920 + } else
12921 + ASSERT(si->gpioidx != BADIDX);
12922 +
12923 + /* return to original core index */
12924 + sb_setcoreidx(&si->sb, origidx);
12925 +}
12926 +
12927 +/* may be called with core in reset */
12928 +void
12929 +sb_detach(sb_t *sbh)
12930 +{
12931 + sb_info_t *si;
12932 + uint idx;
12933 +
12934 + si = SB_INFO(sbh);
12935 +
12936 + if (si == NULL)
12937 + return;
12938 +
12939 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
12940 + for (idx = 0; idx < SB_MAXCORES; idx++)
12941 + if (si->regs[idx]) {
12942 + REG_UNMAP(si->regs[idx]);
12943 + si->regs[idx] = NULL;
12944 + }
12945 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
12946 + if (si != &ksi)
12947 +#endif /* !BCMBUSTYPE || (BCMBUSTYPE == SB_BUS) */
12948 + MFREE(si->osh, si, sizeof(sb_info_t));
12949 +
12950 +}
12951 +
12952 +/* use pci dev id to determine chip id for chips not having a chipcommon core */
12953 +static uint
12954 +BCMINITFN(sb_pcidev2chip)(uint pcidev)
12955 +{
12956 + if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
12957 + return (BCM4710_CHIP_ID);
12958 + if ((pcidev >= BCM4402_ENET_ID) && (pcidev <= BCM4402_V90_ID))
12959 + return (BCM4402_CHIP_ID);
12960 + if (pcidev == BCM4401_ENET_ID)
12961 + return (BCM4402_CHIP_ID);
12962 +
12963 + return (0);
12964 +}
12965 +
12966 +/* convert chip number to number of i/o cores */
12967 +static uint
12968 +BCMINITFN(sb_chip2numcores)(uint chip)
12969 +{
12970 + if (chip == BCM4710_CHIP_ID)
12971 + return (9);
12972 + if (chip == BCM4402_CHIP_ID)
12973 + return (3);
12974 + if (chip == BCM4306_CHIP_ID) /* < 4306c0 */
12975 + return (6);
12976 + if (chip == BCM4704_CHIP_ID)
12977 + return (9);
12978 + if (chip == BCM5365_CHIP_ID)
12979 + return (7);
12980 +
12981 + SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
12982 + ASSERT(0);
12983 + return (1);
12984 +}
12985 +
12986 +/* return index of coreid or BADIDX if not found */
12987 +static uint
12988 +sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit)
12989 +{
12990 + uint found;
12991 + uint i;
12992 +
12993 + found = 0;
12994 +
12995 + for (i = 0; i < si->numcores; i++)
12996 + if (si->coreid[i] == coreid) {
12997 + if (found == coreunit)
12998 + return (i);
12999 + found++;
13000 + }
13001 +
13002 + return (BADIDX);
13003 +}
13004 +
13005 +/*
13006 + * this function changes logical "focus" to the indiciated core,
13007 + * must be called with interrupt off.
13008 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
13009 + */
13010 +void*
13011 +sb_setcoreidx(sb_t *sbh, uint coreidx)
13012 +{
13013 + sb_info_t *si;
13014 + uint32 sbaddr;
13015 + uint8 tmp;
13016 +
13017 + si = SB_INFO(sbh);
13018 +
13019 + if (coreidx >= si->numcores)
13020 + return (NULL);
13021 +
13022 + /*
13023 + * If the user has provided an interrupt mask enabled function,
13024 + * then assert interrupts are disabled before switching the core.
13025 + */
13026 + ASSERT((si->intrsenabled_fn == NULL) || !(*(si)->intrsenabled_fn)((si)->intr_arg));
13027 +
13028 + sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
13029 +
13030 + switch (BUSTYPE(si->sb.bustype)) {
13031 + case SB_BUS:
13032 + /* map new one */
13033 + if (!si->regs[coreidx]) {
13034 + si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
13035 + ASSERT(GOODREGS(si->regs[coreidx]));
13036 + }
13037 + si->curmap = si->regs[coreidx];
13038 + break;
13039 +
13040 + case PCI_BUS:
13041 + /* point bar0 window */
13042 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
13043 + break;
13044 +
13045 + case PCMCIA_BUS:
13046 + tmp = (sbaddr >> 12) & 0x0f;
13047 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
13048 + tmp = (sbaddr >> 16) & 0xff;
13049 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
13050 + tmp = (sbaddr >> 24) & 0xff;
13051 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
13052 + break;
13053 +#ifdef BCMJTAG
13054 + case JTAG_BUS:
13055 + /* map new one */
13056 + if (!si->regs[coreidx]) {
13057 + si->regs[coreidx] = (void *)sbaddr;
13058 + ASSERT(GOODREGS(si->regs[coreidx]));
13059 + }
13060 + si->curmap = si->regs[coreidx];
13061 + break;
13062 +#endif /* BCMJTAG */
13063 + }
13064 +
13065 + si->curidx = coreidx;
13066 +
13067 + return (si->curmap);
13068 +}
13069 +
13070 +/*
13071 + * this function changes logical "focus" to the indiciated core,
13072 + * must be called with interrupt off.
13073 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
13074 + */
13075 +void*
13076 +sb_setcore(sb_t *sbh, uint coreid, uint coreunit)
13077 +{
13078 + sb_info_t *si;
13079 + uint idx;
13080 +
13081 + si = SB_INFO(sbh);
13082 + idx = sb_findcoreidx(si, coreid, coreunit);
13083 + if (!GOODIDX(idx))
13084 + return (NULL);
13085 +
13086 + return (sb_setcoreidx(sbh, idx));
13087 +}
13088 +
13089 +/* return chip number */
13090 +uint
13091 +sb_chip(sb_t *sbh)
13092 +{
13093 + sb_info_t *si;
13094 +
13095 + si = SB_INFO(sbh);
13096 + return (si->sb.chip);
13097 +}
13098 +
13099 +/* return chip revision number */
13100 +uint
13101 +sb_chiprev(sb_t *sbh)
13102 +{
13103 + sb_info_t *si;
13104 +
13105 + si = SB_INFO(sbh);
13106 + return (si->sb.chiprev);
13107 +}
13108 +
13109 +/* return chip common revision number */
13110 +uint
13111 +sb_chipcrev(sb_t *sbh)
13112 +{
13113 + sb_info_t *si;
13114 +
13115 + si = SB_INFO(sbh);
13116 + return (si->sb.ccrev);
13117 +}
13118 +
13119 +/* return chip package option */
13120 +uint
13121 +sb_chippkg(sb_t *sbh)
13122 +{
13123 + sb_info_t *si;
13124 +
13125 + si = SB_INFO(sbh);
13126 + return (si->sb.chippkg);
13127 +}
13128 +
13129 +/* return PCI core rev. */
13130 +uint
13131 +sb_pcirev(sb_t *sbh)
13132 +{
13133 + sb_info_t *si;
13134 +
13135 + si = SB_INFO(sbh);
13136 + return (si->sb.buscorerev);
13137 +}
13138 +
13139 +bool
13140 +BCMINITFN(sb_war16165)(sb_t *sbh)
13141 +{
13142 + sb_info_t *si;
13143 +
13144 + si = SB_INFO(sbh);
13145 +
13146 + return (PCI(si) && (si->sb.buscorerev <= 10));
13147 +}
13148 +
13149 +static void
13150 +BCMINITFN(sb_war30841)(sb_info_t *si)
13151 +{
13152 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128);
13153 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100);
13154 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466);
13155 +}
13156 +
13157 +/* return PCMCIA core rev. */
13158 +uint
13159 +BCMINITFN(sb_pcmciarev)(sb_t *sbh)
13160 +{
13161 + sb_info_t *si;
13162 +
13163 + si = SB_INFO(sbh);
13164 + return (si->sb.buscorerev);
13165 +}
13166 +
13167 +/* return board vendor id */
13168 +uint
13169 +sb_boardvendor(sb_t *sbh)
13170 +{
13171 + sb_info_t *si;
13172 +
13173 + si = SB_INFO(sbh);
13174 + return (si->sb.boardvendor);
13175 +}
13176 +
13177 +/* return boardtype */
13178 +uint
13179 +sb_boardtype(sb_t *sbh)
13180 +{
13181 + sb_info_t *si;
13182 + char *var;
13183 +
13184 + si = SB_INFO(sbh);
13185 +
13186 + if (BUSTYPE(si->sb.bustype) == SB_BUS && si->sb.boardtype == 0xffff) {
13187 + /* boardtype format is a hex string */
13188 + si->sb.boardtype = getintvar(NULL, "boardtype");
13189 +
13190 + /* backward compatibility for older boardtype string format */
13191 + if ((si->sb.boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
13192 + if (!strcmp(var, "bcm94710dev"))
13193 + si->sb.boardtype = BCM94710D_BOARD;
13194 + else if (!strcmp(var, "bcm94710ap"))
13195 + si->sb.boardtype = BCM94710AP_BOARD;
13196 + else if (!strcmp(var, "bu4710"))
13197 + si->sb.boardtype = BU4710_BOARD;
13198 + else if (!strcmp(var, "bcm94702mn"))
13199 + si->sb.boardtype = BCM94702MN_BOARD;
13200 + else if (!strcmp(var, "bcm94710r1"))
13201 + si->sb.boardtype = BCM94710R1_BOARD;
13202 + else if (!strcmp(var, "bcm94710r4"))
13203 + si->sb.boardtype = BCM94710R4_BOARD;
13204 + else if (!strcmp(var, "bcm94702cpci"))
13205 + si->sb.boardtype = BCM94702CPCI_BOARD;
13206 + else if (!strcmp(var, "bcm95380_rr"))
13207 + si->sb.boardtype = BCM95380RR_BOARD;
13208 + }
13209 + }
13210 +
13211 + return (si->sb.boardtype);
13212 +}
13213 +
13214 +/* return bus type of sbh device */
13215 +uint
13216 +sb_bus(sb_t *sbh)
13217 +{
13218 + sb_info_t *si;
13219 +
13220 + si = SB_INFO(sbh);
13221 + return (si->sb.bustype);
13222 +}
13223 +
13224 +/* return bus core type */
13225 +uint
13226 +sb_buscoretype(sb_t *sbh)
13227 +{
13228 + sb_info_t *si;
13229 +
13230 + si = SB_INFO(sbh);
13231 +
13232 + return (si->sb.buscoretype);
13233 +}
13234 +
13235 +/* return bus core revision */
13236 +uint
13237 +sb_buscorerev(sb_t *sbh)
13238 +{
13239 + sb_info_t *si;
13240 + si = SB_INFO(sbh);
13241 +
13242 + return (si->sb.buscorerev);
13243 +}
13244 +
13245 +/* return list of found cores */
13246 +uint
13247 +sb_corelist(sb_t *sbh, uint coreid[])
13248 +{
13249 + sb_info_t *si;
13250 +
13251 + si = SB_INFO(sbh);
13252 +
13253 + bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof(uint)));
13254 + return (si->numcores);
13255 +}
13256 +
13257 +/* return current register mapping */
13258 +void *
13259 +sb_coreregs(sb_t *sbh)
13260 +{
13261 + sb_info_t *si;
13262 +
13263 + si = SB_INFO(sbh);
13264 + ASSERT(GOODREGS(si->curmap));
13265 +
13266 + return (si->curmap);
13267 +}
13268 +
13269 +
13270 +/* do buffered registers update */
13271 +void
13272 +sb_commit(sb_t *sbh)
13273 +{
13274 + sb_info_t *si;
13275 + uint origidx;
13276 + uint intr_val = 0;
13277 +
13278 + si = SB_INFO(sbh);
13279 +
13280 + origidx = si->curidx;
13281 + ASSERT(GOODIDX(origidx));
13282 +
13283 + INTR_OFF(si, intr_val);
13284 +
13285 + /* switch over to chipcommon core if there is one, else use pci */
13286 + if (si->sb.ccrev != NOREV) {
13287 + chipcregs_t *ccregs = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
13288 +
13289 + /* do the buffer registers update */
13290 + W_REG(si->osh, &ccregs->broadcastaddress, SB_COMMIT);
13291 + W_REG(si->osh, &ccregs->broadcastdata, 0x0);
13292 + } else if (PCI(si)) {
13293 + sbpciregs_t *pciregs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
13294 +
13295 + /* do the buffer registers update */
13296 + W_REG(si->osh, &pciregs->bcastaddr, SB_COMMIT);
13297 + W_REG(si->osh, &pciregs->bcastdata, 0x0);
13298 + } else
13299 + ASSERT(0);
13300 +
13301 + /* restore core index */
13302 + sb_setcoreidx(sbh, origidx);
13303 + INTR_RESTORE(si, intr_val);
13304 +}
13305 +
13306 +/* reset and re-enable a core
13307 + * inputs:
13308 + * bits - core specific bits that are set during and after reset sequence
13309 + * resetbits - core specific bits that are set only during reset sequence
13310 + */
13311 +void
13312 +sb_core_reset(sb_t *sbh, uint32 bits, uint32 resetbits)
13313 +{
13314 + sb_info_t *si;
13315 + sbconfig_t *sb;
13316 + volatile uint32 dummy;
13317 +
13318 + si = SB_INFO(sbh);
13319 + ASSERT(GOODREGS(si->curmap));
13320 + sb = REGS2SB(si->curmap);
13321 +
13322 + /*
13323 + * Must do the disable sequence first to work for arbitrary current core state.
13324 + */
13325 + sb_core_disable(sbh, (bits | resetbits));
13326 +
13327 + /*
13328 + * Now do the initialization sequence.
13329 + */
13330 +
13331 + /* set reset while enabling the clock and forcing them on throughout the core */
13332 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits | resetbits));
13333 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13334 + OSL_DELAY(1);
13335 +
13336 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_SERR) {
13337 + W_SBREG(si, &sb->sbtmstatehigh, 0);
13338 + }
13339 + if ((dummy = R_SBREG(si, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
13340 + AND_SBREG(si, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
13341 + }
13342 +
13343 + /* clear reset and allow it to propagate throughout the core */
13344 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
13345 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13346 + OSL_DELAY(1);
13347 +
13348 + /* leave clock enabled */
13349 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_CLK | bits));
13350 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13351 + OSL_DELAY(1);
13352 +}
13353 +
13354 +void
13355 +sb_core_tofixup(sb_t *sbh)
13356 +{
13357 + sb_info_t *si;
13358 + sbconfig_t *sb;
13359 +
13360 + si = SB_INFO(sbh);
13361 +
13362 + if ((BUSTYPE(si->sb.bustype) != PCI_BUS) || PCIE(si) ||
13363 + (PCI(si) && (si->sb.buscorerev >= 5)))
13364 + return;
13365 +
13366 + ASSERT(GOODREGS(si->curmap));
13367 + sb = REGS2SB(si->curmap);
13368 +
13369 + if (BUSTYPE(si->sb.bustype) == SB_BUS) {
13370 + SET_SBREG(si, &sb->sbimconfiglow,
13371 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
13372 + (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
13373 + } else {
13374 + if (sb_coreid(sbh) == SB_PCI) {
13375 + SET_SBREG(si, &sb->sbimconfiglow,
13376 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
13377 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
13378 + } else {
13379 + SET_SBREG(si, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
13380 + }
13381 + }
13382 +
13383 + sb_commit(sbh);
13384 +}
13385 +
13386 +/*
13387 + * Set the initiator timeout for the "master core".
13388 + * The master core is defined to be the core in control
13389 + * of the chip and so it issues accesses to non-memory
13390 + * locations (Because of dma *any* core can access memeory).
13391 + *
13392 + * The routine uses the bus to decide who is the master:
13393 + * SB_BUS => mips
13394 + * JTAG_BUS => chipc
13395 + * PCI_BUS => pci or pcie
13396 + * PCMCIA_BUS => pcmcia
13397 + * SDIO_BUS => pcmcia
13398 + *
13399 + * This routine exists so callers can disable initiator
13400 + * timeouts so accesses to very slow devices like otp
13401 + * won't cause an abort. The routine allows arbitrary
13402 + * settings of the service and request timeouts, though.
13403 + *
13404 + * Returns the timeout state before changing it or -1
13405 + * on error.
13406 + */
13407 +
13408 +#define TO_MASK (SBIMCL_RTO_MASK | SBIMCL_STO_MASK)
13409 +
13410 +uint32
13411 +sb_set_initiator_to(sb_t *sbh, uint32 to)
13412 +{
13413 + sb_info_t *si;
13414 + uint origidx, idx;
13415 + uint intr_val = 0;
13416 + uint32 tmp, ret = 0xffffffff;
13417 + sbconfig_t *sb;
13418 +
13419 + si = SB_INFO(sbh);
13420 +
13421 + if ((to & ~TO_MASK) != 0)
13422 + return ret;
13423 +
13424 + /* Figure out the master core */
13425 + idx = BADIDX;
13426 + switch (BUSTYPE(si->sb.bustype)) {
13427 + case PCI_BUS:
13428 + idx = si->sb.buscoreidx;
13429 + break;
13430 + case JTAG_BUS:
13431 + idx = SB_CC_IDX;
13432 + break;
13433 + case PCMCIA_BUS:
13434 + case SDIO_BUS:
13435 + idx = sb_findcoreidx(si, SB_PCMCIA, 0);
13436 + break;
13437 + case SB_BUS:
13438 + if ((idx = sb_findcoreidx(si, SB_MIPS33, 0)) == BADIDX)
13439 + idx = sb_findcoreidx(si, SB_MIPS, 0);
13440 + break;
13441 + default:
13442 + ASSERT(0);
13443 + }
13444 + if (idx == BADIDX)
13445 + return ret;
13446 +
13447 + INTR_OFF(si, intr_val);
13448 + origidx = sb_coreidx(sbh);
13449 +
13450 + sb = REGS2SB(sb_setcoreidx(sbh, idx));
13451 +
13452 + tmp = R_SBREG(si, &sb->sbimconfiglow);
13453 + ret = tmp & TO_MASK;
13454 + W_SBREG(si, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
13455 +
13456 + sb_commit(sbh);
13457 + sb_setcoreidx(sbh, origidx);
13458 + INTR_RESTORE(si, intr_val);
13459 + return ret;
13460 +}
13461 +
13462 +void
13463 +sb_core_disable(sb_t *sbh, uint32 bits)
13464 +{
13465 + sb_info_t *si;
13466 + volatile uint32 dummy;
13467 + uint32 rej;
13468 + sbconfig_t *sb;
13469 +
13470 + si = SB_INFO(sbh);
13471 +
13472 + ASSERT(GOODREGS(si->curmap));
13473 + sb = REGS2SB(si->curmap);
13474 +
13475 + /* if core is already in reset, just return */
13476 + if (R_SBREG(si, &sb->sbtmstatelow) & SBTML_RESET)
13477 + return;
13478 +
13479 + /* reject value changed between sonics 2.2 and 2.3 */
13480 + if (si->sb.sonicsrev == SONICS_2_2)
13481 + rej = (1 << SBTML_REJ_SHIFT);
13482 + else
13483 + rej = (2 << SBTML_REJ_SHIFT);
13484 +
13485 + /* if clocks are not enabled, put into reset and return */
13486 + if ((R_SBREG(si, &sb->sbtmstatelow) & SBTML_CLK) == 0)
13487 + goto disable;
13488 +
13489 + /* set target reject and spin until busy is clear (preserve core-specific bits) */
13490 + OR_SBREG(si, &sb->sbtmstatelow, rej);
13491 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13492 + OSL_DELAY(1);
13493 + SPINWAIT((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
13494 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY)
13495 + SB_ERROR(("%s: target state still busy\n", __FUNCTION__));
13496 +
13497 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT) {
13498 + OR_SBREG(si, &sb->sbimstate, SBIM_RJ);
13499 + dummy = R_SBREG(si, &sb->sbimstate);
13500 + OSL_DELAY(1);
13501 + SPINWAIT((R_SBREG(si, &sb->sbimstate) & SBIM_BY), 100000);
13502 + }
13503 +
13504 + /* set reset and reject while enabling the clocks */
13505 + W_SBREG(si, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | rej | SBTML_RESET));
13506 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13507 + OSL_DELAY(10);
13508 +
13509 + /* don't forget to clear the initiator reject bit */
13510 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT)
13511 + AND_SBREG(si, &sb->sbimstate, ~SBIM_RJ);
13512 +
13513 +disable:
13514 + /* leave reset and reject asserted */
13515 + W_SBREG(si, &sb->sbtmstatelow, (bits | rej | SBTML_RESET));
13516 + OSL_DELAY(1);
13517 +}
13518 +
13519 +/* set chip watchdog reset timer to fire in 'ticks' backplane cycles */
13520 +void
13521 +sb_watchdog(sb_t *sbh, uint ticks)
13522 +{
13523 + sb_info_t *si = SB_INFO(sbh);
13524 +
13525 + /* make sure we come up in fast clock mode */
13526 + sb_clkctl_clk(sbh, CLK_FAST);
13527 +
13528 + /* instant NMI */
13529 + switch (si->gpioid) {
13530 + case SB_CC:
13531 +#ifdef __mips__
13532 + if (sb_chip(sbh) == BCM4785_CHIP_ID && ticks <= 1)
13533 + MTC0(C0_BROADCOM, 4, (1 << 22));
13534 +#endif /* __mips__ */
13535 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
13536 +#ifdef __mips__
13537 + if (sb_chip(sbh) == BCM4785_CHIP_ID && ticks <= 1) {
13538 + __asm__ __volatile__ (
13539 + ".set\tmips3\n\t"
13540 + "sync\n\t"
13541 + "wait\n\t"
13542 + ".set\tmips0"
13543 + );
13544 + while (1);
13545 + }
13546 +#endif /* __mips__ */
13547 + break;
13548 + case SB_EXTIF:
13549 + sb_corereg(si, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
13550 + break;
13551 + }
13552 +}
13553 +
13554 +/* initialize the pcmcia core */
13555 +void
13556 +sb_pcmcia_init(sb_t *sbh)
13557 +{
13558 + sb_info_t *si;
13559 + uint8 cor = 0;
13560 +
13561 + si = SB_INFO(sbh);
13562 +
13563 + /* enable d11 mac interrupts */
13564 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
13565 + cor |= COR_IRQEN | COR_FUNEN;
13566 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
13567 +
13568 +}
13569 +
13570 +
13571 +/*
13572 + * Configure the pci core for pci client (NIC) action
13573 + * coremask is the bitvec of cores by index to be enabled.
13574 + */
13575 +void
13576 +BCMINITFN(sb_pci_setup)(sb_t *sbh, uint coremask)
13577 +{
13578 + sb_info_t *si;
13579 + sbconfig_t *sb;
13580 + sbpciregs_t *pciregs;
13581 + uint32 sbflag;
13582 + uint32 w;
13583 + uint idx;
13584 + int reg_val;
13585 +
13586 + si = SB_INFO(sbh);
13587 +
13588 + /* if not pci bus, we're done */
13589 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
13590 + return;
13591 +
13592 + ASSERT(PCI(si) || PCIE(si));
13593 + ASSERT(si->sb.buscoreidx != BADIDX);
13594 +
13595 + /* get current core index */
13596 + idx = si->curidx;
13597 +
13598 + /* we interrupt on this backplane flag number */
13599 + ASSERT(GOODREGS(si->curmap));
13600 + sb = REGS2SB(si->curmap);
13601 + sbflag = R_SBREG(si, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
13602 +
13603 + /* switch over to pci core */
13604 + pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->sb.buscoreidx);
13605 + sb = REGS2SB(pciregs);
13606 +
13607 + /*
13608 + * Enable sb->pci interrupts. Assume
13609 + * PCI rev 2.3 support was added in pci core rev 6 and things changed..
13610 + */
13611 + if (PCIE(si) || (PCI(si) && ((si->sb.buscorerev) >= 6))) {
13612 + /* pci config write to set this core bit in PCIIntMask */
13613 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
13614 + w |= (coremask << PCI_SBIM_SHIFT);
13615 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
13616 + } else {
13617 + /* set sbintvec bit for our flag number */
13618 + OR_SBREG(si, &sb->sbintvec, (1 << sbflag));
13619 + }
13620 +
13621 + if (PCI(si)) {
13622 + OR_REG(si->osh, &pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
13623 + if (si->sb.buscorerev >= 11)
13624 + OR_REG(si->osh, &pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
13625 + if (si->sb.buscorerev < 5) {
13626 + SET_SBREG(si, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
13627 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
13628 + sb_commit(sbh);
13629 + }
13630 + }
13631 +
13632 +#ifdef PCIE_SUPPOER
13633 + /* PCIE workarounds */
13634 + if (PCIE(si)) {
13635 + if ((si->sb.buscorerev == 0) || (si->sb.buscorerev == 1)) {
13636 + reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS,
13637 + PCIE_TLP_WORKAROUNDSREG);
13638 + reg_val |= 0x8;
13639 + sb_pcie_writereg((void *)sbh, (void *)PCIE_PCIEREGS,
13640 + PCIE_TLP_WORKAROUNDSREG, reg_val);
13641 + }
13642 +
13643 + if (si->sb.buscorerev == 1) {
13644 + reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS,
13645 + PCIE_DLLP_LCREG);
13646 + reg_val |= (0x40);
13647 + sb_pcie_writereg(sbh, (void *)PCIE_PCIEREGS, PCIE_DLLP_LCREG, reg_val);
13648 + }
13649 +
13650 + if (si->sb.buscorerev == 0)
13651 + sb_war30841(si);
13652 + }
13653 +#endif
13654 +
13655 + /* switch back to previous core */
13656 + sb_setcoreidx(sbh, idx);
13657 +}
13658 +
13659 +uint32
13660 +sb_base(uint32 admatch)
13661 +{
13662 + uint32 base;
13663 + uint type;
13664 +
13665 + type = admatch & SBAM_TYPE_MASK;
13666 + ASSERT(type < 3);
13667 +
13668 + base = 0;
13669 +
13670 + if (type == 0) {
13671 + base = admatch & SBAM_BASE0_MASK;
13672 + } else if (type == 1) {
13673 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13674 + base = admatch & SBAM_BASE1_MASK;
13675 + } else if (type == 2) {
13676 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13677 + base = admatch & SBAM_BASE2_MASK;
13678 + }
13679 +
13680 + return (base);
13681 +}
13682 +
13683 +uint32
13684 +sb_size(uint32 admatch)
13685 +{
13686 + uint32 size;
13687 + uint type;
13688 +
13689 + type = admatch & SBAM_TYPE_MASK;
13690 + ASSERT(type < 3);
13691 +
13692 + size = 0;
13693 +
13694 + if (type == 0) {
13695 + size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
13696 + } else if (type == 1) {
13697 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13698 + size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
13699 + } else if (type == 2) {
13700 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13701 + size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
13702 + }
13703 +
13704 + return (size);
13705 +}
13706 +
13707 +/* return the core-type instantiation # of the current core */
13708 +uint
13709 +sb_coreunit(sb_t *sbh)
13710 +{
13711 + sb_info_t *si;
13712 + uint idx;
13713 + uint coreid;
13714 + uint coreunit;
13715 + uint i;
13716 +
13717 + si = SB_INFO(sbh);
13718 + coreunit = 0;
13719 +
13720 + idx = si->curidx;
13721 +
13722 + ASSERT(GOODREGS(si->curmap));
13723 + coreid = sb_coreid(sbh);
13724 +
13725 + /* count the cores of our type */
13726 + for (i = 0; i < idx; i++)
13727 + if (si->coreid[i] == coreid)
13728 + coreunit++;
13729 +
13730 + return (coreunit);
13731 +}
13732 +
13733 +static INLINE uint32
13734 +factor6(uint32 x)
13735 +{
13736 + switch (x) {
13737 + case CC_F6_2: return 2;
13738 + case CC_F6_3: return 3;
13739 + case CC_F6_4: return 4;
13740 + case CC_F6_5: return 5;
13741 + case CC_F6_6: return 6;
13742 + case CC_F6_7: return 7;
13743 + default: return 0;
13744 + }
13745 +}
13746 +
13747 +/* calculate the speed the SB would run at given a set of clockcontrol values */
13748 +uint32
13749 +sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
13750 +{
13751 + uint32 n1, n2, clock, m1, m2, m3, mc;
13752 +
13753 + n1 = n & CN_N1_MASK;
13754 + n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
13755 +
13756 + if (pll_type == PLL_TYPE6) {
13757 + if (m & CC_T6_MMASK)
13758 + return CC_T6_M1;
13759 + else
13760 + return CC_T6_M0;
13761 + } else if ((pll_type == PLL_TYPE1) ||
13762 + (pll_type == PLL_TYPE3) ||
13763 + (pll_type == PLL_TYPE4) ||
13764 + (pll_type == PLL_TYPE7)) {
13765 + n1 = factor6(n1);
13766 + n2 += CC_F5_BIAS;
13767 + } else if (pll_type == PLL_TYPE2) {
13768 + n1 += CC_T2_BIAS;
13769 + n2 += CC_T2_BIAS;
13770 + ASSERT((n1 >= 2) && (n1 <= 7));
13771 + ASSERT((n2 >= 5) && (n2 <= 23));
13772 + } else if (pll_type == PLL_TYPE5) {
13773 + return (100000000);
13774 + } else
13775 + ASSERT(0);
13776 + /* PLL types 3 and 7 use BASE2 (25Mhz) */
13777 + if ((pll_type == PLL_TYPE3) ||
13778 + (pll_type == PLL_TYPE7)) {
13779 + clock = CC_CLOCK_BASE2 * n1 * n2;
13780 + } else
13781 + clock = CC_CLOCK_BASE1 * n1 * n2;
13782 +
13783 + if (clock == 0)
13784 + return 0;
13785 +
13786 + m1 = m & CC_M1_MASK;
13787 + m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
13788 + m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
13789 + mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
13790 +
13791 + if ((pll_type == PLL_TYPE1) ||
13792 + (pll_type == PLL_TYPE3) ||
13793 + (pll_type == PLL_TYPE4) ||
13794 + (pll_type == PLL_TYPE7)) {
13795 + m1 = factor6(m1);
13796 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
13797 + m2 += CC_F5_BIAS;
13798 + else
13799 + m2 = factor6(m2);
13800 + m3 = factor6(m3);
13801 +
13802 + switch (mc) {
13803 + case CC_MC_BYPASS: return (clock);
13804 + case CC_MC_M1: return (clock / m1);
13805 + case CC_MC_M1M2: return (clock / (m1 * m2));
13806 + case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
13807 + case CC_MC_M1M3: return (clock / (m1 * m3));
13808 + default: return (0);
13809 + }
13810 + } else {
13811 + ASSERT(pll_type == PLL_TYPE2);
13812 +
13813 + m1 += CC_T2_BIAS;
13814 + m2 += CC_T2M2_BIAS;
13815 + m3 += CC_T2_BIAS;
13816 + ASSERT((m1 >= 2) && (m1 <= 7));
13817 + ASSERT((m2 >= 3) && (m2 <= 10));
13818 + ASSERT((m3 >= 2) && (m3 <= 7));
13819 +
13820 + if ((mc & CC_T2MC_M1BYP) == 0)
13821 + clock /= m1;
13822 + if ((mc & CC_T2MC_M2BYP) == 0)
13823 + clock /= m2;
13824 + if ((mc & CC_T2MC_M3BYP) == 0)
13825 + clock /= m3;
13826 +
13827 + return (clock);
13828 + }
13829 +}
13830 +
13831 +/* returns the current speed the SB is running at */
13832 +uint32
13833 +sb_clock(sb_t *sbh)
13834 +{
13835 + sb_info_t *si;
13836 + extifregs_t *eir;
13837 + chipcregs_t *cc;
13838 + uint32 n, m;
13839 + uint idx;
13840 + uint32 pll_type, rate;
13841 + uint intr_val = 0;
13842 +
13843 + si = SB_INFO(sbh);
13844 + idx = si->curidx;
13845 + pll_type = PLL_TYPE1;
13846 +
13847 + INTR_OFF(si, intr_val);
13848 +
13849 + /* switch to extif or chipc core */
13850 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
13851 + n = R_REG(si->osh, &eir->clockcontrol_n);
13852 + m = R_REG(si->osh, &eir->clockcontrol_sb);
13853 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
13854 + pll_type = R_REG(si->osh, &cc->capabilities) & CAP_PLL_MASK;
13855 + if (pll_type == PLL_NONE) {
13856 + INTR_RESTORE(si, intr_val);
13857 + return 80000000;
13858 + }
13859 + n = R_REG(si->osh, &cc->clockcontrol_n);
13860 + if (pll_type == PLL_TYPE6)
13861 + m = R_REG(si->osh, &cc->clockcontrol_m3);
13862 + else if ((pll_type == PLL_TYPE3) && !(BCMINIT(sb_chip)(sbh) == 0x5365))
13863 + m = R_REG(si->osh, &cc->clockcontrol_m2);
13864 + else
13865 + m = R_REG(si->osh, &cc->clockcontrol_sb);
13866 + } else {
13867 + INTR_RESTORE(si, intr_val);
13868 + return 0;
13869 + }
13870 +
13871 + /* calculate rate */
13872 + if (BCMINIT(sb_chip)(sbh) == 0x5365)
13873 + rate = 100000000;
13874 + else {
13875 + rate = sb_clock_rate(pll_type, n, m);
13876 +
13877 + if (pll_type == PLL_TYPE3)
13878 + rate = rate / 2;
13879 + }
13880 +
13881 + /* switch back to previous core */
13882 + sb_setcoreidx(sbh, idx);
13883 +
13884 + INTR_RESTORE(si, intr_val);
13885 +
13886 + return rate;
13887 +}
13888 +
13889 +/* change logical "focus" to the gpio core for optimized access */
13890 +void*
13891 +sb_gpiosetcore(sb_t *sbh)
13892 +{
13893 + sb_info_t *si;
13894 +
13895 + si = SB_INFO(sbh);
13896 +
13897 + return (sb_setcoreidx(sbh, si->gpioidx));
13898 +}
13899 +
13900 +/* mask&set gpiocontrol bits */
13901 +uint32
13902 +sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
13903 +{
13904 + sb_info_t *si;
13905 + uint regoff;
13906 +
13907 + si = SB_INFO(sbh);
13908 + regoff = 0;
13909 +
13910 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
13911 +
13912 + /* gpios could be shared on router platforms */
13913 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
13914 + mask = priority ? (sb_gpioreservation & mask) :
13915 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
13916 + val &= mask;
13917 + }
13918 +
13919 + switch (si->gpioid) {
13920 + case SB_CC:
13921 + regoff = OFFSETOF(chipcregs_t, gpiocontrol);
13922 + break;
13923 +
13924 + case SB_PCI:
13925 + regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
13926 + break;
13927 +
13928 + case SB_EXTIF:
13929 + return (0);
13930 + }
13931 +
13932 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
13933 +}
13934 +
13935 +/* mask&set gpio output enable bits */
13936 +uint32
13937 +sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
13938 +{
13939 + sb_info_t *si;
13940 + uint regoff;
13941 +
13942 + si = SB_INFO(sbh);
13943 + regoff = 0;
13944 +
13945 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
13946 +
13947 + /* gpios could be shared on router platforms */
13948 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
13949 + mask = priority ? (sb_gpioreservation & mask) :
13950 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
13951 + val &= mask;
13952 + }
13953 +
13954 + switch (si->gpioid) {
13955 + case SB_CC:
13956 + regoff = OFFSETOF(chipcregs_t, gpioouten);
13957 + break;
13958 +
13959 + case SB_PCI:
13960 + regoff = OFFSETOF(sbpciregs_t, gpioouten);
13961 + break;
13962 +
13963 + case SB_EXTIF:
13964 + regoff = OFFSETOF(extifregs_t, gpio[0].outen);
13965 + break;
13966 + }
13967 +
13968 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
13969 +}
13970 +
13971 +/* mask&set gpio output bits */
13972 +uint32
13973 +sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
13974 +{
13975 + sb_info_t *si;
13976 + uint regoff;
13977 +
13978 + si = SB_INFO(sbh);
13979 + regoff = 0;
13980 +
13981 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
13982 +
13983 + /* gpios could be shared on router platforms */
13984 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
13985 + mask = priority ? (sb_gpioreservation & mask) :
13986 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
13987 + val &= mask;
13988 + }
13989 +
13990 + switch (si->gpioid) {
13991 + case SB_CC:
13992 + regoff = OFFSETOF(chipcregs_t, gpioout);
13993 + break;
13994 +
13995 + case SB_PCI:
13996 + regoff = OFFSETOF(sbpciregs_t, gpioout);
13997 + break;
13998 +
13999 + case SB_EXTIF:
14000 + regoff = OFFSETOF(extifregs_t, gpio[0].out);
14001 + break;
14002 + }
14003 +
14004 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14005 +}
14006 +
14007 +/* reserve one gpio */
14008 +uint32
14009 +sb_gpioreserve(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
14010 +{
14011 + sb_info_t *si;
14012 +
14013 + si = SB_INFO(sbh);
14014 +
14015 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14016 +
14017 + /* only cores on SB_BUS share GPIO's and only applcation users need to
14018 + * reserve/release GPIO
14019 + */
14020 + if ((BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
14021 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
14022 + return -1;
14023 + }
14024 + /* make sure only one bit is set */
14025 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
14026 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
14027 + return -1;
14028 + }
14029 +
14030 + /* already reserved */
14031 + if (sb_gpioreservation & gpio_bitmask)
14032 + return -1;
14033 + /* set reservation */
14034 + sb_gpioreservation |= gpio_bitmask;
14035 +
14036 + return sb_gpioreservation;
14037 +}
14038 +
14039 +/* release one gpio */
14040 +/*
14041 + * releasing the gpio doesn't change the current value on the GPIO last write value
14042 + * persists till some one overwrites it
14043 +*/
14044 +
14045 +uint32
14046 +sb_gpiorelease(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
14047 +{
14048 + sb_info_t *si;
14049 +
14050 + si = SB_INFO(sbh);
14051 +
14052 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14053 +
14054 + /* only cores on SB_BUS share GPIO's and only applcation users need to
14055 + * reserve/release GPIO
14056 + */
14057 + if ((BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
14058 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
14059 + return -1;
14060 + }
14061 + /* make sure only one bit is set */
14062 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
14063 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
14064 + return -1;
14065 + }
14066 +
14067 + /* already released */
14068 + if (!(sb_gpioreservation & gpio_bitmask))
14069 + return -1;
14070 +
14071 + /* clear reservation */
14072 + sb_gpioreservation &= ~gpio_bitmask;
14073 +
14074 + return sb_gpioreservation;
14075 +}
14076 +
14077 +/* return the current gpioin register value */
14078 +uint32
14079 +sb_gpioin(sb_t *sbh)
14080 +{
14081 + sb_info_t *si;
14082 + uint regoff;
14083 +
14084 + si = SB_INFO(sbh);
14085 + regoff = 0;
14086 +
14087 + switch (si->gpioid) {
14088 + case SB_CC:
14089 + regoff = OFFSETOF(chipcregs_t, gpioin);
14090 + break;
14091 +
14092 + case SB_PCI:
14093 + regoff = OFFSETOF(sbpciregs_t, gpioin);
14094 + break;
14095 +
14096 + case SB_EXTIF:
14097 + regoff = OFFSETOF(extifregs_t, gpioin);
14098 + break;
14099 + }
14100 +
14101 + return (sb_corereg(si, si->gpioidx, regoff, 0, 0));
14102 +}
14103 +
14104 +/* mask&set gpio interrupt polarity bits */
14105 +uint32
14106 +sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
14107 +{
14108 + sb_info_t *si;
14109 + uint regoff;
14110 +
14111 + si = SB_INFO(sbh);
14112 + regoff = 0;
14113 +
14114 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14115 +
14116 + /* gpios could be shared on router platforms */
14117 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
14118 + mask = priority ? (sb_gpioreservation & mask) :
14119 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
14120 + val &= mask;
14121 + }
14122 +
14123 + switch (si->gpioid) {
14124 + case SB_CC:
14125 + regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
14126 + break;
14127 +
14128 + case SB_PCI:
14129 + /* pci gpio implementation does not support interrupt polarity */
14130 + ASSERT(0);
14131 + break;
14132 +
14133 + case SB_EXTIF:
14134 + regoff = OFFSETOF(extifregs_t, gpiointpolarity);
14135 + break;
14136 + }
14137 +
14138 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14139 +}
14140 +
14141 +/* mask&set gpio interrupt mask bits */
14142 +uint32
14143 +sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
14144 +{
14145 + sb_info_t *si;
14146 + uint regoff;
14147 +
14148 + si = SB_INFO(sbh);
14149 + regoff = 0;
14150 +
14151 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14152 +
14153 + /* gpios could be shared on router platforms */
14154 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
14155 + mask = priority ? (sb_gpioreservation & mask) :
14156 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
14157 + val &= mask;
14158 + }
14159 +
14160 + switch (si->gpioid) {
14161 + case SB_CC:
14162 + regoff = OFFSETOF(chipcregs_t, gpiointmask);
14163 + break;
14164 +
14165 + case SB_PCI:
14166 + /* pci gpio implementation does not support interrupt mask */
14167 + ASSERT(0);
14168 + break;
14169 +
14170 + case SB_EXTIF:
14171 + regoff = OFFSETOF(extifregs_t, gpiointmask);
14172 + break;
14173 + }
14174 +
14175 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14176 +}
14177 +
14178 +/* assign the gpio to an led */
14179 +uint32
14180 +sb_gpioled(sb_t *sbh, uint32 mask, uint32 val)
14181 +{
14182 + sb_info_t *si;
14183 +
14184 + si = SB_INFO(sbh);
14185 + if (si->sb.ccrev < 16)
14186 + return -1;
14187 +
14188 + /* gpio led powersave reg */
14189 + return (sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
14190 +}
14191 +
14192 +/* mask & set gpio timer val */
14193 +uint32
14194 +sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 gpiotimerval)
14195 +{
14196 + sb_info_t *si;
14197 + si = SB_INFO(sbh);
14198 +
14199 + if (si->sb.ccrev < 16)
14200 + return -1;
14201 +
14202 + return (sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), mask, gpiotimerval));
14203 +}
14204 +
14205 +
14206 +/* return the slow clock source - LPO, XTAL, or PCI */
14207 +static uint
14208 +sb_slowclk_src(sb_info_t *si)
14209 +{
14210 + chipcregs_t *cc;
14211 +
14212 +
14213 + ASSERT(sb_coreid(&si->sb) == SB_CC);
14214 +
14215 + if (si->sb.ccrev < 6) {
14216 + if ((BUSTYPE(si->sb.bustype) == PCI_BUS) &&
14217 + (OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof(uint32)) &
14218 + PCI_CFG_GPIO_SCS))
14219 + return (SCC_SS_PCI);
14220 + else
14221 + return (SCC_SS_XTAL);
14222 + } else if (si->sb.ccrev < 10) {
14223 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
14224 + return (R_REG(si->osh, &cc->slow_clk_ctl) & SCC_SS_MASK);
14225 + } else /* Insta-clock */
14226 + return (SCC_SS_XTAL);
14227 +}
14228 +
14229 +/* return the ILP (slowclock) min or max frequency */
14230 +static uint
14231 +sb_slowclk_freq(sb_info_t *si, bool max)
14232 +{
14233 + chipcregs_t *cc;
14234 + uint32 slowclk;
14235 + uint div;
14236 +
14237 +
14238 + ASSERT(sb_coreid(&si->sb) == SB_CC);
14239 +
14240 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
14241 +
14242 + /* shouldn't be here unless we've established the chip has dynamic clk control */
14243 + ASSERT(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL);
14244 +
14245 + slowclk = sb_slowclk_src(si);
14246 + if (si->sb.ccrev < 6) {
14247 + if (slowclk == SCC_SS_PCI)
14248 + return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
14249 + else
14250 + return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
14251 + } else if (si->sb.ccrev < 10) {
14252 + div = 4 * (((R_REG(si->osh, &cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
14253 + if (slowclk == SCC_SS_LPO)
14254 + return (max? LPOMAXFREQ : LPOMINFREQ);
14255 + else if (slowclk == SCC_SS_XTAL)
14256 + return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
14257 + else if (slowclk == SCC_SS_PCI)
14258 + return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
14259 + else
14260 + ASSERT(0);
14261 + } else {
14262 + /* Chipc rev 10 is InstaClock */
14263 + div = R_REG(si->osh, &cc->system_clk_ctl) >> SYCC_CD_SHIFT;
14264 + div = 4 * (div + 1);
14265 + return (max ? XTALMAXFREQ : (XTALMINFREQ/div));
14266 + }
14267 + return (0);
14268 +}
14269 +
14270 +static void
14271 +BCMINITFN(sb_clkctl_setdelay)(sb_info_t *si, void *chipcregs)
14272 +{
14273 + chipcregs_t * cc;
14274 + uint slowmaxfreq, pll_delay, slowclk;
14275 + uint pll_on_delay, fref_sel_delay;
14276 +
14277 + pll_delay = PLL_DELAY;
14278 +
14279 + /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
14280 + * since the xtal will also be powered down by dynamic clk control logic.
14281 + */
14282 +
14283 + slowclk = sb_slowclk_src(si);
14284 + if (slowclk != SCC_SS_XTAL)
14285 + pll_delay += XTAL_ON_DELAY;
14286 +
14287 + /* Starting with 4318 it is ILP that is used for the delays */
14288 + slowmaxfreq = sb_slowclk_freq(si, (si->sb.ccrev >= 10) ? FALSE : TRUE);
14289 +
14290 + pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
14291 + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
14292 +
14293 + cc = (chipcregs_t *)chipcregs;
14294 + W_REG(si->osh, &cc->pll_on_delay, pll_on_delay);
14295 + W_REG(si->osh, &cc->fref_sel_delay, fref_sel_delay);
14296 +}
14297 +
14298 +/* initialize power control delay registers */
14299 +void
14300 +BCMINITFN(sb_clkctl_init)(sb_t *sbh)
14301 +{
14302 + sb_info_t *si;
14303 + uint origidx;
14304 + chipcregs_t *cc;
14305 +
14306 + si = SB_INFO(sbh);
14307 +
14308 + origidx = si->curidx;
14309 +
14310 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
14311 + return;
14312 +
14313 + if ((si->sb.chip == BCM4321_CHIP_ID) && (si->sb.chiprev < 2))
14314 + W_REG(si->osh, &cc->chipcontrol,
14315 + (si->sb.chiprev == 0) ? CHIPCTRL_4321A0_DEFAULT : CHIPCTRL_4321A1_DEFAULT);
14316 +
14317 + if (!(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL))
14318 + goto done;
14319 +
14320 + /* set all Instaclk chip ILP to 1 MHz */
14321 + else if (si->sb.ccrev >= 10)
14322 + SET_REG(si->osh, &cc->system_clk_ctl, SYCC_CD_MASK,
14323 + (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
14324 +
14325 + sb_clkctl_setdelay(si, (void *)cc);
14326 +
14327 +done:
14328 + sb_setcoreidx(sbh, origidx);
14329 +}
14330 +
14331 +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
14332 +uint16
14333 +sb_clkctl_fast_pwrup_delay(sb_t *sbh)
14334 +{
14335 + sb_info_t *si;
14336 + uint origidx;
14337 + chipcregs_t *cc;
14338 + uint slowminfreq;
14339 + uint16 fpdelay;
14340 + uint intr_val = 0;
14341 +
14342 + si = SB_INFO(sbh);
14343 + fpdelay = 0;
14344 + origidx = si->curidx;
14345 +
14346 + INTR_OFF(si, intr_val);
14347 +
14348 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
14349 + goto done;
14350 +
14351 + if (!(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL))
14352 + goto done;
14353 +
14354 + slowminfreq = sb_slowclk_freq(si, FALSE);
14355 + fpdelay = (((R_REG(si->osh, &cc->pll_on_delay) + 2) * 1000000) +
14356 + (slowminfreq - 1)) / slowminfreq;
14357 +
14358 +done:
14359 + sb_setcoreidx(sbh, origidx);
14360 + INTR_RESTORE(si, intr_val);
14361 + return (fpdelay);
14362 +}
14363 +
14364 +/* turn primary xtal and/or pll off/on */
14365 +int
14366 +sb_clkctl_xtal(sb_t *sbh, uint what, bool on)
14367 +{
14368 + sb_info_t *si;
14369 + uint32 in, out, outen;
14370 +
14371 + si = SB_INFO(sbh);
14372 +
14373 + switch (BUSTYPE(si->sb.bustype)) {
14374 +
14375 +
14376 + case PCMCIA_BUS:
14377 + return (0);
14378 +
14379 +
14380 + case PCI_BUS:
14381 +
14382 + /* pcie core doesn't have any mapping to control the xtal pu */
14383 + if (PCIE(si))
14384 + return -1;
14385 +
14386 + in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof(uint32));
14387 + out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof(uint32));
14388 + outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof(uint32));
14389 +
14390 + /*
14391 + * Avoid glitching the clock if GPRS is already using it.
14392 + * We can't actually read the state of the PLLPD so we infer it
14393 + * by the value of XTAL_PU which *is* readable via gpioin.
14394 + */
14395 + if (on && (in & PCI_CFG_GPIO_XTAL))
14396 + return (0);
14397 +
14398 + if (what & XTAL)
14399 + outen |= PCI_CFG_GPIO_XTAL;
14400 + if (what & PLL)
14401 + outen |= PCI_CFG_GPIO_PLL;
14402 +
14403 + if (on) {
14404 + /* turn primary xtal on */
14405 + if (what & XTAL) {
14406 + out |= PCI_CFG_GPIO_XTAL;
14407 + if (what & PLL)
14408 + out |= PCI_CFG_GPIO_PLL;
14409 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT,
14410 + sizeof(uint32), out);
14411 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN,
14412 + sizeof(uint32), outen);
14413 + OSL_DELAY(XTAL_ON_DELAY);
14414 + }
14415 +
14416 + /* turn pll on */
14417 + if (what & PLL) {
14418 + out &= ~PCI_CFG_GPIO_PLL;
14419 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT,
14420 + sizeof(uint32), out);
14421 + OSL_DELAY(2000);
14422 + }
14423 + } else {
14424 + if (what & XTAL)
14425 + out &= ~PCI_CFG_GPIO_XTAL;
14426 + if (what & PLL)
14427 + out |= PCI_CFG_GPIO_PLL;
14428 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof(uint32), out);
14429 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof(uint32),
14430 + outen);
14431 + }
14432 +
14433 + default:
14434 + return (-1);
14435 + }
14436 +
14437 + return (0);
14438 +}
14439 +
14440 +/* set dynamic clk control mode (forceslow, forcefast, dynamic) */
14441 +/* returns true if we are forcing fast clock */
14442 +bool
14443 +sb_clkctl_clk(sb_t *sbh, uint mode)
14444 +{
14445 + sb_info_t *si;
14446 + uint origidx;
14447 + chipcregs_t *cc;
14448 + uint32 scc;
14449 + uint intr_val = 0;
14450 +
14451 + si = SB_INFO(sbh);
14452 +
14453 + /* chipcommon cores prior to rev6 don't support dynamic clock control */
14454 + if (si->sb.ccrev < 6)
14455 + return (FALSE);
14456 +
14457 +
14458 + /* Chips with ccrev 10 are EOL and they don't have SYCC_HR which we use below */
14459 + ASSERT(si->sb.ccrev != 10);
14460 +
14461 + INTR_OFF(si, intr_val);
14462 +
14463 + origidx = si->curidx;
14464 +
14465 + if (sb_setcore(sbh, SB_MIPS33, 0) && (sb_corerev(&si->sb) <= 7) &&
14466 + (BUSTYPE(si->sb.bustype) == SB_BUS) && (si->sb.ccrev >= 10))
14467 + goto done;
14468 +
14469 + /* PR32414WAR "Force HT clock on" all the time, no dynamic clk ctl */
14470 + if ((si->sb.chip == BCM4311_CHIP_ID) && (si->sb.chiprev <= 1))
14471 + goto done;
14472 +
14473 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
14474 + ASSERT(cc != NULL);
14475 +
14476 + if (!(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL))
14477 + goto done;
14478 +
14479 + switch (mode) {
14480 + case CLK_FAST: /* force fast (pll) clock */
14481 + if (si->sb.ccrev < 10) {
14482 + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
14483 + sb_clkctl_xtal(&si->sb, XTAL, ON);
14484 +
14485 + SET_REG(si->osh, &cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
14486 + } else
14487 + OR_REG(si->osh, &cc->system_clk_ctl, SYCC_HR);
14488 + /* wait for the PLL */
14489 + OSL_DELAY(PLL_DELAY);
14490 + break;
14491 +
14492 + case CLK_DYNAMIC: /* enable dynamic clock control */
14493 +
14494 + if (si->sb.ccrev < 10) {
14495 + scc = R_REG(si->osh, &cc->slow_clk_ctl);
14496 + scc &= ~(SCC_FS | SCC_IP | SCC_XC);
14497 + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
14498 + scc |= SCC_XC;
14499 + W_REG(si->osh, &cc->slow_clk_ctl, scc);
14500 +
14501 + /* for dynamic control, we have to release our xtal_pu "force on" */
14502 + if (scc & SCC_XC)
14503 + sb_clkctl_xtal(&si->sb, XTAL, OFF);
14504 + } else {
14505 + /* Instaclock */
14506 + AND_REG(si->osh, &cc->system_clk_ctl, ~SYCC_HR);
14507 + }
14508 + break;
14509 +
14510 + default:
14511 + ASSERT(0);
14512 + }
14513 +
14514 +done:
14515 + sb_setcoreidx(sbh, origidx);
14516 + INTR_RESTORE(si, intr_val);
14517 + return (mode == CLK_FAST);
14518 +}
14519 +
14520 +/* register driver interrupt disabling and restoring callback functions */
14521 +void
14522 +sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn,
14523 + void *intrsenabled_fn, void *intr_arg)
14524 +{
14525 + sb_info_t *si;
14526 +
14527 + si = SB_INFO(sbh);
14528 + si->intr_arg = intr_arg;
14529 + si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
14530 + si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
14531 + si->intrsenabled_fn = (sb_intrsenabled_t)intrsenabled_fn;
14532 + /* save current core id. when this function called, the current core
14533 + * must be the core which provides driver functions(il, et, wl, etc.)
14534 + */
14535 + si->dev_coreid = si->coreid[si->curidx];
14536 +}
14537 +
14538 +
14539 +int
14540 +sb_corepciid(sb_t *sbh, uint func, uint16 *pcivendor, uint16 *pcidevice,
14541 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif,
14542 + uint8 *pciheader)
14543 +{
14544 + uint16 vendor = 0xffff, device = 0xffff;
14545 + uint core, unit;
14546 + uint chip, chippkg;
14547 + uint nfunc;
14548 + char varname[SB_DEVPATH_BUFSZ + 8];
14549 + uint8 class, subclass, progif;
14550 + char devpath[SB_DEVPATH_BUFSZ];
14551 + uint8 header;
14552 +
14553 + core = sb_coreid(sbh);
14554 + unit = sb_coreunit(sbh);
14555 +
14556 + chip = sb_chip(sbh);
14557 + chippkg = sb_chippkg(sbh);
14558 +
14559 + progif = 0;
14560 + header = PCI_HEADER_NORMAL;
14561 +
14562 + /* Verify whether the function exists for the core */
14563 + nfunc = (core == SB_USB20H) ? 2 : 1;
14564 + if (func >= nfunc)
14565 + return BCME_ERROR;
14566 +
14567 + /* Known vendor translations */
14568 + switch (sb_corevendor(sbh)) {
14569 + case SB_VEND_BCM:
14570 + vendor = VENDOR_BROADCOM;
14571 + break;
14572 + default:
14573 + return BCME_ERROR;
14574 + }
14575 +
14576 + /* Determine class based on known core codes */
14577 + switch (core) {
14578 + case SB_ILINE20:
14579 + class = PCI_CLASS_NET;
14580 + subclass = PCI_NET_ETHER;
14581 + device = BCM47XX_ILINE_ID;
14582 + break;
14583 + case SB_ENET:
14584 + class = PCI_CLASS_NET;
14585 + subclass = PCI_NET_ETHER;
14586 + device = BCM47XX_ENET_ID;
14587 + break;
14588 + case SB_GIGETH:
14589 + class = PCI_CLASS_NET;
14590 + subclass = PCI_NET_ETHER;
14591 + device = BCM47XX_GIGETH_ID;
14592 + break;
14593 + case SB_SDRAM:
14594 + case SB_MEMC:
14595 + class = PCI_CLASS_MEMORY;
14596 + subclass = PCI_MEMORY_RAM;
14597 + device = (uint16)core;
14598 + break;
14599 + case SB_PCI:
14600 + case SB_PCIE:
14601 + class = PCI_CLASS_BRIDGE;
14602 + subclass = PCI_BRIDGE_PCI;
14603 + device = (uint16)core;
14604 + header = PCI_HEADER_BRIDGE;
14605 + break;
14606 + case SB_MIPS:
14607 + case SB_MIPS33:
14608 + class = PCI_CLASS_CPU;
14609 + subclass = PCI_CPU_MIPS;
14610 + device = (uint16)core;
14611 + break;
14612 + case SB_CODEC:
14613 + class = PCI_CLASS_COMM;
14614 + subclass = PCI_COMM_MODEM;
14615 + device = BCM47XX_V90_ID;
14616 + break;
14617 + case SB_USB:
14618 + class = PCI_CLASS_SERIAL;
14619 + subclass = PCI_SERIAL_USB;
14620 + progif = 0x10; /* OHCI */
14621 + device = BCM47XX_USB_ID;
14622 + break;
14623 + case SB_USB11H:
14624 + class = PCI_CLASS_SERIAL;
14625 + subclass = PCI_SERIAL_USB;
14626 + progif = 0x10; /* OHCI */
14627 + device = BCM47XX_USBH_ID;
14628 + break;
14629 + case SB_USB20H:
14630 + class = PCI_CLASS_SERIAL;
14631 + subclass = PCI_SERIAL_USB;
14632 + progif = func == 0 ? 0x10 : 0x20; /* OHCI/EHCI */
14633 + device = BCM47XX_USB20H_ID;
14634 + header = 0x80; /* multifunction */
14635 + break;
14636 + case SB_USB11D:
14637 + class = PCI_CLASS_SERIAL;
14638 + subclass = PCI_SERIAL_USB;
14639 + device = BCM47XX_USBD_ID;
14640 + break;
14641 + case SB_USB20D:
14642 + class = PCI_CLASS_SERIAL;
14643 + subclass = PCI_SERIAL_USB;
14644 + device = BCM47XX_USB20D_ID;
14645 + break;
14646 + case SB_IPSEC:
14647 + class = PCI_CLASS_CRYPT;
14648 + subclass = PCI_CRYPT_NETWORK;
14649 + device = BCM47XX_IPSEC_ID;
14650 + break;
14651 + case SB_ROBO:
14652 + class = PCI_CLASS_NET;
14653 + subclass = PCI_NET_OTHER;
14654 + device = BCM47XX_ROBO_ID;
14655 + break;
14656 + case SB_EXTIF:
14657 + case SB_CC:
14658 + class = PCI_CLASS_MEMORY;
14659 + subclass = PCI_MEMORY_FLASH;
14660 + device = (uint16)core;
14661 + break;
14662 + case SB_D11:
14663 + class = PCI_CLASS_NET;
14664 + subclass = PCI_NET_OTHER;
14665 + /* Let nvram variable override core ID */
14666 + sb_devpath(sbh, devpath, sizeof(devpath));
14667 + sprintf(varname, "%sdevid", devpath);
14668 + if ((device = (uint16)getintvar(NULL, varname)))
14669 + break;
14670 + /*
14671 + * no longer support wl%did, but keep the code
14672 + * here for backward compatibility.
14673 + */
14674 + sprintf(varname, "wl%did", unit);
14675 + if ((device = (uint16)getintvar(NULL, varname)))
14676 + break;
14677 + /* Chip specific conversion */
14678 + if (chip == BCM4712_CHIP_ID) {
14679 + if (chippkg == BCM4712SMALL_PKG_ID)
14680 + device = BCM4306_D11G_ID;
14681 + else
14682 + device = BCM4306_D11DUAL_ID;
14683 + break;
14684 + }
14685 + /* ignore it */
14686 + device = 0xffff;
14687 + break;
14688 + case SB_SATAXOR:
14689 + class = PCI_CLASS_XOR;
14690 + subclass = PCI_XOR_QDMA;
14691 + device = BCM47XX_SATAXOR_ID;
14692 + break;
14693 + case SB_ATA100:
14694 + class = PCI_CLASS_DASDI;
14695 + subclass = PCI_DASDI_IDE;
14696 + device = BCM47XX_ATA100_ID;
14697 + break;
14698 +
14699 + default:
14700 + class = subclass = progif = 0xff;
14701 + device = (uint16)core;
14702 + break;
14703 + }
14704 +
14705 + *pcivendor = vendor;
14706 + *pcidevice = device;
14707 + *pciclass = class;
14708 + *pcisubclass = subclass;
14709 + *pciprogif = progif;
14710 + *pciheader = header;
14711 +
14712 + return 0;
14713 +}
14714 +
14715 +
14716 +
14717 +/* use the mdio interface to write to mdio slaves */
14718 +static int
14719 +sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint regaddr, uint val)
14720 +{
14721 + uint mdiodata;
14722 + uint i = 0;
14723 + sbpcieregs_t *pcieregs;
14724 +
14725 + pcieregs = (sbpcieregs_t*) sb_setcoreidx(&si->sb, si->sb.buscoreidx);
14726 + ASSERT(pcieregs);
14727 +
14728 + /* enable mdio access to SERDES */
14729 + W_REG(si->osh, (&pcieregs->mdiocontrol), MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
14730 +
14731 + mdiodata = MDIODATA_START | MDIODATA_WRITE |
14732 + (physmedia << MDIODATA_DEVADDR_SHF) |
14733 + (regaddr << MDIODATA_REGADDR_SHF) | MDIODATA_TA | val;
14734 +
14735 + W_REG(si->osh, (&pcieregs->mdiodata), mdiodata);
14736 +
14737 + PR28829_DELAY();
14738 +
14739 + /* retry till the transaction is complete */
14740 + while (i < 10) {
14741 + if (R_REG(si->osh, &(pcieregs->mdiocontrol)) & MDIOCTL_ACCESS_DONE) {
14742 + /* Disable mdio access to SERDES */
14743 + W_REG(si->osh, (&pcieregs->mdiocontrol), 0);
14744 + return 0;
14745 + }
14746 + OSL_DELAY(1000);
14747 + i++;
14748 + }
14749 +
14750 + SB_ERROR(("sb_pcie_mdiowrite: timed out\n"));
14751 + /* Disable mdio access to SERDES */
14752 + W_REG(si->osh, (&pcieregs->mdiocontrol), 0);
14753 + ASSERT(0);
14754 + return 1;
14755 +
14756 +}
14757 +
14758 +/* indirect way to read pcie config regs */
14759 +uint
14760 +sb_pcie_readreg(void *sb, void* arg1, uint offset)
14761 +{
14762 + sb_info_t *si;
14763 + sb_t *sbh;
14764 + uint retval = 0xFFFFFFFF;
14765 + sbpcieregs_t *pcieregs;
14766 + uint addrtype;
14767 +
14768 + sbh = (sb_t *)sb;
14769 + si = SB_INFO(sbh);
14770 + ASSERT(PCIE(si));
14771 +
14772 + pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
14773 + ASSERT(pcieregs);
14774 +
14775 + addrtype = (uint)((uintptr)arg1);
14776 + switch (addrtype) {
14777 + case PCIE_CONFIGREGS:
14778 + W_REG(si->osh, (&pcieregs->configaddr), offset);
14779 + retval = R_REG(si->osh, &(pcieregs->configdata));
14780 + break;
14781 + case PCIE_PCIEREGS:
14782 + W_REG(si->osh, &(pcieregs->pcieaddr), offset);
14783 + retval = R_REG(si->osh, &(pcieregs->pciedata));
14784 + break;
14785 + default:
14786 + ASSERT(0);
14787 + break;
14788 + }
14789 + return retval;
14790 +}
14791 +
14792 +/* indirect way to write pcie config/mdio/pciecore regs */
14793 +uint
14794 +sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val)
14795 +{
14796 + sb_info_t *si;
14797 + sbpcieregs_t *pcieregs;
14798 + uint addrtype;
14799 +
14800 + si = SB_INFO(sbh);
14801 + ASSERT(PCIE(si));
14802 +
14803 + pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
14804 + ASSERT(pcieregs);
14805 +
14806 + addrtype = (uint)((uintptr)arg1);
14807 +
14808 + switch (addrtype) {
14809 + case PCIE_CONFIGREGS:
14810 + W_REG(si->osh, (&pcieregs->configaddr), offset);
14811 + W_REG(si->osh, (&pcieregs->configdata), val);
14812 + break;
14813 + case PCIE_PCIEREGS:
14814 + W_REG(si->osh, (&pcieregs->pcieaddr), offset);
14815 + W_REG(si->osh, (&pcieregs->pciedata), val);
14816 + break;
14817 + default:
14818 + ASSERT(0);
14819 + break;
14820 + }
14821 + return 0;
14822 +}
14823 +
14824 +/* Build device path. Support SB, PCI, and JTAG for now. */
14825 +int
14826 +sb_devpath(sb_t *sbh, char *path, int size)
14827 +{
14828 + ASSERT(path);
14829 + ASSERT(size >= SB_DEVPATH_BUFSZ);
14830 +
14831 + switch (BUSTYPE((SB_INFO(sbh))->sb.bustype)) {
14832 + case SB_BUS:
14833 + case JTAG_BUS:
14834 + sprintf(path, "sb/%u/", sb_coreidx(sbh));
14835 + break;
14836 + case PCI_BUS:
14837 + ASSERT((SB_INFO(sbh))->osh);
14838 + sprintf(path, "pci/%u/%u/", OSL_PCI_BUS((SB_INFO(sbh))->osh),
14839 + OSL_PCI_SLOT((SB_INFO(sbh))->osh));
14840 + break;
14841 + case PCMCIA_BUS:
14842 + SB_ERROR(("sb_devpath: OSL_PCMCIA_BUS() not implemented, bus 1 assumed\n"));
14843 + SB_ERROR(("sb_devpath: OSL_PCMCIA_SLOT() not implemented, slot 1 assumed\n"));
14844 + sprintf(path, "pc/%u/%u/", 1, 1);
14845 + break;
14846 + case SDIO_BUS:
14847 + SB_ERROR(("sb_devpath: device 0 assumed\n"));
14848 + sprintf(path, "sd/%u/", sb_coreidx(sbh));
14849 + break;
14850 + default:
14851 + ASSERT(0);
14852 + break;
14853 + }
14854 +
14855 + return 0;
14856 +}
14857 +
14858 +/*
14859 + * Fixup SROMless PCI device's configuration.
14860 + * The current core may be changed upon return.
14861 + */
14862 +static int
14863 +sb_pci_fixcfg(sb_info_t *si)
14864 +{
14865 + uint origidx, pciidx;
14866 + sbpciregs_t *pciregs;
14867 + sbpcieregs_t *pcieregs;
14868 + uint16 val16, *reg16;
14869 + char name[SB_DEVPATH_BUFSZ+16], *value;
14870 + char devpath[SB_DEVPATH_BUFSZ];
14871 +
14872 + ASSERT(BUSTYPE(si->sb.bustype) == PCI_BUS);
14873 +
14874 + /* Fixup PI in SROM shadow area to enable the correct PCI core access */
14875 + /* save the current index */
14876 + origidx = sb_coreidx(&si->sb);
14877 +
14878 + /* check 'pi' is correct and fix it if not */
14879 + if (si->sb.buscoretype == SB_PCIE) {
14880 + pcieregs = (sbpcieregs_t *)sb_setcore(&si->sb, SB_PCIE, 0);
14881 + ASSERT(pcieregs);
14882 + reg16 = &pcieregs->sprom[SRSH_PI_OFFSET];
14883 + } else if (si->sb.buscoretype == SB_PCI) {
14884 + pciregs = (sbpciregs_t *)sb_setcore(&si->sb, SB_PCI, 0);
14885 + ASSERT(pciregs);
14886 + reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
14887 + } else {
14888 + ASSERT(0);
14889 + return -1;
14890 + }
14891 + pciidx = sb_coreidx(&si->sb);
14892 + val16 = R_REG(si->osh, reg16);
14893 + if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (uint16)pciidx) {
14894 + val16 = (uint16)(pciidx << SRSH_PI_SHIFT) | (val16 & ~SRSH_PI_MASK);
14895 + W_REG(si->osh, reg16, val16);
14896 + }
14897 +
14898 + /* restore the original index */
14899 + sb_setcoreidx(&si->sb, origidx);
14900 +
14901 + /*
14902 + * Fixup bar0window in PCI config space to make the core indicated
14903 + * by the nvram variable the current core.
14904 + * !Do it last, it may change the current core!
14905 + */
14906 + if (sb_devpath(&si->sb, devpath, sizeof(devpath)))
14907 + return -1;
14908 + sprintf(name, "%sb0w", devpath);
14909 + if ((value = getvar(NULL, name))) {
14910 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32),
14911 + bcm_strtoul(value, NULL, 16));
14912 + /* update curidx since the current core is changed */
14913 + si->curidx = _sb_coreidx(si);
14914 + if (si->curidx == BADIDX) {
14915 + SB_ERROR(("sb_pci_fixcfg: bad core index\n"));
14916 + return -1;
14917 + }
14918 + }
14919 +
14920 + return 0;
14921 +}
14922 +
14923 +static uint
14924 +sb_chipc_capability(sb_t *sbh)
14925 +{
14926 + sb_info_t *si;
14927 +
14928 + si = SB_INFO(sbh);
14929 +
14930 + /* Make sure that there is ChipCommon core present */
14931 + if (si->coreid[SB_CC_IDX] == SB_CC)
14932 + return (sb_corereg(si, SB_CC_IDX, OFFSETOF(chipcregs_t, capabilities),
14933 + 0, 0));
14934 + return 0;
14935 +}
14936 +
14937 +/* Return ADDR64 capability of the backplane */
14938 +bool
14939 +sb_backplane64(sb_t *sbh)
14940 +{
14941 + return ((sb_chipc_capability(sbh) & CAP_BKPLN64) != 0);
14942 +}
14943 +
14944 +void
14945 +sb_btcgpiowar(sb_t *sbh)
14946 +{
14947 + sb_info_t *si;
14948 + uint origidx;
14949 + uint intr_val = 0;
14950 + chipcregs_t *cc;
14951 + si = SB_INFO(sbh);
14952 +
14953 + /* Make sure that there is ChipCommon core present &&
14954 + * UART_TX is strapped to 1
14955 + */
14956 + if (!(sb_chipc_capability(sbh) & CAP_UARTGPIO))
14957 + return;
14958 +
14959 + /* sb_corereg cannot be used as we have to guarantee 8-bit read/writes */
14960 + INTR_OFF(si, intr_val);
14961 +
14962 + origidx = sb_coreidx(sbh);
14963 +
14964 + cc = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
14965 + if (cc == NULL)
14966 + goto end;
14967 +
14968 + W_REG(si->osh, &cc->uart0mcr, R_REG(si->osh, &cc->uart0mcr) | 0x04);
14969 +
14970 +end:
14971 + /* restore the original index */
14972 + sb_setcoreidx(sbh, origidx);
14973 +
14974 + INTR_RESTORE(si, intr_val);
14975 +}
14976 +
14977 +/* check if the device is removed */
14978 +bool
14979 +sb_deviceremoved(sb_t *sbh)
14980 +{
14981 + uint32 w;
14982 + sb_info_t *si;
14983 +
14984 + si = SB_INFO(sbh);
14985 +
14986 + switch (BUSTYPE(si->sb.bustype)) {
14987 + case PCI_BUS:
14988 + ASSERT(si->osh);
14989 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_VID, sizeof(uint32));
14990 + if ((w & 0xFFFF) != VENDOR_BROADCOM)
14991 + return TRUE;
14992 + else
14993 + return FALSE;
14994 + default:
14995 + return FALSE;
14996 + }
14997 + return FALSE;
14998 +}
14999 +
15000 +/* Return the RAM size of the SOCRAM core */
15001 +uint32
15002 +sb_socram_size(sb_t *sbh)
15003 +{
15004 + sb_info_t *si;
15005 + uint origidx;
15006 + uint intr_val = 0;
15007 +
15008 + sbsocramregs_t *regs;
15009 + bool wasup;
15010 + uint corerev;
15011 + uint32 coreinfo;
15012 + uint memsize = 0;
15013 +
15014 + si = SB_INFO(sbh);
15015 + ASSERT(si);
15016 +
15017 + /* Block ints and save current core */
15018 + INTR_OFF(si, intr_val);
15019 + origidx = sb_coreidx(sbh);
15020 +
15021 + /* Switch to SOCRAM core */
15022 + if (!(regs = sb_setcore(sbh, SB_SOCRAM, 0)))
15023 + goto done;
15024 +
15025 + /* Get info for determining size */
15026 + if (!(wasup = sb_iscoreup(sbh)))
15027 + sb_core_reset(sbh, 0, 0);
15028 + corerev = sb_corerev(sbh);
15029 + coreinfo = R_REG(si->osh, &regs->coreinfo);
15030 +
15031 + /* Calculate size from coreinfo based on rev */
15032 + switch (corerev) {
15033 + case 0:
15034 + memsize = 1 << (16 + (coreinfo & SRCI_MS0_MASK));
15035 + break;
15036 + default: /* rev >= 1 */
15037 + memsize = 1 << (SR_BSZ_BASE + (coreinfo & SRCI_SRBSZ_MASK));
15038 + memsize *= (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
15039 + break;
15040 + }
15041 +
15042 + /* Return to previous state and core */
15043 + if (!wasup)
15044 + sb_core_disable(sbh, 0);
15045 + sb_setcoreidx(sbh, origidx);
15046 +
15047 +done:
15048 + INTR_RESTORE(si, intr_val);
15049 + return memsize;
15050 +}
15051 +
15052 +
15053 diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setup.c
15054 --- linux.old/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
15055 +++ linux.dev/arch/mips/bcm947xx/setup.c 2006-10-02 21:19:59.000000000 +0200
15056 @@ -0,0 +1,241 @@
15057 +/*
15058 + * Generic setup routines for Broadcom MIPS boards
15059 + *
15060 + * Copyright (C) 2005 Felix Fietkau <nbd@openwrt.org>
15061 + *
15062 + * This program is free software; you can redistribute it and/or modify it
15063 + * under the terms of the GNU General Public License as published by the
15064 + * Free Software Foundation; either version 2 of the License, or (at your
15065 + * option) any later version.
15066 + *
15067 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15068 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15069 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15070 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15071 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15072 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
15073 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
15074 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
15075 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
15076 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15077 + *
15078 + * You should have received a copy of the GNU General Public License along
15079 + * with this program; if not, write to the Free Software Foundation, Inc.,
15080 + * 675 Mass Ave, Cambridge, MA 02139, USA.
15081 + *
15082 + *
15083 + * Copyright 2005, Broadcom Corporation
15084 + * All Rights Reserved.
15085 + *
15086 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15087 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15088 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15089 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15090 + *
15091 + */
15092 +
15093 +#include <linux/config.h>
15094 +#include <linux/init.h>
15095 +#include <linux/kernel.h>
15096 +#include <linux/module.h>
15097 +#include <linux/serialP.h>
15098 +#include <linux/ide.h>
15099 +#include <asm/bootinfo.h>
15100 +#include <asm/cpu.h>
15101 +#include <asm/time.h>
15102 +#include <asm/reboot.h>
15103 +
15104 +#include <typedefs.h>
15105 +#include <osl.h>
15106 +#include <sbutils.h>
15107 +#include <bcmutils.h>
15108 +#include <bcmnvram.h>
15109 +#include <sbhndmips.h>
15110 +#include <hndmips.h>
15111 +#include <trxhdr.h>
15112 +
15113 +/* Virtual IRQ base, after last hw IRQ */
15114 +#define SBMIPS_VIRTIRQ_BASE 6
15115 +
15116 +/* # IRQs, hw and sw IRQs */
15117 +#define SBMIPS_NUMIRQS 8
15118 +
15119 +/* Global SB handle */
15120 +sb_t *bcm947xx_sbh = NULL;
15121 +spinlock_t bcm947xx_sbh_lock = SPIN_LOCK_UNLOCKED;
15122 +
15123 +/* Convenience */
15124 +#define sbh bcm947xx_sbh
15125 +#define sbh_lock bcm947xx_sbh_lock
15126 +
15127 +extern void bcm947xx_time_init(void);
15128 +extern void bcm947xx_timer_setup(struct irqaction *irq);
15129 +
15130 +#ifdef CONFIG_REMOTE_DEBUG
15131 +extern void set_debug_traps(void);
15132 +extern void rs_kgdb_hook(struct serial_state *);
15133 +extern void breakpoint(void);
15134 +#endif
15135 +
15136 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
15137 +extern struct ide_ops std_ide_ops;
15138 +#endif
15139 +
15140 +/* Kernel command line */
15141 +char arcs_cmdline[CL_SIZE] __initdata = CONFIG_CMDLINE;
15142 +extern void sb_serial_init(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
15143 +
15144 +void
15145 +bcm947xx_machine_restart(char *command)
15146 +{
15147 + printk("Please stand by while rebooting the system...\n");
15148 +
15149 + /* Set the watchdog timer to reset immediately */
15150 + __cli();
15151 + sb_watchdog(sbh, 1);
15152 + while (1);
15153 +}
15154 +
15155 +void
15156 +bcm947xx_machine_halt(void)
15157 +{
15158 + printk("System halted\n");
15159 +
15160 + /* Disable interrupts and watchdog and spin forever */
15161 + __cli();
15162 + sb_watchdog(sbh, 0);
15163 + while (1);
15164 +}
15165 +
15166 +#ifdef CONFIG_SERIAL
15167 +
15168 +static int ser_line = 0;
15169 +
15170 +typedef struct {
15171 + void *regs;
15172 + uint irq;
15173 + uint baud_base;
15174 + uint reg_shift;
15175 +} serial_port;
15176 +
15177 +static serial_port ports[4];
15178 +static int num_ports = 0;
15179 +
15180 +static void
15181 +serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
15182 +{
15183 + ports[num_ports].regs = regs;
15184 + ports[num_ports].irq = irq;
15185 + ports[num_ports].baud_base = baud_base;
15186 + ports[num_ports].reg_shift = reg_shift;
15187 + num_ports++;
15188 +}
15189 +
15190 +static void
15191 +do_serial_add(serial_port *port)
15192 +{
15193 + void *regs;
15194 + uint irq;
15195 + uint baud_base;
15196 + uint reg_shift;
15197 + struct serial_struct s;
15198 +
15199 + regs = port->regs;
15200 + irq = port->irq;
15201 + baud_base = port->baud_base;
15202 + reg_shift = port->reg_shift;
15203 +
15204 + memset(&s, 0, sizeof(s));
15205 +
15206 + s.line = ser_line++;
15207 + s.iomem_base = regs;
15208 + s.irq = irq + 2;
15209 + s.baud_base = baud_base / 16;
15210 + s.flags = ASYNC_BOOT_AUTOCONF;
15211 + s.io_type = SERIAL_IO_MEM;
15212 + s.iomem_reg_shift = reg_shift;
15213 +
15214 + if (early_serial_setup(&s) != 0) {
15215 + printk(KERN_ERR "Serial setup failed!\n");
15216 + }
15217 +}
15218 +
15219 +#endif /* CONFIG_SERIAL */
15220 +
15221 +void __init
15222 +brcm_setup(void)
15223 +{
15224 + char *s;
15225 + int i;
15226 + char *value;
15227 +
15228 + /* Get global SB handle */
15229 + sbh = sb_kattach();
15230 +
15231 + /* Initialize clocks and interrupts */
15232 + sb_mips_init(sbh, SBMIPS_VIRTIRQ_BASE);
15233 +
15234 + if (BCM330X(current_cpu_data.processor_id) &&
15235 + (read_c0_diag() & BRCM_PFC_AVAIL)) {
15236 + /*
15237 + * Now that the sbh is inited set the proper PFC value
15238 + */
15239 + printk("Setting the PFC to its default value\n");
15240 + enable_pfc(PFC_AUTO);
15241 + }
15242 +
15243 +
15244 +#ifdef CONFIG_SERIAL
15245 + sb_serial_init(sbh, serial_add);
15246 +
15247 + /* reverse serial ports if nvram variable starts with console=ttyS1 */
15248 + /* Initialize UARTs */
15249 + s = nvram_get("kernel_args");
15250 + if (!s) s = "";
15251 + if (!strncmp(s, "console=ttyS1", 13)) {
15252 + for (i = num_ports; i; i--)
15253 + do_serial_add(&ports[i - 1]);
15254 + } else {
15255 + for (i = 0; i < num_ports; i++)
15256 + do_serial_add(&ports[i]);
15257 + }
15258 +#endif
15259 +
15260 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
15261 + ide_ops = &std_ide_ops;
15262 +#endif
15263 +
15264 + /* Override default command line arguments */
15265 + value = nvram_get("kernel_cmdline");
15266 + if (value && strlen(value) && strncmp(value, "empty", 5))
15267 + strncpy(arcs_cmdline, value, sizeof(arcs_cmdline));
15268 +
15269 +
15270 + /* Generic setup */
15271 + _machine_restart = bcm947xx_machine_restart;
15272 + _machine_halt = bcm947xx_machine_halt;
15273 + _machine_power_off = bcm947xx_machine_halt;
15274 +
15275 + board_time_init = bcm947xx_time_init;
15276 + board_timer_setup = bcm947xx_timer_setup;
15277 +}
15278 +
15279 +const char *
15280 +get_system_type(void)
15281 +{
15282 + static char s[32];
15283 +
15284 + if (bcm947xx_sbh) {
15285 + sprintf(s, "Broadcom BCM%X chip rev %d", sb_chip(bcm947xx_sbh),
15286 + sb_chiprev(bcm947xx_sbh));
15287 + return s;
15288 + }
15289 + else
15290 + return "Broadcom BCM947XX";
15291 +}
15292 +
15293 +void __init
15294 +bus_error_init(void)
15295 +{
15296 +}
15297 +
15298 diff -urN linux.old/arch/mips/bcm947xx/sflash.c linux.dev/arch/mips/bcm947xx/sflash.c
15299 --- linux.old/arch/mips/bcm947xx/sflash.c 1970-01-01 01:00:00.000000000 +0100
15300 +++ linux.dev/arch/mips/bcm947xx/sflash.c 2006-10-02 21:19:59.000000000 +0200
15301 @@ -0,0 +1,422 @@
15302 +/*
15303 + * Broadcom SiliconBackplane chipcommon serial flash interface
15304 + *
15305 + * Copyright 2006, Broadcom Corporation
15306 + * All Rights Reserved.
15307 + *
15308 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15309 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15310 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15311 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15312 + *
15313 + * $Id: sflash.c,v 1.1.1.13 2006/02/27 03:43:16 honor Exp $
15314 + */
15315 +
15316 +#include <osl.h>
15317 +#include <typedefs.h>
15318 +#include <sbconfig.h>
15319 +#include <sbchipc.h>
15320 +#include <mipsinc.h>
15321 +#include <bcmutils.h>
15322 +#include <bcmdevs.h>
15323 +#include <sflash.h>
15324 +
15325 +/* Private global state */
15326 +static struct sflash sflash;
15327 +
15328 +/* Issue a serial flash command */
15329 +static INLINE void
15330 +sflash_cmd(chipcregs_t *cc, uint opcode)
15331 +{
15332 + W_REG(NULL, &cc->flashcontrol, SFLASH_START | opcode);
15333 + while (R_REG(NULL, &cc->flashcontrol) & SFLASH_BUSY);
15334 +}
15335 +
15336 +/* Initialize serial flash access */
15337 +struct sflash *
15338 +sflash_init(chipcregs_t *cc)
15339 +{
15340 + uint32 id, id2;
15341 +
15342 + bzero(&sflash, sizeof(sflash));
15343 +
15344 + sflash.type = R_REG(NULL, &cc->capabilities) & CAP_FLASH_MASK;
15345 +
15346 + switch (sflash.type) {
15347 + case SFLASH_ST:
15348 + /* Probe for ST chips */
15349 + sflash_cmd(cc, SFLASH_ST_DP);
15350 + sflash_cmd(cc, SFLASH_ST_RES);
15351 + id = R_REG(NULL, &cc->flashdata);
15352 + switch (id) {
15353 + case 0x11:
15354 + /* ST M25P20 2 Mbit Serial Flash */
15355 + sflash.blocksize = 64 * 1024;
15356 + sflash.numblocks = 4;
15357 + break;
15358 + case 0x12:
15359 + /* ST M25P40 4 Mbit Serial Flash */
15360 + sflash.blocksize = 64 * 1024;
15361 + sflash.numblocks = 8;
15362 + break;
15363 + case 0x13:
15364 + /* ST M25P80 8 Mbit Serial Flash */
15365 + sflash.blocksize = 64 * 1024;
15366 + sflash.numblocks = 16;
15367 + break;
15368 + case 0x14:
15369 + /* ST M25P16 16 Mbit Serial Flash */
15370 + sflash.blocksize = 64 * 1024;
15371 + sflash.numblocks = 32;
15372 + break;
15373 + case 0x15:
15374 + /* ST M25P32 32 Mbit Serial Flash */
15375 + sflash.blocksize = 64 * 1024;
15376 + sflash.numblocks = 64;
15377 + break;
15378 + case 0x16:
15379 + /* ST M25P64 64 Mbit Serial Flash */
15380 + sflash.blocksize = 64 * 1024;
15381 + sflash.numblocks = 128;
15382 + break;
15383 + case 0xbf:
15384 + W_REG(NULL, &cc->flashaddress, 1);
15385 + sflash_cmd(cc, SFLASH_ST_RES);
15386 + id2 = R_REG(NULL, &cc->flashdata);
15387 + if (id2 == 0x44) {
15388 + /* SST M25VF80 4 Mbit Serial Flash */
15389 + sflash.blocksize = 64 * 1024;
15390 + sflash.numblocks = 8;
15391 + }
15392 + break;
15393 + }
15394 + break;
15395 +
15396 + case SFLASH_AT:
15397 + /* Probe for Atmel chips */
15398 + sflash_cmd(cc, SFLASH_AT_STATUS);
15399 + id = R_REG(NULL, &cc->flashdata) & 0x3c;
15400 + switch (id) {
15401 + case 0xc:
15402 + /* Atmel AT45DB011 1Mbit Serial Flash */
15403 + sflash.blocksize = 256;
15404 + sflash.numblocks = 512;
15405 + break;
15406 + case 0x14:
15407 + /* Atmel AT45DB021 2Mbit Serial Flash */
15408 + sflash.blocksize = 256;
15409 + sflash.numblocks = 1024;
15410 + break;
15411 + case 0x1c:
15412 + /* Atmel AT45DB041 4Mbit Serial Flash */
15413 + sflash.blocksize = 256;
15414 + sflash.numblocks = 2048;
15415 + break;
15416 + case 0x24:
15417 + /* Atmel AT45DB081 8Mbit Serial Flash */
15418 + sflash.blocksize = 256;
15419 + sflash.numblocks = 4096;
15420 + break;
15421 + case 0x2c:
15422 + /* Atmel AT45DB161 16Mbit Serial Flash */
15423 + sflash.blocksize = 512;
15424 + sflash.numblocks = 4096;
15425 + break;
15426 + case 0x34:
15427 + /* Atmel AT45DB321 32Mbit Serial Flash */
15428 + sflash.blocksize = 512;
15429 + sflash.numblocks = 8192;
15430 + break;
15431 + case 0x3c:
15432 + /* Atmel AT45DB642 64Mbit Serial Flash */
15433 + sflash.blocksize = 1024;
15434 + sflash.numblocks = 8192;
15435 + break;
15436 + }
15437 + break;
15438 + }
15439 +
15440 + sflash.size = sflash.blocksize * sflash.numblocks;
15441 + return sflash.size ? &sflash : NULL;
15442 +}
15443 +
15444 +/* Read len bytes starting at offset into buf. Returns number of bytes read. */
15445 +int
15446 +sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf)
15447 +{
15448 + int cnt;
15449 + uint32 *from, *to;
15450 +
15451 + if (!len)
15452 + return 0;
15453 +
15454 + if ((offset + len) > sflash.size)
15455 + return -22;
15456 +
15457 + if ((len >= 4) && (offset & 3))
15458 + cnt = 4 - (offset & 3);
15459 + else if ((len >= 4) && ((uint32)buf & 3))
15460 + cnt = 4 - ((uint32)buf & 3);
15461 + else
15462 + cnt = len;
15463 +
15464 + from = (uint32 *)KSEG1ADDR(SB_FLASH2 + offset);
15465 + to = (uint32 *)buf;
15466 +
15467 + if (cnt < 4) {
15468 + bcopy(from, to, cnt);
15469 + return cnt;
15470 + }
15471 +
15472 + while (cnt >= 4) {
15473 + *to++ = *from++;
15474 + cnt -= 4;
15475 + }
15476 +
15477 + return (len - cnt);
15478 +}
15479 +
15480 +/* Poll for command completion. Returns zero when complete. */
15481 +int
15482 +sflash_poll(chipcregs_t *cc, uint offset)
15483 +{
15484 + if (offset >= sflash.size)
15485 + return -22;
15486 +
15487 + switch (sflash.type) {
15488 + case SFLASH_ST:
15489 + /* Check for ST Write In Progress bit */
15490 + sflash_cmd(cc, SFLASH_ST_RDSR);
15491 + return R_REG(NULL, &cc->flashdata) & SFLASH_ST_WIP;
15492 + case SFLASH_AT:
15493 + /* Check for Atmel Ready bit */
15494 + sflash_cmd(cc, SFLASH_AT_STATUS);
15495 + return !(R_REG(NULL, &cc->flashdata) & SFLASH_AT_READY);
15496 + }
15497 +
15498 + return 0;
15499 +}
15500 +
15501 +/* Write len bytes starting at offset into buf. Returns number of bytes
15502 + * written. Caller should poll for completion.
15503 + */
15504 +int
15505 +sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
15506 +{
15507 + struct sflash *sfl;
15508 + int ret = 0;
15509 + bool is4712b0;
15510 + uint32 page, byte, mask;
15511 +
15512 + if (!len)
15513 + return 0;
15514 +
15515 + if ((offset + len) > sflash.size)
15516 + return -22;
15517 +
15518 + sfl = &sflash;
15519 + switch (sfl->type) {
15520 + case SFLASH_ST:
15521 + mask = R_REG(NULL, &cc->chipid);
15522 + is4712b0 = (((mask & CID_ID_MASK) == BCM4712_CHIP_ID) &&
15523 + ((mask & CID_REV_MASK) == (3 << CID_REV_SHIFT)));
15524 + /* Enable writes */
15525 + sflash_cmd(cc, SFLASH_ST_WREN);
15526 + if (is4712b0) {
15527 + mask = 1 << 14;
15528 + W_REG(NULL, &cc->flashaddress, offset);
15529 + W_REG(NULL, &cc->flashdata, *buf++);
15530 + /* Set chip select */
15531 + OR_REG(NULL, &cc->gpioout, mask);
15532 + /* Issue a page program with the first byte */
15533 + sflash_cmd(cc, SFLASH_ST_PP);
15534 + ret = 1;
15535 + offset++;
15536 + len--;
15537 + while (len > 0) {
15538 + if ((offset & 255) == 0) {
15539 + /* Page boundary, drop cs and return */
15540 + AND_REG(NULL, &cc->gpioout, ~mask);
15541 + if (!sflash_poll(cc, offset)) {
15542 + /* Flash rejected command */
15543 + return -11;
15544 + }
15545 + return ret;
15546 + } else {
15547 + /* Write single byte */
15548 + sflash_cmd(cc, *buf++);
15549 + }
15550 + ret++;
15551 + offset++;
15552 + len--;
15553 + }
15554 + /* All done, drop cs if needed */
15555 + if ((offset & 255) != 1) {
15556 + /* Drop cs */
15557 + AND_REG(NULL, &cc->gpioout, ~mask);
15558 + if (!sflash_poll(cc, offset)) {
15559 + /* Flash rejected command */
15560 + return -12;
15561 + }
15562 + }
15563 + } else {
15564 + ret = 1;
15565 + W_REG(NULL, &cc->flashaddress, offset);
15566 + W_REG(NULL, &cc->flashdata, *buf);
15567 + /* Page program */
15568 + sflash_cmd(cc, SFLASH_ST_PP);
15569 + }
15570 + break;
15571 + case SFLASH_AT:
15572 + mask = sfl->blocksize - 1;
15573 + page = (offset & ~mask) << 1;
15574 + byte = offset & mask;
15575 + /* Read main memory page into buffer 1 */
15576 + if (byte || (len < sfl->blocksize)) {
15577 + W_REG(NULL, &cc->flashaddress, page);
15578 + sflash_cmd(cc, SFLASH_AT_BUF1_LOAD);
15579 + /* 250 us for AT45DB321B */
15580 + SPINWAIT(sflash_poll(cc, offset), 1000);
15581 + ASSERT(!sflash_poll(cc, offset));
15582 + }
15583 + /* Write into buffer 1 */
15584 + for (ret = 0; (ret < (int)len) && (byte < sfl->blocksize); ret++) {
15585 + W_REG(NULL, &cc->flashaddress, byte++);
15586 + W_REG(NULL, &cc->flashdata, *buf++);
15587 + sflash_cmd(cc, SFLASH_AT_BUF1_WRITE);
15588 + }
15589 + /* Write buffer 1 into main memory page */
15590 + W_REG(NULL, &cc->flashaddress, page);
15591 + sflash_cmd(cc, SFLASH_AT_BUF1_PROGRAM);
15592 + break;
15593 + }
15594 +
15595 + return ret;
15596 +}
15597 +
15598 +/* Erase a region. Returns number of bytes scheduled for erasure.
15599 + * Caller should poll for completion.
15600 + */
15601 +int
15602 +sflash_erase(chipcregs_t *cc, uint offset)
15603 +{
15604 + struct sflash *sfl;
15605 +
15606 + if (offset >= sflash.size)
15607 + return -22;
15608 +
15609 + sfl = &sflash;
15610 + switch (sfl->type) {
15611 + case SFLASH_ST:
15612 + sflash_cmd(cc, SFLASH_ST_WREN);
15613 + W_REG(NULL, &cc->flashaddress, offset);
15614 + sflash_cmd(cc, SFLASH_ST_SE);
15615 + return sfl->blocksize;
15616 + case SFLASH_AT:
15617 + W_REG(NULL, &cc->flashaddress, offset << 1);
15618 + sflash_cmd(cc, SFLASH_AT_PAGE_ERASE);
15619 + return sfl->blocksize;
15620 + }
15621 +
15622 + return 0;
15623 +}
15624 +
15625 +/*
15626 + * writes the appropriate range of flash, a NULL buf simply erases
15627 + * the region of flash
15628 + */
15629 +int
15630 +sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
15631 +{
15632 + struct sflash *sfl;
15633 + uchar *block = NULL, *cur_ptr, *blk_ptr;
15634 + uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
15635 + uint blk_offset, blk_len, copied;
15636 + int bytes, ret = 0;
15637 +
15638 + /* Check address range */
15639 + if (len <= 0)
15640 + return 0;
15641 +
15642 + sfl = &sflash;
15643 + if ((offset + len) > sfl->size)
15644 + return -1;
15645 +
15646 + blocksize = sfl->blocksize;
15647 + mask = blocksize - 1;
15648 +
15649 + /* Allocate a block of mem */
15650 + if (!(block = MALLOC(NULL, blocksize)))
15651 + return -1;
15652 +
15653 + while (len) {
15654 + /* Align offset */
15655 + cur_offset = offset & ~mask;
15656 + cur_length = blocksize;
15657 + cur_ptr = block;
15658 +
15659 + remainder = blocksize - (offset & mask);
15660 + if (len < remainder)
15661 + cur_retlen = len;
15662 + else
15663 + cur_retlen = remainder;
15664 +
15665 + /* buf == NULL means erase only */
15666 + if (buf) {
15667 + /* Copy existing data into holding block if necessary */
15668 + if ((offset & mask) || (len < blocksize)) {
15669 + blk_offset = cur_offset;
15670 + blk_len = cur_length;
15671 + blk_ptr = cur_ptr;
15672 +
15673 + /* Copy entire block */
15674 + while (blk_len) {
15675 + copied = sflash_read(cc, blk_offset, blk_len, blk_ptr);
15676 + blk_offset += copied;
15677 + blk_len -= copied;
15678 + blk_ptr += copied;
15679 + }
15680 + }
15681 +
15682 + /* Copy input data into holding block */
15683 + memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
15684 + }
15685 +
15686 + /* Erase block */
15687 + if ((ret = sflash_erase(cc, (uint) cur_offset)) < 0)
15688 + goto done;
15689 + while (sflash_poll(cc, (uint) cur_offset));
15690 +
15691 + /* buf == NULL means erase only */
15692 + if (!buf) {
15693 + offset += cur_retlen;
15694 + len -= cur_retlen;
15695 + continue;
15696 + }
15697 +
15698 + /* Write holding block */
15699 + while (cur_length > 0) {
15700 + if ((bytes = sflash_write(cc,
15701 + (uint) cur_offset,
15702 + (uint) cur_length,
15703 + (uchar *) cur_ptr)) < 0) {
15704 + ret = bytes;
15705 + goto done;
15706 + }
15707 + while (sflash_poll(cc, (uint) cur_offset));
15708 + cur_offset += bytes;
15709 + cur_length -= bytes;
15710 + cur_ptr += bytes;
15711 + }
15712 +
15713 + offset += cur_retlen;
15714 + len -= cur_retlen;
15715 + buf += cur_retlen;
15716 + }
15717 +
15718 + ret = len;
15719 +done:
15720 + if (block)
15721 + MFREE(NULL, block, blocksize);
15722 + return ret;
15723 +}
15724 diff -urN linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c
15725 --- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
15726 +++ linux.dev/arch/mips/bcm947xx/time.c 2006-10-02 21:19:59.000000000 +0200
15727 @@ -0,0 +1,104 @@
15728 +/*
15729 + * Copyright 2006, Broadcom Corporation
15730 + * All Rights Reserved.
15731 + *
15732 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15733 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15734 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15735 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15736 + *
15737 + * $Id: time.c,v 1.1.1.10 2006/02/27 03:42:55 honor Exp $
15738 + */
15739 +#include <linux/config.h>
15740 +#include <linux/init.h>
15741 +#include <linux/kernel.h>
15742 +#include <linux/sched.h>
15743 +#include <linux/serial_reg.h>
15744 +#include <linux/interrupt.h>
15745 +#include <asm/addrspace.h>
15746 +#include <asm/io.h>
15747 +#include <asm/time.h>
15748 +
15749 +#include <typedefs.h>
15750 +#include <osl.h>
15751 +#include <bcmnvram.h>
15752 +#include <sbconfig.h>
15753 +#include <sbextif.h>
15754 +#include <sbutils.h>
15755 +#include <hndmips.h>
15756 +#include <mipsinc.h>
15757 +#include <hndcpu.h>
15758 +
15759 +/* Global SB handle */
15760 +extern void *bcm947xx_sbh;
15761 +extern spinlock_t bcm947xx_sbh_lock;
15762 +
15763 +/* Convenience */
15764 +#define sbh bcm947xx_sbh
15765 +#define sbh_lock bcm947xx_sbh_lock
15766 +
15767 +extern int panic_timeout;
15768 +static int watchdog = 0;
15769 +static u8 *mcr = NULL;
15770 +
15771 +void __init
15772 +bcm947xx_time_init(void)
15773 +{
15774 + unsigned int hz;
15775 + extifregs_t *eir;
15776 +
15777 + /*
15778 + * Use deterministic values for initial counter interrupt
15779 + * so that calibrate delay avoids encountering a counter wrap.
15780 + */
15781 + write_c0_count(0);
15782 + write_c0_compare(0xffff);
15783 +
15784 + if (!(hz = sb_cpu_clock(sbh)))
15785 + hz = 100000000;
15786 +
15787 + printk("CPU: BCM%04x rev %d at %d MHz\n", sb_chip(sbh), sb_chiprev(sbh),
15788 + (hz + 500000) / 1000000);
15789 +
15790 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
15791 + mips_hpt_frequency = hz / 2;
15792 +
15793 + /* Set watchdog interval in ms */
15794 + watchdog = simple_strtoul(nvram_safe_get("watchdog"), NULL, 0);
15795 +
15796 + /* Please set the watchdog to 3 sec if it is less than 3 but not equal to 0 */
15797 + if (watchdog > 0) {
15798 + if (watchdog < 3000)
15799 + watchdog = 3000;
15800 + }
15801 +
15802 + /* Set panic timeout in seconds */
15803 + panic_timeout = watchdog / 1000;
15804 +}
15805 +
15806 +static void
15807 +bcm947xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
15808 +{
15809 + /* Generic MIPS timer code */
15810 + timer_interrupt(irq, dev_id, regs);
15811 +
15812 + /* Set the watchdog timer to reset after the specified number of ms */
15813 + if (watchdog > 0)
15814 + sb_watchdog(sbh, WATCHDOG_CLOCK / 1000 * watchdog);
15815 +}
15816 +
15817 +static struct irqaction bcm947xx_timer_irqaction = {
15818 + bcm947xx_timer_interrupt,
15819 + SA_INTERRUPT,
15820 + 0,
15821 + "timer",
15822 + NULL,
15823 + NULL
15824 +};
15825 +
15826 +void __init
15827 +bcm947xx_timer_setup(struct irqaction *irq)
15828 +{
15829 + /* Enable the timer interrupt */
15830 + setup_irq(7, &bcm947xx_timer_irqaction);
15831 +}
15832 diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
15833 --- linux.old/arch/mips/config-shared.in 2006-10-02 21:23:10.000000000 +0200
15834 +++ linux.dev/arch/mips/config-shared.in 2006-10-02 21:19:59.000000000 +0200
15835 @@ -208,6 +208,14 @@
15836 fi
15837 define_bool CONFIG_MIPS_RTC y
15838 fi
15839 +dep_bool 'Support for Broadcom MIPS-based boards' CONFIG_MIPS_BRCM $CONFIG_EXPERIMENTAL
15840 +dep_bool 'Support for Broadcom BCM947XX' CONFIG_BCM947XX $CONFIG_MIPS_BRCM
15841 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
15842 + bool ' Support for Broadcom BCM4710' CONFIG_BCM4710
15843 + bool ' Support for Broadcom BCM4310' CONFIG_BCM4310
15844 + bool ' Support for Broadcom BCM4704' CONFIG_BCM4704
15845 + bool ' Support for Broadcom BCM5365' CONFIG_BCM5365
15846 +fi
15847 bool 'Support for SNI RM200 PCI' CONFIG_SNI_RM200_PCI
15848 bool 'Support for TANBAC TB0226 (Mbase)' CONFIG_TANBAC_TB0226
15849 bool 'Support for TANBAC TB0229 (VR4131DIMM)' CONFIG_TANBAC_TB0229
15850 @@ -229,6 +237,11 @@
15851 define_bool CONFIG_RWSEM_XCHGADD_ALGORITHM n
15852
15853 #
15854 +# Provide an option for a default kernel command line
15855 +#
15856 +string 'Default kernel command string' CONFIG_CMDLINE ""
15857 +
15858 +#
15859 # Select some configuration options automatically based on user selections.
15860 #
15861 if [ "$CONFIG_ACER_PICA_61" = "y" ]; then
15862 @@ -554,6 +567,12 @@
15863 define_bool CONFIG_SWAP_IO_SPACE_L y
15864 define_bool CONFIG_BOOT_ELF32 y
15865 fi
15866 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
15867 + define_bool CONFIG_PCI y
15868 + define_bool CONFIG_NONCOHERENT_IO y
15869 + define_bool CONFIG_NEW_TIME_C y
15870 + define_bool CONFIG_NEW_IRQ y
15871 +fi
15872 if [ "$CONFIG_SNI_RM200_PCI" = "y" ]; then
15873 define_bool CONFIG_ARC32 y
15874 define_bool CONFIG_ARC_MEMORY y
15875 @@ -1042,7 +1061,11 @@
15876
15877 bool 'Are you using a crosscompiler' CONFIG_CROSSCOMPILE
15878 bool 'Enable run-time debugging' CONFIG_RUNTIME_DEBUG
15879 -bool 'Remote GDB kernel debugging' CONFIG_KGDB
15880 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
15881 + bool 'Remote GDB kernel debugging' CONFIG_REMOTE_DEBUG
15882 +else
15883 + bool 'Remote GDB kernel debugging' CONFIG_KGDB
15884 +fi
15885 dep_bool ' Console output to GDB' CONFIG_GDB_CONSOLE $CONFIG_KGDB
15886 if [ "$CONFIG_KGDB" = "y" ]; then
15887 define_bool CONFIG_DEBUG_INFO y
15888 diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c
15889 --- linux.old/arch/mips/kernel/cpu-probe.c 2006-10-02 21:23:10.000000000 +0200
15890 +++ linux.dev/arch/mips/kernel/cpu-probe.c 2006-10-02 21:19:59.000000000 +0200
15891 @@ -162,7 +162,7 @@
15892
15893 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
15894 {
15895 - switch (c->processor_id & 0xff00) {
15896 + switch (c->processor_id & PRID_IMP_MASK) {
15897 case PRID_IMP_R2000:
15898 c->cputype = CPU_R2000;
15899 c->isa_level = MIPS_CPU_ISA_I;
15900 @@ -172,7 +172,7 @@
15901 c->tlbsize = 64;
15902 break;
15903 case PRID_IMP_R3000:
15904 - if ((c->processor_id & 0xff) == PRID_REV_R3000A)
15905 + if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A)
15906 if (cpu_has_confreg())
15907 c->cputype = CPU_R3081E;
15908 else
15909 @@ -187,12 +187,12 @@
15910 break;
15911 case PRID_IMP_R4000:
15912 if (read_c0_config() & CONF_SC) {
15913 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
15914 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
15915 c->cputype = CPU_R4400PC;
15916 else
15917 c->cputype = CPU_R4000PC;
15918 } else {
15919 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
15920 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
15921 c->cputype = CPU_R4400SC;
15922 else
15923 c->cputype = CPU_R4000SC;
15924 @@ -438,7 +438,7 @@
15925 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
15926 {
15927 decode_config1(c);
15928 - switch (c->processor_id & 0xff00) {
15929 + switch (c->processor_id & PRID_IMP_MASK) {
15930 case PRID_IMP_4KC:
15931 c->cputype = CPU_4KC;
15932 c->isa_level = MIPS_CPU_ISA_M32;
15933 @@ -479,10 +479,10 @@
15934 {
15935 decode_config1(c);
15936 c->options |= MIPS_CPU_PREFETCH;
15937 - switch (c->processor_id & 0xff00) {
15938 + switch (c->processor_id & PRID_IMP_MASK) {
15939 case PRID_IMP_AU1_REV1:
15940 case PRID_IMP_AU1_REV2:
15941 - switch ((c->processor_id >> 24) & 0xff) {
15942 + switch ((c->processor_id >> 24) & PRID_REV_MASK) {
15943 case 0:
15944 c->cputype = CPU_AU1000;
15945 break;
15946 @@ -510,10 +510,34 @@
15947 }
15948 }
15949
15950 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
15951 +{
15952 + decode_config1(c);
15953 + c->options |= MIPS_CPU_PREFETCH;
15954 + switch (c->processor_id & PRID_IMP_MASK) {
15955 + case PRID_IMP_BCM4710:
15956 + c->cputype = CPU_BCM4710;
15957 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
15958 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
15959 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
15960 + break;
15961 + case PRID_IMP_4KC:
15962 + case PRID_IMP_BCM3302:
15963 + c->cputype = CPU_BCM3302;
15964 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
15965 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
15966 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
15967 + break;
15968 + default:
15969 + c->cputype = CPU_UNKNOWN;
15970 + break;
15971 + }
15972 +}
15973 +
15974 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
15975 {
15976 decode_config1(c);
15977 - switch (c->processor_id & 0xff00) {
15978 + switch (c->processor_id & PRID_IMP_MASK) {
15979 case PRID_IMP_SB1:
15980 c->cputype = CPU_SB1;
15981 c->isa_level = MIPS_CPU_ISA_M64;
15982 @@ -535,7 +559,7 @@
15983 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
15984 {
15985 decode_config1(c);
15986 - switch (c->processor_id & 0xff00) {
15987 + switch (c->processor_id & PRID_IMP_MASK) {
15988 case PRID_IMP_SR71000:
15989 c->cputype = CPU_SR71000;
15990 c->isa_level = MIPS_CPU_ISA_M64;
15991 @@ -560,7 +584,7 @@
15992 c->cputype = CPU_UNKNOWN;
15993
15994 c->processor_id = read_c0_prid();
15995 - switch (c->processor_id & 0xff0000) {
15996 + switch (c->processor_id & PRID_COMP_MASK) {
15997
15998 case PRID_COMP_LEGACY:
15999 cpu_probe_legacy(c);
16000 @@ -571,6 +595,9 @@
16001 case PRID_COMP_ALCHEMY:
16002 cpu_probe_alchemy(c);
16003 break;
16004 + case PRID_COMP_BROADCOM:
16005 + cpu_probe_broadcom(c);
16006 + break;
16007 case PRID_COMP_SIBYTE:
16008 cpu_probe_sibyte(c);
16009 break;
16010 diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
16011 --- linux.old/arch/mips/kernel/head.S 2006-10-02 21:23:10.000000000 +0200
16012 +++ linux.dev/arch/mips/kernel/head.S 2006-10-02 21:19:59.000000000 +0200
16013 @@ -28,12 +28,20 @@
16014 #include <asm/mipsregs.h>
16015 #include <asm/stackframe.h>
16016
16017 +#ifdef CONFIG_BCM4710
16018 +#undef eret
16019 +#define eret nop; nop; eret
16020 +#endif
16021 +
16022 .text
16023 + j kernel_entry
16024 + nop
16025 +
16026 /*
16027 * Reserved space for exception handlers.
16028 * Necessary for machines which link their kernels at KSEG0.
16029 */
16030 - .fill 0x400
16031 + .fill 0x3f4
16032
16033 /* The following two symbols are used for kernel profiling. */
16034 EXPORT(stext)
16035 diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c
16036 --- linux.old/arch/mips/kernel/proc.c 2006-10-02 21:23:10.000000000 +0200
16037 +++ linux.dev/arch/mips/kernel/proc.c 2006-10-02 21:19:59.000000000 +0200
16038 @@ -78,9 +78,10 @@
16039 [CPU_AU1550] "Au1550",
16040 [CPU_24K] "MIPS 24K",
16041 [CPU_AU1200] "Au1200",
16042 + [CPU_BCM4710] "BCM4710",
16043 + [CPU_BCM3302] "BCM3302",
16044 };
16045
16046 -
16047 static int show_cpuinfo(struct seq_file *m, void *v)
16048 {
16049 unsigned int version = current_cpu_data.processor_id;
16050 diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
16051 --- linux.old/arch/mips/kernel/setup.c 2006-10-02 21:23:10.000000000 +0200
16052 +++ linux.dev/arch/mips/kernel/setup.c 2006-10-02 21:19:59.000000000 +0200
16053 @@ -493,6 +493,7 @@
16054 void swarm_setup(void);
16055 void hp_setup(void);
16056 void au1x00_setup(void);
16057 + void brcm_setup(void);
16058 void frame_info_init(void);
16059
16060 frame_info_init();
16061 @@ -691,6 +692,11 @@
16062 pmc_yosemite_setup();
16063 break;
16064 #endif
16065 +#if defined(CONFIG_BCM4710) || defined(CONFIG_BCM4310)
16066 + case MACH_GROUP_BRCM:
16067 + brcm_setup();
16068 + break;
16069 +#endif
16070 default:
16071 panic("Unsupported architecture");
16072 }
16073 diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
16074 --- linux.old/arch/mips/kernel/traps.c 2006-10-02 21:23:10.000000000 +0200
16075 +++ linux.dev/arch/mips/kernel/traps.c 2006-10-02 21:19:59.000000000 +0200
16076 @@ -920,6 +920,7 @@
16077 void __init trap_init(void)
16078 {
16079 extern char except_vec1_generic;
16080 + extern char except_vec2_generic;
16081 extern char except_vec3_generic, except_vec3_r4000;
16082 extern char except_vec_ejtag_debug;
16083 extern char except_vec4;
16084 @@ -927,6 +928,7 @@
16085
16086 /* Copy the generic exception handler code to it's final destination. */
16087 memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
16088 + memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
16089
16090 /*
16091 * Setup default vectors
16092 @@ -985,6 +987,12 @@
16093 set_except_vector(13, handle_tr);
16094 set_except_vector(22, handle_mdmx);
16095
16096 + if (current_cpu_data.cputype == CPU_SB1) {
16097 + /* Enable timer interrupt and scd mapped interrupt */
16098 + clear_c0_status(0xf000);
16099 + set_c0_status(0xc00);
16100 + }
16101 +
16102 if (cpu_has_fpu && !cpu_has_nofpuex)
16103 set_except_vector(15, handle_fpe);
16104
16105 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
16106 --- linux.old/arch/mips/Makefile 2006-10-02 21:23:10.000000000 +0200
16107 +++ linux.dev/arch/mips/Makefile 2006-10-02 21:19:59.000000000 +0200
16108 @@ -726,6 +726,19 @@
16109 endif
16110
16111 #
16112 +# Broadcom BCM947XX variants
16113 +#
16114 +ifdef CONFIG_BCM947XX
16115 +LIBS += arch/mips/bcm947xx/generic/brcm.o arch/mips/bcm947xx/bcm947xx.o
16116 +SUBDIRS += arch/mips/bcm947xx/generic arch/mips/bcm947xx
16117 +LOADADDR := 0x80001000
16118 +
16119 +zImage: vmlinux
16120 + $(MAKE) -C arch/$(ARCH)/bcm947xx/compressed
16121 +export LOADADDR
16122 +endif
16123 +
16124 +#
16125 # Choosing incompatible machines durings configuration will result in
16126 # error messages during linking. Select a default linkscript if
16127 # none has been choosen above.
16128 @@ -778,6 +791,7 @@
16129 $(MAKE) -C arch/$(ARCH)/tools clean
16130 $(MAKE) -C arch/mips/baget clean
16131 $(MAKE) -C arch/mips/lasat clean
16132 + $(MAKE) -C arch/mips/bcm947xx/compressed clean
16133
16134 archmrproper:
16135 @$(MAKEBOOT) mrproper
16136 diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
16137 --- linux.old/arch/mips/mm/c-r4k.c 2006-10-02 21:23:10.000000000 +0200
16138 +++ linux.dev/arch/mips/mm/c-r4k.c 2006-10-02 21:19:59.000000000 +0200
16139 @@ -1166,3 +1166,47 @@
16140 build_clear_page();
16141 build_copy_page();
16142 }
16143 +
16144 +#ifdef CONFIG_BCM4704
16145 +static void __init mips32_icache_fill(unsigned long addr, uint nbytes)
16146 +{
16147 + unsigned long ic_lsize = current_cpu_data.icache.linesz;
16148 + int i;
16149 + for (i = 0; i < nbytes; i += ic_lsize)
16150 + fill_icache_line((addr + i));
16151 +}
16152 +
16153 +/*
16154 + * This must be run from the cache on 4704A0
16155 + * so there are no mips core BIU ops in progress
16156 + * when the PFC is enabled.
16157 + */
16158 +#define PFC_CR0 0xff400000 /* control reg 0 */
16159 +#define PFC_CR1 0xff400004 /* control reg 1 */
16160 +static void __init enable_pfc(u32 mode)
16161 +{
16162 + /* write range */
16163 + *(volatile u32 *)PFC_CR1 = 0xffff0000;
16164 +
16165 + /* enable */
16166 + *(volatile u32 *)PFC_CR0 = mode;
16167 +}
16168 +#endif
16169 +
16170 +
16171 +void check_enable_mips_pfc(int val)
16172 +{
16173 +
16174 +#ifdef CONFIG_BCM4704
16175 + struct cpuinfo_mips *c = &current_cpu_data;
16176 +
16177 + /* enable prefetch cache */
16178 + if (((c->processor_id & (PRID_COMP_MASK | PRID_IMP_MASK)) == PRID_IMP_BCM3302)
16179 + && (read_c0_diag() & (1 << 29))) {
16180 + mips32_icache_fill((unsigned long) &enable_pfc, 64);
16181 + enable_pfc(val);
16182 + }
16183 +#endif
16184 +}
16185 +
16186 +
16187 diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
16188 --- linux.old/arch/mips/pci/Makefile 2006-10-02 21:23:10.000000000 +0200
16189 +++ linux.dev/arch/mips/pci/Makefile 2006-10-02 21:19:59.000000000 +0200
16190 @@ -13,7 +13,9 @@
16191 obj-$(CONFIG_MIPS_MSC) += ops-msc.o
16192 obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
16193 obj-$(CONFIG_SNI_RM200_PCI) += ops-sni.o
16194 +ifndef CONFIG_BCM947XX
16195 obj-y += pci.o
16196 +endif
16197 obj-$(CONFIG_PCI_AUTO) += pci_auto.o
16198
16199 include $(TOPDIR)/Rules.make
16200 diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
16201 --- linux.old/drivers/char/serial.c 2006-10-02 21:23:10.000000000 +0200
16202 +++ linux.dev/drivers/char/serial.c 2006-10-02 21:19:59.000000000 +0200
16203 @@ -444,6 +444,10 @@
16204 return inb(info->port+1);
16205 #endif
16206 case SERIAL_IO_MEM:
16207 +#ifdef CONFIG_BCM4310
16208 + readb((unsigned long) info->iomem_base +
16209 + (UART_SCR<<info->iomem_reg_shift));
16210 +#endif
16211 return readb((unsigned long) info->iomem_base +
16212 (offset<<info->iomem_reg_shift));
16213 default:
16214 @@ -464,6 +468,9 @@
16215 case SERIAL_IO_MEM:
16216 writeb(value, (unsigned long) info->iomem_base +
16217 (offset<<info->iomem_reg_shift));
16218 +#ifdef CONFIG_BCM4704
16219 + *((volatile unsigned int *) KSEG1ADDR(0x18000000));
16220 +#endif
16221 break;
16222 default:
16223 outb(value, info->port+offset);
16224 @@ -1728,7 +1735,7 @@
16225 /* Special case since 134 is really 134.5 */
16226 quot = (2*baud_base / 269);
16227 else if (baud)
16228 - quot = baud_base / baud;
16229 + quot = (baud_base + (baud / 2)) / baud;
16230 }
16231 /* If the quotient is zero refuse the change */
16232 if (!quot && old_termios) {
16233 @@ -1745,12 +1752,12 @@
16234 /* Special case since 134 is really 134.5 */
16235 quot = (2*baud_base / 269);
16236 else if (baud)
16237 - quot = baud_base / baud;
16238 + quot = (baud_base + (baud / 2)) / baud;
16239 }
16240 }
16241 /* As a last resort, if the quotient is zero, default to 9600 bps */
16242 if (!quot)
16243 - quot = baud_base / 9600;
16244 + quot = (baud_base + 4800) / 9600;
16245 /*
16246 * Work around a bug in the Oxford Semiconductor 952 rev B
16247 * chip which causes it to seriously miscalculate baud rates
16248 @@ -5994,6 +6001,13 @@
16249 * Divisor, bytesize and parity
16250 */
16251 state = rs_table + co->index;
16252 + /*
16253 + * Safe guard: state structure must have been initialized
16254 + */
16255 + if (state->iomem_base == NULL) {
16256 + printk("!unable to setup serial console!\n");
16257 + return -1;
16258 + }
16259 if (doflow)
16260 state->flags |= ASYNC_CONS_FLOW;
16261 info = &async_sercons;
16262 @@ -6007,7 +6021,7 @@
16263 info->io_type = state->io_type;
16264 info->iomem_base = state->iomem_base;
16265 info->iomem_reg_shift = state->iomem_reg_shift;
16266 - quot = state->baud_base / baud;
16267 + quot = (state->baud_base + (baud / 2)) / baud;
16268 cval = cflag & (CSIZE | CSTOPB);
16269 #if defined(__powerpc__) || defined(__alpha__)
16270 cval >>= 8;
16271 diff -urN linux.old/drivers/net/Makefile linux.dev/drivers/net/Makefile
16272 --- linux.old/drivers/net/Makefile 2006-10-02 21:23:10.000000000 +0200
16273 +++ linux.dev/drivers/net/Makefile 2006-10-02 21:19:59.000000000 +0200
16274 @@ -3,6 +3,8 @@
16275 # Makefile for the Linux network (ethercard) device drivers.
16276 #
16277
16278 +EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include
16279 +
16280 obj-y :=
16281 obj-m :=
16282 obj-n :=
16283 diff -urN linux.old/drivers/parport/Config.in linux.dev/drivers/parport/Config.in
16284 --- linux.old/drivers/parport/Config.in 2006-10-02 21:23:10.000000000 +0200
16285 +++ linux.dev/drivers/parport/Config.in 2006-10-02 21:19:59.000000000 +0200
16286 @@ -11,6 +11,7 @@
16287 tristate 'Parallel port support' CONFIG_PARPORT
16288 if [ "$CONFIG_PARPORT" != "n" ]; then
16289 dep_tristate ' PC-style hardware' CONFIG_PARPORT_PC $CONFIG_PARPORT
16290 + dep_tristate ' Asus WL500g parallel port' CONFIG_PARPORT_SPLINK $CONFIG_PARPORT
16291 if [ "$CONFIG_PARPORT_PC" != "n" -a "$CONFIG_SERIAL" != "n" ]; then
16292 if [ "$CONFIG_SERIAL" = "m" ]; then
16293 define_tristate CONFIG_PARPORT_PC_CML1 m
16294 diff -urN linux.old/drivers/parport/Makefile linux.dev/drivers/parport/Makefile
16295 --- linux.old/drivers/parport/Makefile 2006-10-02 21:23:10.000000000 +0200
16296 +++ linux.dev/drivers/parport/Makefile 2006-10-02 21:19:59.000000000 +0200
16297 @@ -22,6 +22,7 @@
16298
16299 obj-$(CONFIG_PARPORT) += parport.o
16300 obj-$(CONFIG_PARPORT_PC) += parport_pc.o
16301 +obj-$(CONFIG_PARPORT_SPLINK) += parport_splink.o
16302 obj-$(CONFIG_PARPORT_PC_PCMCIA) += parport_cs.o
16303 obj-$(CONFIG_PARPORT_AMIGA) += parport_amiga.o
16304 obj-$(CONFIG_PARPORT_MFC3) += parport_mfc3.o
16305 diff -urN linux.old/drivers/parport/parport_splink.c linux.dev/drivers/parport/parport_splink.c
16306 --- linux.old/drivers/parport/parport_splink.c 1970-01-01 01:00:00.000000000 +0100
16307 +++ linux.dev/drivers/parport/parport_splink.c 2006-10-02 21:19:59.000000000 +0200
16308 @@ -0,0 +1,345 @@
16309 +/* Low-level parallel port routines for the ASUS WL-500g built-in port
16310 + *
16311 + * Author: Nuno Grilo <nuno.grilo@netcabo.pt>
16312 + * Based on parport_pc source
16313 + */
16314 +
16315 +#include <linux/config.h>
16316 +#include <linux/module.h>
16317 +#include <linux/init.h>
16318 +#include <linux/ioport.h>
16319 +#include <linux/kernel.h>
16320 +#include <linux/slab.h>
16321 +#include <linux/parport.h>
16322 +#include <linux/parport_pc.h>
16323 +
16324 +#define SPLINK_ADDRESS 0xBF800010
16325 +
16326 +#undef DEBUG
16327 +
16328 +#ifdef DEBUG
16329 +#define DPRINTK printk
16330 +#else
16331 +#define DPRINTK(stuff...)
16332 +#endif
16333 +
16334 +
16335 +/* __parport_splink_frob_control differs from parport_splink_frob_control in that
16336 + * it doesn't do any extra masking. */
16337 +static __inline__ unsigned char __parport_splink_frob_control (struct parport *p,
16338 + unsigned char mask,
16339 + unsigned char val)
16340 +{
16341 + struct parport_pc_private *priv = p->physport->private_data;
16342 + unsigned char *io = (unsigned char *) p->base;
16343 + unsigned char ctr = priv->ctr;
16344 +#ifdef DEBUG_PARPORT
16345 + printk (KERN_DEBUG
16346 + "__parport_splink_frob_control(%02x,%02x): %02x -> %02x\n",
16347 + mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable);
16348 +#endif
16349 + ctr = (ctr & ~mask) ^ val;
16350 + ctr &= priv->ctr_writable; /* only write writable bits. */
16351 + *(io+2) = ctr;
16352 + priv->ctr = ctr; /* Update soft copy */
16353 + return ctr;
16354 +}
16355 +
16356 +
16357 +
16358 +static void parport_splink_data_forward (struct parport *p)
16359 +{
16360 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
16361 + __parport_splink_frob_control (p, 0x20, 0);
16362 +}
16363 +
16364 +static void parport_splink_data_reverse (struct parport *p)
16365 +{
16366 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
16367 + __parport_splink_frob_control (p, 0x20, 0x20);
16368 +}
16369 +
16370 +/*
16371 +static void parport_splink_interrupt(int irq, void *dev_id, struct pt_regs *regs)
16372 +{
16373 + DPRINTK(KERN_DEBUG "parport_splink: IRQ handler called\n");
16374 + parport_generic_irq(irq, (struct parport *) dev_id, regs);
16375 +}
16376 +*/
16377 +
16378 +static void parport_splink_enable_irq(struct parport *p)
16379 +{
16380 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_enable_irq called\n");
16381 + __parport_splink_frob_control (p, 0x10, 0x10);
16382 +}
16383 +
16384 +static void parport_splink_disable_irq(struct parport *p)
16385 +{
16386 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_disable_irq called\n");
16387 + __parport_splink_frob_control (p, 0x10, 0);
16388 +}
16389 +
16390 +static void parport_splink_init_state(struct pardevice *dev, struct parport_state *s)
16391 +{
16392 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_init_state called\n");
16393 + s->u.pc.ctr = 0xc | (dev->irq_func ? 0x10 : 0x0);
16394 + if (dev->irq_func &&
16395 + dev->port->irq != PARPORT_IRQ_NONE)
16396 + /* Set ackIntEn */
16397 + s->u.pc.ctr |= 0x10;
16398 +}
16399 +
16400 +static void parport_splink_save_state(struct parport *p, struct parport_state *s)
16401 +{
16402 + const struct parport_pc_private *priv = p->physport->private_data;
16403 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_save_state called\n");
16404 + s->u.pc.ctr = priv->ctr;
16405 +}
16406 +
16407 +static void parport_splink_restore_state(struct parport *p, struct parport_state *s)
16408 +{
16409 + struct parport_pc_private *priv = p->physport->private_data;
16410 + unsigned char *io = (unsigned char *) p->base;
16411 + unsigned char ctr = s->u.pc.ctr;
16412 +
16413 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_restore_state called\n");
16414 + *(io+2) = ctr;
16415 + priv->ctr = ctr;
16416 +}
16417 +
16418 +static void parport_splink_setup_interrupt(void) {
16419 + return;
16420 +}
16421 +
16422 +static void parport_splink_write_data(struct parport *p, unsigned char d) {
16423 + DPRINTK(KERN_DEBUG "parport_splink: write data called\n");
16424 + unsigned char *io = (unsigned char *) p->base;
16425 + *io = d;
16426 +}
16427 +
16428 +static unsigned char parport_splink_read_data(struct parport *p) {
16429 + DPRINTK(KERN_DEBUG "parport_splink: read data called\n");
16430 + unsigned char *io = (unsigned char *) p->base;
16431 + return *io;
16432 +}
16433 +
16434 +static void parport_splink_write_control(struct parport *p, unsigned char d)
16435 +{
16436 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
16437 + PARPORT_CONTROL_AUTOFD |
16438 + PARPORT_CONTROL_INIT |
16439 + PARPORT_CONTROL_SELECT);
16440 +
16441 + DPRINTK(KERN_DEBUG "parport_splink: write control called\n");
16442 + /* Take this out when drivers have adapted to the newer interface. */
16443 + if (d & 0x20) {
16444 + printk (KERN_DEBUG "%s (%s): use data_reverse for this!\n",
16445 + p->name, p->cad->name);
16446 + parport_splink_data_reverse (p);
16447 + }
16448 +
16449 + __parport_splink_frob_control (p, wm, d & wm);
16450 +}
16451 +
16452 +static unsigned char parport_splink_read_control(struct parport *p)
16453 +{
16454 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
16455 + PARPORT_CONTROL_AUTOFD |
16456 + PARPORT_CONTROL_INIT |
16457 + PARPORT_CONTROL_SELECT);
16458 + DPRINTK(KERN_DEBUG "parport_splink: read control called\n");
16459 + const struct parport_pc_private *priv = p->physport->private_data;
16460 + return priv->ctr & wm; /* Use soft copy */
16461 +}
16462 +
16463 +static unsigned char parport_splink_frob_control (struct parport *p, unsigned char mask,
16464 + unsigned char val)
16465 +{
16466 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
16467 + PARPORT_CONTROL_AUTOFD |
16468 + PARPORT_CONTROL_INIT |
16469 + PARPORT_CONTROL_SELECT);
16470 +
16471 + DPRINTK(KERN_DEBUG "parport_splink: frob control called\n");
16472 + /* Take this out when drivers have adapted to the newer interface. */
16473 + if (mask & 0x20) {
16474 + printk (KERN_DEBUG "%s (%s): use data_%s for this!\n",
16475 + p->name, p->cad->name,
16476 + (val & 0x20) ? "reverse" : "forward");
16477 + if (val & 0x20)
16478 + parport_splink_data_reverse (p);
16479 + else
16480 + parport_splink_data_forward (p);
16481 + }
16482 +
16483 + /* Restrict mask and val to control lines. */
16484 + mask &= wm;
16485 + val &= wm;
16486 +
16487 + return __parport_splink_frob_control (p, mask, val);
16488 +}
16489 +
16490 +static unsigned char parport_splink_read_status(struct parport *p)
16491 +{
16492 + DPRINTK(KERN_DEBUG "parport_splink: read status called\n");
16493 + unsigned char *io = (unsigned char *) p->base;
16494 + return *(io+1);
16495 +}
16496 +
16497 +static void parport_splink_inc_use_count(void)
16498 +{
16499 +#ifdef MODULE
16500 + MOD_INC_USE_COUNT;
16501 +#endif
16502 +}
16503 +
16504 +static void parport_splink_dec_use_count(void)
16505 +{
16506 +#ifdef MODULE
16507 + MOD_DEC_USE_COUNT;
16508 +#endif
16509 +}
16510 +
16511 +static struct parport_operations parport_splink_ops =
16512 +{
16513 + parport_splink_write_data,
16514 + parport_splink_read_data,
16515 +
16516 + parport_splink_write_control,
16517 + parport_splink_read_control,
16518 + parport_splink_frob_control,
16519 +
16520 + parport_splink_read_status,
16521 +
16522 + parport_splink_enable_irq,
16523 + parport_splink_disable_irq,
16524 +
16525 + parport_splink_data_forward,
16526 + parport_splink_data_reverse,
16527 +
16528 + parport_splink_init_state,
16529 + parport_splink_save_state,
16530 + parport_splink_restore_state,
16531 +
16532 + parport_splink_inc_use_count,
16533 + parport_splink_dec_use_count,
16534 +
16535 + parport_ieee1284_epp_write_data,
16536 + parport_ieee1284_epp_read_data,
16537 + parport_ieee1284_epp_write_addr,
16538 + parport_ieee1284_epp_read_addr,
16539 +
16540 + parport_ieee1284_ecp_write_data,
16541 + parport_ieee1284_ecp_read_data,
16542 + parport_ieee1284_ecp_write_addr,
16543 +
16544 + parport_ieee1284_write_compat,
16545 + parport_ieee1284_read_nibble,
16546 + parport_ieee1284_read_byte,
16547 +};
16548 +
16549 +/* --- Initialisation code -------------------------------- */
16550 +
16551 +static struct parport *parport_splink_probe_port (unsigned long int base)
16552 +{
16553 + struct parport_pc_private *priv;
16554 + struct parport_operations *ops;
16555 + struct parport *p;
16556 +
16557 + if (check_mem_region(base, 3)) {
16558 + printk (KERN_DEBUG "parport (0x%lx): iomem region not available\n", base);
16559 + return NULL;
16560 + }
16561 + priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
16562 + if (!priv) {
16563 + printk (KERN_DEBUG "parport (0x%lx): no memory!\n", base);
16564 + return NULL;
16565 + }
16566 + ops = kmalloc (sizeof (struct parport_operations), GFP_KERNEL);
16567 + if (!ops) {
16568 + printk (KERN_DEBUG "parport (0x%lx): no memory for ops!\n",
16569 + base);
16570 + kfree (priv);
16571 + return NULL;
16572 + }
16573 + memcpy (ops, &parport_splink_ops, sizeof (struct parport_operations));
16574 + priv->ctr = 0xc;
16575 + priv->ctr_writable = 0xff;
16576 +
16577 + if (!(p = parport_register_port(base, PARPORT_IRQ_NONE,
16578 + PARPORT_DMA_NONE, ops))) {
16579 + printk (KERN_DEBUG "parport (0x%lx): registration failed!\n",
16580 + base);
16581 + kfree (priv);
16582 + kfree (ops);
16583 + return NULL;
16584 + }
16585 +
16586 + p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
16587 + p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
16588 + p->private_data = priv;
16589 +
16590 + parport_proc_register(p);
16591 + request_mem_region (p->base, 3, p->name);
16592 +
16593 + /* Done probing. Now put the port into a sensible start-up state. */
16594 + parport_splink_write_data(p, 0);
16595 + parport_splink_data_forward (p);
16596 +
16597 + /* Now that we've told the sharing engine about the port, and
16598 + found out its characteristics, let the high-level drivers
16599 + know about it. */
16600 + parport_announce_port (p);
16601 +
16602 + DPRINTK(KERN_DEBUG "parport (0x%lx): init ok!\n",
16603 + base);
16604 + return p;
16605 +}
16606 +
16607 +static void parport_splink_unregister_port(struct parport *p) {
16608 + struct parport_pc_private *priv = p->private_data;
16609 + struct parport_operations *ops = p->ops;
16610 +
16611 + if (p->irq != PARPORT_IRQ_NONE)
16612 + free_irq(p->irq, p);
16613 + release_mem_region(p->base, 3);
16614 + parport_proc_unregister(p);
16615 + kfree (priv);
16616 + parport_unregister_port(p);
16617 + kfree (ops);
16618 +}
16619 +
16620 +
16621 +int parport_splink_init(void)
16622 +{
16623 + int ret;
16624 +
16625 + DPRINTK(KERN_DEBUG "parport_splink init called\n");
16626 + parport_splink_setup_interrupt();
16627 + ret = !parport_splink_probe_port(SPLINK_ADDRESS);
16628 +
16629 + return ret;
16630 +}
16631 +
16632 +void parport_splink_cleanup(void) {
16633 + struct parport *p = parport_enumerate(), *tmp;
16634 + DPRINTK(KERN_DEBUG "parport_splink cleanup called\n");
16635 + if (p->size) {
16636 + if (p->modes & PARPORT_MODE_PCSPP) {
16637 + while(p) {
16638 + tmp = p->next;
16639 + parport_splink_unregister_port(p);
16640 + p = tmp;
16641 + }
16642 + }
16643 + }
16644 +}
16645 +
16646 +MODULE_AUTHOR("Nuno Grilo <nuno.grilo@netcabo.pt>");
16647 +MODULE_DESCRIPTION("Parport Driver for ASUS WL-500g router builtin Port");
16648 +MODULE_SUPPORTED_DEVICE("ASUS WL-500g builtin Parallel Port");
16649 +MODULE_LICENSE("GPL");
16650 +
16651 +module_init(parport_splink_init)
16652 +module_exit(parport_splink_cleanup)
16653 +
16654 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
16655 --- linux.old/include/asm-mips/bootinfo.h 2006-10-02 21:23:10.000000000 +0200
16656 +++ linux.dev/include/asm-mips/bootinfo.h 2006-10-02 21:19:59.000000000 +0200
16657 @@ -37,6 +37,7 @@
16658 #define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */
16659 #define MACH_GROUP_LASAT 21
16660 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
16661 +#define MACH_GROUP_BRCM 23 /* Broadcom */
16662
16663 /*
16664 * Valid machtype values for group unknown (low order halfword of mips_machtype)
16665 @@ -197,6 +198,15 @@
16666 #define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */
16667
16668 /*
16669 + * Valid machtypes for group Broadcom
16670 + */
16671 +#define MACH_BCM93725 0
16672 +#define MACH_BCM93725_VJ 1
16673 +#define MACH_BCM93730 2
16674 +#define MACH_BCM947XX 3
16675 +#define MACH_BCM933XX 4
16676 +
16677 +/*
16678 * Valid machtype for group TITAN
16679 */
16680 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
16681 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
16682 --- linux.old/include/asm-mips/cpu.h 2006-10-02 21:23:10.000000000 +0200
16683 +++ linux.dev/include/asm-mips/cpu.h 2006-10-02 21:19:59.000000000 +0200
16684 @@ -22,6 +22,11 @@
16685 spec.
16686 */
16687
16688 +#define PRID_COPT_MASK 0xff000000
16689 +#define PRID_COMP_MASK 0x00ff0000
16690 +#define PRID_IMP_MASK 0x0000ff00
16691 +#define PRID_REV_MASK 0x000000ff
16692 +
16693 #define PRID_COMP_LEGACY 0x000000
16694 #define PRID_COMP_MIPS 0x010000
16695 #define PRID_COMP_BROADCOM 0x020000
16696 @@ -58,6 +63,7 @@
16697 #define PRID_IMP_RM7000 0x2700
16698 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
16699 #define PRID_IMP_RM9000 0x3400
16700 +#define PRID_IMP_BCM4710 0x4000
16701 #define PRID_IMP_R5432 0x5400
16702 #define PRID_IMP_R5500 0x5500
16703 #define PRID_IMP_4KC 0x8000
16704 @@ -66,10 +72,16 @@
16705 #define PRID_IMP_4KEC 0x8400
16706 #define PRID_IMP_4KSC 0x8600
16707 #define PRID_IMP_25KF 0x8800
16708 +#define PRID_IMP_BCM3302 0x9000
16709 +#define PRID_IMP_BCM3303 0x9100
16710 #define PRID_IMP_24K 0x9300
16711
16712 #define PRID_IMP_UNKNOWN 0xff00
16713
16714 +#define BCM330X(id) \
16715 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
16716 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
16717 +
16718 /*
16719 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
16720 */
16721 @@ -174,7 +186,9 @@
16722 #define CPU_AU1550 57
16723 #define CPU_24K 58
16724 #define CPU_AU1200 59
16725 -#define CPU_LAST 59
16726 +#define CPU_BCM4710 60
16727 +#define CPU_BCM3302 61
16728 +#define CPU_LAST 61
16729
16730 /*
16731 * ISA Level encodings
16732 diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
16733 --- linux.old/include/asm-mips/r4kcache.h 2006-10-02 21:23:10.000000000 +0200
16734 +++ linux.dev/include/asm-mips/r4kcache.h 2006-10-02 21:19:59.000000000 +0200
16735 @@ -658,4 +658,17 @@
16736 cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
16737 }
16738
16739 +extern inline void fill_icache_line(unsigned long addr)
16740 +{
16741 + __asm__ __volatile__(
16742 + ".set noreorder\n\t"
16743 + ".set mips3\n\t"
16744 + "cache %1, (%0)\n\t"
16745 + ".set mips0\n\t"
16746 + ".set reorder"
16747 + :
16748 + : "r" (addr),
16749 + "i" (Fill));
16750 +}
16751 +
16752 #endif /* __ASM_R4KCACHE_H */
16753 diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
16754 --- linux.old/include/asm-mips/serial.h 2006-10-02 21:23:10.000000000 +0200
16755 +++ linux.dev/include/asm-mips/serial.h 2006-10-02 21:19:59.000000000 +0200
16756 @@ -223,6 +223,13 @@
16757 #define TXX927_SERIAL_PORT_DEFNS
16758 #endif
16759
16760 +#ifdef CONFIG_BCM947XX
16761 +/* reserve 4 ports to be configured at runtime */
16762 +#define BCM947XX_SERIAL_PORT_DEFNS { 0, }, { 0, }, { 0, }, { 0, },
16763 +#else
16764 +#define BCM947XX_SERIAL_PORT_DEFNS
16765 +#endif
16766 +
16767 #ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
16768 #define STD_SERIAL_PORT_DEFNS \
16769 /* UART CLK PORT IRQ FLAGS */ \
16770 @@ -470,6 +477,7 @@
16771 #define SERIAL_PORT_DFNS \
16772 ATLAS_SERIAL_PORT_DEFNS \
16773 AU1000_SERIAL_PORT_DEFNS \
16774 + BCM947XX_SERIAL_PORT_DEFNS \
16775 COBALT_SERIAL_PORT_DEFNS \
16776 DDB5477_SERIAL_PORT_DEFNS \
16777 EV96100_SERIAL_PORT_DEFNS \
16778 diff -urN linux.old/init/do_mounts.c linux.dev/init/do_mounts.c
16779 --- linux.old/init/do_mounts.c 2006-10-02 21:23:10.000000000 +0200
16780 +++ linux.dev/init/do_mounts.c 2006-10-02 21:19:59.000000000 +0200
16781 @@ -254,7 +254,13 @@
16782 { "ftlb", 0x2c08 },
16783 { "ftlc", 0x2c10 },
16784 { "ftld", 0x2c18 },
16785 +#if defined(CONFIG_MTD_BLOCK) || defined(CONFIG_MTD_BLOCK_RO)
16786 { "mtdblock", 0x1f00 },
16787 + { "mtdblock0",0x1f00 },
16788 + { "mtdblock1",0x1f01 },
16789 + { "mtdblock2",0x1f02 },
16790 + { "mtdblock3",0x1f03 },
16791 +#endif
16792 { "nb", 0x2b00 },
16793 { NULL, 0 }
16794 };
OpenWrt Source Repository