add a few missing exports
[openwrt/openwrt.git] / target / linux / brcm-2.4 / patches / 001-bcm47xx.patch
1 diff -urN linux.old/arch/mips/bcm947xx/bcmsrom.c linux.dev/arch/mips/bcm947xx/bcmsrom.c
2 --- linux.old/arch/mips/bcm947xx/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
3 +++ linux.dev/arch/mips/bcm947xx/bcmsrom.c 2006-10-02 21:19:59.000000000 +0200
4 @@ -0,0 +1,1213 @@
5 +/*
6 + * Misc useful routines to access NIC SROM/OTP .
7 + *
8 + * Copyright 2006, Broadcom Corporation
9 + * All Rights Reserved.
10 + *
11 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15 + * $Id: bcmsrom.c,v 1.1.1.14 2006/04/15 01:28:25 michael Exp $
16 + */
17 +
18 +#include <typedefs.h>
19 +#include <bcmdefs.h>
20 +#include <osl.h>
21 +#include <bcmutils.h>
22 +#include <bcmsrom.h>
23 +#include <bcmdevs.h>
24 +#include <bcmendian.h>
25 +#include <sbpcmcia.h>
26 +#include <pcicfg.h>
27 +#include <sbutils.h>
28 +#include <bcmnvram.h>
29 +
30 +/* debug/trace */
31 +#if defined(WLTEST)
32 +#define BS_ERROR(args) printf args
33 +#else
34 +#define BS_ERROR(args)
35 +#endif /* BCMDBG_ERR || WLTEST */
36 +
37 +#define VARS_MAX 4096 /* should be reduced */
38 +
39 +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
40 +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
41 +
42 +static int initvars_srom_pci(void *sbh, void *curmap, char **vars, uint *count);
43 +static int initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, uint *count);
44 +static int initvars_flash_sb(void *sbh, char **vars, uint *count);
45 +static int srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt, char **vars, uint *count);
46 +static int sprom_cmd_pcmcia(osl_t *osh, uint8 cmd);
47 +static int sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data);
48 +static int sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data);
49 +static int sprom_read_pci(osl_t *osh, uint16 *sprom, uint wordoff, uint16 *buf, uint nwords,
50 + bool check_crc);
51 +
52 +static int initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count);
53 +static int initvars_flash(osl_t *osh, char **vp, uint len, char *devpath);
54 +
55 +/*
56 + * Initialize local vars from the right source for this platform.
57 + * Return 0 on success, nonzero on error.
58 + */
59 +int
60 +srom_var_init(void *sbh, uint bustype, void *curmap, osl_t *osh, char **vars, uint *count)
61 +{
62 + ASSERT(bustype == BUSTYPE(bustype));
63 + if (vars == NULL || count == NULL)
64 + return (0);
65 +
66 + switch (BUSTYPE(bustype)) {
67 + case SB_BUS:
68 + case JTAG_BUS:
69 + return initvars_flash_sb(sbh, vars, count);
70 +
71 + case PCI_BUS:
72 + ASSERT(curmap); /* can not be NULL */
73 + return initvars_srom_pci(sbh, curmap, vars, count);
74 +
75 + case PCMCIA_BUS:
76 + return initvars_cis_pcmcia(sbh, osh, vars, count);
77 +
78 +
79 + default:
80 + ASSERT(0);
81 + }
82 + return (-1);
83 +}
84 +
85 +/* support only 16-bit word read from srom */
86 +int
87 +srom_read(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
88 +{
89 + void *srom;
90 + uint i, off, nw;
91 +
92 + ASSERT(bustype == BUSTYPE(bustype));
93 +
94 + /* check input - 16-bit access only */
95 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
96 + return 1;
97 +
98 + off = byteoff / 2;
99 + nw = nbytes / 2;
100 +
101 + if (BUSTYPE(bustype) == PCI_BUS) {
102 + if (!curmap)
103 + return 1;
104 + srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
105 + if (sprom_read_pci(osh, srom, off, buf, nw, FALSE))
106 + return 1;
107 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
108 + for (i = 0; i < nw; i++) {
109 + if (sprom_read_pcmcia(osh, (uint16)(off + i), (uint16*)(buf + i)))
110 + return 1;
111 + }
112 + } else {
113 + return 1;
114 + }
115 +
116 + return 0;
117 +}
118 +
119 +/* support only 16-bit word write into srom */
120 +int
121 +srom_write(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
122 +{
123 + uint16 *srom;
124 + uint i, nw, crc_range;
125 + uint16 image[SPROM_SIZE];
126 + uint8 crc;
127 + volatile uint32 val32;
128 +
129 + ASSERT(bustype == BUSTYPE(bustype));
130 +
131 + /* check input - 16-bit access only */
132 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
133 + return 1;
134 +
135 + /* Are we writing the whole thing at once? */
136 + if ((byteoff == 0) &&
137 + ((nbytes == SPROM_SIZE) ||
138 + (nbytes == (SPROM_CRC_RANGE * 2)) ||
139 + (nbytes == (SROM4_WORDS * 2)))) {
140 + crc_range = nbytes;
141 + bcopy((void*)buf, (void*)image, nbytes);
142 + nw = nbytes / 2;
143 + } else {
144 + if ((BUSTYPE(bustype) == PCMCIA_BUS) || (BUSTYPE(bustype) == SDIO_BUS))
145 + crc_range = SPROM_SIZE;
146 + else
147 + crc_range = SPROM_CRC_RANGE * 2; /* Tentative */
148 +
149 + nw = crc_range / 2;
150 + /* read first 64 words from srom */
151 + if (srom_read(bustype, curmap, osh, 0, crc_range, image))
152 + return 1;
153 + if (image[SROM4_SIGN] == SROM4_SIGNATURE) {
154 + crc_range = SROM4_WORDS;
155 + nw = crc_range / 2;
156 + if (srom_read(bustype, curmap, osh, 0, crc_range, image))
157 + return 1;
158 + }
159 + /* make changes */
160 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
161 + }
162 +
163 + /* calculate crc */
164 + htol16_buf(image, crc_range);
165 + crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
166 + ltoh16_buf(image, crc_range);
167 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
168 +
169 + if (BUSTYPE(bustype) == PCI_BUS) {
170 + srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
171 + /* enable writes to the SPROM */
172 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
173 + val32 |= SPROM_WRITEEN;
174 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
175 + bcm_mdelay(WRITE_ENABLE_DELAY);
176 + /* write srom */
177 + for (i = 0; i < nw; i++) {
178 + W_REG(osh, &srom[i], image[i]);
179 + bcm_mdelay(WRITE_WORD_DELAY);
180 + }
181 + /* disable writes to the SPROM */
182 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 &
183 + ~SPROM_WRITEEN);
184 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
185 + /* enable writes to the SPROM */
186 + if (sprom_cmd_pcmcia(osh, SROM_WEN))
187 + return 1;
188 + bcm_mdelay(WRITE_ENABLE_DELAY);
189 + /* write srom */
190 + for (i = 0; i < nw; i++) {
191 + sprom_write_pcmcia(osh, (uint16)(i), image[i]);
192 + bcm_mdelay(WRITE_WORD_DELAY);
193 + }
194 + /* disable writes to the SPROM */
195 + if (sprom_cmd_pcmcia(osh, SROM_WDS))
196 + return 1;
197 + } else {
198 + return 1;
199 + }
200 +
201 + bcm_mdelay(WRITE_ENABLE_DELAY);
202 + return 0;
203 +}
204 +
205 +
206 +static int
207 +srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt, char **vars, uint *count)
208 +{
209 + char eabuf[32];
210 + char *vp, *base;
211 + uint8 *cis, tup, tlen, sromrev = 1;
212 + int i, j;
213 + uint varsize;
214 + bool ag_init = FALSE;
215 + uint32 w32;
216 +
217 + ASSERT(vars);
218 + ASSERT(count);
219 +
220 + base = vp = MALLOC(osh, VARS_MAX);
221 + ASSERT(vp);
222 + if (!vp)
223 + return -2;
224 +
225 + while (ciscnt--) {
226 + cis = *pcis++;
227 + i = 0;
228 + do {
229 + tup = cis[i++];
230 + tlen = cis[i++];
231 + if ((i + tlen) >= CIS_SIZE)
232 + break;
233 +
234 + switch (tup) {
235 + case CISTPL_MANFID:
236 + vp += sprintf(vp, "manfid=%d", (cis[i + 1] << 8) + cis[i]);
237 + vp++;
238 + vp += sprintf(vp, "prodid=%d", (cis[i + 3] << 8) + cis[i + 2]);
239 + vp++;
240 + break;
241 +
242 + case CISTPL_FUNCE:
243 + switch (cis[i]) {
244 + case LAN_NID:
245 + ASSERT(cis[i + 1] == 6);
246 + bcm_ether_ntoa((struct ether_addr *)&cis[i + 2], eabuf);
247 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
248 + vp++;
249 + break;
250 + case 1: /* SDIO Extended Data */
251 + vp += sprintf(vp, "sdmaxblk=%d",
252 + (cis[i + 13] << 8) | cis[i + 12]);
253 + vp++;
254 + break;
255 + }
256 + break;
257 +
258 + case CISTPL_CFTABLE:
259 + vp += sprintf(vp, "regwindowsz=%d", (cis[i + 7] << 8) | cis[i + 6]);
260 + vp++;
261 + break;
262 +
263 + case CISTPL_BRCM_HNBU:
264 + switch (cis[i]) {
265 + case HNBU_SROMREV:
266 + sromrev = cis[i + 1];
267 + break;
268 +
269 + case HNBU_CHIPID:
270 + vp += sprintf(vp, "vendid=%d", (cis[i + 2] << 8) +
271 + cis[i + 1]);
272 + vp++;
273 + vp += sprintf(vp, "devid=%d", (cis[i + 4] << 8) +
274 + cis[i + 3]);
275 + vp++;
276 + if (tlen == 7) {
277 + vp += sprintf(vp, "chiprev=%d",
278 + (cis[i + 6] << 8) + cis[i + 5]);
279 + vp++;
280 + }
281 + break;
282 +
283 + case HNBU_BOARDREV:
284 + vp += sprintf(vp, "boardrev=%d", cis[i + 1]);
285 + vp++;
286 + break;
287 +
288 + case HNBU_AA:
289 + vp += sprintf(vp, "aa2g=%d", cis[i + 1]);
290 + vp++;
291 + break;
292 +
293 + case HNBU_AG:
294 + vp += sprintf(vp, "ag0=%d", cis[i + 1]);
295 + vp++;
296 + ag_init = TRUE;
297 + break;
298 +
299 + case HNBU_CC:
300 + ASSERT(sromrev == 1);
301 + vp += sprintf(vp, "cc=%d", cis[i + 1]);
302 + vp++;
303 + break;
304 +
305 + case HNBU_PAPARMS:
306 + if (tlen == 2) {
307 + ASSERT(sromrev == 1);
308 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 1]);
309 + vp++;
310 + } else if (tlen >= 9) {
311 + if (tlen == 10) {
312 + ASSERT(sromrev == 2);
313 + vp += sprintf(vp, "opo=%d", cis[i + 9]);
314 + vp++;
315 + } else
316 + ASSERT(tlen == 9);
317 +
318 + for (j = 0; j < 3; j++) {
319 + vp += sprintf(vp, "pa0b%d=%d", j,
320 + (cis[i + (j * 2) + 2] << 8) +
321 + cis[i + (j * 2) + 1]);
322 + vp++;
323 + }
324 + vp += sprintf(vp, "pa0itssit=%d", cis[i + 7]);
325 + vp++;
326 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 8]);
327 + vp++;
328 + } else
329 + ASSERT(tlen >= 9);
330 + break;
331 +
332 + case HNBU_OEM:
333 + ASSERT(sromrev == 1);
334 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
335 + cis[i + 1], cis[i + 2],
336 + cis[i + 3], cis[i + 4],
337 + cis[i + 5], cis[i + 6],
338 + cis[i + 7], cis[i + 8]);
339 + vp++;
340 + break;
341 +
342 + case HNBU_BOARDFLAGS:
343 + w32 = (cis[i + 2] << 8) + cis[i + 1];
344 + if (tlen == 5)
345 + w32 |= (cis[i + 4] << 24) + (cis[i + 3] << 16);
346 + vp += sprintf(vp, "boardflags=0x%x", w32);
347 + vp++;
348 + break;
349 +
350 + case HNBU_LEDS:
351 + if (cis[i + 1] != 0xff) {
352 + vp += sprintf(vp, "ledbh0=%d", cis[i + 1]);
353 + vp++;
354 + }
355 + if (cis[i + 2] != 0xff) {
356 + vp += sprintf(vp, "ledbh1=%d", cis[i + 2]);
357 + vp++;
358 + }
359 + if (cis[i + 3] != 0xff) {
360 + vp += sprintf(vp, "ledbh2=%d", cis[i + 3]);
361 + vp++;
362 + }
363 + if (cis[i + 4] != 0xff) {
364 + vp += sprintf(vp, "ledbh3=%d", cis[i + 4]);
365 + vp++;
366 + }
367 + break;
368 +
369 + case HNBU_CCODE:
370 + {
371 + char str[3];
372 + ASSERT(sromrev > 1);
373 + str[0] = cis[i + 1];
374 + str[1] = cis[i + 2];
375 + str[2] = 0;
376 + vp += sprintf(vp, "ccode=%s", str);
377 + vp++;
378 + vp += sprintf(vp, "cctl=0x%x", cis[i + 3]);
379 + vp++;
380 + break;
381 + }
382 +
383 + case HNBU_CCKPO:
384 + ASSERT(sromrev > 2);
385 + vp += sprintf(vp, "cckpo=0x%x",
386 + (cis[i + 2] << 8) | cis[i + 1]);
387 + vp++;
388 + break;
389 +
390 + case HNBU_OFDMPO:
391 + ASSERT(sromrev > 2);
392 + vp += sprintf(vp, "ofdmpo=0x%x",
393 + (cis[i + 4] << 24) |
394 + (cis[i + 3] << 16) |
395 + (cis[i + 2] << 8) |
396 + cis[i + 1]);
397 + vp++;
398 + break;
399 + }
400 + break;
401 +
402 + }
403 + i += tlen;
404 + } while (tup != 0xff);
405 + }
406 +
407 + /* Set the srom version */
408 + vp += sprintf(vp, "sromrev=%d", sromrev);
409 + vp++;
410 +
411 + /* if there is no antenna gain field, set default */
412 + if (ag_init == FALSE) {
413 + ASSERT(sromrev == 1);
414 + vp += sprintf(vp, "ag0=%d", 0xff);
415 + vp++;
416 + }
417 +
418 + /* final nullbyte terminator */
419 + *vp++ = '\0';
420 + varsize = (uint)(vp - base);
421 +
422 + ASSERT((vp - base) < VARS_MAX);
423 +
424 + if (varsize == VARS_MAX) {
425 + *vars = base;
426 + } else {
427 + vp = MALLOC(osh, varsize);
428 + ASSERT(vp);
429 + if (vp)
430 + bcopy(base, vp, varsize);
431 + MFREE(osh, base, VARS_MAX);
432 + *vars = vp;
433 + if (!vp) {
434 + *count = 0;
435 + return -2;
436 + }
437 + }
438 + *count = varsize;
439 +
440 + return (0);
441 +}
442 +
443 +
444 +/* set PCMCIA sprom command register */
445 +static int
446 +sprom_cmd_pcmcia(osl_t *osh, uint8 cmd)
447 +{
448 + uint8 status = 0;
449 + uint wait_cnt = 1000;
450 +
451 + /* write sprom command register */
452 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_CS, &cmd, 1);
453 +
454 + /* wait status */
455 + while (wait_cnt--) {
456 + OSL_PCMCIA_READ_ATTR(osh, SROM_CS, &status, 1);
457 + if (status & SROM_DONE)
458 + return 0;
459 + }
460 +
461 + return 1;
462 +}
463 +
464 +/* read a word from the PCMCIA srom */
465 +static int
466 +sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data)
467 +{
468 + uint8 addr_l, addr_h, data_l, data_h;
469 +
470 + addr_l = (uint8)((addr * 2) & 0xff);
471 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
472 +
473 + /* set address */
474 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
475 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
476 +
477 + /* do read */
478 + if (sprom_cmd_pcmcia(osh, SROM_READ))
479 + return 1;
480 +
481 + /* read data */
482 + data_h = data_l = 0;
483 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAH, &data_h, 1);
484 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAL, &data_l, 1);
485 +
486 + *data = (data_h << 8) | data_l;
487 + return 0;
488 +}
489 +
490 +/* write a word to the PCMCIA srom */
491 +static int
492 +sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data)
493 +{
494 + uint8 addr_l, addr_h, data_l, data_h;
495 +
496 + addr_l = (uint8)((addr * 2) & 0xff);
497 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
498 + data_l = (uint8)(data & 0xff);
499 + data_h = (uint8)((data >> 8) & 0xff);
500 +
501 + /* set address */
502 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
503 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
504 +
505 + /* write data */
506 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAH, &data_h, 1);
507 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAL, &data_l, 1);
508 +
509 + /* do write */
510 + return sprom_cmd_pcmcia(osh, SROM_WRITE);
511 +}
512 +
513 +/*
514 + * Read in and validate sprom.
515 + * Return 0 on success, nonzero on error.
516 + */
517 +static int
518 +sprom_read_pci(osl_t *osh, uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
519 +{
520 + int err = 0;
521 + uint i;
522 +
523 + /* read the sprom */
524 + for (i = 0; i < nwords; i++)
525 + buf[i] = R_REG(osh, &sprom[wordoff + i]);
526 +
527 + if (check_crc) {
528 + /* fixup the endianness so crc8 will pass */
529 + htol16_buf(buf, nwords * 2);
530 + if (hndcrc8((uint8*)buf, nwords * 2, CRC8_INIT_VALUE) != CRC8_GOOD_VALUE)
531 + err = 1;
532 + /* now correct the endianness of the byte array */
533 + ltoh16_buf(buf, nwords * 2);
534 + }
535 +
536 + return err;
537 +}
538 +
539 +/*
540 +* Create variable table from memory.
541 +* Return 0 on success, nonzero on error.
542 +*/
543 +static int
544 +initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count)
545 +{
546 + int c = (int)(end - start);
547 +
548 + /* do it only when there is more than just the null string */
549 + if (c > 1) {
550 + char *vp = MALLOC(osh, c);
551 + ASSERT(vp);
552 + if (!vp)
553 + return BCME_NOMEM;
554 + bcopy(start, vp, c);
555 + *vars = vp;
556 + *count = c;
557 + }
558 + else {
559 + *vars = NULL;
560 + *count = 0;
561 + }
562 +
563 + return 0;
564 +}
565 +
566 +/*
567 + * Find variables with <devpath> from flash. 'base' points to the beginning
568 + * of the table upon enter and to the end of the table upon exit when success.
569 + * Return 0 on success, nonzero on error.
570 + */
571 +static int
572 +initvars_flash(osl_t *osh, char **base, uint len, char *devpath)
573 +{
574 + char *vp = *base;
575 + char *flash;
576 + int err;
577 + char *s;
578 + uint l, dl, copy_len;
579 +
580 + /* allocate memory and read in flash */
581 + if (!(flash = MALLOC(osh, NVRAM_SPACE)))
582 + return BCME_NOMEM;
583 + if ((err = nvram_getall(flash, NVRAM_SPACE)))
584 + goto exit;
585 +
586 + /* grab vars with the <devpath> prefix in name */
587 + dl = strlen(devpath);
588 + for (s = flash; s && *s; s += l + 1) {
589 + l = strlen(s);
590 +
591 + /* skip non-matching variable */
592 + if (strncmp(s, devpath, dl))
593 + continue;
594 +
595 + /* is there enough room to copy? */
596 + copy_len = l - dl + 1;
597 + if (len < copy_len) {
598 + err = BCME_BUFTOOSHORT;
599 + goto exit;
600 + }
601 +
602 + /* no prefix, just the name=value */
603 + strcpy(vp, &s[dl]);
604 + vp += copy_len;
605 + len -= copy_len;
606 + }
607 +
608 + /* add null string as terminator */
609 + if (len < 1) {
610 + err = BCME_BUFTOOSHORT;
611 + goto exit;
612 + }
613 + *vp++ = '\0';
614 +
615 + *base = vp;
616 +
617 +exit: MFREE(osh, flash, NVRAM_SPACE);
618 + return err;
619 +}
620 +
621 +/*
622 + * Initialize nonvolatile variable table from flash.
623 + * Return 0 on success, nonzero on error.
624 + */
625 +static int
626 +initvars_flash_sb(void *sbh, char **vars, uint *count)
627 +{
628 + osl_t *osh = sb_osh(sbh);
629 + char devpath[SB_DEVPATH_BUFSZ];
630 + char *vp, *base;
631 + int err;
632 +
633 + ASSERT(vars);
634 + ASSERT(count);
635 +
636 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
637 + return err;
638 +
639 + base = vp = MALLOC(osh, VARS_MAX);
640 + ASSERT(vp);
641 + if (!vp)
642 + return BCME_NOMEM;
643 +
644 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
645 + goto err;
646 +
647 + err = initvars_table(osh, base, vp, vars, count);
648 +
649 +err: MFREE(osh, base, VARS_MAX);
650 + return err;
651 +}
652 +
653 +#ifdef WLTEST
654 +char mfgsromvars[256];
655 +char *defaultsromvars = "il0macaddr=00:11:22:33:44:51\0"
656 + "et0macaddr=00:11:22:33:44:52\0"
657 + "et1macaddr=00:11:22:33:44:53\0"
658 + "boardtype=0xffff\0"
659 + "boardrev=0x10\0"
660 + "boardflags=8\0"
661 + "sromrev=2\0"
662 + "aa2g=3";
663 +#define MFGSROM_DEFVARSLEN 147 /* default srom len */
664 +#endif /* WL_TEST */
665 +
666 +/*
667 + * Initialize nonvolatile variable table from sprom.
668 + * Return 0 on success, nonzero on error.
669 + */
670 +static int
671 +initvars_srom_pci(void *sbh, void *curmap, char **vars, uint *count)
672 +{
673 + uint16 w, *b;
674 + uint8 sromrev = 0;
675 + struct ether_addr ea;
676 + char eabuf[32];
677 + uint32 w32;
678 + int woff, i;
679 + char *vp, *base;
680 + osl_t *osh = sb_osh(sbh);
681 + bool flash = FALSE;
682 + char name[SB_DEVPATH_BUFSZ+16], *value;
683 + char devpath[SB_DEVPATH_BUFSZ];
684 + int err;
685 +
686 + /*
687 + * Apply CRC over SROM content regardless SROM is present or not,
688 + * and use variable <devpath>sromrev's existance in flash to decide
689 + * if we should return an error when CRC fails or read SROM variables
690 + * from flash.
691 + */
692 + b = MALLOC(osh, SROM_MAX);
693 + ASSERT(b);
694 + if (!b)
695 + return -2;
696 +
697 + err = sprom_read_pci(osh, (void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b,
698 + 64, TRUE);
699 + if (b[SROM4_SIGN] == SROM4_SIGNATURE) {
700 + /* sromrev >= 4, read more */
701 + err = sprom_read_pci(osh, (void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b, SROM4_WORDS, TRUE);
702 + sromrev = b[SROM4_WORDS - 1] & 0xff;
703 + } else if (err == 0) {
704 + /* srom is good and is rev < 4 */
705 + /* top word of sprom contains version and crc8 */
706 + sromrev = b[63] & 0xff;
707 + /* bcm4401 sroms misprogrammed */
708 + if (sromrev == 0x10)
709 + sromrev = 1;
710 + }
711 +
712 + if (err) {
713 +#ifdef WLTEST
714 + BS_ERROR(("SROM Crc Error, so see if we could use a default\n"));
715 + w32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
716 + if (w32 & SPROM_OTPIN_USE) {
717 + BS_ERROR(("srom crc failed with OTP, use default vars....\n"));
718 + vp = base = mfgsromvars;
719 + if (sb_chip(sbh) == BCM4311_CHIP_ID) {
720 + BS_ERROR(("setting the devid to be 4311\n"));
721 + vp += sprintf(vp, "devid=0x4311");
722 + vp++;
723 + }
724 + bcopy(defaultsromvars, vp, MFGSROM_DEFVARSLEN);
725 + vp += MFGSROM_DEFVARSLEN;
726 + goto varsdone;
727 + } else {
728 + BS_ERROR(("srom crc failed with SPROM....\n"));
729 +#endif /* WLTEST */
730 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
731 + return err;
732 + sprintf(name, "%ssromrev", devpath);
733 + if (!(value = getvar(NULL, name)))
734 + return (-1);
735 + sromrev = (uint8)bcm_strtoul(value, NULL, 0);
736 + flash = TRUE;
737 +#ifdef WLTEST
738 + }
739 +#endif /* WLTEST */
740 + }
741 +
742 + /* srom version check */
743 + if (sromrev > 4)
744 + return (-2);
745 +
746 + ASSERT(vars);
747 + ASSERT(count);
748 +
749 + base = vp = MALLOC(osh, VARS_MAX);
750 + ASSERT(vp);
751 + if (!vp)
752 + return -2;
753 +
754 + /* read variables from flash */
755 + if (flash) {
756 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
757 + goto err;
758 + goto varsdone;
759 + }
760 +
761 + vp += sprintf(vp, "sromrev=%d", sromrev);
762 + vp++;
763 +
764 + if (sromrev >= 4) {
765 + uint path, pathbase;
766 + const uint pathbases[MAX_PATH] = {SROM4_PATH0, SROM4_PATH1,
767 + SROM4_PATH2, SROM4_PATH3};
768 +
769 + vp += sprintf(vp, "boardrev=%d", b[SROM4_BREV]);
770 + vp++;
771 +
772 + vp += sprintf(vp, "boardflags=%d", (b[SROM4_BFL1] << 16) | b[SROM4_BFL0]);
773 + vp++;
774 +
775 + vp += sprintf(vp, "boardflags2=%d", (b[SROM4_BFL3] << 16) | b[SROM4_BFL2]);
776 + vp++;
777 +
778 + /* The macaddr */
779 + ea.octet[0] = (b[SROM4_MACHI] >> 8) & 0xff;
780 + ea.octet[1] = b[SROM4_MACHI] & 0xff;
781 + ea.octet[2] = (b[SROM4_MACMID] >> 8) & 0xff;
782 + ea.octet[3] = b[SROM4_MACMID] & 0xff;
783 + ea.octet[4] = (b[SROM4_MACLO] >> 8) & 0xff;
784 + ea.octet[5] = b[SROM4_MACLO] & 0xff;
785 + bcm_ether_ntoa(&ea, eabuf);
786 + vp += sprintf(vp, "macaddr=%s", eabuf);
787 + vp++;
788 +
789 + w = b[SROM4_CCODE];
790 + if (w == 0)
791 + vp += sprintf(vp, "ccode=");
792 + else
793 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
794 + vp++;
795 + vp += sprintf(vp, "regrev=%d", b[SROM4_REGREV]);
796 + vp++;
797 +
798 + w = b[SROM4_LEDBH10];
799 + if ((w != 0) && (w != 0xffff)) {
800 + /* ledbh0 */
801 + vp += sprintf(vp, "ledbh0=%d", (w & 0xff));
802 + vp++;
803 +
804 + /* ledbh1 */
805 + vp += sprintf(vp, "ledbh1=%d", (w >> 8) & 0xff);
806 + vp++;
807 + }
808 + w = b[SROM4_LEDBH32];
809 + if ((w != 0) && (w != 0xffff)) {
810 + /* ledbh2 */
811 + vp += sprintf(vp, "ledbh2=%d", w & 0xff);
812 + vp++;
813 +
814 + /* ledbh3 */
815 + vp += sprintf(vp, "ledbh3=%d", (w >> 8) & 0xff);
816 + vp++;
817 + }
818 + /* LED Powersave duty cycle (oncount >> 24) (offcount >> 8) */
819 + if (w != 0xffff) {
820 + w = b[SROM4_LEDDC];
821 + w32 = ((uint32)((unsigned char)(w >> 8) & 0xff) << 24) | /* oncount */
822 + ((uint32)((unsigned char)(w & 0xff)) << 8); /* offcount */
823 + vp += sprintf(vp, "leddc=%d", w32);
824 + vp++;
825 + }
826 +
827 + w = b[SROM4_AA];
828 + vp += sprintf(vp, "aa2g=%d", w & SROM4_AA2G_MASK);
829 + vp++;
830 + vp += sprintf(vp, "aa5g=%d", w >> SROM4_AA5G_SHIFT);
831 + vp++;
832 +
833 + w = b[SROM4_AG10];
834 + vp += sprintf(vp, "ag0=%d", w & 0xff);
835 + vp++;
836 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
837 + vp++;
838 + w = b[SROM4_AG32];
839 + vp += sprintf(vp, "ag2=%d", w & 0xff);
840 + vp++;
841 + vp += sprintf(vp, "ag3=%d", (w >> 8) & 0xff);
842 + vp++;
843 +
844 + /* Fixed power indices when power control is disabled */
845 + for (i = 0; i < 2; i++) {
846 + w = b[SROM4_TXPID2G + i];
847 + vp += sprintf(vp, "txpid2ga%d=%d", 2 * i, w & 0xff);
848 + vp++;
849 + vp += sprintf(vp, "txpid2ga%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
850 + vp++;
851 + w = b[SROM4_TXPID5G + i];
852 + vp += sprintf(vp, "txpid5ga%d=%d", 2 * i, w & 0xff);
853 + vp++;
854 + vp += sprintf(vp, "txpid5ga%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
855 + vp++;
856 + w = b[SROM4_TXPID5GL + i];
857 + vp += sprintf(vp, "txpid5gla%d=%d", 2 * i, w & 0xff);
858 + vp++;
859 + vp += sprintf(vp, "txpid5gla%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
860 + vp++;
861 + w = b[SROM4_TXPID5GH + i];
862 + vp += sprintf(vp, "txpid5gha%d=%d", 2 * i, w & 0xff);
863 + vp++;
864 + vp += sprintf(vp, "txpid5gha%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
865 + vp++;
866 + }
867 +
868 + /* Per path variables */
869 + for (path = 0; path < MAX_PATH; path++) {
870 + pathbase = pathbases[path];
871 + w = b[pathbase + SROM4_2G_ITT_MAXP];
872 + vp += sprintf(vp, "itt2ga%d=%d", path, w >> B2G_ITT_SHIFT);
873 + vp++;
874 + vp += sprintf(vp, "maxp2ga%d=%d", path, w & B2G_MAXP_MASK);
875 + vp++;
876 +
877 + for (i = 0; i < 4; i++) {
878 + vp += sprintf(vp, "pa2gw%da%d=%d", i, path,
879 + b[pathbase + SROM4_2G_PA + i]);
880 + vp++;
881 + }
882 +
883 + w = b[pathbase + SROM4_5G_ITT_MAXP];
884 + vp += sprintf(vp, "itt5ga%d=%d", path, w >> B5G_ITT_SHIFT);
885 + vp++;
886 + vp += sprintf(vp, "maxp5ga%d=%d", path, w & B5G_MAXP_MASK);
887 + vp++;
888 +
889 + w = b[pathbase + SROM4_5GLH_MAXP];
890 + vp += sprintf(vp, "maxp5lga%d=%d", path, w >> B5GL_MAXP_SHIFT);
891 + vp++;
892 + vp += sprintf(vp, "maxp5gha%d=%d", path, w & B5GH_MAXP_MASK);
893 + vp++;
894 +
895 + for (i = 0; i < 4; i++) {
896 + vp += sprintf(vp, "pa5gw%da%d=%d", i, path,
897 + b[pathbase + SROM4_5G_PA + i]);
898 + vp++;
899 + vp += sprintf(vp, "pa5glw%da%d=%d", i, path,
900 + b[pathbase + SROM4_5GL_PA + i]);
901 + vp++;
902 + vp += sprintf(vp, "pa5hgw%da%d=%d", i, path,
903 + b[pathbase + SROM4_5GH_PA + i]);
904 + vp++;
905 + }
906 + }
907 +
908 + vp += sprintf(vp, "cck2gpo=%d", b[SROM4_2G_CCKPO]);
909 + vp++;
910 +
911 + w32 = ((uint32)b[SROM4_2G_OFDMPO + 1] << 16) | b[SROM4_2G_OFDMPO];
912 + vp += sprintf(vp, "ofdm2gpo=%d", w32);
913 + vp++;
914 +
915 + w32 = ((uint32)b[SROM4_5G_OFDMPO + 1] << 16) | b[SROM4_5G_OFDMPO];
916 + vp += sprintf(vp, "ofdm5gpo=%d", w32);
917 + vp++;
918 +
919 + w32 = ((uint32)b[SROM4_5GL_OFDMPO + 1] << 16) | b[SROM4_5GL_OFDMPO];
920 + vp += sprintf(vp, "ofdm5glpo=%d", w32);
921 + vp++;
922 +
923 + w32 = ((uint32)b[SROM4_5GH_OFDMPO + 1] << 16) | b[SROM4_5GH_OFDMPO];
924 + vp += sprintf(vp, "ofdm5ghpo=%d", w32);
925 + vp++;
926 +
927 + for (i = 0; i < 8; i++) {
928 + vp += sprintf(vp, "mcs2gpo%d=%d", i, b[SROM4_2G_MCSPO]);
929 + vp++;
930 + vp += sprintf(vp, "mcs5gpo%d=%d", i, b[SROM4_5G_MCSPO]);
931 + vp++;
932 + vp += sprintf(vp, "mcs5glpo%d=%d", i, b[SROM4_5GL_MCSPO]);
933 + vp++;
934 + vp += sprintf(vp, "mcs5ghpo%d=%d", i, b[SROM4_5GH_MCSPO]);
935 + vp++;
936 + }
937 +
938 + vp += sprintf(vp, "ccdpo%d=%d", i, b[SROM4_CCDPO]);
939 + vp++;
940 + vp += sprintf(vp, "stbcpo%d=%d", i, b[SROM4_STBCPO]);
941 + vp++;
942 + vp += sprintf(vp, "bw40po%d=%d", i, b[SROM4_BW40PO]);
943 + vp++;
944 + vp += sprintf(vp, "bwduppo%d=%d", i, b[SROM4_BWDUPPO]);
945 + vp++;
946 +
947 + goto done;
948 + }
949 + if (sromrev >= 3) {
950 + /* New section takes over the 3th hardware function space */
951 +
952 + /* Words 22+23 are 11a (mid) ofdm power offsets */
953 + w32 = ((uint32)b[23] << 16) | b[22];
954 + vp += sprintf(vp, "ofdmapo=%d", w32);
955 + vp++;
956 +
957 + /* Words 24+25 are 11a (low) ofdm power offsets */
958 + w32 = ((uint32)b[25] << 16) | b[24];
959 + vp += sprintf(vp, "ofdmalpo=%d", w32);
960 + vp++;
961 +
962 + /* Words 26+27 are 11a (high) ofdm power offsets */
963 + w32 = ((uint32)b[27] << 16) | b[26];
964 + vp += sprintf(vp, "ofdmahpo=%d", w32);
965 + vp++;
966 +
967 + /* LED Powersave duty cycle (oncount >> 24) (offcount >> 8) */
968 + w32 = ((uint32)((unsigned char)(b[21] >> 8) & 0xff) << 24) | /* oncount */
969 + ((uint32)((unsigned char)(b[21] & 0xff)) << 8); /* offcount */
970 + vp += sprintf(vp, "leddc=%d", w32);
971 +
972 + vp++;
973 + }
974 +
975 + if (sromrev >= 2) {
976 + /* New section takes over the 4th hardware function space */
977 +
978 + /* Word 29 is max power 11a high/low */
979 + w = b[29];
980 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
981 + vp++;
982 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
983 + vp++;
984 +
985 + /* Words 30-32 set the 11alow pa settings,
986 + * 33-35 are the 11ahigh ones.
987 + */
988 + for (i = 0; i < 3; i++) {
989 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
990 + vp++;
991 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
992 + vp++;
993 + }
994 + w = b[59];
995 + if (w == 0)
996 + vp += sprintf(vp, "ccode=");
997 + else
998 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
999 + vp++;
1000 +
1001 + }
1002 +
1003 + /* parameter section of sprom starts at byte offset 72 */
1004 + woff = 72/2;
1005 +
1006 + /* first 6 bytes are il0macaddr */
1007 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1008 + ea.octet[1] = b[woff] & 0xff;
1009 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1010 + ea.octet[3] = b[woff+1] & 0xff;
1011 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1012 + ea.octet[5] = b[woff+2] & 0xff;
1013 + woff += 3;
1014 + bcm_ether_ntoa(&ea, eabuf);
1015 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
1016 + vp++;
1017 +
1018 + /* next 6 bytes are et0macaddr */
1019 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1020 + ea.octet[1] = b[woff] & 0xff;
1021 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1022 + ea.octet[3] = b[woff+1] & 0xff;
1023 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1024 + ea.octet[5] = b[woff+2] & 0xff;
1025 + woff += 3;
1026 + bcm_ether_ntoa(&ea, eabuf);
1027 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
1028 + vp++;
1029 +
1030 + /* next 6 bytes are et1macaddr */
1031 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1032 + ea.octet[1] = b[woff] & 0xff;
1033 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1034 + ea.octet[3] = b[woff+1] & 0xff;
1035 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1036 + ea.octet[5] = b[woff+2] & 0xff;
1037 + woff += 3;
1038 + bcm_ether_ntoa(&ea, eabuf);
1039 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
1040 + vp++;
1041 +
1042 + /*
1043 + * Enet phy settings one or two singles or a dual
1044 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
1045 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
1046 + * Bit 14 : Mdio for enet0
1047 + * Bit 15 : Mdio for enet1
1048 + */
1049 + w = b[woff];
1050 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
1051 + vp++;
1052 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
1053 + vp++;
1054 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
1055 + vp++;
1056 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
1057 + vp++;
1058 +
1059 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
1060 + w = b[46];
1061 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
1062 + vp++;
1063 +
1064 + if (sromrev > 1)
1065 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
1066 + else
1067 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
1068 + vp++;
1069 +
1070 + vp += sprintf(vp, "aa2g=%d", (w >> 12) & 0x3);
1071 + vp++;
1072 +
1073 + vp += sprintf(vp, "aa5g=%d", (w >> 14) & 0x3);
1074 + vp++;
1075 +
1076 + /* Words 47-49 set the (wl) pa settings */
1077 + woff = 47;
1078 +
1079 + for (i = 0; i < 3; i++) {
1080 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
1081 + vp++;
1082 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
1083 + vp++;
1084 + }
1085 +
1086 + /*
1087 + * Words 50-51 set the customer-configured wl led behavior.
1088 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
1089 + * LED behavior values defined in wlioctl.h .
1090 + */
1091 + w = b[50];
1092 + if ((w != 0) && (w != 0xffff)) {
1093 + /* ledbh0 */
1094 + vp += sprintf(vp, "ledbh0=%d", (w & 0xff));
1095 + vp++;
1096 +
1097 + /* ledbh1 */
1098 + vp += sprintf(vp, "ledbh1=%d", (w >> 8) & 0xff);
1099 + vp++;
1100 + }
1101 + w = b[51];
1102 + if ((w != 0) && (w != 0xffff)) {
1103 + /* ledbh2 */
1104 + vp += sprintf(vp, "ledbh2=%d", w & 0xff);
1105 + vp++;
1106 +
1107 + /* ledbh */
1108 + vp += sprintf(vp, "ledbh3=%d", (w >> 8) & 0xff);
1109 + vp++;
1110 + }
1111 +
1112 + /* Word 52 is max power 0/1 */
1113 + w = b[52];
1114 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
1115 + vp++;
1116 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
1117 + vp++;
1118 +
1119 + /* Word 56 is idle tssi target 0/1 */
1120 + w = b[56];
1121 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
1122 + vp++;
1123 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
1124 + vp++;
1125 +
1126 + /* Word 57 is boardflags, if not programmed make it zero */
1127 + w32 = (uint32)b[57];
1128 + if (w32 == 0xffff) w32 = 0;
1129 + if (sromrev > 1) {
1130 + /* Word 28 is the high bits of boardflags */
1131 + w32 |= (uint32)b[28] << 16;
1132 + }
1133 + vp += sprintf(vp, "boardflags=%d", w32);
1134 + vp++;
1135 +
1136 + /* Word 58 is antenna gain 0/1 */
1137 + w = b[58];
1138 + vp += sprintf(vp, "ag0=%d", w & 0xff);
1139 + vp++;
1140 +
1141 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
1142 + vp++;
1143 +
1144 + if (sromrev == 1) {
1145 + /* set the oem string */
1146 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
1147 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
1148 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
1149 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
1150 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
1151 + vp++;
1152 + } else if (sromrev == 2) {
1153 + /* Word 60 OFDM tx power offset from CCK level */
1154 + /* OFDM Power Offset - opo */
1155 + vp += sprintf(vp, "opo=%d", b[60] & 0xff);
1156 + vp++;
1157 + } else {
1158 + /* Word 60: cck power offsets */
1159 + vp += sprintf(vp, "cckpo=%d", b[60]);
1160 + vp++;
1161 +
1162 + /* Words 61+62: 11g ofdm power offsets */
1163 + w32 = ((uint32)b[62] << 16) | b[61];
1164 + vp += sprintf(vp, "ofdmgpo=%d", w32);
1165 + vp++;
1166 + }
1167 +
1168 + /* final nullbyte terminator */
1169 +done: *vp++ = '\0';
1170 +
1171 + ASSERT((vp - base) <= VARS_MAX);
1172 +
1173 +varsdone:
1174 + err = initvars_table(osh, base, vp, vars, count);
1175 +
1176 +err:
1177 +#ifdef WLTEST
1178 + if (base != mfgsromvars)
1179 +#endif
1180 + MFREE(osh, base, VARS_MAX);
1181 + MFREE(osh, b, SROM_MAX);
1182 + return err;
1183 +}
1184 +
1185 +/*
1186 + * Read the cis and call parsecis to initialize the vars.
1187 + * Return 0 on success, nonzero on error.
1188 + */
1189 +static int
1190 +initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, uint *count)
1191 +{
1192 + uint8 *cis = NULL;
1193 + int rc;
1194 + uint data_sz;
1195 +
1196 + data_sz = (sb_pcmciarev(sbh) == 1) ? (SPROM_SIZE * 2) : CIS_SIZE;
1197 +
1198 + if ((cis = MALLOC(osh, data_sz)) == NULL)
1199 + return (-2);
1200 +
1201 + if (sb_pcmciarev(sbh) == 1) {
1202 + if (srom_read(PCMCIA_BUS, (void *)NULL, osh, 0, data_sz, (uint16 *)cis)) {
1203 + MFREE(osh, cis, data_sz);
1204 + return (-1);
1205 + }
1206 + /* fix up endianess for 16-bit data vs 8-bit parsing */
1207 + ltoh16_buf((uint16 *)cis, data_sz);
1208 + } else
1209 + OSL_PCMCIA_READ_ATTR(osh, 0, cis, data_sz);
1210 +
1211 + rc = srom_parsecis(osh, &cis, 1, vars, count);
1212 +
1213 + MFREE(osh, cis, data_sz);
1214 +
1215 + return (rc);
1216 +}
1217 +
1218 diff -urN linux.old/arch/mips/bcm947xx/bcmutils.c linux.dev/arch/mips/bcm947xx/bcmutils.c
1219 --- linux.old/arch/mips/bcm947xx/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
1220 +++ linux.dev/arch/mips/bcm947xx/bcmutils.c 2006-10-02 21:19:59.000000000 +0200
1221 @@ -0,0 +1,247 @@
1222 +/*
1223 + * Misc useful OS-independent routines.
1224 + *
1225 + * Copyright 2006, Broadcom Corporation
1226 + * All Rights Reserved.
1227 + *
1228 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1229 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1230 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1231 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1232 + * $Id: bcmutils.c,v 1.1.1.12 2006/02/27 03:43:16 honor Exp $
1233 + */
1234 +
1235 +#include <typedefs.h>
1236 +#include <bcmdefs.h>
1237 +#include <stdarg.h>
1238 +#include <bcmutils.h>
1239 +#include <osl.h>
1240 +#include <sbutils.h>
1241 +#include <bcmnvram.h>
1242 +#include <bcmendian.h>
1243 +#include <bcmdevs.h>
1244 +
1245 +unsigned char bcm_ctype[] = {
1246 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
1247 + _BCM_C, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C,
1248 + _BCM_C, /* 8-15 */
1249 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
1250 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
1251 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
1252 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
1253 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
1254 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
1255 + _BCM_P, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X,
1256 + _BCM_U|_BCM_X, _BCM_U, /* 64-71 */
1257 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
1258 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
1259 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
1260 + _BCM_P, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X,
1261 + _BCM_L|_BCM_X, _BCM_L, /* 96-103 */
1262 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
1263 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
1264 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
1265 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 128-143 */
1266 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 144-159 */
1267 + _BCM_S|_BCM_SP, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
1268 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, /* 160-175 */
1269 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
1270 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, /* 176-191 */
1271 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U,
1272 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, /* 192-207 */
1273 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_P, _BCM_U, _BCM_U, _BCM_U,
1274 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_L, /* 208-223 */
1275 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L,
1276 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, /* 224-239 */
1277 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_P, _BCM_L, _BCM_L, _BCM_L,
1278 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L /* 240-255 */
1279 +};
1280 +
1281 +
1282 +ulong
1283 +bcm_strtoul(char *cp, char **endp, uint base)
1284 +{
1285 + ulong result, value;
1286 + bool minus;
1287 +
1288 + minus = FALSE;
1289 +
1290 + while (bcm_isspace(*cp))
1291 + cp++;
1292 +
1293 + if (cp[0] == '+')
1294 + cp++;
1295 + else if (cp[0] == '-') {
1296 + minus = TRUE;
1297 + cp++;
1298 + }
1299 +
1300 + if (base == 0) {
1301 + if (cp[0] == '0') {
1302 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
1303 + base = 16;
1304 + cp = &cp[2];
1305 + } else {
1306 + base = 8;
1307 + cp = &cp[1];
1308 + }
1309 + } else
1310 + base = 10;
1311 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
1312 + cp = &cp[2];
1313 + }
1314 +
1315 + result = 0;
1316 +
1317 + while (bcm_isxdigit(*cp) &&
1318 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
1319 + result = result*base + value;
1320 + cp++;
1321 + }
1322 +
1323 + if (minus)
1324 + result = (ulong)(result * -1);
1325 +
1326 + if (endp)
1327 + *endp = (char *)cp;
1328 +
1329 + return (result);
1330 +}
1331 +
1332 +uchar
1333 +bcm_toupper(uchar c)
1334 +{
1335 + if (bcm_islower(c))
1336 + c -= 'a'-'A';
1337 + return (c);
1338 +}
1339 +
1340 +char*
1341 +bcm_ether_ntoa(struct ether_addr *ea, char *buf)
1342 +{
1343 + sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x",
1344 + ea->octet[0]&0xff, ea->octet[1]&0xff, ea->octet[2]&0xff,
1345 + ea->octet[3]&0xff, ea->octet[4]&0xff, ea->octet[5]&0xff);
1346 + return (buf);
1347 +}
1348 +
1349 +
1350 +/*
1351 + * Search the name=value vars for a specific one and return its value.
1352 + * Returns NULL if not found.
1353 + */
1354 +char*
1355 +getvar(char *vars, char *name)
1356 +{
1357 + char *s;
1358 + int len;
1359 +
1360 + len = strlen(name);
1361 +
1362 + /* first look in vars[] */
1363 + for (s = vars; s && *s;) {
1364 + /* CSTYLED */
1365 + if ((memcmp(s, name, len) == 0) && (s[len] == '='))
1366 + return (&s[len+1]);
1367 +
1368 + while (*s++)
1369 + ;
1370 + }
1371 +
1372 + /* then query nvram */
1373 + return (nvram_get(name));
1374 +}
1375 +
1376 +/*
1377 + * Search the vars for a specific one and return its value as
1378 + * an integer. Returns 0 if not found.
1379 + */
1380 +int
1381 +getintvar(char *vars, char *name)
1382 +{
1383 + char *val;
1384 +
1385 + if ((val = getvar(vars, name)) == NULL)
1386 + return (0);
1387 +
1388 + return (bcm_strtoul(val, NULL, 0));
1389 +}
1390 +
1391 +
1392 +/*******************************************************************************
1393 + * crc8
1394 + *
1395 + * Computes a crc8 over the input data using the polynomial:
1396 + *
1397 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
1398 + *
1399 + * The caller provides the initial value (either CRC8_INIT_VALUE
1400 + * or the previous returned value) to allow for processing of
1401 + * discontiguous blocks of data. When generating the CRC the
1402 + * caller is responsible for complementing the final return value
1403 + * and inserting it into the byte stream. When checking, a final
1404 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
1405 + *
1406 + * Reference: Dallas Semiconductor Application Note 27
1407 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
1408 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
1409 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
1410 + *
1411 + * ****************************************************************************
1412 + */
1413 +
1414 +static uint8 crc8_table[256] = {
1415 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
1416 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
1417 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
1418 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
1419 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
1420 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
1421 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
1422 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
1423 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
1424 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
1425 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
1426 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
1427 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
1428 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
1429 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
1430 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
1431 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
1432 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
1433 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
1434 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
1435 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
1436 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
1437 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
1438 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
1439 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
1440 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
1441 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
1442 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
1443 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
1444 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
1445 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
1446 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
1447 +};
1448 +
1449 +#define CRC_INNER_LOOP(n, c, x) \
1450 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
1451 +
1452 +uint8
1453 +hndcrc8(
1454 + uint8 *pdata, /* pointer to array of data to process */
1455 + uint nbytes, /* number of input data bytes to process */
1456 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
1457 +)
1458 +{
1459 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
1460 + * to avoid the undefined and unnecessary (uint8 >> 8) operation.
1461 + */
1462 + while (nbytes-- > 0)
1463 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
1464 +
1465 + return crc;
1466 +}
1467 +
1468 +
1469 diff -urN linux.old/arch/mips/bcm947xx/cfe_env.c linux.dev/arch/mips/bcm947xx/cfe_env.c
1470 --- linux.old/arch/mips/bcm947xx/cfe_env.c 1970-01-01 01:00:00.000000000 +0100
1471 +++ linux.dev/arch/mips/bcm947xx/cfe_env.c 2006-10-02 21:19:59.000000000 +0200
1472 @@ -0,0 +1,234 @@
1473 +/*
1474 + * NVRAM variable manipulation (Linux kernel half)
1475 + *
1476 + * Copyright 2001-2003, Broadcom Corporation
1477 + * All Rights Reserved.
1478 + *
1479 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1480 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1481 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1482 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1483 + *
1484 + * $Id$
1485 + */
1486 +
1487 +#include <linux/config.h>
1488 +#include <linux/init.h>
1489 +#include <linux/module.h>
1490 +#include <linux/kernel.h>
1491 +#include <linux/string.h>
1492 +#include <asm/io.h>
1493 +#include <asm/uaccess.h>
1494 +
1495 +#include <typedefs.h>
1496 +#include <osl.h>
1497 +#include <bcmendian.h>
1498 +#include <bcmutils.h>
1499 +
1500 +#define NVRAM_SIZE (0x1ff0)
1501 +static char _nvdata[NVRAM_SIZE] __initdata;
1502 +static char _valuestr[256] __initdata;
1503 +
1504 +/*
1505 + * TLV types. These codes are used in the "type-length-value"
1506 + * encoding of the items stored in the NVRAM device (flash or EEPROM)
1507 + *
1508 + * The layout of the flash/nvram is as follows:
1509 + *
1510 + * <type> <length> <data ...> <type> <length> <data ...> <type_end>
1511 + *
1512 + * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
1513 + * The "length" field marks the length of the data section, not
1514 + * including the type and length fields.
1515 + *
1516 + * Environment variables are stored as follows:
1517 + *
1518 + * <type_env> <length> <flags> <name> = <value>
1519 + *
1520 + * If bit 0 (low bit) is set, the length is an 8-bit value.
1521 + * If bit 0 (low bit) is clear, the length is a 16-bit value
1522 + *
1523 + * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
1524 + * indicates the size of the length field.
1525 + *
1526 + * Flags are from the constants below:
1527 + *
1528 + */
1529 +#define ENV_LENGTH_16BITS 0x00 /* for low bit */
1530 +#define ENV_LENGTH_8BITS 0x01
1531 +
1532 +#define ENV_TYPE_USER 0x80
1533 +
1534 +#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
1535 +#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
1536 +
1537 +/*
1538 + * The actual TLV types we support
1539 + */
1540 +
1541 +#define ENV_TLV_TYPE_END 0x00
1542 +#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
1543 +
1544 +/*
1545 + * Environment variable flags
1546 + */
1547 +
1548 +#define ENV_FLG_NORMAL 0x00 /* normal read/write */
1549 +#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
1550 +#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
1551 +
1552 +#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
1553 +#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
1554 +
1555 +
1556 +/* *********************************************************************
1557 + * _nvram_read(buffer,offset,length)
1558 + *
1559 + * Read data from the NVRAM device
1560 + *
1561 + * Input parameters:
1562 + * buffer - destination buffer
1563 + * offset - offset of data to read
1564 + * length - number of bytes to read
1565 + *
1566 + * Return value:
1567 + * number of bytes read, or <0 if error occured
1568 + ********************************************************************* */
1569 +static int
1570 +_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
1571 +{
1572 + int i;
1573 + if (offset > NVRAM_SIZE)
1574 + return -1;
1575 +
1576 + for ( i = 0; i < length; i++) {
1577 + buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
1578 + }
1579 + return length;
1580 +}
1581 +
1582 +
1583 +static char*
1584 +_strnchr(const char *dest,int c,size_t cnt)
1585 +{
1586 + while (*dest && (cnt > 0)) {
1587 + if (*dest == c) return (char *) dest;
1588 + dest++;
1589 + cnt--;
1590 + }
1591 + return NULL;
1592 +}
1593 +
1594 +
1595 +
1596 +/*
1597 + * Core support API: Externally visible.
1598 + */
1599 +
1600 +/*
1601 + * Get the value of an NVRAM variable
1602 + * @param name name of variable to get
1603 + * @return value of variable or NULL if undefined
1604 + */
1605 +
1606 +char*
1607 +cfe_env_get(unsigned char *nv_buf, char* name)
1608 +{
1609 + int size;
1610 + unsigned char *buffer;
1611 + unsigned char *ptr;
1612 + unsigned char *envval;
1613 + unsigned int reclen;
1614 + unsigned int rectype;
1615 + int offset;
1616 + int flg;
1617 +
1618 + size = NVRAM_SIZE;
1619 + buffer = &_nvdata[0];
1620 +
1621 + ptr = buffer;
1622 + offset = 0;
1623 +
1624 + /* Read the record type and length */
1625 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1626 + goto error;
1627 + }
1628 +
1629 + while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
1630 +
1631 + /* Adjust pointer for TLV type */
1632 + rectype = *(ptr);
1633 + offset++;
1634 + size--;
1635 +
1636 + /*
1637 + * Read the length. It can be either 1 or 2 bytes
1638 + * depending on the code
1639 + */
1640 + if (rectype & ENV_LENGTH_8BITS) {
1641 + /* Read the record type and length - 8 bits */
1642 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1643 + goto error;
1644 + }
1645 + reclen = *(ptr);
1646 + size--;
1647 + offset++;
1648 + }
1649 + else {
1650 + /* Read the record type and length - 16 bits, MSB first */
1651 + if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
1652 + goto error;
1653 + }
1654 + reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
1655 + size -= 2;
1656 + offset += 2;
1657 + }
1658 +
1659 + if (reclen > size)
1660 + break; /* should not happen, bad NVRAM */
1661 +
1662 + switch (rectype) {
1663 + case ENV_TLV_TYPE_ENV:
1664 + /* Read the TLV data */
1665 + if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
1666 + goto error;
1667 + flg = *ptr++;
1668 + envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
1669 + if (envval) {
1670 + *envval++ = '\0';
1671 + memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
1672 + _valuestr[(reclen-1)-(envval-ptr)] = '\0';
1673 +#if 0
1674 + printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
1675 +#endif
1676 + if(!strcmp(ptr, name)){
1677 + return _valuestr;
1678 + }
1679 + if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
1680 + return _valuestr;
1681 + }
1682 + break;
1683 +
1684 + default:
1685 + /* Unknown TLV type, skip it. */
1686 + break;
1687 + }
1688 +
1689 + /*
1690 + * Advance to next TLV
1691 + */
1692 +
1693 + size -= (int)reclen;
1694 + offset += reclen;
1695 +
1696 + /* Read the next record type */
1697 + ptr = buffer;
1698 + if (_nvram_read(nv_buf, ptr,offset,1) != 1)
1699 + goto error;
1700 + }
1701 +
1702 +error:
1703 + return NULL;
1704 +
1705 +}
1706 +
1707 diff -urN linux.old/arch/mips/bcm947xx/compressed/Makefile linux.dev/arch/mips/bcm947xx/compressed/Makefile
1708 --- linux.old/arch/mips/bcm947xx/compressed/Makefile 1970-01-01 01:00:00.000000000 +0100
1709 +++ linux.dev/arch/mips/bcm947xx/compressed/Makefile 2006-10-02 21:19:59.000000000 +0200
1710 @@ -0,0 +1,33 @@
1711 +#
1712 +# Makefile for Broadcom BCM947XX boards
1713 +#
1714 +# Copyright 2001-2003, Broadcom Corporation
1715 +# All Rights Reserved.
1716 +#
1717 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1718 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1719 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1720 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1721 +#
1722 +# $Id: Makefile,v 1.2 2005/04/02 12:12:57 wbx Exp $
1723 +#
1724 +
1725 +OBJCOPY_ARGS = -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
1726 +SYSTEM ?= $(TOPDIR)/vmlinux
1727 +
1728 +all: vmlinuz
1729 +
1730 +# Don't build dependencies, this may die if $(CC) isn't gcc
1731 +dep:
1732 +
1733 +# Create a gzipped version named vmlinuz for compatibility
1734 +vmlinuz: piggy
1735 + gzip -c9 $< > $@
1736 +
1737 +piggy: $(SYSTEM)
1738 + $(OBJCOPY) $(OBJCOPY_ARGS) $< $@
1739 +
1740 +mrproper: clean
1741 +
1742 +clean:
1743 + rm -f vmlinuz piggy
1744 diff -urN linux.old/arch/mips/bcm947xx/export.c linux.dev/arch/mips/bcm947xx/export.c
1745 --- linux.old/arch/mips/bcm947xx/export.c 1970-01-01 01:00:00.000000000 +0100
1746 +++ linux.dev/arch/mips/bcm947xx/export.c 2006-10-02 21:19:59.000000000 +0200
1747 @@ -0,0 +1,71 @@
1748 +#include <linux/module.h>
1749 +
1750 +#define _export(n) \
1751 + void n(void); \
1752 + EXPORT_SYMBOL(n);
1753 +
1754 +_export(bcm947xx_sbh)
1755 +
1756 +_export(sb_attach)
1757 +_export(sb_kattach)
1758 +_export(sb_boardtype)
1759 +_export(sb_boardvendor)
1760 +_export(sb_btcgpiowar)
1761 +_export(sb_bus)
1762 +_export(sb_chip)
1763 +_export(sb_chiprev)
1764 +_export(sb_chipcrev)
1765 +_export(sb_chippkg)
1766 +_export(sb_clkctl_clk)
1767 +_export(sb_clkctl_fast_pwrup_delay)
1768 +_export(sb_clkctl_init)
1769 +_export(sb_clkctl_xtal)
1770 +_export(sb_core_disable)
1771 +_export(sb_core_reset)
1772 +_export(sb_core_tofixup)
1773 +_export(sb_coreflags)
1774 +_export(sb_coreflagshi)
1775 +_export(sb_coreidx)
1776 +_export(sb_coreregs)
1777 +_export(sb_corerev)
1778 +_export(sb_coreunit)
1779 +_export(sb_detach)
1780 +_export(sb_deviceremoved)
1781 +_export(sb_gpiosetcore)
1782 +_export(sb_gpiocontrol)
1783 +_export(sb_gpiointmask)
1784 +_export(sb_gpiointpolarity)
1785 +_export(sb_gpioled)
1786 +_export(sb_gpioin)
1787 +_export(sb_gpioout)
1788 +_export(sb_gpioouten)
1789 +_export(sb_gpiotimerval)
1790 +_export(sb_irq)
1791 +_export(sb_iscoreup)
1792 +_export(sb_pci_setup)
1793 +_export(sb_pcirev)
1794 +_export(sb_pcmcia_init)
1795 +_export(sb_pcmciarev)
1796 +_export(sb_register_intr_callback)
1797 +_export(sb_setcore)
1798 +_export(sb_setcoreidx)
1799 +_export(sb_war16165)
1800 +_export(sb_war32414_forceHT)
1801 +_export(sb_osh)
1802 +
1803 +_export(getvar)
1804 +_export(getintvar)
1805 +_export(bcm_strtoul)
1806 +_export(bcm_ctype)
1807 +_export(bcm_toupper)
1808 +_export(bcm_ether_ntoa)
1809 +
1810 +_export(nvram_get)
1811 +_export(nvram_getall)
1812 +_export(nvram_set)
1813 +_export(nvram_unset)
1814 +_export(nvram_commit)
1815 +
1816 +_export(srom_read)
1817 +_export(srom_write)
1818 +
1819 diff -urN linux.old/arch/mips/bcm947xx/generic/int-handler.S linux.dev/arch/mips/bcm947xx/generic/int-handler.S
1820 --- linux.old/arch/mips/bcm947xx/generic/int-handler.S 1970-01-01 01:00:00.000000000 +0100
1821 +++ linux.dev/arch/mips/bcm947xx/generic/int-handler.S 2006-10-02 21:19:59.000000000 +0200
1822 @@ -0,0 +1,51 @@
1823 +/*
1824 + * Generic interrupt handler for Broadcom MIPS boards
1825 + *
1826 + * Copyright 2004, Broadcom Corporation
1827 + * All Rights Reserved.
1828 + *
1829 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1830 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1831 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1832 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1833 + *
1834 + * $Id: int-handler.S,v 1.1 2005/03/16 13:50:00 wbx Exp $
1835 + */
1836 +
1837 +#include <linux/config.h>
1838 +
1839 +#include <asm/asm.h>
1840 +#include <asm/mipsregs.h>
1841 +#include <asm/regdef.h>
1842 +#include <asm/stackframe.h>
1843 +
1844 +/*
1845 + * MIPS IRQ Source
1846 + * -------- ------
1847 + * 0 Software (ignored)
1848 + * 1 Software (ignored)
1849 + * 2 Combined hardware interrupt (hw0)
1850 + * 3 Hardware
1851 + * 4 Hardware
1852 + * 5 Hardware
1853 + * 6 Hardware
1854 + * 7 R4k timer
1855 + */
1856 +
1857 + .text
1858 + .set noreorder
1859 + .set noat
1860 + .align 5
1861 + NESTED(brcmIRQ, PT_SIZE, sp)
1862 + SAVE_ALL
1863 + CLI
1864 + .set at
1865 + .set noreorder
1866 +
1867 + jal brcm_irq_dispatch
1868 + move a0, sp
1869 +
1870 + j ret_from_irq
1871 + nop
1872 +
1873 + END(brcmIRQ)
1874 diff -urN linux.old/arch/mips/bcm947xx/generic/irq.c linux.dev/arch/mips/bcm947xx/generic/irq.c
1875 --- linux.old/arch/mips/bcm947xx/generic/irq.c 1970-01-01 01:00:00.000000000 +0100
1876 +++ linux.dev/arch/mips/bcm947xx/generic/irq.c 2006-10-02 21:19:59.000000000 +0200
1877 @@ -0,0 +1,130 @@
1878 +/*
1879 + * Generic interrupt control functions for Broadcom MIPS boards
1880 + *
1881 + * Copyright 2004, Broadcom Corporation
1882 + * All Rights Reserved.
1883 + *
1884 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1885 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1886 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1887 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1888 + *
1889 + * $Id: irq.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
1890 + */
1891 +
1892 +#include <linux/config.h>
1893 +#include <linux/init.h>
1894 +#include <linux/kernel.h>
1895 +#include <linux/types.h>
1896 +#include <linux/interrupt.h>
1897 +#include <linux/irq.h>
1898 +
1899 +#include <asm/irq.h>
1900 +#include <asm/mipsregs.h>
1901 +#include <asm/gdb-stub.h>
1902 +
1903 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
1904 +
1905 +extern asmlinkage void brcmIRQ(void);
1906 +extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
1907 +
1908 +void
1909 +brcm_irq_dispatch(struct pt_regs *regs)
1910 +{
1911 + u32 cause;
1912 +
1913 + cause = read_c0_cause() &
1914 + read_c0_status() &
1915 + CAUSEF_IP;
1916 +
1917 +#ifdef CONFIG_KERNPROF
1918 + change_c0_status(cause | 1, 1);
1919 +#else
1920 + clear_c0_status(cause);
1921 +#endif
1922 +
1923 + if (cause & CAUSEF_IP7)
1924 + do_IRQ(7, regs);
1925 + if (cause & CAUSEF_IP2)
1926 + do_IRQ(2, regs);
1927 + if (cause & CAUSEF_IP3)
1928 + do_IRQ(3, regs);
1929 + if (cause & CAUSEF_IP4)
1930 + do_IRQ(4, regs);
1931 + if (cause & CAUSEF_IP5)
1932 + do_IRQ(5, regs);
1933 + if (cause & CAUSEF_IP6)
1934 + do_IRQ(6, regs);
1935 +}
1936 +
1937 +static void
1938 +enable_brcm_irq(unsigned int irq)
1939 +{
1940 + if (irq < 8)
1941 + set_c0_status(1 << (irq + 8));
1942 + else
1943 + set_c0_status(IE_IRQ0);
1944 +}
1945 +
1946 +static void
1947 +disable_brcm_irq(unsigned int irq)
1948 +{
1949 + if (irq < 8)
1950 + clear_c0_status(1 << (irq + 8));
1951 + else
1952 + clear_c0_status(IE_IRQ0);
1953 +}
1954 +
1955 +static void
1956 +ack_brcm_irq(unsigned int irq)
1957 +{
1958 + /* Already done in brcm_irq_dispatch */
1959 +}
1960 +
1961 +static unsigned int
1962 +startup_brcm_irq(unsigned int irq)
1963 +{
1964 + enable_brcm_irq(irq);
1965 +
1966 + return 0; /* never anything pending */
1967 +}
1968 +
1969 +static void
1970 +end_brcm_irq(unsigned int irq)
1971 +{
1972 + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
1973 + enable_brcm_irq(irq);
1974 +}
1975 +
1976 +static struct hw_interrupt_type brcm_irq_type = {
1977 + typename: "MIPS",
1978 + startup: startup_brcm_irq,
1979 + shutdown: disable_brcm_irq,
1980 + enable: enable_brcm_irq,
1981 + disable: disable_brcm_irq,
1982 + ack: ack_brcm_irq,
1983 + end: end_brcm_irq,
1984 + NULL
1985 +};
1986 +
1987 +void __init
1988 +init_IRQ(void)
1989 +{
1990 + int i;
1991 +
1992 + for (i = 0; i < NR_IRQS; i++) {
1993 + irq_desc[i].status = IRQ_DISABLED;
1994 + irq_desc[i].action = 0;
1995 + irq_desc[i].depth = 1;
1996 + irq_desc[i].handler = &brcm_irq_type;
1997 + }
1998 +
1999 + set_except_vector(0, brcmIRQ);
2000 + change_c0_status(ST0_IM, ALLINTS);
2001 +
2002 +#ifdef CONFIG_REMOTE_DEBUG
2003 + printk("Breaking into debugger...\n");
2004 + set_debug_traps();
2005 + breakpoint();
2006 +#endif
2007 +}
2008 diff -urN linux.old/arch/mips/bcm947xx/generic/Makefile linux.dev/arch/mips/bcm947xx/generic/Makefile
2009 --- linux.old/arch/mips/bcm947xx/generic/Makefile 1970-01-01 01:00:00.000000000 +0100
2010 +++ linux.dev/arch/mips/bcm947xx/generic/Makefile 2006-10-02 21:26:29.000000000 +0200
2011 @@ -0,0 +1,12 @@
2012 +#
2013 +# Makefile for the BCM947xx specific kernel interface routines
2014 +# under Linux.
2015 +#
2016 +EXTRA_CFLAGS += -fno-delayed-branch
2017 +USE_STANDARD_AS_RULE := true
2018 +
2019 +O_TARGET := brcm.o
2020 +
2021 +obj-y := int-handler.o irq.o
2022 +
2023 +include $(TOPDIR)/Rules.make
2024 diff -urN linux.old/arch/mips/bcm947xx/gpio.c linux.dev/arch/mips/bcm947xx/gpio.c
2025 --- linux.old/arch/mips/bcm947xx/gpio.c 1970-01-01 01:00:00.000000000 +0100
2026 +++ linux.dev/arch/mips/bcm947xx/gpio.c 2006-10-02 21:19:59.000000000 +0200
2027 @@ -0,0 +1,159 @@
2028 +/*
2029 + * GPIO char driver
2030 + *
2031 + * Copyright 2005, Broadcom Corporation
2032 + * All Rights Reserved.
2033 + *
2034 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2035 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2036 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2037 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2038 + *
2039 + * $Id$
2040 + */
2041 +
2042 +#include <linux/module.h>
2043 +#include <linux/init.h>
2044 +#include <linux/fs.h>
2045 +#include <linux/miscdevice.h>
2046 +#include <asm/uaccess.h>
2047 +
2048 +#include <typedefs.h>
2049 +#include <osl.h>
2050 +#include <bcmutils.h>
2051 +#include <sbutils.h>
2052 +#include <bcmdevs.h>
2053 +
2054 +static sb_t *gpio_sbh;
2055 +static int gpio_major;
2056 +static devfs_handle_t gpio_dir;
2057 +static struct {
2058 + char *name;
2059 + devfs_handle_t handle;
2060 +} gpio_file[] = {
2061 + { "in", NULL },
2062 + { "out", NULL },
2063 + { "outen", NULL },
2064 + { "control", NULL }
2065 +};
2066 +
2067 +static int
2068 +gpio_open(struct inode *inode, struct file * file)
2069 +{
2070 + if (MINOR(inode->i_rdev) > ARRAYSIZE(gpio_file))
2071 + return -ENODEV;
2072 +
2073 + MOD_INC_USE_COUNT;
2074 + return 0;
2075 +}
2076 +
2077 +static int
2078 +gpio_release(struct inode *inode, struct file * file)
2079 +{
2080 + MOD_DEC_USE_COUNT;
2081 + return 0;
2082 +}
2083 +
2084 +static ssize_t
2085 +gpio_read(struct file *file, char *buf, size_t count, loff_t *ppos)
2086 +{
2087 + u32 val;
2088 +
2089 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
2090 + case 0:
2091 + val = sb_gpioin(gpio_sbh);
2092 + break;
2093 + case 1:
2094 + val = sb_gpioout(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2095 + break;
2096 + case 2:
2097 + val = sb_gpioouten(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2098 + break;
2099 + case 3:
2100 + val = sb_gpiocontrol(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2101 + break;
2102 + default:
2103 + return -ENODEV;
2104 + }
2105 +
2106 + if (put_user(val, (u32 *) buf))
2107 + return -EFAULT;
2108 +
2109 + return sizeof(val);
2110 +}
2111 +
2112 +static ssize_t
2113 +gpio_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
2114 +{
2115 + u32 val;
2116 +
2117 + if (get_user(val, (u32 *) buf))
2118 + return -EFAULT;
2119 +
2120 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
2121 + case 0:
2122 + return -EACCES;
2123 + case 1:
2124 + sb_gpioout(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2125 + break;
2126 + case 2:
2127 + sb_gpioouten(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2128 + break;
2129 + case 3:
2130 + sb_gpiocontrol(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2131 + break;
2132 + default:
2133 + return -ENODEV;
2134 + }
2135 +
2136 + return sizeof(val);
2137 +}
2138 +
2139 +static struct file_operations gpio_fops = {
2140 + owner: THIS_MODULE,
2141 + open: gpio_open,
2142 + release: gpio_release,
2143 + read: gpio_read,
2144 + write: gpio_write,
2145 +};
2146 +
2147 +static int __init
2148 +gpio_init(void)
2149 +{
2150 + int i;
2151 +
2152 + if (!(gpio_sbh = sb_kattach()))
2153 + return -ENODEV;
2154 +
2155 + sb_gpiosetcore(gpio_sbh);
2156 +
2157 + if ((gpio_major = devfs_register_chrdev(0, "gpio", &gpio_fops)) < 0)
2158 + return gpio_major;
2159 +
2160 + gpio_dir = devfs_mk_dir(NULL, "gpio", NULL);
2161 +
2162 + for (i = 0; i < ARRAYSIZE(gpio_file); i++) {
2163 + gpio_file[i].handle = devfs_register(gpio_dir,
2164 + gpio_file[i].name,
2165 + DEVFS_FL_DEFAULT, gpio_major, i,
2166 + S_IFCHR | S_IRUGO | S_IWUGO,
2167 + &gpio_fops, NULL);
2168 + }
2169 +
2170 + return 0;
2171 +}
2172 +
2173 +static void __exit
2174 +gpio_exit(void)
2175 +{
2176 + int i;
2177 +
2178 + for (i = 0; i < ARRAYSIZE(gpio_file); i++)
2179 + devfs_unregister(gpio_file[i].handle);
2180 + devfs_unregister(gpio_dir);
2181 + devfs_unregister_chrdev(gpio_major, "gpio");
2182 + sb_detach(gpio_sbh);
2183 +}
2184 +
2185 +module_init(gpio_init);
2186 +module_exit(gpio_exit);
2187 diff -urN linux.old/arch/mips/bcm947xx/hndchipc.c linux.dev/arch/mips/bcm947xx/hndchipc.c
2188 --- linux.old/arch/mips/bcm947xx/hndchipc.c 1970-01-01 01:00:00.000000000 +0100
2189 +++ linux.dev/arch/mips/bcm947xx/hndchipc.c 2006-10-02 21:19:59.000000000 +0200
2190 @@ -0,0 +1,158 @@
2191 +/*
2192 + * BCM47XX support code for some chipcommon (old extif) facilities (uart)
2193 + *
2194 + * Copyright 2006, Broadcom Corporation
2195 + * All Rights Reserved.
2196 + *
2197 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2198 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2199 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2200 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2201 + *
2202 + * $Id: hndchipc.c,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
2203 + */
2204 +
2205 +#include <typedefs.h>
2206 +#include <bcmdefs.h>
2207 +#include <osl.h>
2208 +#include <bcmutils.h>
2209 +#include <sbutils.h>
2210 +#include <bcmdevs.h>
2211 +#include <bcmnvram.h>
2212 +#include <sbconfig.h>
2213 +#include <sbextif.h>
2214 +#include <sbchipc.h>
2215 +#include <hndcpu.h>
2216 +
2217 +/*
2218 + * Returns TRUE if an external UART exists at the given base
2219 + * register.
2220 + */
2221 +static bool
2222 +BCMINITFN(serial_exists)(osl_t *osh, uint8 *regs)
2223 +{
2224 + uint8 save_mcr, status1;
2225 +
2226 + save_mcr = R_REG(osh, &regs[UART_MCR]);
2227 + W_REG(osh, &regs[UART_MCR], UART_MCR_LOOP | 0x0a);
2228 + status1 = R_REG(osh, &regs[UART_MSR]) & 0xf0;
2229 + W_REG(osh, &regs[UART_MCR], save_mcr);
2230 +
2231 + return (status1 == 0x90);
2232 +}
2233 +
2234 +/*
2235 + * Initializes UART access. The callback function will be called once
2236 + * per found UART.
2237 + */
2238 +void
2239 +BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base,
2240 + uint reg_shift))
2241 +{
2242 + osl_t *osh;
2243 + void *regs;
2244 + ulong base;
2245 + uint irq;
2246 + int i, n;
2247 +
2248 + osh = sb_osh(sbh);
2249 +
2250 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
2251 + extifregs_t *eir = (extifregs_t *) regs;
2252 + sbconfig_t *sb;
2253 +
2254 + /* Determine external UART register base */
2255 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
2256 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(osh, &sb->sbadmatch1)));
2257 +
2258 + /* Determine IRQ */
2259 + irq = sb_irq(sbh);
2260 +
2261 + /* Disable GPIO interrupt initially */
2262 + W_REG(osh, &eir->gpiointpolarity, 0);
2263 + W_REG(osh, &eir->gpiointmask, 0);
2264 +
2265 + /* Search for external UARTs */
2266 + n = 2;
2267 + for (i = 0; i < 2; i++) {
2268 + regs = (void *) REG_MAP(base + (i * 8), 8);
2269 + if (serial_exists(osh, regs)) {
2270 + /* Set GPIO 1 to be the external UART IRQ */
2271 + W_REG(osh, &eir->gpiointmask, 2);
2272 + /* XXXDetermine external UART clock */
2273 + if (add)
2274 + add(regs, irq, 13500000, 0);
2275 + }
2276 + }
2277 +
2278 + /* Add internal UART if enabled */
2279 + if (R_REG(osh, &eir->corecontrol) & CC_UE)
2280 + if (add)
2281 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
2282 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
2283 + chipcregs_t *cc = (chipcregs_t *) regs;
2284 + uint32 rev, cap, pll, baud_base, div;
2285 +
2286 + /* Determine core revision and capabilities */
2287 + rev = sb_corerev(sbh);
2288 + cap = R_REG(osh, &cc->capabilities);
2289 + pll = cap & CAP_PLL_MASK;
2290 +
2291 + /* Determine IRQ */
2292 + irq = sb_irq(sbh);
2293 +
2294 + if (pll == PLL_TYPE1) {
2295 + /* PLL clock */
2296 + baud_base = sb_clock_rate(pll,
2297 + R_REG(osh, &cc->clockcontrol_n),
2298 + R_REG(osh, &cc->clockcontrol_m2));
2299 + div = 1;
2300 + } else {
2301 + /* Fixed ALP clock */
2302 + if (rev >= 11 && rev != 15) {
2303 + baud_base = 20000000;
2304 + div = 1;
2305 + /* Set the override bit so we don't divide it */
2306 + W_REG(osh, &cc->corecontrol, CC_UARTCLKO);
2307 + }
2308 + /* Internal backplane clock */
2309 + else if (rev >= 3) {
2310 + baud_base = sb_clock(sbh);
2311 + div = 2; /* Minimum divisor */
2312 + W_REG(osh, &cc->clkdiv,
2313 + ((R_REG(osh, &cc->clkdiv) & ~CLKD_UART) | div));
2314 + }
2315 + /* Fixed internal backplane clock */
2316 + else {
2317 + baud_base = 88000000;
2318 + div = 48;
2319 + }
2320 +
2321 + /* Clock source depends on strapping if UartClkOverride is unset */
2322 + if ((rev > 0) &&
2323 + ((R_REG(osh, &cc->corecontrol) & CC_UARTCLKO) == 0)) {
2324 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
2325 + /* Internal divided backplane clock */
2326 + baud_base /= div;
2327 + } else {
2328 + /* Assume external clock of 1.8432 MHz */
2329 + baud_base = 1843200;
2330 + }
2331 + }
2332 + }
2333 +
2334 + /* Add internal UARTs */
2335 + n = cap & CAP_UARTS_MASK;
2336 + for (i = 0; i < n; i++) {
2337 + /* Register offset changed after revision 0 */
2338 + if (rev)
2339 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
2340 + else
2341 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
2342 +
2343 + if (add)
2344 + add(regs, irq, baud_base, 0);
2345 + }
2346 + }
2347 +}
2348 +
2349 diff -urN linux.old/arch/mips/bcm947xx/include/bcm4710.h linux.dev/arch/mips/bcm947xx/include/bcm4710.h
2350 --- linux.old/arch/mips/bcm947xx/include/bcm4710.h 1970-01-01 01:00:00.000000000 +0100
2351 +++ linux.dev/arch/mips/bcm947xx/include/bcm4710.h 2006-10-02 21:19:59.000000000 +0200
2352 @@ -0,0 +1,91 @@
2353 +/*
2354 + * BCM4710 address space map and definitions
2355 + * Think twice before adding to this file, this is not the kitchen sink
2356 + * These definitions are not guaranteed for all 47xx chips, only the 4710
2357 + *
2358 + * Copyright 2004, Broadcom Corporation
2359 + * All Rights Reserved.
2360 + *
2361 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2362 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2363 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2364 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2365 + *
2366 + * $Id: bcm4710.h,v 1.3 2004/09/27 07:23:30 tallest Exp $
2367 + */
2368 +
2369 +#ifndef _bcm4710_h_
2370 +#define _bcm4710_h_
2371 +
2372 +/* Address map */
2373 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
2374 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
2375 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
2376 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
2377 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
2378 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
2379 +
2380 +/* Core register space */
2381 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
2382 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
2383 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
2384 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
2385 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
2386 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
2387 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
2388 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
2389 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
2390 +
2391 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
2392 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
2393 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
2394 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
2395 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
2396 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
2397 +
2398 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
2399 +
2400 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
2401 +
2402 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
2403 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
2404 +
2405 +#define SBFLAG_PCI 0
2406 +#define SBFLAG_ENET0 1
2407 +#define SBFLAG_ILINE20 2
2408 +#define SBFLAG_CODEC 3
2409 +#define SBFLAG_USB 4
2410 +#define SBFLAG_EXTIF 5
2411 +#define SBFLAG_ENET1 6
2412 +
2413 +#ifdef CONFIG_HWSIM
2414 +#define BCM4710_TRACE(trval) do { *((int *)0xa0000f18) = (trval); } while (0)
2415 +#else
2416 +#define BCM4710_TRACE(trval)
2417 +#endif
2418 +
2419 +
2420 +/* BCM94702 CPCI -ExtIF used for LocalBus devs */
2421 +
2422 +#define BCM94702_CPCI_RESET_ADDR BCM4710_EXTIF
2423 +#define BCM94702_CPCI_BOARDID_ADDR (BCM4710_EXTIF | 0x4000)
2424 +#define BCM94702_CPCI_DOC_ADDR (BCM4710_EXTIF | 0x6000)
2425 +#define BCM94702_DOC_ADDR BCM94702_CPCI_DOC_ADDR
2426 +#define BCM94702_CPCI_LED_ADDR (BCM4710_EXTIF | 0xc000)
2427 +#define BCM94702_CPCI_NVRAM_ADDR (BCM4710_EXTIF | 0xe000)
2428 +#define BCM94702_CPCI_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
2429 +#define BCM94702_CPCI_TOD_REG_BASE (BCM94702_CPCI_NVRAM_ADDR | 0x1ff0)
2430 +
2431 +#define LED_REG(x) \
2432 + (*(volatile unsigned char *) (KSEG1ADDR(BCM94702_CPCI_LED_ADDR) + (x)))
2433 +
2434 +/*
2435 + * Reset function implemented in PLD. Read or write should trigger hard reset
2436 + */
2437 +#define SYS_HARD_RESET() \
2438 + { for (;;) \
2439 + *( (volatile unsigned char *)\
2440 + KSEG1ADDR(BCM94702_CPCI_RESET_ADDR) ) = 0x80; \
2441 + }
2442 +
2443 +#endif /* _bcm4710_h_ */
2444 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdefs.h linux.dev/arch/mips/bcm947xx/include/bcmdefs.h
2445 --- linux.old/arch/mips/bcm947xx/include/bcmdefs.h 1970-01-01 01:00:00.000000000 +0100
2446 +++ linux.dev/arch/mips/bcm947xx/include/bcmdefs.h 2006-10-02 21:19:59.000000000 +0200
2447 @@ -0,0 +1,106 @@
2448 +/*
2449 + * Misc system wide definitions
2450 + *
2451 + * Copyright 2006, Broadcom Corporation
2452 + * All Rights Reserved.
2453 + *
2454 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2455 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2456 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2457 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2458 + * $Id: bcmdefs.h,v 1.1.1.3 2006/04/08 06:13:39 honor Exp $
2459 + */
2460 +
2461 +#ifndef _bcmdefs_h_
2462 +#define _bcmdefs_h_
2463 +
2464 +/*
2465 + * One doesn't need to include this file explicitly, gets included automatically if
2466 + * typedefs.h is included.
2467 + */
2468 +
2469 +/* Reclaiming text and data :
2470 + * The following macros specify special linker sections that can be reclaimed
2471 + * after a system is considered 'up'.
2472 + */
2473 +#if defined(__GNUC__) && defined(BCMRECLAIM)
2474 +extern bool bcmreclaimed;
2475 +#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data
2476 +#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn
2477 +#else /* #if defined(__GNUC__) && defined(BCMRECLAIM) */
2478 +#define BCMINITDATA(_data) _data
2479 +#define BCMINITFN(_fn) _fn
2480 +#define bcmreclaimed 0
2481 +#endif /* #if defined(__GNUC__) && defined(BCMRECLAIM) */
2482 +
2483 +/* Reclaim uninit functions if BCMNODOWN is defined */
2484 +/* and if they are not already removed by -gc-sections */
2485 +#ifdef BCMNODOWN
2486 +#define BCMUNINITFN(_fn) BCMINITFN(_fn)
2487 +#else
2488 +#define BCMUNINITFN(_fn) _fn
2489 +#endif
2490 +
2491 +#ifdef BCMRECLAIM
2492 +#define CONST
2493 +#else
2494 +#define CONST const
2495 +#endif /* BCMRECLAIM */
2496 +
2497 +/* Compatibility with old-style BCMRECLAIM */
2498 +#define BCMINIT(_id) _id
2499 +
2500 +
2501 +/* Put some library data/code into ROM to reduce RAM requirements */
2502 +#if defined(__GNUC__) && defined(BCMROMOFFLOAD)
2503 +#define BCMROMDATA(_data) __attribute__ ((__section__ (".datarom." #_data))) _data
2504 +#define BCMROMFN(_fn) __attribute__ ((__section__ (".textrom." #_fn))) _fn
2505 +#else
2506 +#define BCMROMDATA(_data) _data
2507 +#define BCMROMFN(_fn) _fn
2508 +#endif
2509 +
2510 +/* Bus types */
2511 +#define SB_BUS 0 /* Silicon Backplane */
2512 +#define PCI_BUS 1 /* PCI target */
2513 +#define PCMCIA_BUS 2 /* PCMCIA target */
2514 +#define SDIO_BUS 3 /* SDIO target */
2515 +#define JTAG_BUS 4 /* JTAG */
2516 +#define NO_BUS 0xFF /* Bus that does not support R/W REG */
2517 +
2518 +/* Allows optimization for single-bus support */
2519 +#ifdef BCMBUSTYPE
2520 +#define BUSTYPE(bus) (BCMBUSTYPE)
2521 +#else
2522 +#define BUSTYPE(bus) (bus)
2523 +#endif
2524 +
2525 +/* Defines for DMA Address Width - Shared between OSL and HNDDMA */
2526 +#define DMADDR_MASK_32 0x0 /* Address mask for 32-bits */
2527 +#define DMADDR_MASK_30 0xc0000000 /* Address mask for 30-bits */
2528 +#define DMADDR_MASK_0 0xffffffff /* Address mask for 0-bits (hi-part) */
2529 +
2530 +#define DMADDRWIDTH_30 30 /* 30-bit addressing capability */
2531 +#define DMADDRWIDTH_32 32 /* 32-bit addressing capability */
2532 +#define DMADDRWIDTH_63 63 /* 64-bit addressing capability */
2533 +#define DMADDRWIDTH_64 64 /* 64-bit addressing capability */
2534 +
2535 +/* packet headroom necessary to accomodate the largest header in the system, (i.e TXOFF).
2536 + * By doing, we avoid the need to allocate an extra buffer for the header when bridging to WL.
2537 + * There is a compile time check in wlc.c which ensure that this value is at least as big
2538 + * as TXOFF. This value is used in dma_rxfill (hnddma.c).
2539 + */
2540 +#define BCMEXTRAHDROOM 160
2541 +
2542 +/* Headroom required for dongle-to-host communication. Packets allocated
2543 + * locally in the dongle (e.g. for CDC ioctls or RNDIS messages) should
2544 + * leave this much room in front for low-level message headers which may
2545 + * be needed to get across the dongle bus to the host. (These messages
2546 + * don't go over the network, so room for the full WL header above would
2547 + * be a waste.)
2548 + */
2549 +#define BCMDONGLEHDRSZ 8
2550 +
2551 +
2552 +
2553 +#endif /* _bcmdefs_h_ */
2554 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs1.h linux.dev/arch/mips/bcm947xx/include/bcmdevs1.h
2555 --- linux.old/arch/mips/bcm947xx/include/bcmdevs1.h 1970-01-01 01:00:00.000000000 +0100
2556 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs1.h 2006-10-02 21:19:59.000000000 +0200
2557 @@ -0,0 +1,391 @@
2558 +/*
2559 + * Broadcom device-specific manifest constants.
2560 + *
2561 + * Copyright 2005, Broadcom Corporation
2562 + * All Rights Reserved.
2563 + *
2564 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2565 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2566 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2567 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2568 + * $Id$
2569 + */
2570 +
2571 +#ifndef _BCMDEVS_H
2572 +#define _BCMDEVS_H
2573 +
2574 +
2575 +/* Known PCI vendor Id's */
2576 +#define VENDOR_EPIGRAM 0xfeda
2577 +#define VENDOR_BROADCOM 0x14e4
2578 +#define VENDOR_3COM 0x10b7
2579 +#define VENDOR_NETGEAR 0x1385
2580 +#define VENDOR_DIAMOND 0x1092
2581 +#define VENDOR_DELL 0x1028
2582 +#define VENDOR_HP 0x0e11
2583 +#define VENDOR_APPLE 0x106b
2584 +
2585 +/* PCI Device Id's */
2586 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
2587 +#define BCM4211_DEVICE_ID 0x4211
2588 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
2589 +#define BCM4231_DEVICE_ID 0x4231
2590 +
2591 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
2592 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
2593 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
2594 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
2595 +
2596 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
2597 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
2598 +
2599 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
2600 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
2601 +
2602 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
2603 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
2604 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
2605 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
2606 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
2607 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
2608 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
2609 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
2610 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
2611 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
2612 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
2613 +
2614 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
2615 +
2616 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
2617 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
2618 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
2619 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
2620 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
2621 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
2622 +
2623 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
2624 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
2625 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
2626 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
2627 +
2628 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
2629 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
2630 +
2631 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
2632 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
2633 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
2634 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
2635 +
2636 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
2637 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
2638 +#define BCM4306_D11G_ID2 0x4325
2639 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
2640 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
2641 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
2642 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
2643 +
2644 +#define BCM4309_PKG_ID 1 /* 4309 package id */
2645 +
2646 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
2647 +#define BCM4303_PKG_ID 2 /* 4303 package id */
2648 +
2649 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
2650 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
2651 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
2652 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
2653 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
2654 +
2655 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
2656 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
2657 +
2658 +
2659 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
2660 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
2661 +
2662 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
2663 +
2664 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
2665 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
2666 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
2667 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
2668 +
2669 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
2670 +
2671 +/* Address map */
2672 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
2673 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
2674 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
2675 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
2676 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
2677 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
2678 +
2679 +/* Core register space */
2680 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
2681 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
2682 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
2683 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
2684 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
2685 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
2686 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
2687 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
2688 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
2689 +
2690 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
2691 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
2692 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
2693 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
2694 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
2695 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
2696 +
2697 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
2698 +
2699 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
2700 +
2701 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
2702 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
2703 +
2704 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
2705 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
2706 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
2707 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
2708 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
2709 +
2710 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
2711 +
2712 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
2713 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
2714 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
2715 +
2716 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
2717 +
2718 +/* PCMCIA vendor Id's */
2719 +
2720 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
2721 +
2722 +/* SDIO vendor Id's */
2723 +#define VENDOR_BROADCOM_SDIO 0x00BF
2724 +
2725 +
2726 +/* boardflags */
2727 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
2728 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
2729 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
2730 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
2731 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
2732 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
2733 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
2734 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
2735 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
2736 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
2737 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
2738 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
2739 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
2740 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
2741 +
2742 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
2743 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
2744 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
2745 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
2746 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
2747 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
2748 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
2749 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
2750 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
2751 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
2752 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
2753 +
2754 +/* Bus types */
2755 +#define SB_BUS 0 /* Silicon Backplane */
2756 +#define PCI_BUS 1 /* PCI target */
2757 +#define PCMCIA_BUS 2 /* PCMCIA target */
2758 +#define SDIO_BUS 3 /* SDIO target */
2759 +#define JTAG_BUS 4 /* JTAG */
2760 +
2761 +/* Allows optimization for single-bus support */
2762 +#ifdef BCMBUSTYPE
2763 +#define BUSTYPE(bus) (BCMBUSTYPE)
2764 +#else
2765 +#define BUSTYPE(bus) (bus)
2766 +#endif
2767 +
2768 +/* power control defines */
2769 +#define PLL_DELAY 150 /* us pll on delay */
2770 +#define FREF_DELAY 200 /* us fref change delay */
2771 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
2772 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
2773 +
2774 +/* Reference Board Types */
2775 +
2776 +#define BU4710_BOARD 0x0400
2777 +#define VSIM4710_BOARD 0x0401
2778 +#define QT4710_BOARD 0x0402
2779 +
2780 +#define BU4610_BOARD 0x0403
2781 +#define VSIM4610_BOARD 0x0404
2782 +
2783 +#define BU4307_BOARD 0x0405
2784 +#define BCM94301CB_BOARD 0x0406
2785 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
2786 +#define BCM94301MP_BOARD 0x0407
2787 +#define BCM94307MP_BOARD 0x0408
2788 +#define BCMAP4307_BOARD 0x0409
2789 +
2790 +#define BU4309_BOARD 0x040a
2791 +#define BCM94309CB_BOARD 0x040b
2792 +#define BCM94309MP_BOARD 0x040c
2793 +#define BCM4309AP_BOARD 0x040d
2794 +
2795 +#define BCM94302MP_BOARD 0x040e
2796 +
2797 +#define VSIM4310_BOARD 0x040f
2798 +#define BU4711_BOARD 0x0410
2799 +#define BCM94310U_BOARD 0x0411
2800 +#define BCM94310AP_BOARD 0x0412
2801 +#define BCM94310MP_BOARD 0x0414
2802 +
2803 +#define BU4306_BOARD 0x0416
2804 +#define BCM94306CB_BOARD 0x0417
2805 +#define BCM94306MP_BOARD 0x0418
2806 +
2807 +#define BCM94710D_BOARD 0x041a
2808 +#define BCM94710R1_BOARD 0x041b
2809 +#define BCM94710R4_BOARD 0x041c
2810 +#define BCM94710AP_BOARD 0x041d
2811 +
2812 +
2813 +#define BU2050_BOARD 0x041f
2814 +
2815 +
2816 +#define BCM94309G_BOARD 0x0421
2817 +
2818 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
2819 +
2820 +#define BU4704_BOARD 0x0423
2821 +#define BU4702_BOARD 0x0424
2822 +
2823 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
2824 +
2825 +#define BU4317_BOARD 0x0426
2826 +
2827 +
2828 +#define BCM94702MN_BOARD 0x0428
2829 +
2830 +/* BCM4702 1U CompactPCI Board */
2831 +#define BCM94702CPCI_BOARD 0x0429
2832 +
2833 +/* BCM4702 with BCM95380 VLAN Router */
2834 +#define BCM95380RR_BOARD 0x042a
2835 +
2836 +/* cb4306 with SiGe PA */
2837 +#define BCM94306CBSG_BOARD 0x042b
2838 +
2839 +/* mp4301 with 2050 radio */
2840 +#define BCM94301MPL_BOARD 0x042c
2841 +
2842 +/* cb4306 with SiGe PA */
2843 +#define PCSG94306_BOARD 0x042d
2844 +
2845 +/* bu4704 with sdram */
2846 +#define BU4704SD_BOARD 0x042e
2847 +
2848 +/* Dual 11a/11g Router */
2849 +#define BCM94704AGR_BOARD 0x042f
2850 +
2851 +/* 11a-only minipci */
2852 +#define BCM94308MP_BOARD 0x0430
2853 +
2854 +
2855 +
2856 +/* BCM94317 boards */
2857 +#define BCM94317CB_BOARD 0x0440
2858 +#define BCM94317MP_BOARD 0x0441
2859 +#define BCM94317PCMCIA_BOARD 0x0442
2860 +#define BCM94317SDIO_BOARD 0x0443
2861 +
2862 +#define BU4712_BOARD 0x0444
2863 +#define BU4712SD_BOARD 0x045d
2864 +#define BU4712L_BOARD 0x045f
2865 +
2866 +/* BCM4712 boards */
2867 +#define BCM94712AP_BOARD 0x0445
2868 +#define BCM94712P_BOARD 0x0446
2869 +
2870 +/* BCM4318 boards */
2871 +#define BU4318_BOARD 0x0447
2872 +#define CB4318_BOARD 0x0448
2873 +#define MPG4318_BOARD 0x0449
2874 +#define MP4318_BOARD 0x044a
2875 +#define SD4318_BOARD 0x044b
2876 +
2877 +/* BCM63XX boards */
2878 +#define BCM96338_BOARD 0x6338
2879 +#define BCM96345_BOARD 0x6345
2880 +#define BCM96348_BOARD 0x6348
2881 +
2882 +/* Another mp4306 with SiGe */
2883 +#define BCM94306P_BOARD 0x044c
2884 +
2885 +/* CF-like 4317 modules */
2886 +#define BCM94317CF_BOARD 0x044d
2887 +
2888 +/* mp4303 */
2889 +#define BCM94303MP_BOARD 0x044e
2890 +
2891 +/* mpsgh4306 */
2892 +#define BCM94306MPSGH_BOARD 0x044f
2893 +
2894 +/* BRCM 4306 w/ Front End Modules */
2895 +#define BCM94306MPM 0x0450
2896 +#define BCM94306MPL 0x0453
2897 +
2898 +/* 4712agr */
2899 +#define BCM94712AGR_BOARD 0x0451
2900 +
2901 +/* The real CF 4317 board */
2902 +#define CFI4317_BOARD 0x0452
2903 +
2904 +/* pcmcia 4303 */
2905 +#define PC4303_BOARD 0x0454
2906 +
2907 +/* 5350K */
2908 +#define BCM95350K_BOARD 0x0455
2909 +
2910 +/* 5350R */
2911 +#define BCM95350R_BOARD 0x0456
2912 +
2913 +/* 4306mplna */
2914 +#define BCM94306MPLNA_BOARD 0x0457
2915 +
2916 +/* 4320 boards */
2917 +#define BU4320_BOARD 0x0458
2918 +#define BU4320S_BOARD 0x0459
2919 +#define BCM94320PH_BOARD 0x045a
2920 +
2921 +/* 4306mph */
2922 +#define BCM94306MPH_BOARD 0x045b
2923 +
2924 +/* 4306pciv */
2925 +#define BCM94306PCIV_BOARD 0x045c
2926 +
2927 +#define BU4712SD_BOARD 0x045d
2928 +
2929 +#define BCM94320PFLSH_BOARD 0x045e
2930 +
2931 +#define BU4712L_BOARD 0x045f
2932 +#define BCM94712LGR_BOARD 0x0460
2933 +#define BCM94320R_BOARD 0x0461
2934 +
2935 +#define BU5352_BOARD 0x0462
2936 +
2937 +#define BCM94318MPGH_BOARD 0x0463
2938 +
2939 +
2940 +#define BCM95352GR_BOARD 0x0467
2941 +
2942 +/* bcm95351agr */
2943 +#define BCM95351AGR_BOARD 0x0470
2944 +
2945 +/* # of GPIO pins */
2946 +#define GPIO_NUMPINS 16
2947 +
2948 +#endif /* _BCMDEVS_H */
2949 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs.h linux.dev/arch/mips/bcm947xx/include/bcmdevs.h
2950 --- linux.old/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
2951 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs.h 2006-10-02 21:19:59.000000000 +0200
2952 @@ -0,0 +1,369 @@
2953 +/*
2954 + * Broadcom device-specific manifest constants.
2955 + *
2956 + * Copyright 2006, Broadcom Corporation
2957 + * All Rights Reserved.
2958 + *
2959 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2960 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2961 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2962 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2963 + * $Id: bcmdevs.h,v 1.1.1.17 2006/04/15 01:29:08 michael Exp $
2964 + */
2965 +
2966 +#ifndef _BCMDEVS_H
2967 +#define _BCMDEVS_H
2968 +
2969 +#include "bcm4710.h"
2970 +
2971 +/* Known PCI vendor Id's */
2972 +#define VENDOR_EPIGRAM 0xfeda
2973 +#define VENDOR_BROADCOM 0x14e4
2974 +#define VENDOR_3COM 0x10b7
2975 +#define VENDOR_NETGEAR 0x1385
2976 +#define VENDOR_DIAMOND 0x1092
2977 +#define VENDOR_DELL 0x1028
2978 +#define VENDOR_HP 0x0e11
2979 +#define VENDOR_APPLE 0x106b
2980 +
2981 +/* PCI Device Id's */
2982 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
2983 +#define BCM4211_DEVICE_ID 0x4211
2984 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
2985 +#define BCM4231_DEVICE_ID 0x4231
2986 +
2987 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
2988 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
2989 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
2990 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
2991 +
2992 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
2993 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
2994 +
2995 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
2996 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
2997 +
2998 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
2999 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
3000 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
3001 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
3002 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
3003 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
3004 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
3005 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
3006 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
3007 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
3008 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
3009 +#define BCM47XX_ATA100_ID 0x471d /* 47xx parallel ATA */
3010 +#define BCM47XX_SATAXOR_ID 0x471e /* 47xx serial ATA & XOR DMA */
3011 +#define BCM47XX_GIGETH_ID 0x471f /* 47xx GbE (5700) */
3012 +
3013 +#define BCM47XX_SMBUS_EMU_ID 0x47fe /* 47xx emulated SMBus device */
3014 +#define BCM47XX_XOR_EMU_ID 0x47ff /* 47xx emulated XOR engine */
3015 +
3016 +#define BCM4710_CHIP_ID 0x4710 /* 4710 chipid returned by sb_chip() */
3017 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
3018 +
3019 +#define BCM4402_CHIP_ID 0x4402 /* 4402 chipid */
3020 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
3021 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
3022 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
3023 +
3024 +#define BCM4306_CHIP_ID 0x4306 /* 4306 chipcommon chipid */
3025 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
3026 +#define BCM4306_D11G_ID2 0x4325
3027 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
3028 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
3029 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
3030 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
3031 +
3032 +#define BCM4309_PKG_ID 1 /* 4309 package id */
3033 +
3034 +#define BCM4311_CHIP_ID 0x4311 /* 4311 PCIe 802.11a/b/g */
3035 +#define BCM4311_D11G_ID 0x4311 /* 4311 802.11b/g id */
3036 +#define BCM4311_D11DUAL_ID 0x4312 /* 4311 802.11a/b/g id */
3037 +#define BCM4311_D11A_ID 0x4313 /* 4311 802.11a id */
3038 +
3039 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
3040 +#define BCM4303_PKG_ID 2 /* 4303 package id */
3041 +
3042 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
3043 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
3044 +
3045 +#define BCM4704_CHIP_ID 0x4704 /* 4704 chipcommon chipid */
3046 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
3047 +
3048 +#define BCM4318_CHIP_ID 0x4318 /* 4318 chip common chipid */
3049 +#define BCM4318_D11G_ID 0x4318 /* 4318 802.11b/g id */
3050 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 802.11a/b/g id */
3051 +#define BCM4318_D11A_ID 0x431a /* 4318 802.11a id */
3052 +
3053 +#define BCM4321_CHIP_ID 0x4321 /* 4321 chip common chipid */
3054 +#define BCM4321_D11N_ID 0x4328 /* 4321 802.11n dualband id */
3055 +#define BCM4321_D11N2G_ID 0x4329 /* 4321 802.11n 2.4Hgz band id */
3056 +#define BCM4321_D11N5G_ID 0x432a /* 4321 802.11n 5Ghz band id */
3057 +
3058 +#define BCM4331_CHIP_ID 0x4331 /* 4331 chip common chipid */
3059 +#define BCM4331_D11N2G_ID 0x4330 /* 4331 802.11n 2.4Ghz band id */
3060 +#define BCM4331_D11N_ID 0x4331 /* 4331 802.11n dualband id */
3061 +#define BCM4331_D11N5G_ID 0x4332 /* 4331 802.11n 5Ghz band id */
3062 +
3063 +#define HDLSIM5350_PKG_ID 1 /* HDL simulator package id for a 5350 */
3064 +#define HDLSIM_PKG_ID 14 /* HDL simulator package id */
3065 +#define HWSIM_PKG_ID 15 /* Hardware simulator package id */
3066 +
3067 +#define BCM4712_CHIP_ID 0x4712 /* 4712 chipcommon chipid */
3068 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
3069 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
3070 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
3071 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
3072 +
3073 +#define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */
3074 +#define BCM5350_CHIP_ID 0x5350 /* bcm5350 chipcommon chipid */
3075 +#define BCM5352_CHIP_ID 0x5352 /* bcm5352 chipcommon chipid */
3076 +
3077 +#define BCM4320_CHIP_ID 0x4320 /* bcm4320 chipcommon chipid */
3078 +
3079 +#define BCM4328_CHIP_ID 0x4328 /* bcm4328 chipcommon chipid */
3080 +
3081 +#define FPGA_JTAGM_ID 0x43f0 /* FPGA jtagm device id */
3082 +#define BCM43XX_JTAGM_ID 0x43f1 /* 43xx jtagm device id */
3083 +#define BCM43XXOLD_JTAGM_ID 0x4331 /* 43xx old jtagm device id */
3084 +
3085 +#define SDIOH_FPGA_ID 0x43f2 /* sdio host fpga */
3086 +#define SDIOD_FPGA_ID 0x43f4 /* sdio device fpga */
3087 +
3088 +#define MIMO_FPGA_ID 0x43f8 /* FPGA mimo minimacphy device id */
3089 +
3090 +#define BCM4785_CHIP_ID 0x4785 /* 4785 chipcommon chipid */
3091 +
3092 +/* PCMCIA vendor Id's */
3093 +
3094 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
3095 +
3096 +/* SDIO vendor Id's */
3097 +#define VENDOR_BROADCOM_SDIO 0x00BF
3098 +
3099 +
3100 +/* boardflags */
3101 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
3102 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
3103 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
3104 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
3105 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
3106 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
3107 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
3108 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
3109 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
3110 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
3111 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
3112 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
3113 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
3114 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
3115 +
3116 +/* boardflags2 */
3117 +#define BFL2_RXBB_INT_REG_DIS 0x00000001 /* This board has an external rxbb regulator */
3118 +#define BFL2_SSWITCH_AVAIL 0x00000002 /* This board has a superswitch for > 2 antennas */
3119 +#define BFL2_TXPWRCTRL_EN 0x00000004 /* This board permits TX Power Control to be enabled */
3120 +
3121 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
3122 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
3123 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
3124 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
3125 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
3126 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
3127 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
3128 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
3129 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
3130 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
3131 +
3132 +/* power control defines */
3133 +#define PLL_DELAY 150 /* us pll on delay */
3134 +#define FREF_DELAY 200 /* us fref change delay */
3135 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
3136 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
3137 +
3138 +/* Reference Board Types */
3139 +
3140 +#define BU4710_BOARD 0x0400
3141 +#define VSIM4710_BOARD 0x0401
3142 +#define QT4710_BOARD 0x0402
3143 +
3144 +#define BU4309_BOARD 0x040a
3145 +#define BCM94309CB_BOARD 0x040b
3146 +#define BCM94309MP_BOARD 0x040c
3147 +#define BCM4309AP_BOARD 0x040d
3148 +
3149 +#define BCM94302MP_BOARD 0x040e
3150 +
3151 +#define BU4306_BOARD 0x0416
3152 +#define BCM94306CB_BOARD 0x0417
3153 +#define BCM94306MP_BOARD 0x0418
3154 +
3155 +#define BCM94710D_BOARD 0x041a
3156 +#define BCM94710R1_BOARD 0x041b
3157 +#define BCM94710R4_BOARD 0x041c
3158 +#define BCM94710AP_BOARD 0x041d
3159 +
3160 +#define BU2050_BOARD 0x041f
3161 +
3162 +
3163 +#define BCM94309G_BOARD 0x0421
3164 +
3165 +#define BU4704_BOARD 0x0423
3166 +#define BU4702_BOARD 0x0424
3167 +
3168 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
3169 +
3170 +
3171 +#define BCM94702MN_BOARD 0x0428
3172 +
3173 +/* BCM4702 1U CompactPCI Board */
3174 +#define BCM94702CPCI_BOARD 0x0429
3175 +
3176 +/* BCM4702 with BCM95380 VLAN Router */
3177 +#define BCM95380RR_BOARD 0x042a
3178 +
3179 +/* cb4306 with SiGe PA */
3180 +#define BCM94306CBSG_BOARD 0x042b
3181 +
3182 +/* cb4306 with SiGe PA */
3183 +#define PCSG94306_BOARD 0x042d
3184 +
3185 +/* bu4704 with sdram */
3186 +#define BU4704SD_BOARD 0x042e
3187 +
3188 +/* Dual 11a/11g Router */
3189 +#define BCM94704AGR_BOARD 0x042f
3190 +
3191 +/* 11a-only minipci */
3192 +#define BCM94308MP_BOARD 0x0430
3193 +
3194 +
3195 +
3196 +#define BU4712_BOARD 0x0444
3197 +#define BU4712SD_BOARD 0x045d
3198 +#define BU4712L_BOARD 0x045f
3199 +
3200 +/* BCM4712 boards */
3201 +#define BCM94712AP_BOARD 0x0445
3202 +#define BCM94712P_BOARD 0x0446
3203 +
3204 +/* BCM4318 boards */
3205 +#define BU4318_BOARD 0x0447
3206 +#define CB4318_BOARD 0x0448
3207 +#define MPG4318_BOARD 0x0449
3208 +#define MP4318_BOARD 0x044a
3209 +#define SD4318_BOARD 0x044b
3210 +
3211 +/* BCM63XX boards */
3212 +#define BCM96338_BOARD 0x6338
3213 +#define BCM96348_BOARD 0x6348
3214 +
3215 +/* Another mp4306 with SiGe */
3216 +#define BCM94306P_BOARD 0x044c
3217 +
3218 +/* mp4303 */
3219 +#define BCM94303MP_BOARD 0x044e
3220 +
3221 +/* mpsgh4306 */
3222 +#define BCM94306MPSGH_BOARD 0x044f
3223 +
3224 +/* BRCM 4306 w/ Front End Modules */
3225 +#define BCM94306MPM 0x0450
3226 +#define BCM94306MPL 0x0453
3227 +
3228 +/* 4712agr */
3229 +#define BCM94712AGR_BOARD 0x0451
3230 +
3231 +/* pcmcia 4303 */
3232 +#define PC4303_BOARD 0x0454
3233 +
3234 +/* 5350K */
3235 +#define BCM95350K_BOARD 0x0455
3236 +
3237 +/* 5350R */
3238 +#define BCM95350R_BOARD 0x0456
3239 +
3240 +/* 4306mplna */
3241 +#define BCM94306MPLNA_BOARD 0x0457
3242 +
3243 +/* 4320 boards */
3244 +#define BU4320_BOARD 0x0458
3245 +#define BU4320S_BOARD 0x0459
3246 +#define BCM94320PH_BOARD 0x045a
3247 +
3248 +/* 4306mph */
3249 +#define BCM94306MPH_BOARD 0x045b
3250 +
3251 +/* 4306pciv */
3252 +#define BCM94306PCIV_BOARD 0x045c
3253 +
3254 +#define BU4712SD_BOARD 0x045d
3255 +
3256 +#define BCM94320PFLSH_BOARD 0x045e
3257 +
3258 +#define BU4712L_BOARD 0x045f
3259 +#define BCM94712LGR_BOARD 0x0460
3260 +#define BCM94320R_BOARD 0x0461
3261 +
3262 +#define BU5352_BOARD 0x0462
3263 +
3264 +#define BCM94318MPGH_BOARD 0x0463
3265 +
3266 +#define BU4311_BOARD 0x0464
3267 +#define BCM94311MC_BOARD 0x0465
3268 +#define BCM94311MCAG_BOARD 0x0466
3269 +
3270 +#define BCM95352GR_BOARD 0x0467
3271 +
3272 +/* bcm95351agr */
3273 +#define BCM95351AGR_BOARD 0x0470
3274 +
3275 +/* bcm94704mpcb */
3276 +#define BCM94704MPCB_BOARD 0x0472
3277 +
3278 +/* 4785 boards */
3279 +#define BU4785_BOARD 0x0478
3280 +
3281 +/* 4321 boards */
3282 +#define BU4321_BOARD 0x046b
3283 +#define BU4321E_BOARD 0x047c
3284 +#define MP4321_BOARD 0x046c
3285 +#define CB2_4321_BOARD 0x046d
3286 +#define MC4321_BOARD 0x046e
3287 +
3288 +/* # of GPIO pins */
3289 +#define GPIO_NUMPINS 16
3290 +
3291 +/* radio ID codes */
3292 +#define NORADIO_ID 0xe4f5
3293 +#define NORADIO_IDCODE 0x4e4f5246
3294 +
3295 +#define BCM2050_ID 0x2050
3296 +#define BCM2050_IDCODE 0x02050000
3297 +#define BCM2050A0_IDCODE 0x1205017f
3298 +#define BCM2050A1_IDCODE 0x2205017f
3299 +#define BCM2050R8_IDCODE 0x8205017f
3300 +
3301 +#define BCM2055_ID 0x2055
3302 +#define BCM2055_IDCODE 0x02055000
3303 +#define BCM2055A0_IDCODE 0x1205517f
3304 +
3305 +#define BCM2060_ID 0x2060
3306 +#define BCM2060_IDCODE 0x02060000
3307 +#define BCM2060WW_IDCODE 0x1206017f
3308 +
3309 +#define BCM2062_ID 0x2062
3310 +#define BCM2062_IDCODE 0x02062000
3311 +#define BCM2062A0_IDCODE 0x0206217f
3312 +
3313 +/* parts of an idcode: */
3314 +#define IDCODE_MFG_MASK 0x00000fff
3315 +#define IDCODE_MFG_SHIFT 0
3316 +#define IDCODE_ID_MASK 0x0ffff000
3317 +#define IDCODE_ID_SHIFT 12
3318 +#define IDCODE_REV_MASK 0xf0000000
3319 +#define IDCODE_REV_SHIFT 28
3320 +
3321 +#endif /* _BCMDEVS_H */
3322 diff -urN linux.old/arch/mips/bcm947xx/include/bcmendian.h linux.dev/arch/mips/bcm947xx/include/bcmendian.h
3323 --- linux.old/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
3324 +++ linux.dev/arch/mips/bcm947xx/include/bcmendian.h 2006-10-02 21:19:59.000000000 +0200
3325 @@ -0,0 +1,198 @@
3326 +/*
3327 + * local version of endian.h - byte order defines
3328 + *
3329 + * Copyright 2006, Broadcom Corporation
3330 + * All Rights Reserved.
3331 + *
3332 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3333 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3334 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3335 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3336 + *
3337 + * $Id: bcmendian.h,v 1.1.1.10 2006/02/27 03:43:16 honor Exp $
3338 +*/
3339 +
3340 +#ifndef _BCMENDIAN_H_
3341 +#define _BCMENDIAN_H_
3342 +
3343 +#include <typedefs.h>
3344 +
3345 +/* Byte swap a 16 bit value */
3346 +#define BCMSWAP16(val) \
3347 + ((uint16)(\
3348 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
3349 + (((uint16)(val) & (uint16)0xff00U) >> 8)))
3350 +
3351 +/* Byte swap a 32 bit value */
3352 +#define BCMSWAP32(val) \
3353 + ((uint32)(\
3354 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
3355 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
3356 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
3357 + (((uint32)(val) & (uint32)0xff000000UL) >> 24)))
3358 +
3359 +/* 2 Byte swap a 32 bit value */
3360 +#define BCMSWAP32BY16(val) \
3361 + ((uint32)(\
3362 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
3363 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16)))
3364 +
3365 +
3366 +static INLINE uint16
3367 +bcmswap16(uint16 val)
3368 +{
3369 + return BCMSWAP16(val);
3370 +}
3371 +
3372 +static INLINE uint32
3373 +bcmswap32(uint32 val)
3374 +{
3375 + return BCMSWAP32(val);
3376 +}
3377 +
3378 +static INLINE uint32
3379 +bcmswap32by16(uint32 val)
3380 +{
3381 + return BCMSWAP32BY16(val);
3382 +}
3383 +
3384 +/* buf - start of buffer of shorts to swap */
3385 +/* len - byte length of buffer */
3386 +static INLINE void
3387 +bcmswap16_buf(uint16 *buf, uint len)
3388 +{
3389 + len = len/2;
3390 +
3391 + while (len--) {
3392 + *buf = bcmswap16(*buf);
3393 + buf++;
3394 + }
3395 +}
3396 +
3397 +#ifndef hton16
3398 +#ifndef IL_BIGENDIAN
3399 +#define HTON16(i) BCMSWAP16(i)
3400 +#define hton16(i) bcmswap16(i)
3401 +#define hton32(i) bcmswap32(i)
3402 +#define ntoh16(i) bcmswap16(i)
3403 +#define ntoh32(i) bcmswap32(i)
3404 +#define ltoh16(i) (i)
3405 +#define ltoh32(i) (i)
3406 +#define htol16(i) (i)
3407 +#define htol32(i) (i)
3408 +#else
3409 +#define HTON16(i) (i)
3410 +#define hton16(i) (i)
3411 +#define hton32(i) (i)
3412 +#define ntoh16(i) (i)
3413 +#define ntoh32(i) (i)
3414 +#define ltoh16(i) bcmswap16(i)
3415 +#define ltoh32(i) bcmswap32(i)
3416 +#define htol16(i) bcmswap16(i)
3417 +#define htol32(i) bcmswap32(i)
3418 +#endif /* IL_BIGENDIAN */
3419 +#endif /* hton16 */
3420 +
3421 +#ifndef IL_BIGENDIAN
3422 +#define ltoh16_buf(buf, i)
3423 +#define htol16_buf(buf, i)
3424 +#else
3425 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
3426 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
3427 +#endif /* IL_BIGENDIAN */
3428 +
3429 +/*
3430 +* store 16-bit value to unaligned little endian byte array.
3431 +*/
3432 +static INLINE void
3433 +htol16_ua_store(uint16 val, uint8 *bytes)
3434 +{
3435 + bytes[0] = val&0xff;
3436 + bytes[1] = val>>8;
3437 +}
3438 +
3439 +/*
3440 +* store 32-bit value to unaligned little endian byte array.
3441 +*/
3442 +static INLINE void
3443 +htol32_ua_store(uint32 val, uint8 *bytes)
3444 +{
3445 + bytes[0] = val&0xff;
3446 + bytes[1] = (val>>8)&0xff;
3447 + bytes[2] = (val>>16)&0xff;
3448 + bytes[3] = val>>24;
3449 +}
3450 +
3451 +/*
3452 +* store 16-bit value to unaligned network(big) endian byte array.
3453 +*/
3454 +static INLINE void
3455 +hton16_ua_store(uint16 val, uint8 *bytes)
3456 +{
3457 + bytes[1] = val&0xff;
3458 + bytes[0] = val>>8;
3459 +}
3460 +
3461 +/*
3462 +* store 32-bit value to unaligned network(big) endian byte array.
3463 +*/
3464 +static INLINE void
3465 +hton32_ua_store(uint32 val, uint8 *bytes)
3466 +{
3467 + bytes[3] = val&0xff;
3468 + bytes[2] = (val>>8)&0xff;
3469 + bytes[1] = (val>>16)&0xff;
3470 + bytes[0] = val>>24;
3471 +}
3472 +
3473 +/*
3474 +* load 16-bit value from unaligned little endian byte array.
3475 +*/
3476 +static INLINE uint16
3477 +ltoh16_ua(void *bytes)
3478 +{
3479 + return (((uint8*)bytes)[1]<<8)+((uint8 *)bytes)[0];
3480 +}
3481 +
3482 +/*
3483 +* load 32-bit value from unaligned little endian byte array.
3484 +*/
3485 +static INLINE uint32
3486 +ltoh32_ua(void *bytes)
3487 +{
3488 + return (((uint8*)bytes)[3]<<24)+(((uint8*)bytes)[2]<<16)+
3489 + (((uint8*)bytes)[1]<<8)+((uint8*)bytes)[0];
3490 +}
3491 +
3492 +/*
3493 +* load 16-bit value from unaligned big(network) endian byte array.
3494 +*/
3495 +static INLINE uint16
3496 +ntoh16_ua(void *bytes)
3497 +{
3498 + return (((uint8*)bytes)[0]<<8)+((uint8*)bytes)[1];
3499 +}
3500 +
3501 +/*
3502 +* load 32-bit value from unaligned big(network) endian byte array.
3503 +*/
3504 +static INLINE uint32
3505 +ntoh32_ua(void *bytes)
3506 +{
3507 + return (((uint8*)bytes)[0]<<24)+(((uint8*)bytes)[1]<<16)+
3508 + (((uint8*)bytes)[2]<<8)+((uint8*)bytes)[3];
3509 +}
3510 +
3511 +#define ltoh_ua(ptr) (\
3512 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
3513 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
3514 + (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
3515 +)
3516 +
3517 +#define ntoh_ua(ptr) (\
3518 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
3519 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
3520 + (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
3521 +)
3522 +
3523 +#endif /* _BCMENDIAN_H_ */
3524 diff -urN linux.old/arch/mips/bcm947xx/include/bcmnvram.h linux.dev/arch/mips/bcm947xx/include/bcmnvram.h
3525 --- linux.old/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
3526 +++ linux.dev/arch/mips/bcm947xx/include/bcmnvram.h 2006-10-02 21:19:59.000000000 +0200
3527 @@ -0,0 +1,159 @@
3528 +/*
3529 + * NVRAM variable manipulation
3530 + *
3531 + * Copyright 2006, Broadcom Corporation
3532 + * All Rights Reserved.
3533 + *
3534 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3535 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3536 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3537 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3538 + *
3539 + * $Id: bcmnvram.h,v 1.17 2006/03/02 12:33:44 honor Exp $
3540 + */
3541 +
3542 +#ifndef _bcmnvram_h_
3543 +#define _bcmnvram_h_
3544 +
3545 +#ifndef _LANGUAGE_ASSEMBLY
3546 +
3547 +#include <typedefs.h>
3548 +#include <bcmdefs.h>
3549 +
3550 +struct nvram_header {
3551 + uint32 magic;
3552 + uint32 len;
3553 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
3554 + uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
3555 + uint32 config_ncdl; /* ncdl values for memc */
3556 +};
3557 +
3558 +struct nvram_tuple {
3559 + char *name;
3560 + char *value;
3561 + struct nvram_tuple *next;
3562 +};
3563 +
3564 +/*
3565 + * Initialize NVRAM access. May be unnecessary or undefined on certain
3566 + * platforms.
3567 + */
3568 +extern int nvram_init(void *sbh);
3569 +
3570 +/*
3571 + * Disable NVRAM access. May be unnecessary or undefined on certain
3572 + * platforms.
3573 + */
3574 +extern void nvram_exit(void *sbh);
3575 +
3576 +/*
3577 + * Get the value of an NVRAM variable. The pointer returned may be
3578 + * invalid after a set.
3579 + * @param name name of variable to get
3580 + * @return value of variable or NULL if undefined
3581 + */
3582 +extern char * nvram_get(const char *name);
3583 +
3584 +/*
3585 + * Read the reset GPIO value from the nvram and set the GPIO
3586 + * as input
3587 + */
3588 +extern int BCMINITFN(nvram_resetgpio_init)(void *sbh);
3589 +extern int BCMINITFN(nvram_gpio_init)(const char *name, void *sbh);
3590 +extern int BCMINITFN(nvram_gpio_set)(const char *name, void *sbh, int type);
3591 +
3592 +/*
3593 + * Get the value of an NVRAM variable.
3594 + * @param name name of variable to get
3595 + * @return value of variable or NUL if undefined
3596 + */
3597 +#define nvram_safe_get(name) (nvram_get(name) ? : "")
3598 +
3599 +#define nvram_safe_unset(name) ({ \
3600 + if(nvram_get(name)) \
3601 + nvram_unset(name); \
3602 +})
3603 +
3604 +#define nvram_safe_set(name, value) ({ \
3605 + if(!nvram_get(name) || strcmp(nvram_get(name), value)) \
3606 + nvram_set(name, value); \
3607 +})
3608 +
3609 +/*
3610 + * Match an NVRAM variable.
3611 + * @param name name of variable to match
3612 + * @param match value to compare against value of variable
3613 + * @return TRUE if variable is defined and its value is string equal
3614 + * to match or FALSE otherwise
3615 + */
3616 +static INLINE int
3617 +nvram_match(char *name, char *match) {
3618 + const char *value = nvram_get(name);
3619 + return (value && !strcmp(value, match));
3620 +}
3621 +
3622 +/*
3623 + * Inversely match an NVRAM variable.
3624 + * @param name name of variable to match
3625 + * @param match value to compare against value of variable
3626 + * @return TRUE if variable is defined and its value is not string
3627 + * equal to invmatch or FALSE otherwise
3628 + */
3629 +static INLINE int
3630 +nvram_invmatch(char *name, char *invmatch) {
3631 + const char *value = nvram_get(name);
3632 + return (value && strcmp(value, invmatch));
3633 +}
3634 +
3635 +/*
3636 + * Set the value of an NVRAM variable. The name and value strings are
3637 + * copied into private storage. Pointers to previously set values
3638 + * may become invalid. The new value may be immediately
3639 + * retrieved but will not be permanently stored until a commit.
3640 + * @param name name of variable to set
3641 + * @param value value of variable
3642 + * @return 0 on success and errno on failure
3643 + */
3644 +extern int nvram_set(const char *name, const char *value);
3645 +
3646 +/*
3647 + * Unset an NVRAM variable. Pointers to previously set values
3648 + * remain valid until a set.
3649 + * @param name name of variable to unset
3650 + * @return 0 on success and errno on failure
3651 + * NOTE: use nvram_commit to commit this change to flash.
3652 + */
3653 +extern int nvram_unset(const char *name);
3654 +
3655 +/*
3656 + * Commit NVRAM variables to permanent storage. All pointers to values
3657 + * may be invalid after a commit.
3658 + * NVRAM values are undefined after a commit.
3659 + * @return 0 on success and errno on failure
3660 + */
3661 +extern int nvram_commit(void);
3662 +
3663 +/*
3664 + * Get all NVRAM variables (format name=value\0 ... \0\0).
3665 + * @param buf buffer to store variables
3666 + * @param count size of buffer in bytes
3667 + * @return 0 on success and errno on failure
3668 + */
3669 +extern int nvram_getall(char *buf, int count);
3670 +
3671 +extern int file2nvram(char *filename, char *varname);
3672 +extern int nvram2file(char *varname, char *filename);
3673 +
3674 +#endif /* _LANGUAGE_ASSEMBLY */
3675 +
3676 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
3677 +#define NVRAM_CLEAR_MAGIC 0x0
3678 +#define NVRAM_INVALID_MAGIC 0xFFFFFFFF
3679 +#define NVRAM_VERSION 1
3680 +#define NVRAM_HEADER_SIZE 20
3681 +#define NVRAM_SPACE 0x8000
3682 +
3683 +#define NVRAM_MAX_VALUE_LEN 255
3684 +#define NVRAM_MAX_PARAM_LEN 64
3685 +
3686 +#endif /* _bcmnvram_h_ */
3687 diff -urN linux.old/arch/mips/bcm947xx/include/bcmsrom.h linux.dev/arch/mips/bcm947xx/include/bcmsrom.h
3688 --- linux.old/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
3689 +++ linux.dev/arch/mips/bcm947xx/include/bcmsrom.h 2006-10-02 21:19:59.000000000 +0200
3690 @@ -0,0 +1,108 @@
3691 +/*
3692 + * Misc useful routines to access NIC local SROM/OTP .
3693 + *
3694 + * Copyright 2006, Broadcom Corporation
3695 + * All Rights Reserved.
3696 + *
3697 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3698 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3699 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3700 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3701 + *
3702 + * $Id: bcmsrom.h,v 1.1.1.13 2006/04/15 01:29:08 michael Exp $
3703 + */
3704 +
3705 +#ifndef _bcmsrom_h_
3706 +#define _bcmsrom_h_
3707 +
3708 +/* Maximum srom: 4 Kilobits == 512 bytes */
3709 +#define SROM_MAX 512
3710 +
3711 +/* SROM Rev 4: Reallocate the software part of the srom to accomodate
3712 + * MIMO features. It assumes up to two PCIE functions and 440 bytes
3713 + * of useable srom i.e. the useable storage in chips with OTP that
3714 + * implements hardware redundancy.
3715 + */
3716 +
3717 +#define SROM4_WORDS 220
3718 +
3719 +#define SROM4_SIGN 32
3720 +#define SROM4_SIGNATURE 0x5372
3721 +
3722 +#define SROM4_BREV 33
3723 +
3724 +#define SROM4_BFL0 34
3725 +#define SROM4_BFL1 35
3726 +#define SROM4_BFL2 36
3727 +#define SROM4_BFL3 37
3728 +
3729 +#define SROM4_MACHI 38
3730 +#define SROM4_MACMID 39
3731 +#define SROM4_MACLO 40
3732 +
3733 +#define SROM4_CCODE 41
3734 +#define SROM4_REGREV 42
3735 +
3736 +#define SROM4_LEDBH10 43
3737 +#define SROM4_LEDBH32 44
3738 +
3739 +#define SROM4_LEDDC 45
3740 +
3741 +#define SROM4_AA 46
3742 +#define SROM4_AA2G_MASK 0x00ff
3743 +#define SROM4_AA2G_SHIFT 0
3744 +#define SROM4_AA5G_MASK 0xff00
3745 +#define SROM4_AA5G_SHIFT 8
3746 +
3747 +#define SROM4_AG10 47
3748 +#define SROM4_AG32 48
3749 +
3750 +#define SROM4_TXPID2G 49
3751 +#define SROM4_TXPID5G 51