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[openwrt/openwrt.git] / target / linux / brcm2708 / patches-4.1 / 0001-Main-bcm2708-bcm2709-linux-port.patch
1 From 6f0468a9f44474189135066bbeb8eecf8d99bebf Mon Sep 17 00:00:00 2001
2 From: popcornmix <popcornmix@gmail.com>
3 Date: Sun, 12 May 2013 12:24:19 +0100
4 Subject: [PATCH 001/148] Main bcm2708/bcm2709 linux port
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
8
9 Signed-off-by: popcornmix <popcornmix@gmail.com>
10 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
11 ---
12 arch/arm/Kconfig | 39 ++
13 arch/arm/Kconfig.debug | 8 +
14 arch/arm/Makefile | 2 +
15 arch/arm/kernel/head.S | 8 +
16 arch/arm/kernel/process.c | 10 +
17 arch/arm/mach-bcm2708/Kconfig | 30 +
18 arch/arm/mach-bcm2708/Makefile | 5 +
19 arch/arm/mach-bcm2708/Makefile.boot | 3 +
20 arch/arm/mach-bcm2708/armctrl.c | 304 +++++++++
21 arch/arm/mach-bcm2708/armctrl.h | 27 +
22 arch/arm/mach-bcm2708/bcm2708.c | 622 ++++++++++++++++++
23 arch/arm/mach-bcm2708/bcm2708.h | 49 ++
24 arch/arm/mach-bcm2708/include/mach/arm_control.h | 419 ++++++++++++
25 arch/arm/mach-bcm2708/include/mach/clkdev.h | 7 +
26 arch/arm/mach-bcm2708/include/mach/debug-macro.S | 22 +
27 arch/arm/mach-bcm2708/include/mach/entry-macro.S | 69 ++
28 arch/arm/mach-bcm2708/include/mach/frc.h | 38 ++
29 arch/arm/mach-bcm2708/include/mach/hardware.h | 28 +
30 arch/arm/mach-bcm2708/include/mach/io.h | 27 +
31 arch/arm/mach-bcm2708/include/mach/irqs.h | 196 ++++++
32 arch/arm/mach-bcm2708/include/mach/memory.h | 57 ++
33 arch/arm/mach-bcm2708/include/mach/platform.h | 228 +++++++
34 arch/arm/mach-bcm2708/include/mach/system.h | 38 ++
35 arch/arm/mach-bcm2708/include/mach/timex.h | 23 +
36 arch/arm/mach-bcm2708/include/mach/uncompress.h | 84 +++
37 arch/arm/mach-bcm2708/include/mach/vmalloc.h | 20 +
38 arch/arm/mach-bcm2709/Kconfig | 42 ++
39 arch/arm/mach-bcm2709/Makefile | 6 +
40 arch/arm/mach-bcm2709/Makefile.boot | 3 +
41 arch/arm/mach-bcm2709/armctrl.c | 361 ++++++++++
42 arch/arm/mach-bcm2709/armctrl.h | 27 +
43 arch/arm/mach-bcm2709/bcm2708_gpio.c | 426 ++++++++++++
44 arch/arm/mach-bcm2709/bcm2709.c | 801 +++++++++++++++++++++++
45 arch/arm/mach-bcm2709/bcm2709.h | 49 ++
46 arch/arm/mach-bcm2709/delay.S | 21 +
47 arch/arm/mach-bcm2709/include/mach/arm_control.h | 493 ++++++++++++++
48 arch/arm/mach-bcm2709/include/mach/barriers.h | 3 +
49 arch/arm/mach-bcm2709/include/mach/clkdev.h | 7 +
50 arch/arm/mach-bcm2709/include/mach/debug-macro.S | 22 +
51 arch/arm/mach-bcm2709/include/mach/entry-macro.S | 123 ++++
52 arch/arm/mach-bcm2709/include/mach/frc.h | 38 ++
53 arch/arm/mach-bcm2709/include/mach/gpio.h | 17 +
54 arch/arm/mach-bcm2709/include/mach/hardware.h | 28 +
55 arch/arm/mach-bcm2709/include/mach/io.h | 27 +
56 arch/arm/mach-bcm2709/include/mach/irqs.h | 225 +++++++
57 arch/arm/mach-bcm2709/include/mach/memory.h | 57 ++
58 arch/arm/mach-bcm2709/include/mach/platform.h | 225 +++++++
59 arch/arm/mach-bcm2709/include/mach/system.h | 38 ++
60 arch/arm/mach-bcm2709/include/mach/timex.h | 23 +
61 arch/arm/mach-bcm2709/include/mach/uncompress.h | 84 +++
62 arch/arm/mach-bcm2709/include/mach/vc_mem.h | 35 +
63 arch/arm/mach-bcm2709/include/mach/vc_support.h | 69 ++
64 arch/arm/mach-bcm2709/include/mach/vmalloc.h | 20 +
65 arch/arm/mach-bcm2709/vc_mem.c | 431 ++++++++++++
66 arch/arm/mach-bcm2709/vc_support.c | 318 +++++++++
67 arch/arm/mm/Kconfig | 2 +-
68 arch/arm/mm/proc-v6.S | 15 +-
69 arch/arm/mm/proc-v7.S | 1 +
70 arch/arm/tools/mach-types | 2 +
71 drivers/clocksource/arm_arch_timer.c | 36 +
72 drivers/tty/serial/amba-pl011.c | 2 +-
73 include/linux/mmc/host.h | 1 +
74 62 files changed, 6436 insertions(+), 5 deletions(-)
75 create mode 100644 arch/arm/mach-bcm2708/Kconfig
76 create mode 100644 arch/arm/mach-bcm2708/Makefile
77 create mode 100644 arch/arm/mach-bcm2708/Makefile.boot
78 create mode 100644 arch/arm/mach-bcm2708/armctrl.c
79 create mode 100644 arch/arm/mach-bcm2708/armctrl.h
80 create mode 100644 arch/arm/mach-bcm2708/bcm2708.c
81 create mode 100644 arch/arm/mach-bcm2708/bcm2708.h
82 create mode 100644 arch/arm/mach-bcm2708/include/mach/arm_control.h
83 create mode 100644 arch/arm/mach-bcm2708/include/mach/clkdev.h
84 create mode 100644 arch/arm/mach-bcm2708/include/mach/debug-macro.S
85 create mode 100644 arch/arm/mach-bcm2708/include/mach/entry-macro.S
86 create mode 100644 arch/arm/mach-bcm2708/include/mach/frc.h
87 create mode 100644 arch/arm/mach-bcm2708/include/mach/hardware.h
88 create mode 100644 arch/arm/mach-bcm2708/include/mach/io.h
89 create mode 100644 arch/arm/mach-bcm2708/include/mach/irqs.h
90 create mode 100644 arch/arm/mach-bcm2708/include/mach/memory.h
91 create mode 100644 arch/arm/mach-bcm2708/include/mach/platform.h
92 create mode 100644 arch/arm/mach-bcm2708/include/mach/system.h
93 create mode 100644 arch/arm/mach-bcm2708/include/mach/timex.h
94 create mode 100644 arch/arm/mach-bcm2708/include/mach/uncompress.h
95 create mode 100644 arch/arm/mach-bcm2708/include/mach/vmalloc.h
96 create mode 100644 arch/arm/mach-bcm2709/Kconfig
97 create mode 100644 arch/arm/mach-bcm2709/Makefile
98 create mode 100644 arch/arm/mach-bcm2709/Makefile.boot
99 create mode 100644 arch/arm/mach-bcm2709/armctrl.c
100 create mode 100644 arch/arm/mach-bcm2709/armctrl.h
101 create mode 100644 arch/arm/mach-bcm2709/bcm2708_gpio.c
102 create mode 100644 arch/arm/mach-bcm2709/bcm2709.c
103 create mode 100644 arch/arm/mach-bcm2709/bcm2709.h
104 create mode 100644 arch/arm/mach-bcm2709/delay.S
105 create mode 100644 arch/arm/mach-bcm2709/include/mach/arm_control.h
106 create mode 100644 arch/arm/mach-bcm2709/include/mach/barriers.h
107 create mode 100644 arch/arm/mach-bcm2709/include/mach/clkdev.h
108 create mode 100644 arch/arm/mach-bcm2709/include/mach/debug-macro.S
109 create mode 100644 arch/arm/mach-bcm2709/include/mach/entry-macro.S
110 create mode 100644 arch/arm/mach-bcm2709/include/mach/frc.h
111 create mode 100644 arch/arm/mach-bcm2709/include/mach/gpio.h
112 create mode 100644 arch/arm/mach-bcm2709/include/mach/hardware.h
113 create mode 100644 arch/arm/mach-bcm2709/include/mach/io.h
114 create mode 100644 arch/arm/mach-bcm2709/include/mach/irqs.h
115 create mode 100644 arch/arm/mach-bcm2709/include/mach/memory.h
116 create mode 100644 arch/arm/mach-bcm2709/include/mach/platform.h
117 create mode 100644 arch/arm/mach-bcm2709/include/mach/system.h
118 create mode 100644 arch/arm/mach-bcm2709/include/mach/timex.h
119 create mode 100644 arch/arm/mach-bcm2709/include/mach/uncompress.h
120 create mode 100644 arch/arm/mach-bcm2709/include/mach/vc_mem.h
121 create mode 100755 arch/arm/mach-bcm2709/include/mach/vc_support.h
122 create mode 100644 arch/arm/mach-bcm2709/include/mach/vmalloc.h
123 create mode 100644 arch/arm/mach-bcm2709/vc_mem.c
124 create mode 100644 arch/arm/mach-bcm2709/vc_support.c
125
126 --- a/arch/arm/Kconfig
127 +++ b/arch/arm/Kconfig
128 @@ -314,6 +314,42 @@ choice
129 default ARCH_VERSATILE if !MMU
130 default ARCH_MULTIPLATFORM if MMU
131
132 +config ARCH_BCM2708
133 + bool "Broadcom BCM2708 family"
134 + select CPU_V6
135 + select ARM_AMBA
136 + select HAVE_SCHED_CLOCK
137 + select NEED_MACH_GPIO_H
138 + select NEED_MACH_MEMORY_H
139 + select COMMON_CLK
140 + select ARCH_HAS_CPUFREQ
141 + select GENERIC_CLOCKEVENTS
142 + select ARM_ERRATA_411920
143 + select MACH_BCM2708
144 + select VC4
145 + select FIQ
146 + help
147 + This enables support for Broadcom BCM2708 boards.
148 +
149 +config ARCH_BCM2709
150 + bool "Broadcom BCM2709 family"
151 + select ARCH_HAS_BARRIERS if SMP
152 + select CPU_V7
153 + select HAVE_SMP
154 + select ARM_AMBA
155 + select MIGHT_HAVE_CACHE_L2X0
156 + select HAVE_SCHED_CLOCK
157 + select NEED_MACH_MEMORY_H
158 + select NEED_MACH_IO_H
159 + select COMMON_CLK
160 + select ARCH_HAS_CPUFREQ
161 + select GENERIC_CLOCKEVENTS
162 + select MACH_BCM2709
163 + select VC4
164 + select FIQ
165 + help
166 + This enables support for Broadcom BCM2709 boards.
167 +
168 config ARCH_MULTIPLATFORM
169 bool "Allow multiple platforms to be selected"
170 depends on MMU
171 @@ -823,6 +859,9 @@ config ARCH_VIRT
172 # Kconfigs may be included either alphabetically (according to the
173 # plat- suffix) or along side the corresponding mach-* source.
174 #
175 +source "arch/arm/mach-bcm2708/Kconfig"
176 +source "arch/arm/mach-bcm2709/Kconfig"
177 +
178 source "arch/arm/mach-mvebu/Kconfig"
179
180 source "arch/arm/mach-alpine/Kconfig"
181 --- a/arch/arm/Kconfig.debug
182 +++ b/arch/arm/Kconfig.debug
183 @@ -1197,6 +1197,14 @@ choice
184 options; the platform specific options are deprecated
185 and will be soon removed.
186
187 + config DEBUG_BCM2708_UART0
188 + bool "Broadcom BCM2708 UART0 (PL011)"
189 + depends on MACH_BCM2708
190 + help
191 + Say Y here if you want the debug print routines to direct
192 + their output to UART 0. The port must have been initialised
193 + by the boot-loader before use.
194 +
195 endchoice
196
197 config DEBUG_AT91_UART
198 --- a/arch/arm/Makefile
199 +++ b/arch/arm/Makefile
200 @@ -147,6 +147,8 @@ textofs-$(CONFIG_ARCH_AXXIA) := 0x003080
201
202 # Machine directory name. This list is sorted alphanumerically
203 # by CONFIG_* macro name.
204 +machine-$(CONFIG_ARCH_BCM2708) += bcm2708
205 +machine-$(CONFIG_ARCH_BCM2709) += bcm2709
206 machine-$(CONFIG_ARCH_ALPINE) += alpine
207 machine-$(CONFIG_ARCH_AT91) += at91
208 machine-$(CONFIG_ARCH_AXXIA) += axxia
209 --- a/arch/arm/kernel/head.S
210 +++ b/arch/arm/kernel/head.S
211 @@ -680,6 +680,14 @@ ARM_BE8(rev16 ip, ip)
212 ldrcc r7, [r4], #4 @ use branch for delay slot
213 bcc 1b
214 ret lr
215 + nop
216 + nop
217 + nop
218 + nop
219 + nop
220 + nop
221 + nop
222 + nop
223 #endif
224 ENDPROC(__fixup_a_pv_table)
225
226 --- a/arch/arm/kernel/process.c
227 +++ b/arch/arm/kernel/process.c
228 @@ -98,6 +98,16 @@ void arch_cpu_idle_dead(void)
229 }
230 #endif
231
232 +char bcm2708_reboot_mode = 'h';
233 +
234 +int __init reboot_setup(char *str)
235 +{
236 + bcm2708_reboot_mode = str[0];
237 + return 1;
238 +}
239 +
240 +__setup("reboot=", reboot_setup);
241 +
242 void __show_regs(struct pt_regs *regs)
243 {
244 unsigned long flags;
245 --- /dev/null
246 +++ b/arch/arm/mach-bcm2708/Kconfig
247 @@ -0,0 +1,30 @@
248 +menu "Broadcom BCM2708 Implementations"
249 + depends on ARCH_BCM2708
250 +
251 +config MACH_BCM2708
252 + bool "Broadcom BCM2708 Development Platform"
253 + select NEED_MACH_MEMORY_H
254 + select NEED_MACH_IO_H
255 + select CPU_V6
256 + help
257 + Include support for the Broadcom(R) BCM2708 platform.
258 +
259 +config BCM2708_DT
260 + bool "BCM2708 Device Tree support"
261 + depends on MACH_BCM2708
262 + default n
263 + select USE_OF
264 + select ARCH_REQUIRE_GPIOLIB
265 + select PINCTRL
266 + select PINCTRL_BCM2835
267 + help
268 + Enable Device Tree support for BCM2708
269 +
270 +config BCM2708_NOL2CACHE
271 + bool "Videocore L2 cache disable"
272 + depends on MACH_BCM2708
273 + default n
274 + help
275 + Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
276 +
277 +endmenu
278 --- /dev/null
279 +++ b/arch/arm/mach-bcm2708/Makefile
280 @@ -0,0 +1,5 @@
281 +#
282 +# Makefile for the linux kernel.
283 +#
284 +
285 +obj-$(CONFIG_MACH_BCM2708) += bcm2708.o armctrl.o
286 --- /dev/null
287 +++ b/arch/arm/mach-bcm2708/Makefile.boot
288 @@ -0,0 +1,3 @@
289 + zreladdr-y := 0x00008000
290 +params_phys-y := 0x00000100
291 +initrd_phys-y := 0x00800000
292 --- /dev/null
293 +++ b/arch/arm/mach-bcm2708/armctrl.c
294 @@ -0,0 +1,304 @@
295 +/*
296 + * linux/arch/arm/mach-bcm2708/armctrl.c
297 + *
298 + * Copyright (C) 2010 Broadcom
299 + *
300 + * This program is free software; you can redistribute it and/or modify
301 + * it under the terms of the GNU General Public License as published by
302 + * the Free Software Foundation; either version 2 of the License, or
303 + * (at your option) any later version.
304 + *
305 + * This program is distributed in the hope that it will be useful,
306 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
307 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
308 + * GNU General Public License for more details.
309 + *
310 + * You should have received a copy of the GNU General Public License
311 + * along with this program; if not, write to the Free Software
312 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
313 + */
314 +#include <linux/init.h>
315 +#include <linux/list.h>
316 +#include <linux/io.h>
317 +#include <linux/version.h>
318 +#include <linux/syscore_ops.h>
319 +#include <linux/interrupt.h>
320 +#include <linux/irqdomain.h>
321 +#include <linux/of.h>
322 +
323 +#include <asm/mach/irq.h>
324 +#include <mach/hardware.h>
325 +#include "armctrl.h"
326 +
327 +/* For support of kernels >= 3.0 assume only one VIC for now*/
328 +static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = {
329 + INTERRUPT_VC_JPEG,
330 + INTERRUPT_VC_USB,
331 + INTERRUPT_VC_3D,
332 + INTERRUPT_VC_DMA2,
333 + INTERRUPT_VC_DMA3,
334 + INTERRUPT_VC_I2C,
335 + INTERRUPT_VC_SPI,
336 + INTERRUPT_VC_I2SPCM,
337 + INTERRUPT_VC_SDIO,
338 + INTERRUPT_VC_UART,
339 + INTERRUPT_VC_ARASANSDIO
340 +};
341 +
342 +static void armctrl_mask_irq(struct irq_data *d)
343 +{
344 + static const unsigned int disables[4] = {
345 + ARM_IRQ_DIBL1,
346 + ARM_IRQ_DIBL2,
347 + ARM_IRQ_DIBL3,
348 + 0
349 + };
350 +
351 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
352 + writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3]));
353 +}
354 +
355 +static void armctrl_unmask_irq(struct irq_data *d)
356 +{
357 + static const unsigned int enables[4] = {
358 + ARM_IRQ_ENBL1,
359 + ARM_IRQ_ENBL2,
360 + ARM_IRQ_ENBL3,
361 + 0
362 + };
363 +
364 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
365 + writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3]));
366 +}
367 +
368 +#ifdef CONFIG_OF
369 +
370 +#define NR_IRQS_BANK0 21
371 +#define NR_BANKS 3
372 +#define IRQS_PER_BANK 32
373 +
374 +/* from drivers/irqchip/irq-bcm2835.c */
375 +static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
376 + const u32 *intspec, unsigned int intsize,
377 + unsigned long *out_hwirq, unsigned int *out_type)
378 +{
379 + if (WARN_ON(intsize != 2))
380 + return -EINVAL;
381 +
382 + if (WARN_ON(intspec[0] >= NR_BANKS))
383 + return -EINVAL;
384 +
385 + if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
386 + return -EINVAL;
387 +
388 + if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
389 + return -EINVAL;
390 +
391 + if (intspec[0] == 0)
392 + *out_hwirq = ARM_IRQ0_BASE + intspec[1];
393 + else if (intspec[0] == 1)
394 + *out_hwirq = ARM_IRQ1_BASE + intspec[1];
395 + else
396 + *out_hwirq = ARM_IRQ2_BASE + intspec[1];
397 +
398 + /* reverse remap_irqs[] */
399 + switch (*out_hwirq) {
400 + case INTERRUPT_VC_JPEG:
401 + *out_hwirq = INTERRUPT_JPEG;
402 + break;
403 + case INTERRUPT_VC_USB:
404 + *out_hwirq = INTERRUPT_USB;
405 + break;
406 + case INTERRUPT_VC_3D:
407 + *out_hwirq = INTERRUPT_3D;
408 + break;
409 + case INTERRUPT_VC_DMA2:
410 + *out_hwirq = INTERRUPT_DMA2;
411 + break;
412 + case INTERRUPT_VC_DMA3:
413 + *out_hwirq = INTERRUPT_DMA3;
414 + break;
415 + case INTERRUPT_VC_I2C:
416 + *out_hwirq = INTERRUPT_I2C;
417 + break;
418 + case INTERRUPT_VC_SPI:
419 + *out_hwirq = INTERRUPT_SPI;
420 + break;
421 + case INTERRUPT_VC_I2SPCM:
422 + *out_hwirq = INTERRUPT_I2SPCM;
423 + break;
424 + case INTERRUPT_VC_SDIO:
425 + *out_hwirq = INTERRUPT_SDIO;
426 + break;
427 + case INTERRUPT_VC_UART:
428 + *out_hwirq = INTERRUPT_UART;
429 + break;
430 + case INTERRUPT_VC_ARASANSDIO:
431 + *out_hwirq = INTERRUPT_ARASANSDIO;
432 + break;
433 + }
434 +
435 + *out_type = IRQ_TYPE_NONE;
436 + return 0;
437 +}
438 +
439 +static struct irq_domain_ops armctrl_ops = {
440 + .xlate = armctrl_xlate
441 +};
442 +
443 +void __init armctrl_dt_init(void)
444 +{
445 + struct device_node *np;
446 + struct irq_domain *domain;
447 +
448 + np = of_find_compatible_node(NULL, NULL, "brcm,bcm2708-armctrl-ic");
449 + if (!np)
450 + return;
451 +
452 + domain = irq_domain_add_legacy(np, BCM2708_ALLOC_IRQS,
453 + IRQ_ARMCTRL_START, 0,
454 + &armctrl_ops, NULL);
455 + WARN_ON(!domain);
456 +}
457 +#else
458 +void __init armctrl_dt_init(void) { }
459 +#endif /* CONFIG_OF */
460 +
461 +#if defined(CONFIG_PM)
462 +
463 +/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */
464 +
465 +/* Static defines
466 + * struct armctrl_device - VIC PM device (< 3.xx)
467 + * @sysdev: The system device which is registered. (< 3.xx)
468 + * @irq: The IRQ number for the base of the VIC.
469 + * @base: The register base for the VIC.
470 + * @resume_sources: A bitmask of interrupts for resume.
471 + * @resume_irqs: The IRQs enabled for resume.
472 + * @int_select: Save for VIC_INT_SELECT.
473 + * @int_enable: Save for VIC_INT_ENABLE.
474 + * @soft_int: Save for VIC_INT_SOFT.
475 + * @protect: Save for VIC_PROTECT.
476 + */
477 +struct armctrl_info {
478 + void __iomem *base;
479 + int irq;
480 + u32 resume_sources;
481 + u32 resume_irqs;
482 + u32 int_select;
483 + u32 int_enable;
484 + u32 soft_int;
485 + u32 protect;
486 +} armctrl;
487 +
488 +static int armctrl_suspend(void)
489 +{
490 + return 0;
491 +}
492 +
493 +static void armctrl_resume(void)
494 +{
495 + return;
496 +}
497 +
498 +/**
499 + * armctrl_pm_register - Register a VIC for later power management control
500 + * @base: The base address of the VIC.
501 + * @irq: The base IRQ for the VIC.
502 + * @resume_sources: bitmask of interrupts allowed for resume sources.
503 + *
504 + * For older kernels (< 3.xx) do -
505 + * Register the VIC with the system device tree so that it can be notified
506 + * of suspend and resume requests and ensure that the correct actions are
507 + * taken to re-instate the settings on resume.
508 + */
509 +static void __init armctrl_pm_register(void __iomem * base, unsigned int irq,
510 + u32 resume_sources)
511 +{
512 + armctrl.base = base;
513 + armctrl.resume_sources = resume_sources;
514 + armctrl.irq = irq;
515 +}
516 +
517 +static int armctrl_set_wake(struct irq_data *d, unsigned int on)
518 +{
519 + unsigned int off = d->irq & 31;
520 + u32 bit = 1 << off;
521 +
522 + if (!(bit & armctrl.resume_sources))
523 + return -EINVAL;
524 +
525 + if (on)
526 + armctrl.resume_irqs |= bit;
527 + else
528 + armctrl.resume_irqs &= ~bit;
529 +
530 + return 0;
531 +}
532 +
533 +#else
534 +static inline void armctrl_pm_register(void __iomem * base, unsigned int irq,
535 + u32 arg1)
536 +{
537 +}
538 +
539 +#define armctrl_suspend NULL
540 +#define armctrl_resume NULL
541 +#define armctrl_set_wake NULL
542 +#endif /* CONFIG_PM */
543 +
544 +static struct syscore_ops armctrl_syscore_ops = {
545 + .suspend = armctrl_suspend,
546 + .resume = armctrl_resume,
547 +};
548 +
549 +/**
550 + * armctrl_syscore_init - initicall to register VIC pm functions
551 + *
552 + * This is called via late_initcall() to register
553 + * the resources for the VICs due to the early
554 + * nature of the VIC's registration.
555 +*/
556 +static int __init armctrl_syscore_init(void)
557 +{
558 + register_syscore_ops(&armctrl_syscore_ops);
559 + return 0;
560 +}
561 +
562 +late_initcall(armctrl_syscore_init);
563 +
564 +static struct irq_chip armctrl_chip = {
565 + .name = "ARMCTRL",
566 + .irq_ack = NULL,
567 + .irq_mask = armctrl_mask_irq,
568 + .irq_unmask = armctrl_unmask_irq,
569 + .irq_set_wake = armctrl_set_wake,
570 +};
571 +
572 +/**
573 + * armctrl_init - initialise a vectored interrupt controller
574 + * @base: iomem base address
575 + * @irq_start: starting interrupt number, must be muliple of 32
576 + * @armctrl_sources: bitmask of interrupt sources to allow
577 + * @resume_sources: bitmask of interrupt sources to allow for resume
578 + */
579 +int __init armctrl_init(void __iomem * base, unsigned int irq_start,
580 + u32 armctrl_sources, u32 resume_sources)
581 +{
582 + unsigned int irq;
583 +
584 + for (irq = 0; irq < BCM2708_ALLOC_IRQS; irq++) {
585 + unsigned int data = irq;
586 + if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO)
587 + data = remap_irqs[irq - INTERRUPT_JPEG];
588 +
589 + irq_set_chip(irq, &armctrl_chip);
590 + irq_set_chip_data(irq, (void *)data);
591 + irq_set_handler(irq, handle_level_irq);
592 + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
593 + }
594 +
595 + armctrl_pm_register(base, irq_start, resume_sources);
596 + armctrl_dt_init();
597 + return 0;
598 +}
599 --- /dev/null
600 +++ b/arch/arm/mach-bcm2708/armctrl.h
601 @@ -0,0 +1,27 @@
602 +/*
603 + * linux/arch/arm/mach-bcm2708/armctrl.h
604 + *
605 + * Copyright (C) 2010 Broadcom
606 + *
607 + * This program is free software; you can redistribute it and/or modify
608 + * it under the terms of the GNU General Public License as published by
609 + * the Free Software Foundation; either version 2 of the License, or
610 + * (at your option) any later version.
611 + *
612 + * This program is distributed in the hope that it will be useful,
613 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
614 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
615 + * GNU General Public License for more details.
616 + *
617 + * You should have received a copy of the GNU General Public License
618 + * along with this program; if not, write to the Free Software
619 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
620 + */
621 +
622 +#ifndef __BCM2708_ARMCTRL_H
623 +#define __BCM2708_ARMCTRL_H
624 +
625 +extern int __init armctrl_init(void __iomem * base, unsigned int irq_start,
626 + u32 armctrl_sources, u32 resume_sources);
627 +
628 +#endif
629 --- /dev/null
630 +++ b/arch/arm/mach-bcm2708/bcm2708.c
631 @@ -0,0 +1,622 @@
632 +/*
633 + * linux/arch/arm/mach-bcm2708/bcm2708.c
634 + *
635 + * Copyright (C) 2010 Broadcom
636 + *
637 + * This program is free software; you can redistribute it and/or modify
638 + * it under the terms of the GNU General Public License as published by
639 + * the Free Software Foundation; either version 2 of the License, or
640 + * (at your option) any later version.
641 + *
642 + * This program is distributed in the hope that it will be useful,
643 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
644 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
645 + * GNU General Public License for more details.
646 + *
647 + * You should have received a copy of the GNU General Public License
648 + * along with this program; if not, write to the Free Software
649 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
650 + */
651 +
652 +#include <linux/init.h>
653 +#include <linux/device.h>
654 +#include <linux/dma-mapping.h>
655 +#include <linux/serial_8250.h>
656 +#include <linux/platform_device.h>
657 +#include <linux/syscore_ops.h>
658 +#include <linux/interrupt.h>
659 +#include <linux/amba/bus.h>
660 +#include <linux/amba/clcd.h>
661 +#include <linux/clk-provider.h>
662 +#include <linux/clkdev.h>
663 +#include <linux/clockchips.h>
664 +#include <linux/cnt32_to_63.h>
665 +#include <linux/io.h>
666 +#include <linux/module.h>
667 +#include <linux/of_platform.h>
668 +#include <linux/gpio/machine.h>
669 +
670 +#include <linux/version.h>
671 +#include <linux/clkdev.h>
672 +#include <asm/system_info.h>
673 +#include <mach/hardware.h>
674 +#include <asm/irq.h>
675 +#include <linux/leds.h>
676 +#include <asm/mach-types.h>
677 +#include <linux/sched_clock.h>
678 +
679 +#include <asm/mach/arch.h>
680 +#include <asm/mach/flash.h>
681 +#include <asm/mach/irq.h>
682 +#include <asm/mach/time.h>
683 +#include <asm/mach/map.h>
684 +
685 +#include <mach/timex.h>
686 +#include <mach/system.h>
687 +
688 +#include <linux/delay.h>
689 +
690 +#include "bcm2708.h"
691 +#include "armctrl.h"
692 +
693 +#ifdef CONFIG_BCM_VC_CMA
694 +#include <linux/broadcom/vc_cma.h>
695 +#endif
696 +
697 +
698 +/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
699 + * give us IO access only to 64Mbytes of physical memory (26 bits). We could
700 + * represent this window by setting our dmamasks to 26 bits but, in fact
701 + * we're not going to use addresses outside this range (they're not in real
702 + * memory) so we don't bother.
703 + *
704 + * In the future we might include code to use this IOMMU to remap other
705 + * physical addresses onto VideoCore memory then the use of 32-bits would be
706 + * more legitimate.
707 + */
708 +#define DMA_MASK_BITS_COMMON 32
709 +
710 +/* command line parameters */
711 +static unsigned boardrev, serial;
712 +static unsigned uart_clock = UART0_CLOCK;
713 +static unsigned disk_led_gpio = 16;
714 +static unsigned disk_led_active_low = 1;
715 +static unsigned reboot_part = 0;
716 +
717 +static unsigned use_dt = 0;
718 +
719 +static void __init bcm2708_init_led(void);
720 +
721 +void __init bcm2708_init_irq(void)
722 +{
723 + armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0);
724 +}
725 +
726 +static struct map_desc bcm2708_io_desc[] __initdata = {
727 + {
728 + .virtual = IO_ADDRESS(ARMCTRL_BASE),
729 + .pfn = __phys_to_pfn(ARMCTRL_BASE),
730 + .length = SZ_4K,
731 + .type = MT_DEVICE},
732 + {
733 + .virtual = IO_ADDRESS(UART0_BASE),
734 + .pfn = __phys_to_pfn(UART0_BASE),
735 + .length = SZ_4K,
736 + .type = MT_DEVICE},
737 + {
738 + .virtual = IO_ADDRESS(UART1_BASE),
739 + .pfn = __phys_to_pfn(UART1_BASE),
740 + .length = SZ_4K,
741 + .type = MT_DEVICE},
742 + {
743 + .virtual = IO_ADDRESS(DMA_BASE),
744 + .pfn = __phys_to_pfn(DMA_BASE),
745 + .length = SZ_4K,
746 + .type = MT_DEVICE},
747 + {
748 + .virtual = IO_ADDRESS(MCORE_BASE),
749 + .pfn = __phys_to_pfn(MCORE_BASE),
750 + .length = SZ_4K,
751 + .type = MT_DEVICE},
752 + {
753 + .virtual = IO_ADDRESS(ST_BASE),
754 + .pfn = __phys_to_pfn(ST_BASE),
755 + .length = SZ_4K,
756 + .type = MT_DEVICE},
757 + {
758 + .virtual = IO_ADDRESS(USB_BASE),
759 + .pfn = __phys_to_pfn(USB_BASE),
760 + .length = SZ_128K,
761 + .type = MT_DEVICE},
762 + {
763 + .virtual = IO_ADDRESS(PM_BASE),
764 + .pfn = __phys_to_pfn(PM_BASE),
765 + .length = SZ_4K,
766 + .type = MT_DEVICE},
767 + {
768 + .virtual = IO_ADDRESS(GPIO_BASE),
769 + .pfn = __phys_to_pfn(GPIO_BASE),
770 + .length = SZ_4K,
771 + .type = MT_DEVICE}
772 +};
773 +
774 +void __init bcm2708_map_io(void)
775 +{
776 + iotable_init(bcm2708_io_desc, ARRAY_SIZE(bcm2708_io_desc));
777 +}
778 +
779 +/* The STC is a free running counter that increments at the rate of 1MHz */
780 +#define STC_FREQ_HZ 1000000
781 +
782 +static inline uint32_t timer_read(void)
783 +{
784 + /* STC: a free running counter that increments at the rate of 1MHz */
785 + return readl(__io_address(ST_BASE + 0x04));
786 +}
787 +
788 +static unsigned long bcm2708_read_current_timer(void)
789 +{
790 + return timer_read();
791 +}
792 +
793 +static u64 notrace bcm2708_read_sched_clock(void)
794 +{
795 + return timer_read();
796 +}
797 +
798 +static cycle_t clksrc_read(struct clocksource *cs)
799 +{
800 + return timer_read();
801 +}
802 +
803 +static struct clocksource clocksource_stc = {
804 + .name = "stc",
805 + .rating = 300,
806 + .read = clksrc_read,
807 + .mask = CLOCKSOURCE_MASK(32),
808 + .flags = CLOCK_SOURCE_IS_CONTINUOUS,
809 +};
810 +
811 +unsigned long frc_clock_ticks32(void)
812 +{
813 + return timer_read();
814 +}
815 +
816 +static void __init bcm2708_clocksource_init(void)
817 +{
818 + if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) {
819 + printk(KERN_ERR "timer: failed to initialize clock "
820 + "source %s\n", clocksource_stc.name);
821 + }
822 +}
823 +
824 +struct clk __init *bcm2708_clk_register(const char *name, unsigned long fixed_rate)
825 +{
826 + struct clk *clk;
827 +
828 + clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT,
829 + fixed_rate);
830 + if (IS_ERR(clk))
831 + pr_err("%s not registered\n", name);
832 +
833 + return clk;
834 +}
835 +
836 +void __init bcm2708_register_clkdev(struct clk *clk, const char *name)
837 +{
838 + int ret;
839 +
840 + ret = clk_register_clkdev(clk, NULL, name);
841 + if (ret)
842 + pr_err("%s alias not registered\n", name);
843 +}
844 +
845 +void __init bcm2708_init_clocks(void)
846 +{
847 + struct clk *clk;
848 +
849 + clk = bcm2708_clk_register("uart0_clk", uart_clock);
850 + bcm2708_register_clkdev(clk, "dev:f1");
851 +
852 + clk = bcm2708_clk_register("sdhost_clk", 250000000);
853 + bcm2708_register_clkdev(clk, "mmc-bcm2835.0");
854 + bcm2708_register_clkdev(clk, "bcm2708_spi.0");
855 + bcm2708_register_clkdev(clk, "bcm2708_i2c.0");
856 + bcm2708_register_clkdev(clk, "bcm2708_i2c.1");
857 +}
858 +
859 +#define UART0_IRQ { IRQ_UART, 0 /*NO_IRQ*/ }
860 +#define UART0_DMA { 15, 14 }
861 +
862 +AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
863 +
864 +static struct amba_device *amba_devs[] __initdata = {
865 + &uart0_device,
866 +};
867 +
868 +static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
869 +
870 +static struct platform_device bcm2708_fb_device = {
871 + .name = "bcm2708_fb",
872 + .id = -1, /* only one bcm2708_fb */
873 + .resource = NULL,
874 + .num_resources = 0,
875 + .dev = {
876 + .dma_mask = &fb_dmamask,
877 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
878 + },
879 +};
880 +
881 +static struct resource bcm2708_usb_resources[] = {
882 + [0] = {
883 + .start = USB_BASE,
884 + .end = USB_BASE + SZ_128K - 1,
885 + .flags = IORESOURCE_MEM,
886 + },
887 + [1] = {
888 + .start = IRQ_USB,
889 + .end = IRQ_USB,
890 + .flags = IORESOURCE_IRQ,
891 + },
892 +};
893 +
894 +static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
895 +
896 +static struct platform_device bcm2708_usb_device = {
897 + .name = "bcm2708_usb",
898 + .id = -1, /* only one bcm2708_usb */
899 + .resource = bcm2708_usb_resources,
900 + .num_resources = ARRAY_SIZE(bcm2708_usb_resources),
901 + .dev = {
902 + .dma_mask = &usb_dmamask,
903 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
904 + },
905 +};
906 +
907 +static struct resource bcm2708_vcio_resources[] = {
908 + {
909 + .start = ARMCTRL_0_MAIL0_BASE,
910 + .end = ARMCTRL_0_MAIL0_BASE + SZ_64 - 1,
911 + .flags = IORESOURCE_MEM,
912 + }, {
913 + .start = IRQ_ARM_MAILBOX,
914 + .end = IRQ_ARM_MAILBOX,
915 + .flags = IORESOURCE_IRQ,
916 + },
917 +};
918 +
919 +static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
920 +
921 +static struct platform_device bcm2708_vcio_device = {
922 + .name = "bcm2708_vcio",
923 + .id = -1, /* only one VideoCore I/O area */
924 + .resource = bcm2708_vcio_resources,
925 + .num_resources = ARRAY_SIZE(bcm2708_vcio_resources),
926 + .dev = {
927 + .dma_mask = &vcio_dmamask,
928 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
929 + },
930 +};
931 +
932 +int __init bcm_register_device(struct platform_device *pdev)
933 +{
934 + int ret;
935 +
936 + ret = platform_device_register(pdev);
937 + if (ret)
938 + pr_debug("Unable to register platform device '%s': %d\n",
939 + pdev->name, ret);
940 +
941 + return ret;
942 +}
943 +
944 +/*
945 + * Use these macros for platform and i2c devices that are present in the
946 + * Device Tree. This way the devices are only added on non-DT systems.
947 + */
948 +#define bcm_register_device_dt(pdev) \
949 + if (!use_dt) bcm_register_device(pdev)
950 +
951 +#define i2c_register_board_info_dt(busnum, info, n) \
952 + if (!use_dt) i2c_register_board_info(busnum, info, n)
953 +
954 +int calc_rsts(int partition)
955 +{
956 + return PM_PASSWORD |
957 + ((partition & (1 << 0)) << 0) |
958 + ((partition & (1 << 1)) << 1) |
959 + ((partition & (1 << 2)) << 2) |
960 + ((partition & (1 << 3)) << 3) |
961 + ((partition & (1 << 4)) << 4) |
962 + ((partition & (1 << 5)) << 5);
963 +}
964 +
965 +static void bcm2708_restart(enum reboot_mode mode, const char *cmd)
966 +{
967 + extern char bcm2708_reboot_mode;
968 + uint32_t pm_rstc, pm_wdog;
969 + uint32_t timeout = 10;
970 + uint32_t pm_rsts = 0;
971 +
972 + if(bcm2708_reboot_mode == 'q')
973 + {
974 + // NOOBS < 1.3 booting with reboot=q
975 + pm_rsts = readl(__io_address(PM_RSTS));
976 + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET;
977 + }
978 + else if(bcm2708_reboot_mode == 'p')
979 + {
980 + // NOOBS < 1.3 halting
981 + pm_rsts = readl(__io_address(PM_RSTS));
982 + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET;
983 + }
984 + else
985 + {
986 + pm_rsts = calc_rsts(reboot_part);
987 + }
988 +
989 + writel(pm_rsts, __io_address(PM_RSTS));
990 +
991 + /* Setup watchdog for reset */
992 + pm_rstc = readl(__io_address(PM_RSTC));
993 +
994 + pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
995 + pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
996 +
997 + writel(pm_wdog, __io_address(PM_WDOG));
998 + writel(pm_rstc, __io_address(PM_RSTC));
999 +}
1000 +
1001 +/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */
1002 +static void bcm2708_power_off(void)
1003 +{
1004 + extern char bcm2708_reboot_mode;
1005 + if(bcm2708_reboot_mode == 'q')
1006 + {
1007 + // NOOBS < v1.3
1008 + bcm2708_restart('p', "");
1009 + }
1010 + else
1011 + {
1012 + /* partition 63 is special code for HALT the bootloader knows not to boot*/
1013 + reboot_part = 63;
1014 + /* continue with normal reset mechanism */
1015 + bcm2708_restart(0, "");
1016 + }
1017 +}
1018 +
1019 +static void __init bcm2708_init_uart1(void)
1020 +{
1021 + struct device_node *np;
1022 +
1023 + np = of_find_compatible_node(NULL, NULL, "brcm,bcm2835-aux-uart");
1024 + if (of_device_is_available(np)) {
1025 + pr_info("bcm2708: Mini UART enabled\n");
1026 + writel(1, __io_address(UART1_BASE + 0x4));
1027 + }
1028 +}
1029 +
1030 +#ifdef CONFIG_OF
1031 +static void __init bcm2708_dt_init(void)
1032 +{
1033 + int ret;
1034 +
1035 + of_clk_init(NULL);
1036 + ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
1037 + if (ret) {
1038 + pr_err("of_platform_populate failed: %d\n", ret);
1039 + /* Proceed as if CONFIG_OF was not defined */
1040 + } else {
1041 + use_dt = 1;
1042 + }
1043 +}
1044 +#else
1045 +static void __init bcm2708_dt_init(void) { }
1046 +#endif /* CONFIG_OF */
1047 +
1048 +void __init bcm2708_init(void)
1049 +{
1050 + int i;
1051 +
1052 +#if defined(CONFIG_BCM_VC_CMA)
1053 + vc_cma_early_init();
1054 +#endif
1055 + printk("bcm2708.uart_clock = %d\n", uart_clock);
1056 + pm_power_off = bcm2708_power_off;
1057 +
1058 + bcm2708_init_clocks();
1059 + bcm2708_dt_init();
1060 +
1061 + bcm_register_device(&bcm2708_vcio_device);
1062 +#ifdef CONFIG_BCM2708_GPIO
1063 + bcm_register_device_dt(&bcm2708_gpio_device);
1064 +#endif
1065 + bcm_register_device_dt(&bcm2708_fb_device);
1066 + bcm_register_device_dt(&bcm2708_usb_device);
1067 +
1068 + bcm2708_init_led();
1069 + bcm2708_init_uart1();
1070 +
1071 + if (!use_dt) {
1072 + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
1073 + struct amba_device *d = amba_devs[i];
1074 + amba_device_register(d, &iomem_resource);
1075 + }
1076 + }
1077 + system_rev = boardrev;
1078 + system_serial_low = serial;
1079 +}
1080 +
1081 +static void timer_set_mode(enum clock_event_mode mode,
1082 + struct clock_event_device *clk)
1083 +{
1084 + switch (mode) {
1085 + case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */
1086 + case CLOCK_EVT_MODE_SHUTDOWN:
1087 + break;
1088 + case CLOCK_EVT_MODE_PERIODIC:
1089 +
1090 + case CLOCK_EVT_MODE_UNUSED:
1091 + case CLOCK_EVT_MODE_RESUME:
1092 +
1093 + default:
1094 + printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n",
1095 + (int)mode);
1096 + break;
1097 + }
1098 +
1099 +}
1100 +
1101 +static int timer_set_next_event(unsigned long cycles,
1102 + struct clock_event_device *unused)
1103 +{
1104 + unsigned long stc;
1105 + do {
1106 + stc = readl(__io_address(ST_BASE + 0x04));
1107 + /* We could take a FIQ here, which may push ST above STC3 */
1108 + writel(stc + cycles, __io_address(ST_BASE + 0x18));
1109 + } while ((signed long) cycles >= 0 &&
1110 + (signed long) (readl(__io_address(ST_BASE + 0x04)) - stc)
1111 + >= (signed long) cycles);
1112 + return 0;
1113 +}
1114 +
1115 +static struct clock_event_device timer0_clockevent = {
1116 + .name = "timer0",
1117 + .shift = 32,
1118 + .features = CLOCK_EVT_FEAT_ONESHOT,
1119 + .set_mode = timer_set_mode,
1120 + .set_next_event = timer_set_next_event,
1121 +};
1122 +
1123 +/*
1124 + * IRQ handler for the timer
1125 + */
1126 +static irqreturn_t bcm2708_timer_interrupt(int irq, void *dev_id)
1127 +{
1128 + struct clock_event_device *evt = &timer0_clockevent;
1129 +
1130 + writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */
1131 +
1132 + evt->event_handler(evt);
1133 +
1134 + return IRQ_HANDLED;
1135 +}
1136 +
1137 +static struct irqaction bcm2708_timer_irq = {
1138 + .name = "BCM2708 Timer Tick",
1139 + .flags = IRQF_TIMER | IRQF_IRQPOLL,
1140 + .handler = bcm2708_timer_interrupt,
1141 +};
1142 +
1143 +/*
1144 + * Set up timer interrupt, and return the current time in seconds.
1145 + */
1146 +
1147 +static struct delay_timer bcm2708_delay_timer = {
1148 + .read_current_timer = bcm2708_read_current_timer,
1149 + .freq = STC_FREQ_HZ,
1150 +};
1151 +
1152 +static void __init bcm2708_timer_init(void)
1153 +{
1154 + /* init high res timer */
1155 + bcm2708_clocksource_init();
1156 +
1157 + /*
1158 + * Make irqs happen for the system timer
1159 + */
1160 + setup_irq(IRQ_TIMER3, &bcm2708_timer_irq);
1161 +
1162 + sched_clock_register(bcm2708_read_sched_clock, 32, STC_FREQ_HZ);
1163 +
1164 + timer0_clockevent.mult =
1165 + div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift);
1166 + timer0_clockevent.max_delta_ns =
1167 + clockevent_delta2ns(0xffffffff, &timer0_clockevent);
1168 + timer0_clockevent.min_delta_ns =
1169 + clockevent_delta2ns(0xf, &timer0_clockevent);
1170 +
1171 + timer0_clockevent.cpumask = cpumask_of(0);
1172 + clockevents_register_device(&timer0_clockevent);
1173 +
1174 + register_current_timer_delay(&bcm2708_delay_timer);
1175 +}
1176 +
1177 +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
1178 +#include <linux/leds.h>
1179 +
1180 +static struct gpio_led bcm2708_leds[] = {
1181 + [0] = {
1182 + .gpio = 16,
1183 + .name = "led0",
1184 + .default_trigger = "mmc0",
1185 + .active_low = 1,
1186 + },
1187 +};
1188 +
1189 +static struct gpio_led_platform_data bcm2708_led_pdata = {
1190 + .num_leds = ARRAY_SIZE(bcm2708_leds),
1191 + .leds = bcm2708_leds,
1192 +};
1193 +
1194 +static struct platform_device bcm2708_led_device = {
1195 + .name = "leds-gpio",
1196 + .id = -1,
1197 + .dev = {
1198 + .platform_data = &bcm2708_led_pdata,
1199 + },
1200 +};
1201 +
1202 +static void __init bcm2708_init_led(void)
1203 +{
1204 + bcm2708_leds[0].gpio = disk_led_gpio;
1205 + bcm2708_leds[0].active_low = disk_led_active_low;
1206 + bcm_register_device_dt(&bcm2708_led_device);
1207 +}
1208 +#else
1209 +static inline void bcm2708_init_led(void)
1210 +{
1211 +}
1212 +#endif
1213 +
1214 +void __init bcm2708_init_early(void)
1215 +{
1216 + /*
1217 + * Some devices allocate their coherent buffers from atomic
1218 + * context. Increase size of atomic coherent pool to make sure such
1219 + * the allocations won't fail.
1220 + */
1221 + init_dma_coherent_pool_size(SZ_4M);
1222 +}
1223 +
1224 +static void __init board_reserve(void)
1225 +{
1226 +#if defined(CONFIG_BCM_VC_CMA)
1227 + vc_cma_reserve();
1228 +#endif
1229 +}
1230 +
1231 +static const char * const bcm2708_compat[] = {
1232 + "brcm,bcm2708",
1233 + NULL
1234 +};
1235 +
1236 +MACHINE_START(BCM2708, "BCM2708")
1237 + /* Maintainer: Broadcom Europe Ltd. */
1238 + .map_io = bcm2708_map_io,
1239 + .init_irq = bcm2708_init_irq,
1240 + .init_time = bcm2708_timer_init,
1241 + .init_machine = bcm2708_init,
1242 + .init_early = bcm2708_init_early,
1243 + .reserve = board_reserve,
1244 + .restart = bcm2708_restart,
1245 + .dt_compat = bcm2708_compat,
1246 +MACHINE_END
1247 +
1248 +module_param(boardrev, uint, 0644);
1249 +module_param(serial, uint, 0644);
1250 +module_param(uart_clock, uint, 0644);
1251 +module_param(disk_led_gpio, uint, 0644);
1252 +module_param(disk_led_active_low, uint, 0644);
1253 +module_param(reboot_part, uint, 0644);
1254 --- /dev/null
1255 +++ b/arch/arm/mach-bcm2708/bcm2708.h
1256 @@ -0,0 +1,49 @@
1257 +/*
1258 + * linux/arch/arm/mach-bcm2708/bcm2708.h
1259 + *
1260 + * BCM2708 machine support header
1261 + *
1262 + * Copyright (C) 2010 Broadcom
1263 + *
1264 + * This program is free software; you can redistribute it and/or modify
1265 + * it under the terms of the GNU General Public License as published by
1266 + * the Free Software Foundation; either version 2 of the License, or
1267 + * (at your option) any later version.
1268 + *
1269 + * This program is distributed in the hope that it will be useful,
1270 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1271 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1272 + * GNU General Public License for more details.
1273 + *
1274 + * You should have received a copy of the GNU General Public License
1275 + * along with this program; if not, write to the Free Software
1276 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1277 + */
1278 +
1279 +#ifndef __BCM2708_BCM2708_H
1280 +#define __BCM2708_BCM2708_H
1281 +
1282 +#include <linux/amba/bus.h>
1283 +
1284 +extern void __init bcm2708_init(void);
1285 +extern void __init bcm2708_init_irq(void);
1286 +extern void __init bcm2708_map_io(void);
1287 +extern struct sys_timer bcm2708_timer;
1288 +extern unsigned int mmc_status(struct device *dev);
1289 +
1290 +#define AMBA_DEVICE(name, busid, base, plat) \
1291 +static struct amba_device name##_device = { \
1292 + .dev = { \
1293 + .coherent_dma_mask = ~0, \
1294 + .init_name = busid, \
1295 + .platform_data = plat, \
1296 + }, \
1297 + .res = { \
1298 + .start = base##_BASE, \
1299 + .end = (base##_BASE) + SZ_4K - 1,\
1300 + .flags = IORESOURCE_MEM, \
1301 + }, \
1302 + .irq = base##_IRQ, \
1303 +}
1304 +
1305 +#endif
1306 --- /dev/null
1307 +++ b/arch/arm/mach-bcm2708/include/mach/arm_control.h
1308 @@ -0,0 +1,419 @@
1309 +/*
1310 + * linux/arch/arm/mach-bcm2708/arm_control.h
1311 + *
1312 + * Copyright (C) 2010 Broadcom
1313 + *
1314 + * This program is free software; you can redistribute it and/or modify
1315 + * it under the terms of the GNU General Public License as published by
1316 + * the Free Software Foundation; either version 2 of the License, or
1317 + * (at your option) any later version.
1318 + *
1319 + * This program is distributed in the hope that it will be useful,
1320 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1321 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1322 + * GNU General Public License for more details.
1323 + *
1324 + * You should have received a copy of the GNU General Public License
1325 + * along with this program; if not, write to the Free Software
1326 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1327 + */
1328 +
1329 +#ifndef __BCM2708_ARM_CONTROL_H
1330 +#define __BCM2708_ARM_CONTROL_H
1331 +
1332 +/*
1333 + * Definitions and addresses for the ARM CONTROL logic
1334 + * This file is manually generated.
1335 + */
1336 +
1337 +#define ARM_BASE 0x7E00B000
1338 +
1339 +/* Basic configuration */
1340 +#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000)
1341 +#define ARM_C0_SIZ128M 0x00000000
1342 +#define ARM_C0_SIZ256M 0x00000001
1343 +#define ARM_C0_SIZ512M 0x00000002
1344 +#define ARM_C0_SIZ1G 0x00000003
1345 +#define ARM_C0_BRESP0 0x00000000
1346 +#define ARM_C0_BRESP1 0x00000004
1347 +#define ARM_C0_BRESP2 0x00000008
1348 +#define ARM_C0_BOOTHI 0x00000010
1349 +#define ARM_C0_UNUSED05 0x00000020 /* free */
1350 +#define ARM_C0_FULLPERI 0x00000040
1351 +#define ARM_C0_UNUSED78 0x00000180 /* free */
1352 +#define ARM_C0_JTAGMASK 0x00000E00
1353 +#define ARM_C0_JTAGOFF 0x00000000
1354 +#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */
1355 +#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */
1356 +#define ARM_C0_APROTMSK 0x0000F000
1357 +#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */
1358 +#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */
1359 +#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */
1360 +#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */
1361 +#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */
1362 +#define ARM_C0_PRIO_L2 0x0F000000
1363 +#define ARM_C0_PRIO_UC 0xF0000000
1364 +
1365 +#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */
1366 +#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */
1367 +#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */
1368 +
1369 +
1370 +#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440)
1371 +#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */
1372 +#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */
1373 +#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */
1374 +#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */
1375 +#define ARM_C1_PERSON 0x00000100 /* peripherals on */
1376 +#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */
1377 +
1378 +#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444)
1379 +#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */
1380 +#define ARM_S_READPEND 0x000003FF /* pending reads counter */
1381 +#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */
1382 +
1383 +#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448)
1384 +#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */
1385 +#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */
1386 +#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */
1387 +#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */
1388 +#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */
1389 +#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */
1390 +
1391 +#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C)
1392 +#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C)
1393 +#define ARM_IDVAL 0x364D5241
1394 +
1395 +/* Translation memory */
1396 +#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100)
1397 +/* 32 locations: 0x100.. 0x17F */
1398 +/* 32 spare means we CAN go to 64 pages.... */
1399 +
1400 +
1401 +/* Interrupts */
1402 +#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */
1403 +#define ARM_I0_TIMER 0x00000001 /* timer IRQ */
1404 +#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */
1405 +#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */
1406 +#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */
1407 +#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */
1408 +#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */
1409 +
1410 +#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */
1411 +/* todo: all I1_interrupt sources */
1412 +#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */
1413 +/* todo: all I2_interrupt sources */
1414 +
1415 +#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */
1416 +#define ARM_IF_INDEX 0x0000007F /* FIQ select */
1417 +#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */
1418 +#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */
1419 +#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */
1420 +#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */
1421 +#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */
1422 +#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */
1423 +#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */
1424 +#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */
1425 +#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */
1426 +
1427 +#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */
1428 +#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */
1429 +#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */
1430 +#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */
1431 +#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */
1432 +#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */
1433 +#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */
1434 +#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */
1435 +#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */
1436 +#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */
1437 +#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */
1438 +#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */
1439 +#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */
1440 +
1441 +/* Timer */
1442 +/* For reg. fields see sp804 spec. */
1443 +#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400)
1444 +#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404)
1445 +#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408)
1446 +#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C)
1447 +#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410)
1448 +#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414)
1449 +#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418)
1450 +#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c)
1451 +#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420)
1452 +
1453 +#define TIMER_CTRL_ONESHOT (1 << 0)
1454 +#define TIMER_CTRL_32BIT (1 << 1)
1455 +#define TIMER_CTRL_DIV1 (0 << 2)
1456 +#define TIMER_CTRL_DIV16 (1 << 2)
1457 +#define TIMER_CTRL_DIV256 (2 << 2)
1458 +#define TIMER_CTRL_IE (1 << 5)
1459 +#define TIMER_CTRL_PERIODIC (1 << 6)
1460 +#define TIMER_CTRL_ENABLE (1 << 7)
1461 +#define TIMER_CTRL_DBGHALT (1 << 8)
1462 +#define TIMER_CTRL_ENAFREE (1 << 9)
1463 +#define TIMER_CTRL_FREEDIV_SHIFT 16)
1464 +#define TIMER_CTRL_FREEDIV_MASK 0xff
1465 +
1466 +/* Semaphores, Doorbells, Mailboxes */
1467 +#define ARM_SBM_OWN0 (ARM_BASE+0x800)
1468 +#define ARM_SBM_OWN1 (ARM_BASE+0x900)
1469 +#define ARM_SBM_OWN2 (ARM_BASE+0xA00)
1470 +#define ARM_SBM_OWN3 (ARM_BASE+0xB00)
1471 +
1472 +/* MAILBOXES
1473 + * Register flags are common across all
1474 + * owner registers. See end of this section
1475 + *
1476 + * Semaphores, Doorbells, Mailboxes Owner 0
1477 + *
1478 + */
1479 +
1480 +#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
1481 +#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
1482 +#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04)
1483 +#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08)
1484 +#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C)
1485 +#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10)
1486 +#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14)
1487 +#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18)
1488 +#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C)
1489 +#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40)
1490 +#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44)
1491 +#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48)
1492 +#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C)
1493 +/* MAILBOX 0 access in Owner 0 area */
1494 +/* Some addresses should ONLY be used by owner 0 */
1495 +#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */
1496 +#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */
1497 +#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */
1498 +#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */
1499 +#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */
1500 +#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */
1501 +/* MAILBOX 1 access in Owner 0 area */
1502 +/* Owner 0 should only WRITE to this mailbox */
1503 +#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */
1504 +/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */
1505 +/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */
1506 +/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */
1507 +#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */
1508 +/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */
1509 +/* General SEM, BELL, MAIL config/status */
1510 +#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */
1511 +#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */
1512 +#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */
1513 +#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */
1514 +
1515 +/* Semaphores, Doorbells, Mailboxes Owner 1 */
1516 +#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
1517 +#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
1518 +#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04)
1519 +#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08)
1520 +#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C)
1521 +#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10)
1522 +#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14)
1523 +#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18)
1524 +#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C)
1525 +#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40)
1526 +#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44)
1527 +#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48)
1528 +#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C)
1529 +/* MAILBOX 0 access in Owner 0 area */
1530 +/* Owner 1 should only WRITE to this mailbox */
1531 +#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */
1532 +/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */
1533 +/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */
1534 +/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */
1535 +#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */
1536 +/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */
1537 +/* MAILBOX 1 access in Owner 0 area */
1538 +#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */
1539 +#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */
1540 +#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */
1541 +#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */
1542 +#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */
1543 +#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC)
1544 +/* General SEM, BELL, MAIL config/status */
1545 +#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */
1546 +#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */
1547 +#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */
1548 +#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */
1549 +
1550 +/* Semaphores, Doorbells, Mailboxes Owner 2 */
1551 +#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
1552 +#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
1553 +#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04)
1554 +#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08)
1555 +#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C)
1556 +#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10)
1557 +#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14)
1558 +#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18)
1559 +#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C)
1560 +#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40)
1561 +#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44)
1562 +#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48)
1563 +#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C)
1564 +/* MAILBOX 0 access in Owner 2 area */
1565 +/* Owner 2 should only WRITE to this mailbox */
1566 +#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */
1567 +/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */
1568 +/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */
1569 +/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */
1570 +#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */
1571 +/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */
1572 +/* MAILBOX 1 access in Owner 2 area */
1573 +/* Owner 2 should only WRITE to this mailbox */
1574 +#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */
1575 +/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */
1576 +/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */
1577 +/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */
1578 +#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */
1579 +/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */
1580 +/* General SEM, BELL, MAIL config/status */
1581 +#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */
1582 +#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */
1583 +#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */
1584 +#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */
1585 +
1586 +/* Semaphores, Doorbells, Mailboxes Owner 3 */
1587 +#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
1588 +#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
1589 +#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04)
1590 +#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08)
1591 +#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C)
1592 +#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10)
1593 +#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14)
1594 +#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18)
1595 +#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C)
1596 +#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40)
1597 +#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44)
1598 +#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48)
1599 +#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C)
1600 +/* MAILBOX 0 access in Owner 3 area */
1601 +/* Owner 3 should only WRITE to this mailbox */
1602 +#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */
1603 +/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */
1604 +/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */
1605 +/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */
1606 +#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */
1607 +/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */
1608 +/* MAILBOX 1 access in Owner 3 area */
1609 +/* Owner 3 should only WRITE to this mailbox */
1610 +#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */
1611 +/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */
1612 +/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */
1613 +/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */
1614 +#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */
1615 +/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */
1616 +/* General SEM, BELL, MAIL config/status */
1617 +#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */
1618 +#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */
1619 +#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */
1620 +#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */
1621 +
1622 +
1623 +
1624 +/* Mailbox flags. Valid for all owners */
1625 +
1626 +/* Mailbox status register (...0x98) */
1627 +#define ARM_MS_FULL 0x80000000
1628 +#define ARM_MS_EMPTY 0x40000000
1629 +#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */
1630 +
1631 +/* MAILBOX config/status register (...0x9C) */
1632 +/* ANY write to this register clears the error bits! */
1633 +#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */
1634 +#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */
1635 +#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */
1636 +#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */
1637 +#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */
1638 +#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */
1639 +#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */
1640 +/* Bit 7 is unused */
1641 +#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */
1642 +#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */
1643 +#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */
1644 +
1645 +/* Semaphore clear/debug register (...0xE0) */
1646 +#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */
1647 +#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */
1648 +#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */
1649 +#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */
1650 +#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */
1651 +#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */
1652 +#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */
1653 +#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */
1654 +#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */
1655 +#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */
1656 +#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */
1657 +#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */
1658 +#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */
1659 +#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */
1660 +#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */
1661 +#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */
1662 +
1663 +/* Doorbells clear/debug register (...0xE4) */
1664 +#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */
1665 +#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */
1666 +#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */
1667 +#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */
1668 +#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */
1669 +#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */
1670 +#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */
1671 +#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */
1672 +
1673 +/* MY IRQS register (...0xF8) */
1674 +#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */
1675 +#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */
1676 +
1677 +/* ALL IRQS register (...0xF8) */
1678 +#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */
1679 +#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */
1680 +#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */
1681 +#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */
1682 +#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */
1683 +#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */
1684 +#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */
1685 +#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */
1686 +#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */
1687 +#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */
1688 +/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */
1689 +/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */
1690 +/* */
1691 +/* ARM JTAG BASH */
1692 +/* */
1693 +#define AJB_BASE 0x7e2000c0
1694 +
1695 +#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00)
1696 +#define AJB_BITS0 0x000000
1697 +#define AJB_BITS4 0x000004
1698 +#define AJB_BITS8 0x000008
1699 +#define AJB_BITS12 0x00000C
1700 +#define AJB_BITS16 0x000010
1701 +#define AJB_BITS20 0x000014
1702 +#define AJB_BITS24 0x000018
1703 +#define AJB_BITS28 0x00001C
1704 +#define AJB_BITS32 0x000020
1705 +#define AJB_BITS34 0x000022
1706 +#define AJB_OUT_MS 0x000040
1707 +#define AJB_OUT_LS 0x000000
1708 +#define AJB_INV_CLK 0x000080
1709 +#define AJB_D0_RISE 0x000100
1710 +#define AJB_D0_FALL 0x000000
1711 +#define AJB_D1_RISE 0x000200
1712 +#define AJB_D1_FALL 0x000000
1713 +#define AJB_IN_RISE 0x000400
1714 +#define AJB_IN_FALL 0x000000
1715 +#define AJB_ENABLE 0x000800
1716 +#define AJB_HOLD0 0x000000
1717 +#define AJB_HOLD1 0x001000
1718 +#define AJB_HOLD2 0x002000
1719 +#define AJB_HOLD3 0x003000
1720 +#define AJB_RESETN 0x004000
1721 +#define AJB_CLKSHFT 16
1722 +#define AJB_BUSY 0x80000000
1723 +#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04)
1724 +#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08)
1725 +#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c)
1726 +
1727 +#endif
1728 --- /dev/null
1729 +++ b/arch/arm/mach-bcm2708/include/mach/clkdev.h
1730 @@ -0,0 +1,7 @@
1731 +#ifndef __ASM_MACH_CLKDEV_H
1732 +#define __ASM_MACH_CLKDEV_H
1733 +
1734 +#define __clk_get(clk) ({ 1; })
1735 +#define __clk_put(clk) do { } while (0)
1736 +
1737 +#endif
1738 --- /dev/null
1739 +++ b/arch/arm/mach-bcm2708/include/mach/debug-macro.S
1740 @@ -0,0 +1,22 @@
1741 +/* arch/arm/mach-bcm2708/include/mach/debug-macro.S
1742 + *
1743 + * Debugging macro include header
1744 + *
1745 + * Copyright (C) 2010 Broadcom
1746 + * Copyright (C) 1994-1999 Russell King
1747 + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
1748 + *
1749 + * This program is free software; you can redistribute it and/or modify
1750 + * it under the terms of the GNU General Public License version 2 as
1751 + * published by the Free Software Foundation.
1752 + *
1753 +*/
1754 +
1755 +#include <mach/platform.h>
1756 +
1757 + .macro addruart, rp, rv, tmp
1758 + ldr \rp, =UART0_BASE
1759 + ldr \rv, =IO_ADDRESS(UART0_BASE)
1760 + .endm
1761 +
1762 +#include <debug/pl01x.S>
1763 --- /dev/null
1764 +++ b/arch/arm/mach-bcm2708/include/mach/entry-macro.S
1765 @@ -0,0 +1,69 @@
1766 +/*
1767 + * arch/arm/mach-bcm2708/include/mach/entry-macro.S
1768 + *
1769 + * Low-level IRQ helper macros for BCM2708 platforms
1770 + *
1771 + * Copyright (C) 2010 Broadcom
1772 + *
1773 + * This program is free software; you can redistribute it and/or modify
1774 + * it under the terms of the GNU General Public License as published by
1775 + * the Free Software Foundation; either version 2 of the License, or
1776 + * (at your option) any later version.
1777 + *
1778 + * This program is distributed in the hope that it will be useful,
1779 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1780 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1781 + * GNU General Public License for more details.
1782 + *
1783 + * You should have received a copy of the GNU General Public License
1784 + * along with this program; if not, write to the Free Software
1785 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1786 + */
1787 +#include <mach/hardware.h>
1788 +
1789 + .macro disable_fiq
1790 + .endm
1791 +
1792 + .macro get_irqnr_preamble, base, tmp
1793 + ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
1794 + .endm
1795 +
1796 + .macro arch_ret_to_user, tmp1, tmp2
1797 + .endm
1798 +
1799 + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
1800 + /* get masked status */
1801 + ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
1802 + mov \irqnr, #(ARM_IRQ0_BASE + 31)
1803 + and \tmp, \irqstat, #0x300 @ save bits 8 and 9
1804 + /* clear bits 8 and 9, and test */
1805 + bics \irqstat, \irqstat, #0x300
1806 + bne 1010f
1807 +
1808 + tst \tmp, #0x100
1809 + ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
1810 + movne \irqnr, #(ARM_IRQ1_BASE + 31)
1811 + @ Mask out the interrupts also present in PEND0 - see SW-5809
1812 + bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
1813 + bicne \irqstat, #((1<<18) | (1<<19))
1814 + bne 1010f
1815 +
1816 + tst \tmp, #0x200
1817 + ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
1818 + movne \irqnr, #(ARM_IRQ2_BASE + 31)
1819 + @ Mask out the interrupts also present in PEND0 - see SW-5809
1820 + bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
1821 + bicne \irqstat, #((1<<30))
1822 + beq 1020f
1823 +
1824 +1010:
1825 + @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
1826 + @ N.B. CLZ is an ARM5 instruction.
1827 + sub \tmp, \irqstat, #1
1828 + eor \irqstat, \irqstat, \tmp
1829 + clz \tmp, \irqstat
1830 + sub \irqnr, \tmp
1831 +
1832 +1020: @ EQ will be set if no irqs pending
1833 +
1834 + .endm
1835 --- /dev/null
1836 +++ b/arch/arm/mach-bcm2708/include/mach/frc.h
1837 @@ -0,0 +1,38 @@
1838 +/*
1839 + * arch/arm/mach-bcm2708/include/mach/timex.h
1840 + *
1841 + * BCM2708 free running counter (timer)
1842 + *
1843 + * Copyright (C) 2010 Broadcom
1844 + *
1845 + * This program is free software; you can redistribute it and/or modify
1846 + * it under the terms of the GNU General Public License as published by
1847 + * the Free Software Foundation; either version 2 of the License, or
1848 + * (at your option) any later version.
1849 + *
1850 + * This program is distributed in the hope that it will be useful,
1851 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1852 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1853 + * GNU General Public License for more details.
1854 + *
1855 + * You should have received a copy of the GNU General Public License
1856 + * along with this program; if not, write to the Free Software
1857 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1858 + */
1859 +
1860 +#ifndef _MACH_FRC_H
1861 +#define _MACH_FRC_H
1862 +
1863 +#define FRC_TICK_RATE (1000000)
1864 +
1865 +/*! Free running counter incrementing at the CLOCK_TICK_RATE
1866 + (slightly faster than frc_clock_ticks63()
1867 + */
1868 +extern unsigned long frc_clock_ticks32(void);
1869 +
1870 +/*! Free running counter incrementing at the CLOCK_TICK_RATE
1871 + * Note - top bit should be ignored (see cnt32_to_63)
1872 + */
1873 +extern unsigned long long frc_clock_ticks63(void);
1874 +
1875 +#endif
1876 --- /dev/null
1877 +++ b/arch/arm/mach-bcm2708/include/mach/hardware.h
1878 @@ -0,0 +1,28 @@
1879 +/*
1880 + * arch/arm/mach-bcm2708/include/mach/hardware.h
1881 + *
1882 + * This file contains the hardware definitions of the BCM2708 devices.
1883 + *
1884 + * Copyright (C) 2010 Broadcom
1885 + *
1886 + * This program is free software; you can redistribute it and/or modify
1887 + * it under the terms of the GNU General Public License as published by
1888 + * the Free Software Foundation; either version 2 of the License, or
1889 + * (at your option) any later version.
1890 + *
1891 + * This program is distributed in the hope that it will be useful,
1892 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1893 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1894 + * GNU General Public License for more details.
1895 + *
1896 + * You should have received a copy of the GNU General Public License
1897 + * along with this program; if not, write to the Free Software
1898 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1899 + */
1900 +#ifndef __ASM_ARCH_HARDWARE_H
1901 +#define __ASM_ARCH_HARDWARE_H
1902 +
1903 +#include <asm/sizes.h>
1904 +#include <mach/platform.h>
1905 +
1906 +#endif
1907 --- /dev/null
1908 +++ b/arch/arm/mach-bcm2708/include/mach/io.h
1909 @@ -0,0 +1,27 @@
1910 +/*
1911 + * arch/arm/mach-bcm2708/include/mach/io.h
1912 + *
1913 + * Copyright (C) 2003 ARM Limited
1914 + *
1915 + * This program is free software; you can redistribute it and/or modify
1916 + * it under the terms of the GNU General Public License as published by
1917 + * the Free Software Foundation; either version 2 of the License, or
1918 + * (at your option) any later version.
1919 + *
1920 + * This program is distributed in the hope that it will be useful,
1921 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1922 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1923 + * GNU General Public License for more details.
1924 + *
1925 + * You should have received a copy of the GNU General Public License
1926 + * along with this program; if not, write to the Free Software
1927 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1928 + */
1929 +#ifndef __ASM_ARM_ARCH_IO_H
1930 +#define __ASM_ARM_ARCH_IO_H
1931 +
1932 +#define IO_SPACE_LIMIT 0xffffffff
1933 +
1934 +#define __io(a) __typesafe_io(a)
1935 +
1936 +#endif
1937 --- /dev/null
1938 +++ b/arch/arm/mach-bcm2708/include/mach/irqs.h
1939 @@ -0,0 +1,196 @@
1940 +/*
1941 + * arch/arm/mach-bcm2708/include/mach/irqs.h
1942 + *
1943 + * Copyright (C) 2010 Broadcom
1944 + * Copyright (C) 2003 ARM Limited
1945 + * Copyright (C) 2000 Deep Blue Solutions Ltd.
1946 + *
1947 + * This program is free software; you can redistribute it and/or modify
1948 + * it under the terms of the GNU General Public License as published by
1949 + * the Free Software Foundation; either version 2 of the License, or
1950 + * (at your option) any later version.
1951 + *
1952 + * This program is distributed in the hope that it will be useful,
1953 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1954 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1955 + * GNU General Public License for more details.
1956 + *
1957 + * You should have received a copy of the GNU General Public License
1958 + * along with this program; if not, write to the Free Software
1959 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1960 + */
1961 +
1962 +#ifndef _BCM2708_IRQS_H_
1963 +#define _BCM2708_IRQS_H_
1964 +
1965 +#include <mach/platform.h>
1966 +
1967 +/*
1968 + * IRQ interrupts definitions are the same as the INT definitions
1969 + * held within platform.h
1970 + */
1971 +#define IRQ_ARMCTRL_START 0
1972 +#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0)
1973 +#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1)
1974 +#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2)
1975 +#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3)
1976 +#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0)
1977 +#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1)
1978 +#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2)
1979 +#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG)
1980 +#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP)
1981 +#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB)
1982 +#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D)
1983 +#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER)
1984 +#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0)
1985 +#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1)
1986 +#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2)
1987 +#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3)
1988 +#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0)
1989 +#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1)
1990 +#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2)
1991 +#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3)
1992 +#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4)
1993 +#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5)
1994 +#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6)
1995 +#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7)
1996 +#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8)
1997 +#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9)
1998 +#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10)
1999 +#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11)
2000 +#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12)
2001 +#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX)
2002 +#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM)
2003 +#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA)
2004 +#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT)
2005 +#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER)
2006 +#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX)
2007 +#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC)
2008 +#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0)
2009 +#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE)
2010 +#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0)
2011 +#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1)
2012 +#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0)
2013 +#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1)
2014 +#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1)
2015 +#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV)
2016 +#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1)
2017 +#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0)
2018 +#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1)
2019 +#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR)
2020 +#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI)
2021 +#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0)
2022 +#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1)
2023 +#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2)
2024 +#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3)
2025 +#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C)
2026 +#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI)
2027 +#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM)
2028 +#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO)
2029 +#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART)
2030 +#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS)
2031 +#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC)
2032 +#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG)
2033 +#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG)
2034 +#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO)
2035 +#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON)
2036 +
2037 +#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER)
2038 +#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX)
2039 +#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0)
2040 +#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1)
2041 +#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED)
2042 +#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED)
2043 +#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0)
2044 +#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1)
2045 +#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1)
2046 +#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2)
2047 +
2048 +/*
2049 + * FIQ interrupts definitions are the same as the INT definitions.
2050 + */
2051 +#define FIQ_TIMER0 INT_TIMER0
2052 +#define FIQ_TIMER1 INT_TIMER1
2053 +#define FIQ_TIMER2 INT_TIMER2
2054 +#define FIQ_TIMER3 INT_TIMER3
2055 +#define FIQ_CODEC0 INT_CODEC0
2056 +#define FIQ_CODEC1 INT_CODEC1
2057 +#define FIQ_CODEC2 INT_CODEC2
2058 +#define FIQ_JPEG INT_JPEG
2059 +#define FIQ_ISP INT_ISP
2060 +#define FIQ_USB INT_USB
2061 +#define FIQ_3D INT_3D
2062 +#define FIQ_TRANSPOSER INT_TRANSPOSER
2063 +#define FIQ_MULTICORESYNC0 INT_MULTICORESYNC0
2064 +#define FIQ_MULTICORESYNC1 INT_MULTICORESYNC1
2065 +#define FIQ_MULTICORESYNC2 INT_MULTICORESYNC2
2066 +#define FIQ_MULTICORESYNC3 INT_MULTICORESYNC3
2067 +#define FIQ_DMA0 INT_DMA0
2068 +#define FIQ_DMA1 INT_DMA1
2069 +#define FIQ_DMA2 INT_DMA2
2070 +#define FIQ_DMA3 INT_DMA3
2071 +#define FIQ_DMA4 INT_DMA4
2072 +#define FIQ_DMA5 INT_DMA5
2073 +#define FIQ_DMA6 INT_DMA6
2074 +#define FIQ_DMA7 INT_DMA7
2075 +#define FIQ_DMA8 INT_DMA8
2076 +#define FIQ_DMA9 INT_DMA9
2077 +#define FIQ_DMA10 INT_DMA10
2078 +#define FIQ_DMA11 INT_DMA11
2079 +#define FIQ_DMA12 INT_DMA12
2080 +#define FIQ_AUX INT_AUX
2081 +#define FIQ_ARM INT_ARM
2082 +#define FIQ_VPUDMA INT_VPUDMA
2083 +#define FIQ_HOSTPORT INT_HOSTPORT
2084 +#define FIQ_VIDEOSCALER INT_VIDEOSCALER
2085 +#define FIQ_CCP2TX INT_CCP2TX
2086 +#define FIQ_SDC INT_SDC
2087 +#define FIQ_DSI0 INT_DSI0
2088 +#define FIQ_AVE INT_AVE
2089 +#define FIQ_CAM0 INT_CAM0
2090 +#define FIQ_CAM1 INT_CAM1
2091 +#define FIQ_HDMI0 INT_HDMI0
2092 +#define FIQ_HDMI1 INT_HDMI1
2093 +#define FIQ_PIXELVALVE1 INT_PIXELVALVE1
2094 +#define FIQ_I2CSPISLV INT_I2CSPISLV
2095 +#define FIQ_DSI1 INT_DSI1
2096 +#define FIQ_PWA0 INT_PWA0
2097 +#define FIQ_PWA1 INT_PWA1
2098 +#define FIQ_CPR INT_CPR
2099 +#define FIQ_SMI INT_SMI
2100 +#define FIQ_GPIO0 INT_GPIO0
2101 +#define FIQ_GPIO1 INT_GPIO1
2102 +#define FIQ_GPIO2 INT_GPIO2
2103 +#define FIQ_GPIO3 INT_GPIO3
2104 +#define FIQ_I2C INT_I2C
2105 +#define FIQ_SPI INT_SPI
2106 +#define FIQ_I2SPCM INT_I2SPCM
2107 +#define FIQ_SDIO INT_SDIO
2108 +#define FIQ_UART INT_UART
2109 +#define FIQ_SLIMBUS INT_SLIMBUS
2110 +#define FIQ_VEC INT_VEC
2111 +#define FIQ_CPG INT_CPG
2112 +#define FIQ_RNG INT_RNG
2113 +#define FIQ_ARASANSDIO INT_ARASANSDIO
2114 +#define FIQ_AVSPMON INT_AVSPMON
2115 +
2116 +#define FIQ_ARM_TIMER INT_ARM_TIMER
2117 +#define FIQ_ARM_MAILBOX INT_ARM_MAILBOX
2118 +#define FIQ_ARM_DOORBELL_0 INT_ARM_DOORBELL_0
2119 +#define FIQ_ARM_DOORBELL_1 INT_ARM_DOORBELL_1
2120 +#define FIQ_VPU0_HALTED INT_VPU0_HALTED
2121 +#define FIQ_VPU1_HALTED INT_VPU1_HALTED
2122 +#define FIQ_ILLEGAL_TYPE0 INT_ILLEGAL_TYPE0
2123 +#define FIQ_ILLEGAL_TYPE1 INT_ILLEGAL_TYPE1
2124 +#define FIQ_PENDING1 INT_PENDING1
2125 +#define FIQ_PENDING2 INT_PENDING2
2126 +
2127 +#define HARD_IRQS (64 + 21)
2128 +#define GPIO_IRQ_START (HARD_IRQS)
2129 +#define GPIO_IRQS (32*5)
2130 +#define SPARE_ALLOC_IRQS 64
2131 +#define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS)
2132 +#define FREE_IRQS 128
2133 +#define NR_IRQS (BCM2708_ALLOC_IRQS+FREE_IRQS)
2134 +
2135 +#endif /* _BCM2708_IRQS_H_ */
2136 --- /dev/null
2137 +++ b/arch/arm/mach-bcm2708/include/mach/memory.h
2138 @@ -0,0 +1,57 @@
2139 +/*
2140 + * arch/arm/mach-bcm2708/include/mach/memory.h
2141 + *
2142 + * Copyright (C) 2010 Broadcom
2143 + *
2144 + * This program is free software; you can redistribute it and/or modify
2145 + * it under the terms of the GNU General Public License as published by
2146 + * the Free Software Foundation; either version 2 of the License, or
2147 + * (at your option) any later version.
2148 + *
2149 + * This program is distributed in the hope that it will be useful,
2150 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2151 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2152 + * GNU General Public License for more details.
2153 + *
2154 + * You should have received a copy of the GNU General Public License
2155 + * along with this program; if not, write to the Free Software
2156 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2157 + */
2158 +#ifndef __ASM_ARCH_MEMORY_H
2159 +#define __ASM_ARCH_MEMORY_H
2160 +
2161 +/* Memory overview:
2162 +
2163 + [ARMcore] <--virtual addr-->
2164 + [ARMmmu] <--physical addr-->
2165 + [GERTmap] <--bus add-->
2166 + [VCperiph]
2167 +
2168 +*/
2169 +
2170 +/*
2171 + * Physical DRAM offset.
2172 + */
2173 +#define BCM_PLAT_PHYS_OFFSET UL(0x00000000)
2174 +#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */
2175 +
2176 +#ifdef CONFIG_BCM2708_NOL2CACHE
2177 + #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */
2178 +#else
2179 + #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */
2180 +#endif
2181 +
2182 +/* We're using the memory at 64M in the VideoCore for Linux - this adjustment
2183 + * will provide the offset into this area as well as setting the bits that
2184 + * stop the L1 and L2 cache from being used
2185 + *
2186 + * WARNING: this only works because the ARM is given memory at a fixed location
2187 + * (ARMMEM_OFFSET)
2188 + */
2189 +#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET)
2190 +#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET))
2191 +#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET))
2192 +#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
2193 +#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
2194 +
2195 +#endif
2196 --- /dev/null
2197 +++ b/arch/arm/mach-bcm2708/include/mach/platform.h
2198 @@ -0,0 +1,228 @@
2199 +/*
2200 + * arch/arm/mach-bcm2708/include/mach/platform.h
2201 + *
2202 + * Copyright (C) 2010 Broadcom
2203 + *
2204 + * This program is free software; you can redistribute it and/or modify
2205 + * it under the terms of the GNU General Public License as published by
2206 + * the Free Software Foundation; either version 2 of the License, or
2207 + * (at your option) any later version.
2208 + *
2209 + * This program is distributed in the hope that it will be useful,
2210 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2211 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2212 + * GNU General Public License for more details.
2213 + *
2214 + * You should have received a copy of the GNU General Public License
2215 + * along with this program; if not, write to the Free Software
2216 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2217 + */
2218 +
2219 +#ifndef _BCM2708_PLATFORM_H
2220 +#define _BCM2708_PLATFORM_H
2221 +
2222 +
2223 +/* macros to get at IO space when running virtually */
2224 +#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
2225 +
2226 +#define __io_address(n) IOMEM(IO_ADDRESS(n))
2227 +
2228 +
2229 +/*
2230 + * SDRAM
2231 + */
2232 +#define BCM2708_SDRAM_BASE 0x00000000
2233 +
2234 +/*
2235 + * Logic expansion modules
2236 + *
2237 + */
2238 +
2239 +
2240 +/* ------------------------------------------------------------------------
2241 + * BCM2708 ARMCTRL Registers
2242 + * ------------------------------------------------------------------------
2243 + */
2244 +
2245 +#define HW_REGISTER_RW(addr) (addr)
2246 +#define HW_REGISTER_RO(addr) (addr)
2247 +
2248 +#include "arm_control.h"
2249 +#undef ARM_BASE
2250 +
2251 +/*
2252 + * Definitions and addresses for the ARM CONTROL logic
2253 + * This file is manually generated.
2254 + */
2255 +
2256 +#define BCM2708_PERI_BASE 0x20000000
2257 +#define IC0_BASE (BCM2708_PERI_BASE + 0x2000)
2258 +#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */
2259 +#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */
2260 +#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */
2261 +#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */
2262 +#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
2263 +#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */
2264 +#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */
2265 +#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */
2266 +#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */
2267 +#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
2268 +#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */
2269 +#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */
2270 +#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */
2271 +#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
2272 +#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
2273 +#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */
2274 +#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */
2275 +#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
2276 +#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/
2277 +
2278 +#define ARMCTRL_BASE (ARM_BASE + 0x000)
2279 +#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */
2280 +#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */
2281 +#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
2282 +
2283 +
2284 +/*
2285 + * Interrupt assignments
2286 + */
2287 +
2288 +#define ARM_IRQ1_BASE 0
2289 +#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0)
2290 +#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1)
2291 +#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2)
2292 +#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3)
2293 +#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4)
2294 +#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5)
2295 +#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6)
2296 +#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7)
2297 +#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8)
2298 +#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9)
2299 +#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10)
2300 +#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11)
2301 +#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12)
2302 +#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13)
2303 +#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14)
2304 +#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15)
2305 +#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16)
2306 +#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17)
2307 +#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18)
2308 +#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19)
2309 +#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20)
2310 +#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21)
2311 +#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22)
2312 +#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23)
2313 +#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24)
2314 +#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25)
2315 +#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26)
2316 +#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27)
2317 +#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28)
2318 +#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29)
2319 +#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30)
2320 +#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31)
2321 +
2322 +#define ARM_IRQ2_BASE 32
2323 +#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0)
2324 +#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1)
2325 +#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2)
2326 +#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3)
2327 +#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4)
2328 +#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5)
2329 +#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6)
2330 +#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7)
2331 +#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8)
2332 +#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9)
2333 +#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10)
2334 +#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11)
2335 +#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12)
2336 +#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13)
2337 +#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14)
2338 +#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15)
2339 +#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16)
2340 +#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17)
2341 +#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18)
2342 +#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19)
2343 +#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20)
2344 +#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21)
2345 +#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22)
2346 +#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23)
2347 +#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24)
2348 +#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25)
2349 +#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26)
2350 +#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27)
2351 +#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28)
2352 +#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29)
2353 +#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30)
2354 +#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31)
2355 +
2356 +#define ARM_IRQ0_BASE 64
2357 +#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0)
2358 +#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1)
2359 +#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2)
2360 +#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3)
2361 +#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4)
2362 +#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5)
2363 +#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6)
2364 +#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7)
2365 +#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8)
2366 +#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9)
2367 +#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10)
2368 +#define INTERRUPT_USB (ARM_IRQ0_BASE + 11)
2369 +#define INTERRUPT_3D (ARM_IRQ0_BASE + 12)
2370 +#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13)
2371 +#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14)
2372 +#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15)
2373 +#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16)
2374 +#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17)
2375 +#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18)
2376 +#define INTERRUPT_UART (ARM_IRQ0_BASE + 19)
2377 +#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20)
2378 +
2379 +#define MAXIRQNUM (32 + 32 + 20)
2380 +#define MAXFIQNUM (32 + 32 + 20)
2381 +
2382 +#define MAX_TIMER 2
2383 +#define MAX_PERIOD 699050
2384 +#define TICKS_PER_uSEC 1
2385 +
2386 +/*
2387 + * These are useconds NOT ticks.
2388 + *
2389 + */
2390 +#define mSEC_1 1000
2391 +#define mSEC_5 (mSEC_1 * 5)
2392 +#define mSEC_10 (mSEC_1 * 10)
2393 +#define mSEC_25 (mSEC_1 * 25)
2394 +#define SEC_1 (mSEC_1 * 1000)
2395 +
2396 +/*
2397 + * Watchdog
2398 + */
2399 +#define PM_RSTC (PM_BASE+0x1c)
2400 +#define PM_RSTS (PM_BASE+0x20)
2401 +#define PM_WDOG (PM_BASE+0x24)
2402 +
2403 +#define PM_WDOG_RESET 0000000000
2404 +#define PM_PASSWORD 0x5a000000
2405 +#define PM_WDOG_TIME_SET 0x000fffff
2406 +#define PM_RSTC_WRCFG_CLR 0xffffffcf
2407 +#define PM_RSTC_WRCFG_SET 0x00000030
2408 +#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
2409 +#define PM_RSTC_RESET 0x00000102
2410 +
2411 +#define PM_RSTS_HADPOR_SET 0x00001000
2412 +#define PM_RSTS_HADSRH_SET 0x00000400
2413 +#define PM_RSTS_HADSRF_SET 0x00000200
2414 +#define PM_RSTS_HADSRQ_SET 0x00000100
2415 +#define PM_RSTS_HADWRH_SET 0x00000040
2416 +#define PM_RSTS_HADWRF_SET 0x00000020
2417 +#define PM_RSTS_HADWRQ_SET 0x00000010
2418 +#define PM_RSTS_HADDRH_SET 0x00000004
2419 +#define PM_RSTS_HADDRF_SET 0x00000002
2420 +#define PM_RSTS_HADDRQ_SET 0x00000001
2421 +
2422 +#define UART0_CLOCK 3000000
2423 +
2424 +#endif
2425 +
2426 +/* END */
2427 --- /dev/null
2428 +++ b/arch/arm/mach-bcm2708/include/mach/system.h
2429 @@ -0,0 +1,38 @@
2430 +/*
2431 + * arch/arm/mach-bcm2708/include/mach/system.h
2432 + *
2433 + * Copyright (C) 2010 Broadcom
2434 + * Copyright (C) 2003 ARM Limited
2435 + * Copyright (C) 2000 Deep Blue Solutions Ltd
2436 + *
2437 + * This program is free software; you can redistribute it and/or modify
2438 + * it under the terms of the GNU General Public License as published by
2439 + * the Free Software Foundation; either version 2 of the License, or
2440 + * (at your option) any later version.
2441 + *
2442 + * This program is distributed in the hope that it will be useful,
2443 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2444 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2445 + * GNU General Public License for more details.
2446 + *
2447 + * You should have received a copy of the GNU General Public License
2448 + * along with this program; if not, write to the Free Software
2449 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2450 + */
2451 +#ifndef __ASM_ARCH_SYSTEM_H
2452 +#define __ASM_ARCH_SYSTEM_H
2453 +
2454 +#include <linux/io.h>
2455 +#include <mach/hardware.h>
2456 +#include <mach/platform.h>
2457 +
2458 +static inline void arch_idle(void)
2459 +{
2460 + /*
2461 + * This should do all the clock switching
2462 + * and wait for interrupt tricks
2463 + */
2464 + cpu_do_idle();
2465 +}
2466 +
2467 +#endif
2468 --- /dev/null
2469 +++ b/arch/arm/mach-bcm2708/include/mach/timex.h
2470 @@ -0,0 +1,23 @@
2471 +/*
2472 + * arch/arm/mach-bcm2708/include/mach/timex.h
2473 + *
2474 + * BCM2708 sysem clock frequency
2475 + *
2476 + * Copyright (C) 2010 Broadcom
2477 + *
2478 + * This program is free software; you can redistribute it and/or modify
2479 + * it under the terms of the GNU General Public License as published by
2480 + * the Free Software Foundation; either version 2 of the License, or
2481 + * (at your option) any later version.
2482 + *
2483 + * This program is distributed in the hope that it will be useful,
2484 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2485 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2486 + * GNU General Public License for more details.
2487 + *
2488 + * You should have received a copy of the GNU General Public License
2489 + * along with this program; if not, write to the Free Software
2490 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2491 + */
2492 +
2493 +#define CLOCK_TICK_RATE (1000000)
2494 --- /dev/null
2495 +++ b/arch/arm/mach-bcm2708/include/mach/uncompress.h
2496 @@ -0,0 +1,84 @@
2497 +/*
2498 + * arch/arm/mach-bcn2708/include/mach/uncompress.h
2499 + *
2500 + * Copyright (C) 2010 Broadcom
2501 + * Copyright (C) 2003 ARM Limited
2502 + *
2503 + * This program is free software; you can redistribute it and/or modify
2504 + * it under the terms of the GNU General Public License as published by
2505 + * the Free Software Foundation; either version 2 of the License, or
2506 + * (at your option) any later version.
2507 + *
2508 + * This program is distributed in the hope that it will be useful,
2509 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2510 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2511 + * GNU General Public License for more details.
2512 + *
2513 + * You should have received a copy of the GNU General Public License
2514 + * along with this program; if not, write to the Free Software
2515 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2516 + */
2517 +
2518 +#include <linux/io.h>
2519 +#include <linux/amba/serial.h>
2520 +#include <mach/hardware.h>
2521 +
2522 +#define UART_BAUD 115200
2523 +
2524 +#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR)
2525 +#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR)
2526 +#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD)
2527 +#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD)
2528 +#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH)
2529 +#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR)
2530 +
2531 +/*
2532 + * This does not append a newline
2533 + */
2534 +static inline void putc(int c)
2535 +{
2536 + while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF)
2537 + barrier();
2538 +
2539 + __raw_writel(c, BCM2708_UART_DR);
2540 +}
2541 +
2542 +static inline void flush(void)
2543 +{
2544 + int fr;
2545 +
2546 + do {
2547 + fr = __raw_readl(BCM2708_UART_FR);
2548 + barrier();
2549 + } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
2550 +}
2551 +
2552 +static inline void arch_decomp_setup(void)
2553 +{
2554 + int temp, div, rem, frac;
2555 +
2556 + temp = 16 * UART_BAUD;
2557 + div = UART0_CLOCK / temp;
2558 + rem = UART0_CLOCK % temp;
2559 + temp = (8 * rem) / UART_BAUD;
2560 + frac = (temp >> 1) + (temp & 1);
2561 +
2562 + /* Make sure the UART is disabled before we start */
2563 + __raw_writel(0, BCM2708_UART_CR);
2564 +
2565 + /* Set the baud rate */
2566 + __raw_writel(div, BCM2708_UART_IBRD);
2567 + __raw_writel(frac, BCM2708_UART_FBRD);
2568 +
2569 + /* Set the UART to 8n1, FIFO enabled */
2570 + __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH);
2571 +
2572 + /* Enable the UART */
2573 + __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE,
2574 + BCM2708_UART_CR);
2575 +}
2576 +
2577 +/*
2578 + * nothing to do
2579 + */
2580 +#define arch_decomp_wdog()
2581 --- /dev/null
2582 +++ b/arch/arm/mach-bcm2708/include/mach/vmalloc.h
2583 @@ -0,0 +1,20 @@
2584 +/*
2585 + * arch/arm/mach-bcm2708/include/mach/vmalloc.h
2586 + *
2587 + * Copyright (C) 2010 Broadcom
2588 + *
2589 + * This program is free software; you can redistribute it and/or modify
2590 + * it under the terms of the GNU General Public License as published by
2591 + * the Free Software Foundation; either version 2 of the License, or
2592 + * (at your option) any later version.
2593 + *
2594 + * This program is distributed in the hope that it will be useful,
2595 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2596 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2597 + * GNU General Public License for more details.
2598 + *
2599 + * You should have received a copy of the GNU General Public License
2600 + * along with this program; if not, write to the Free Software
2601 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2602 + */
2603 +#define VMALLOC_END (0xe8000000)
2604 --- /dev/null
2605 +++ b/arch/arm/mach-bcm2709/Kconfig
2606 @@ -0,0 +1,42 @@
2607 +menu "Broadcom BCM2709 Implementations"
2608 + depends on ARCH_BCM2709
2609 +
2610 +config MACH_BCM2709
2611 + bool "Broadcom BCM2709 Development Platform"
2612 + help
2613 + Include support for the Broadcom(R) BCM2709 platform.
2614 +
2615 +config BCM2709_DT
2616 + bool "BCM2709 Device Tree support"
2617 + depends on MACH_BCM2709
2618 + default n
2619 + select USE_OF
2620 + select ARCH_REQUIRE_GPIOLIB
2621 + select PINCTRL
2622 + select PINCTRL_BCM2835
2623 + help
2624 + Enable Device Tree support for BCM2709
2625 +
2626 +config BCM2708_GPIO
2627 + bool "BCM2709 gpio support"
2628 + depends on MACH_BCM2709
2629 + select ARCH_REQUIRE_GPIOLIB
2630 + default y
2631 + help
2632 + Include support for the Broadcom(R) BCM2709 gpio.
2633 +
2634 +config BCM2708_NOL2CACHE
2635 + bool "Videocore L2 cache disable"
2636 + depends on MACH_BCM2709
2637 + default y
2638 + help
2639 + Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
2640 +
2641 +config BCM2708_SPIDEV
2642 + bool "Bind spidev to SPI0 master"
2643 + depends on MACH_BCM2709
2644 + depends on SPI
2645 + default y
2646 + help
2647 + Binds spidev driver to the SPI0 master
2648 +endmenu
2649 --- /dev/null
2650 +++ b/arch/arm/mach-bcm2709/Makefile
2651 @@ -0,0 +1,6 @@
2652 +#
2653 +# Makefile for the linux kernel.
2654 +#
2655 +
2656 +obj-$(CONFIG_MACH_BCM2709) += bcm2709.o armctrl.o
2657 +obj-$(CONFIG_BCM2708_GPIO) += bcm2708_gpio.o
2658 --- /dev/null
2659 +++ b/arch/arm/mach-bcm2709/Makefile.boot
2660 @@ -0,0 +1,3 @@
2661 + zreladdr-y := 0x00008000
2662 +params_phys-y := 0x00000100
2663 +initrd_phys-y := 0x00800000
2664 --- /dev/null
2665 +++ b/arch/arm/mach-bcm2709/armctrl.c
2666 @@ -0,0 +1,361 @@
2667 +/*
2668 + * linux/arch/arm/mach-bcm2708/armctrl.c
2669 + *
2670 + * Copyright (C) 2010 Broadcom
2671 + *
2672 + * This program is free software; you can redistribute it and/or modify
2673 + * it under the terms of the GNU General Public License as published by
2674 + * the Free Software Foundation; either version 2 of the License, or
2675 + * (at your option) any later version.
2676 + *
2677 + * This program is distributed in the hope that it will be useful,
2678 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2679 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2680 + * GNU General Public License for more details.
2681 + *
2682 + * You should have received a copy of the GNU General Public License
2683 + * along with this program; if not, write to the Free Software
2684 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2685 + */
2686 +#include <linux/init.h>
2687 +#include <linux/list.h>
2688 +#include <linux/io.h>
2689 +#include <linux/version.h>
2690 +#include <linux/syscore_ops.h>
2691 +#include <linux/interrupt.h>
2692 +#include <linux/irqdomain.h>
2693 +#include <linux/of.h>
2694 +
2695 +#include <asm/mach/irq.h>
2696 +#include <mach/hardware.h>
2697 +#include "armctrl.h"
2698 +
2699 +/* For support of kernels >= 3.0 assume only one VIC for now*/
2700 +static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = {
2701 + INTERRUPT_VC_JPEG,
2702 + INTERRUPT_VC_USB,
2703 + INTERRUPT_VC_3D,
2704 + INTERRUPT_VC_DMA2,
2705 + INTERRUPT_VC_DMA3,
2706 + INTERRUPT_VC_I2C,
2707 + INTERRUPT_VC_SPI,
2708 + INTERRUPT_VC_I2SPCM,
2709 + INTERRUPT_VC_SDIO,
2710 + INTERRUPT_VC_UART,
2711 + INTERRUPT_VC_ARASANSDIO
2712 +};
2713 +
2714 +static void armctrl_mask_irq(struct irq_data *d)
2715 +{
2716 + static const unsigned int disables[4] = {
2717 + ARM_IRQ_DIBL1,
2718 + ARM_IRQ_DIBL2,
2719 + ARM_IRQ_DIBL3,
2720 + 0
2721 + };
2722 + int i;
2723 + if (d->irq >= FIQ_START) {
2724 + writel(0, __io_address(ARM_IRQ_FAST));
2725 + } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) {
2726 +#if 1
2727 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ;
2728 + for (i=0; i<4; i++) // i = raw_smp_processor_id(); //
2729 + {
2730 + unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i));
2731 + writel(val &~ (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i));
2732 + }
2733 +#endif
2734 + } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) {
2735 +#if 0
2736 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0;
2737 + for (i=0; i<4; i++) {
2738 + unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i));
2739 + writel(val &~ (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i));
2740 + }
2741 +#endif
2742 + } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) {
2743 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
2744 + writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3]));
2745 + } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) {
2746 + writel(0xf, __io_address(ARM_LOCAL_PM_ROUTING_CLR));
2747 + } else { printk("%s: %d\n", __func__, d->irq); BUG(); }
2748 +}
2749 +
2750 +static void armctrl_unmask_irq(struct irq_data *d)
2751 +{
2752 + static const unsigned int enables[4] = {
2753 + ARM_IRQ_ENBL1,
2754 + ARM_IRQ_ENBL2,
2755 + ARM_IRQ_ENBL3,
2756 + 0
2757 + };
2758 + int i;
2759 + if (d->irq >= FIQ_START) {
2760 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START;
2761 + writel(0x80 | data, __io_address(ARM_IRQ_FAST));
2762 + } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) {
2763 +#if 1
2764 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ;
2765 + for (i=0; i<4; i++) // i = raw_smp_processor_id();
2766 + {
2767 + unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i));
2768 + writel(val | (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i));
2769 + }
2770 +#endif
2771 + } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) {
2772 +#if 0
2773 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0;
2774 + for (i=0; i<4; i++) {
2775 + unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i));
2776 + writel(val | (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i));
2777 + }
2778 +#endif
2779 + } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) {
2780 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
2781 + writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3]));
2782 + } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) {
2783 + writel(0xf, __io_address(ARM_LOCAL_PM_ROUTING_SET));
2784 + } else { printk("%s: %d\n", __func__, d->irq); BUG(); }
2785 +}
2786 +
2787 +#ifdef CONFIG_OF
2788 +
2789 +#define NR_IRQS_BANK0 21
2790 +#define NR_BANKS 4
2791 +#define IRQS_PER_BANK 32
2792 +
2793 +/* from drivers/irqchip/irq-bcm2835.c */
2794 +static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
2795 + const u32 *intspec, unsigned int intsize,
2796 + unsigned long *out_hwirq, unsigned int *out_type)
2797 +{
2798 + if (WARN_ON(intsize != 2))
2799 + return -EINVAL;
2800 +
2801 + if (WARN_ON(intspec[0] >= NR_BANKS))
2802 + return -EINVAL;
2803 +
2804 + if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
2805 + return -EINVAL;
2806 +
2807 + if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
2808 + return -EINVAL;
2809 +
2810 + if (WARN_ON(intspec[0] == 3 && intspec[1] > 3 && intspec[1] != 5 && intspec[1] != 9))
2811 + return -EINVAL;
2812 +
2813 + if (intspec[0] == 0)
2814 + *out_hwirq = ARM_IRQ0_BASE + intspec[1];
2815 + else if (intspec[0] == 1)
2816 + *out_hwirq = ARM_IRQ1_BASE + intspec[1];
2817 + else if (intspec[0] == 2)
2818 + *out_hwirq = ARM_IRQ2_BASE + intspec[1];
2819 + else
2820 + *out_hwirq = ARM_IRQ_LOCAL_BASE + intspec[1];
2821 +
2822 + /* reverse remap_irqs[] */
2823 + switch (*out_hwirq) {
2824 + case INTERRUPT_VC_JPEG:
2825 + *out_hwirq = INTERRUPT_JPEG;
2826 + break;
2827 + case INTERRUPT_VC_USB:
2828 + *out_hwirq = INTERRUPT_USB;
2829 + break;
2830 + case INTERRUPT_VC_3D:
2831 + *out_hwirq = INTERRUPT_3D;
2832 + break;
2833 + case INTERRUPT_VC_DMA2:
2834 + *out_hwirq = INTERRUPT_DMA2;
2835 + break;
2836 + case INTERRUPT_VC_DMA3:
2837 + *out_hwirq = INTERRUPT_DMA3;
2838 + break;
2839 + case INTERRUPT_VC_I2C:
2840 + *out_hwirq = INTERRUPT_I2C;
2841 + break;
2842 + case INTERRUPT_VC_SPI:
2843 + *out_hwirq = INTERRUPT_SPI;
2844 + break;
2845 + case INTERRUPT_VC_I2SPCM:
2846 + *out_hwirq = INTERRUPT_I2SPCM;
2847 + break;
2848 + case INTERRUPT_VC_SDIO:
2849 + *out_hwirq = INTERRUPT_SDIO;
2850 + break;
2851 + case INTERRUPT_VC_UART:
2852 + *out_hwirq = INTERRUPT_UART;
2853 + break;
2854 + case INTERRUPT_VC_ARASANSDIO:
2855 + *out_hwirq = INTERRUPT_ARASANSDIO;
2856 + break;
2857 + }
2858 +
2859 + *out_type = IRQ_TYPE_NONE;
2860 + return 0;
2861 +}
2862 +
2863 +static struct irq_domain_ops armctrl_ops = {
2864 + .xlate = armctrl_xlate
2865 +};
2866 +
2867 +void __init armctrl_dt_init(void)
2868 +{
2869 + struct device_node *np;
2870 + struct irq_domain *domain;
2871 +
2872 + np = of_find_compatible_node(NULL, NULL, "brcm,bcm2708-armctrl-ic");
2873 + if (!np)
2874 + return;
2875 +
2876 + domain = irq_domain_add_legacy(np, BCM2708_ALLOC_IRQS,
2877 + IRQ_ARMCTRL_START, 0,
2878 + &armctrl_ops, NULL);
2879 + WARN_ON(!domain);
2880 +}
2881 +#else
2882 +void __init armctrl_dt_init(void) { }
2883 +#endif /* CONFIG_OF */
2884 +
2885 +#if defined(CONFIG_PM)
2886 +
2887 +/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */
2888 +
2889 +/* Static defines
2890 + * struct armctrl_device - VIC PM device (< 3.xx)
2891 + * @sysdev: The system device which is registered. (< 3.xx)
2892 + * @irq: The IRQ number for the base of the VIC.
2893 + * @base: The register base for the VIC.
2894 + * @resume_sources: A bitmask of interrupts for resume.
2895 + * @resume_irqs: The IRQs enabled for resume.
2896 + * @int_select: Save for VIC_INT_SELECT.
2897 + * @int_enable: Save for VIC_INT_ENABLE.
2898 + * @soft_int: Save for VIC_INT_SOFT.
2899 + * @protect: Save for VIC_PROTECT.
2900 + */
2901 +struct armctrl_info {
2902 + void __iomem *base;
2903 + int irq;
2904 + u32 resume_sources;
2905 + u32 resume_irqs;
2906 + u32 int_select;
2907 + u32 int_enable;
2908 + u32 soft_int;
2909 + u32 protect;
2910 +} armctrl;
2911 +
2912 +static int armctrl_suspend(void)
2913 +{
2914 + return 0;
2915 +}
2916 +
2917 +static void armctrl_resume(void)
2918 +{
2919 + return;
2920 +}
2921 +
2922 +/**
2923 + * armctrl_pm_register - Register a VIC for later power management control
2924 + * @base: The base address of the VIC.
2925 + * @irq: The base IRQ for the VIC.
2926 + * @resume_sources: bitmask of interrupts allowed for resume sources.
2927 + *
2928 + * For older kernels (< 3.xx) do -
2929 + * Register the VIC with the system device tree so that it can be notified
2930 + * of suspend and resume requests and ensure that the correct actions are
2931 + * taken to re-instate the settings on resume.
2932 + */
2933 +static void __init armctrl_pm_register(void __iomem * base, unsigned int irq,
2934 + u32 resume_sources)
2935 +{
2936 + armctrl.base = base;
2937 + armctrl.resume_sources = resume_sources;
2938 + armctrl.irq = irq;
2939 +}
2940 +
2941 +static int armctrl_set_wake(struct irq_data *d, unsigned int on)
2942 +{
2943 + unsigned int off = d->irq & 31;
2944 + u32 bit = 1 << off;
2945 +
2946 + if (!(bit & armctrl.resume_sources))
2947 + return -EINVAL;
2948 +
2949 + if (on)
2950 + armctrl.resume_irqs |= bit;
2951 + else
2952 + armctrl.resume_irqs &= ~bit;
2953 +
2954 + return 0;
2955 +}
2956 +
2957 +#else
2958 +static inline void armctrl_pm_register(void __iomem * base, unsigned int irq,
2959 + u32 arg1)
2960 +{
2961 +}
2962 +
2963 +#define armctrl_suspend NULL
2964 +#define armctrl_resume NULL
2965 +#define armctrl_set_wake NULL
2966 +#endif /* CONFIG_PM */
2967 +
2968 +static struct syscore_ops armctrl_syscore_ops = {
2969 + .suspend = armctrl_suspend,
2970 + .resume = armctrl_resume,
2971 +};
2972 +
2973 +/**
2974 + * armctrl_syscore_init - initicall to register VIC pm functions
2975 + *
2976 + * This is called via late_initcall() to register
2977 + * the resources for the VICs due to the early
2978 + * nature of the VIC's registration.
2979 +*/
2980 +static int __init armctrl_syscore_init(void)
2981 +{
2982 + register_syscore_ops(&armctrl_syscore_ops);
2983 + return 0;
2984 +}
2985 +
2986 +late_initcall(armctrl_syscore_init);
2987 +
2988 +static struct irq_chip armctrl_chip = {
2989 + .name = "ARMCTRL",
2990 + .irq_ack = NULL,
2991 + .irq_mask = armctrl_mask_irq,
2992 + .irq_unmask = armctrl_unmask_irq,
2993 + .irq_set_wake = armctrl_set_wake,
2994 +};
2995 +
2996 +/**
2997 + * armctrl_init - initialise a vectored interrupt controller
2998 + * @base: iomem base address
2999 + * @irq_start: starting interrupt number, must be muliple of 32
3000 + * @armctrl_sources: bitmask of interrupt sources to allow
3001 + * @resume_sources: bitmask of interrupt sources to allow for resume
3002 + */
3003 +int __init armctrl_init(void __iomem * base, unsigned int irq_start,
3004 + u32 armctrl_sources, u32 resume_sources)
3005 +{
3006 + unsigned int irq;
3007 +
3008 + for (irq = 0; irq < BCM2708_ALLOC_IRQS; irq++) {
3009 + unsigned int data = irq;
3010 + if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO)
3011 + data = remap_irqs[irq - INTERRUPT_JPEG];
3012 + if (irq >= IRQ_ARM_LOCAL_CNTPSIRQ && irq <= IRQ_ARM_LOCAL_TIMER) {
3013 + irq_set_percpu_devid(irq);
3014 + irq_set_chip_and_handler(irq, &armctrl_chip, handle_percpu_devid_irq);
3015 + set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
3016 + } else {
3017 + irq_set_chip_and_handler(irq, &armctrl_chip, handle_level_irq);
3018 + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
3019 + }
3020 + irq_set_chip_data(irq, (void *)data);
3021 + }
3022 +
3023 + armctrl_pm_register(base, irq_start, resume_sources);
3024 + init_FIQ(FIQ_START);
3025 + armctrl_dt_init();
3026 + return 0;
3027 +}
3028 --- /dev/null
3029 +++ b/arch/arm/mach-bcm2709/armctrl.h
3030 @@ -0,0 +1,27 @@
3031 +/*
3032 + * linux/arch/arm/mach-bcm2708/armctrl.h
3033 + *
3034 + * Copyright (C) 2010 Broadcom
3035 + *
3036 + * This program is free software; you can redistribute it and/or modify
3037 + * it under the terms of the GNU General Public License as published by
3038 + * the Free Software Foundation; either version 2 of the License, or
3039 + * (at your option) any later version.
3040 + *
3041 + * This program is distributed in the hope that it will be useful,
3042 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3043 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3044 + * GNU General Public License for more details.
3045 + *
3046 + * You should have received a copy of the GNU General Public License
3047 + * along with this program; if not, write to the Free Software
3048 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3049 + */
3050 +
3051 +#ifndef __BCM2708_ARMCTRL_H
3052 +#define __BCM2708_ARMCTRL_H
3053 +
3054 +extern int __init armctrl_init(void __iomem * base, unsigned int irq_start,
3055 + u32 armctrl_sources, u32 resume_sources);
3056 +
3057 +#endif
3058 --- /dev/null
3059 +++ b/arch/arm/mach-bcm2709/bcm2708_gpio.c
3060 @@ -0,0 +1,426 @@
3061 +/*
3062 + * linux/arch/arm/mach-bcm2708/bcm2708_gpio.c
3063 + *
3064 + * Copyright (C) 2010 Broadcom
3065 + *
3066 + * This program is free software; you can redistribute it and/or modify
3067 + * it under the terms of the GNU General Public License version 2 as
3068 + * published by the Free Software Foundation.
3069 + *
3070 + */
3071 +
3072 +#include <linux/spinlock.h>
3073 +#include <linux/module.h>
3074 +#include <linux/delay.h>
3075 +#include <linux/list.h>
3076 +#include <linux/io.h>
3077 +#include <linux/irq.h>
3078 +#include <linux/interrupt.h>
3079 +#include <linux/slab.h>
3080 +#include <mach/gpio.h>
3081 +#include <linux/gpio.h>
3082 +#include <linux/platform_device.h>
3083 +#include <mach/platform.h>
3084 +#include <linux/pinctrl/consumer.h>
3085 +
3086 +#include <linux/platform_data/bcm2708.h>
3087 +
3088 +#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
3089 +#define DRIVER_NAME BCM_GPIO_DRIVER_NAME
3090 +#define BCM_GPIO_USE_IRQ 1
3091 +
3092 +#define GPIOFSEL(x) (0x00+(x)*4)
3093 +#define GPIOSET(x) (0x1c+(x)*4)
3094 +#define GPIOCLR(x) (0x28+(x)*4)
3095 +#define GPIOLEV(x) (0x34+(x)*4)
3096 +#define GPIOEDS(x) (0x40+(x)*4)
3097 +#define GPIOREN(x) (0x4c+(x)*4)
3098 +#define GPIOFEN(x) (0x58+(x)*4)
3099 +#define GPIOHEN(x) (0x64+(x)*4)
3100 +#define GPIOLEN(x) (0x70+(x)*4)
3101 +#define GPIOAREN(x) (0x7c+(x)*4)
3102 +#define GPIOAFEN(x) (0x88+(x)*4)
3103 +#define GPIOUD(x) (0x94+(x)*4)
3104 +#define GPIOUDCLK(x) (0x98+(x)*4)
3105 +
3106 +#define GPIO_BANKS 2
3107 +
3108 +enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT,
3109 + GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4,
3110 + GPIO_FSEL_ALT0, GPIO_FSEL_ALT1,
3111 + GPIO_FSEL_ALT2, GPIO_FSEL_ALT3,
3112 +};
3113 +
3114 + /* Each of the two spinlocks protects a different set of hardware
3115 + * regiters and data structurs. This decouples the code of the IRQ from
3116 + * the GPIO code. This also makes the case of a GPIO routine call from
3117 + * the IRQ code simpler.
3118 + */
3119 +static DEFINE_SPINLOCK(lock); /* GPIO registers */
3120 +
3121 +struct bcm2708_gpio {
3122 + struct list_head list;
3123 + void __iomem *base;
3124 + struct gpio_chip gc;
3125 + unsigned long rising[(BCM2708_NR_GPIOS + 31) / 32];
3126 + unsigned long falling[(BCM2708_NR_GPIOS + 31) / 32];
3127 + unsigned long high[(BCM2708_NR_GPIOS + 31) / 32];
3128 + unsigned long low[(BCM2708_NR_GPIOS + 31) / 32];
3129 +};
3130 +
3131 +static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset,
3132 + int function)
3133 +{
3134 + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
3135 + unsigned long flags;
3136 + unsigned gpiodir;
3137 + unsigned gpio_bank = offset / 10;
3138 + unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3;
3139 +
3140 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function);
3141 + if (offset >= BCM2708_NR_GPIOS)
3142 + return -EINVAL;
3143 +
3144 + spin_lock_irqsave(&lock, flags);
3145 +
3146 + gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
3147 + gpiodir &= ~(7 << gpio_field_offset);
3148 + gpiodir |= function << gpio_field_offset;
3149 + writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank));
3150 + spin_unlock_irqrestore(&lock, flags);
3151 + gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
3152 +
3153 + return 0;
3154 +}
3155 +
3156 +static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset)
3157 +{
3158 + return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT);
3159 +}
3160 +
3161 +static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
3162 +static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset,
3163 + int value)
3164 +{
3165 + int ret;
3166 + ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT);
3167 + if (ret >= 0)
3168 + bcm2708_gpio_set(gc, offset, value);
3169 + return ret;
3170 +}
3171 +
3172 +static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset)
3173 +{
3174 + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
3175 + unsigned gpio_bank = offset / 32;
3176 + unsigned gpio_field_offset = (offset - 32 * gpio_bank);
3177 + unsigned lev;
3178 +
3179 + if (offset >= BCM2708_NR_GPIOS)
3180 + return 0;
3181 + lev = readl(gpio->base + GPIOLEV(gpio_bank));
3182 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset));
3183 + return 0x1 & (lev >> gpio_field_offset);
3184 +}
3185 +
3186 +static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
3187 +{
3188 + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
3189 + unsigned gpio_bank = offset / 32;
3190 + unsigned gpio_field_offset = (offset - 32 * gpio_bank);
3191 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value);
3192 + if (offset >= BCM2708_NR_GPIOS)
3193 + return;
3194 + if (value)
3195 + writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank));
3196 + else
3197 + writel(1 << gpio_field_offset, gpio->base + GPIOCLR(gpio_bank));
3198 +}
3199 +
3200 +/**********************
3201 + * extension to configure pullups
3202 + */
3203 +int bcm2708_gpio_setpull(struct gpio_chip *gc, unsigned offset,
3204 + bcm2708_gpio_pull_t value)
3205 +{
3206 + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
3207 + unsigned gpio_bank = offset / 32;
3208 + unsigned gpio_field_offset = (offset - 32 * gpio_bank);
3209 +
3210 + if (offset >= BCM2708_NR_GPIOS)
3211 + return -EINVAL;
3212 +
3213 + switch (value) {
3214 + case BCM2708_PULL_UP:
3215 + writel(2, gpio->base + GPIOUD(0));
3216 + break;
3217 + case BCM2708_PULL_DOWN:
3218 + writel(1, gpio->base + GPIOUD(0));
3219 + break;
3220 + case BCM2708_PULL_OFF:
3221 + writel(0, gpio->base + GPIOUD(0));
3222 + break;
3223 + }
3224 +
3225 + udelay(5);
3226 + writel(1 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank));
3227 + udelay(5);
3228 + writel(0, gpio->base + GPIOUD(0));
3229 + writel(0 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank));
3230 +
3231 + return 0;
3232 +}
3233 +EXPORT_SYMBOL(bcm2708_gpio_setpull);
3234 +
3235 +/*************************************************************************************************************************
3236 + * bcm2708 GPIO IRQ
3237 + */
3238 +
3239 +#if BCM_GPIO_USE_IRQ
3240 +
3241 +static int bcm2708_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
3242 +{
3243 + return gpio_to_irq(gpio);
3244 +}
3245 +
3246 +static int bcm2708_gpio_irq_set_type(struct irq_data *d, unsigned type)
3247 +{
3248 + unsigned irq = d->irq;
3249 + struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
3250 + unsigned gn = irq_to_gpio(irq);
3251 + unsigned gb = gn / 32;
3252 + unsigned go = gn % 32;
3253 +
3254 + gpio->rising[gb] &= ~(1 << go);
3255 + gpio->falling[gb] &= ~(1 << go);
3256 + gpio->high[gb] &= ~(1 << go);
3257 + gpio->low[gb] &= ~(1 << go);
3258 +
3259 + if (type & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
3260 + return -EINVAL;
3261 +
3262 + if (type & IRQ_TYPE_EDGE_RISING)
3263 + gpio->rising[gb] |= (1 << go);
3264 + if (type & IRQ_TYPE_EDGE_FALLING)
3265 + gpio->falling[gb] |= (1 << go);
3266 + if (type & IRQ_TYPE_LEVEL_HIGH)
3267 + gpio->high[gb] |= (1 << go);
3268 + if (type & IRQ_TYPE_LEVEL_LOW)
3269 + gpio->low[gb] |= (1 << go);
3270 + return 0;
3271 +}
3272 +
3273 +static void bcm2708_gpio_irq_mask(struct irq_data *d)
3274 +{
3275 + unsigned irq = d->irq;
3276 + struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
3277 + unsigned gn = irq_to_gpio(irq);
3278 + unsigned gb = gn / 32;
3279 + unsigned long rising = readl(gpio->base + GPIOREN(gb));
3280 + unsigned long falling = readl(gpio->base + GPIOFEN(gb));
3281 + unsigned long high = readl(gpio->base + GPIOHEN(gb));
3282 + unsigned long low = readl(gpio->base + GPIOLEN(gb));
3283 +
3284 + gn = gn % 32;
3285 +
3286 + writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb));
3287 + writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb));
3288 + writel(high & ~(1 << gn), gpio->base + GPIOHEN(gb));
3289 + writel(low & ~(1 << gn), gpio->base + GPIOLEN(gb));
3290 +}
3291 +
3292 +static void bcm2708_gpio_irq_unmask(struct irq_data *d)
3293 +{
3294 + unsigned irq = d->irq;
3295 + struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
3296 + unsigned gn = irq_to_gpio(irq);
3297 + unsigned gb = gn / 32;
3298 + unsigned go = gn % 32;
3299 + unsigned long rising = readl(gpio->base + GPIOREN(gb));
3300 + unsigned long falling = readl(gpio->base + GPIOFEN(gb));
3301 + unsigned long high = readl(gpio->base + GPIOHEN(gb));
3302 + unsigned long low = readl(gpio->base + GPIOLEN(gb));
3303 +
3304 + if (gpio->rising[gb] & (1 << go)) {
3305 + writel(rising | (1 << go), gpio->base + GPIOREN(gb));
3306 + } else {
3307 + writel(rising & ~(1 << go), gpio->base + GPIOREN(gb));
3308 + }
3309 +
3310 + if (gpio->falling[gb] & (1 << go)) {
3311 + writel(falling | (1 << go), gpio->base + GPIOFEN(gb));
3312 + } else {
3313 + writel(falling & ~(1 << go), gpio->base + GPIOFEN(gb));
3314 + }
3315 +
3316 + if (gpio->high[gb] & (1 << go)) {
3317 + writel(high | (1 << go), gpio->base + GPIOHEN(gb));
3318 + } else {
3319 + writel(high & ~(1 << go), gpio->base + GPIOHEN(gb));
3320 + }
3321 +
3322 + if (gpio->low[gb] & (1 << go)) {
3323 + writel(low | (1 << go), gpio->base + GPIOLEN(gb));
3324 + } else {
3325 + writel(low & ~(1 << go), gpio->base + GPIOLEN(gb));
3326 + }
3327 +}
3328 +
3329 +static struct irq_chip bcm2708_irqchip = {
3330 + .name = "GPIO",
3331 + .irq_enable = bcm2708_gpio_irq_unmask,
3332 + .irq_disable = bcm2708_gpio_irq_mask,
3333 + .irq_unmask = bcm2708_gpio_irq_unmask,
3334 + .irq_mask = bcm2708_gpio_irq_mask,
3335 + .irq_set_type = bcm2708_gpio_irq_set_type,
3336 +};
3337 +
3338 +static irqreturn_t bcm2708_gpio_interrupt(int irq, void *dev_id)
3339 +{
3340 + unsigned long edsr;
3341 + unsigned bank;
3342 + int i;
3343 + unsigned gpio;
3344 + unsigned level_bits;
3345 + struct bcm2708_gpio *gpio_data = dev_id;
3346 +
3347 + for (bank = 0; bank < GPIO_BANKS; bank++) {
3348 + edsr = readl(__io_address(GPIO_BASE) + GPIOEDS(bank));
3349 + level_bits = gpio_data->high[bank] | gpio_data->low[bank];
3350 +
3351 + for_each_set_bit(i, &edsr, 32) {
3352 + gpio = i + bank * 32;
3353 + /* ack edge triggered IRQs immediately */
3354 + if (!(level_bits & (1<<i)))
3355 + writel(1<<i,
3356 + __io_address(GPIO_BASE) + GPIOEDS(bank));
3357 + generic_handle_irq(gpio_to_irq(gpio));
3358 + /* ack level triggered IRQ after handling them */
3359 + if (level_bits & (1<<i))
3360 + writel(1<<i,
3361 + __io_address(GPIO_BASE) + GPIOEDS(bank));
3362 + }
3363 + }
3364 + return IRQ_HANDLED;
3365 +}
3366 +
3367 +static struct irqaction bcm2708_gpio_irq = {
3368 + .name = "BCM2708 GPIO catchall handler",
3369 + .flags = IRQF_TIMER | IRQF_IRQPOLL,
3370 + .handler = bcm2708_gpio_interrupt,
3371 +};
3372 +
3373 +static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
3374 +{
3375 + unsigned irq;
3376 +
3377 + ucb->gc.to_irq = bcm2708_gpio_to_irq;
3378 +
3379 + for (irq = GPIO_IRQ_START; irq < (GPIO_IRQ_START + GPIO_IRQS); irq++) {
3380 + irq_set_chip_data(irq, ucb);
3381 + irq_set_chip_and_handler(irq, &bcm2708_irqchip,
3382 + handle_simple_irq);
3383 + set_irq_flags(irq, IRQF_VALID);
3384 + }
3385 +
3386 + bcm2708_gpio_irq.dev_id = ucb;
3387 + setup_irq(IRQ_GPIO3, &bcm2708_gpio_irq);
3388 +}
3389 +
3390 +#else
3391 +
3392 +static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
3393 +{
3394 +}
3395 +
3396 +#endif /* #if BCM_GPIO_USE_IRQ ***************************************************************************************************************** */
3397 +
3398 +static int bcm2708_gpio_probe(struct platform_device *dev)
3399 +{
3400 + struct bcm2708_gpio *ucb;
3401 + struct resource *res;
3402 + int bank;
3403 + int err = 0;
3404 +
3405 + printk(KERN_INFO DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev);
3406 +
3407 + ucb = kzalloc(sizeof(*ucb), GFP_KERNEL);
3408 + if (NULL == ucb) {
3409 + printk(KERN_ERR DRIVER_NAME ": failed to allocate "
3410 + "mailbox memory\n");
3411 + err = -ENOMEM;
3412 + goto err;
3413 + }
3414 +
3415 + res = platform_get_resource(dev, IORESOURCE_MEM, 0);
3416 +
3417 + platform_set_drvdata(dev, ucb);
3418 + ucb->base = __io_address(GPIO_BASE);
3419 +
3420 + ucb->gc.label = "bcm2708_gpio";
3421 + ucb->gc.base = 0;
3422 + ucb->gc.ngpio = BCM2708_NR_GPIOS;
3423 + ucb->gc.owner = THIS_MODULE;
3424 +
3425 + ucb->gc.direction_input = bcm2708_gpio_dir_in;
3426 + ucb->gc.direction_output = bcm2708_gpio_dir_out;
3427 + ucb->gc.get = bcm2708_gpio_get;
3428 + ucb->gc.set = bcm2708_gpio_set;
3429 + ucb->gc.can_sleep = 0;
3430 +
3431 + for (bank = 0; bank < GPIO_BANKS; bank++) {
3432 + writel(0, ucb->base + GPIOREN(bank));
3433 + writel(0, ucb->base + GPIOFEN(bank));
3434 + writel(0, ucb->base + GPIOHEN(bank));
3435 + writel(0, ucb->base + GPIOLEN(bank));
3436 + writel(0, ucb->base + GPIOAREN(bank));
3437 + writel(0, ucb->base + GPIOAFEN(bank));
3438 + writel(~0, ucb->base + GPIOEDS(bank));
3439 + }
3440 +
3441 + bcm2708_gpio_irq_init(ucb);
3442 +
3443 + err = gpiochip_add(&ucb->gc);
3444 +
3445 +err:
3446 + return err;
3447 +
3448 +}
3449 +
3450 +static int bcm2708_gpio_remove(struct platform_device *dev)
3451 +{
3452 + int err = 0;
3453 + struct bcm2708_gpio *ucb = platform_get_drvdata(dev);
3454 +
3455 + printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_remove %p\n", dev);
3456 +
3457 + gpiochip_remove(&ucb->gc);
3458 +
3459 + platform_set_drvdata(dev, NULL);
3460 + kfree(ucb);
3461 +
3462 + return err;
3463 +}
3464 +
3465 +static struct platform_driver bcm2708_gpio_driver = {
3466 + .probe = bcm2708_gpio_probe,
3467 + .remove = bcm2708_gpio_remove,
3468 + .driver = {
3469 + .name = "bcm2708_gpio"},
3470 +};
3471 +
3472 +static int __init bcm2708_gpio_init(void)
3473 +{
3474 + return platform_driver_register(&bcm2708_gpio_driver);
3475 +}
3476 +
3477 +static void __exit bcm2708_gpio_exit(void)
3478 +{
3479 + platform_driver_unregister(&bcm2708_gpio_driver);
3480 +}
3481 +
3482 +module_init(bcm2708_gpio_init);
3483 +module_exit(bcm2708_gpio_exit);
3484 +
3485 +MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver");
3486 +MODULE_LICENSE("GPL");
3487 --- /dev/null
3488 +++ b/arch/arm/mach-bcm2709/bcm2709.c
3489 @@ -0,0 +1,801 @@
3490 +/*
3491 + * linux/arch/arm/mach-bcm2709/bcm2709.c
3492 + *
3493 + * Copyright (C) 2010 Broadcom
3494 + *
3495 + * This program is free software; you can redistribute it and/or modify
3496 + * it under the terms of the GNU General Public License as published by
3497 + * the Free Software Foundation; either version 2 of the License, or
3498 + * (at your option) any later version.
3499 + *
3500 + * This program is distributed in the hope that it will be useful,
3501 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3502 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3503 + * GNU General Public License for more details.
3504 + *
3505 + * You should have received a copy of the GNU General Public License
3506 + * along with this program; if not, write to the Free Software
3507 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3508 + */
3509 +
3510 +#include <linux/init.h>
3511 +#include <linux/device.h>
3512 +#include <linux/dma-mapping.h>
3513 +#include <linux/serial_8250.h>
3514 +#include <linux/platform_device.h>
3515 +#include <linux/syscore_ops.h>
3516 +#include <linux/interrupt.h>
3517 +#include <linux/amba/bus.h>
3518 +#include <linux/amba/clcd.h>
3519 +#include <linux/clk-provider.h>
3520 +#include <linux/clkdev.h>
3521 +#include <linux/clockchips.h>
3522 +#include <linux/cnt32_to_63.h>
3523 +#include <linux/io.h>
3524 +#include <linux/module.h>
3525 +#include <linux/of_platform.h>
3526 +#include <linux/gpio/machine.h>
3527 +
3528 +#include <linux/version.h>
3529 +#include <linux/clkdev.h>
3530 +#include <asm/system_info.h>
3531 +#include <mach/hardware.h>
3532 +#include <asm/irq.h>
3533 +#include <linux/leds.h>
3534 +#include <asm/mach-types.h>
3535 +#include <asm/cputype.h>
3536 +#include <linux/sched_clock.h>
3537 +
3538 +#include <asm/mach/arch.h>
3539 +#include <asm/mach/flash.h>
3540 +#include <asm/mach/irq.h>
3541 +#include <asm/mach/time.h>
3542 +#include <asm/mach/map.h>
3543 +
3544 +#include <mach/timex.h>
3545 +#include <mach/system.h>
3546 +
3547 +#include <linux/delay.h>
3548 +
3549 +#include "bcm2709.h"
3550 +#include "armctrl.h"
3551 +
3552 +#ifdef CONFIG_BCM_VC_CMA
3553 +#include <linux/broadcom/vc_cma.h>
3554 +#endif
3555 +
3556 +//#define SYSTEM_TIMER
3557 +
3558 +/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
3559 + * give us IO access only to 64Mbytes of physical memory (26 bits). We could
3560 + * represent this window by setting our dmamasks to 26 bits but, in fact
3561 + * we're not going to use addresses outside this range (they're not in real
3562 + * memory) so we don't bother.
3563 + *
3564 + * In the future we might include code to use this IOMMU to remap other
3565 + * physical addresses onto VideoCore memory then the use of 32-bits would be
3566 + * more legitimate.
3567 + */
3568 +#define DMA_MASK_BITS_COMMON 32
3569 +
3570 +/* command line parameters */
3571 +static unsigned boardrev, serial;
3572 +static unsigned uart_clock = UART0_CLOCK;
3573 +static unsigned disk_led_gpio = 16;
3574 +static unsigned disk_led_active_low = 1;
3575 +static unsigned reboot_part = 0;
3576 +
3577 +static unsigned use_dt = 0;
3578 +
3579 +static void __init bcm2709_init_led(void);
3580 +
3581 +void __init bcm2709_init_irq(void)
3582 +{
3583 + armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0);
3584 +}
3585 +
3586 +static struct map_desc bcm2709_io_desc[] __initdata = {
3587 + {
3588 + .virtual = IO_ADDRESS(ARMCTRL_BASE),
3589 + .pfn = __phys_to_pfn(ARMCTRL_BASE),
3590 + .length = SZ_4K,
3591 + .type = MT_DEVICE},
3592 + {
3593 + .virtual = IO_ADDRESS(UART0_BASE),
3594 + .pfn = __phys_to_pfn(UART0_BASE),
3595 + .length = SZ_4K,
3596 + .type = MT_DEVICE},
3597 + {
3598 + .virtual = IO_ADDRESS(UART1_BASE),
3599 + .pfn = __phys_to_pfn(UART1_BASE),
3600 + .length = SZ_4K,
3601 + .type = MT_DEVICE},
3602 + {
3603 + .virtual = IO_ADDRESS(DMA_BASE),
3604 + .pfn = __phys_to_pfn(DMA_BASE),
3605 + .length = SZ_4K,
3606 + .type = MT_DEVICE},
3607 + {
3608 + .virtual = IO_ADDRESS(MCORE_BASE),
3609 + .pfn = __phys_to_pfn(MCORE_BASE),
3610 + .length = SZ_4K,
3611 + .type = MT_DEVICE},
3612 + {
3613 + .virtual = IO_ADDRESS(ST_BASE),
3614 + .pfn = __phys_to_pfn(ST_BASE),
3615 + .length = SZ_4K,
3616 + .type = MT_DEVICE},
3617 + {
3618 + .virtual = IO_ADDRESS(USB_BASE),
3619 + .pfn = __phys_to_pfn(USB_BASE),
3620 + .length = SZ_128K,
3621 + .type = MT_DEVICE},
3622 + {
3623 + .virtual = IO_ADDRESS(PM_BASE),
3624 + .pfn = __phys_to_pfn(PM_BASE),
3625 + .length = SZ_4K,
3626 + .type = MT_DEVICE},
3627 + {
3628 + .virtual = IO_ADDRESS(GPIO_BASE),
3629 + .pfn = __phys_to_pfn(GPIO_BASE),
3630 + .length = SZ_4K,
3631 + .type = MT_DEVICE},
3632 + {
3633 + .virtual = IO_ADDRESS(ARM_LOCAL_BASE),
3634 + .pfn = __phys_to_pfn(ARM_LOCAL_BASE),
3635 + .length = SZ_4K,
3636 + .type = MT_DEVICE},
3637 +};
3638 +
3639 +void __init bcm2709_map_io(void)
3640 +{
3641 + iotable_init(bcm2709_io_desc, ARRAY_SIZE(bcm2709_io_desc));
3642 +}
3643 +
3644 +#ifdef SYSTEM_TIMER
3645 +
3646 +/* The STC is a free running counter that increments at the rate of 1MHz */
3647 +#define STC_FREQ_HZ 1000000
3648 +
3649 +static inline uint32_t timer_read(void)
3650 +{
3651 + /* STC: a free running counter that increments at the rate of 1MHz */
3652 + return readl(__io_address(ST_BASE + 0x04));
3653 +}
3654 +
3655 +static unsigned long bcm2709_read_current_timer(void)
3656 +{
3657 + return timer_read();
3658 +}
3659 +
3660 +static u64 notrace bcm2709_read_sched_clock(void)
3661 +{
3662 + return timer_read();
3663 +}
3664 +
3665 +static cycle_t clksrc_read(struct clocksource *cs)
3666 +{
3667 + return timer_read();
3668 +}
3669 +
3670 +static struct clocksource clocksource_stc = {
3671 + .name = "stc",
3672 + .rating = 300,
3673 + .read = clksrc_read,
3674 + .mask = CLOCKSOURCE_MASK(32),
3675 + .flags = CLOCK_SOURCE_IS_CONTINUOUS,
3676 +};
3677 +
3678 +unsigned long frc_clock_ticks32(void)
3679 +{
3680 + return timer_read();
3681 +}
3682 +
3683 +static void __init bcm2709_clocksource_init(void)
3684 +{
3685 + if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) {
3686 + printk(KERN_ERR "timer: failed to initialize clock "
3687 + "source %s\n", clocksource_stc.name);
3688 + }
3689 +}
3690 +#endif
3691 +
3692 +struct clk __init *bcm2709_clk_register(const char *name, unsigned long fixed_rate)
3693 +{
3694 + struct clk *clk;
3695 +
3696 + clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT,
3697 + fixed_rate);
3698 + if (IS_ERR(clk))
3699 + pr_err("%s not registered\n", name);
3700 +
3701 + return clk;
3702 +}
3703 +
3704 +void __init bcm2709_register_clkdev(struct clk *clk, const char *name)
3705 +{
3706 + int ret;
3707 +
3708 + ret = clk_register_clkdev(clk, NULL, name);
3709 + if (ret)
3710 + pr_err("%s alias not registered\n", name);
3711 +}
3712 +
3713 +void __init bcm2709_init_clocks(void)
3714 +{
3715 + struct clk *clk;
3716 +
3717 + clk = bcm2709_clk_register("uart0_clk", uart_clock);
3718 + bcm2709_register_clkdev(clk, "dev:f1");
3719 +
3720 + clk = bcm2709_clk_register("sdhost_clk", 250000000);
3721 + bcm2709_register_clkdev(clk, "mmc-bcm2835.0");
3722 + bcm2709_register_clkdev(clk, "bcm2708_spi.0");
3723 + bcm2709_register_clkdev(clk, "bcm2708_i2c.0");
3724 + bcm2709_register_clkdev(clk, "bcm2708_i2c.1");
3725 +}
3726 +
3727 +#define UART0_IRQ { IRQ_UART, 0 /*NO_IRQ*/ }
3728 +#define UART0_DMA { 15, 14 }
3729 +
3730 +AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
3731 +
3732 +static struct amba_device *amba_devs[] __initdata = {
3733 + &uart0_device,
3734 +};
3735 +
3736 +static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
3737 +
3738 +static struct platform_device bcm2708_fb_device = {
3739 + .name = "bcm2708_fb",
3740 + .id = -1, /* only one bcm2708_fb */
3741 + .resource = NULL,
3742 + .num_resources = 0,
3743 + .dev = {
3744 + .dma_mask = &fb_dmamask,
3745 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
3746 + },
3747 +};
3748 +
3749 +static struct resource bcm2708_usb_resources[] = {
3750 + [0] = {
3751 + .start = USB_BASE,
3752 + .end = USB_BASE + SZ_128K - 1,
3753 + .flags = IORESOURCE_MEM,
3754 + },
3755 + [1] = {
3756 + .start = MPHI_BASE,
3757 + .end = MPHI_BASE + SZ_4K - 1,
3758 + .flags = IORESOURCE_MEM,
3759 + },
3760 + [2] = {
3761 + .start = IRQ_HOSTPORT,
3762 + .end = IRQ_HOSTPORT,
3763 + .flags = IORESOURCE_IRQ,
3764 + },
3765 + [3] = {
3766 + .start = IRQ_USB,
3767 + .end = IRQ_USB,
3768 + .flags = IORESOURCE_IRQ,
3769 + },
3770 + [4] = {
3771 + .start = ARM_LOCAL_BASE,
3772 + .end = ARM_LOCAL_BASE + SZ_4K - 1,
3773 + .flags = IORESOURCE_MEM,
3774 + },
3775 + [5] = {
3776 + .start = IRQ_ARM_LOCAL_MAILBOX1,
3777 + .end = IRQ_ARM_LOCAL_MAILBOX1,
3778 + .flags = IORESOURCE_IRQ
3779 + },
3780 +};
3781 +
3782 +
3783 +static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
3784 +
3785 +static struct platform_device bcm2708_usb_device = {
3786 + .name = "bcm2708_usb",
3787 + .id = -1, /* only one bcm2708_usb */
3788 + .resource = bcm2708_usb_resources,
3789 + .num_resources = ARRAY_SIZE(bcm2708_usb_resources),
3790 + .dev = {
3791 + .dma_mask = &usb_dmamask,
3792 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
3793 + },
3794 +};
3795 +
3796 +static struct resource bcm2708_vcio_resources[] = {
3797 + {
3798 + .start = ARMCTRL_0_MAIL0_BASE,
3799 + .end = ARMCTRL_0_MAIL0_BASE + SZ_64 - 1,
3800 + .flags = IORESOURCE_MEM,
3801 + }, {
3802 + .start = IRQ_ARM_MAILBOX,
3803 + .end = IRQ_ARM_MAILBOX,
3804 + .flags = IORESOURCE_IRQ,
3805 + },
3806 +};
3807 +
3808 +static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
3809 +
3810 +static struct platform_device bcm2708_vcio_device = {
3811 + .name = "bcm2708_vcio",
3812 + .id = -1, /* only one VideoCore I/O area */
3813 + .resource = bcm2708_vcio_resources,
3814 + .num_resources = ARRAY_SIZE(bcm2708_vcio_resources),
3815 + .dev = {
3816 + .dma_mask = &vcio_dmamask,
3817 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
3818 + },
3819 +};
3820 +
3821 +int __init bcm_register_device(struct platform_device *pdev)
3822 +{
3823 + int ret;
3824 +
3825 + ret = platform_device_register(pdev);
3826 + if (ret)
3827 + pr_debug("Unable to register platform device '%s': %d\n",
3828 + pdev->name, ret);
3829 +
3830 + return ret;
3831 +}
3832 +
3833 +/*
3834 + * Use these macros for platform and i2c devices that are present in the
3835 + * Device Tree. This way the devices are only added on non-DT systems.
3836 + */
3837 +#define bcm_register_device_dt(pdev) \
3838 + if (!use_dt) bcm_register_device(pdev)
3839 +
3840 +#define i2c_register_board_info_dt(busnum, info, n) \
3841 + if (!use_dt) i2c_register_board_info(busnum, info, n)
3842 +
3843 +int calc_rsts(int partition)
3844 +{
3845 + return PM_PASSWORD |
3846 + ((partition & (1 << 0)) << 0) |
3847 + ((partition & (1 << 1)) << 1) |
3848 + ((partition & (1 << 2)) << 2) |
3849 + ((partition & (1 << 3)) << 3) |
3850 + ((partition & (1 << 4)) << 4) |
3851 + ((partition & (1 << 5)) << 5);
3852 +}
3853 +
3854 +static void bcm2709_restart(enum reboot_mode mode, const char *cmd)
3855 +{
3856 + extern char bcm2708_reboot_mode;
3857 + uint32_t pm_rstc, pm_wdog;
3858 + uint32_t timeout = 10;
3859 + uint32_t pm_rsts = 0;
3860 +
3861 + if(bcm2708_reboot_mode == 'q')
3862 + {
3863 + // NOOBS < 1.3 booting with reboot=q
3864 + pm_rsts = readl(__io_address(PM_RSTS));
3865 + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET;
3866 + }
3867 + else if(bcm2708_reboot_mode == 'p')
3868 + {
3869 + // NOOBS < 1.3 halting
3870 + pm_rsts = readl(__io_address(PM_RSTS));
3871 + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET;
3872 + }
3873 + else
3874 + {
3875 + pm_rsts = calc_rsts(reboot_part);
3876 + }
3877 +
3878 + writel(pm_rsts, __io_address(PM_RSTS));
3879 +
3880 + /* Setup watchdog for reset */
3881 + pm_rstc = readl(__io_address(PM_RSTC));
3882 +
3883 + pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
3884 + pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
3885 +
3886 + writel(pm_wdog, __io_address(PM_WDOG));
3887 + writel(pm_rstc, __io_address(PM_RSTC));
3888 +}
3889 +
3890 +/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */
3891 +static void bcm2709_power_off(void)
3892 +{
3893 + extern char bcm2708_reboot_mode;
3894 + if(bcm2708_reboot_mode == 'q')
3895 + {
3896 + // NOOBS < v1.3
3897 + bcm2709_restart('p', "");
3898 + }
3899 + else
3900 + {
3901 + /* partition 63 is special code for HALT the bootloader knows not to boot*/
3902 + reboot_part = 63;
3903 + /* continue with normal reset mechanism */
3904 + bcm2709_restart(0, "");
3905 + }
3906 +}
3907 +
3908 +static void __init bcm2709_init_uart1(void)
3909 +{
3910 + struct device_node *np;
3911 +
3912 + np = of_find_compatible_node(NULL, NULL, "brcm,bcm2835-aux-uart");
3913 + if (of_device_is_available(np)) {
3914 + pr_info("bcm2709: Mini UART enabled\n");
3915 + writel(1, __io_address(UART1_BASE + 0x4));
3916 + }
3917 +}
3918 +
3919 +#ifdef CONFIG_OF
3920 +static void __init bcm2709_dt_init(void)
3921 +{
3922 + int ret;
3923 +
3924 + of_clk_init(NULL);
3925 + ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
3926 + if (ret) {
3927 + pr_err("of_platform_populate failed: %d\n", ret);
3928 + /* Proceed as if CONFIG_OF was not defined */
3929 + } else {
3930 + use_dt = 1;
3931 + }
3932 +}
3933 +#else
3934 +static void __init bcm2709_dt_init(void) { }
3935 +#endif /* CONFIG_OF */
3936 +
3937 +void __init bcm2709_init(void)
3938 +{
3939 + int i;
3940 +
3941 +#if defined(CONFIG_BCM_VC_CMA)
3942 + vc_cma_early_init();
3943 +#endif
3944 + printk("bcm2709.uart_clock = %d\n", uart_clock);
3945 + pm_power_off = bcm2709_power_off;
3946 +
3947 + bcm2709_init_clocks();
3948 + bcm2709_dt_init();
3949 +
3950 + bcm_register_device(&bcm2708_vcio_device);
3951 +#ifdef CONFIG_BCM2708_GPIO
3952 + bcm_register_device_dt(&bcm2708_gpio_device);
3953 +#endif
3954 + bcm_register_device_dt(&bcm2708_fb_device);
3955 + bcm_register_device_dt(&bcm2708_usb_device);
3956 +
3957 + bcm2708_init_led();
3958 + bcm2708_init_uart1();
3959 +
3960 + if (!use_dt) {
3961 + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
3962 + struct amba_device *d = amba_devs[i];
3963 + amba_device_register(d, &iomem_resource);
3964 + }
3965 + }
3966 + system_rev = boardrev;
3967 + system_serial_low = serial;
3968 +}
3969 +
3970 +#ifdef SYSTEM_TIMER
3971 +static void timer_set_mode(enum clock_event_mode mode,
3972 + struct clock_event_device *clk)
3973 +{
3974 + switch (mode) {
3975 + case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */
3976 + case CLOCK_EVT_MODE_SHUTDOWN:
3977 + break;
3978 + case CLOCK_EVT_MODE_PERIODIC:
3979 +
3980 + case CLOCK_EVT_MODE_UNUSED:
3981 + case CLOCK_EVT_MODE_RESUME:
3982 +
3983 + default:
3984 + printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n",
3985 + (int)mode);
3986 + break;
3987 + }
3988 +
3989 +}
3990 +
3991 +static int timer_set_next_event(unsigned long cycles,
3992 + struct clock_event_device *unused)
3993 +{
3994 + unsigned long stc;
3995 + do {
3996 + stc = readl(__io_address(ST_BASE + 0x04));
3997 + /* We could take a FIQ here, which may push ST above STC3 */
3998 + writel(stc + cycles, __io_address(ST_BASE + 0x18));
3999 + } while ((signed long) cycles >= 0 &&
4000 + (signed long) (readl(__io_address(ST_BASE + 0x04)) - stc)
4001 + >= (signed long) cycles);
4002 + return 0;
4003 +}
4004 +
4005 +static struct clock_event_device timer0_clockevent = {
4006 + .name = "timer0",
4007 + .shift = 32,
4008 + .features = CLOCK_EVT_FEAT_ONESHOT,
4009 + .set_mode = timer_set_mode,
4010 + .set_next_event = timer_set_next_event,
4011 +};
4012 +
4013 +/*
4014 + * IRQ handler for the timer
4015 + */
4016 +static irqreturn_t bcm2709_timer_interrupt(int irq, void *dev_id)
4017 +{
4018 + struct clock_event_device *evt = &timer0_clockevent;
4019 +
4020 + writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */
4021 +
4022 + evt->event_handler(evt);
4023 +
4024 + return IRQ_HANDLED;
4025 +}
4026 +
4027 +static struct irqaction bcm2709_timer_irq = {
4028 + .name = "BCM2709 Timer Tick",
4029 + .flags = IRQF_TIMER | IRQF_IRQPOLL,
4030 + .handler = bcm2709_timer_interrupt,
4031 +};
4032 +
4033 +/*
4034 + * Set up timer interrupt, and return the current time in seconds.
4035 + */
4036 +
4037 +static struct delay_timer bcm2709_delay_timer = {
4038 + .read_current_timer = bcm2709_read_current_timer,
4039 + .freq = STC_FREQ_HZ,
4040 +};
4041 +
4042 +static void __init bcm2709_timer_init(void)
4043 +{
4044 + /* init high res timer */
4045 + bcm2709_clocksource_init();
4046 +
4047 + /*
4048 + * Make irqs happen for the system timer
4049 + */
4050 + setup_irq(IRQ_TIMER3, &bcm2709_timer_irq);
4051 +
4052 + sched_clock_register(bcm2709_read_sched_clock, 32, STC_FREQ_HZ);
4053 +
4054 + timer0_clockevent.mult =
4055 + div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift);
4056 + timer0_clockevent.max_delta_ns =
4057 + clockevent_delta2ns(0xffffffff, &timer0_clockevent);
4058 + timer0_clockevent.min_delta_ns =
4059 + clockevent_delta2ns(0xf, &timer0_clockevent);
4060 +
4061 + timer0_clockevent.cpumask = cpumask_of(0);
4062 + clockevents_register_device(&timer0_clockevent);
4063 +
4064 + register_current_timer_delay(&bcm2709_delay_timer);
4065 +}
4066 +
4067 +#else
4068 +
4069 +static void __init bcm2709_timer_init(void)
4070 +{
4071 + extern void dc4_arch_timer_init(void);
4072 + // timer control
4073 + writel(0, __io_address(ARM_LOCAL_CONTROL));
4074 + // timer pre_scaler
4075 + writel(0x80000000, __io_address(ARM_LOCAL_PRESCALER)); // 19.2MHz
4076 + //writel(0x06AAAAAB, __io_address(ARM_LOCAL_PRESCALER)); // 1MHz
4077 +
4078 + if (use_dt)
4079 + {
4080 + of_clk_init(NULL);
4081 + clocksource_of_init();
4082 + }
4083 + else
4084 + dc4_arch_timer_init();
4085 +}
4086 +
4087 +#endif
4088 +
4089 +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
4090 +#include <linux/leds.h>
4091 +
4092 +static struct gpio_led bcm2709_leds[] = {
4093 + [0] = {
4094 + .gpio = 16,
4095 + .name = "led0",
4096 + .default_trigger = "mmc0",
4097 + .active_low = 1,
4098 + },
4099 +};
4100 +
4101 +static struct gpio_led_platform_data bcm2709_led_pdata = {
4102 + .num_leds = ARRAY_SIZE(bcm2709_leds),
4103 + .leds = bcm2709_leds,
4104 +};
4105 +
4106 +static struct platform_device bcm2709_led_device = {
4107 + .name = "leds-gpio",
4108 + .id = -1,
4109 + .dev = {
4110 + .platform_data = &bcm2709_led_pdata,
4111 + },
4112 +};
4113 +
4114 +static void __init bcm2709_init_led(void)
4115 +{
4116 + bcm2709_leds[0].gpio = disk_led_gpio;
4117 + bcm2709_leds[0].active_low = disk_led_active_low;
4118 + bcm_register_device_dt(&bcm2709_led_device);
4119 +}
4120 +#else
4121 +static inline void bcm2709_init_led(void)
4122 +{
4123 +}
4124 +#endif
4125 +
4126 +void __init bcm2709_init_early(void)
4127 +{
4128 + /*
4129 + * Some devices allocate their coherent buffers from atomic
4130 + * context. Increase size of atomic coherent pool to make sure such
4131 + * the allocations won't fail.
4132 + */
4133 + init_dma_coherent_pool_size(SZ_4M);
4134 +}
4135 +
4136 +static void __init board_reserve(void)
4137 +{
4138 +#if defined(CONFIG_BCM_VC_CMA)
4139 + vc_cma_reserve();
4140 +#endif
4141 +}
4142 +
4143 +
4144 +#ifdef CONFIG_SMP
4145 +#include <linux/smp.h>
4146 +
4147 +#include <mach/hardware.h>
4148 +#include <asm/cacheflush.h>
4149 +#include <asm/smp_plat.h>
4150 +int dc4=0;
4151 +//void dc4_log(unsigned x) { if (dc4) writel((x), __io_address(ST_BASE+10 + raw_smp_processor_id()*4)); }
4152 +void dc4_log_dead(unsigned x) { if (dc4) writel((readl(__io_address(ST_BASE+0x10 + raw_smp_processor_id()*4)) & 0xffff) | ((x)<<16), __io_address(ST_BASE+0x10 + raw_smp_processor_id()*4)); }
4153 +
4154 +static void bcm2835_send_doorbell(const struct cpumask *mask, unsigned int irq)
4155 +{
4156 + int cpu;
4157 + /*
4158 + * Ensure that stores to Normal memory are visible to the
4159 + * other CPUs before issuing the IPI.
4160 + */
4161 + dsb();
4162 +
4163 + /* Convert our logical CPU mask into a physical one. */
4164 + for_each_cpu(cpu, mask)
4165 + {
4166 + /* submit softirq */
4167 + writel(1<<irq, __io_address(ARM_LOCAL_MAILBOX0_SET0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0)));
4168 + }
4169 +}
4170 +
4171 +void __init bcm2709_smp_init_cpus(void)
4172 +{
4173 + void secondary_startup(void);
4174 + unsigned int i, ncores;
4175 +
4176 + ncores = 4; // xxx scu_get_core_count(NULL);
4177 + printk("[%s] enter (%x->%x)\n", __FUNCTION__, (unsigned)virt_to_phys((void *)secondary_startup), (unsigned)__io_address(ST_BASE + 0x10));
4178 + printk("[%s] ncores=%d\n", __FUNCTION__, ncores);
4179 +
4180 + for (i = 0; i < ncores; i++) {
4181 + set_cpu_possible(i, true);
4182 + /* enable IRQ (not FIQ) */
4183 + writel(0x1, __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 0x4 * i));
4184 + //writel(0xf, __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 0x4 * i));
4185 + }
4186 + set_smp_cross_call(bcm2835_send_doorbell);
4187 +}
4188 +
4189 +/*
4190 + * for arch/arm/kernel/smp.c:smp_prepare_cpus(unsigned int max_cpus)
4191 + */
4192 +void __init bcm2709_smp_prepare_cpus(unsigned int max_cpus)
4193 +{
4194 + //void __iomem *scu_base;
4195 +
4196 + printk("[%s] enter\n", __FUNCTION__);
4197 + //scu_base = scu_base_addr();
4198 + //scu_enable(scu_base);
4199 +}
4200 +
4201 +/*
4202 + * for linux/arch/arm/kernel/smp.c:secondary_start_kernel(void)
4203 + */
4204 +void __cpuinit bcm2709_secondary_init(unsigned int cpu)
4205 +{
4206 + printk("[%s] enter cpu:%d\n", __FUNCTION__, cpu);
4207 + //gic_secondary_init(0);
4208 +}
4209 +
4210 +/*
4211 + * for linux/arch/arm/kernel/smp.c:__cpu_up(..)
4212 + */
4213 +int __cpuinit bcm2709_boot_secondary(unsigned int cpu, struct task_struct *idle)
4214 +{
4215 + void secondary_startup(void);
4216 + void *mbox_set = __io_address(ARM_LOCAL_MAILBOX3_SET0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0));
4217 + void *mbox_clr = __io_address(ARM_LOCAL_MAILBOX3_CLR0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0));
4218 + unsigned secondary_boot = (unsigned)virt_to_phys((void *)secondary_startup);
4219 + int timeout=20;
4220 + unsigned t = -1;
4221 + //printk("[%s] enter cpu:%d (%x->%p) %x\n", __FUNCTION__, cpu, secondary_boot, wake, readl(wake));
4222 +
4223 + dsb();
4224 + BUG_ON(readl(mbox_clr) != 0);
4225 + writel(secondary_boot, mbox_set);
4226 +
4227 + while (--timeout > 0) {
4228 + t = readl(mbox_clr);
4229 + if (t == 0) break;
4230 + cpu_relax();
4231 + }
4232 + if (timeout==0)
4233 + printk("[%s] cpu:%d failed to start (%x)\n", __FUNCTION__, cpu, t);
4234 + else
4235 + printk("[%s] cpu:%d started (%x) %d\n", __FUNCTION__, cpu, t, timeout);
4236 +
4237 + return 0;
4238 +}
4239 +
4240 +
4241 +struct smp_operations bcm2709_smp_ops __initdata = {
4242 + .smp_init_cpus = bcm2709_smp_init_cpus,
4243 + .smp_prepare_cpus = bcm2709_smp_prepare_cpus,
4244 + .smp_secondary_init = bcm2709_secondary_init,
4245 + .smp_boot_secondary = bcm2709_boot_secondary,
4246 +};
4247 +#endif
4248 +
4249 +static const char * const bcm2709_compat[] = {
4250 + "brcm,bcm2709",
4251 + "brcm,bcm2708", /* Could use bcm2708 in a pinch */
4252 + NULL
4253 +};
4254 +
4255 +MACHINE_START(BCM2709, "BCM2709")
4256 + /* Maintainer: Broadcom Europe Ltd. */
4257 +#ifdef CONFIG_SMP
4258 + .smp = smp_ops(bcm2709_smp_ops),
4259 +#endif
4260 + .map_io = bcm2709_map_io,
4261 + .init_irq = bcm2709_init_irq,
4262 + .init_time = bcm2709_timer_init,
4263 + .init_machine = bcm2709_init,
4264 + .init_early = bcm2709_init_early,
4265 + .reserve = board_reserve,
4266 + .restart = bcm2709_restart,
4267 + .dt_compat = bcm2709_compat,
4268 +MACHINE_END
4269 +
4270 +MACHINE_START(BCM2708, "BCM2709")
4271 + /* Maintainer: Broadcom Europe Ltd. */
4272 +#ifdef CONFIG_SMP
4273 + .smp = smp_ops(bcm2709_smp_ops),
4274 +#endif
4275 + .map_io = bcm2709_map_io,
4276 + .init_irq = bcm2709_init_irq,
4277 + .init_time = bcm2709_timer_init,
4278 + .init_machine = bcm2709_init,
4279 + .init_early = bcm2709_init_early,
4280 + .reserve = board_reserve,
4281 + .restart = bcm2709_restart,
4282 + .dt_compat = bcm2709_compat,
4283 +MACHINE_END
4284 +
4285 +module_param(boardrev, uint, 0644);
4286 +module_param(serial, uint, 0644);
4287 +module_param(uart_clock, uint, 0644);
4288 +module_param(disk_led_gpio, uint, 0644);
4289 +module_param(disk_led_active_low, uint, 0644);
4290 +module_param(reboot_part, uint, 0644);
4291 --- /dev/null
4292 +++ b/arch/arm/mach-bcm2709/bcm2709.h
4293 @@ -0,0 +1,49 @@
4294 +/*
4295 + * linux/arch/arm/mach-bcm2708/bcm2708.h
4296 + *
4297 + * BCM2708 machine support header
4298 + *
4299 + * Copyright (C) 2010 Broadcom
4300 + *
4301 + * This program is free software; you can redistribute it and/or modify
4302 + * it under the terms of the GNU General Public License as published by
4303 + * the Free Software Foundation; either version 2 of the License, or
4304 + * (at your option) any later version.
4305 + *
4306 + * This program is distributed in the hope that it will be useful,
4307 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4308 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4309 + * GNU General Public License for more details.
4310 + *
4311 + * You should have received a copy of the GNU General Public License
4312 + * along with this program; if not, write to the Free Software
4313 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4314 + */
4315 +
4316 +#ifndef __BCM2708_BCM2708_H
4317 +#define __BCM2708_BCM2708_H
4318 +
4319 +#include <linux/amba/bus.h>
4320 +
4321 +extern void __init bcm2708_init(void);
4322 +extern void __init bcm2708_init_irq(void);
4323 +extern void __init bcm2708_map_io(void);
4324 +extern struct sys_timer bcm2708_timer;
4325 +extern unsigned int mmc_status(struct device *dev);
4326 +
4327 +#define AMBA_DEVICE(name, busid, base, plat) \
4328 +static struct amba_device name##_device = { \
4329 + .dev = { \
4330 + .coherent_dma_mask = ~0, \
4331 + .init_name = busid, \
4332 + .platform_data = plat, \
4333 + }, \
4334 + .res = { \
4335 + .start = base##_BASE, \
4336 + .end = (base##_BASE) + SZ_4K - 1,\
4337 + .flags = IORESOURCE_MEM, \
4338 + }, \
4339 + .irq = base##_IRQ, \
4340 +}
4341 +
4342 +#endif
4343 --- /dev/null
4344 +++ b/arch/arm/mach-bcm2709/delay.S
4345 @@ -0,0 +1,21 @@
4346 +/*
4347 + * linux/arch/arm/lib/delay.S
4348 + *
4349 + * Copyright (C) 1995, 1996 Russell King
4350 + *
4351 + * This program is free software; you can redistribute it and/or modify
4352 + * it under the terms of the GNU General Public License version 2 as
4353 + * published by the Free Software Foundation.
4354 + */
4355 +#include <linux/linkage.h>
4356 +#include <asm/assembler.h>
4357 +#include <asm/param.h>
4358 +
4359 + .text
4360 +.align 3 @ 8 byte alignment seems to be needed to avoid fetching stalls
4361 +@ Delay routine
4362 +ENTRY(bcm2708_delay)
4363 + subs r0, r0, #1
4364 + bhi bcm2708_delay
4365 + mov pc, lr
4366 +ENDPROC(bcm2708_delay)
4367 --- /dev/null
4368 +++ b/arch/arm/mach-bcm2709/include/mach/arm_control.h
4369 @@ -0,0 +1,493 @@
4370 +/*
4371 + * linux/arch/arm/mach-bcm2708/arm_control.h
4372 + *
4373 + * Copyright (C) 2010 Broadcom
4374 + *
4375 + * This program is free software; you can redistribute it and/or modify
4376 + * it under the terms of the GNU General Public License as published by
4377 + * the Free Software Foundation; either version 2 of the License, or
4378 + * (at your option) any later version.
4379 + *
4380 + * This program is distributed in the hope that it will be useful,
4381 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4382 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4383 + * GNU General Public License for more details.
4384 + *
4385 + * You should have received a copy of the GNU General Public License
4386 + * along with this program; if not, write to the Free Software
4387 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4388 + */
4389 +
4390 +#ifndef __BCM2708_ARM_CONTROL_H
4391 +#define __BCM2708_ARM_CONTROL_H
4392 +
4393 +/*
4394 + * Definitions and addresses for the ARM CONTROL logic
4395 + * This file is manually generated.
4396 + */
4397 +
4398 +#define ARM_BASE 0x7E00B000
4399 +
4400 +/* Basic configuration */
4401 +#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000)
4402 +#define ARM_C0_SIZ128M 0x00000000
4403 +#define ARM_C0_SIZ256M 0x00000001
4404 +#define ARM_C0_SIZ512M 0x00000002
4405 +#define ARM_C0_SIZ1G 0x00000003
4406 +#define ARM_C0_BRESP0 0x00000000
4407 +#define ARM_C0_BRESP1 0x00000004
4408 +#define ARM_C0_BRESP2 0x00000008
4409 +#define ARM_C0_BOOTHI 0x00000010
4410 +#define ARM_C0_UNUSED05 0x00000020 /* free */
4411 +#define ARM_C0_FULLPERI 0x00000040
4412 +#define ARM_C0_UNUSED78 0x00000180 /* free */
4413 +#define ARM_C0_JTAGMASK 0x00000E00
4414 +#define ARM_C0_JTAGOFF 0x00000000
4415 +#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */
4416 +#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */
4417 +#define ARM_C0_APROTMSK 0x0000F000
4418 +#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */
4419 +#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */
4420 +#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */
4421 +#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */
4422 +#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */
4423 +#define ARM_C0_PRIO_L2 0x0F000000
4424 +#define ARM_C0_PRIO_UC 0xF0000000
4425 +
4426 +#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */
4427 +#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */
4428 +#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */
4429 +
4430 +
4431 +#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440)
4432 +#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */
4433 +#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */
4434 +#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */
4435 +#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */
4436 +#define ARM_C1_PERSON 0x00000100 /* peripherals on */
4437 +#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */
4438 +
4439 +#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444)
4440 +#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */
4441 +#define ARM_S_READPEND 0x000003FF /* pending reads counter */
4442 +#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */
4443 +
4444 +#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448)
4445 +#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */
4446 +#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */
4447 +#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */
4448 +#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */
4449 +#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */
4450 +#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */
4451 +
4452 +#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C)
4453 +#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C)
4454 +#define ARM_IDVAL 0x364D5241
4455 +
4456 +/* Translation memory */
4457 +#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100)
4458 +/* 32 locations: 0x100.. 0x17F */
4459 +/* 32 spare means we CAN go to 64 pages.... */
4460 +
4461 +
4462 +/* Interrupts */
4463 +#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */
4464 +#define ARM_I0_TIMER 0x00000001 /* timer IRQ */
4465 +#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */
4466 +#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */
4467 +#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */
4468 +#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */
4469 +#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */
4470 +
4471 +#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */
4472 +/* todo: all I1_interrupt sources */
4473 +#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */
4474 +/* todo: all I2_interrupt sources */
4475 +
4476 +#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */
4477 +#define ARM_IF_INDEX 0x0000007F /* FIQ select */
4478 +#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */
4479 +#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */
4480 +#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */
4481 +#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */
4482 +#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */
4483 +#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */
4484 +#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */
4485 +#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */
4486 +#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */
4487 +
4488 +#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */
4489 +#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */
4490 +#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */
4491 +#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */
4492 +#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */
4493 +#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */
4494 +#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */
4495 +#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */
4496 +#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */
4497 +#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */
4498 +#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */
4499 +#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */
4500 +#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */
4501 +
4502 +/* Timer */
4503 +/* For reg. fields see sp804 spec. */
4504 +#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400)
4505 +#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404)
4506 +#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408)
4507 +#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C)
4508 +#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410)
4509 +#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414)
4510 +#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418)
4511 +#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c)
4512 +#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420)
4513 +
4514 +#define TIMER_CTRL_ONESHOT (1 << 0)
4515 +#define TIMER_CTRL_32BIT (1 << 1)
4516 +#define TIMER_CTRL_DIV1 (0 << 2)
4517 +#define TIMER_CTRL_DIV16 (1 << 2)
4518 +#define TIMER_CTRL_DIV256 (2 << 2)
4519 +#define TIMER_CTRL_IE (1 << 5)
4520 +#define TIMER_CTRL_PERIODIC (1 << 6)
4521 +#define TIMER_CTRL_ENABLE (1 << 7)
4522 +#define TIMER_CTRL_DBGHALT (1 << 8)
4523 +#define TIMER_CTRL_ENAFREE (1 << 9)
4524 +#define TIMER_CTRL_FREEDIV_SHIFT 16)
4525 +#define TIMER_CTRL_FREEDIV_MASK 0xff
4526 +
4527 +/* Semaphores, Doorbells, Mailboxes */
4528 +#define ARM_SBM_OWN0 (ARM_BASE+0x800)
4529 +#define ARM_SBM_OWN1 (ARM_BASE+0x900)
4530 +#define ARM_SBM_OWN2 (ARM_BASE+0xA00)
4531 +#define ARM_SBM_OWN3 (ARM_BASE+0xB00)
4532 +
4533 +/* MAILBOXES
4534 + * Register flags are common across all
4535 + * owner registers. See end of this section
4536 + *
4537 + * Semaphores, Doorbells, Mailboxes Owner 0
4538 + *
4539 + */
4540 +
4541 +#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
4542 +#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
4543 +#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04)
4544 +#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08)
4545 +#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C)
4546 +#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10)
4547 +#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14)
4548 +#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18)
4549 +#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C)
4550 +#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40)
4551 +#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44)
4552 +#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48)
4553 +#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C)
4554 +/* MAILBOX 0 access in Owner 0 area */
4555 +/* Some addresses should ONLY be used by owner 0 */
4556 +#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */
4557 +#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */
4558 +#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */
4559 +#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */
4560 +#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */
4561 +#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */
4562 +/* MAILBOX 1 access in Owner 0 area */
4563 +/* Owner 0 should only WRITE to this mailbox */
4564 +#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */
4565 +/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */
4566 +/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */
4567 +/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */
4568 +#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */
4569 +/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */
4570 +/* General SEM, BELL, MAIL config/status */
4571 +#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */
4572 +#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */
4573 +#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */
4574 +#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */
4575 +
4576 +/* Semaphores, Doorbells, Mailboxes Owner 1 */
4577 +#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
4578 +#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
4579 +#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04)
4580 +#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08)
4581 +#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C)
4582 +#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10)
4583 +#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14)
4584 +#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18)
4585 +#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C)
4586 +#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40)
4587 +#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44)
4588 +#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48)
4589 +#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C)
4590 +/* MAILBOX 0 access in Owner 0 area */
4591 +/* Owner 1 should only WRITE to this mailbox */
4592 +#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */
4593 +/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */
4594 +/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */
4595 +/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */
4596 +#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */
4597 +/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */
4598 +/* MAILBOX 1 access in Owner 0 area */
4599 +#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */
4600 +#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */
4601 +#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */
4602 +#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */
4603 +#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */
4604 +#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC)
4605 +/* General SEM, BELL, MAIL config/status */
4606 +#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */
4607 +#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */
4608 +#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */
4609 +#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */
4610 +
4611 +/* Semaphores, Doorbells, Mailboxes Owner 2 */
4612 +#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
4613 +#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
4614 +#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04)
4615 +#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08)
4616 +#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C)
4617 +#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10)
4618 +#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14)
4619 +#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18)
4620 +#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C)
4621 +#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40)
4622 +#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44)
4623 +#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48)
4624 +#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C)
4625 +/* MAILBOX 0 access in Owner 2 area */
4626 +/* Owner 2 should only WRITE to this mailbox */
4627 +#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */
4628 +/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */
4629 +/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */
4630 +/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */
4631 +#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */
4632 +/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */
4633 +/* MAILBOX 1 access in Owner 2 area */
4634 +/* Owner 2 should only WRITE to this mailbox */
4635 +#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */
4636 +/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */
4637 +/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */
4638 +/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */
4639 +#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */
4640 +/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */
4641 +/* General SEM, BELL, MAIL config/status */
4642 +#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */
4643 +#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */
4644 +#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */
4645 +#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */
4646 +
4647 +/* Semaphores, Doorbells, Mailboxes Owner 3 */
4648 +#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
4649 +#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
4650 +#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04)
4651 +#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08)
4652 +#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C)
4653 +#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10)
4654 +#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14)
4655 +#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18)
4656 +#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C)
4657 +#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40)
4658 +#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44)
4659 +#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48)
4660 +#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C)
4661 +/* MAILBOX 0 access in Owner 3 area */
4662 +/* Owner 3 should only WRITE to this mailbox */
4663 +#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */
4664 +/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */
4665 +/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */
4666 +/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */
4667 +#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */
4668 +/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */
4669 +/* MAILBOX 1 access in Owner 3 area */
4670 +/* Owner 3 should only WRITE to this mailbox */
4671 +#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */
4672 +/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */
4673 +/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */
4674 +/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */
4675 +#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */
4676 +/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */
4677 +/* General SEM, BELL, MAIL config/status */
4678 +#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */
4679 +#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */
4680 +#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */
4681 +#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */
4682 +
4683 +
4684 +
4685 +/* Mailbox flags. Valid for all owners */
4686 +
4687 +/* Mailbox status register (...0x98) */
4688 +#define ARM_MS_FULL 0x80000000
4689 +#define ARM_MS_EMPTY 0x40000000
4690 +#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */
4691 +
4692 +/* MAILBOX config/status register (...0x9C) */
4693 +/* ANY write to this register clears the error bits! */
4694 +#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */
4695 +#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */
4696 +#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */
4697 +#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */
4698 +#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */
4699 +#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */
4700 +#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */
4701 +/* Bit 7 is unused */
4702 +#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */
4703 +#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */
4704 +#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */
4705 +
4706 +/* Semaphore clear/debug register (...0xE0) */
4707 +#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */
4708 +#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */
4709 +#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */
4710 +#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */
4711 +#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */
4712 +#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */
4713 +#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */
4714 +#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */
4715 +#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */
4716 +#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */
4717 +#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */
4718 +#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */
4719 +#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */
4720 +#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */
4721 +#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */
4722 +#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */
4723 +
4724 +/* Doorbells clear/debug register (...0xE4) */
4725 +#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */
4726 +#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */
4727 +#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */
4728 +#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */
4729 +#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */
4730 +#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */
4731 +#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */
4732 +#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */
4733 +
4734 +/* MY IRQS register (...0xF8) */
4735 +#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */
4736 +#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */
4737 +
4738 +/* ALL IRQS register (...0xF8) */
4739 +#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */
4740 +#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */
4741 +#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */
4742 +#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */
4743 +#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */
4744 +#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */
4745 +#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */
4746 +#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */
4747 +#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */
4748 +#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */
4749 +/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */
4750 +/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */
4751 +/* */
4752 +/* ARM JTAG BASH */
4753 +/* */
4754 +#define AJB_BASE 0x7e2000c0
4755 +
4756 +#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00)
4757 +#define AJB_BITS0 0x000000
4758 +#define AJB_BITS4 0x000004
4759 +#define AJB_BITS8 0x000008
4760 +#define AJB_BITS12 0x00000C
4761 +#define AJB_BITS16 0x000010
4762 +#define AJB_BITS20 0x000014
4763 +#define AJB_BITS24 0x000018
4764 +#define AJB_BITS28 0x00001C
4765 +#define AJB_BITS32 0x000020
4766 +#define AJB_BITS34 0x000022
4767 +#define AJB_OUT_MS 0x000040
4768 +#define AJB_OUT_LS 0x000000
4769 +#define AJB_INV_CLK 0x000080
4770 +#define AJB_D0_RISE 0x000100
4771 +#define AJB_D0_FALL 0x000000
4772 +#define AJB_D1_RISE 0x000200
4773 +#define AJB_D1_FALL 0x000000
4774 +#define AJB_IN_RISE 0x000400
4775 +#define AJB_IN_FALL 0x000000
4776 +#define AJB_ENABLE 0x000800
4777 +#define AJB_HOLD0 0x000000
4778 +#define AJB_HOLD1 0x001000
4779 +#define AJB_HOLD2 0x002000
4780 +#define AJB_HOLD3 0x003000
4781 +#define AJB_RESETN 0x004000
4782 +#define AJB_CLKSHFT 16
4783 +#define AJB_BUSY 0x80000000
4784 +#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04)
4785 +#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08)
4786 +#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c)
4787 +
4788 +#define ARM_LOCAL_BASE 0x40000000
4789 +#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000)
4790 +#define ARM_LOCAL_PRESCALER HW_REGISTER_RW(ARM_LOCAL_BASE+0x008)
4791 +#define ARM_LOCAL_GPU_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x00C)
4792 +#define ARM_LOCAL_PM_ROUTING_SET HW_REGISTER_RW(ARM_LOCAL_BASE+0x010)
4793 +#define ARM_LOCAL_PM_ROUTING_CLR HW_REGISTER_RW(ARM_LOCAL_BASE+0x014)
4794 +#define ARM_LOCAL_TIMER_LS HW_REGISTER_RW(ARM_LOCAL_BASE+0x01C)
4795 +#define ARM_LOCAL_TIMER_MS HW_REGISTER_RW(ARM_LOCAL_BASE+0x020)
4796 +#define ARM_LOCAL_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x024)
4797 +#define ARM_LOCAL_AXI_COUNT HW_REGISTER_RW(ARM_LOCAL_BASE+0x02C)
4798 +#define ARM_LOCAL_AXI_IRQ HW_REGISTER_RW(ARM_LOCAL_BASE+0x030)
4799 +#define ARM_LOCAL_TIMER_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x034)
4800 +#define ARM_LOCAL_TIMER_WRITE HW_REGISTER_RW(ARM_LOCAL_BASE+0x038)
4801 +
4802 +#define ARM_LOCAL_TIMER_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x040)
4803 +#define ARM_LOCAL_TIMER_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x044)
4804 +#define ARM_LOCAL_TIMER_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x048)
4805 +#define ARM_LOCAL_TIMER_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x04C)
4806 +
4807 +#define ARM_LOCAL_MAILBOX_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x050)
4808 +#define ARM_LOCAL_MAILBOX_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x054)
4809 +#define ARM_LOCAL_MAILBOX_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x058)
4810 +#define ARM_LOCAL_MAILBOX_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x05C)
4811 +
4812 +#define ARM_LOCAL_IRQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x060)
4813 +#define ARM_LOCAL_IRQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x064)
4814 +#define ARM_LOCAL_IRQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x068)
4815 +#define ARM_LOCAL_IRQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x06C)
4816 +
4817 +#define ARM_LOCAL_FIQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x070)
4818 +#define ARM_LOCAL_FIQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x074)
4819 +#define ARM_LOCAL_FIQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x078)
4820 +#define ARM_LOCAL_FIQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x07C)
4821 +
4822 +#define ARM_LOCAL_MAILBOX0_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x080)
4823 +#define ARM_LOCAL_MAILBOX1_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x084)
4824 +#define ARM_LOCAL_MAILBOX2_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x088)
4825 +#define ARM_LOCAL_MAILBOX3_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x08C)
4826 +
4827 +#define ARM_LOCAL_MAILBOX0_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x090)
4828 +#define ARM_LOCAL_MAILBOX1_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x094)
4829 +#define ARM_LOCAL_MAILBOX2_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x098)
4830 +#define ARM_LOCAL_MAILBOX3_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x09C)
4831 +
4832 +#define ARM_LOCAL_MAILBOX0_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A0)
4833 +#define ARM_LOCAL_MAILBOX1_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A4)
4834 +#define ARM_LOCAL_MAILBOX2_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A8)
4835 +#define ARM_LOCAL_MAILBOX3_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0AC)
4836 +
4837 +#define ARM_LOCAL_MAILBOX0_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B0)
4838 +#define ARM_LOCAL_MAILBOX1_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B4)
4839 +#define ARM_LOCAL_MAILBOX2_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B8)
4840 +#define ARM_LOCAL_MAILBOX3_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0BC)
4841 +
4842 +#define ARM_LOCAL_MAILBOX0_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C0)
4843 +#define ARM_LOCAL_MAILBOX1_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C4)
4844 +#define ARM_LOCAL_MAILBOX2_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C8)
4845 +#define ARM_LOCAL_MAILBOX3_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0CC)
4846 +
4847 +#define ARM_LOCAL_MAILBOX0_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D0)
4848 +#define ARM_LOCAL_MAILBOX1_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D4)
4849 +#define ARM_LOCAL_MAILBOX2_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D8)
4850 +#define ARM_LOCAL_MAILBOX3_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0DC)
4851 +
4852 +#define ARM_LOCAL_MAILBOX0_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E0)
4853 +#define ARM_LOCAL_MAILBOX1_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E4)
4854 +#define ARM_LOCAL_MAILBOX2_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E8)
4855 +#define ARM_LOCAL_MAILBOX3_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0EC)
4856 +
4857 +#define ARM_LOCAL_MAILBOX0_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F0)
4858 +#define ARM_LOCAL_MAILBOX1_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F4)
4859 +#define ARM_LOCAL_MAILBOX2_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F8)
4860 +#define ARM_LOCAL_MAILBOX3_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0FC)
4861 +
4862 +#endif
4863 --- /dev/null
4864 +++ b/arch/arm/mach-bcm2709/include/mach/barriers.h
4865 @@ -0,0 +1,3 @@
4866 +#define mb() dsb()
4867 +#define rmb() dsb()
4868 +#define wmb() mb()
4869 --- /dev/null
4870 +++ b/arch/arm/mach-bcm2709/include/mach/clkdev.h
4871 @@ -0,0 +1,7 @@
4872 +#ifndef __ASM_MACH_CLKDEV_H
4873 +#define __ASM_MACH_CLKDEV_H
4874 +
4875 +#define __clk_get(clk) ({ 1; })
4876 +#define __clk_put(clk) do { } while (0)
4877 +
4878 +#endif
4879 --- /dev/null
4880 +++ b/arch/arm/mach-bcm2709/include/mach/debug-macro.S
4881 @@ -0,0 +1,22 @@
4882 +/* arch/arm/mach-bcm2708/include/mach/debug-macro.S
4883 + *
4884 + * Debugging macro include header
4885 + *
4886 + * Copyright (C) 2010 Broadcom
4887 + * Copyright (C) 1994-1999 Russell King
4888 + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
4889 + *
4890 + * This program is free software; you can redistribute it and/or modify
4891 + * it under the terms of the GNU General Public License version 2 as
4892 + * published by the Free Software Foundation.
4893 + *
4894 +*/
4895 +
4896 +#include <mach/platform.h>
4897 +
4898 + .macro addruart, rp, rv, tmp
4899 + ldr \rp, =UART0_BASE
4900 + ldr \rv, =IO_ADDRESS(UART0_BASE)
4901 + .endm
4902 +
4903 +#include <debug/pl01x.S>
4904 --- /dev/null
4905 +++ b/arch/arm/mach-bcm2709/include/mach/entry-macro.S
4906 @@ -0,0 +1,123 @@
4907 +/*
4908 + * arch/arm/mach-bcm2708/include/mach/entry-macro.S
4909 + *
4910 + * Low-level IRQ helper macros for BCM2708 platforms
4911 + *
4912 + * Copyright (C) 2010 Broadcom
4913 + *
4914 + * This program is free software; you can redistribute it and/or modify
4915 + * it under the terms of the GNU General Public License as published by
4916 + * the Free Software Foundation; either version 2 of the License, or
4917 + * (at your option) any later version.
4918 + *
4919 + * This program is distributed in the hope that it will be useful,
4920 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4921 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4922 + * GNU General Public License for more details.
4923 + *
4924 + * You should have received a copy of the GNU General Public License
4925 + * along with this program; if not, write to the Free Software
4926 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4927 + */
4928 +#include <mach/hardware.h>
4929 +#include <mach/irqs.h>
4930 +
4931 + .macro disable_fiq
4932 + .endm
4933 +
4934 + .macro get_irqnr_preamble, base, tmp
4935 + ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
4936 + .endm
4937 +
4938 + .macro arch_ret_to_user, tmp1, tmp2
4939 + .endm
4940 +
4941 + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
4942 + /* get core number */
4943 + mrc p15, 0, \tmp, c0, c0, 5
4944 + ubfx \tmp, \tmp, #0, #2
4945 +
4946 + /* get core's local interrupt controller */
4947 + ldr \irqstat, = __io_address(ARM_LOCAL_IRQ_PENDING0) @ local interrupt source
4948 + add \irqstat, \irqstat, \tmp, lsl #2
4949 + ldr \tmp, [\irqstat]
4950 + /* ignore gpu interrupt */
4951 + bic \tmp, #0x100
4952 + /* ignore mailbox interrupts */
4953 + bics \tmp, #0xf0
4954 + beq 1005f
4955 +
4956 + @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
4957 + @ N.B. CLZ is an ARM5 instruction.
4958 + mov \irqnr, #(ARM_IRQ_LOCAL_BASE + 31)
4959 + sub \irqstat, \tmp, #1
4960 + eor \irqstat, \irqstat, \tmp
4961 + clz \tmp, \irqstat
4962 + sub \irqnr, \tmp
4963 + b 1020f
4964 +1005:
4965 + /* get core number */
4966 + mrc p15, 0, \tmp, c0, c0, 5
4967 + ubfx \tmp, \tmp, #0, #2
4968 +
4969 + cmp \tmp, #1
4970 + beq 1020f
4971 + cmp \tmp, #2
4972 + beq 1020f
4973 + cmp \tmp, #3
4974 + beq 1020f
4975 +
4976 + /* get masked status */
4977 + ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
4978 + mov \irqnr, #(ARM_IRQ0_BASE + 31)
4979 + and \tmp, \irqstat, #0x300 @ save bits 8 and 9
4980 + /* clear bits 8 and 9, and test */
4981 + bics \irqstat, \irqstat, #0x300
4982 + bne 1010f
4983 +
4984 + tst \tmp, #0x100
4985 + ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
4986 + movne \irqnr, #(ARM_IRQ1_BASE + 31)
4987 + @ Mask out the interrupts also present in PEND0 - see SW-5809
4988 + bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
4989 + bicne \irqstat, #((1<<18) | (1<<19))
4990 + bne 1010f
4991 +
4992 + tst \tmp, #0x200
4993 + ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
4994 + movne \irqnr, #(ARM_IRQ2_BASE + 31)
4995 + @ Mask out the interrupts also present in PEND0 - see SW-5809
4996 + bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
4997 + bicne \irqstat, #((1<<30))
4998 + beq 1020f
4999 +
5000 +1010:
5001 + @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
5002 + @ N.B. CLZ is an ARM5 instruction.
5003 + sub \tmp, \irqstat, #1
5004 + eor \irqstat, \irqstat, \tmp
5005 + clz \tmp, \irqstat
5006 + sub \irqnr, \tmp
5007 +
5008 +1020: @ EQ will be set if no irqs pending
5009 +
5010 + .endm
5011 +
5012 + .macro test_for_ipi, irqnr, irqstat, base, tmp
5013 + /* get core number */
5014 + mrc p15, 0, \tmp, c0, c0, 5
5015 + ubfx \tmp, \tmp, #0, #2
5016 + /* get core's mailbox interrupt control */
5017 + ldr \irqstat, = __io_address(ARM_LOCAL_MAILBOX0_CLR0) @ mbox_clr
5018 + add \irqstat, \irqstat, \tmp, lsl #4
5019 + ldr \tmp, [\irqstat]
5020 + cmp \tmp, #0
5021 + beq 1030f
5022 + clz \tmp, \tmp
5023 + rsb \irqnr, \tmp, #31
5024 + mov \tmp, #1
5025 + lsl \tmp, \irqnr
5026 + str \tmp, [\irqstat] @ clear interrupt source
5027 + dsb
5028 +1030: @ EQ will be set if no irqs pending
5029 + .endm
5030 --- /dev/null
5031 +++ b/arch/arm/mach-bcm2709/include/mach/frc.h
5032 @@ -0,0 +1,38 @@
5033 +/*
5034 + * arch/arm/mach-bcm2708/include/mach/timex.h
5035 + *
5036 + * BCM2708 free running counter (timer)
5037 + *
5038 + * Copyright (C) 2010 Broadcom
5039 + *
5040 + * This program is free software; you can redistribute it and/or modify
5041 + * it under the terms of the GNU General Public License as published by
5042 + * the Free Software Foundation; either version 2 of the License, or
5043 + * (at your option) any later version.
5044 + *
5045 + * This program is distributed in the hope that it will be useful,
5046 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5047 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5048 + * GNU General Public License for more details.
5049 + *
5050 + * You should have received a copy of the GNU General Public License
5051 + * along with this program; if not, write to the Free Software
5052 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5053 + */
5054 +
5055 +#ifndef _MACH_FRC_H
5056 +#define _MACH_FRC_H
5057 +
5058 +#define FRC_TICK_RATE (1000000)
5059 +
5060 +/*! Free running counter incrementing at the CLOCK_TICK_RATE
5061 + (slightly faster than frc_clock_ticks63()
5062 + */
5063 +extern unsigned long frc_clock_ticks32(void);
5064 +
5065 +/*! Free running counter incrementing at the CLOCK_TICK_RATE
5066 + * Note - top bit should be ignored (see cnt32_to_63)
5067 + */
5068 +extern unsigned long long frc_clock_ticks63(void);
5069 +
5070 +#endif
5071 --- /dev/null
5072 +++ b/arch/arm/mach-bcm2709/include/mach/gpio.h
5073 @@ -0,0 +1,17 @@
5074 +/*
5075 + * arch/arm/mach-bcm2708/include/mach/gpio.h
5076 + *
5077 + * This file is licensed under the terms of the GNU General Public
5078 + * License version 2. This program is licensed "as is" without any
5079 + * warranty of any kind, whether express or implied.
5080 + */
5081 +
5082 +#ifndef __ASM_ARCH_GPIO_H
5083 +#define __ASM_ARCH_GPIO_H
5084 +
5085 +#define BCM2708_NR_GPIOS 54 // number of gpio lines
5086 +
5087 +#define gpio_to_irq(x) ((x) + GPIO_IRQ_START)
5088 +#define irq_to_gpio(x) ((x) - GPIO_IRQ_START)
5089 +
5090 +#endif
5091 --- /dev/null
5092 +++ b/arch/arm/mach-bcm2709/include/mach/hardware.h
5093 @@ -0,0 +1,28 @@
5094 +/*
5095 + * arch/arm/mach-bcm2708/include/mach/hardware.h
5096 + *
5097 + * This file contains the hardware definitions of the BCM2708 devices.
5098 + *
5099 + * Copyright (C) 2010 Broadcom
5100 + *
5101 + * This program is free software; you can redistribute it and/or modify
5102 + * it under the terms of the GNU General Public License as published by
5103 + * the Free Software Foundation; either version 2 of the License, or
5104 + * (at your option) any later version.
5105 + *
5106 + * This program is distributed in the hope that it will be useful,
5107 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5108 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5109 + * GNU General Public License for more details.
5110 + *
5111 + * You should have received a copy of the GNU General Public License
5112 + * along with this program; if not, write to the Free Software
5113 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5114 + */
5115 +#ifndef __ASM_ARCH_HARDWARE_H
5116 +#define __ASM_ARCH_HARDWARE_H
5117 +
5118 +#include <asm/sizes.h>
5119 +#include <mach/platform.h>
5120 +
5121 +#endif
5122 --- /dev/null
5123 +++ b/arch/arm/mach-bcm2709/include/mach/io.h
5124 @@ -0,0 +1,27 @@
5125 +/*
5126 + * arch/arm/mach-bcm2708/include/mach/io.h
5127 + *
5128 + * Copyright (C) 2003 ARM Limited
5129 + *
5130 + * This program is free software; you can redistribute it and/or modify
5131 + * it under the terms of the GNU General Public License as published by
5132 + * the Free Software Foundation; either version 2 of the License, or
5133 + * (at your option) any later version.
5134 + *
5135 + * This program is distributed in the hope that it will be useful,
5136 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5137 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5138 + * GNU General Public License for more details.
5139 + *
5140 + * You should have received a copy of the GNU General Public License
5141 + * along with this program; if not, write to the Free Software
5142 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5143 + */
5144 +#ifndef __ASM_ARM_ARCH_IO_H
5145 +#define __ASM_ARM_ARCH_IO_H
5146 +
5147 +#define IO_SPACE_LIMIT 0xffffffff
5148 +
5149 +#define __io(a) __typesafe_io(a)
5150 +
5151 +#endif
5152 --- /dev/null
5153 +++ b/arch/arm/mach-bcm2709/include/mach/irqs.h
5154 @@ -0,0 +1,225 @@
5155 +/*
5156 + * arch/arm/mach-bcm2708/include/mach/irqs.h
5157 + *
5158 + * Copyright (C) 2010 Broadcom
5159 + * Copyright (C) 2003 ARM Limited
5160 + * Copyright (C) 2000 Deep Blue Solutions Ltd.
5161 + *
5162 + * This program is free software; you can redistribute it and/or modify
5163 + * it under the terms of the GNU General Public License as published by
5164 + * the Free Software Foundation; either version 2 of the License, or
5165 + * (at your option) any later version.
5166 + *
5167 + * This program is distributed in the hope that it will be useful,
5168 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5169 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5170 + * GNU General Public License for more details.
5171 + *
5172 + * You should have received a copy of the GNU General Public License
5173 + * along with this program; if not, write to the Free Software
5174 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5175 + */
5176 +
5177 +#ifndef _BCM2708_IRQS_H_
5178 +#define _BCM2708_IRQS_H_
5179 +
5180 +#include <mach/platform.h>
5181 +
5182 +/*
5183 + * IRQ interrupts definitions are the same as the INT definitions
5184 + * held within platform.h
5185 + */
5186 +#define IRQ_ARMCTRL_START 0
5187 +#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0)
5188 +#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1)
5189 +#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2)
5190 +#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3)
5191 +#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0)
5192 +#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1)
5193 +#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2)
5194 +#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG)
5195 +#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP)
5196 +#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB)
5197 +#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D)
5198 +#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER)
5199 +#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0)
5200 +#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1)
5201 +#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2)
5202 +#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3)
5203 +#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0)
5204 +#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1)
5205 +#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2)
5206 +#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3)
5207 +#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4)
5208 +#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5)
5209 +#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6)
5210 +#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7)
5211 +#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8)
5212 +#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9)
5213 +#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10)
5214 +#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11)
5215 +#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12)
5216 +#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX)
5217 +#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM)
5218 +#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA)
5219 +#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT)
5220 +#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER)
5221 +#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX)
5222 +#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC)
5223 +#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0)
5224 +#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE)
5225 +#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0)
5226 +#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1)
5227 +#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0)
5228 +#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1)
5229 +#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1)
5230 +#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV)
5231 +#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1)
5232 +#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0)
5233 +#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1)
5234 +#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR)
5235 +#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI)
5236 +#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0)
5237 +#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1)
5238 +#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2)
5239 +#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3)
5240 +#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C)
5241 +#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI)
5242 +#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM)
5243 +#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO)
5244 +#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART)
5245 +#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS)
5246 +#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC)
5247 +#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG)
5248 +#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG)
5249 +#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO)
5250 +#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON)
5251 +
5252 +#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER)
5253 +#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX)
5254 +#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0)
5255 +#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1)
5256 +#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED)
5257 +#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED)
5258 +#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0)
5259 +#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1)
5260 +#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1)
5261 +#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2)
5262 +
5263 +#define IRQ_ARM_LOCAL_CNTPSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ)
5264 +#define IRQ_ARM_LOCAL_CNTPNSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ)
5265 +#define IRQ_ARM_LOCAL_CNTHPIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ)
5266 +#define IRQ_ARM_LOCAL_CNTVIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ)
5267 +#define IRQ_ARM_LOCAL_MAILBOX0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0)
5268 +#define IRQ_ARM_LOCAL_MAILBOX1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1)
5269 +#define IRQ_ARM_LOCAL_MAILBOX2 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2)
5270 +#define IRQ_ARM_LOCAL_MAILBOX3 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3)
5271 +#define IRQ_ARM_LOCAL_GPU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST)
5272 +#define IRQ_ARM_LOCAL_PMU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST)
5273 +#define IRQ_ARM_LOCAL_ZERO (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO)
5274 +#define IRQ_ARM_LOCAL_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER)
5275 +
5276 +#define FIQ_START HARD_IRQS
5277 +
5278 +/*
5279 + * FIQ interrupts definitions are the same as the INT definitions.
5280 + */
5281 +#define FIQ_TIMER0 (FIQ_START+INTERRUPT_TIMER0)
5282 +#define FIQ_TIMER1 (FIQ_START+INTERRUPT_TIMER1)
5283 +#define FIQ_TIMER2 (FIQ_START+INTERRUPT_TIMER2)
5284 +#define FIQ_TIMER3 (FIQ_START+INTERRUPT_TIMER3)
5285 +#define FIQ_CODEC0 (FIQ_START+INTERRUPT_CODEC0)
5286 +#define FIQ_CODEC1 (FIQ_START+INTERRUPT_CODEC1)
5287 +#define FIQ_CODEC2 (FIQ_START+INTERRUPT_CODEC2)
5288 +#define FIQ_JPEG (FIQ_START+INTERRUPT_JPEG)
5289 +#define FIQ_ISP (FIQ_START+INTERRUPT_ISP)
5290 +#define FIQ_USB (FIQ_START+INTERRUPT_USB)
5291 +#define FIQ_3D (FIQ_START+INTERRUPT_3D)
5292 +#define FIQ_TRANSPOSER (FIQ_START+INTERRUPT_TRANSPOSER)
5293 +#define FIQ_MULTICORESYNC0 (FIQ_START+INTERRUPT_MULTICORESYNC0)
5294 +#define FIQ_MULTICORESYNC1 (FIQ_START+INTERRUPT_MULTICORESYNC1)
5295 +#define FIQ_MULTICORESYNC2 (FIQ_START+INTERRUPT_MULTICORESYNC2)
5296 +#define FIQ_MULTICORESYNC3 (FIQ_START+INTERRUPT_MULTICORESYNC3)
5297 +#define FIQ_DMA0 (FIQ_START+INTERRUPT_DMA0)
5298 +#define FIQ_DMA1 (FIQ_START+INTERRUPT_DMA1)
5299 +#define FIQ_DMA2 (FIQ_START+INTERRUPT_DMA2)
5300 +#define FIQ_DMA3 (FIQ_START+INTERRUPT_DMA3)
5301 +#define FIQ_DMA4 (FIQ_START+INTERRUPT_DMA4)
5302 +#define FIQ_DMA5 (FIQ_START+INTERRUPT_DMA5)
5303 +#define FIQ_DMA6 (FIQ_START+INTERRUPT_DMA6)
5304 +#define FIQ_DMA7 (FIQ_START+INTERRUPT_DMA7)
5305 +#define FIQ_DMA8 (FIQ_START+INTERRUPT_DMA8)
5306 +#define FIQ_DMA9 (FIQ_START+INTERRUPT_DMA9)
5307 +#define FIQ_DMA10 (FIQ_START+INTERRUPT_DMA10)
5308 +#define FIQ_DMA11 (FIQ_START+INTERRUPT_DMA11)
5309 +#define FIQ_DMA12 (FIQ_START+INTERRUPT_DMA12)
5310 +#define FIQ_AUX (FIQ_START+INTERRUPT_AUX)
5311 +#define FIQ_ARM (FIQ_START+INTERRUPT_ARM)
5312 +#define FIQ_VPUDMA (FIQ_START+INTERRUPT_VPUDMA)
5313 +#define FIQ_HOSTPORT (FIQ_START+INTERRUPT_HOSTPORT)
5314 +#define FIQ_VIDEOSCALER (FIQ_START+INTERRUPT_VIDEOSCALER)
5315 +#define FIQ_CCP2TX (FIQ_START+INTERRUPT_CCP2TX)
5316 +#define FIQ_SDC (FIQ_START+INTERRUPT_SDC)
5317 +#define FIQ_DSI0 (FIQ_START+INTERRUPT_DSI0)
5318 +#define FIQ_AVE (FIQ_START+INTERRUPT_AVE)
5319 +#define FIQ_CAM0 (FIQ_START+INTERRUPT_CAM0)
5320 +#define FIQ_CAM1 (FIQ_START+INTERRUPT_CAM1)
5321 +#define FIQ_HDMI0 (FIQ_START+INTERRUPT_HDMI0)
5322 +#define FIQ_HDMI1 (FIQ_START+INTERRUPT_HDMI1)
5323 +#define FIQ_PIXELVALVE1 (FIQ_START+INTERRUPT_PIXELVALVE1)
5324 +#define FIQ_I2CSPISLV (FIQ_START+INTERRUPT_I2CSPISLV)
5325 +#define FIQ_DSI1 (FIQ_START+INTERRUPT_DSI1)
5326 +#define FIQ_PWA0 (FIQ_START+INTERRUPT_PWA0)
5327 +#define FIQ_PWA1 (FIQ_START+INTERRUPT_PWA1)
5328 +#define FIQ_CPR (FIQ_START+INTERRUPT_CPR)
5329 +#define FIQ_SMI (FIQ_START+INTERRUPT_SMI)
5330 +#define FIQ_GPIO0 (FIQ_START+INTERRUPT_GPIO0)
5331 +#define FIQ_GPIO1 (FIQ_START+INTERRUPT_GPIO1)
5332 +#define FIQ_GPIO2 (FIQ_START+INTERRUPT_GPIO2)
5333 +#define FIQ_GPIO3 (FIQ_START+INTERRUPT_GPIO3)
5334 +#define FIQ_I2C (FIQ_START+INTERRUPT_I2C)
5335 +#define FIQ_SPI (FIQ_START+INTERRUPT_SPI)
5336 +#define FIQ_I2SPCM (FIQ_START+INTERRUPT_I2SPCM)
5337 +#define FIQ_SDIO (FIQ_START+INTERRUPT_SDIO)
5338 +#define FIQ_UART (FIQ_START+INTERRUPT_UART)
5339 +#define FIQ_SLIMBUS (FIQ_START+INTERRUPT_SLIMBUS)
5340 +#define FIQ_VEC (FIQ_START+INTERRUPT_VEC)
5341 +#define FIQ_CPG (FIQ_START+INTERRUPT_CPG)
5342 +#define FIQ_RNG (FIQ_START+INTERRUPT_RNG)
5343 +#define FIQ_ARASANSDIO (FIQ_START+INTERRUPT_ARASANSDIO)
5344 +#define FIQ_AVSPMON (FIQ_START+INTERRUPT_AVSPMON)
5345 +
5346 +#define FIQ_ARM_TIMER (FIQ_START+INTERRUPT_ARM_TIMER)
5347 +#define FIQ_ARM_MAILBOX (FIQ_START+INTERRUPT_ARM_MAILBOX)
5348 +#define FIQ_ARM_DOORBELL_0 (FIQ_START+INTERRUPT_ARM_DOORBELL_0)
5349 +#define FIQ_ARM_DOORBELL_1 (FIQ_START+INTERRUPT_ARM_DOORBELL_1)
5350 +#define FIQ_VPU0_HALTED (FIQ_START+INTERRUPT_VPU0_HALTED)
5351 +#define FIQ_VPU1_HALTED (FIQ_START+INTERRUPT_VPU1_HALTED)
5352 +#define FIQ_ILLEGAL_TYPE0 (FIQ_START+INTERRUPT_ILLEGAL_TYPE0)
5353 +#define FIQ_ILLEGAL_TYPE1 (FIQ_START+INTERRUPT_ILLEGAL_TYPE1)
5354 +#define FIQ_PENDING1 (FIQ_START+INTERRUPT_PENDING1)
5355 +#define FIQ_PENDING2 (FIQ_START+INTERRUPT_PENDING2)
5356 +
5357 +#define FIQ_ARM_LOCAL_CNTPSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ)
5358 +#define FIQ_ARM_LOCAL_CNTPNSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ)
5359 +#define FIQ_ARM_LOCAL_CNTHPIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ)
5360 +#define FIQ_ARM_LOCAL_CNTVIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ)
5361 +#define FIQ_ARM_LOCAL_MAILBOX0 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0)
5362 +#define FIQ_ARM_LOCAL_MAILBOX1 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1)
5363 +#define FIQ_ARM_LOCAL_MAILBOX2 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2)
5364 +#define FIQ_ARM_LOCAL_MAILBOX3 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3)
5365 +#define FIQ_ARM_LOCAL_GPU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST)
5366 +#define FIQ_ARM_LOCAL_PMU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST)
5367 +#define FIQ_ARM_LOCAL_ZERO (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO)
5368 +#define FIQ_ARM_LOCAL_TIMER (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER)
5369 +
5370 +#define HARD_IRQS (128)
5371 +#define FIQ_IRQS (128)
5372 +#define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS)
5373 +#define GPIO_IRQS (32*5)
5374 +#define SPARE_ALLOC_IRQS 64
5375 +#define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS)
5376 +#define FREE_IRQS 128
5377 +#define NR_IRQS (BCM2708_ALLOC_IRQS+FREE_IRQS)
5378 +
5379 +#endif /* _BCM2708_IRQS_H_ */
5380 --- /dev/null
5381 +++ b/arch/arm/mach-bcm2709/include/mach/memory.h
5382 @@ -0,0 +1,57 @@
5383 +/*
5384 + * arch/arm/mach-bcm2708/include/mach/memory.h
5385 + *
5386 + * Copyright (C) 2010 Broadcom
5387 + *
5388 + * This program is free software; you can redistribute it and/or modify
5389 + * it under the terms of the GNU General Public License as published by
5390 + * the Free Software Foundation; either version 2 of the License, or
5391 + * (at your option) any later version.
5392 + *
5393 + * This program is distributed in the hope that it will be useful,
5394 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5395 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5396 + * GNU General Public License for more details.
5397 + *
5398 + * You should have received a copy of the GNU General Public License
5399 + * along with this program; if not, write to the Free Software
5400 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5401 + */
5402 +#ifndef __ASM_ARCH_MEMORY_H
5403 +#define __ASM_ARCH_MEMORY_H
5404 +
5405 +/* Memory overview:
5406 +
5407 + [ARMcore] <--virtual addr-->
5408 + [ARMmmu] <--physical addr-->
5409 + [GERTmap] <--bus add-->
5410 + [VCperiph]
5411 +
5412 +*/
5413 +
5414 +/*
5415 + * Physical DRAM offset.
5416 + */
5417 +#define BCM_PLAT_PHYS_OFFSET UL(0x00000000)
5418 +#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */
5419 +
5420 +#ifdef CONFIG_BCM2708_NOL2CACHE
5421 + #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */
5422 +#else
5423 + #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */
5424 +#endif
5425 +
5426 +/* We're using the memory at 64M in the VideoCore for Linux - this adjustment
5427 + * will provide the offset into this area as well as setting the bits that
5428 + * stop the L1 and L2 cache from being used
5429 + *
5430 + * WARNING: this only works because the ARM is given memory at a fixed location
5431 + * (ARMMEM_OFFSET)
5432 + */
5433 +#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET)
5434 +#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET))
5435 +#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET))
5436 +#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
5437 +#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
5438 +
5439 +#endif
5440 --- /dev/null
5441 +++ b/arch/arm/mach-bcm2709/include/mach/platform.h
5442 @@ -0,0 +1,225 @@
5443 +/*
5444 + * arch/arm/mach-bcm2708/include/mach/platform.h
5445 + *
5446 + * Copyright (C) 2010 Broadcom
5447 + *
5448 + * This program is free software; you can redistribute it and/or modify
5449 + * it under the terms of the GNU General Public License as published by
5450 + * the Free Software Foundation; either version 2 of the License, or
5451 + * (at your option) any later version.
5452 + *
5453 + * This program is distributed in the hope that it will be useful,
5454 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5455 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5456 + * GNU General Public License for more details.
5457 + *
5458 + * You should have received a copy of the GNU General Public License
5459 + * along with this program; if not, write to the Free Software
5460 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5461 + */
5462 +
5463 +#ifndef _BCM2708_PLATFORM_H
5464 +#define _BCM2708_PLATFORM_H
5465 +
5466 +
5467 +/* macros to get at IO space when running virtually */
5468 +#define IO_ADDRESS(x) (((x) & 0x00ffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
5469 +
5470 +#define __io_address(n) IOMEM(IO_ADDRESS(n))
5471 +
5472 +
5473 +/*
5474 + * SDRAM
5475 + */
5476 +#define BCM2708_SDRAM_BASE 0x00000000
5477 +
5478 +/*
5479 + * Logic expansion modules
5480 + *
5481 + */
5482 +
5483 +
5484 +/* ------------------------------------------------------------------------
5485 + * BCM2708 ARMCTRL Registers
5486 + * ------------------------------------------------------------------------
5487 + */
5488 +
5489 +#define HW_REGISTER_RW(addr) (addr)
5490 +#define HW_REGISTER_RO(addr) (addr)
5491 +
5492 +#include "arm_control.h"
5493 +#undef ARM_BASE
5494 +
5495 +/*
5496 + * Definitions and addresses for the ARM CONTROL logic
5497 + * This file is manually generated.
5498 + */
5499 +
5500 +#define BCM2708_PERI_BASE 0x3F000000
5501 +#define IC0_BASE (BCM2708_PERI_BASE + 0x2000)
5502 +#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */
5503 +#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */
5504 +#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */
5505 +#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */
5506 +#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
5507 +#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */
5508 +#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */
5509 +#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */
5510 +#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */
5511 +#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
5512 +#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */
5513 +#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */
5514 +#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */
5515 +#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
5516 +#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
5517 +#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */
5518 +#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */
5519 +#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
5520 +#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/
5521 +
5522 +#define ARMCTRL_BASE (ARM_BASE + 0x000)
5523 +#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */
5524 +#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */
5525 +#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
5526 +
5527 +
5528 +/*
5529 + * Interrupt assignments
5530 + */
5531 +
5532 +#define ARM_IRQ1_BASE 0
5533 +#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0)
5534 +#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1)
5535 +#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2)
5536 +#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3)
5537 +#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4)
5538 +#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5)
5539 +#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6)
5540 +#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7)
5541 +#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8)
5542 +#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9)
5543 +#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10)
5544 +#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11)
5545 +#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12)
5546 +#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13)
5547 +#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14)
5548 +#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15)
5549 +#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16)
5550 +#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17)
5551 +#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18)
5552 +#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19)
5553 +#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20)
5554 +#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21)
5555 +#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22)
5556 +#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23)
5557 +#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24)
5558 +#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25)
5559 +#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26)
5560 +#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27)
5561 +#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28)
5562 +#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29)
5563 +#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30)
5564 +#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31)
5565 +
5566 +#define ARM_IRQ2_BASE 32
5567 +#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0)
5568 +#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1)
5569 +#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2)
5570 +#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3)
5571 +#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4)
5572 +#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5)
5573 +#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6)
5574 +#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7)
5575 +#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8)
5576 +#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9)
5577 +#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10)
5578 +#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11)
5579 +#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12)
5580 +#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13)
5581 +#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14)
5582 +#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15)
5583 +#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16)
5584 +#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17)
5585 +#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18)
5586 +#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19)
5587 +#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20)
5588 +#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21)
5589 +#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22)
5590 +#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23)
5591 +#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24)
5592 +#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25)
5593 +#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26)
5594 +#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27)
5595 +#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28)
5596 +#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29)
5597 +#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30)
5598 +#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31)
5599 +
5600 +#define ARM_IRQ0_BASE 64
5601 +#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0)
5602 +#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1)
5603 +#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2)
5604 +#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3)
5605 +#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4)
5606 +#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5)
5607 +#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6)
5608 +#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7)
5609 +#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8)
5610 +#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9)
5611 +#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10)
5612 +#define INTERRUPT_USB (ARM_IRQ0_BASE + 11)
5613 +#define INTERRUPT_3D (ARM_IRQ0_BASE + 12)
5614 +#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13)
5615 +#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14)
5616 +#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15)
5617 +#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16)
5618 +#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17)
5619 +#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18)
5620 +#define INTERRUPT_UART (ARM_IRQ0_BASE + 19)
5621 +#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20)
5622 +
5623 +#define ARM_IRQ_LOCAL_BASE 96
5624 +#define INTERRUPT_ARM_LOCAL_CNTPSIRQ (ARM_IRQ_LOCAL_BASE + 0)
5625 +#define INTERRUPT_ARM_LOCAL_CNTPNSIRQ (ARM_IRQ_LOCAL_BASE + 1)
5626 +#define INTERRUPT_ARM_LOCAL_CNTHPIRQ (ARM_IRQ_LOCAL_BASE + 2)
5627 +#define INTERRUPT_ARM_LOCAL_CNTVIRQ (ARM_IRQ_LOCAL_BASE + 3)
5628 +#define INTERRUPT_ARM_LOCAL_MAILBOX0 (ARM_IRQ_LOCAL_BASE + 4)
5629 +#define INTERRUPT_ARM_LOCAL_MAILBOX1 (ARM_IRQ_LOCAL_BASE + 5)
5630 +#define INTERRUPT_ARM_LOCAL_MAILBOX2 (ARM_IRQ_LOCAL_BASE + 6)
5631 +#define INTERRUPT_ARM_LOCAL_MAILBOX3 (ARM_IRQ_LOCAL_BASE + 7)
5632 +#define INTERRUPT_ARM_LOCAL_GPU_FAST (ARM_IRQ_LOCAL_BASE + 8)
5633 +#define INTERRUPT_ARM_LOCAL_PMU_FAST (ARM_IRQ_LOCAL_BASE + 9)
5634 +#define INTERRUPT_ARM_LOCAL_ZERO (ARM_IRQ_LOCAL_BASE + 10)
5635 +#define INTERRUPT_ARM_LOCAL_TIMER (ARM_IRQ_LOCAL_BASE + 11)
5636 +
5637 +/*
5638 + * Watchdog
5639 + */
5640 +#define PM_RSTC (PM_BASE+0x1c)
5641 +#define PM_RSTS (PM_BASE+0x20)
5642 +#define PM_WDOG (PM_BASE+0x24)
5643 +
5644 +#define PM_WDOG_RESET 0000000000
5645 +#define PM_PASSWORD 0x5a000000
5646 +#define PM_WDOG_TIME_SET 0x000fffff
5647 +#define PM_RSTC_WRCFG_CLR 0xffffffcf
5648 +#define PM_RSTC_WRCFG_SET 0x00000030
5649 +#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
5650 +#define PM_RSTC_RESET 0x00000102
5651 +
5652 +#define PM_RSTS_HADPOR_SET 0x00001000
5653 +#define PM_RSTS_HADSRH_SET 0x00000400
5654 +#define PM_RSTS_HADSRF_SET 0x00000200
5655 +#define PM_RSTS_HADSRQ_SET 0x00000100
5656 +#define PM_RSTS_HADWRH_SET 0x00000040
5657 +#define PM_RSTS_HADWRF_SET 0x00000020
5658 +#define PM_RSTS_HADWRQ_SET 0x00000010
5659 +#define PM_RSTS_HADDRH_SET 0x00000004
5660 +#define PM_RSTS_HADDRF_SET 0x00000002
5661 +#define PM_RSTS_HADDRQ_SET 0x00000001
5662 +
5663 +#define UART0_CLOCK 3000000
5664 +
5665 +#endif
5666 +
5667 +/* END */
5668 --- /dev/null
5669 +++ b/arch/arm/mach-bcm2709/include/mach/system.h
5670 @@ -0,0 +1,38 @@
5671 +/*
5672 + * arch/arm/mach-bcm2708/include/mach/system.h
5673 + *
5674 + * Copyright (C) 2010 Broadcom
5675 + * Copyright (C) 2003 ARM Limited
5676 + * Copyright (C) 2000 Deep Blue Solutions Ltd
5677 + *
5678 + * This program is free software; you can redistribute it and/or modify
5679 + * it under the terms of the GNU General Public License as published by
5680 + * the Free Software Foundation; either version 2 of the License, or
5681 + * (at your option) any later version.
5682 + *
5683 + * This program is distributed in the hope that it will be useful,
5684 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5685 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5686 + * GNU General Public License for more details.
5687 + *
5688 + * You should have received a copy of the GNU General Public License
5689 + * along with this program; if not, write to the Free Software
5690 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5691 + */
5692 +#ifndef __ASM_ARCH_SYSTEM_H
5693 +#define __ASM_ARCH_SYSTEM_H
5694 +
5695 +#include <linux/io.h>
5696 +#include <mach/hardware.h>
5697 +#include <mach/platform.h>
5698 +
5699 +static inline void arch_idle(void)
5700 +{
5701 + /*
5702 + * This should do all the clock switching
5703 + * and wait for interrupt tricks
5704 + */
5705 + cpu_do_idle();
5706 +}
5707 +
5708 +#endif
5709 --- /dev/null
5710 +++ b/arch/arm/mach-bcm2709/include/mach/timex.h
5711 @@ -0,0 +1,23 @@
5712 +/*
5713 + * arch/arm/mach-bcm2708/include/mach/timex.h
5714 + *
5715 + * BCM2708 sysem clock frequency
5716 + *
5717 + * Copyright (C) 2010 Broadcom
5718 + *
5719 + * This program is free software; you can redistribute it and/or modify
5720 + * it under the terms of the GNU General Public License as published by
5721 + * the Free Software Foundation; either version 2 of the License, or
5722 + * (at your option) any later version.
5723 + *
5724 + * This program is distributed in the hope that it will be useful,
5725 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5726 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5727 + * GNU General Public License for more details.
5728 + *
5729 + * You should have received a copy of the GNU General Public License
5730 + * along with this program; if not, write to the Free Software
5731 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5732 + */
5733 +
5734 +#define CLOCK_TICK_RATE (1000000)
5735 --- /dev/null
5736 +++ b/arch/arm/mach-bcm2709/include/mach/uncompress.h
5737 @@ -0,0 +1,84 @@
5738 +/*
5739 + * arch/arm/mach-bcn2708/include/mach/uncompress.h
5740 + *
5741 + * Copyright (C) 2010 Broadcom
5742 + * Copyright (C) 2003 ARM Limited
5743 + *
5744 + * This program is free software; you can redistribute it and/or modify
5745 + * it under the terms of the GNU General Public License as published by
5746 + * the Free Software Foundation; either version 2 of the License, or
5747 + * (at your option) any later version.
5748 + *
5749 + * This program is distributed in the hope that it will be useful,
5750 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5751 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5752 + * GNU General Public License for more details.
5753 + *
5754 + * You should have received a copy of the GNU General Public License
5755 + * along with this program; if not, write to the Free Software
5756 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5757 + */
5758 +
5759 +#include <linux/io.h>
5760 +#include <linux/amba/serial.h>
5761 +#include <mach/hardware.h>
5762 +
5763 +#define UART_BAUD 115200
5764 +
5765 +#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR)
5766 +#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR)
5767 +#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD)
5768 +#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD)
5769 +#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH)
5770 +#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR)
5771 +
5772 +/*
5773 + * This does not append a newline
5774 + */
5775 +static inline void putc(int c)
5776 +{
5777 + while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF)
5778 + barrier();
5779 +
5780 + __raw_writel(c, BCM2708_UART_DR);
5781 +}
5782 +
5783 +static inline void flush(void)
5784 +{
5785 + int fr;
5786 +
5787 + do {
5788 + fr = __raw_readl(BCM2708_UART_FR);
5789 + barrier();
5790 + } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
5791 +}
5792 +
5793 +static inline void arch_decomp_setup(void)
5794 +{
5795 + int temp, div, rem, frac;
5796 +
5797 + temp = 16 * UART_BAUD;
5798 + div = UART0_CLOCK / temp;
5799 + rem = UART0_CLOCK % temp;
5800 + temp = (8 * rem) / UART_BAUD;
5801 + frac = (temp >> 1) + (temp & 1);
5802 +
5803 + /* Make sure the UART is disabled before we start */
5804 + __raw_writel(0, BCM2708_UART_CR);
5805 +
5806 + /* Set the baud rate */
5807 + __raw_writel(div, BCM2708_UART_IBRD);
5808 + __raw_writel(frac, BCM2708_UART_FBRD);
5809 +
5810 + /* Set the UART to 8n1, FIFO enabled */
5811 + __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH);
5812 +
5813 + /* Enable the UART */
5814 + __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE,
5815 + BCM2708_UART_CR);
5816 +}
5817 +
5818 +/*
5819 + * nothing to do
5820 + */
5821 +#define arch_decomp_wdog()
5822 --- /dev/null
5823 +++ b/arch/arm/mach-bcm2709/include/mach/vc_mem.h
5824 @@ -0,0 +1,35 @@
5825 +/*****************************************************************************
5826 +* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
5827 +*
5828 +* Unless you and Broadcom execute a separate written software license
5829 +* agreement governing use of this software, this software is licensed to you
5830 +* under the terms of the GNU General Public License version 2, available at
5831 +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
5832 +*
5833 +* Notwithstanding the above, under no circumstances may you combine this
5834 +* software in any way with any other Broadcom software provided under a
5835 +* license other than the GPL, without Broadcom's express prior written
5836 +* consent.
5837 +*****************************************************************************/
5838 +
5839 +#if !defined( VC_MEM_H )
5840 +#define VC_MEM_H
5841 +
5842 +#include <linux/ioctl.h>
5843 +
5844 +#define VC_MEM_IOC_MAGIC 'v'
5845 +
5846 +#define VC_MEM_IOC_MEM_PHYS_ADDR _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long )
5847 +#define VC_MEM_IOC_MEM_SIZE _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int )
5848 +#define VC_MEM_IOC_MEM_BASE _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int )
5849 +#define VC_MEM_IOC_MEM_LOAD _IOR( VC_MEM_IOC_MAGIC, 3, unsigned int )
5850 +
5851 +#if defined( __KERNEL__ )
5852 +#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF
5853 +
5854 +extern unsigned long mm_vc_mem_phys_addr;
5855 +extern unsigned int mm_vc_mem_size;
5856 +extern int vc_mem_get_current_size( void );
5857 +#endif
5858 +
5859 +#endif /* VC_MEM_H */
5860 --- /dev/null
5861 +++ b/arch/arm/mach-bcm2709/include/mach/vc_support.h
5862 @@ -0,0 +1,69 @@
5863 +#ifndef _VC_SUPPORT_H_
5864 +#define _VC_SUPPORT_H_
5865 +
5866 +/*
5867 + * vc_support.h
5868 + *
5869 + * Created on: 25 Nov 2012
5870 + * Author: Simon
5871 + */
5872 +
5873 +enum {
5874 +/*
5875 + If a MEM_HANDLE_T is discardable, the memory manager may resize it to size
5876 + 0 at any time when it is not locked or retained.
5877 + */
5878 + MEM_FLAG_DISCARDABLE = 1 << 0,
5879 +
5880 + /*
5881 + If a MEM_HANDLE_T is allocating (or normal), its block of memory will be
5882 + accessed in an allocating fashion through the cache.
5883 + */
5884 + MEM_FLAG_NORMAL = 0 << 2,
5885 + MEM_FLAG_ALLOCATING = MEM_FLAG_NORMAL,
5886 +
5887 + /*
5888 + If a MEM_HANDLE_T is direct, its block of memory will be accessed
5889 + directly, bypassing the cache.
5890 + */
5891 + MEM_FLAG_DIRECT = 1 << 2,
5892 +
5893 + /*
5894 + If a MEM_HANDLE_T is coherent, its block of memory will be accessed in a
5895 + non-allocating fashion through the cache.
5896 + */
5897 + MEM_FLAG_COHERENT = 2 << 2,
5898 +
5899 + /*
5900 + If a MEM_HANDLE_T is L1-nonallocating, its block of memory will be accessed by
5901 + the VPU in a fashion which is allocating in L2, but only coherent in L1.
5902 + */
5903 + MEM_FLAG_L1_NONALLOCATING = (MEM_FLAG_DIRECT | MEM_FLAG_COHERENT),
5904 +
5905 + /*
5906 + If a MEM_HANDLE_T is zero'd, its contents are set to 0 rather than
5907 + MEM_HANDLE_INVALID on allocation and resize up.
5908 + */
5909 + MEM_FLAG_ZERO = 1 << 4,
5910 +
5911 + /*
5912 + If a MEM_HANDLE_T is uninitialised, it will not be reset to a defined value
5913 + (either zero, or all 1's) on allocation.
5914 + */
5915 + MEM_FLAG_NO_INIT = 1 << 5,
5916 +
5917 + /*
5918 + Hints.
5919 + */
5920 + MEM_FLAG_HINT_PERMALOCK = 1 << 6, /* Likely to be locked for long periods of time. */
5921 +};
5922 +
5923 +unsigned int AllocateVcMemory(unsigned int *pHandle, unsigned int size, unsigned int alignment, unsigned int flags);
5924 +unsigned int ReleaseVcMemory(unsigned int handle);
5925 +unsigned int LockVcMemory(unsigned int *pBusAddress, unsigned int handle);
5926 +unsigned int UnlockVcMemory(unsigned int handle);
5927 +
5928 +unsigned int ExecuteVcCode(unsigned int code,
5929 + unsigned int r0, unsigned int r1, unsigned int r2, unsigned int r3, unsigned int r4, unsigned int r5);
5930 +
5931 +#endif
5932 --- /dev/null
5933 +++ b/arch/arm/mach-bcm2709/include/mach/vmalloc.h
5934 @@ -0,0 +1,20 @@
5935 +/*
5936 + * arch/arm/mach-bcm2708/include/mach/vmalloc.h
5937 + *
5938 + * Copyright (C) 2010 Broadcom
5939 + *
5940 + * This program is free software; you can redistribute it and/or modify
5941 + * it under the terms of the GNU General Public License as published by
5942 + * the Free Software Foundation; either version 2 of the License, or
5943 + * (at your option) any later version.
5944 + *
5945 + * This program is distributed in the hope that it will be useful,
5946 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5947 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5948 + * GNU General Public License for more details.
5949 + *
5950 + * You should have received a copy of the GNU General Public License
5951 + * along with this program; if not, write to the Free Software
5952 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5953 + */
5954 +#define VMALLOC_END (0xff000000)
5955 --- /dev/null
5956 +++ b/arch/arm/mach-bcm2709/vc_mem.c
5957 @@ -0,0 +1,431 @@
5958 +/*****************************************************************************
5959 +* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
5960 +*
5961 +* Unless you and Broadcom execute a separate written software license
5962 +* agreement governing use of this software, this software is licensed to you
5963 +* under the terms of the GNU General Public License version 2, available at
5964 +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
5965 +*
5966 +* Notwithstanding the above, under no circumstances may you combine this
5967 +* software in any way with any other Broadcom software provided under a
5968 +* license other than the GPL, without Broadcom's express prior written
5969 +* consent.
5970 +*****************************************************************************/
5971 +
5972 +#include <linux/kernel.h>
5973 +#include <linux/module.h>
5974 +#include <linux/fs.h>
5975 +#include <linux/device.h>
5976 +#include <linux/cdev.h>
5977 +#include <linux/mm.h>
5978 +#include <linux/slab.h>
5979 +#include <linux/debugfs.h>
5980 +#include <asm/uaccess.h>
5981 +#include <linux/dma-mapping.h>
5982 +#include <linux/platform_data/mailbox-bcm2708.h>
5983 +
5984 +#ifdef CONFIG_ARCH_KONA
5985 +#include <chal/chal_ipc.h>
5986 +#elif defined(CONFIG_ARCH_BCM2708) || defined(CONFIG_ARCH_BCM2709)
5987 +#else
5988 +#include <csp/chal_ipc.h>
5989 +#endif
5990 +
5991 +#include "mach/vc_mem.h"
5992 +
5993 +#define DRIVER_NAME "vc-mem"
5994 +
5995 +// Device (/dev) related variables
5996 +static dev_t vc_mem_devnum = 0;
5997 +static struct class *vc_mem_class = NULL;
5998 +static struct cdev vc_mem_cdev;
5999 +static int vc_mem_inited = 0;
6000 +
6001 +#ifdef CONFIG_DEBUG_FS
6002 +static struct dentry *vc_mem_debugfs_entry;
6003 +#endif
6004 +
6005 +/*
6006 + * Videocore memory addresses and size
6007 + *
6008 + * Drivers that wish to know the videocore memory addresses and sizes should
6009 + * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in
6010 + * headers. This allows the other drivers to not be tied down to a a certain
6011 + * address/size at compile time.
6012 + *
6013 + * In the future, the goal is to have the videocore memory virtual address and
6014 + * size be calculated at boot time rather than at compile time. The decision of
6015 + * where the videocore memory resides and its size would be in the hands of the
6016 + * bootloader (and/or kernel). When that happens, the values of these variables
6017 + * would be calculated and assigned in the init function.
6018 + */
6019 +// in the 2835 VC in mapped above ARM, but ARM has full access to VC space
6020 +unsigned long mm_vc_mem_phys_addr = 0x00000000;
6021 +unsigned int mm_vc_mem_size = 0;
6022 +unsigned int mm_vc_mem_base = 0;
6023 +
6024 +EXPORT_SYMBOL(mm_vc_mem_phys_addr);
6025 +EXPORT_SYMBOL(mm_vc_mem_size);
6026 +EXPORT_SYMBOL(mm_vc_mem_base);
6027 +
6028 +static uint phys_addr = 0;
6029 +static uint mem_size = 0;
6030 +static uint mem_base = 0;
6031 +
6032 +
6033 +/****************************************************************************
6034 +*
6035 +* vc_mem_open
6036 +*
6037 +***************************************************************************/
6038 +
6039 +static int
6040 +vc_mem_open(struct inode *inode, struct file *file)
6041 +{
6042 + (void) inode;
6043 + (void) file;
6044 +
6045 + pr_debug("%s: called file = 0x%p\n", __func__, file);
6046 +
6047 + return 0;
6048 +}
6049 +
6050 +/****************************************************************************
6051 +*
6052 +* vc_mem_release
6053 +*
6054 +***************************************************************************/
6055 +
6056 +static int
6057 +vc_mem_release(struct inode *inode, struct file *file)
6058 +{
6059 + (void) inode;
6060 + (void) file;
6061 +
6062 + pr_debug("%s: called file = 0x%p\n", __func__, file);
6063 +
6064 + return 0;
6065 +}
6066 +
6067 +/****************************************************************************
6068 +*
6069 +* vc_mem_get_size
6070 +*
6071 +***************************************************************************/
6072 +
6073 +static void
6074 +vc_mem_get_size(void)
6075 +{
6076 +}
6077 +
6078 +/****************************************************************************
6079 +*
6080 +* vc_mem_get_base
6081 +*
6082 +***************************************************************************/
6083 +
6084 +static void
6085 +vc_mem_get_base(void)
6086 +{
6087 +}
6088 +
6089 +/****************************************************************************
6090 +*
6091 +* vc_mem_get_current_size
6092 +*
6093 +***************************************************************************/
6094 +
6095 +int
6096 +vc_mem_get_current_size(void)
6097 +{
6098 + return mm_vc_mem_size;
6099 +}
6100 +
6101 +EXPORT_SYMBOL_GPL(vc_mem_get_current_size);
6102 +
6103 +/****************************************************************************
6104 +*
6105 +* vc_mem_ioctl
6106 +*
6107 +***************************************************************************/
6108 +
6109 +static long
6110 +vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
6111 +{
6112 + int rc = 0;
6113 +
6114 + (void) cmd;
6115 + (void) arg;
6116 +
6117 + pr_debug("%s: called file = 0x%p\n", __func__, file);
6118 +
6119 + switch (cmd) {
6120 + case VC_MEM_IOC_MEM_PHYS_ADDR:
6121 + {
6122 + pr_debug("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p\n",
6123 + __func__, (void *) mm_vc_mem_phys_addr);
6124 +
6125 + if (copy_to_user((void *) arg, &mm_vc_mem_phys_addr,
6126 + sizeof (mm_vc_mem_phys_addr)) != 0) {
6127 + rc = -EFAULT;
6128 + }
6129 + break;
6130 + }
6131 + case VC_MEM_IOC_MEM_SIZE:
6132 + {
6133 + // Get the videocore memory size first
6134 + vc_mem_get_size();
6135 +
6136 + pr_debug("%s: VC_MEM_IOC_MEM_SIZE=%u\n", __func__,
6137 + mm_vc_mem_size);
6138 +
6139 + if (copy_to_user((void *) arg, &mm_vc_mem_size,
6140 + sizeof (mm_vc_mem_size)) != 0) {
6141 + rc = -EFAULT;
6142 + }
6143 + break;
6144 + }
6145 + case VC_MEM_IOC_MEM_BASE:
6146 + {
6147 + // Get the videocore memory base
6148 + vc_mem_get_base();
6149 +
6150 + pr_debug("%s: VC_MEM_IOC_MEM_BASE=%u\n", __func__,
6151 + mm_vc_mem_base);
6152 +
6153 + if (copy_to_user((void *) arg, &mm_vc_mem_base,
6154 + sizeof (mm_vc_mem_base)) != 0) {
6155 + rc = -EFAULT;
6156 + }
6157 + break;
6158 + }
6159 + case VC_MEM_IOC_MEM_LOAD:
6160 + {
6161 + // Get the videocore memory base
6162 + vc_mem_get_base();
6163 +
6164 + pr_debug("%s: VC_MEM_IOC_MEM_LOAD=%u\n", __func__,
6165 + mm_vc_mem_base);
6166 +
6167 + if (copy_to_user((void *) arg, &mm_vc_mem_base,
6168 + sizeof (mm_vc_mem_base)) != 0) {
6169 + rc = -EFAULT;
6170 + }
6171 + break;
6172 + }
6173 + default:
6174 + {
6175 + return -ENOTTY;
6176 + }
6177 + }
6178 + pr_debug("%s: file = 0x%p returning %d\n", __func__, file, rc);
6179 +
6180 + return rc;
6181 +}
6182 +
6183 +/****************************************************************************
6184 +*
6185 +* vc_mem_mmap
6186 +*
6187 +***************************************************************************/
6188 +
6189 +static int
6190 +vc_mem_mmap(struct file *filp, struct vm_area_struct *vma)
6191 +{
6192 + int rc = 0;
6193 + unsigned long length = vma->vm_end - vma->vm_start;
6194 + unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
6195 +
6196 + pr_debug("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx\n",
6197 + __func__, (long) vma->vm_start, (long) vma->vm_end,
6198 + (long) vma->vm_pgoff);
6199 +
6200 + if (offset + length > mm_vc_mem_size) {
6201 + pr_err("%s: length %ld is too big\n", __func__, length);
6202 + return -EINVAL;
6203 + }
6204 + // Do not cache the memory map
6205 + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
6206 +
6207 + rc = remap_pfn_range(vma, vma->vm_start,
6208 + (mm_vc_mem_phys_addr >> PAGE_SHIFT) +
6209 + vma->vm_pgoff, length, vma->vm_page_prot);
6210 + if (rc != 0) {
6211 + pr_err("%s: remap_pfn_range failed (rc=%d)\n", __func__, rc);
6212 + }
6213 +
6214 + return rc;
6215 +}
6216 +
6217 +/****************************************************************************
6218 +*
6219 +* File Operations for the driver.
6220 +*
6221 +***************************************************************************/
6222 +
6223 +static const struct file_operations vc_mem_fops = {
6224 + .owner = THIS_MODULE,
6225 + .open = vc_mem_open,
6226 + .release = vc_mem_release,
6227 + .unlocked_ioctl = vc_mem_ioctl,
6228 + .mmap = vc_mem_mmap,
6229 +};
6230 +
6231 +#ifdef CONFIG_DEBUG_FS
6232 +static void vc_mem_debugfs_deinit(void)
6233 +{
6234 + debugfs_remove_recursive(vc_mem_debugfs_entry);
6235 + vc_mem_debugfs_entry = NULL;
6236 +}
6237 +
6238 +
6239 +static int vc_mem_debugfs_init(
6240 + struct device *dev)
6241 +{
6242 + vc_mem_debugfs_entry = debugfs_create_dir(DRIVER_NAME, NULL);
6243 + if (!vc_mem_debugfs_entry) {
6244 + dev_warn(dev, "could not create debugfs entry\n");
6245 + return -EFAULT;
6246 + }
6247 +
6248 + if (!debugfs_create_x32("vc_mem_phys_addr",
6249 + 0444,
6250 + vc_mem_debugfs_entry,
6251 + (u32 *)&mm_vc_mem_phys_addr)) {
6252 + dev_warn(dev, "%s:could not create vc_mem_phys entry\n",
6253 + __func__);
6254 + goto fail;
6255 + }
6256 +
6257 + if (!debugfs_create_x32("vc_mem_size",
6258 + 0444,
6259 + vc_mem_debugfs_entry,
6260 + (u32 *)&mm_vc_mem_size)) {
6261 + dev_warn(dev, "%s:could not create vc_mem_size entry\n",
6262 + __func__);
6263 + goto fail;
6264 + }
6265 +
6266 + if (!debugfs_create_x32("vc_mem_base",
6267 + 0444,
6268 + vc_mem_debugfs_entry,
6269 + (u32 *)&mm_vc_mem_base)) {
6270 + dev_warn(dev, "%s:could not create vc_mem_base entry\n",
6271 + __func__);
6272 + goto fail;
6273 + }
6274 +
6275 + return 0;
6276 +
6277 +fail:
6278 + vc_mem_debugfs_deinit();
6279 + return -EFAULT;
6280 +}
6281 +
6282 +#endif /* CONFIG_DEBUG_FS */
6283 +
6284 +
6285 +/****************************************************************************
6286 +*
6287 +* vc_mem_init
6288 +*
6289 +***************************************************************************/
6290 +
6291 +static int __init
6292 +vc_mem_init(void)
6293 +{
6294 + int rc = -EFAULT;
6295 + struct device *dev;
6296 +
6297 + pr_debug("%s: called\n", __func__);
6298 +
6299 + mm_vc_mem_phys_addr = phys_addr;
6300 + mm_vc_mem_size = mem_size;
6301 + mm_vc_mem_base = mem_base;
6302 +
6303 + vc_mem_get_size();
6304 +
6305 + pr_info("vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\n",
6306 + mm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024));
6307 +
6308 + if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) {
6309 + pr_err("%s: alloc_chrdev_region failed (rc=%d)\n",
6310 + __func__, rc);
6311 + goto out_err;
6312 + }
6313 +
6314 + cdev_init(&vc_mem_cdev, &vc_mem_fops);
6315 + if ((rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1)) != 0) {
6316 + pr_err("%s: cdev_add failed (rc=%d)\n", __func__, rc);
6317 + goto out_unregister;
6318 + }
6319 +
6320 + vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME);
6321 + if (IS_ERR(vc_mem_class)) {
6322 + rc = PTR_ERR(vc_mem_class);
6323 + pr_err("%s: class_create failed (rc=%d)\n", __func__, rc);
6324 + goto out_cdev_del;
6325 + }
6326 +
6327 + dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL,
6328 + DRIVER_NAME);
6329 + if (IS_ERR(dev)) {
6330 + rc = PTR_ERR(dev);
6331 + pr_err("%s: device_create failed (rc=%d)\n", __func__, rc);
6332 + goto out_class_destroy;
6333 + }
6334 +
6335 +#ifdef CONFIG_DEBUG_FS
6336 + /* don't fail if the debug entries cannot be created */
6337 + vc_mem_debugfs_init(dev);
6338 +#endif
6339 +
6340 + vc_mem_inited = 1;
6341 + return 0;
6342 +
6343 + device_destroy(vc_mem_class, vc_mem_devnum);
6344 +
6345 + out_class_destroy:
6346 + class_destroy(vc_mem_class);
6347 + vc_mem_class = NULL;
6348 +
6349 + out_cdev_del:
6350 + cdev_del(&vc_mem_cdev);
6351 +
6352 + out_unregister:
6353 + unregister_chrdev_region(vc_mem_devnum, 1);
6354 +
6355 + out_err:
6356 + return -1;
6357 +}
6358 +
6359 +/****************************************************************************
6360 +*
6361 +* vc_mem_exit
6362 +*
6363 +***************************************************************************/
6364 +
6365 +static void __exit
6366 +vc_mem_exit(void)
6367 +{
6368 + pr_debug("%s: called\n", __func__);
6369 +
6370 + if (vc_mem_inited) {
6371 +#if CONFIG_DEBUG_FS
6372 + vc_mem_debugfs_deinit();
6373 +#endif
6374 + device_destroy(vc_mem_class, vc_mem_devnum);
6375 + class_destroy(vc_mem_class);
6376 + cdev_del(&vc_mem_cdev);
6377 + unregister_chrdev_region(vc_mem_devnum, 1);
6378 + }
6379 +}
6380 +
6381 +module_init(vc_mem_init);
6382 +module_exit(vc_mem_exit);
6383 +MODULE_LICENSE("GPL");
6384 +MODULE_AUTHOR("Broadcom Corporation");
6385 +
6386 +module_param(phys_addr, uint, 0644);
6387 +module_param(mem_size, uint, 0644);
6388 +module_param(mem_base, uint, 0644);
6389 --- /dev/null
6390 +++ b/arch/arm/mach-bcm2709/vc_support.c
6391 @@ -0,0 +1,318 @@
6392 +/*
6393 + * vc_support.c
6394 + *
6395 + * Created on: 25 Nov 2012
6396 + * Author: Simon
6397 + */
6398 +
6399 +#include <linux/module.h>
6400 +#include <linux/platform_data/mailbox-bcm2708.h>
6401 +
6402 +#ifdef ECLIPSE_IGNORE
6403 +
6404 +#define __user
6405 +#define __init
6406 +#define __exit
6407 +#define __iomem
6408 +#define KERN_DEBUG
6409 +#define KERN_ERR
6410 +#define KERN_WARNING
6411 +#define KERN_INFO
6412 +#define _IOWR(a, b, c) b
6413 +#define _IOW(a, b, c) b
6414 +#define _IO(a, b) b
6415 +
6416 +#endif
6417 +
6418 +/****** VC MAILBOX FUNCTIONALITY ******/
6419 +unsigned int AllocateVcMemory(unsigned int *pHandle, unsigned int size, unsigned int alignment, unsigned int flags)
6420 +{
6421 + struct vc_msg
6422 + {
6423 + unsigned int m_msgSize;
6424 + unsigned int m_response;
6425 +
6426 + struct vc_tag
6427 + {
6428 + unsigned int m_tagId;
6429 + unsigned int m_sendBufferSize;
6430 + union {
6431 + unsigned int m_sendDataSize;
6432 + unsigned int m_recvDataSize;
6433 + };
6434 +
6435 + struct args
6436 + {
6437 + union {
6438 + unsigned int m_size;
6439 + unsigned int m_handle;
6440 + };
6441 + unsigned int m_alignment;
6442 + unsigned int m_flags;
6443 + } m_args;
6444 + } m_tag;
6445 +
6446 + unsigned int m_endTag;
6447 + } msg;
6448 + int s;
6449 +
6450 + msg.m_msgSize = sizeof(msg);
6451 + msg.m_response = 0;
6452 + msg.m_endTag = 0;
6453 +
6454 + //fill in the tag for the allocation command
6455 + msg.m_tag.m_tagId = 0x3000c;
6456 + msg.m_tag.m_sendBufferSize = 12;
6457 + msg.m_tag.m_sendDataSize = 12;
6458 +
6459 + //fill in our args
6460 + msg.m_tag.m_args.m_size = size;
6461 + msg.m_tag.m_args.m_alignment = alignment;
6462 + msg.m_tag.m_args.m_flags = flags;
6463 +
6464 + //run the command
6465 + s = bcm_mailbox_property(&msg, sizeof(msg));
6466 +
6467 + if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004)
6468 + {
6469 + *pHandle = msg.m_tag.m_args.m_handle;
6470 + return 0;
6471 + }
6472 + else
6473 + {
6474 + printk(KERN_ERR "failed to allocate vc memory: s=%d response=%08x recv data size=%08x\n",
6475 + s, msg.m_response, msg.m_tag.m_recvDataSize);
6476 + return 1;
6477 + }
6478 +}
6479 +
6480 +unsigned int ReleaseVcMemory(unsigned int handle)
6481 +{
6482 + struct vc_msg
6483 + {
6484 + unsigned int m_msgSize;
6485 + unsigned int m_response;
6486 +
6487 + struct vc_tag
6488 + {
6489 + unsigned int m_tagId;
6490 + unsigned int m_sendBufferSize;
6491 + union {
6492 + unsigned int m_sendDataSize;
6493 + unsigned int m_recvDataSize;
6494 + };
6495 +
6496 + struct args
6497 + {
6498 + union {
6499 + unsigned int m_handle;
6500 + unsigned int m_error;
6501 + };
6502 + } m_args;
6503 + } m_tag;
6504 +
6505 + unsigned int m_endTag;
6506 + } msg;
6507 + int s;
6508 +
6509 + msg.m_msgSize = sizeof(msg);
6510 + msg.m_response = 0;
6511 + msg.m_endTag = 0;
6512 +
6513 + //fill in the tag for the release command
6514 + msg.m_tag.m_tagId = 0x3000f;
6515 + msg.m_tag.m_sendBufferSize = 4;
6516 + msg.m_tag.m_sendDataSize = 4;
6517 +
6518 + //pass across the handle
6519 + msg.m_tag.m_args.m_handle = handle;
6520 +
6521 + s = bcm_mailbox_property(&msg, sizeof(msg));
6522 +
6523 + if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004 && msg.m_tag.m_args.m_error == 0)
6524 + return 0;
6525 + else
6526 + {
6527 + printk(KERN_ERR "failed to release vc memory: s=%d response=%08x recv data size=%08x error=%08x\n",
6528 + s, msg.m_response, msg.m_tag.m_recvDataSize, msg.m_tag.m_args.m_error);
6529 + return 1;
6530 + }
6531 +}
6532 +
6533 +unsigned int LockVcMemory(unsigned int *pBusAddress, unsigned int handle)
6534 +{
6535 + struct vc_msg
6536 + {
6537 + unsigned int m_msgSize;
6538 + unsigned int m_response;
6539 +
6540 + struct vc_tag
6541 + {
6542 + unsigned int m_tagId;
6543 + unsigned int m_sendBufferSize;
6544 + union {
6545 + unsigned int m_sendDataSize;
6546 + unsigned int m_recvDataSize;
6547 + };
6548 +
6549 + struct args
6550 + {
6551 + union {
6552 + unsigned int m_handle;
6553 + unsigned int m_busAddress;
6554 + };
6555 + } m_args;
6556 + } m_tag;
6557 +
6558 + unsigned int m_endTag;
6559 + } msg;
6560 + int s;
6561 +
6562 + msg.m_msgSize = sizeof(msg);
6563 + msg.m_response = 0;
6564 + msg.m_endTag = 0;
6565 +
6566 + //fill in the tag for the lock command
6567 + msg.m_tag.m_tagId = 0x3000d;
6568 + msg.m_tag.m_sendBufferSize = 4;
6569 + msg.m_tag.m_sendDataSize = 4;
6570 +
6571 + //pass across the handle
6572 + msg.m_tag.m_args.m_handle = handle;
6573 +
6574 + s = bcm_mailbox_property(&msg, sizeof(msg));
6575 +
6576 + if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004)
6577 + {
6578 + //pick out the bus address
6579 + *pBusAddress = msg.m_tag.m_args.m_busAddress;
6580 + return 0;
6581 + }
6582 + else
6583 + {
6584 + printk(KERN_ERR "failed to lock vc memory: s=%d response=%08x recv data size=%08x\n",
6585 + s, msg.m_response, msg.m_tag.m_recvDataSize);
6586 + return 1;
6587 + }
6588 +}
6589 +
6590 +unsigned int UnlockVcMemory(unsigned int handle)
6591 +{
6592 + struct vc_msg
6593 + {
6594 + unsigned int m_msgSize;
6595 + unsigned int m_response;
6596 +
6597 + struct vc_tag
6598 + {
6599 + unsigned int m_tagId;
6600 + unsigned int m_sendBufferSize;
6601 + union {
6602 + unsigned int m_sendDataSize;
6603 + unsigned int m_recvDataSize;
6604 + };
6605 +
6606 + struct args
6607 + {
6608 + union {
6609 + unsigned int m_handle;
6610 + unsigned int m_error;
6611 + };
6612 + } m_args;
6613 + } m_tag;
6614 +
6615 + unsigned int m_endTag;
6616 + } msg;
6617 + int s;
6618 +
6619 + msg.m_msgSize = sizeof(msg);
6620 + msg.m_response = 0;
6621 + msg.m_endTag = 0;
6622 +
6623 + //fill in the tag for the unlock command
6624 + msg.m_tag.m_tagId = 0x3000e;
6625 + msg.m_tag.m_sendBufferSize = 4;
6626 + msg.m_tag.m_sendDataSize = 4;
6627 +
6628 + //pass across the handle
6629 + msg.m_tag.m_args.m_handle = handle;
6630 +
6631 + s = bcm_mailbox_property(&msg, sizeof(msg));
6632 +
6633 + //check the error code too
6634 + if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004 && msg.m_tag.m_args.m_error == 0)
6635 + return 0;
6636 + else
6637 + {
6638 + printk(KERN_ERR "failed to unlock vc memory: s=%d response=%08x recv data size=%08x error%08x\n",
6639 + s, msg.m_response, msg.m_tag.m_recvDataSize, msg.m_tag.m_args.m_error);
6640 + return 1;
6641 + }
6642 +}
6643 +
6644 +unsigned int ExecuteVcCode(unsigned int code,
6645 + unsigned int r0, unsigned int r1, unsigned int r2, unsigned int r3, unsigned int r4, unsigned int r5)
6646 +{
6647 + struct vc_msg
6648 + {
6649 + unsigned int m_msgSize;
6650 + unsigned int m_response;
6651 +
6652 + struct vc_tag
6653 + {
6654 + unsigned int m_tagId;
6655 + unsigned int m_sendBufferSize;
6656 + union {
6657 + unsigned int m_sendDataSize;
6658 + unsigned int m_recvDataSize;
6659 + };
6660 +
6661 + struct args
6662 + {
6663 + union {
6664 + unsigned int m_pCode;
6665 + unsigned int m_return;
6666 + };
6667 + unsigned int m_r0;
6668 + unsigned int m_r1;
6669 + unsigned int m_r2;
6670 + unsigned int m_r3;
6671 + unsigned int m_r4;
6672 + unsigned int m_r5;
6673 + } m_args;
6674 + } m_tag;
6675 +
6676 + unsigned int m_endTag;
6677 + } msg;
6678 + int s;
6679 +
6680 + msg.m_msgSize = sizeof(msg);
6681 + msg.m_response = 0;
6682 + msg.m_endTag = 0;
6683 +
6684 + //fill in the tag for the unlock command
6685 + msg.m_tag.m_tagId = 0x30010;
6686 + msg.m_tag.m_sendBufferSize = 28;
6687 + msg.m_tag.m_sendDataSize = 28;
6688 +
6689 + //pass across the handle
6690 + msg.m_tag.m_args.m_pCode = code;
6691 + msg.m_tag.m_args.m_r0 = r0;
6692 + msg.m_tag.m_args.m_r1 = r1;
6693 + msg.m_tag.m_args.m_r2 = r2;
6694 + msg.m_tag.m_args.m_r3 = r3;
6695 + msg.m_tag.m_args.m_r4 = r4;
6696 + msg.m_tag.m_args.m_r5 = r5;
6697 +
6698 + s = bcm_mailbox_property(&msg, sizeof(msg));
6699 +
6700 + //check the error code too
6701 + if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004)
6702 + return msg.m_tag.m_args.m_return;
6703 + else
6704 + {
6705 + printk(KERN_ERR "failed to execute: s=%d response=%08x recv data size=%08x\n",
6706 + s, msg.m_response, msg.m_tag.m_recvDataSize);
6707 + return 1;
6708 + }
6709 +}
6710 --- a/arch/arm/mm/Kconfig
6711 +++ b/arch/arm/mm/Kconfig
6712 @@ -358,7 +358,7 @@ config CPU_PJ4B
6713
6714 # ARMv6
6715 config CPU_V6
6716 - bool "Support ARM V6 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX)
6717 + bool "Support ARM V6 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || MACH_BCM2708)
6718 select CPU_32v6
6719 select CPU_ABRT_EV6
6720 select CPU_CACHE_V6
6721 --- a/arch/arm/mm/proc-v6.S
6722 +++ b/arch/arm/mm/proc-v6.S
6723 @@ -73,10 +73,19 @@ ENDPROC(cpu_v6_reset)
6724 *
6725 * IRQs are already disabled.
6726 */
6727 +
6728 +/* See jira SW-5991 for details of this workaround */
6729 ENTRY(cpu_v6_do_idle)
6730 - mov r1, #0
6731 - mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
6732 - mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
6733 + .align 5
6734 + mov r1, #2
6735 +1: subs r1, #1
6736 + nop
6737 + mcreq p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
6738 + mcreq p15, 0, r1, c7, c0, 4 @ wait for interrupt
6739 + nop
6740 + nop
6741 + nop
6742 + bne 1b
6743 ret lr
6744
6745 ENTRY(cpu_v6_dcache_clean_area)
6746 --- a/arch/arm/mm/proc-v7.S
6747 +++ b/arch/arm/mm/proc-v7.S
6748 @@ -456,6 +456,7 @@ __v7_setup:
6749 orr r0, r0, r6 @ set them
6750 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
6751 ret lr @ return to head.S:__ret
6752 + .space 256
6753 ENDPROC(__v7_setup)
6754
6755 .align 2
6756 --- a/arch/arm/tools/mach-types
6757 +++ b/arch/arm/tools/mach-types
6758 @@ -522,6 +522,8 @@ torbreck MACH_TORBRECK TORBRECK 3090
6759 prima2_evb MACH_PRIMA2_EVB PRIMA2_EVB 3103
6760 paz00 MACH_PAZ00 PAZ00 3128
6761 acmenetusfoxg20 MACH_ACMENETUSFOXG20 ACMENETUSFOXG20 3129
6762 +bcm2708 MACH_BCM2708 BCM2708 3138
6763 +bcm2709 MACH_BCM2709 BCM2709 3139
6764 ag5evm MACH_AG5EVM AG5EVM 3189
6765 ics_if_voip MACH_ICS_IF_VOIP ICS_IF_VOIP 3206
6766 wlf_cragg_6410 MACH_WLF_CRAGG_6410 WLF_CRAGG_6410 3207
6767 --- a/drivers/clocksource/arm_arch_timer.c
6768 +++ b/drivers/clocksource/arm_arch_timer.c
6769 @@ -882,3 +882,39 @@ void __init acpi_generic_timer_init(void
6770 acpi_table_parse(ACPI_SIG_GTDT, arch_timer_acpi_init);
6771 }
6772 #endif
6773 +
6774 +int __init dc4_arch_timer_init(void)
6775 +{
6776 + if (arch_timers_present & ARCH_CP15_TIMER) {
6777 + pr_warn("arch_timer: multiple nodes in dt, skipping\n");
6778 + return -1;
6779 + }
6780 +
6781 + arch_timers_present |= ARCH_CP15_TIMER;
6782 +
6783 + /* Try to determine the frequency from the device tree or CNTFRQ */
6784 + arch_timer_rate = 19200000;
6785 +
6786 + arch_timer_ppi[PHYS_SECURE_PPI] = IRQ_ARM_LOCAL_CNTPSIRQ;
6787 + arch_timer_ppi[PHYS_NONSECURE_PPI] = IRQ_ARM_LOCAL_CNTPNSIRQ;
6788 + arch_timer_ppi[VIRT_PPI] = IRQ_ARM_LOCAL_CNTVIRQ;
6789 + arch_timer_ppi[HYP_PPI] = IRQ_ARM_LOCAL_CNTHPIRQ;
6790 +
6791 + /*
6792 + * If HYP mode is available, we know that the physical timer
6793 + * has been configured to be accessible from PL1. Use it, so
6794 + * that a guest can use the virtual timer instead.
6795 + *
6796 + * If no interrupt provided for virtual timer, we'll have to
6797 + * stick to the physical timer. It'd better be accessible...
6798 + */
6799 + if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) {
6800 + arch_timer_use_virtual = false;
6801 + }
6802 +
6803 + arch_timer_c3stop = 0;
6804 +
6805 + arch_timer_register();
6806 + arch_timer_common_init();
6807 + return 0;
6808 +}
6809 --- a/drivers/tty/serial/amba-pl011.c
6810 +++ b/drivers/tty/serial/amba-pl011.c
6811 @@ -85,7 +85,7 @@ struct vendor_data {
6812
6813 static unsigned int get_fifosize_arm(struct amba_device *dev)
6814 {
6815 - return amba_rev(dev) < 3 ? 16 : 32;
6816 + return 16; //TODO: fix: amba_rev(dev) < 3 ? 16 : 32;
6817 }
6818
6819 static struct vendor_data vendor_arm = {
6820 --- a/include/linux/mmc/host.h
6821 +++ b/include/linux/mmc/host.h
6822 @@ -285,6 +285,7 @@ struct mmc_host {
6823 MMC_CAP2_HS400_1_2V)
6824 #define MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V)
6825 #define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17)
6826 +#define MMC_CAP2_FORCE_MULTIBLOCK (1 << 31) /* Always use multiblock transfers */
6827
6828 mmc_pm_flag_t pm_caps; /* supported pm features */
6829
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