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brcm2708: add linux 4.1 support
[openwrt/openwrt.git] / target / linux / brcm2708 / patches-4.1 / 0004-Add-dwc_otg-driver.patch
1 From 7c8a47937b598fa8dad4cd50753164b5ee44f8c1 Mon Sep 17 00:00:00 2001
2 From: popcornmix <popcornmix@gmail.com>
3 Date: Wed, 1 May 2013 19:46:17 +0100
4 Subject: [PATCH 004/121] Add dwc_otg driver
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
8
9 Signed-off-by: popcornmix <popcornmix@gmail.com>
10
11 usb: dwc: fix lockdep false positive
12
13 Signed-off-by: Kari Suvanto <karis79@gmail.com>
14
15 usb: dwc: fix inconsistent lock state
16
17 Signed-off-by: Kari Suvanto <karis79@gmail.com>
18
19 Add FIQ patch to dwc_otg driver. Enable with dwc_otg.fiq_fix_enable=1. Should give about 10% more ARM performance.
20 Thanks to Gordon and Costas
21
22 Avoid dynamic memory allocation for channel lock in USB driver. Thanks ddv2005.
23
24 Add NAK holdoff scheme. Enabled by default, disable with dwc_otg.nak_holdoff_enable=0. Thanks gsh
25
26 Make sure we wait for the reset to finish
27
28 dwc_otg: fix bug in dwc_otg_hcd.c resulting in silent kernel
29 memory corruption, escalating to OOPS under high USB load.
30
31 dwc_otg: Fix unsafe access of QTD during URB enqueue
32
33 In dwc_otg_hcd_urb_enqueue during qtd creation, it was possible that the
34 transaction could complete almost immediately after the qtd was assigned
35 to a host channel during URB enqueue, which meant the qtd pointer was no
36 longer valid having been completed and removed. Usually, this resulted in
37 an OOPS during URB submission. By predetermining whether transactions
38 need to be queued or not, this unsafe pointer access is avoided.
39
40 This bug was only evident on the Pi model A where a device was attached
41 that had no periodic endpoints (e.g. USB pendrive or some wlan devices).
42
43 dwc_otg: Fix incorrect URB allocation error handling
44
45 If the memory allocation for a dwc_otg_urb failed, the kernel would OOPS
46 because for some reason a member of the *unallocated* struct was set to
47 zero. Error handling changed to fail correctly.
48
49 dwc_otg: fix potential use-after-free case in interrupt handler
50
51 If a transaction had previously aborted, certain interrupts are
52 enabled to track error counts and reset where necessary. On IN
53 endpoints the host generates an ACK interrupt near-simultaneously
54 with completion of transfer. In the case where this transfer had
55 previously had an error, this results in a use-after-free on
56 the QTD memory space with a 1-byte length being overwritten to
57 0x00.
58
59 dwc_otg: add handling of SPLIT transaction data toggle errors
60
61 Previously a data toggle error on packets from a USB1.1 device behind
62 a TT would result in the Pi locking up as the driver never handled
63 the associated interrupt. Patch adds basic retry mechanism and
64 interrupt acknowledgement to cater for either a chance toggle error or
65 for devices that have a broken initial toggle state (FT8U232/FT232BM).
66
67 dwc_otg: implement tasklet for returning URBs to usbcore hcd layer
68
69 The dwc_otg driver interrupt handler for transfer completion will spend
70 a very long time with interrupts disabled when a URB is completed -
71 this is because usb_hcd_giveback_urb is called from within the handler
72 which for a USB device driver with complicated processing (e.g. webcam)
73 will take an exorbitant amount of time to complete. This results in
74 missed completion interrupts for other USB packets which lead to them
75 being dropped due to microframe overruns.
76
77 This patch splits returning the URB to the usb hcd layer into a
78 high-priority tasklet. This will have most benefit for isochronous IN
79 transfers but will also have incidental benefit where multiple periodic
80 devices are active at once.
81
82 dwc_otg: fix NAK holdoff and allow on split transactions only
83
84 This corrects a bug where if a single active non-periodic endpoint
85 had at least one transaction in its qh, on frnum == MAX_FRNUM the qh
86 would get skipped and never get queued again. This would result in
87 a silent device until error detection (automatic or otherwise) would
88 either reset the device or flush and requeue the URBs.
89
90 Additionally the NAK holdoff was enabled for all transactions - this
91 would potentially stall a HS endpoint for 1ms if a previous error state
92 enabled this interrupt and the next response was a NAK. Fix so that
93 only split transactions get held off.
94
95 dwc_otg: Call usb_hcd_unlink_urb_from_ep with lock held in completion handler
96
97 usb_hcd_unlink_urb_from_ep must be called with the HCD lock held. Calling it
98 asynchronously in the tasklet was not safe (regression in
99 c4564d4a1a0a9b10d4419e48239f5d99e88d2667).
100
101 This change unlinks it from the endpoint prior to queueing it for handling in
102 the tasklet, and also adds a check to ensure the urb is OK to be unlinked
103 before doing so.
104
105 NULL pointer dereference kernel oopses had been observed in usb_hcd_giveback_urb
106 when a USB device was unplugged/replugged during data transfer. This effect
107 was reproduced using automated USB port power control, hundreds of replug
108 events were performed during active transfers to confirm that the problem was
109 eliminated.
110
111 USB fix using a FIQ to implement split transactions
112
113 This commit adds a FIQ implementaion that schedules
114 the split transactions using a FIQ so we don't get
115 held off by the interrupt latency of Linux
116
117 dwc_otg: fix device attributes and avoid kernel warnings on boot
118
119 dcw_otg: avoid logging function that can cause panics
120
121 See: https://github.com/raspberrypi/firmware/issues/21
122 Thanks to cleverca22 for fix
123
124 dwc_otg: mask correct interrupts after transaction error recovery
125
126 The dwc_otg driver will unmask certain interrupts on a transaction
127 that previously halted in the error state in order to reset the
128 QTD error count. The various fine-grained interrupt handlers do not
129 consider that other interrupts besides themselves were unmasked.
130
131 By disabling the two other interrupts only ever enabled in DMA mode
132 for this purpose, we can avoid unnecessary function calls in the
133 IRQ handler. This will also prevent an unneccesary FIQ interrupt
134 from being generated if the FIQ is enabled.
135
136 dwc_otg: fiq: prevent FIQ thrash and incorrect state passing to IRQ
137
138 In the case of a transaction to a device that had previously aborted
139 due to an error, several interrupts are enabled to reset the error
140 count when a device responds. This has the side-effect of making the
141 FIQ thrash because the hardware will generate multiple instances of
142 a NAK on an IN bulk/interrupt endpoint and multiple instances of ACK
143 on an OUT bulk/interrupt endpoint. Make the FIQ mask and clear the
144 associated interrupts.
145
146 Additionally, on non-split transactions make sure that only unmasked
147 interrupts are cleared. This caused a hard-to-trigger but serious
148 race condition when you had the combination of an endpoint awaiting
149 error recovery and a transaction completed on an endpoint - due to
150 the sequencing and timing of interrupts generated by the dwc_otg core,
151 it was possible to confuse the IRQ handler.
152
153 Fix function tracing
154
155 dwc_otg: whitespace cleanup in dwc_otg_urb_enqueue
156
157 dwc_otg: prevent OOPSes during device disconnects
158
159 The dwc_otg_urb_enqueue function is thread-unsafe. In particular the
160 access of urb->hcpriv, usb_hcd_link_urb_to_ep, dwc_otg_urb->qtd and
161 friends does not occur within a critical section and so if a device
162 was unplugged during activity there was a high chance that the
163 usbcore hub_thread would try to disable the endpoint with partially-
164 formed entries in the URB queue. This would result in BUG() or null
165 pointer dereferences.
166
167 Fix so that access of urb->hcpriv, enqueuing to the hardware and
168 adding to usbcore endpoint URB lists is contained within a single
169 critical section.
170
171 dwc_otg: prevent BUG() in TT allocation if hub address is > 16
172
173 A fixed-size array is used to track TT allocation. This was
174 previously set to 16 which caused a crash because
175 dwc_otg_hcd_allocate_port would read past the end of the array.
176
177 This was hit if a hub was plugged in which enumerated as addr > 16,
178 due to previous device resets or unplugs.
179
180 Also add #ifdef FIQ_DEBUG around hcd->hub_port_alloc[], which grows
181 to a large size if 128 hub addresses are supported. This field is
182 for debug only for tracking which frame an allocate happened in.
183
184 dwc_otg: make channel halts with unknown state less damaging
185
186 If the IRQ received a channel halt interrupt through the FIQ
187 with no other bits set, the IRQ would not release the host
188 channel and never complete the URB.
189
190 Add catchall handling to treat as a transaction error and retry.
191
192 dwc_otg: fiq_split: use TTs with more granularity
193
194 This fixes certain issues with split transaction scheduling.
195
196 - Isochronous multi-packet OUT transactions now hog the TT until
197 they are completed - this prevents hubs aborting transactions
198 if they get a periodic start-split out-of-order
199 - Don't perform TT allocation on non-periodic endpoints - this
200 allows simultaneous use of the TT's bulk/control and periodic
201 transaction buffers
202
203 This commit will mainly affect USB audio playback.
204
205 dwc_otg: fix potential sleep while atomic during urb enqueue
206
207 Fixes a regression introduced with eb1b482a. Kmalloc called from
208 dwc_otg_hcd_qtd_add / dwc_otg_hcd_qtd_create did not always have
209 the GPF_ATOMIC flag set. Force this flag when inside the larger
210 critical section.
211
212 dwc_otg: make fiq_split_enable imply fiq_fix_enable
213
214 Failing to set up the FIQ correctly would result in
215 "IRQ 32: nobody cared" errors in dmesg.
216
217 dwc_otg: prevent crashes on host port disconnects
218
219 Fix several issues resulting in crashes or inconsistent state
220 if a Model A root port was disconnected.
221
222 - Clean up queue heads properly in kill_urbs_in_qh_list by
223 removing the empty QHs from the schedule lists
224 - Set the halt status properly to prevent IRQ handlers from
225 using freed memory
226 - Add fiq_split related cleanup for saved registers
227 - Make microframe scheduling reclaim host channels if
228 active during a disconnect
229 - Abort URBs with -ESHUTDOWN status response, informing
230 device drivers so they respond in a more correct fashion
231 and don't try to resubmit URBs
232 - Prevent IRQ handlers from attempting to handle channel
233 interrupts if the associated URB was dequeued (and the
234 driver state was cleared)
235
236 dwc_otg: prevent leaking URBs during enqueue
237
238 A dwc_otg_urb would get leaked if the HCD enqueue function
239 failed for any reason. Free the URB at the appropriate points.
240
241 dwc_otg: Enable NAK holdoff for control split transactions
242
243 Certain low-speed devices take a very long time to complete a
244 data or status stage of a control transaction, producing NAK
245 responses until they complete internal processing - the USB2.0
246 spec limit is up to 500mS. This causes the same type of interrupt
247 storm as seen with USB-serial dongles prior to c8edb238.
248
249 In certain circumstances, usually while booting, this interrupt
250 storm could cause SD card timeouts.
251
252 dwc_otg: Fix for occasional lockup on boot when doing a USB reset
253
254 dwc_otg: Don't issue traffic to LS devices in FS mode
255
256 Issuing low-speed packets when the root port is in full-speed mode
257 causes the root port to stop responding. Explicitly fail when
258 enqueuing URBs to a LS endpoint on a FS bus.
259
260 Fix ARM architecture issue with local_irq_restore()
261
262 If local_fiq_enable() is called before a local_irq_restore(flags) where
263 the flags variable has the F bit set, the FIQ will be erroneously disabled.
264
265 Fixup arch_local_irq_restore to avoid trampling the F bit in CPSR.
266
267 Also fix some of the hacks previously implemented for previous dwc_otg
268 incarnations.
269
270 dwc_otg: fiq_fsm: Base commit for driver rewrite
271
272 This commit removes the previous FIQ fixes entirely and adds fiq_fsm.
273
274 This rewrite features much more complete support for split transactions
275 and takes into account several OTG hardware bugs. High-speed
276 isochronous transactions are also capable of being performed by fiq_fsm.
277
278 All driver options have been removed and replaced with:
279 - dwc_otg.fiq_enable (bool)
280 - dwc_otg.fiq_fsm_enable (bool)
281 - dwc_otg.fiq_fsm_mask (bitmask)
282 - dwc_otg.nak_holdoff (unsigned int)
283
284 Defaults are specified such that fiq_fsm behaves similarly to the
285 previously implemented FIQ fixes.
286
287 fiq_fsm: Push error recovery into the FIQ when fiq_fsm is used
288
289 If the transfer associated with a QTD failed due to a bus error, the HCD
290 would retry the transfer up to 3 times (implementing the USB2.0
291 three-strikes retry in software).
292
293 Due to the masking mechanism used by fiq_fsm, it is only possible to pass
294 a single interrupt through to the HCD per-transfer.
295
296 In this instance host channels would fall off the radar because the error
297 reset would function, but the subsequent channel halt would be lost.
298
299 Push the error count reset into the FIQ handler.
300
301 fiq_fsm: Implement timeout mechanism
302
303 For full-speed endpoints with a large packet size, interrupt latency
304 runs the risk of the FIQ starting a transaction too late in a full-speed
305 frame. If the device is still transmitting data when EOF2 for the
306 downstream frame occurs, the hub will disable the port. This change is
307 not reflected in the hub status endpoint and the device becomes
308 unresponsive.
309
310 Prevent high-bandwidth transactions from being started too late in a
311 frame. The mechanism is not guaranteed: a combination of bit stuffing
312 and hub latency may still result in a device overrunning.
313
314 fiq_fsm: fix bounce buffer utilisation for Isochronous OUT
315
316 Multi-packet isochronous OUT transactions were subject to a few bounday
317 bugs. Fix them.
318
319 Audio playback is now much more robust: however, an issue stands with
320 devices that have adaptive sinks - ALSA plays samples too fast.
321
322 dwc_otg: Return full-speed frame numbers in HS mode
323
324 The frame counter increments on every *microframe* in high-speed mode.
325 Most device drivers expect this number to be in full-speed frames - this
326 caused considerable confusion to e.g. snd_usb_audio which uses the
327 frame counter to estimate the number of samples played.
328
329 fiq_fsm: save PID on completion of interrupt OUT transfers
330
331 Also add edge case handling for interrupt transports.
332
333 Note that for periodic split IN, data toggles are unimplemented in the
334 OTG host hardware - it unconditionally accepts any PID.
335
336 fiq_fsm: add missing case for fiq_fsm_tt_in_use()
337
338 Certain combinations of bitrate and endpoint activity could
339 result in a periodic transaction erroneously getting started
340 while the previous Isochronous OUT was still active.
341
342 fiq_fsm: clear hcintmsk for aborted transactions
343
344 Prevents the FIQ from erroneously handling interrupts
345 on a timed out channel.
346
347 fiq_fsm: enable by default
348
349 fiq_fsm: fix dequeues for non-periodic split transactions
350
351 If a dequeue happened between the SSPLIT and CSPLIT phases of the
352 transaction, the HCD would never receive an interrupt.
353
354 fiq_fsm: Disable by default
355
356 fiq_fsm: Handle HC babble errors
357
358 The HCTSIZ transfer size field raises a babble interrupt if
359 the counter wraps. Handle the resulting interrupt in this case.
360
361 dwc_otg: fix interrupt registration for fiq_enable=0
362
363 Additionally make the module parameter conditional for wherever
364 hcd->fiq_state is touched.
365
366 fiq_fsm: Enable by default
367
368 dwc_otg: Fix various issues with root port and transaction errors
369
370 Process the host port interrupts correctly (and don't trample them).
371 Root port hotplug now functional again.
372
373 Fix a few thinkos with the transaction error passthrough for fiq_fsm.
374
375 fiq_fsm: Implement hack for Split Interrupt transactions
376
377 Hubs aren't too picky about which endpoint we send Control type split
378 transactions to. By treating Interrupt transfers as Control, it is
379 possible to use the non-periodic queue in the OTG core as well as the
380 non-periodic FIFOs in the hub itself. This massively reduces the
381 microframe exclusivity/contention that periodic split transactions
382 otherwise have to enforce.
383
384 It goes without saying that this is a fairly egregious USB specification
385 violation, but it works.
386
387 Original idea by Hans Petter Selasky @ FreeBSD.org.
388
389 dwc_otg: FIQ support on SMP. Set up FIQ stack and handler on Core 0 only.
390
391 dwc_otg: introduce fiq_fsm_spin(un|)lock()
392
393 SMP safety for the FIQ relies on register read-modify write cycles being
394 completed in the correct order. Several places in the DWC code modify
395 registers also touched by the FIQ. Protect these by a bare-bones lock
396 mechanism.
397
398 This also makes it possible to run the FIQ and IRQ handlers on different
399 cores.
400
401 fiq_fsm: fix build on bcm2708 and bcm2709 platforms
402
403 dwc_otg: put some barriers back where they should be for UP
404
405 bcm2709/dwc_otg: Setup FIQ on core 1 if >1 core active
406
407 dwc_otg: fixup read-modify-write in critical paths
408
409 Be more careful about read-modify-write on registers that the FIQ
410 also touches.
411
412 Guard fiq_fsm_spin_lock with fiq_enable check
413
414 fiq_fsm: Falling out of the state machine isn't fatal
415
416 This edge case can be hit if the port is disabled while the FIQ is
417 in the middle of a transaction. Make the effects less severe.
418
419 Also get rid of the useless return value.
420
421 squash: dwc_otg: Allow to build without SMP
422
423 usb: core: make overcurrent messages more prominent
424
425 Hub overcurrent messages are more serious than "debug". Increase loglevel.
426
427 usb: dwc_otg: Don't use dma_to_virt()
428
429 Commit 6ce0d20 changes dma_to_virt() which breaks this driver.
430 Open code the old dma_to_virt() implementation to work around this.
431
432 Limit the use of __bus_to_virt() to cases where transfer_buffer_length
433 is set and transfer_buffer is not set. This is done to increase the
434 chance that this driver will also work on ARCH_BCM2835.
435
436 transfer_buffer should not be NULL if the length is set, but the
437 comment in the code indicates that there are situations where this
438 might happen. drivers/usb/isp1760/isp1760-hcd.c also has a similar
439 comment pointing to a possible: 'usb storage / SCSI bug'.
440
441 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
442
443 dwc_otg: Fix crash when fiq_enable=0
444 ---
445 arch/arm/include/asm/irqflags.h | 16 +-
446 arch/arm/kernel/fiqasm.S | 4 +
447 arch/arm/mach-bcm2708/armctrl.c | 19 +-
448 arch/arm/mach-bcm2708/bcm2708.c | 11 +
449 arch/arm/mach-bcm2708/include/mach/irqs.h | 153 +-
450 arch/arm/mach-bcm2709/armctrl.c | 10 +-
451 drivers/usb/Makefile | 1 +
452 drivers/usb/core/generic.c | 1 +
453 drivers/usb/core/hub.c | 2 +-
454 drivers/usb/core/message.c | 79 +
455 drivers/usb/core/otg_whitelist.h | 114 +-
456 drivers/usb/gadget/file_storage.c | 3676 ++++++++++
457 drivers/usb/host/Kconfig | 13 +
458 drivers/usb/host/Makefile | 2 +
459 drivers/usb/host/dwc_common_port/Makefile | 58 +
460 drivers/usb/host/dwc_common_port/Makefile.fbsd | 17 +
461 drivers/usb/host/dwc_common_port/Makefile.linux | 49 +
462 drivers/usb/host/dwc_common_port/changes.txt | 174 +
463 drivers/usb/host/dwc_common_port/doc/doxygen.cfg | 270 +
464 drivers/usb/host/dwc_common_port/dwc_cc.c | 532 ++
465 drivers/usb/host/dwc_common_port/dwc_cc.h | 224 +
466 drivers/usb/host/dwc_common_port/dwc_common_fbsd.c | 1308 ++++
467 .../usb/host/dwc_common_port/dwc_common_linux.c | 1434 ++++
468 drivers/usb/host/dwc_common_port/dwc_common_nbsd.c | 1275 ++++
469 drivers/usb/host/dwc_common_port/dwc_crypto.c | 308 +
470 drivers/usb/host/dwc_common_port/dwc_crypto.h | 111 +
471 drivers/usb/host/dwc_common_port/dwc_dh.c | 291 +
472 drivers/usb/host/dwc_common_port/dwc_dh.h | 106 +
473 drivers/usb/host/dwc_common_port/dwc_list.h | 594 ++
474 drivers/usb/host/dwc_common_port/dwc_mem.c | 245 +
475 drivers/usb/host/dwc_common_port/dwc_modpow.c | 636 ++
476 drivers/usb/host/dwc_common_port/dwc_modpow.h | 34 +
477 drivers/usb/host/dwc_common_port/dwc_notifier.c | 319 +
478 drivers/usb/host/dwc_common_port/dwc_notifier.h | 122 +
479 drivers/usb/host/dwc_common_port/dwc_os.h | 1276 ++++
480 drivers/usb/host/dwc_common_port/usb.h | 946 +++
481 drivers/usb/host/dwc_otg/Makefile | 82 +
482 drivers/usb/host/dwc_otg/doc/doxygen.cfg | 224 +
483 drivers/usb/host/dwc_otg/dummy_audio.c | 1575 +++++
484 drivers/usb/host/dwc_otg/dwc_cfi_common.h | 142 +
485 drivers/usb/host/dwc_otg/dwc_otg_adp.c | 854 +++
486 drivers/usb/host/dwc_otg/dwc_otg_adp.h | 80 +
487 drivers/usb/host/dwc_otg/dwc_otg_attr.c | 1210 ++++
488 drivers/usb/host/dwc_otg/dwc_otg_attr.h | 89 +
489 drivers/usb/host/dwc_otg/dwc_otg_cfi.c | 1876 +++++
490 drivers/usb/host/dwc_otg/dwc_otg_cfi.h | 320 +
491 drivers/usb/host/dwc_otg/dwc_otg_cil.c | 7141 ++++++++++++++++++++
492 drivers/usb/host/dwc_otg/dwc_otg_cil.h | 1464 ++++
493 drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c | 1594 +++++
494 drivers/usb/host/dwc_otg/dwc_otg_core_if.h | 705 ++
495 drivers/usb/host/dwc_otg/dwc_otg_dbg.h | 117 +
496 drivers/usb/host/dwc_otg/dwc_otg_driver.c | 1756 +++++
497 drivers/usb/host/dwc_otg/dwc_otg_driver.h | 86 +
498 drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c | 1346 ++++
499 drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h | 367 +
500 drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S | 80 +
501 drivers/usb/host/dwc_otg/dwc_otg_hcd.c | 4252 ++++++++++++
502 drivers/usb/host/dwc_otg/dwc_otg_hcd.h | 862 +++
503 drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c | 1132 ++++
504 drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h | 417 ++
505 drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 2713 ++++++++
506 drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c | 995 +++
507 drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c | 957 +++
508 drivers/usb/host/dwc_otg/dwc_otg_os_dep.h | 188 +
509 drivers/usb/host/dwc_otg/dwc_otg_pcd.c | 2712 ++++++++
510 drivers/usb/host/dwc_otg/dwc_otg_pcd.h | 266 +
511 drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h | 360 +
512 drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c | 5147 ++++++++++++++
513 drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c | 1360 ++++
514 drivers/usb/host/dwc_otg/dwc_otg_regs.h | 2550 +++++++
515 drivers/usb/host/dwc_otg/test/Makefile | 16 +
516 drivers/usb/host/dwc_otg/test/dwc_otg_test.pm | 337 +
517 drivers/usb/host/dwc_otg/test/test_mod_param.pl | 133 +
518 drivers/usb/host/dwc_otg/test/test_sysfs.pl | 193 +
519 74 files changed, 60032 insertions(+), 96 deletions(-)
520 create mode 100644 drivers/usb/gadget/file_storage.c
521 create mode 100644 drivers/usb/host/dwc_common_port/Makefile
522 create mode 100644 drivers/usb/host/dwc_common_port/Makefile.fbsd
523 create mode 100644 drivers/usb/host/dwc_common_port/Makefile.linux
524 create mode 100644 drivers/usb/host/dwc_common_port/changes.txt
525 create mode 100644 drivers/usb/host/dwc_common_port/doc/doxygen.cfg
526 create mode 100644 drivers/usb/host/dwc_common_port/dwc_cc.c
527 create mode 100644 drivers/usb/host/dwc_common_port/dwc_cc.h
528 create mode 100644 drivers/usb/host/dwc_common_port/dwc_common_fbsd.c
529 create mode 100644 drivers/usb/host/dwc_common_port/dwc_common_linux.c
530 create mode 100644 drivers/usb/host/dwc_common_port/dwc_common_nbsd.c
531 create mode 100644 drivers/usb/host/dwc_common_port/dwc_crypto.c
532 create mode 100644 drivers/usb/host/dwc_common_port/dwc_crypto.h
533 create mode 100644 drivers/usb/host/dwc_common_port/dwc_dh.c
534 create mode 100644 drivers/usb/host/dwc_common_port/dwc_dh.h
535 create mode 100644 drivers/usb/host/dwc_common_port/dwc_list.h
536 create mode 100644 drivers/usb/host/dwc_common_port/dwc_mem.c
537 create mode 100644 drivers/usb/host/dwc_common_port/dwc_modpow.c
538 create mode 100644 drivers/usb/host/dwc_common_port/dwc_modpow.h
539 create mode 100644 drivers/usb/host/dwc_common_port/dwc_notifier.c
540 create mode 100644 drivers/usb/host/dwc_common_port/dwc_notifier.h
541 create mode 100644 drivers/usb/host/dwc_common_port/dwc_os.h
542 create mode 100644 drivers/usb/host/dwc_common_port/usb.h
543 create mode 100644 drivers/usb/host/dwc_otg/Makefile
544 create mode 100644 drivers/usb/host/dwc_otg/doc/doxygen.cfg
545 create mode 100644 drivers/usb/host/dwc_otg/dummy_audio.c
546 create mode 100644 drivers/usb/host/dwc_otg/dwc_cfi_common.h
547 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_adp.c
548 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_adp.h
549 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_attr.c
550 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_attr.h
551 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cfi.c
552 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cfi.h
553 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cil.c
554 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cil.h
555 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c
556 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_core_if.h
557 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_dbg.h
558 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_driver.c
559 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_driver.h
560 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
561 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h
562 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S
563 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd.c
564 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd.h
565 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c
566 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h
567 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
568 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
569 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c
570 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_os_dep.h
571 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd.c
572 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd.h
573 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h
574 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c
575 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c
576 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_regs.h
577 create mode 100644 drivers/usb/host/dwc_otg/test/Makefile
578 create mode 100644 drivers/usb/host/dwc_otg/test/dwc_otg_test.pm
579 create mode 100644 drivers/usb/host/dwc_otg/test/test_mod_param.pl
580 create mode 100644 drivers/usb/host/dwc_otg/test/test_sysfs.pl
581
582 --- a/arch/arm/include/asm/irqflags.h
583 +++ b/arch/arm/include/asm/irqflags.h
584 @@ -145,12 +145,22 @@ static inline unsigned long arch_local_s
585 }
586
587 /*
588 - * restore saved IRQ & FIQ state
589 + * restore saved IRQ state
590 */
591 static inline void arch_local_irq_restore(unsigned long flags)
592 {
593 - asm volatile(
594 - " msr " IRQMASK_REG_NAME_W ", %0 @ local_irq_restore"
595 + unsigned long temp = 0;
596 + flags &= ~(1 << 6);
597 + asm volatile (
598 + " mrs %0, cpsr"
599 + : "=r" (temp)
600 + :
601 + : "memory", "cc");
602 + /* Preserve FIQ bit */
603 + temp &= (1 << 6);
604 + flags = flags | temp;
605 + asm volatile (
606 + " msr cpsr_c, %0 @ local_irq_restore"
607 :
608 : "r" (flags)
609 : "memory", "cc");
610 --- a/arch/arm/kernel/fiqasm.S
611 +++ b/arch/arm/kernel/fiqasm.S
612 @@ -47,3 +47,7 @@ ENTRY(__get_fiq_regs)
613 mov r0, r0 @ avoid hazard prior to ARMv4
614 ret lr
615 ENDPROC(__get_fiq_regs)
616 +
617 +ENTRY(__FIQ_Branch)
618 + mov pc, r8
619 +ENDPROC(__FIQ_Branch)
620 --- a/arch/arm/mach-bcm2708/armctrl.c
621 +++ b/arch/arm/mach-bcm2708/armctrl.c
622 @@ -54,8 +54,12 @@ static void armctrl_mask_irq(struct irq_
623 0
624 };
625
626 - unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
627 - writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3]));
628 + if (d->irq >= FIQ_START) {
629 + writel(0, __io_address(ARM_IRQ_FAST));
630 + } else {
631 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
632 + writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3]));
633 + }
634 }
635
636 static void armctrl_unmask_irq(struct irq_data *d)
637 @@ -67,8 +71,14 @@ static void armctrl_unmask_irq(struct ir
638 0
639 };
640
641 - unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
642 - writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3]));
643 + if (d->irq >= FIQ_START) {
644 + unsigned int data =
645 + (unsigned int)irq_get_chip_data(d->irq) - FIQ_START;
646 + writel(0x80 | data, __io_address(ARM_IRQ_FAST));
647 + } else {
648 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
649 + writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3]));
650 + }
651 }
652
653 #ifdef CONFIG_OF
654 @@ -299,6 +309,7 @@ int __init armctrl_init(void __iomem * b
655 }
656
657 armctrl_pm_register(base, irq_start, resume_sources);
658 + init_FIQ(FIQ_START);
659 armctrl_dt_init();
660 return 0;
661 }
662 --- a/arch/arm/mach-bcm2708/bcm2708.c
663 +++ b/arch/arm/mach-bcm2708/bcm2708.c
664 @@ -254,12 +254,23 @@ static struct resource bcm2708_usb_resou
665 .flags = IORESOURCE_MEM,
666 },
667 [1] = {
668 + .start = MPHI_BASE,
669 + .end = MPHI_BASE + SZ_4K - 1,
670 + .flags = IORESOURCE_MEM,
671 + },
672 + [2] = {
673 + .start = IRQ_HOSTPORT,
674 + .end = IRQ_HOSTPORT,
675 + .flags = IORESOURCE_IRQ,
676 + },
677 + [3] = {
678 .start = IRQ_USB,
679 .end = IRQ_USB,
680 .flags = IORESOURCE_IRQ,
681 },
682 };
683
684 +
685 static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
686
687 static struct platform_device bcm2708_usb_device = {
688 --- a/arch/arm/mach-bcm2708/include/mach/irqs.h
689 +++ b/arch/arm/mach-bcm2708/include/mach/irqs.h
690 @@ -106,87 +106,90 @@
691 #define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1)
692 #define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2)
693
694 +#define FIQ_START HARD_IRQS
695 +
696 /*
697 * FIQ interrupts definitions are the same as the INT definitions.
698 */
699 -#define FIQ_TIMER0 INT_TIMER0
700 -#define FIQ_TIMER1 INT_TIMER1
701 -#define FIQ_TIMER2 INT_TIMER2
702 -#define FIQ_TIMER3 INT_TIMER3
703 -#define FIQ_CODEC0 INT_CODEC0
704 -#define FIQ_CODEC1 INT_CODEC1
705 -#define FIQ_CODEC2 INT_CODEC2
706 -#define FIQ_JPEG INT_JPEG
707 -#define FIQ_ISP INT_ISP
708 -#define FIQ_USB INT_USB
709 -#define FIQ_3D INT_3D
710 -#define FIQ_TRANSPOSER INT_TRANSPOSER
711 -#define FIQ_MULTICORESYNC0 INT_MULTICORESYNC0
712 -#define FIQ_MULTICORESYNC1 INT_MULTICORESYNC1
713 -#define FIQ_MULTICORESYNC2 INT_MULTICORESYNC2
714 -#define FIQ_MULTICORESYNC3 INT_MULTICORESYNC3
715 -#define FIQ_DMA0 INT_DMA0
716 -#define FIQ_DMA1 INT_DMA1
717 -#define FIQ_DMA2 INT_DMA2
718 -#define FIQ_DMA3 INT_DMA3
719 -#define FIQ_DMA4 INT_DMA4
720 -#define FIQ_DMA5 INT_DMA5
721 -#define FIQ_DMA6 INT_DMA6
722 -#define FIQ_DMA7 INT_DMA7
723 -#define FIQ_DMA8 INT_DMA8
724 -#define FIQ_DMA9 INT_DMA9
725 -#define FIQ_DMA10 INT_DMA10
726 -#define FIQ_DMA11 INT_DMA11
727 -#define FIQ_DMA12 INT_DMA12
728 -#define FIQ_AUX INT_AUX
729 -#define FIQ_ARM INT_ARM
730 -#define FIQ_VPUDMA INT_VPUDMA
731 -#define FIQ_HOSTPORT INT_HOSTPORT
732 -#define FIQ_VIDEOSCALER INT_VIDEOSCALER
733 -#define FIQ_CCP2TX INT_CCP2TX
734 -#define FIQ_SDC INT_SDC
735 -#define FIQ_DSI0 INT_DSI0
736 -#define FIQ_AVE INT_AVE
737 -#define FIQ_CAM0 INT_CAM0
738 -#define FIQ_CAM1 INT_CAM1
739 -#define FIQ_HDMI0 INT_HDMI0
740 -#define FIQ_HDMI1 INT_HDMI1
741 -#define FIQ_PIXELVALVE1 INT_PIXELVALVE1
742 -#define FIQ_I2CSPISLV INT_I2CSPISLV
743 -#define FIQ_DSI1 INT_DSI1
744 -#define FIQ_PWA0 INT_PWA0
745 -#define FIQ_PWA1 INT_PWA1
746 -#define FIQ_CPR INT_CPR
747 -#define FIQ_SMI INT_SMI
748 -#define FIQ_GPIO0 INT_GPIO0
749 -#define FIQ_GPIO1 INT_GPIO1
750 -#define FIQ_GPIO2 INT_GPIO2
751 -#define FIQ_GPIO3 INT_GPIO3
752 -#define FIQ_I2C INT_I2C
753 -#define FIQ_SPI INT_SPI
754 -#define FIQ_I2SPCM INT_I2SPCM
755 -#define FIQ_SDIO INT_SDIO
756 -#define FIQ_UART INT_UART
757 -#define FIQ_SLIMBUS INT_SLIMBUS
758 -#define FIQ_VEC INT_VEC
759 -#define FIQ_CPG INT_CPG
760 -#define FIQ_RNG INT_RNG
761 -#define FIQ_ARASANSDIO INT_ARASANSDIO
762 -#define FIQ_AVSPMON INT_AVSPMON
763 +#define FIQ_TIMER0 (FIQ_START+INTERRUPT_TIMER0)
764 +#define FIQ_TIMER1 (FIQ_START+INTERRUPT_TIMER1)
765 +#define FIQ_TIMER2 (FIQ_START+INTERRUPT_TIMER2)
766 +#define FIQ_TIMER3 (FIQ_START+INTERRUPT_TIMER3)
767 +#define FIQ_CODEC0 (FIQ_START+INTERRUPT_CODEC0)
768 +#define FIQ_CODEC1 (FIQ_START+INTERRUPT_CODEC1)
769 +#define FIQ_CODEC2 (FIQ_START+INTERRUPT_CODEC2)
770 +#define FIQ_JPEG (FIQ_START+INTERRUPT_JPEG)
771 +#define FIQ_ISP (FIQ_START+INTERRUPT_ISP)
772 +#define FIQ_USB (FIQ_START+INTERRUPT_USB)
773 +#define FIQ_3D (FIQ_START+INTERRUPT_3D)
774 +#define FIQ_TRANSPOSER (FIQ_START+INTERRUPT_TRANSPOSER)
775 +#define FIQ_MULTICORESYNC0 (FIQ_START+INTERRUPT_MULTICORESYNC0)
776 +#define FIQ_MULTICORESYNC1 (FIQ_START+INTERRUPT_MULTICORESYNC1)
777 +#define FIQ_MULTICORESYNC2 (FIQ_START+INTERRUPT_MULTICORESYNC2)
778 +#define FIQ_MULTICORESYNC3 (FIQ_START+INTERRUPT_MULTICORESYNC3)
779 +#define FIQ_DMA0 (FIQ_START+INTERRUPT_DMA0)
780 +#define FIQ_DMA1 (FIQ_START+INTERRUPT_DMA1)
781 +#define FIQ_DMA2 (FIQ_START+INTERRUPT_DMA2)
782 +#define FIQ_DMA3 (FIQ_START+INTERRUPT_DMA3)
783 +#define FIQ_DMA4 (FIQ_START+INTERRUPT_DMA4)
784 +#define FIQ_DMA5 (FIQ_START+INTERRUPT_DMA5)
785 +#define FIQ_DMA6 (FIQ_START+INTERRUPT_DMA6)
786 +#define FIQ_DMA7 (FIQ_START+INTERRUPT_DMA7)
787 +#define FIQ_DMA8 (FIQ_START+INTERRUPT_DMA8)
788 +#define FIQ_DMA9 (FIQ_START+INTERRUPT_DMA9)
789 +#define FIQ_DMA10 (FIQ_START+INTERRUPT_DMA10)
790 +#define FIQ_DMA11 (FIQ_START+INTERRUPT_DMA11)
791 +#define FIQ_DMA12 (FIQ_START+INTERRUPT_DMA12)
792 +#define FIQ_AUX (FIQ_START+INTERRUPT_AUX)
793 +#define FIQ_ARM (FIQ_START+INTERRUPT_ARM)
794 +#define FIQ_VPUDMA (FIQ_START+INTERRUPT_VPUDMA)
795 +#define FIQ_HOSTPORT (FIQ_START+INTERRUPT_HOSTPORT)
796 +#define FIQ_VIDEOSCALER (FIQ_START+INTERRUPT_VIDEOSCALER)
797 +#define FIQ_CCP2TX (FIQ_START+INTERRUPT_CCP2TX)
798 +#define FIQ_SDC (FIQ_START+INTERRUPT_SDC)
799 +#define FIQ_DSI0 (FIQ_START+INTERRUPT_DSI0)
800 +#define FIQ_AVE (FIQ_START+INTERRUPT_AVE)
801 +#define FIQ_CAM0 (FIQ_START+INTERRUPT_CAM0)
802 +#define FIQ_CAM1 (FIQ_START+INTERRUPT_CAM1)
803 +#define FIQ_HDMI0 (FIQ_START+INTERRUPT_HDMI0)
804 +#define FIQ_HDMI1 (FIQ_START+INTERRUPT_HDMI1)
805 +#define FIQ_PIXELVALVE1 (FIQ_START+INTERRUPT_PIXELVALVE1)
806 +#define FIQ_I2CSPISLV (FIQ_START+INTERRUPT_I2CSPISLV)
807 +#define FIQ_DSI1 (FIQ_START+INTERRUPT_DSI1)
808 +#define FIQ_PWA0 (FIQ_START+INTERRUPT_PWA0)
809 +#define FIQ_PWA1 (FIQ_START+INTERRUPT_PWA1)
810 +#define FIQ_CPR (FIQ_START+INTERRUPT_CPR)
811 +#define FIQ_SMI (FIQ_START+INTERRUPT_SMI)
812 +#define FIQ_GPIO0 (FIQ_START+INTERRUPT_GPIO0)
813 +#define FIQ_GPIO1 (FIQ_START+INTERRUPT_GPIO1)
814 +#define FIQ_GPIO2 (FIQ_START+INTERRUPT_GPIO2)
815 +#define FIQ_GPIO3 (FIQ_START+INTERRUPT_GPIO3)
816 +#define FIQ_I2C (FIQ_START+INTERRUPT_I2C)
817 +#define FIQ_SPI (FIQ_START+INTERRUPT_SPI)
818 +#define FIQ_I2SPCM (FIQ_START+INTERRUPT_I2SPCM)
819 +#define FIQ_SDIO (FIQ_START+INTERRUPT_SDIO)
820 +#define FIQ_UART (FIQ_START+INTERRUPT_UART)
821 +#define FIQ_SLIMBUS (FIQ_START+INTERRUPT_SLIMBUS)
822 +#define FIQ_VEC (FIQ_START+INTERRUPT_VEC)
823 +#define FIQ_CPG (FIQ_START+INTERRUPT_CPG)
824 +#define FIQ_RNG (FIQ_START+INTERRUPT_RNG)
825 +#define FIQ_ARASANSDIO (FIQ_START+INTERRUPT_ARASANSDIO)
826 +#define FIQ_AVSPMON (FIQ_START+INTERRUPT_AVSPMON)
827
828 -#define FIQ_ARM_TIMER INT_ARM_TIMER
829 -#define FIQ_ARM_MAILBOX INT_ARM_MAILBOX
830 -#define FIQ_ARM_DOORBELL_0 INT_ARM_DOORBELL_0
831 -#define FIQ_ARM_DOORBELL_1 INT_ARM_DOORBELL_1
832 -#define FIQ_VPU0_HALTED INT_VPU0_HALTED
833 -#define FIQ_VPU1_HALTED INT_VPU1_HALTED
834 -#define FIQ_ILLEGAL_TYPE0 INT_ILLEGAL_TYPE0
835 -#define FIQ_ILLEGAL_TYPE1 INT_ILLEGAL_TYPE1
836 -#define FIQ_PENDING1 INT_PENDING1
837 -#define FIQ_PENDING2 INT_PENDING2
838 +#define FIQ_ARM_TIMER (FIQ_START+INTERRUPT_ARM_TIMER)
839 +#define FIQ_ARM_MAILBOX (FIQ_START+INTERRUPT_ARM_MAILBOX)
840 +#define FIQ_ARM_DOORBELL_0 (FIQ_START+INTERRUPT_ARM_DOORBELL_0)
841 +#define FIQ_ARM_DOORBELL_1 (FIQ_START+INTERRUPT_ARM_DOORBELL_1)
842 +#define FIQ_VPU0_HALTED (FIQ_START+INTERRUPT_VPU0_HALTED)
843 +#define FIQ_VPU1_HALTED (FIQ_START+INTERRUPT_VPU1_HALTED)
844 +#define FIQ_ILLEGAL_TYPE0 (FIQ_START+INTERRUPT_ILLEGAL_TYPE0)
845 +#define FIQ_ILLEGAL_TYPE1 (FIQ_START+INTERRUPT_ILLEGAL_TYPE1)
846 +#define FIQ_PENDING1 (FIQ_START+INTERRUPT_PENDING1)
847 +#define FIQ_PENDING2 (FIQ_START+INTERRUPT_PENDING2)
848
849 #define HARD_IRQS (64 + 21)
850 -#define GPIO_IRQ_START (HARD_IRQS)
851 +#define FIQ_IRQS (64 + 21)
852 +#define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS)
853 #define GPIO_IRQS (32*5)
854 #define SPARE_ALLOC_IRQS 64
855 #define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS)
856 --- a/arch/arm/mach-bcm2709/armctrl.c
857 +++ b/arch/arm/mach-bcm2709/armctrl.c
858 @@ -91,7 +91,15 @@ static void armctrl_unmask_irq(struct ir
859 };
860 int i;
861 if (d->irq >= FIQ_START) {
862 - unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START;
863 + unsigned int data;
864 + if (num_online_cpus() > 1) {
865 + data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING));
866 + data &= ~0xc;
867 + data |= (1 << 2);
868 + writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING));
869 + }
870 + /* Unmask in ARMCTRL block after routing it properly */
871 + data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START;
872 writel(0x80 | data, __io_address(ARM_IRQ_FAST));
873 } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) {
874 #if 1
875 --- a/drivers/usb/Makefile
876 +++ b/drivers/usb/Makefile
877 @@ -7,6 +7,7 @@
878 obj-$(CONFIG_USB) += core/
879 obj-$(CONFIG_USB_SUPPORT) += phy/
880
881 +obj-$(CONFIG_USB_DWCOTG) += host/
882 obj-$(CONFIG_USB_DWC3) += dwc3/
883 obj-$(CONFIG_USB_DWC2) += dwc2/
884 obj-$(CONFIG_USB_ISP1760) += isp1760/
885 --- a/drivers/usb/core/generic.c
886 +++ b/drivers/usb/core/generic.c
887 @@ -152,6 +152,7 @@ int usb_choose_configuration(struct usb_
888 dev_warn(&udev->dev,
889 "no configuration chosen from %d choice%s\n",
890 num_configs, plural(num_configs));
891 + dev_warn(&udev->dev, "No support over %dmA\n", udev->bus_mA);
892 }
893 return i;
894 }
895 --- a/drivers/usb/core/hub.c
896 +++ b/drivers/usb/core/hub.c
897 @@ -4922,7 +4922,7 @@ static void port_event(struct usb_hub *h
898 if (portchange & USB_PORT_STAT_C_OVERCURRENT) {
899 u16 status = 0, unused;
900
901 - dev_dbg(&port_dev->dev, "over-current change\n");
902 + dev_notice(&port_dev->dev, "over-current change\n");
903 usb_clear_port_feature(hdev, port1,
904 USB_PORT_FEAT_C_OVER_CURRENT);
905 msleep(100); /* Cool down */
906 --- a/drivers/usb/core/message.c
907 +++ b/drivers/usb/core/message.c
908 @@ -1872,6 +1872,85 @@ free_interfaces:
909 if (cp->string == NULL &&
910 !(dev->quirks & USB_QUIRK_CONFIG_INTF_STRINGS))
911 cp->string = usb_cache_string(dev, cp->desc.iConfiguration);
912 +/* Uncomment this define to enable the HS Electrical Test support */
913 +#define DWC_HS_ELECT_TST 1
914 +#ifdef DWC_HS_ELECT_TST
915 + /* Here we implement the HS Electrical Test support. The
916 + * tester uses a vendor ID of 0x1A0A to indicate we should
917 + * run a special test sequence. The product ID tells us
918 + * which sequence to run. We invoke the test sequence by
919 + * sending a non-standard SetFeature command to our root
920 + * hub port. Our dwc_otg_hcd_hub_control() routine will
921 + * recognize the command and perform the desired test
922 + * sequence.
923 + */
924 + if (dev->descriptor.idVendor == 0x1A0A) {
925 + /* HSOTG Electrical Test */
926 + dev_warn(&dev->dev, "VID from HSOTG Electrical Test Fixture\n");
927 +
928 + if (dev->bus && dev->bus->root_hub) {
929 + struct usb_device *hdev = dev->bus->root_hub;
930 + dev_warn(&dev->dev, "Got PID 0x%x\n", dev->descriptor.idProduct);
931 +
932 + switch (dev->descriptor.idProduct) {
933 + case 0x0101: /* TEST_SE0_NAK */
934 + dev_warn(&dev->dev, "TEST_SE0_NAK\n");
935 + usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
936 + USB_REQ_SET_FEATURE, USB_RT_PORT,
937 + USB_PORT_FEAT_TEST, 0x300, NULL, 0, HZ);
938 + break;
939 +
940 + case 0x0102: /* TEST_J */
941 + dev_warn(&dev->dev, "TEST_J\n");
942 + usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
943 + USB_REQ_SET_FEATURE, USB_RT_PORT,
944 + USB_PORT_FEAT_TEST, 0x100, NULL, 0, HZ);
945 + break;
946 +
947 + case 0x0103: /* TEST_K */
948 + dev_warn(&dev->dev, "TEST_K\n");
949 + usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
950 + USB_REQ_SET_FEATURE, USB_RT_PORT,
951 + USB_PORT_FEAT_TEST, 0x200, NULL, 0, HZ);
952 + break;
953 +
954 + case 0x0104: /* TEST_PACKET */
955 + dev_warn(&dev->dev, "TEST_PACKET\n");
956 + usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
957 + USB_REQ_SET_FEATURE, USB_RT_PORT,
958 + USB_PORT_FEAT_TEST, 0x400, NULL, 0, HZ);
959 + break;
960 +
961 + case 0x0105: /* TEST_FORCE_ENABLE */
962 + dev_warn(&dev->dev, "TEST_FORCE_ENABLE\n");
963 + usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
964 + USB_REQ_SET_FEATURE, USB_RT_PORT,
965 + USB_PORT_FEAT_TEST, 0x500, NULL, 0, HZ);
966 + break;
967 +
968 + case 0x0106: /* HS_HOST_PORT_SUSPEND_RESUME */
969 + dev_warn(&dev->dev, "HS_HOST_PORT_SUSPEND_RESUME\n");
970 + usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
971 + USB_REQ_SET_FEATURE, USB_RT_PORT,
972 + USB_PORT_FEAT_TEST, 0x600, NULL, 0, 40 * HZ);
973 + break;
974 +
975 + case 0x0107: /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
976 + dev_warn(&dev->dev, "SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup\n");
977 + usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
978 + USB_REQ_SET_FEATURE, USB_RT_PORT,
979 + USB_PORT_FEAT_TEST, 0x700, NULL, 0, 40 * HZ);
980 + break;
981 +
982 + case 0x0108: /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
983 + dev_warn(&dev->dev, "SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute\n");
984 + usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
985 + USB_REQ_SET_FEATURE, USB_RT_PORT,
986 + USB_PORT_FEAT_TEST, 0x800, NULL, 0, 40 * HZ);
987 + }
988 + }
989 + }
990 +#endif /* DWC_HS_ELECT_TST */
991
992 /* Now that the interfaces are installed, re-enable LPM. */
993 usb_unlocked_enable_lpm(dev);
994 --- a/drivers/usb/core/otg_whitelist.h
995 +++ b/drivers/usb/core/otg_whitelist.h
996 @@ -19,33 +19,82 @@
997 static struct usb_device_id whitelist_table [] = {
998
999 /* hubs are optional in OTG, but very handy ... */
1000 +#define CERT_WITHOUT_HUBS
1001 +#if defined(CERT_WITHOUT_HUBS)
1002 +{ USB_DEVICE( 0x0000, 0x0000 ), }, /* Root HUB Only*/
1003 +#else
1004 { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 0), },
1005 { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 1), },
1006 +{ USB_DEVICE_INFO(USB_CLASS_HUB, 0, 2), },
1007 +#endif
1008
1009 #ifdef CONFIG_USB_PRINTER /* ignoring nonstatic linkage! */
1010 /* FIXME actually, printers are NOT supposed to use device classes;
1011 * they're supposed to use interface classes...
1012 */
1013 -{ USB_DEVICE_INFO(7, 1, 1) },
1014 -{ USB_DEVICE_INFO(7, 1, 2) },
1015 -{ USB_DEVICE_INFO(7, 1, 3) },
1016 +//{ USB_DEVICE_INFO(7, 1, 1) },
1017 +//{ USB_DEVICE_INFO(7, 1, 2) },
1018 +//{ USB_DEVICE_INFO(7, 1, 3) },
1019 #endif
1020
1021 #ifdef CONFIG_USB_NET_CDCETHER
1022 /* Linux-USB CDC Ethernet gadget */
1023 -{ USB_DEVICE(0x0525, 0xa4a1), },
1024 +//{ USB_DEVICE(0x0525, 0xa4a1), },
1025 /* Linux-USB CDC Ethernet + RNDIS gadget */
1026 -{ USB_DEVICE(0x0525, 0xa4a2), },
1027 +//{ USB_DEVICE(0x0525, 0xa4a2), },
1028 #endif
1029
1030 #if defined(CONFIG_USB_TEST) || defined(CONFIG_USB_TEST_MODULE)
1031 /* gadget zero, for testing */
1032 -{ USB_DEVICE(0x0525, 0xa4a0), },
1033 +//{ USB_DEVICE(0x0525, 0xa4a0), },
1034 #endif
1035
1036 +/* OPT Tester */
1037 +{ USB_DEVICE( 0x1a0a, 0x0101 ), }, /* TEST_SE0_NAK */
1038 +{ USB_DEVICE( 0x1a0a, 0x0102 ), }, /* Test_J */
1039 +{ USB_DEVICE( 0x1a0a, 0x0103 ), }, /* Test_K */
1040 +{ USB_DEVICE( 0x1a0a, 0x0104 ), }, /* Test_PACKET */
1041 +{ USB_DEVICE( 0x1a0a, 0x0105 ), }, /* Test_FORCE_ENABLE */
1042 +{ USB_DEVICE( 0x1a0a, 0x0106 ), }, /* HS_PORT_SUSPEND_RESUME */
1043 +{ USB_DEVICE( 0x1a0a, 0x0107 ), }, /* SINGLE_STEP_GET_DESCRIPTOR setup */
1044 +{ USB_DEVICE( 0x1a0a, 0x0108 ), }, /* SINGLE_STEP_GET_DESCRIPTOR execute */
1045 +
1046 +/* Sony cameras */
1047 +{ USB_DEVICE_VER(0x054c,0x0010,0x0410, 0x0500), },
1048 +
1049 +/* Memory Devices */
1050 +//{ USB_DEVICE( 0x0781, 0x5150 ), }, /* SanDisk */
1051 +//{ USB_DEVICE( 0x05DC, 0x0080 ), }, /* Lexar */
1052 +//{ USB_DEVICE( 0x4146, 0x9281 ), }, /* IOMEGA */
1053 +//{ USB_DEVICE( 0x067b, 0x2507 ), }, /* Hammer 20GB External HD */
1054 +{ USB_DEVICE( 0x0EA0, 0x2168 ), }, /* Ours Technology Inc. (BUFFALO ClipDrive)*/
1055 +//{ USB_DEVICE( 0x0457, 0x0150 ), }, /* Silicon Integrated Systems Corp. */
1056 +
1057 +/* HP Printers */
1058 +//{ USB_DEVICE( 0x03F0, 0x1102 ), }, /* HP Photosmart 245 */
1059 +//{ USB_DEVICE( 0x03F0, 0x1302 ), }, /* HP Photosmart 370 Series */
1060 +
1061 +/* Speakers */
1062 +//{ USB_DEVICE( 0x0499, 0x3002 ), }, /* YAMAHA YST-MS35D USB Speakers */
1063 +//{ USB_DEVICE( 0x0672, 0x1041 ), }, /* Labtec USB Headset */
1064 +
1065 { } /* Terminating entry */
1066 };
1067
1068 +static inline void report_errors(struct usb_device *dev)
1069 +{
1070 + /* OTG MESSAGE: report errors here, customize to match your product */
1071 + dev_info(&dev->dev, "device Vendor:%04x Product:%04x is not supported\n",
1072 + le16_to_cpu(dev->descriptor.idVendor),
1073 + le16_to_cpu(dev->descriptor.idProduct));
1074 + if (USB_CLASS_HUB == dev->descriptor.bDeviceClass){
1075 + dev_printk(KERN_CRIT, &dev->dev, "Unsupported Hub Topology\n");
1076 + } else {
1077 + dev_printk(KERN_CRIT, &dev->dev, "Attached Device is not Supported\n");
1078 + }
1079 +}
1080 +
1081 +
1082 static int is_targeted(struct usb_device *dev)
1083 {
1084 struct usb_device_id *id = whitelist_table;
1085 @@ -95,16 +144,57 @@ static int is_targeted(struct usb_device
1086 continue;
1087
1088 return 1;
1089 - }
1090 + /* NOTE: can't use usb_match_id() since interface caches
1091 + * aren't set up yet. this is cut/paste from that code.
1092 + */
1093 + for (id = whitelist_table; id->match_flags; id++) {
1094 +#ifdef DEBUG
1095 + dev_dbg(&dev->dev,
1096 + "ID: V:%04x P:%04x DC:%04x SC:%04x PR:%04x \n",
1097 + id->idVendor,
1098 + id->idProduct,
1099 + id->bDeviceClass,
1100 + id->bDeviceSubClass,
1101 + id->bDeviceProtocol);
1102 +#endif
1103
1104 - /* add other match criteria here ... */
1105 + if ((id->match_flags & USB_DEVICE_ID_MATCH_VENDOR) &&
1106 + id->idVendor != le16_to_cpu(dev->descriptor.idVendor))
1107 + continue;
1108 +
1109 + if ((id->match_flags & USB_DEVICE_ID_MATCH_PRODUCT) &&
1110 + id->idProduct != le16_to_cpu(dev->descriptor.idProduct))
1111 + continue;
1112 +
1113 + /* No need to test id->bcdDevice_lo != 0, since 0 is never
1114 + greater than any unsigned number. */
1115 + if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_LO) &&
1116 + (id->bcdDevice_lo > le16_to_cpu(dev->descriptor.bcdDevice)))
1117 + continue;
1118 +
1119 + if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_HI) &&
1120 + (id->bcdDevice_hi < le16_to_cpu(dev->descriptor.bcdDevice)))
1121 + continue;
1122 +
1123 + if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_CLASS) &&
1124 + (id->bDeviceClass != dev->descriptor.bDeviceClass))
1125 + continue;
1126 +
1127 + if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_SUBCLASS) &&
1128 + (id->bDeviceSubClass != dev->descriptor.bDeviceSubClass))
1129 + continue;
1130 +
1131 + if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_PROTOCOL) &&
1132 + (id->bDeviceProtocol != dev->descriptor.bDeviceProtocol))
1133 + continue;
1134
1135 + return 1;
1136 + }
1137 + }
1138
1139 - /* OTG MESSAGE: report errors here, customize to match your product */
1140 - dev_err(&dev->dev, "device v%04x p%04x is not supported\n",
1141 - le16_to_cpu(dev->descriptor.idVendor),
1142 - le16_to_cpu(dev->descriptor.idProduct));
1143 + /* add other match criteria here ... */
1144
1145 + report_errors(dev);
1146 return 0;
1147 }
1148
1149 --- /dev/null
1150 +++ b/drivers/usb/gadget/file_storage.c
1151 @@ -0,0 +1,3676 @@
1152 +/*
1153 + * file_storage.c -- File-backed USB Storage Gadget, for USB development
1154 + *
1155 + * Copyright (C) 2003-2008 Alan Stern
1156 + * All rights reserved.
1157 + *
1158 + * Redistribution and use in source and binary forms, with or without
1159 + * modification, are permitted provided that the following conditions
1160 + * are met:
1161 + * 1. Redistributions of source code must retain the above copyright
1162 + * notice, this list of conditions, and the following disclaimer,
1163 + * without modification.
1164 + * 2. Redistributions in binary form must reproduce the above copyright
1165 + * notice, this list of conditions and the following disclaimer in the
1166 + * documentation and/or other materials provided with the distribution.
1167 + * 3. The names of the above-listed copyright holders may not be used
1168 + * to endorse or promote products derived from this software without
1169 + * specific prior written permission.
1170 + *
1171 + * ALTERNATIVELY, this software may be distributed under the terms of the
1172 + * GNU General Public License ("GPL") as published by the Free Software
1173 + * Foundation, either version 2 of that License or (at your option) any
1174 + * later version.
1175 + *
1176 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
1177 + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
1178 + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
1179 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
1180 + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
1181 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
1182 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
1183 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
1184 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
1185 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
1186 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1187 + */
1188 +
1189 +
1190 +/*
1191 + * The File-backed Storage Gadget acts as a USB Mass Storage device,
1192 + * appearing to the host as a disk drive or as a CD-ROM drive. In addition
1193 + * to providing an example of a genuinely useful gadget driver for a USB
1194 + * device, it also illustrates a technique of double-buffering for increased
1195 + * throughput. Last but not least, it gives an easy way to probe the
1196 + * behavior of the Mass Storage drivers in a USB host.
1197 + *
1198 + * Backing storage is provided by a regular file or a block device, specified
1199 + * by the "file" module parameter. Access can be limited to read-only by
1200 + * setting the optional "ro" module parameter. (For CD-ROM emulation,
1201 + * access is always read-only.) The gadget will indicate that it has
1202 + * removable media if the optional "removable" module parameter is set.
1203 + *
1204 + * The gadget supports the Control-Bulk (CB), Control-Bulk-Interrupt (CBI),
1205 + * and Bulk-Only (also known as Bulk-Bulk-Bulk or BBB) transports, selected
1206 + * by the optional "transport" module parameter. It also supports the
1207 + * following protocols: RBC (0x01), ATAPI or SFF-8020i (0x02), QIC-157 (0c03),
1208 + * UFI (0x04), SFF-8070i (0x05), and transparent SCSI (0x06), selected by
1209 + * the optional "protocol" module parameter. In addition, the default
1210 + * Vendor ID, Product ID, release number and serial number can be overridden.
1211 + *
1212 + * There is support for multiple logical units (LUNs), each of which has
1213 + * its own backing file. The number of LUNs can be set using the optional
1214 + * "luns" module parameter (anywhere from 1 to 8), and the corresponding
1215 + * files are specified using comma-separated lists for "file" and "ro".
1216 + * The default number of LUNs is taken from the number of "file" elements;
1217 + * it is 1 if "file" is not given. If "removable" is not set then a backing
1218 + * file must be specified for each LUN. If it is set, then an unspecified
1219 + * or empty backing filename means the LUN's medium is not loaded. Ideally
1220 + * each LUN would be settable independently as a disk drive or a CD-ROM
1221 + * drive, but currently all LUNs have to be the same type. The CD-ROM
1222 + * emulation includes a single data track and no audio tracks; hence there
1223 + * need be only one backing file per LUN.
1224 + *
1225 + * Requirements are modest; only a bulk-in and a bulk-out endpoint are
1226 + * needed (an interrupt-out endpoint is also needed for CBI). The memory
1227 + * requirement amounts to two 16K buffers, size configurable by a parameter.
1228 + * Support is included for both full-speed and high-speed operation.
1229 + *
1230 + * Note that the driver is slightly non-portable in that it assumes a
1231 + * single memory/DMA buffer will be useable for bulk-in, bulk-out, and
1232 + * interrupt-in endpoints. With most device controllers this isn't an
1233 + * issue, but there may be some with hardware restrictions that prevent
1234 + * a buffer from being used by more than one endpoint.
1235 + *
1236 + * Module options:
1237 + *
1238 + * file=filename[,filename...]
1239 + * Required if "removable" is not set, names of
1240 + * the files or block devices used for
1241 + * backing storage
1242 + * serial=HHHH... Required serial number (string of hex chars)
1243 + * ro=b[,b...] Default false, booleans for read-only access
1244 + * removable Default false, boolean for removable media
1245 + * luns=N Default N = number of filenames, number of
1246 + * LUNs to support
1247 + * nofua=b[,b...] Default false, booleans for ignore FUA flag
1248 + * in SCSI WRITE(10,12) commands
1249 + * stall Default determined according to the type of
1250 + * USB device controller (usually true),
1251 + * boolean to permit the driver to halt
1252 + * bulk endpoints
1253 + * cdrom Default false, boolean for whether to emulate
1254 + * a CD-ROM drive
1255 + * transport=XXX Default BBB, transport name (CB, CBI, or BBB)
1256 + * protocol=YYY Default SCSI, protocol name (RBC, 8020 or
1257 + * ATAPI, QIC, UFI, 8070, or SCSI;
1258 + * also 1 - 6)
1259 + * vendor=0xVVVV Default 0x0525 (NetChip), USB Vendor ID
1260 + * product=0xPPPP Default 0xa4a5 (FSG), USB Product ID
1261 + * release=0xRRRR Override the USB release number (bcdDevice)
1262 + * buflen=N Default N=16384, buffer size used (will be
1263 + * rounded down to a multiple of
1264 + * PAGE_CACHE_SIZE)
1265 + *
1266 + * If CONFIG_USB_FILE_STORAGE_TEST is not set, only the "file", "serial", "ro",
1267 + * "removable", "luns", "nofua", "stall", and "cdrom" options are available;
1268 + * default values are used for everything else.
1269 + *
1270 + * The pathnames of the backing files and the ro settings are available in
1271 + * the attribute files "file", "nofua", and "ro" in the lun<n> subdirectory of
1272 + * the gadget's sysfs directory. If the "removable" option is set, writing to
1273 + * these files will simulate ejecting/loading the medium (writing an empty
1274 + * line means eject) and adjusting a write-enable tab. Changes to the ro
1275 + * setting are not allowed when the medium is loaded or if CD-ROM emulation
1276 + * is being used.
1277 + *
1278 + * This gadget driver is heavily based on "Gadget Zero" by David Brownell.
1279 + * The driver's SCSI command interface was based on the "Information
1280 + * technology - Small Computer System Interface - 2" document from
1281 + * X3T9.2 Project 375D, Revision 10L, 7-SEP-93, available at
1282 + * <http://www.t10.org/ftp/t10/drafts/s2/s2-r10l.pdf>. The single exception
1283 + * is opcode 0x23 (READ FORMAT CAPACITIES), which was based on the
1284 + * "Universal Serial Bus Mass Storage Class UFI Command Specification"
1285 + * document, Revision 1.0, December 14, 1998, available at
1286 + * <http://www.usb.org/developers/devclass_docs/usbmass-ufi10.pdf>.
1287 + */
1288 +
1289 +
1290 +/*
1291 + * Driver Design
1292 + *
1293 + * The FSG driver is fairly straightforward. There is a main kernel
1294 + * thread that handles most of the work. Interrupt routines field
1295 + * callbacks from the controller driver: bulk- and interrupt-request
1296 + * completion notifications, endpoint-0 events, and disconnect events.
1297 + * Completion events are passed to the main thread by wakeup calls. Many
1298 + * ep0 requests are handled at interrupt time, but SetInterface,
1299 + * SetConfiguration, and device reset requests are forwarded to the
1300 + * thread in the form of "exceptions" using SIGUSR1 signals (since they
1301 + * should interrupt any ongoing file I/O operations).
1302 + *
1303 + * The thread's main routine implements the standard command/data/status
1304 + * parts of a SCSI interaction. It and its subroutines are full of tests
1305 + * for pending signals/exceptions -- all this polling is necessary since
1306 + * the kernel has no setjmp/longjmp equivalents. (Maybe this is an
1307 + * indication that the driver really wants to be running in userspace.)
1308 + * An important point is that so long as the thread is alive it keeps an
1309 + * open reference to the backing file. This will prevent unmounting
1310 + * the backing file's underlying filesystem and could cause problems
1311 + * during system shutdown, for example. To prevent such problems, the
1312 + * thread catches INT, TERM, and KILL signals and converts them into
1313 + * an EXIT exception.
1314 + *
1315 + * In normal operation the main thread is started during the gadget's
1316 + * fsg_bind() callback and stopped during fsg_unbind(). But it can also
1317 + * exit when it receives a signal, and there's no point leaving the
1318 + * gadget running when the thread is dead. So just before the thread
1319 + * exits, it deregisters the gadget driver. This makes things a little
1320 + * tricky: The driver is deregistered at two places, and the exiting
1321 + * thread can indirectly call fsg_unbind() which in turn can tell the
1322 + * thread to exit. The first problem is resolved through the use of the
1323 + * REGISTERED atomic bitflag; the driver will only be deregistered once.
1324 + * The second problem is resolved by having fsg_unbind() check
1325 + * fsg->state; it won't try to stop the thread if the state is already
1326 + * FSG_STATE_TERMINATED.
1327 + *
1328 + * To provide maximum throughput, the driver uses a circular pipeline of
1329 + * buffer heads (struct fsg_buffhd). In principle the pipeline can be
1330 + * arbitrarily long; in practice the benefits don't justify having more
1331 + * than 2 stages (i.e., double buffering). But it helps to think of the
1332 + * pipeline as being a long one. Each buffer head contains a bulk-in and
1333 + * a bulk-out request pointer (since the buffer can be used for both
1334 + * output and input -- directions always are given from the host's
1335 + * point of view) as well as a pointer to the buffer and various state
1336 + * variables.
1337 + *
1338 + * Use of the pipeline follows a simple protocol. There is a variable
1339 + * (fsg->next_buffhd_to_fill) that points to the next buffer head to use.
1340 + * At any time that buffer head may still be in use from an earlier
1341 + * request, so each buffer head has a state variable indicating whether
1342 + * it is EMPTY, FULL, or BUSY. Typical use involves waiting for the
1343 + * buffer head to be EMPTY, filling the buffer either by file I/O or by
1344 + * USB I/O (during which the buffer head is BUSY), and marking the buffer
1345 + * head FULL when the I/O is complete. Then the buffer will be emptied
1346 + * (again possibly by USB I/O, during which it is marked BUSY) and
1347 + * finally marked EMPTY again (possibly by a completion routine).
1348 + *
1349 + * A module parameter tells the driver to avoid stalling the bulk
1350 + * endpoints wherever the transport specification allows. This is
1351 + * necessary for some UDCs like the SuperH, which cannot reliably clear a
1352 + * halt on a bulk endpoint. However, under certain circumstances the
1353 + * Bulk-only specification requires a stall. In such cases the driver
1354 + * will halt the endpoint and set a flag indicating that it should clear
1355 + * the halt in software during the next device reset. Hopefully this
1356 + * will permit everything to work correctly. Furthermore, although the
1357 + * specification allows the bulk-out endpoint to halt when the host sends
1358 + * too much data, implementing this would cause an unavoidable race.
1359 + * The driver will always use the "no-stall" approach for OUT transfers.
1360 + *
1361 + * One subtle point concerns sending status-stage responses for ep0
1362 + * requests. Some of these requests, such as device reset, can involve
1363 + * interrupting an ongoing file I/O operation, which might take an
1364 + * arbitrarily long time. During that delay the host might give up on
1365 + * the original ep0 request and issue a new one. When that happens the
1366 + * driver should not notify the host about completion of the original
1367 + * request, as the host will no longer be waiting for it. So the driver
1368 + * assigns to each ep0 request a unique tag, and it keeps track of the
1369 + * tag value of the request associated with a long-running exception
1370 + * (device-reset, interface-change, or configuration-change). When the
1371 + * exception handler is finished, the status-stage response is submitted
1372 + * only if the current ep0 request tag is equal to the exception request
1373 + * tag. Thus only the most recently received ep0 request will get a
1374 + * status-stage response.
1375 + *
1376 + * Warning: This driver source file is too long. It ought to be split up
1377 + * into a header file plus about 3 separate .c files, to handle the details
1378 + * of the Gadget, USB Mass Storage, and SCSI protocols.
1379 + */
1380 +
1381 +
1382 +/* #define VERBOSE_DEBUG */
1383 +/* #define DUMP_MSGS */
1384 +
1385 +
1386 +#include <linux/blkdev.h>
1387 +#include <linux/completion.h>
1388 +#include <linux/dcache.h>
1389 +#include <linux/delay.h>
1390 +#include <linux/device.h>
1391 +#include <linux/fcntl.h>
1392 +#include <linux/file.h>
1393 +#include <linux/fs.h>
1394 +#include <linux/kref.h>
1395 +#include <linux/kthread.h>
1396 +#include <linux/limits.h>
1397 +#include <linux/module.h>
1398 +#include <linux/rwsem.h>
1399 +#include <linux/slab.h>
1400 +#include <linux/spinlock.h>
1401 +#include <linux/string.h>
1402 +#include <linux/freezer.h>
1403 +#include <linux/utsname.h>
1404 +
1405 +#include <linux/usb/ch9.h>
1406 +#include <linux/usb/gadget.h>
1407 +
1408 +#include "gadget_chips.h"
1409 +
1410 +
1411 +
1412 +/*
1413 + * Kbuild is not very cooperative with respect to linking separately
1414 + * compiled library objects into one module. So for now we won't use
1415 + * separate compilation ... ensuring init/exit sections work to shrink
1416 + * the runtime footprint, and giving us at least some parts of what
1417 + * a "gcc --combine ... part1.c part2.c part3.c ... " build would.
1418 + */
1419 +#include "usbstring.c"
1420 +#include "config.c"
1421 +#include "epautoconf.c"
1422 +
1423 +/*-------------------------------------------------------------------------*/
1424 +
1425 +#define DRIVER_DESC "File-backed Storage Gadget"
1426 +#define DRIVER_NAME "g_file_storage"
1427 +#define DRIVER_VERSION "1 September 2010"
1428 +
1429 +static char fsg_string_manufacturer[64];
1430 +static const char fsg_string_product[] = DRIVER_DESC;
1431 +static const char fsg_string_config[] = "Self-powered";
1432 +static const char fsg_string_interface[] = "Mass Storage";
1433 +
1434 +
1435 +#include "storage_common.c"
1436 +
1437 +
1438 +MODULE_DESCRIPTION(DRIVER_DESC);
1439 +MODULE_AUTHOR("Alan Stern");
1440 +MODULE_LICENSE("Dual BSD/GPL");
1441 +
1442 +/*
1443 + * This driver assumes self-powered hardware and has no way for users to
1444 + * trigger remote wakeup. It uses autoconfiguration to select endpoints
1445 + * and endpoint addresses.
1446 + */
1447 +
1448 +
1449 +/*-------------------------------------------------------------------------*/
1450 +
1451 +
1452 +/* Encapsulate the module parameter settings */
1453 +
1454 +static struct {
1455 + char *file[FSG_MAX_LUNS];
1456 + char *serial;
1457 + bool ro[FSG_MAX_LUNS];
1458 + bool nofua[FSG_MAX_LUNS];
1459 + unsigned int num_filenames;
1460 + unsigned int num_ros;
1461 + unsigned int num_nofuas;
1462 + unsigned int nluns;
1463 +
1464 + bool removable;
1465 + bool can_stall;
1466 + bool cdrom;
1467 +
1468 + char *transport_parm;
1469 + char *protocol_parm;
1470 + unsigned short vendor;
1471 + unsigned short product;
1472 + unsigned short release;
1473 + unsigned int buflen;
1474 +
1475 + int transport_type;
1476 + char *transport_name;
1477 + int protocol_type;
1478 + char *protocol_name;
1479 +
1480 +} mod_data = { // Default values
1481 + .transport_parm = "BBB",
1482 + .protocol_parm = "SCSI",
1483 + .removable = 0,
1484 + .can_stall = 1,
1485 + .cdrom = 0,
1486 + .vendor = FSG_VENDOR_ID,
1487 + .product = FSG_PRODUCT_ID,
1488 + .release = 0xffff, // Use controller chip type
1489 + .buflen = 16384,
1490 + };
1491 +
1492 +
1493 +module_param_array_named(file, mod_data.file, charp, &mod_data.num_filenames,
1494 + S_IRUGO);
1495 +MODULE_PARM_DESC(file, "names of backing files or devices");
1496 +
1497 +module_param_named(serial, mod_data.serial, charp, S_IRUGO);
1498 +MODULE_PARM_DESC(serial, "USB serial number");
1499 +
1500 +module_param_array_named(ro, mod_data.ro, bool, &mod_data.num_ros, S_IRUGO);
1501 +MODULE_PARM_DESC(ro, "true to force read-only");
1502 +
1503 +module_param_array_named(nofua, mod_data.nofua, bool, &mod_data.num_nofuas,
1504 + S_IRUGO);
1505 +MODULE_PARM_DESC(nofua, "true to ignore SCSI WRITE(10,12) FUA bit");
1506 +
1507 +module_param_named(luns, mod_data.nluns, uint, S_IRUGO);
1508 +MODULE_PARM_DESC(luns, "number of LUNs");
1509 +
1510 +module_param_named(removable, mod_data.removable, bool, S_IRUGO);
1511 +MODULE_PARM_DESC(removable, "true to simulate removable media");
1512 +
1513 +module_param_named(stall, mod_data.can_stall, bool, S_IRUGO);
1514 +MODULE_PARM_DESC(stall, "false to prevent bulk stalls");
1515 +
1516 +module_param_named(cdrom, mod_data.cdrom, bool, S_IRUGO);
1517 +MODULE_PARM_DESC(cdrom, "true to emulate cdrom instead of disk");
1518 +
1519 +/* In the non-TEST version, only the module parameters listed above
1520 + * are available. */
1521 +#ifdef CONFIG_USB_FILE_STORAGE_TEST
1522 +
1523 +module_param_named(transport, mod_data.transport_parm, charp, S_IRUGO);
1524 +MODULE_PARM_DESC(transport, "type of transport (BBB, CBI, or CB)");
1525 +
1526 +module_param_named(protocol, mod_data.protocol_parm, charp, S_IRUGO);
1527 +MODULE_PARM_DESC(protocol, "type of protocol (RBC, 8020, QIC, UFI, "
1528 + "8070, or SCSI)");
1529 +
1530 +module_param_named(vendor, mod_data.vendor, ushort, S_IRUGO);
1531 +MODULE_PARM_DESC(vendor, "USB Vendor ID");
1532 +
1533 +module_param_named(product, mod_data.product, ushort, S_IRUGO);
1534 +MODULE_PARM_DESC(product, "USB Product ID");
1535 +
1536 +module_param_named(release, mod_data.release, ushort, S_IRUGO);
1537 +MODULE_PARM_DESC(release, "USB release number");
1538 +
1539 +module_param_named(buflen, mod_data.buflen, uint, S_IRUGO);
1540 +MODULE_PARM_DESC(buflen, "I/O buffer size");
1541 +
1542 +#endif /* CONFIG_USB_FILE_STORAGE_TEST */
1543 +
1544 +
1545 +/*
1546 + * These definitions will permit the compiler to avoid generating code for
1547 + * parts of the driver that aren't used in the non-TEST version. Even gcc
1548 + * can recognize when a test of a constant expression yields a dead code
1549 + * path.
1550 + */
1551 +
1552 +#ifdef CONFIG_USB_FILE_STORAGE_TEST
1553 +
1554 +#define transport_is_bbb() (mod_data.transport_type == USB_PR_BULK)
1555 +#define transport_is_cbi() (mod_data.transport_type == USB_PR_CBI)
1556 +#define protocol_is_scsi() (mod_data.protocol_type == USB_SC_SCSI)
1557 +
1558 +#else
1559 +
1560 +#define transport_is_bbb() 1
1561 +#define transport_is_cbi() 0
1562 +#define protocol_is_scsi() 1
1563 +
1564 +#endif /* CONFIG_USB_FILE_STORAGE_TEST */
1565 +
1566 +
1567 +/*-------------------------------------------------------------------------*/
1568 +
1569 +
1570 +struct fsg_dev {
1571 + /* lock protects: state, all the req_busy's, and cbbuf_cmnd */
1572 + spinlock_t lock;
1573 + struct usb_gadget *gadget;
1574 +
1575 + /* filesem protects: backing files in use */
1576 + struct rw_semaphore filesem;
1577 +
1578 + /* reference counting: wait until all LUNs are released */
1579 + struct kref ref;
1580 +
1581 + struct usb_ep *ep0; // Handy copy of gadget->ep0
1582 + struct usb_request *ep0req; // For control responses
1583 + unsigned int ep0_req_tag;
1584 + const char *ep0req_name;
1585 +
1586 + struct usb_request *intreq; // For interrupt responses
1587 + int intreq_busy;
1588 + struct fsg_buffhd *intr_buffhd;
1589 +
1590 + unsigned int bulk_out_maxpacket;
1591 + enum fsg_state state; // For exception handling
1592 + unsigned int exception_req_tag;
1593 +
1594 + u8 config, new_config;
1595 +
1596 + unsigned int running : 1;
1597 + unsigned int bulk_in_enabled : 1;
1598 + unsigned int bulk_out_enabled : 1;
1599 + unsigned int intr_in_enabled : 1;
1600 + unsigned int phase_error : 1;
1601 + unsigned int short_packet_received : 1;
1602 + unsigned int bad_lun_okay : 1;
1603 +
1604 + unsigned long atomic_bitflags;
1605 +#define REGISTERED 0
1606 +#define IGNORE_BULK_OUT 1
1607 +#define SUSPENDED 2
1608 +
1609 + struct usb_ep *bulk_in;
1610 + struct usb_ep *bulk_out;
1611 + struct usb_ep *intr_in;
1612 +
1613 + struct fsg_buffhd *next_buffhd_to_fill;
1614 + struct fsg_buffhd *next_buffhd_to_drain;
1615 +
1616 + int thread_wakeup_needed;
1617 + struct completion thread_notifier;
1618 + struct task_struct *thread_task;
1619 +
1620 + int cmnd_size;
1621 + u8 cmnd[MAX_COMMAND_SIZE];
1622 + enum data_direction data_dir;
1623 + u32 data_size;
1624 + u32 data_size_from_cmnd;
1625 + u32 tag;
1626 + unsigned int lun;
1627 + u32 residue;
1628 + u32 usb_amount_left;
1629 +
1630 + /* The CB protocol offers no way for a host to know when a command
1631 + * has completed. As a result the next command may arrive early,
1632 + * and we will still have to handle it. For that reason we need
1633 + * a buffer to store new commands when using CB (or CBI, which
1634 + * does not oblige a host to wait for command completion either). */
1635 + int cbbuf_cmnd_size;
1636 + u8 cbbuf_cmnd[MAX_COMMAND_SIZE];
1637 +
1638 + unsigned int nluns;
1639 + struct fsg_lun *luns;
1640 + struct fsg_lun *curlun;
1641 + /* Must be the last entry */
1642 + struct fsg_buffhd buffhds[];
1643 +};
1644 +
1645 +typedef void (*fsg_routine_t)(struct fsg_dev *);
1646 +
1647 +static int exception_in_progress(struct fsg_dev *fsg)
1648 +{
1649 + return (fsg->state > FSG_STATE_IDLE);
1650 +}
1651 +
1652 +/* Make bulk-out requests be divisible by the maxpacket size */
1653 +static void set_bulk_out_req_length(struct fsg_dev *fsg,
1654 + struct fsg_buffhd *bh, unsigned int length)
1655 +{
1656 + unsigned int rem;
1657 +
1658 + bh->bulk_out_intended_length = length;
1659 + rem = length % fsg->bulk_out_maxpacket;
1660 + if (rem > 0)
1661 + length += fsg->bulk_out_maxpacket - rem;
1662 + bh->outreq->length = length;
1663 +}
1664 +
1665 +static struct fsg_dev *the_fsg;
1666 +static struct usb_gadget_driver fsg_driver;
1667 +
1668 +
1669 +/*-------------------------------------------------------------------------*/
1670 +
1671 +static int fsg_set_halt(struct fsg_dev *fsg, struct usb_ep *ep)
1672 +{
1673 + const char *name;
1674 +
1675 + if (ep == fsg->bulk_in)
1676 + name = "bulk-in";
1677 + else if (ep == fsg->bulk_out)
1678 + name = "bulk-out";
1679 + else
1680 + name = ep->name;
1681 + DBG(fsg, "%s set halt\n", name);
1682 + return usb_ep_set_halt(ep);
1683 +}
1684 +
1685 +
1686 +/*-------------------------------------------------------------------------*/
1687 +
1688 +/*
1689 + * DESCRIPTORS ... most are static, but strings and (full) configuration
1690 + * descriptors are built on demand. Also the (static) config and interface
1691 + * descriptors are adjusted during fsg_bind().
1692 + */
1693 +
1694 +/* There is only one configuration. */
1695 +#define CONFIG_VALUE 1
1696 +
1697 +static struct usb_device_descriptor
1698 +device_desc = {
1699 + .bLength = sizeof device_desc,
1700 + .bDescriptorType = USB_DT_DEVICE,
1701 +
1702 + .bcdUSB = cpu_to_le16(0x0200),
1703 + .bDeviceClass = USB_CLASS_PER_INTERFACE,
1704 +
1705 + /* The next three values can be overridden by module parameters */
1706 + .idVendor = cpu_to_le16(FSG_VENDOR_ID),
1707 + .idProduct = cpu_to_le16(FSG_PRODUCT_ID),
1708 + .bcdDevice = cpu_to_le16(0xffff),
1709 +
1710 + .iManufacturer = FSG_STRING_MANUFACTURER,
1711 + .iProduct = FSG_STRING_PRODUCT,
1712 + .iSerialNumber = FSG_STRING_SERIAL,
1713 + .bNumConfigurations = 1,
1714 +};
1715 +
1716 +static struct usb_config_descriptor
1717 +config_desc = {
1718 + .bLength = sizeof config_desc,
1719 + .bDescriptorType = USB_DT_CONFIG,
1720 +
1721 + /* wTotalLength computed by usb_gadget_config_buf() */
1722 + .bNumInterfaces = 1,
1723 + .bConfigurationValue = CONFIG_VALUE,
1724 + .iConfiguration = FSG_STRING_CONFIG,
1725 + .bmAttributes = USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER,
1726 + .bMaxPower = CONFIG_USB_GADGET_VBUS_DRAW / 2,
1727 +};
1728 +
1729 +
1730 +static struct usb_qualifier_descriptor
1731 +dev_qualifier = {
1732 + .bLength = sizeof dev_qualifier,
1733 + .bDescriptorType = USB_DT_DEVICE_QUALIFIER,
1734 +
1735 + .bcdUSB = cpu_to_le16(0x0200),
1736 + .bDeviceClass = USB_CLASS_PER_INTERFACE,
1737 +
1738 + .bNumConfigurations = 1,
1739 +};
1740 +
1741 +static int populate_bos(struct fsg_dev *fsg, u8 *buf)
1742 +{
1743 + memcpy(buf, &fsg_bos_desc, USB_DT_BOS_SIZE);
1744 + buf += USB_DT_BOS_SIZE;
1745 +
1746 + memcpy(buf, &fsg_ext_cap_desc, USB_DT_USB_EXT_CAP_SIZE);
1747 + buf += USB_DT_USB_EXT_CAP_SIZE;
1748 +
1749 + memcpy(buf, &fsg_ss_cap_desc, USB_DT_USB_SS_CAP_SIZE);
1750 +
1751 + return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE
1752 + + USB_DT_USB_EXT_CAP_SIZE;
1753 +}
1754 +
1755 +/*
1756 + * Config descriptors must agree with the code that sets configurations
1757 + * and with code managing interfaces and their altsettings. They must
1758 + * also handle different speeds and other-speed requests.
1759 + */
1760 +static int populate_config_buf(struct usb_gadget *gadget,
1761 + u8 *buf, u8 type, unsigned index)
1762 +{
1763 + enum usb_device_speed speed = gadget->speed;
1764 + int len;
1765 + const struct usb_descriptor_header **function;
1766 +
1767 + if (index > 0)
1768 + return -EINVAL;
1769 +
1770 + if (gadget_is_dualspeed(gadget) && type == USB_DT_OTHER_SPEED_CONFIG)
1771 + speed = (USB_SPEED_FULL + USB_SPEED_HIGH) - speed;
1772 + function = gadget_is_dualspeed(gadget) && speed == USB_SPEED_HIGH
1773 + ? (const struct usb_descriptor_header **)fsg_hs_function
1774 + : (const struct usb_descriptor_header **)fsg_fs_function;
1775 +
1776 + /* for now, don't advertise srp-only devices */
1777 + if (!gadget_is_otg(gadget))
1778 + function++;
1779 +
1780 + len = usb_gadget_config_buf(&config_desc, buf, EP0_BUFSIZE, function);
1781 + ((struct usb_config_descriptor *) buf)->bDescriptorType = type;
1782 + return len;
1783 +}
1784 +
1785 +
1786 +/*-------------------------------------------------------------------------*/
1787 +
1788 +/* These routines may be called in process context or in_irq */
1789 +
1790 +/* Caller must hold fsg->lock */
1791 +static void wakeup_thread(struct fsg_dev *fsg)
1792 +{
1793 + /* Tell the main thread that something has happened */
1794 + fsg->thread_wakeup_needed = 1;
1795 + if (fsg->thread_task)
1796 + wake_up_process(fsg->thread_task);
1797 +}
1798 +
1799 +
1800 +static void raise_exception(struct fsg_dev *fsg, enum fsg_state new_state)
1801 +{
1802 + unsigned long flags;
1803 +
1804 + /* Do nothing if a higher-priority exception is already in progress.
1805 + * If a lower-or-equal priority exception is in progress, preempt it
1806 + * and notify the main thread by sending it a signal. */
1807 + spin_lock_irqsave(&fsg->lock, flags);
1808 + if (fsg->state <= new_state) {
1809 + fsg->exception_req_tag = fsg->ep0_req_tag;
1810 + fsg->state = new_state;
1811 + if (fsg->thread_task)
1812 + send_sig_info(SIGUSR1, SEND_SIG_FORCED,
1813 + fsg->thread_task);
1814 + }
1815 + spin_unlock_irqrestore(&fsg->lock, flags);
1816 +}
1817 +
1818 +
1819 +/*-------------------------------------------------------------------------*/
1820 +
1821 +/* The disconnect callback and ep0 routines. These always run in_irq,
1822 + * except that ep0_queue() is called in the main thread to acknowledge
1823 + * completion of various requests: set config, set interface, and
1824 + * Bulk-only device reset. */
1825 +
1826 +static void fsg_disconnect(struct usb_gadget *gadget)
1827 +{
1828 + struct fsg_dev *fsg = get_gadget_data(gadget);
1829 +
1830 + DBG(fsg, "disconnect or port reset\n");
1831 + raise_exception(fsg, FSG_STATE_DISCONNECT);
1832 +}
1833 +
1834 +
1835 +static int ep0_queue(struct fsg_dev *fsg)
1836 +{
1837 + int rc;
1838 +
1839 + rc = usb_ep_queue(fsg->ep0, fsg->ep0req, GFP_ATOMIC);
1840 + if (rc != 0 && rc != -ESHUTDOWN) {
1841 +
1842 + /* We can't do much more than wait for a reset */
1843 + WARNING(fsg, "error in submission: %s --> %d\n",
1844 + fsg->ep0->name, rc);
1845 + }
1846 + return rc;
1847 +}
1848 +
1849 +static void ep0_complete(struct usb_ep *ep, struct usb_request *req)
1850 +{
1851 + struct fsg_dev *fsg = ep->driver_data;
1852 +
1853 + if (req->actual > 0)
1854 + dump_msg(fsg, fsg->ep0req_name, req->buf, req->actual);
1855 + if (req->status || req->actual != req->length)
1856 + DBG(fsg, "%s --> %d, %u/%u\n", __func__,
1857 + req->status, req->actual, req->length);
1858 + if (req->status == -ECONNRESET) // Request was cancelled
1859 + usb_ep_fifo_flush(ep);
1860 +
1861 + if (req->status == 0 && req->context)
1862 + ((fsg_routine_t) (req->context))(fsg);
1863 +}
1864 +
1865 +
1866 +/*-------------------------------------------------------------------------*/
1867 +
1868 +/* Bulk and interrupt endpoint completion handlers.
1869 + * These always run in_irq. */
1870 +
1871 +static void bulk_in_complete(struct usb_ep *ep, struct usb_request *req)
1872 +{
1873 + struct fsg_dev *fsg = ep->driver_data;
1874 + struct fsg_buffhd *bh = req->context;
1875 +
1876 + if (req->status || req->actual != req->length)
1877 + DBG(fsg, "%s --> %d, %u/%u\n", __func__,
1878 + req->status, req->actual, req->length);
1879 + if (req->status == -ECONNRESET) // Request was cancelled
1880 + usb_ep_fifo_flush(ep);
1881 +
1882 + /* Hold the lock while we update the request and buffer states */
1883 + smp_wmb();
1884 + spin_lock(&fsg->lock);
1885 + bh->inreq_busy = 0;
1886 + bh->state = BUF_STATE_EMPTY;
1887 + wakeup_thread(fsg);
1888 + spin_unlock(&fsg->lock);
1889 +}
1890 +
1891 +static void bulk_out_complete(struct usb_ep *ep, struct usb_request *req)
1892 +{
1893 + struct fsg_dev *fsg = ep->driver_data;
1894 + struct fsg_buffhd *bh = req->context;
1895 +
1896 + dump_msg(fsg, "bulk-out", req->buf, req->actual);
1897 + if (req->status || req->actual != bh->bulk_out_intended_length)
1898 + DBG(fsg, "%s --> %d, %u/%u\n", __func__,
1899 + req->status, req->actual,
1900 + bh->bulk_out_intended_length);
1901 + if (req->status == -ECONNRESET) // Request was cancelled
1902 + usb_ep_fifo_flush(ep);
1903 +
1904 + /* Hold the lock while we update the request and buffer states */
1905 + smp_wmb();
1906 + spin_lock(&fsg->lock);
1907 + bh->outreq_busy = 0;
1908 + bh->state = BUF_STATE_FULL;
1909 + wakeup_thread(fsg);
1910 + spin_unlock(&fsg->lock);
1911 +}
1912 +
1913 +
1914 +#ifdef CONFIG_USB_FILE_STORAGE_TEST
1915 +static void intr_in_complete(struct usb_ep *ep, struct usb_request *req)
1916 +{
1917 + struct fsg_dev *fsg = ep->driver_data;
1918 + struct fsg_buffhd *bh = req->context;
1919 +
1920 + if (req->status || req->actual != req->length)
1921 + DBG(fsg, "%s --> %d, %u/%u\n", __func__,
1922 + req->status, req->actual, req->length);
1923 + if (req->status == -ECONNRESET) // Request was cancelled
1924 + usb_ep_fifo_flush(ep);
1925 +
1926 + /* Hold the lock while we update the request and buffer states */
1927 + smp_wmb();
1928 + spin_lock(&fsg->lock);
1929 + fsg->intreq_busy = 0;
1930 + bh->state = BUF_STATE_EMPTY;
1931 + wakeup_thread(fsg);
1932 + spin_unlock(&fsg->lock);
1933 +}
1934 +
1935 +#else
1936 +static void intr_in_complete(struct usb_ep *ep, struct usb_request *req)
1937 +{}
1938 +#endif /* CONFIG_USB_FILE_STORAGE_TEST */
1939 +
1940 +
1941 +/*-------------------------------------------------------------------------*/
1942 +
1943 +/* Ep0 class-specific handlers. These always run in_irq. */
1944 +
1945 +#ifdef CONFIG_USB_FILE_STORAGE_TEST
1946 +static void received_cbi_adsc(struct fsg_dev *fsg, struct fsg_buffhd *bh)
1947 +{
1948 + struct usb_request *req = fsg->ep0req;
1949 + static u8 cbi_reset_cmnd[6] = {
1950 + SEND_DIAGNOSTIC, 4, 0xff, 0xff, 0xff, 0xff};
1951 +
1952 + /* Error in command transfer? */
1953 + if (req->status || req->length != req->actual ||
1954 + req->actual < 6 || req->actual > MAX_COMMAND_SIZE) {
1955 +
1956 + /* Not all controllers allow a protocol stall after
1957 + * receiving control-out data, but we'll try anyway. */
1958 + fsg_set_halt(fsg, fsg->ep0);
1959 + return; // Wait for reset
1960 + }
1961 +
1962 + /* Is it the special reset command? */
1963 + if (req->actual >= sizeof cbi_reset_cmnd &&
1964 + memcmp(req->buf, cbi_reset_cmnd,
1965 + sizeof cbi_reset_cmnd) == 0) {
1966 +
1967 + /* Raise an exception to stop the current operation
1968 + * and reinitialize our state. */
1969 + DBG(fsg, "cbi reset request\n");
1970 + raise_exception(fsg, FSG_STATE_RESET);
1971 + return;
1972 + }
1973 +
1974 + VDBG(fsg, "CB[I] accept device-specific command\n");
1975 + spin_lock(&fsg->lock);
1976 +
1977 + /* Save the command for later */
1978 + if (fsg->cbbuf_cmnd_size)
1979 + WARNING(fsg, "CB[I] overwriting previous command\n");
1980 + fsg->cbbuf_cmnd_size = req->actual;
1981 + memcpy(fsg->cbbuf_cmnd, req->buf, fsg->cbbuf_cmnd_size);
1982 +
1983 + wakeup_thread(fsg);
1984 + spin_unlock(&fsg->lock);
1985 +}
1986 +
1987 +#else
1988 +static void received_cbi_adsc(struct fsg_dev *fsg, struct fsg_buffhd *bh)
1989 +{}
1990 +#endif /* CONFIG_USB_FILE_STORAGE_TEST */
1991 +
1992 +
1993 +static int class_setup_req(struct fsg_dev *fsg,
1994 + const struct usb_ctrlrequest *ctrl)
1995 +{
1996 + struct usb_request *req = fsg->ep0req;
1997 + int value = -EOPNOTSUPP;
1998 + u16 w_index = le16_to_cpu(ctrl->wIndex);
1999 + u16 w_value = le16_to_cpu(ctrl->wValue);
2000 + u16 w_length = le16_to_cpu(ctrl->wLength);
2001 +
2002 + if (!fsg->config)
2003 + return value;
2004 +
2005 + /* Handle Bulk-only class-specific requests */
2006 + if (transport_is_bbb()) {
2007 + switch (ctrl->bRequest) {
2008 +
2009 + case US_BULK_RESET_REQUEST:
2010 + if (ctrl->bRequestType != (USB_DIR_OUT |
2011 + USB_TYPE_CLASS | USB_RECIP_INTERFACE))
2012 + break;
2013 + if (w_index != 0 || w_value != 0 || w_length != 0) {
2014 + value = -EDOM;
2015 + break;
2016 + }
2017 +
2018 + /* Raise an exception to stop the current operation
2019 + * and reinitialize our state. */
2020 + DBG(fsg, "bulk reset request\n");
2021 + raise_exception(fsg, FSG_STATE_RESET);
2022 + value = DELAYED_STATUS;
2023 + break;
2024 +
2025 + case US_BULK_GET_MAX_LUN:
2026 + if (ctrl->bRequestType != (USB_DIR_IN |
2027 + USB_TYPE_CLASS | USB_RECIP_INTERFACE))
2028 + break;
2029 + if (w_index != 0 || w_value != 0 || w_length != 1) {
2030 + value = -EDOM;
2031 + break;
2032 + }
2033 + VDBG(fsg, "get max LUN\n");
2034 + *(u8 *) req->buf = fsg->nluns - 1;
2035 + value = 1;
2036 + break;
2037 + }
2038 + }
2039 +
2040 + /* Handle CBI class-specific requests */
2041 + else {
2042 + switch (ctrl->bRequest) {
2043 +
2044 + case USB_CBI_ADSC_REQUEST:
2045 + if (ctrl->bRequestType != (USB_DIR_OUT |
2046 + USB_TYPE_CLASS | USB_RECIP_INTERFACE))
2047 + break;
2048 + if (w_index != 0 || w_value != 0) {
2049 + value = -EDOM;
2050 + break;
2051 + }
2052 + if (w_length > MAX_COMMAND_SIZE) {
2053 + value = -EOVERFLOW;
2054 + break;
2055 + }
2056 + value = w_length;
2057 + fsg->ep0req->context = received_cbi_adsc;
2058 + break;
2059 + }
2060 + }
2061 +
2062 + if (value == -EOPNOTSUPP)
2063 + VDBG(fsg,
2064 + "unknown class-specific control req "
2065 + "%02x.%02x v%04x i%04x l%u\n",
2066 + ctrl->bRequestType, ctrl->bRequest,
2067 + le16_to_cpu(ctrl->wValue), w_index, w_length);
2068 + return value;
2069 +}
2070 +
2071 +
2072 +/*-------------------------------------------------------------------------*/
2073 +
2074 +/* Ep0 standard request handlers. These always run in_irq. */
2075 +
2076 +static int standard_setup_req(struct fsg_dev *fsg,
2077 + const struct usb_ctrlrequest *ctrl)
2078 +{
2079 + struct usb_request *req = fsg->ep0req;
2080 + int value = -EOPNOTSUPP;
2081 + u16 w_index = le16_to_cpu(ctrl->wIndex);
2082 + u16 w_value = le16_to_cpu(ctrl->wValue);
2083 +
2084 + /* Usually this just stores reply data in the pre-allocated ep0 buffer,
2085 + * but config change events will also reconfigure hardware. */
2086 + switch (ctrl->bRequest) {
2087 +
2088 + case USB_REQ_GET_DESCRIPTOR:
2089 + if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |
2090 + USB_RECIP_DEVICE))
2091 + break;
2092 + switch (w_value >> 8) {
2093 +
2094 + case USB_DT_DEVICE:
2095 + VDBG(fsg, "get device descriptor\n");
2096 + device_desc.bMaxPacketSize0 = fsg->ep0->maxpacket;
2097 + value = sizeof device_desc;
2098 + memcpy(req->buf, &device_desc, value);
2099 + break;
2100 + case USB_DT_DEVICE_QUALIFIER:
2101 + VDBG(fsg, "get device qualifier\n");
2102 + if (!gadget_is_dualspeed(fsg->gadget) ||
2103 + fsg->gadget->speed == USB_SPEED_SUPER)
2104 + break;
2105 + /*
2106 + * Assume ep0 uses the same maxpacket value for both
2107 + * speeds
2108 + */
2109 + dev_qualifier.bMaxPacketSize0 = fsg->ep0->maxpacket;
2110 + value = sizeof dev_qualifier;
2111 + memcpy(req->buf, &dev_qualifier, value);
2112 + break;
2113 +
2114 + case USB_DT_OTHER_SPEED_CONFIG:
2115 + VDBG(fsg, "get other-speed config descriptor\n");
2116 + if (!gadget_is_dualspeed(fsg->gadget) ||
2117 + fsg->gadget->speed == USB_SPEED_SUPER)
2118 + break;
2119 + goto get_config;
2120 + case USB_DT_CONFIG:
2121 + VDBG(fsg, "get configuration descriptor\n");
2122 +get_config:
2123 + value = populate_config_buf(fsg->gadget,
2124 + req->buf,
2125 + w_value >> 8,
2126 + w_value & 0xff);
2127 + break;
2128 +
2129 + case USB_DT_STRING:
2130 + VDBG(fsg, "get string descriptor\n");
2131 +
2132 + /* wIndex == language code */
2133 + value = usb_gadget_get_string(&fsg_stringtab,
2134 + w_value & 0xff, req->buf);
2135 + break;
2136 +
2137 + case USB_DT_BOS:
2138 + VDBG(fsg, "get bos descriptor\n");
2139 +
2140 + if (gadget_is_superspeed(fsg->gadget))
2141 + value = populate_bos(fsg, req->buf);
2142 + break;
2143 + }
2144 +
2145 + break;
2146 +
2147 + /* One config, two speeds */
2148 + case USB_REQ_SET_CONFIGURATION:
2149 + if (ctrl->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD |
2150 + USB_RECIP_DEVICE))
2151 + break;
2152 + VDBG(fsg, "set configuration\n");
2153 + if (w_value == CONFIG_VALUE || w_value == 0) {
2154 + fsg->new_config = w_value;
2155 +
2156 + /* Raise an exception to wipe out previous transaction
2157 + * state (queued bufs, etc) and set the new config. */
2158 + raise_exception(fsg, FSG_STATE_CONFIG_CHANGE);
2159 + value = DELAYED_STATUS;
2160 + }
2161 + break;
2162 + case USB_REQ_GET_CONFIGURATION:
2163 + if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |
2164 + USB_RECIP_DEVICE))
2165 + break;
2166 + VDBG(fsg, "get configuration\n");
2167 + *(u8 *) req->buf = fsg->config;
2168 + value = 1;
2169 + break;
2170 +
2171 + case USB_REQ_SET_INTERFACE:
2172 + if (ctrl->bRequestType != (USB_DIR_OUT| USB_TYPE_STANDARD |
2173 + USB_RECIP_INTERFACE))
2174 + break;
2175 + if (fsg->config && w_index == 0) {
2176 +
2177 + /* Raise an exception to wipe out previous transaction
2178 + * state (queued bufs, etc) and install the new
2179 + * interface altsetting. */
2180 + raise_exception(fsg, FSG_STATE_INTERFACE_CHANGE);
2181 + value = DELAYED_STATUS;
2182 + }
2183 + break;
2184 + case USB_REQ_GET_INTERFACE:
2185 + if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |
2186 + USB_RECIP_INTERFACE))
2187 + break;
2188 + if (!fsg->config)
2189 + break;
2190 + if (w_index != 0) {
2191 + value = -EDOM;
2192 + break;
2193 + }
2194 + VDBG(fsg, "get interface\n");
2195 + *(u8 *) req->buf = 0;
2196 + value = 1;
2197 + break;
2198 +
2199 + default:
2200 + VDBG(fsg,
2201 + "unknown control req %02x.%02x v%04x i%04x l%u\n",
2202 + ctrl->bRequestType, ctrl->bRequest,
2203 + w_value, w_index, le16_to_cpu(ctrl->wLength));
2204 + }
2205 +
2206 + return value;
2207 +}
2208 +
2209 +
2210 +static int fsg_setup(struct usb_gadget *gadget,
2211 + const struct usb_ctrlrequest *ctrl)
2212 +{
2213 + struct fsg_dev *fsg = get_gadget_data(gadget);
2214 + int rc;
2215 + int w_length = le16_to_cpu(ctrl->wLength);
2216 +
2217 + ++fsg->ep0_req_tag; // Record arrival of a new request
2218 + fsg->ep0req->context = NULL;
2219 + fsg->ep0req->length = 0;
2220 + dump_msg(fsg, "ep0-setup", (u8 *) ctrl, sizeof(*ctrl));
2221 +
2222 + if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_CLASS)
2223 + rc = class_setup_req(fsg, ctrl);
2224 + else
2225 + rc = standard_setup_req(fsg, ctrl);
2226 +
2227 + /* Respond with data/status or defer until later? */
2228 + if (rc >= 0 && rc != DELAYED_STATUS) {
2229 + rc = min(rc, w_length);
2230 + fsg->ep0req->length = rc;
2231 + fsg->ep0req->zero = rc < w_length;
2232 + fsg->ep0req_name = (ctrl->bRequestType & USB_DIR_IN ?
2233 + "ep0-in" : "ep0-out");
2234 + rc = ep0_queue(fsg);
2235 + }
2236 +
2237 + /* Device either stalls (rc < 0) or reports success */
2238 + return rc;
2239 +}
2240 +
2241 +
2242 +/*-------------------------------------------------------------------------*/
2243 +
2244 +/* All the following routines run in process context */
2245 +
2246 +
2247 +/* Use this for bulk or interrupt transfers, not ep0 */
2248 +static void start_transfer(struct fsg_dev *fsg, struct usb_ep *ep,
2249 + struct usb_request *req, int *pbusy,
2250 + enum fsg_buffer_state *state)
2251 +{
2252 + int rc;
2253 +
2254 + if (ep == fsg->bulk_in)
2255 + dump_msg(fsg, "bulk-in", req->buf, req->length);
2256 + else if (ep == fsg->intr_in)
2257 + dump_msg(fsg, "intr-in", req->buf, req->length);
2258 +
2259 + spin_lock_irq(&fsg->lock);
2260 + *pbusy = 1;
2261 + *state = BUF_STATE_BUSY;
2262 + spin_unlock_irq(&fsg->lock);
2263 + rc = usb_ep_queue(ep, req, GFP_KERNEL);
2264 + if (rc != 0) {
2265 + *pbusy = 0;
2266 + *state = BUF_STATE_EMPTY;
2267 +
2268 + /* We can't do much more than wait for a reset */
2269 +
2270 + /* Note: currently the net2280 driver fails zero-length
2271 + * submissions if DMA is enabled. */
2272 + if (rc != -ESHUTDOWN && !(rc == -EOPNOTSUPP &&
2273 + req->length == 0))
2274 + WARNING(fsg, "error in submission: %s --> %d\n",
2275 + ep->name, rc);
2276 + }
2277 +}
2278 +
2279 +
2280 +static int sleep_thread(struct fsg_dev *fsg)
2281 +{
2282 + int rc = 0;
2283 +
2284 + /* Wait until a signal arrives or we are woken up */
2285 + for (;;) {
2286 + try_to_freeze();
2287 + set_current_state(TASK_INTERRUPTIBLE);
2288 + if (signal_pending(current)) {
2289 + rc = -EINTR;
2290 + break;
2291 + }
2292 + if (fsg->thread_wakeup_needed)
2293 + break;
2294 + schedule();
2295 + }
2296 + __set_current_state(TASK_RUNNING);
2297 + fsg->thread_wakeup_needed = 0;
2298 + return rc;
2299 +}
2300 +
2301 +
2302 +/*-------------------------------------------------------------------------*/
2303 +
2304 +static int do_read(struct fsg_dev *fsg)
2305 +{
2306 + struct fsg_lun *curlun = fsg->curlun;
2307 + u32 lba;
2308 + struct fsg_buffhd *bh;
2309 + int rc;
2310 + u32 amount_left;
2311 + loff_t file_offset, file_offset_tmp;
2312 + unsigned int amount;
2313 + ssize_t nread;
2314 +
2315 + /* Get the starting Logical Block Address and check that it's
2316 + * not too big */
2317 + if (fsg->cmnd[0] == READ_6)
2318 + lba = get_unaligned_be24(&fsg->cmnd[1]);
2319 + else {
2320 + lba = get_unaligned_be32(&fsg->cmnd[2]);
2321 +
2322 + /* We allow DPO (Disable Page Out = don't save data in the
2323 + * cache) and FUA (Force Unit Access = don't read from the
2324 + * cache), but we don't implement them. */
2325 + if ((fsg->cmnd[1] & ~0x18) != 0) {
2326 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2327 + return -EINVAL;
2328 + }
2329 + }
2330 + if (lba >= curlun->num_sectors) {
2331 + curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
2332 + return -EINVAL;
2333 + }
2334 + file_offset = ((loff_t) lba) << curlun->blkbits;
2335 +
2336 + /* Carry out the file reads */
2337 + amount_left = fsg->data_size_from_cmnd;
2338 + if (unlikely(amount_left == 0))
2339 + return -EIO; // No default reply
2340 +
2341 + for (;;) {
2342 +
2343 + /* Figure out how much we need to read:
2344 + * Try to read the remaining amount.
2345 + * But don't read more than the buffer size.
2346 + * And don't try to read past the end of the file.
2347 + */
2348 + amount = min((unsigned int) amount_left, mod_data.buflen);
2349 + amount = min((loff_t) amount,
2350 + curlun->file_length - file_offset);
2351 +
2352 + /* Wait for the next buffer to become available */
2353 + bh = fsg->next_buffhd_to_fill;
2354 + while (bh->state != BUF_STATE_EMPTY) {
2355 + rc = sleep_thread(fsg);
2356 + if (rc)
2357 + return rc;
2358 + }
2359 +
2360 + /* If we were asked to read past the end of file,
2361 + * end with an empty buffer. */
2362 + if (amount == 0) {
2363 + curlun->sense_data =
2364 + SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
2365 + curlun->sense_data_info = file_offset >> curlun->blkbits;
2366 + curlun->info_valid = 1;
2367 + bh->inreq->length = 0;
2368 + bh->state = BUF_STATE_FULL;
2369 + break;
2370 + }
2371 +
2372 + /* Perform the read */
2373 + file_offset_tmp = file_offset;
2374 + nread = vfs_read(curlun->filp,
2375 + (char __user *) bh->buf,
2376 + amount, &file_offset_tmp);
2377 + VLDBG(curlun, "file read %u @ %llu -> %d\n", amount,
2378 + (unsigned long long) file_offset,
2379 + (int) nread);
2380 + if (signal_pending(current))
2381 + return -EINTR;
2382 +
2383 + if (nread < 0) {
2384 + LDBG(curlun, "error in file read: %d\n",
2385 + (int) nread);
2386 + nread = 0;
2387 + } else if (nread < amount) {
2388 + LDBG(curlun, "partial file read: %d/%u\n",
2389 + (int) nread, amount);
2390 + nread = round_down(nread, curlun->blksize);
2391 + }
2392 + file_offset += nread;
2393 + amount_left -= nread;
2394 + fsg->residue -= nread;
2395 +
2396 + /* Except at the end of the transfer, nread will be
2397 + * equal to the buffer size, which is divisible by the
2398 + * bulk-in maxpacket size.
2399 + */
2400 + bh->inreq->length = nread;
2401 + bh->state = BUF_STATE_FULL;
2402 +
2403 + /* If an error occurred, report it and its position */
2404 + if (nread < amount) {
2405 + curlun->sense_data = SS_UNRECOVERED_READ_ERROR;
2406 + curlun->sense_data_info = file_offset >> curlun->blkbits;
2407 + curlun->info_valid = 1;
2408 + break;
2409 + }
2410 +
2411 + if (amount_left == 0)
2412 + break; // No more left to read
2413 +
2414 + /* Send this buffer and go read some more */
2415 + bh->inreq->zero = 0;
2416 + start_transfer(fsg, fsg->bulk_in, bh->inreq,
2417 + &bh->inreq_busy, &bh->state);
2418 + fsg->next_buffhd_to_fill = bh->next;
2419 + }
2420 +
2421 + return -EIO; // No default reply
2422 +}
2423 +
2424 +
2425 +/*-------------------------------------------------------------------------*/
2426 +
2427 +static int do_write(struct fsg_dev *fsg)
2428 +{
2429 + struct fsg_lun *curlun = fsg->curlun;
2430 + u32 lba;
2431 + struct fsg_buffhd *bh;
2432 + int get_some_more;
2433 + u32 amount_left_to_req, amount_left_to_write;
2434 + loff_t usb_offset, file_offset, file_offset_tmp;
2435 + unsigned int amount;
2436 + ssize_t nwritten;
2437 + int rc;
2438 +
2439 + if (curlun->ro) {
2440 + curlun->sense_data = SS_WRITE_PROTECTED;
2441 + return -EINVAL;
2442 + }
2443 + spin_lock(&curlun->filp->f_lock);
2444 + curlun->filp->f_flags &= ~O_SYNC; // Default is not to wait
2445 + spin_unlock(&curlun->filp->f_lock);
2446 +
2447 + /* Get the starting Logical Block Address and check that it's
2448 + * not too big */
2449 + if (fsg->cmnd[0] == WRITE_6)
2450 + lba = get_unaligned_be24(&fsg->cmnd[1]);
2451 + else {
2452 + lba = get_unaligned_be32(&fsg->cmnd[2]);
2453 +
2454 + /* We allow DPO (Disable Page Out = don't save data in the
2455 + * cache) and FUA (Force Unit Access = write directly to the
2456 + * medium). We don't implement DPO; we implement FUA by
2457 + * performing synchronous output. */
2458 + if ((fsg->cmnd[1] & ~0x18) != 0) {
2459 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2460 + return -EINVAL;
2461 + }
2462 + /* FUA */
2463 + if (!curlun->nofua && (fsg->cmnd[1] & 0x08)) {
2464 + spin_lock(&curlun->filp->f_lock);
2465 + curlun->filp->f_flags |= O_DSYNC;
2466 + spin_unlock(&curlun->filp->f_lock);
2467 + }
2468 + }
2469 + if (lba >= curlun->num_sectors) {
2470 + curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
2471 + return -EINVAL;
2472 + }
2473 +
2474 + /* Carry out the file writes */
2475 + get_some_more = 1;
2476 + file_offset = usb_offset = ((loff_t) lba) << curlun->blkbits;
2477 + amount_left_to_req = amount_left_to_write = fsg->data_size_from_cmnd;
2478 +
2479 + while (amount_left_to_write > 0) {
2480 +
2481 + /* Queue a request for more data from the host */
2482 + bh = fsg->next_buffhd_to_fill;
2483 + if (bh->state == BUF_STATE_EMPTY && get_some_more) {
2484 +
2485 + /* Figure out how much we want to get:
2486 + * Try to get the remaining amount,
2487 + * but not more than the buffer size.
2488 + */
2489 + amount = min(amount_left_to_req, mod_data.buflen);
2490 +
2491 + /* Beyond the end of the backing file? */
2492 + if (usb_offset >= curlun->file_length) {
2493 + get_some_more = 0;
2494 + curlun->sense_data =
2495 + SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
2496 + curlun->sense_data_info = usb_offset >> curlun->blkbits;
2497 + curlun->info_valid = 1;
2498 + continue;
2499 + }
2500 +
2501 + /* Get the next buffer */
2502 + usb_offset += amount;
2503 + fsg->usb_amount_left -= amount;
2504 + amount_left_to_req -= amount;
2505 + if (amount_left_to_req == 0)
2506 + get_some_more = 0;
2507 +
2508 + /* Except at the end of the transfer, amount will be
2509 + * equal to the buffer size, which is divisible by
2510 + * the bulk-out maxpacket size.
2511 + */
2512 + set_bulk_out_req_length(fsg, bh, amount);
2513 + start_transfer(fsg, fsg->bulk_out, bh->outreq,
2514 + &bh->outreq_busy, &bh->state);
2515 + fsg->next_buffhd_to_fill = bh->next;
2516 + continue;
2517 + }
2518 +
2519 + /* Write the received data to the backing file */
2520 + bh = fsg->next_buffhd_to_drain;
2521 + if (bh->state == BUF_STATE_EMPTY && !get_some_more)
2522 + break; // We stopped early
2523 + if (bh->state == BUF_STATE_FULL) {
2524 + smp_rmb();
2525 + fsg->next_buffhd_to_drain = bh->next;
2526 + bh->state = BUF_STATE_EMPTY;
2527 +
2528 + /* Did something go wrong with the transfer? */
2529 + if (bh->outreq->status != 0) {
2530 + curlun->sense_data = SS_COMMUNICATION_FAILURE;
2531 + curlun->sense_data_info = file_offset >> curlun->blkbits;
2532 + curlun->info_valid = 1;
2533 + break;
2534 + }
2535 +
2536 + amount = bh->outreq->actual;
2537 + if (curlun->file_length - file_offset < amount) {
2538 + LERROR(curlun,
2539 + "write %u @ %llu beyond end %llu\n",
2540 + amount, (unsigned long long) file_offset,
2541 + (unsigned long long) curlun->file_length);
2542 + amount = curlun->file_length - file_offset;
2543 + }
2544 +
2545 + /* Don't accept excess data. The spec doesn't say
2546 + * what to do in this case. We'll ignore the error.
2547 + */
2548 + amount = min(amount, bh->bulk_out_intended_length);
2549 +
2550 + /* Don't write a partial block */
2551 + amount = round_down(amount, curlun->blksize);
2552 + if (amount == 0)
2553 + goto empty_write;
2554 +
2555 + /* Perform the write */
2556 + file_offset_tmp = file_offset;
2557 + nwritten = vfs_write(curlun->filp,
2558 + (char __user *) bh->buf,
2559 + amount, &file_offset_tmp);
2560 + VLDBG(curlun, "file write %u @ %llu -> %d\n", amount,
2561 + (unsigned long long) file_offset,
2562 + (int) nwritten);
2563 + if (signal_pending(current))
2564 + return -EINTR; // Interrupted!
2565 +
2566 + if (nwritten < 0) {
2567 + LDBG(curlun, "error in file write: %d\n",
2568 + (int) nwritten);
2569 + nwritten = 0;
2570 + } else if (nwritten < amount) {
2571 + LDBG(curlun, "partial file write: %d/%u\n",
2572 + (int) nwritten, amount);
2573 + nwritten = round_down(nwritten, curlun->blksize);
2574 + }
2575 + file_offset += nwritten;
2576 + amount_left_to_write -= nwritten;
2577 + fsg->residue -= nwritten;
2578 +
2579 + /* If an error occurred, report it and its position */
2580 + if (nwritten < amount) {
2581 + curlun->sense_data = SS_WRITE_ERROR;
2582 + curlun->sense_data_info = file_offset >> curlun->blkbits;
2583 + curlun->info_valid = 1;
2584 + break;
2585 + }
2586 +
2587 + empty_write:
2588 + /* Did the host decide to stop early? */
2589 + if (bh->outreq->actual < bh->bulk_out_intended_length) {
2590 + fsg->short_packet_received = 1;
2591 + break;
2592 + }
2593 + continue;
2594 + }
2595 +
2596 + /* Wait for something to happen */
2597 + rc = sleep_thread(fsg);
2598 + if (rc)
2599 + return rc;
2600 + }
2601 +
2602 + return -EIO; // No default reply
2603 +}
2604 +
2605 +
2606 +/*-------------------------------------------------------------------------*/
2607 +
2608 +static int do_synchronize_cache(struct fsg_dev *fsg)
2609 +{
2610 + struct fsg_lun *curlun = fsg->curlun;
2611 + int rc;
2612 +
2613 + /* We ignore the requested LBA and write out all file's
2614 + * dirty data buffers. */
2615 + rc = fsg_lun_fsync_sub(curlun);
2616 + if (rc)
2617 + curlun->sense_data = SS_WRITE_ERROR;
2618 + return 0;
2619 +}
2620 +
2621 +
2622 +/*-------------------------------------------------------------------------*/
2623 +
2624 +static void invalidate_sub(struct fsg_lun *curlun)
2625 +{
2626 + struct file *filp = curlun->filp;
2627 + struct inode *inode = filp->f_path.dentry->d_inode;
2628 + unsigned long rc;
2629 +
2630 + rc = invalidate_mapping_pages(inode->i_mapping, 0, -1);
2631 + VLDBG(curlun, "invalidate_mapping_pages -> %ld\n", rc);
2632 +}
2633 +
2634 +static int do_verify(struct fsg_dev *fsg)
2635 +{
2636 + struct fsg_lun *curlun = fsg->curlun;
2637 + u32 lba;
2638 + u32 verification_length;
2639 + struct fsg_buffhd *bh = fsg->next_buffhd_to_fill;
2640 + loff_t file_offset, file_offset_tmp;
2641 + u32 amount_left;
2642 + unsigned int amount;
2643 + ssize_t nread;
2644 +
2645 + /* Get the starting Logical Block Address and check that it's
2646 + * not too big */
2647 + lba = get_unaligned_be32(&fsg->cmnd[2]);
2648 + if (lba >= curlun->num_sectors) {
2649 + curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
2650 + return -EINVAL;
2651 + }
2652 +
2653 + /* We allow DPO (Disable Page Out = don't save data in the
2654 + * cache) but we don't implement it. */
2655 + if ((fsg->cmnd[1] & ~0x10) != 0) {
2656 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2657 + return -EINVAL;
2658 + }
2659 +
2660 + verification_length = get_unaligned_be16(&fsg->cmnd[7]);
2661 + if (unlikely(verification_length == 0))
2662 + return -EIO; // No default reply
2663 +
2664 + /* Prepare to carry out the file verify */
2665 + amount_left = verification_length << curlun->blkbits;
2666 + file_offset = ((loff_t) lba) << curlun->blkbits;
2667 +
2668 + /* Write out all the dirty buffers before invalidating them */
2669 + fsg_lun_fsync_sub(curlun);
2670 + if (signal_pending(current))
2671 + return -EINTR;
2672 +
2673 + invalidate_sub(curlun);
2674 + if (signal_pending(current))
2675 + return -EINTR;
2676 +
2677 + /* Just try to read the requested blocks */
2678 + while (amount_left > 0) {
2679 +
2680 + /* Figure out how much we need to read:
2681 + * Try to read the remaining amount, but not more than
2682 + * the buffer size.
2683 + * And don't try to read past the end of the file.
2684 + */
2685 + amount = min((unsigned int) amount_left, mod_data.buflen);
2686 + amount = min((loff_t) amount,
2687 + curlun->file_length - file_offset);
2688 + if (amount == 0) {
2689 + curlun->sense_data =
2690 + SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
2691 + curlun->sense_data_info = file_offset >> curlun->blkbits;
2692 + curlun->info_valid = 1;
2693 + break;
2694 + }
2695 +
2696 + /* Perform the read */
2697 + file_offset_tmp = file_offset;
2698 + nread = vfs_read(curlun->filp,
2699 + (char __user *) bh->buf,
2700 + amount, &file_offset_tmp);
2701 + VLDBG(curlun, "file read %u @ %llu -> %d\n", amount,
2702 + (unsigned long long) file_offset,
2703 + (int) nread);
2704 + if (signal_pending(current))
2705 + return -EINTR;
2706 +
2707 + if (nread < 0) {
2708 + LDBG(curlun, "error in file verify: %d\n",
2709 + (int) nread);
2710 + nread = 0;
2711 + } else if (nread < amount) {
2712 + LDBG(curlun, "partial file verify: %d/%u\n",
2713 + (int) nread, amount);
2714 + nread = round_down(nread, curlun->blksize);
2715 + }
2716 + if (nread == 0) {
2717 + curlun->sense_data = SS_UNRECOVERED_READ_ERROR;
2718 + curlun->sense_data_info = file_offset >> curlun->blkbits;
2719 + curlun->info_valid = 1;
2720 + break;
2721 + }
2722 + file_offset += nread;
2723 + amount_left -= nread;
2724 + }
2725 + return 0;
2726 +}
2727 +
2728 +
2729 +/*-------------------------------------------------------------------------*/
2730 +
2731 +static int do_inquiry(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2732 +{
2733 + u8 *buf = (u8 *) bh->buf;
2734 +
2735 + static char vendor_id[] = "Linux ";
2736 + static char product_disk_id[] = "File-Stor Gadget";
2737 + static char product_cdrom_id[] = "File-CD Gadget ";
2738 +
2739 + if (!fsg->curlun) { // Unsupported LUNs are okay
2740 + fsg->bad_lun_okay = 1;
2741 + memset(buf, 0, 36);
2742 + buf[0] = 0x7f; // Unsupported, no device-type
2743 + buf[4] = 31; // Additional length
2744 + return 36;
2745 + }
2746 +
2747 + memset(buf, 0, 8);
2748 + buf[0] = (mod_data.cdrom ? TYPE_ROM : TYPE_DISK);
2749 + if (mod_data.removable)
2750 + buf[1] = 0x80;
2751 + buf[2] = 2; // ANSI SCSI level 2
2752 + buf[3] = 2; // SCSI-2 INQUIRY data format
2753 + buf[4] = 31; // Additional length
2754 + // No special options
2755 + sprintf(buf + 8, "%-8s%-16s%04x", vendor_id,
2756 + (mod_data.cdrom ? product_cdrom_id :
2757 + product_disk_id),
2758 + mod_data.release);
2759 + return 36;
2760 +}
2761 +
2762 +
2763 +static int do_request_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2764 +{
2765 + struct fsg_lun *curlun = fsg->curlun;
2766 + u8 *buf = (u8 *) bh->buf;
2767 + u32 sd, sdinfo;
2768 + int valid;
2769 +
2770 + /*
2771 + * From the SCSI-2 spec., section 7.9 (Unit attention condition):
2772 + *
2773 + * If a REQUEST SENSE command is received from an initiator
2774 + * with a pending unit attention condition (before the target
2775 + * generates the contingent allegiance condition), then the
2776 + * target shall either:
2777 + * a) report any pending sense data and preserve the unit
2778 + * attention condition on the logical unit, or,
2779 + * b) report the unit attention condition, may discard any
2780 + * pending sense data, and clear the unit attention
2781 + * condition on the logical unit for that initiator.
2782 + *
2783 + * FSG normally uses option a); enable this code to use option b).
2784 + */
2785 +#if 0
2786 + if (curlun && curlun->unit_attention_data != SS_NO_SENSE) {
2787 + curlun->sense_data = curlun->unit_attention_data;
2788 + curlun->unit_attention_data = SS_NO_SENSE;
2789 + }
2790 +#endif
2791 +
2792 + if (!curlun) { // Unsupported LUNs are okay
2793 + fsg->bad_lun_okay = 1;
2794 + sd = SS_LOGICAL_UNIT_NOT_SUPPORTED;
2795 + sdinfo = 0;
2796 + valid = 0;
2797 + } else {
2798 + sd = curlun->sense_data;
2799 + sdinfo = curlun->sense_data_info;
2800 + valid = curlun->info_valid << 7;
2801 + curlun->sense_data = SS_NO_SENSE;
2802 + curlun->sense_data_info = 0;
2803 + curlun->info_valid = 0;
2804 + }
2805 +
2806 + memset(buf, 0, 18);
2807 + buf[0] = valid | 0x70; // Valid, current error
2808 + buf[2] = SK(sd);
2809 + put_unaligned_be32(sdinfo, &buf[3]); /* Sense information */
2810 + buf[7] = 18 - 8; // Additional sense length
2811 + buf[12] = ASC(sd);
2812 + buf[13] = ASCQ(sd);
2813 + return 18;
2814 +}
2815 +
2816 +
2817 +static int do_read_capacity(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2818 +{
2819 + struct fsg_lun *curlun = fsg->curlun;
2820 + u32 lba = get_unaligned_be32(&fsg->cmnd[2]);
2821 + int pmi = fsg->cmnd[8];
2822 + u8 *buf = (u8 *) bh->buf;
2823 +
2824 + /* Check the PMI and LBA fields */
2825 + if (pmi > 1 || (pmi == 0 && lba != 0)) {
2826 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2827 + return -EINVAL;
2828 + }
2829 +
2830 + put_unaligned_be32(curlun->num_sectors - 1, &buf[0]);
2831 + /* Max logical block */
2832 + put_unaligned_be32(curlun->blksize, &buf[4]); /* Block length */
2833 + return 8;
2834 +}
2835 +
2836 +
2837 +static int do_read_header(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2838 +{
2839 + struct fsg_lun *curlun = fsg->curlun;
2840 + int msf = fsg->cmnd[1] & 0x02;
2841 + u32 lba = get_unaligned_be32(&fsg->cmnd[2]);
2842 + u8 *buf = (u8 *) bh->buf;
2843 +
2844 + if ((fsg->cmnd[1] & ~0x02) != 0) { /* Mask away MSF */
2845 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2846 + return -EINVAL;
2847 + }
2848 + if (lba >= curlun->num_sectors) {
2849 + curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
2850 + return -EINVAL;
2851 + }
2852 +
2853 + memset(buf, 0, 8);
2854 + buf[0] = 0x01; /* 2048 bytes of user data, rest is EC */
2855 + store_cdrom_address(&buf[4], msf, lba);
2856 + return 8;
2857 +}
2858 +
2859 +
2860 +static int do_read_toc(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2861 +{
2862 + struct fsg_lun *curlun = fsg->curlun;
2863 + int msf = fsg->cmnd[1] & 0x02;
2864 + int start_track = fsg->cmnd[6];
2865 + u8 *buf = (u8 *) bh->buf;
2866 +
2867 + if ((fsg->cmnd[1] & ~0x02) != 0 || /* Mask away MSF */
2868 + start_track > 1) {
2869 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2870 + return -EINVAL;
2871 + }
2872 +
2873 + memset(buf, 0, 20);
2874 + buf[1] = (20-2); /* TOC data length */
2875 + buf[2] = 1; /* First track number */
2876 + buf[3] = 1; /* Last track number */
2877 + buf[5] = 0x16; /* Data track, copying allowed */
2878 + buf[6] = 0x01; /* Only track is number 1 */
2879 + store_cdrom_address(&buf[8], msf, 0);
2880 +
2881 + buf[13] = 0x16; /* Lead-out track is data */
2882 + buf[14] = 0xAA; /* Lead-out track number */
2883 + store_cdrom_address(&buf[16], msf, curlun->num_sectors);
2884 + return 20;
2885 +}
2886 +
2887 +
2888 +static int do_mode_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2889 +{
2890 + struct fsg_lun *curlun = fsg->curlun;
2891 + int mscmnd = fsg->cmnd[0];
2892 + u8 *buf = (u8 *) bh->buf;
2893 + u8 *buf0 = buf;
2894 + int pc, page_code;
2895 + int changeable_values, all_pages;
2896 + int valid_page = 0;
2897 + int len, limit;
2898 +
2899 + if ((fsg->cmnd[1] & ~0x08) != 0) { // Mask away DBD
2900 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2901 + return -EINVAL;
2902 + }
2903 + pc = fsg->cmnd[2] >> 6;
2904 + page_code = fsg->cmnd[2] & 0x3f;
2905 + if (pc == 3) {
2906 + curlun->sense_data = SS_SAVING_PARAMETERS_NOT_SUPPORTED;
2907 + return -EINVAL;
2908 + }
2909 + changeable_values = (pc == 1);
2910 + all_pages = (page_code == 0x3f);
2911 +
2912 + /* Write the mode parameter header. Fixed values are: default
2913 + * medium type, no cache control (DPOFUA), and no block descriptors.
2914 + * The only variable value is the WriteProtect bit. We will fill in
2915 + * the mode data length later. */
2916 + memset(buf, 0, 8);
2917 + if (mscmnd == MODE_SENSE) {
2918 + buf[2] = (curlun->ro ? 0x80 : 0x00); // WP, DPOFUA
2919 + buf += 4;
2920 + limit = 255;
2921 + } else { // MODE_SENSE_10
2922 + buf[3] = (curlun->ro ? 0x80 : 0x00); // WP, DPOFUA
2923 + buf += 8;
2924 + limit = 65535; // Should really be mod_data.buflen
2925 + }
2926 +
2927 + /* No block descriptors */
2928 +
2929 + /* The mode pages, in numerical order. The only page we support
2930 + * is the Caching page. */
2931 + if (page_code == 0x08 || all_pages) {
2932 + valid_page = 1;
2933 + buf[0] = 0x08; // Page code
2934 + buf[1] = 10; // Page length
2935 + memset(buf+2, 0, 10); // None of the fields are changeable
2936 +
2937 + if (!changeable_values) {
2938 + buf[2] = 0x04; // Write cache enable,
2939 + // Read cache not disabled
2940 + // No cache retention priorities
2941 + put_unaligned_be16(0xffff, &buf[4]);
2942 + /* Don't disable prefetch */
2943 + /* Minimum prefetch = 0 */
2944 + put_unaligned_be16(0xffff, &buf[8]);
2945 + /* Maximum prefetch */
2946 + put_unaligned_be16(0xffff, &buf[10]);
2947 + /* Maximum prefetch ceiling */
2948 + }
2949 + buf += 12;
2950 + }
2951 +
2952 + /* Check that a valid page was requested and the mode data length
2953 + * isn't too long. */
2954 + len = buf - buf0;
2955 + if (!valid_page || len > limit) {
2956 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2957 + return -EINVAL;
2958 + }
2959 +
2960 + /* Store the mode data length */
2961 + if (mscmnd == MODE_SENSE)
2962 + buf0[0] = len - 1;
2963 + else
2964 + put_unaligned_be16(len - 2, buf0);
2965 + return len;
2966 +}
2967 +
2968 +
2969 +static int do_start_stop(struct fsg_dev *fsg)
2970 +{
2971 + struct fsg_lun *curlun = fsg->curlun;
2972 + int loej, start;
2973 +
2974 + if (!mod_data.removable) {
2975 + curlun->sense_data = SS_INVALID_COMMAND;
2976 + return -EINVAL;
2977 + }
2978 +
2979 + // int immed = fsg->cmnd[1] & 0x01;
2980 + loej = fsg->cmnd[4] & 0x02;
2981 + start = fsg->cmnd[4] & 0x01;
2982 +
2983 +#ifdef CONFIG_USB_FILE_STORAGE_TEST
2984 + if ((fsg->cmnd[1] & ~0x01) != 0 || // Mask away Immed
2985 + (fsg->cmnd[4] & ~0x03) != 0) { // Mask LoEj, Start
2986 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2987 + return -EINVAL;
2988 + }
2989 +
2990 + if (!start) {
2991 +
2992 + /* Are we allowed to unload the media? */
2993 + if (curlun->prevent_medium_removal) {
2994 + LDBG(curlun, "unload attempt prevented\n");
2995 + curlun->sense_data = SS_MEDIUM_REMOVAL_PREVENTED;
2996 + return -EINVAL;
2997 + }
2998 + if (loej) { // Simulate an unload/eject
2999 + up_read(&fsg->filesem);
3000 + down_write(&fsg->filesem);
3001 + fsg_lun_close(curlun);
3002 + up_write(&fsg->filesem);
3003 + down_read(&fsg->filesem);
3004 + }
3005 + } else {
3006 +
3007 + /* Our emulation doesn't support mounting; the medium is
3008 + * available for use as soon as it is loaded. */
3009 + if (!fsg_lun_is_open(curlun)) {
3010 + curlun->sense_data = SS_MEDIUM_NOT_PRESENT;
3011 + return -EINVAL;
3012 + }
3013 + }
3014 +#endif
3015 + return 0;
3016 +}
3017 +
3018 +
3019 +static int do_prevent_allow(struct fsg_dev *fsg)
3020 +{
3021 + struct fsg_lun *curlun = fsg->curlun;
3022 + int prevent;
3023 +
3024 + if (!mod_data.removable) {
3025 + curlun->sense_data = SS_INVALID_COMMAND;
3026 + return -EINVAL;
3027 + }
3028 +
3029 + prevent = fsg->cmnd[4] & 0x01;
3030 + if ((fsg->cmnd[4] & ~0x01) != 0) { // Mask away Prevent
3031 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
3032 + return -EINVAL;
3033 + }
3034 +
3035 + if (curlun->prevent_medium_removal && !prevent)
3036 + fsg_lun_fsync_sub(curlun);
3037 + curlun->prevent_medium_removal = prevent;
3038 + return 0;
3039 +}
3040 +
3041 +
3042 +static int do_read_format_capacities(struct fsg_dev *fsg,
3043 + struct fsg_buffhd *bh)
3044 +{
3045 + struct fsg_lun *curlun = fsg->curlun;
3046 + u8 *buf = (u8 *) bh->buf;
3047 +
3048 + buf[0] = buf[1] = buf[2] = 0;
3049 + buf[3] = 8; // Only the Current/Maximum Capacity Descriptor
3050 + buf += 4;
3051 +
3052 + put_unaligned_be32(curlun->num_sectors, &buf[0]);
3053 + /* Number of blocks */
3054 + put_unaligned_be32(curlun->blksize, &buf[4]); /* Block length */
3055 + buf[4] = 0x02; /* Current capacity */
3056 + return 12;
3057 +}
3058 +
3059 +
3060 +static int do_mode_select(struct fsg_dev *fsg, struct fsg_buffhd *bh)
3061 +{
3062 + struct fsg_lun *curlun = fsg->curlun;
3063 +
3064 + /* We don't support MODE SELECT */
3065 + curlun->sense_data = SS_INVALID_COMMAND;
3066 + return -EINVAL;
3067 +}
3068 +
3069 +
3070 +/*-------------------------------------------------------------------------*/
3071 +
3072 +static int halt_bulk_in_endpoint(struct fsg_dev *fsg)
3073 +{
3074 + int rc;
3075 +
3076 + rc = fsg_set_halt(fsg, fsg->bulk_in);
3077 + if (rc == -EAGAIN)
3078 + VDBG(fsg, "delayed bulk-in endpoint halt\n");
3079 + while (rc != 0) {
3080 + if (rc != -EAGAIN) {
3081 + WARNING(fsg, "usb_ep_set_halt -> %d\n", rc);
3082 + rc = 0;
3083 + break;
3084 + }
3085 +
3086 + /* Wait for a short time and then try again */
3087 + if (msleep_interruptible(100) != 0)
3088 + return -EINTR;
3089 + rc = usb_ep_set_halt(fsg->bulk_in);
3090 + }
3091 + return rc;
3092 +}
3093 +
3094 +static int wedge_bulk_in_endpoint(struct fsg_dev *fsg)
3095 +{
3096 + int rc;
3097 +
3098 + DBG(fsg, "bulk-in set wedge\n");
3099 + rc = usb_ep_set_wedge(fsg->bulk_in);
3100 + if (rc == -EAGAIN)
3101 + VDBG(fsg, "delayed bulk-in endpoint wedge\n");
3102 + while (rc != 0) {
3103 + if (rc != -EAGAIN) {
3104 + WARNING(fsg, "usb_ep_set_wedge -> %d\n", rc);
3105 + rc = 0;
3106 + break;
3107 + }
3108 +
3109 + /* Wait for a short time and then try again */
3110 + if (msleep_interruptible(100) != 0)
3111 + return -EINTR;
3112 + rc = usb_ep_set_wedge(fsg->bulk_in);
3113 + }
3114 + return rc;
3115 +}
3116 +
3117 +static int throw_away_data(struct fsg_dev *fsg)
3118 +{
3119 + struct fsg_buffhd *bh;
3120 + u32 amount;
3121 + int rc;
3122 +
3123 + while ((bh = fsg->next_buffhd_to_drain)->state != BUF_STATE_EMPTY ||
3124 + fsg->usb_amount_left > 0) {
3125 +
3126 + /* Throw away the data in a filled buffer */
3127 + if (bh->state == BUF_STATE_FULL) {
3128 + smp_rmb();
3129 + bh->state = BUF_STATE_EMPTY;
3130 + fsg->next_buffhd_to_drain = bh->next;
3131 +
3132 + /* A short packet or an error ends everything */
3133 + if (bh->outreq->actual < bh->bulk_out_intended_length ||
3134 + bh->outreq->status != 0) {
3135 + raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
3136 + return -EINTR;
3137 + }
3138 + continue;
3139 + }
3140 +
3141 + /* Try to submit another request if we need one */
3142 + bh = fsg->next_buffhd_to_fill;
3143 + if (bh->state == BUF_STATE_EMPTY && fsg->usb_amount_left > 0) {
3144 + amount = min(fsg->usb_amount_left,
3145 + (u32) mod_data.buflen);
3146 +
3147 + /* Except at the end of the transfer, amount will be
3148 + * equal to the buffer size, which is divisible by
3149 + * the bulk-out maxpacket size.
3150 + */
3151 + set_bulk_out_req_length(fsg, bh, amount);
3152 + start_transfer(fsg, fsg->bulk_out, bh->outreq,
3153 + &bh->outreq_busy, &bh->state);
3154 + fsg->next_buffhd_to_fill = bh->next;
3155 + fsg->usb_amount_left -= amount;
3156 + continue;
3157 + }
3158 +
3159 + /* Otherwise wait for something to happen */
3160 + rc = sleep_thread(fsg);
3161 + if (rc)
3162 + return rc;
3163 + }
3164 + return 0;
3165 +}
3166 +
3167 +
3168 +static int finish_reply(struct fsg_dev *fsg)
3169 +{
3170 + struct fsg_buffhd *bh = fsg->next_buffhd_to_fill;
3171 + int rc = 0;
3172 +
3173 + switch (fsg->data_dir) {
3174 + case DATA_DIR_NONE:
3175 + break; // Nothing to send
3176 +
3177 + /* If we don't know whether the host wants to read or write,
3178 + * this must be CB or CBI with an unknown command. We mustn't
3179 + * try to send or receive any data. So stall both bulk pipes
3180 + * if we can and wait for a reset. */
3181 + case DATA_DIR_UNKNOWN:
3182 + if (mod_data.can_stall) {
3183 + fsg_set_halt(fsg, fsg->bulk_out);
3184 + rc = halt_bulk_in_endpoint(fsg);
3185 + }
3186 + break;
3187 +
3188 + /* All but the last buffer of data must have already been sent */
3189 + case DATA_DIR_TO_HOST:
3190 + if (fsg->data_size == 0)
3191 + ; // Nothing to send
3192 +
3193 + /* If there's no residue, simply send the last buffer */
3194 + else if (fsg->residue == 0) {
3195 + bh->inreq->zero = 0;
3196 + start_transfer(fsg, fsg->bulk_in, bh->inreq,
3197 + &bh->inreq_busy, &bh->state);
3198 + fsg->next_buffhd_to_fill = bh->next;
3199 + }
3200 +
3201 + /* There is a residue. For CB and CBI, simply mark the end
3202 + * of the data with a short packet. However, if we are
3203 + * allowed to stall, there was no data at all (residue ==
3204 + * data_size), and the command failed (invalid LUN or
3205 + * sense data is set), then halt the bulk-in endpoint
3206 + * instead. */
3207 + else if (!transport_is_bbb()) {
3208 + if (mod_data.can_stall &&
3209 + fsg->residue == fsg->data_size &&
3210 + (!fsg->curlun || fsg->curlun->sense_data != SS_NO_SENSE)) {
3211 + bh->state = BUF_STATE_EMPTY;
3212 + rc = halt_bulk_in_endpoint(fsg);
3213 + } else {
3214 + bh->inreq->zero = 1;
3215 + start_transfer(fsg, fsg->bulk_in, bh->inreq,
3216 + &bh->inreq_busy, &bh->state);
3217 + fsg->next_buffhd_to_fill = bh->next;
3218 + }
3219 + }
3220 +
3221 + /*
3222 + * For Bulk-only, mark the end of the data with a short
3223 + * packet. If we are allowed to stall, halt the bulk-in
3224 + * endpoint. (Note: This violates the Bulk-Only Transport
3225 + * specification, which requires us to pad the data if we
3226 + * don't halt the endpoint. Presumably nobody will mind.)
3227 + */
3228 + else {
3229 + bh->inreq->zero = 1;
3230 + start_transfer(fsg, fsg->bulk_in, bh->inreq,
3231 + &bh->inreq_busy, &bh->state);
3232 + fsg->next_buffhd_to_fill = bh->next;
3233 + if (mod_data.can_stall)
3234 + rc = halt_bulk_in_endpoint(fsg);
3235 + }
3236 + break;
3237 +
3238 + /* We have processed all we want from the data the host has sent.
3239 + * There may still be outstanding bulk-out requests. */
3240 + case DATA_DIR_FROM_HOST:
3241 + if (fsg->residue == 0)
3242 + ; // Nothing to receive
3243 +
3244 + /* Did the host stop sending unexpectedly early? */
3245 + else if (fsg->short_packet_received) {
3246 + raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
3247 + rc = -EINTR;
3248 + }
3249 +
3250 + /* We haven't processed all the incoming data. Even though
3251 + * we may be allowed to stall, doing so would cause a race.
3252 + * The controller may already have ACK'ed all the remaining
3253 + * bulk-out packets, in which case the host wouldn't see a
3254 + * STALL. Not realizing the endpoint was halted, it wouldn't
3255 + * clear the halt -- leading to problems later on. */
3256 +#if 0
3257 + else if (mod_data.can_stall) {
3258 + fsg_set_halt(fsg, fsg->bulk_out);
3259 + raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
3260 + rc = -EINTR;
3261 + }
3262 +#endif
3263 +
3264 + /* We can't stall. Read in the excess data and throw it
3265 + * all away. */
3266 + else
3267 + rc = throw_away_data(fsg);
3268 + break;
3269 + }
3270 + return rc;
3271 +}
3272 +
3273 +
3274 +static int send_status(struct fsg_dev *fsg)
3275 +{
3276 + struct fsg_lun *curlun = fsg->curlun;
3277 + struct fsg_buffhd *bh;
3278 + int rc;
3279 + u8 status = US_BULK_STAT_OK;
3280 + u32 sd, sdinfo = 0;
3281 +
3282 + /* Wait for the next buffer to become available */
3283 + bh = fsg->next_buffhd_to_fill;
3284 + while (bh->state != BUF_STATE_EMPTY) {
3285 + rc = sleep_thread(fsg);
3286 + if (rc)
3287 + return rc;
3288 + }
3289 +
3290 + if (curlun) {
3291 + sd = curlun->sense_data;
3292 + sdinfo = curlun->sense_data_info;
3293 + } else if (fsg->bad_lun_okay)
3294 + sd = SS_NO_SENSE;
3295 + else
3296 + sd = SS_LOGICAL_UNIT_NOT_SUPPORTED;
3297 +
3298 + if (fsg->phase_error) {
3299 + DBG(fsg, "sending phase-error status\n");
3300 + status = US_BULK_STAT_PHASE;
3301 + sd = SS_INVALID_COMMAND;
3302 + } else if (sd != SS_NO_SENSE) {
3303 + DBG(fsg, "sending command-failure status\n");
3304 + status = US_BULK_STAT_FAIL;
3305 + VDBG(fsg, " sense data: SK x%02x, ASC x%02x, ASCQ x%02x;"
3306 + " info x%x\n",
3307 + SK(sd), ASC(sd), ASCQ(sd), sdinfo);
3308 + }
3309 +
3310 + if (transport_is_bbb()) {
3311 + struct bulk_cs_wrap *csw = bh->buf;
3312 +
3313 + /* Store and send the Bulk-only CSW */
3314 + csw->Signature = cpu_to_le32(US_BULK_CS_SIGN);
3315 + csw->Tag = fsg->tag;
3316 + csw->Residue = cpu_to_le32(fsg->residue);
3317 + csw->Status = status;
3318 +
3319 + bh->inreq->length = US_BULK_CS_WRAP_LEN;
3320 + bh->inreq->zero = 0;
3321 + start_transfer(fsg, fsg->bulk_in, bh->inreq,
3322 + &bh->inreq_busy, &bh->state);
3323 +
3324 + } else if (mod_data.transport_type == USB_PR_CB) {
3325 +
3326 + /* Control-Bulk transport has no status phase! */
3327 + return 0;
3328 +
3329 + } else { // USB_PR_CBI
3330 + struct interrupt_data *buf = bh->buf;
3331 +
3332 + /* Store and send the Interrupt data. UFI sends the ASC
3333 + * and ASCQ bytes. Everything else sends a Type (which
3334 + * is always 0) and the status Value. */
3335 + if (mod_data.protocol_type == USB_SC_UFI) {
3336 + buf->bType = ASC(sd);
3337 + buf->bValue = ASCQ(sd);
3338 + } else {
3339 + buf->bType = 0;
3340 + buf->bValue = status;
3341 + }
3342 + fsg->intreq->length = CBI_INTERRUPT_DATA_LEN;
3343 +
3344 + fsg->intr_buffhd = bh; // Point to the right buffhd
3345 + fsg->intreq->buf = bh->inreq->buf;
3346 + fsg->intreq->context = bh;
3347 + start_transfer(fsg, fsg->intr_in, fsg->intreq,
3348 + &fsg->intreq_busy, &bh->state);
3349 + }
3350 +
3351 + fsg->next_buffhd_to_fill = bh->next;
3352 + return 0;
3353 +}
3354 +
3355 +
3356 +/*-------------------------------------------------------------------------*/
3357 +
3358 +/* Check whether the command is properly formed and whether its data size
3359 + * and direction agree with the values we already have. */
3360 +static int check_command(struct fsg_dev *fsg, int cmnd_size,
3361 + enum data_direction data_dir, unsigned int mask,
3362 + int needs_medium, const char *name)
3363 +{
3364 + int i;
3365 + int lun = fsg->cmnd[1] >> 5;
3366 + static const char dirletter[4] = {'u', 'o', 'i', 'n'};
3367 + char hdlen[20];
3368 + struct fsg_lun *curlun;
3369 +
3370 + /* Adjust the expected cmnd_size for protocol encapsulation padding.
3371 + * Transparent SCSI doesn't pad. */
3372 + if (protocol_is_scsi())
3373 + ;
3374 +
3375 + /* There's some disagreement as to whether RBC pads commands or not.
3376 + * We'll play it safe and accept either form. */
3377 + else if (mod_data.protocol_type == USB_SC_RBC) {
3378 + if (fsg->cmnd_size == 12)
3379 + cmnd_size = 12;
3380 +
3381 + /* All the other protocols pad to 12 bytes */
3382 + } else
3383 + cmnd_size = 12;
3384 +
3385 + hdlen[0] = 0;
3386 + if (fsg->data_dir != DATA_DIR_UNKNOWN)
3387 + sprintf(hdlen, ", H%c=%u", dirletter[(int) fsg->data_dir],
3388 + fsg->data_size);
3389 + VDBG(fsg, "SCSI command: %s; Dc=%d, D%c=%u; Hc=%d%s\n",
3390 + name, cmnd_size, dirletter[(int) data_dir],
3391 + fsg->data_size_from_cmnd, fsg->cmnd_size, hdlen);
3392 +
3393 + /* We can't reply at all until we know the correct data direction
3394 + * and size. */
3395 + if (fsg->data_size_from_cmnd == 0)
3396 + data_dir = DATA_DIR_NONE;
3397 + if (fsg->data_dir == DATA_DIR_UNKNOWN) { // CB or CBI
3398 + fsg->data_dir = data_dir;
3399 + fsg->data_size = fsg->data_size_from_cmnd;
3400 +
3401 + } else { // Bulk-only
3402 + if (fsg->data_size < fsg->data_size_from_cmnd) {
3403 +
3404 + /* Host data size < Device data size is a phase error.
3405 + * Carry out the command, but only transfer as much
3406 + * as we are allowed. */
3407 + fsg->data_size_from_cmnd = fsg->data_size;
3408 + fsg->phase_error = 1;
3409 + }
3410 + }
3411 + fsg->residue = fsg->usb_amount_left = fsg->data_size;
3412 +
3413 + /* Conflicting data directions is a phase error */
3414 + if (fsg->data_dir != data_dir && fsg->data_size_from_cmnd > 0) {
3415 + fsg->phase_error = 1;
3416 + return -EINVAL;
3417 + }
3418 +
3419 + /* Verify the length of the command itself */
3420 + if (cmnd_size != fsg->cmnd_size) {
3421 +
3422 + /* Special case workaround: There are plenty of buggy SCSI
3423 + * implementations. Many have issues with cbw->Length
3424 + * field passing a wrong command size. For those cases we
3425 + * always try to work around the problem by using the length
3426 + * sent by the host side provided it is at least as large
3427 + * as the correct command length.
3428 + * Examples of such cases would be MS-Windows, which issues
3429 + * REQUEST SENSE with cbw->Length == 12 where it should
3430 + * be 6, and xbox360 issuing INQUIRY, TEST UNIT READY and
3431 + * REQUEST SENSE with cbw->Length == 10 where it should
3432 + * be 6 as well.
3433 + */
3434 + if (cmnd_size <= fsg->cmnd_size) {
3435 + DBG(fsg, "%s is buggy! Expected length %d "
3436 + "but we got %d\n", name,
3437 + cmnd_size, fsg->cmnd_size);
3438 + cmnd_size = fsg->cmnd_size;
3439 + } else {
3440 + fsg->phase_error = 1;
3441 + return -EINVAL;
3442 + }
3443 + }
3444 +
3445 + /* Check that the LUN values are consistent */
3446 + if (transport_is_bbb()) {
3447 + if (fsg->lun != lun)
3448 + DBG(fsg, "using LUN %d from CBW, "
3449 + "not LUN %d from CDB\n",
3450 + fsg->lun, lun);
3451 + }
3452 +
3453 + /* Check the LUN */
3454 + curlun = fsg->curlun;
3455 + if (curlun) {
3456 + if (fsg->cmnd[0] != REQUEST_SENSE) {
3457 + curlun->sense_data = SS_NO_SENSE;
3458 + curlun->sense_data_info = 0;
3459 + curlun->info_valid = 0;
3460 + }
3461 + } else {
3462 + fsg->bad_lun_okay = 0;
3463 +
3464 + /* INQUIRY and REQUEST SENSE commands are explicitly allowed
3465 + * to use unsupported LUNs; all others may not. */
3466 + if (fsg->cmnd[0] != INQUIRY &&
3467 + fsg->cmnd[0] != REQUEST_SENSE) {
3468 + DBG(fsg, "unsupported LUN %d\n", fsg->lun);
3469 + return -EINVAL;
3470 + }
3471 + }
3472 +
3473 + /* If a unit attention condition exists, only INQUIRY and
3474 + * REQUEST SENSE commands are allowed; anything else must fail. */
3475 + if (curlun && curlun->unit_attention_data != SS_NO_SENSE &&
3476 + fsg->cmnd[0] != INQUIRY &&
3477 + fsg->cmnd[0] != REQUEST_SENSE) {
3478 + curlun->sense_data = curlun->unit_attention_data;
3479 + curlun->unit_attention_data = SS_NO_SENSE;
3480 + return -EINVAL;
3481 + }
3482 +
3483 + /* Check that only command bytes listed in the mask are non-zero */
3484 + fsg->cmnd[1] &= 0x1f; // Mask away the LUN
3485 + for (i = 1; i < cmnd_size; ++i) {
3486 + if (fsg->cmnd[i] && !(mask & (1 << i))) {
3487 + if (curlun)
3488 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
3489 + return -EINVAL;
3490 + }
3491 + }
3492 +
3493 + /* If the medium isn't mounted and the command needs to access
3494 + * it, return an error. */
3495 + if (curlun && !fsg_lun_is_open(curlun) && needs_medium) {
3496 + curlun->sense_data = SS_MEDIUM_NOT_PRESENT;
3497 + return -EINVAL;
3498 + }
3499 +
3500 + return 0;
3501 +}
3502 +
3503 +/* wrapper of check_command for data size in blocks handling */
3504 +static int check_command_size_in_blocks(struct fsg_dev *fsg, int cmnd_size,
3505 + enum data_direction data_dir, unsigned int mask,
3506 + int needs_medium, const char *name)
3507 +{
3508 + if (fsg->curlun)
3509 + fsg->data_size_from_cmnd <<= fsg->curlun->blkbits;
3510 + return check_command(fsg, cmnd_size, data_dir,
3511 + mask, needs_medium, name);
3512 +}
3513 +
3514 +static int do_scsi_command(struct fsg_dev *fsg)
3515 +{
3516 + struct fsg_buffhd *bh;
3517 + int rc;
3518 + int reply = -EINVAL;
3519 + int i;
3520 + static char unknown[16];
3521 +
3522 + dump_cdb(fsg);
3523 +
3524 + /* Wait for the next buffer to become available for data or status */
3525 + bh = fsg->next_buffhd_to_drain = fsg->next_buffhd_to_fill;
3526 + while (bh->state != BUF_STATE_EMPTY) {
3527 + rc = sleep_thread(fsg);
3528 + if (rc)
3529 + return rc;
3530 + }
3531 + fsg->phase_error = 0;
3532 + fsg->short_packet_received = 0;
3533 +
3534 + down_read(&fsg->filesem); // We're using the backing file
3535 + switch (fsg->cmnd[0]) {
3536 +
3537 + case INQUIRY:
3538 + fsg->data_size_from_cmnd = fsg->cmnd[4];
3539 + if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
3540 + (1<<4), 0,
3541 + "INQUIRY")) == 0)
3542 + reply = do_inquiry(fsg, bh);
3543 + break;
3544 +
3545 + case MODE_SELECT:
3546 + fsg->data_size_from_cmnd = fsg->cmnd[4];
3547 + if ((reply = check_command(fsg, 6, DATA_DIR_FROM_HOST,
3548 + (1<<1) | (1<<4), 0,
3549 + "MODE SELECT(6)")) == 0)
3550 + reply = do_mode_select(fsg, bh);
3551 + break;
3552 +
3553 + case MODE_SELECT_10:
3554 + fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
3555 + if ((reply = check_command(fsg, 10, DATA_DIR_FROM_HOST,
3556 + (1<<1) | (3<<7), 0,
3557 + "MODE SELECT(10)")) == 0)
3558 + reply = do_mode_select(fsg, bh);
3559 + break;
3560 +
3561 + case MODE_SENSE:
3562 + fsg->data_size_from_cmnd = fsg->cmnd[4];
3563 + if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
3564 + (1<<1) | (1<<2) | (1<<4), 0,
3565 + "MODE SENSE(6)")) == 0)
3566 + reply = do_mode_sense(fsg, bh);
3567 + break;
3568 +
3569 + case MODE_SENSE_10:
3570 + fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
3571 + if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
3572 + (1<<1) | (1<<2) | (3<<7), 0,
3573 + "MODE SENSE(10)")) == 0)
3574 + reply = do_mode_sense(fsg, bh);
3575 + break;
3576 +
3577 + case ALLOW_MEDIUM_REMOVAL:
3578 + fsg->data_size_from_cmnd = 0;
3579 + if ((reply = check_command(fsg, 6, DATA_DIR_NONE,
3580 + (1<<4), 0,
3581 + "PREVENT-ALLOW MEDIUM REMOVAL")) == 0)
3582 + reply = do_prevent_allow(fsg);
3583 + break;
3584 +
3585 + case READ_6:
3586 + i = fsg->cmnd[4];
3587 + fsg->data_size_from_cmnd = (i == 0) ? 256 : i;
3588 + if ((reply = check_command_size_in_blocks(fsg, 6,
3589 + DATA_DIR_TO_HOST,
3590 + (7<<1) | (1<<4), 1,
3591 + "READ(6)")) == 0)
3592 + reply = do_read(fsg);
3593 + break;
3594 +
3595 + case READ_10:
3596 + fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
3597 + if ((reply = check_command_size_in_blocks(fsg, 10,
3598 + DATA_DIR_TO_HOST,
3599 + (1<<1) | (0xf<<2) | (3<<7), 1,
3600 + "READ(10)")) == 0)
3601 + reply = do_read(fsg);
3602 + break;
3603 +
3604 + case READ_12:
3605 + fsg->data_size_from_cmnd = get_unaligned_be32(&fsg->cmnd[6]);
3606 + if ((reply = check_command_size_in_blocks(fsg, 12,
3607 + DATA_DIR_TO_HOST,
3608 + (1<<1) | (0xf<<2) | (0xf<<6), 1,
3609 + "READ(12)")) == 0)
3610 + reply = do_read(fsg);
3611 + break;
3612 +
3613 + case READ_CAPACITY:
3614 + fsg->data_size_from_cmnd = 8;
3615 + if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
3616 + (0xf<<2) | (1<<8), 1,
3617 + "READ CAPACITY")) == 0)
3618 + reply = do_read_capacity(fsg, bh);
3619 + break;
3620 +
3621 + case READ_HEADER:
3622 + if (!mod_data.cdrom)
3623 + goto unknown_cmnd;
3624 + fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
3625 + if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
3626 + (3<<7) | (0x1f<<1), 1,
3627 + "READ HEADER")) == 0)
3628 + reply = do_read_header(fsg, bh);
3629 + break;
3630 +
3631 + case READ_TOC:
3632 + if (!mod_data.cdrom)
3633 + goto unknown_cmnd;
3634 + fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
3635 + if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
3636 + (7<<6) | (1<<1), 1,
3637 + "READ TOC")) == 0)
3638 + reply = do_read_toc(fsg, bh);
3639 + break;
3640 +
3641 + case READ_FORMAT_CAPACITIES:
3642 + fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
3643 + if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
3644 + (3<<7), 1,
3645 + "READ FORMAT CAPACITIES")) == 0)
3646 + reply = do_read_format_capacities(fsg, bh);
3647 + break;
3648 +
3649 + case REQUEST_SENSE:
3650 + fsg->data_size_from_cmnd = fsg->cmnd[4];
3651 + if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
3652 + (1<<4), 0,
3653 + "REQUEST SENSE")) == 0)
3654 + reply = do_request_sense(fsg, bh);
3655 + break;
3656 +
3657 + case START_STOP:
3658 + fsg->data_size_from_cmnd = 0;
3659 + if ((reply = check_command(fsg, 6, DATA_DIR_NONE,
3660 + (1<<1) | (1<<4), 0,
3661 + "START-STOP UNIT")) == 0)
3662 + reply = do_start_stop(fsg);
3663 + break;
3664 +
3665 + case SYNCHRONIZE_CACHE:
3666 + fsg->data_size_from_cmnd = 0;
3667 + if ((reply = check_command(fsg, 10, DATA_DIR_NONE,
3668 + (0xf<<2) | (3<<7), 1,
3669 + "SYNCHRONIZE CACHE")) == 0)
3670 + reply = do_synchronize_cache(fsg);
3671 + break;
3672 +
3673 + case TEST_UNIT_READY:
3674 + fsg->data_size_from_cmnd = 0;
3675 + reply = check_command(fsg, 6, DATA_DIR_NONE,
3676 + 0, 1,
3677 + "TEST UNIT READY");
3678 + break;
3679 +
3680 + /* Although optional, this command is used by MS-Windows. We
3681 + * support a minimal version: BytChk must be 0. */
3682 + case VERIFY:
3683 + fsg->data_size_from_cmnd = 0;
3684 + if ((reply = check_command(fsg, 10, DATA_DIR_NONE,
3685 + (1<<1) | (0xf<<2) | (3<<7), 1,
3686 + "VERIFY")) == 0)
3687 + reply = do_verify(fsg);
3688 + break;
3689 +
3690 + case WRITE_6:
3691 + i = fsg->cmnd[4];
3692 + fsg->data_size_from_cmnd = (i == 0) ? 256 : i;
3693 + if ((reply = check_command_size_in_blocks(fsg, 6,
3694 + DATA_DIR_FROM_HOST,
3695 + (7<<1) | (1<<4), 1,
3696 + "WRITE(6)")) == 0)
3697 + reply = do_write(fsg);
3698 + break;
3699 +
3700 + case WRITE_10:
3701 + fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
3702 + if ((reply = check_command_size_in_blocks(fsg, 10,
3703 + DATA_DIR_FROM_HOST,
3704 + (1<<1) | (0xf<<2) | (3<<7), 1,
3705 + "WRITE(10)")) == 0)
3706 + reply = do_write(fsg);
3707 + break;
3708 +
3709 + case WRITE_12:
3710 + fsg->data_size_from_cmnd = get_unaligned_be32(&fsg->cmnd[6]);
3711 + if ((reply = check_command_size_in_blocks(fsg, 12,
3712 + DATA_DIR_FROM_HOST,
3713 + (1<<1) | (0xf<<2) | (0xf<<6), 1,
3714 + "WRITE(12)")) == 0)
3715 + reply = do_write(fsg);
3716 + break;
3717 +
3718 + /* Some mandatory commands that we recognize but don't implement.
3719 + * They don't mean much in this setting. It's left as an exercise
3720 + * for anyone interested to implement RESERVE and RELEASE in terms
3721 + * of Posix locks. */
3722 + case FORMAT_UNIT:
3723 + case RELEASE:
3724 + case RESERVE:
3725 + case SEND_DIAGNOSTIC:
3726 + // Fall through
3727 +
3728 + default:
3729 + unknown_cmnd:
3730 + fsg->data_size_from_cmnd = 0;
3731 + sprintf(unknown, "Unknown x%02x", fsg->cmnd[0]);
3732 + if ((reply = check_command(fsg, fsg->cmnd_size,
3733 + DATA_DIR_UNKNOWN, ~0, 0, unknown)) == 0) {
3734 + fsg->curlun->sense_data = SS_INVALID_COMMAND;
3735 + reply = -EINVAL;
3736 + }
3737 + break;
3738 + }
3739 + up_read(&fsg->filesem);
3740 +
3741 + if (reply == -EINTR || signal_pending(current))
3742 + return -EINTR;
3743 +
3744 + /* Set up the single reply buffer for finish_reply() */
3745 + if (reply == -EINVAL)
3746 + reply = 0; // Error reply length
3747 + if (reply >= 0 && fsg->data_dir == DATA_DIR_TO_HOST) {
3748 + reply = min((u32) reply, fsg->data_size_from_cmnd);
3749 + bh->inreq->length = reply;
3750 + bh->state = BUF_STATE_FULL;
3751 + fsg->residue -= reply;
3752 + } // Otherwise it's already set
3753 +
3754 + return 0;
3755 +}
3756 +
3757 +
3758 +/*-------------------------------------------------------------------------*/
3759 +
3760 +static int received_cbw(struct fsg_dev *fsg, struct fsg_buffhd *bh)
3761 +{
3762 + struct usb_request *req = bh->outreq;
3763 + struct bulk_cb_wrap *cbw = req->buf;
3764 +
3765 + /* Was this a real packet? Should it be ignored? */
3766 + if (req->status || test_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags))
3767 + return -EINVAL;
3768 +
3769 + /* Is the CBW valid? */
3770 + if (req->actual != US_BULK_CB_WRAP_LEN ||
3771 + cbw->Signature != cpu_to_le32(
3772 + US_BULK_CB_SIGN)) {
3773 + DBG(fsg, "invalid CBW: len %u sig 0x%x\n",
3774 + req->actual,
3775 + le32_to_cpu(cbw->Signature));
3776 +
3777 + /* The Bulk-only spec says we MUST stall the IN endpoint
3778 + * (6.6.1), so it's unavoidable. It also says we must
3779 + * retain this state until the next reset, but there's
3780 + * no way to tell the controller driver it should ignore
3781 + * Clear-Feature(HALT) requests.
3782 + *
3783 + * We aren't required to halt the OUT endpoint; instead
3784 + * we can simply accept and discard any data received
3785 + * until the next reset. */
3786 + wedge_bulk_in_endpoint(fsg);
3787 + set_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags);
3788 + return -EINVAL;
3789 + }
3790 +
3791 + /* Is the CBW meaningful? */
3792 + if (cbw->Lun >= FSG_MAX_LUNS || cbw->Flags & ~US_BULK_FLAG_IN ||
3793 + cbw->Length <= 0 || cbw->Length > MAX_COMMAND_SIZE) {
3794 + DBG(fsg, "non-meaningful CBW: lun = %u, flags = 0x%x, "
3795 + "cmdlen %u\n",
3796 + cbw->Lun, cbw->Flags, cbw->Length);
3797 +
3798 + /* We can do anything we want here, so let's stall the
3799 + * bulk pipes if we are allowed to. */
3800 + if (mod_data.can_stall) {
3801 + fsg_set_halt(fsg, fsg->bulk_out);
3802 + halt_bulk_in_endpoint(fsg);
3803 + }
3804 + return -EINVAL;
3805 + }
3806 +
3807 + /* Save the command for later */
3808 + fsg->cmnd_size = cbw->Length;
3809 + memcpy(fsg->cmnd, cbw->CDB, fsg->cmnd_size);
3810 + if (cbw->Flags & US_BULK_FLAG_IN)
3811 + fsg->data_dir = DATA_DIR_TO_HOST;
3812 + else
3813 + fsg->data_dir = DATA_DIR_FROM_HOST;
3814 + fsg->data_size = le32_to_cpu(cbw->DataTransferLength);
3815 + if (fsg->data_size == 0)
3816 + fsg->data_dir = DATA_DIR_NONE;
3817 + fsg->lun = cbw->Lun;
3818 + fsg->tag = cbw->Tag;
3819 + return 0;
3820 +}
3821 +
3822 +
3823 +static int get_next_command(struct fsg_dev *fsg)
3824 +{
3825 + struct fsg_buffhd *bh;
3826 + int rc = 0;
3827 +
3828 + if (transport_is_bbb()) {
3829 +
3830 + /* Wait for the next buffer to become available */
3831 + bh = fsg->next_buffhd_to_fill;
3832 + while (bh->state != BUF_STATE_EMPTY) {
3833 + rc = sleep_thread(fsg);
3834 + if (rc)
3835 + return rc;
3836 + }
3837 +
3838 + /* Queue a request to read a Bulk-only CBW */
3839 + set_bulk_out_req_length(fsg, bh, US_BULK_CB_WRAP_LEN);
3840 + start_transfer(fsg, fsg->bulk_out, bh->outreq,
3841 + &bh->outreq_busy, &bh->state);
3842 +
3843 + /* We will drain the buffer in software, which means we
3844 + * can reuse it for the next filling. No need to advance
3845 + * next_buffhd_to_fill. */
3846 +
3847 + /* Wait for the CBW to arrive */
3848 + while (bh->state != BUF_STATE_FULL) {
3849 + rc = sleep_thread(fsg);
3850 + if (rc)
3851 + return rc;
3852 + }
3853 + smp_rmb();
3854 + rc = received_cbw(fsg, bh);
3855 + bh->state = BUF_STATE_EMPTY;
3856 +
3857 + } else { // USB_PR_CB or USB_PR_CBI
3858 +
3859 + /* Wait for the next command to arrive */
3860 + while (fsg->cbbuf_cmnd_size == 0) {
3861 + rc = sleep_thread(fsg);
3862 + if (rc)
3863 + return rc;
3864 + }
3865 +
3866 + /* Is the previous status interrupt request still busy?
3867 + * The host is allowed to skip reading the status,
3868 + * so we must cancel it. */
3869 + if (fsg->intreq_busy)
3870 + usb_ep_dequeue(fsg->intr_in, fsg->intreq);
3871 +
3872 + /* Copy the command and mark the buffer empty */
3873 + fsg->data_dir = DATA_DIR_UNKNOWN;
3874 + spin_lock_irq(&fsg->lock);
3875 + fsg->cmnd_size = fsg->cbbuf_cmnd_size;
3876 + memcpy(fsg->cmnd, fsg->cbbuf_cmnd, fsg->cmnd_size);
3877 + fsg->cbbuf_cmnd_size = 0;
3878 + spin_unlock_irq(&fsg->lock);
3879 +
3880 + /* Use LUN from the command */
3881 + fsg->lun = fsg->cmnd[1] >> 5;
3882 + }
3883 +
3884 + /* Update current lun */
3885 + if (fsg->lun >= 0 && fsg->lun < fsg->nluns)
3886 + fsg->curlun = &fsg->luns[fsg->lun];
3887 + else
3888 + fsg->curlun = NULL;
3889 +
3890 + return rc;
3891 +}
3892 +
3893 +
3894 +/*-------------------------------------------------------------------------*/
3895 +
3896 +static int enable_endpoint(struct fsg_dev *fsg, struct usb_ep *ep,
3897 + const struct usb_endpoint_descriptor *d)
3898 +{
3899 + int rc;
3900 +
3901 + ep->driver_data = fsg;
3902 + ep->desc = d;
3903 + rc = usb_ep_enable(ep);
3904 + if (rc)
3905 + ERROR(fsg, "can't enable %s, result %d\n", ep->name, rc);
3906 + return rc;
3907 +}
3908 +
3909 +static int alloc_request(struct fsg_dev *fsg, struct usb_ep *ep,
3910 + struct usb_request **preq)
3911 +{
3912 + *preq = usb_ep_alloc_request(ep, GFP_ATOMIC);
3913 + if (*preq)
3914 + return 0;
3915 + ERROR(fsg, "can't allocate request for %s\n", ep->name);
3916 + return -ENOMEM;
3917 +}
3918 +
3919 +/*
3920 + * Reset interface setting and re-init endpoint state (toggle etc).
3921 + * Call with altsetting < 0 to disable the interface. The only other
3922 + * available altsetting is 0, which enables the interface.
3923 + */
3924 +static int do_set_interface(struct fsg_dev *fsg, int altsetting)
3925 +{
3926 + int rc = 0;
3927 + int i;
3928 + const struct usb_endpoint_descriptor *d;
3929 +
3930 + if (fsg->running)
3931 + DBG(fsg, "reset interface\n");
3932 +
3933 +reset:
3934 + /* Deallocate the requests */
3935 + for (i = 0; i < fsg_num_buffers; ++i) {
3936 + struct fsg_buffhd *bh = &fsg->buffhds[i];
3937 +
3938 + if (bh->inreq) {
3939 + usb_ep_free_request(fsg->bulk_in, bh->inreq);
3940 + bh->inreq = NULL;
3941 + }
3942 + if (bh->outreq) {
3943 + usb_ep_free_request(fsg->bulk_out, bh->outreq);
3944 + bh->outreq = NULL;
3945 + }
3946 + }
3947 + if (fsg->intreq) {
3948 + usb_ep_free_request(fsg->intr_in, fsg->intreq);
3949 + fsg->intreq = NULL;
3950 + }
3951 +
3952 + /* Disable the endpoints */
3953 + if (fsg->bulk_in_enabled) {
3954 + usb_ep_disable(fsg->bulk_in);
3955 + fsg->bulk_in_enabled = 0;
3956 + }
3957 + if (fsg->bulk_out_enabled) {
3958 + usb_ep_disable(fsg->bulk_out);
3959 + fsg->bulk_out_enabled = 0;
3960 + }
3961 + if (fsg->intr_in_enabled) {
3962 + usb_ep_disable(fsg->intr_in);
3963 + fsg->intr_in_enabled = 0;
3964 + }
3965 +
3966 + fsg->running = 0;
3967 + if (altsetting < 0 || rc != 0)
3968 + return rc;
3969 +
3970 + DBG(fsg, "set interface %d\n", altsetting);
3971 +
3972 + /* Enable the endpoints */
3973 + d = fsg_ep_desc(fsg->gadget,
3974 + &fsg_fs_bulk_in_desc, &fsg_hs_bulk_in_desc,
3975 + &fsg_ss_bulk_in_desc);
3976 + if ((rc = enable_endpoint(fsg, fsg->bulk_in, d)) != 0)
3977 + goto reset;
3978 + fsg->bulk_in_enabled = 1;
3979 +
3980 + d = fsg_ep_desc(fsg->gadget,
3981 + &fsg_fs_bulk_out_desc, &fsg_hs_bulk_out_desc,
3982 + &fsg_ss_bulk_out_desc);
3983 + if ((rc = enable_endpoint(fsg, fsg->bulk_out, d)) != 0)
3984 + goto reset;
3985 + fsg->bulk_out_enabled = 1;
3986 + fsg->bulk_out_maxpacket = usb_endpoint_maxp(d);
3987 + clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags);
3988 +
3989 + if (transport_is_cbi()) {
3990 + d = fsg_ep_desc(fsg->gadget,
3991 + &fsg_fs_intr_in_desc, &fsg_hs_intr_in_desc,
3992 + &fsg_ss_intr_in_desc);
3993 + if ((rc = enable_endpoint(fsg, fsg->intr_in, d)) != 0)
3994 + goto reset;
3995 + fsg->intr_in_enabled = 1;
3996 + }
3997 +
3998 + /* Allocate the requests */
3999 + for (i = 0; i < fsg_num_buffers; ++i) {
4000 + struct fsg_buffhd *bh = &fsg->buffhds[i];
4001 +
4002 + if ((rc = alloc_request(fsg, fsg->bulk_in, &bh->inreq)) != 0)
4003 + goto reset;
4004 + if ((rc = alloc_request(fsg, fsg->bulk_out, &bh->outreq)) != 0)
4005 + goto reset;
4006 + bh->inreq->buf = bh->outreq->buf = bh->buf;
4007 + bh->inreq->context = bh->outreq->context = bh;
4008 + bh->inreq->complete = bulk_in_complete;
4009 + bh->outreq->complete = bulk_out_complete;
4010 + }
4011 + if (transport_is_cbi()) {
4012 + if ((rc = alloc_request(fsg, fsg->intr_in, &fsg->intreq)) != 0)
4013 + goto reset;
4014 + fsg->intreq->complete = intr_in_complete;
4015 + }
4016 +
4017 + fsg->running = 1;
4018 + for (i = 0; i < fsg->nluns; ++i)
4019 + fsg->luns[i].unit_attention_data = SS_RESET_OCCURRED;
4020 + return rc;
4021 +}
4022 +
4023 +
4024 +/*
4025 + * Change our operational configuration. This code must agree with the code
4026 + * that returns config descriptors, and with interface altsetting code.
4027 + *
4028 + * It's also responsible for power management interactions. Some
4029 + * configurations might not work with our current power sources.
4030 + * For now we just assume the gadget is always self-powered.
4031 + */
4032 +static int do_set_config(struct fsg_dev *fsg, u8 new_config)
4033 +{
4034 + int rc = 0;
4035 +
4036 + /* Disable the single interface */
4037 + if (fsg->config != 0) {
4038 + DBG(fsg, "reset config\n");
4039 + fsg->config = 0;
4040 + rc = do_set_interface(fsg, -1);
4041 + }
4042 +
4043 + /* Enable the interface */
4044 + if (new_config != 0) {
4045 + fsg->config = new_config;
4046 + if ((rc = do_set_interface(fsg, 0)) != 0)
4047 + fsg->config = 0; // Reset on errors
4048 + else
4049 + INFO(fsg, "%s config #%d\n",
4050 + usb_speed_string(fsg->gadget->speed),
4051 + fsg->config);
4052 + }
4053 + return rc;
4054 +}
4055 +
4056 +
4057 +/*-------------------------------------------------------------------------*/
4058 +
4059 +static void handle_exception(struct fsg_dev *fsg)
4060 +{
4061 + siginfo_t info;
4062 + int sig;
4063 + int i;
4064 + int num_active;
4065 + struct fsg_buffhd *bh;
4066 + enum fsg_state old_state;
4067 + u8 new_config;
4068 + struct fsg_lun *curlun;
4069 + unsigned int exception_req_tag;
4070 + int rc;
4071 +
4072 + /* Clear the existing signals. Anything but SIGUSR1 is converted
4073 + * into a high-priority EXIT exception. */
4074 + for (;;) {
4075 + sig = dequeue_signal_lock(current, &current->blocked, &info);
4076 + if (!sig)
4077 + break;
4078 + if (sig != SIGUSR1) {
4079 + if (fsg->state < FSG_STATE_EXIT)
4080 + DBG(fsg, "Main thread exiting on signal\n");
4081 + raise_exception(fsg, FSG_STATE_EXIT);
4082 + }
4083 + }
4084 +
4085 + /* Cancel all the pending transfers */
4086 + if (fsg->intreq_busy)
4087 + usb_ep_dequeue(fsg->intr_in, fsg->intreq);
4088 + for (i = 0; i < fsg_num_buffers; ++i) {
4089 + bh = &fsg->buffhds[i];
4090 + if (bh->inreq_busy)
4091 + usb_ep_dequeue(fsg->bulk_in, bh->inreq);
4092 + if (bh->outreq_busy)
4093 + usb_ep_dequeue(fsg->bulk_out, bh->outreq);
4094 + }
4095 +
4096 + /* Wait until everything is idle */
4097 + for (;;) {
4098 + num_active = fsg->intreq_busy;
4099 + for (i = 0; i < fsg_num_buffers; ++i) {
4100 + bh = &fsg->buffhds[i];
4101 + num_active += bh->inreq_busy + bh->outreq_busy;
4102 + }
4103 + if (num_active == 0)
4104 + break;
4105 + if (sleep_thread(fsg))
4106 + return;
4107 + }
4108 +
4109 + /* Clear out the controller's fifos */
4110 + if (fsg->bulk_in_enabled)
4111 + usb_ep_fifo_flush(fsg->bulk_in);
4112 + if (fsg->bulk_out_enabled)
4113 + usb_ep_fifo_flush(fsg->bulk_out);
4114 + if (fsg->intr_in_enabled)
4115 + usb_ep_fifo_flush(fsg->intr_in);
4116 +
4117 + /* Reset the I/O buffer states and pointers, the SCSI
4118 + * state, and the exception. Then invoke the handler. */
4119 + spin_lock_irq(&fsg->lock);
4120 +
4121 + for (i = 0; i < fsg_num_buffers; ++i) {
4122 + bh = &fsg->buffhds[i];
4123 + bh->state = BUF_STATE_EMPTY;
4124 + }
4125 + fsg->next_buffhd_to_fill = fsg->next_buffhd_to_drain =
4126 + &fsg->buffhds[0];
4127 +
4128 + exception_req_tag = fsg->exception_req_tag;
4129 + new_config = fsg->new_config;
4130 + old_state = fsg->state;
4131 +
4132 + if (old_state == FSG_STATE_ABORT_BULK_OUT)
4133 + fsg->state = FSG_STATE_STATUS_PHASE;
4134 + else {
4135 + for (i = 0; i < fsg->nluns; ++i) {
4136 + curlun = &fsg->luns[i];
4137 + curlun->prevent_medium_removal = 0;
4138 + curlun->sense_data = curlun->unit_attention_data =
4139 + SS_NO_SENSE;
4140 + curlun->sense_data_info = 0;
4141 + curlun->info_valid = 0;
4142 + }
4143 + fsg->state = FSG_STATE_IDLE;
4144 + }
4145 + spin_unlock_irq(&fsg->lock);
4146 +
4147 + /* Carry out any extra actions required for the exception */
4148 + switch (old_state) {
4149 + default:
4150 + break;
4151 +
4152 + case FSG_STATE_ABORT_BULK_OUT:
4153 + send_status(fsg);
4154 + spin_lock_irq(&fsg->lock);
4155 + if (fsg->state == FSG_STATE_STATUS_PHASE)
4156 + fsg->state = FSG_STATE_IDLE;
4157 + spin_unlock_irq(&fsg->lock);
4158 + break;
4159 +
4160 + case FSG_STATE_RESET:
4161 + /* In case we were forced against our will to halt a
4162 + * bulk endpoint, clear the halt now. (The SuperH UDC
4163 + * requires this.) */
4164 + if (test_and_clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags))
4165 + usb_ep_clear_halt(fsg->bulk_in);
4166 +
4167 + if (transport_is_bbb()) {
4168 + if (fsg->ep0_req_tag == exception_req_tag)
4169 + ep0_queue(fsg); // Complete the status stage
4170 +
4171 + } else if (transport_is_cbi())
4172 + send_status(fsg); // Status by interrupt pipe
4173 +
4174 + /* Technically this should go here, but it would only be
4175 + * a waste of time. Ditto for the INTERFACE_CHANGE and
4176 + * CONFIG_CHANGE cases. */
4177 + // for (i = 0; i < fsg->nluns; ++i)
4178 + // fsg->luns[i].unit_attention_data = SS_RESET_OCCURRED;
4179 + break;
4180 +
4181 + case FSG_STATE_INTERFACE_CHANGE:
4182 + rc = do_set_interface(fsg, 0);
4183 + if (fsg->ep0_req_tag != exception_req_tag)
4184 + break;
4185 + if (rc != 0) // STALL on errors
4186 + fsg_set_halt(fsg, fsg->ep0);
4187 + else // Complete the status stage
4188 + ep0_queue(fsg);
4189 + break;
4190 +
4191 + case FSG_STATE_CONFIG_CHANGE:
4192 + rc = do_set_config(fsg, new_config);
4193 + if (fsg->ep0_req_tag != exception_req_tag)
4194 + break;
4195 + if (rc != 0) // STALL on errors
4196 + fsg_set_halt(fsg, fsg->ep0);
4197 + else // Complete the status stage
4198 + ep0_queue(fsg);
4199 + break;
4200 +
4201 + case FSG_STATE_DISCONNECT:
4202 + for (i = 0; i < fsg->nluns; ++i)
4203 + fsg_lun_fsync_sub(fsg->luns + i);
4204 + do_set_config(fsg, 0); // Unconfigured state
4205 + break;
4206 +
4207 + case FSG_STATE_EXIT:
4208 + case FSG_STATE_TERMINATED:
4209 + do_set_config(fsg, 0); // Free resources
4210 + spin_lock_irq(&fsg->lock);
4211 + fsg->state = FSG_STATE_TERMINATED; // Stop the thread
4212 + spin_unlock_irq(&fsg->lock);
4213 + break;
4214 + }
4215 +}
4216 +
4217 +
4218 +/*-------------------------------------------------------------------------*/
4219 +
4220 +static int fsg_main_thread(void *fsg_)
4221 +{
4222 + struct fsg_dev *fsg = fsg_;
4223 +
4224 + /* Allow the thread to be killed by a signal, but set the signal mask
4225 + * to block everything but INT, TERM, KILL, and USR1. */
4226 + allow_signal(SIGINT);
4227 + allow_signal(SIGTERM);
4228 + allow_signal(SIGKILL);
4229 + allow_signal(SIGUSR1);
4230 +
4231 + /* Allow the thread to be frozen */
4232 + set_freezable();
4233 +
4234 + /* Arrange for userspace references to be interpreted as kernel
4235 + * pointers. That way we can pass a kernel pointer to a routine
4236 + * that expects a __user pointer and it will work okay. */
4237 + set_fs(get_ds());
4238 +
4239 + /* The main loop */
4240 + while (fsg->state != FSG_STATE_TERMINATED) {
4241 + if (exception_in_progress(fsg) || signal_pending(current)) {
4242 + handle_exception(fsg);
4243 + continue;
4244 + }
4245 +
4246 + if (!fsg->running) {
4247 + sleep_thread(fsg);
4248 + continue;
4249 + }
4250 +
4251 + if (get_next_command(fsg))
4252 + continue;
4253 +
4254 + spin_lock_irq(&fsg->lock);
4255 + if (!exception_in_progress(fsg))
4256 + fsg->state = FSG_STATE_DATA_PHASE;
4257 + spin_unlock_irq(&fsg->lock);
4258 +
4259 + if (do_scsi_command(fsg) || finish_reply(fsg))
4260 + continue;
4261 +
4262 + spin_lock_irq(&fsg->lock);
4263 + if (!exception_in_progress(fsg))
4264 + fsg->state = FSG_STATE_STATUS_PHASE;
4265 + spin_unlock_irq(&fsg->lock);
4266 +
4267 + if (send_status(fsg))
4268 + continue;
4269 +
4270 + spin_lock_irq(&fsg->lock);
4271 + if (!exception_in_progress(fsg))
4272 + fsg->state = FSG_STATE_IDLE;
4273 + spin_unlock_irq(&fsg->lock);
4274 + }
4275 +
4276 + spin_lock_irq(&fsg->lock);
4277 + fsg->thread_task = NULL;
4278 + spin_unlock_irq(&fsg->lock);
4279 +
4280 + /* If we are exiting because of a signal, unregister the
4281 + * gadget driver. */
4282 + if (test_and_clear_bit(REGISTERED, &fsg->atomic_bitflags))
4283 + usb_gadget_unregister_driver(&fsg_driver);
4284 +
4285 + /* Let the unbind and cleanup routines know the thread has exited */
4286 + complete_and_exit(&fsg->thread_notifier, 0);
4287 +}
4288 +
4289 +
4290 +/*-------------------------------------------------------------------------*/
4291 +
4292 +
4293 +/* The write permissions and store_xxx pointers are set in fsg_bind() */
4294 +static DEVICE_ATTR(ro, 0444, fsg_show_ro, NULL);
4295 +static DEVICE_ATTR(nofua, 0644, fsg_show_nofua, NULL);
4296 +static DEVICE_ATTR(file, 0444, fsg_show_file, NULL);
4297 +
4298 +
4299 +/*-------------------------------------------------------------------------*/
4300 +
4301 +static void fsg_release(struct kref *ref)
4302 +{
4303 + struct fsg_dev *fsg = container_of(ref, struct fsg_dev, ref);
4304 +
4305 + kfree(fsg->luns);
4306 + kfree(fsg);
4307 +}
4308 +
4309 +static void lun_release(struct device *dev)
4310 +{
4311 + struct rw_semaphore *filesem = dev_get_drvdata(dev);
4312 + struct fsg_dev *fsg =
4313 + container_of(filesem, struct fsg_dev, filesem);
4314 +
4315 + kref_put(&fsg->ref, fsg_release);
4316 +}
4317 +
4318 +static void /* __init_or_exit */ fsg_unbind(struct usb_gadget *gadget)
4319 +{
4320 + struct fsg_dev *fsg = get_gadget_data(gadget);
4321 + int i;
4322 + struct fsg_lun *curlun;
4323 + struct usb_request *req = fsg->ep0req;
4324 +
4325 + DBG(fsg, "unbind\n");
4326 + clear_bit(REGISTERED, &fsg->atomic_bitflags);
4327 +
4328 + /* If the thread isn't already dead, tell it to exit now */
4329 + if (fsg->state != FSG_STATE_TERMINATED) {
4330 + raise_exception(fsg, FSG_STATE_EXIT);
4331 + wait_for_completion(&fsg->thread_notifier);
4332 +
4333 + /* The cleanup routine waits for this completion also */
4334 + complete(&fsg->thread_notifier);
4335 + }
4336 +
4337 + /* Unregister the sysfs attribute files and the LUNs */
4338 + for (i = 0; i < fsg->nluns; ++i) {
4339 + curlun = &fsg->luns[i];
4340 + if (curlun->registered) {
4341 + device_remove_file(&curlun->dev, &dev_attr_nofua);
4342 + device_remove_file(&curlun->dev, &dev_attr_ro);
4343 + device_remove_file(&curlun->dev, &dev_attr_file);
4344 + fsg_lun_close(curlun);
4345 + device_unregister(&curlun->dev);
4346 + curlun->registered = 0;
4347 + }
4348 + }
4349 +
4350 + /* Free the data buffers */
4351 + for (i = 0; i < fsg_num_buffers; ++i)
4352 + kfree(fsg->buffhds[i].buf);
4353 +
4354 + /* Free the request and buffer for endpoint 0 */
4355 + if (req) {
4356 + kfree(req->buf);
4357 + usb_ep_free_request(fsg->ep0, req);
4358 + }
4359 +
4360 + set_gadget_data(gadget, NULL);
4361 +}
4362 +
4363 +
4364 +static int __init check_parameters(struct fsg_dev *fsg)
4365 +{
4366 + int prot;
4367 + int gcnum;
4368 +
4369 + /* Store the default values */
4370 + mod_data.transport_type = USB_PR_BULK;
4371 + mod_data.transport_name = "Bulk-only";
4372 + mod_data.protocol_type = USB_SC_SCSI;
4373 + mod_data.protocol_name = "Transparent SCSI";
4374 +
4375 + /* Some peripheral controllers are known not to be able to
4376 + * halt bulk endpoints correctly. If one of them is present,
4377 + * disable stalls.
4378 + */
4379 + if (gadget_is_at91(fsg->gadget))
4380 + mod_data.can_stall = 0;
4381 +
4382 + if (mod_data.release == 0xffff) { // Parameter wasn't set
4383 + gcnum = usb_gadget_controller_number(fsg->gadget);
4384 + if (gcnum >= 0)
4385 + mod_data.release = 0x0300 + gcnum;
4386 + else {
4387 + WARNING(fsg, "controller '%s' not recognized\n",
4388 + fsg->gadget->name);
4389 + mod_data.release = 0x0399;
4390 + }
4391 + }
4392 +
4393 + prot = simple_strtol(mod_data.protocol_parm, NULL, 0);
4394 +
4395 +#ifdef CONFIG_USB_FILE_STORAGE_TEST
4396 + if (strnicmp(mod_data.transport_parm, "BBB", 10) == 0) {
4397 + ; // Use default setting
4398 + } else if (strnicmp(mod_data.transport_parm, "CB", 10) == 0) {
4399 + mod_data.transport_type = USB_PR_CB;
4400 + mod_data.transport_name = "Control-Bulk";
4401 + } else if (strnicmp(mod_data.transport_parm, "CBI", 10) == 0) {
4402 + mod_data.transport_type = USB_PR_CBI;
4403 + mod_data.transport_name = "Control-Bulk-Interrupt";
4404 + } else {
4405 + ERROR(fsg, "invalid transport: %s\n", mod_data.transport_parm);
4406 + return -EINVAL;
4407 + }
4408 +
4409 + if (strnicmp(mod_data.protocol_parm, "SCSI", 10) == 0 ||
4410 + prot == USB_SC_SCSI) {
4411 + ; // Use default setting
4412 + } else if (strnicmp(mod_data.protocol_parm, "RBC", 10) == 0 ||
4413 + prot == USB_SC_RBC) {
4414 + mod_data.protocol_type = USB_SC_RBC;
4415 + mod_data.protocol_name = "RBC";
4416 + } else if (strnicmp(mod_data.protocol_parm, "8020", 4) == 0 ||
4417 + strnicmp(mod_data.protocol_parm, "ATAPI", 10) == 0 ||
4418 + prot == USB_SC_8020) {
4419 + mod_data.protocol_type = USB_SC_8020;
4420 + mod_data.protocol_name = "8020i (ATAPI)";
4421 + } else if (strnicmp(mod_data.protocol_parm, "QIC", 3) == 0 ||
4422 + prot == USB_SC_QIC) {
4423 + mod_data.protocol_type = USB_SC_QIC;
4424 + mod_data.protocol_name = "QIC-157";
4425 + } else if (strnicmp(mod_data.protocol_parm, "UFI", 10) == 0 ||
4426 + prot == USB_SC_UFI) {
4427 + mod_data.protocol_type = USB_SC_UFI;
4428 + mod_data.protocol_name = "UFI";
4429 + } else if (strnicmp(mod_data.protocol_parm, "8070", 4) == 0 ||
4430 + prot == USB_SC_8070) {
4431 + mod_data.protocol_type = USB_SC_8070;
4432 + mod_data.protocol_name = "8070i";
4433 + } else {
4434 + ERROR(fsg, "invalid protocol: %s\n", mod_data.protocol_parm);
4435 + return -EINVAL;
4436 + }
4437 +
4438 + mod_data.buflen &= PAGE_CACHE_MASK;
4439 + if (mod_data.buflen <= 0) {
4440 + ERROR(fsg, "invalid buflen\n");
4441 + return -ETOOSMALL;
4442 + }
4443 +
4444 +#endif /* CONFIG_USB_FILE_STORAGE_TEST */
4445 +
4446 + /* Serial string handling.
4447 + * On a real device, the serial string would be loaded
4448 + * from permanent storage. */
4449 + if (mod_data.serial) {
4450 + const char *ch;
4451 + unsigned len = 0;
4452 +
4453 + /* Sanity check :
4454 + * The CB[I] specification limits the serial string to
4455 + * 12 uppercase hexadecimal characters.
4456 + * BBB need at least 12 uppercase hexadecimal characters,
4457 + * with a maximum of 126. */
4458 + for (ch = mod_data.serial; *ch; ++ch) {
4459 + ++len;
4460 + if ((*ch < '0' || *ch > '9') &&
4461 + (*ch < 'A' || *ch > 'F')) { /* not uppercase hex */
4462 + WARNING(fsg,
4463 + "Invalid serial string character: %c\n",
4464 + *ch);
4465 + goto no_serial;
4466 + }
4467 + }
4468 + if (len > 126 ||
4469 + (mod_data.transport_type == USB_PR_BULK && len < 12) ||
4470 + (mod_data.transport_type != USB_PR_BULK && len > 12)) {
4471 + WARNING(fsg, "Invalid serial string length!\n");
4472 + goto no_serial;
4473 + }
4474 + fsg_strings[FSG_STRING_SERIAL - 1].s = mod_data.serial;
4475 + } else {
4476 + WARNING(fsg, "No serial-number string provided!\n");
4477 + no_serial:
4478 + device_desc.iSerialNumber = 0;
4479 + }
4480 +
4481 + return 0;
4482 +}
4483 +
4484 +
4485 +static int __init fsg_bind(struct usb_gadget *gadget)
4486 +{
4487 + struct fsg_dev *fsg = the_fsg;
4488 + int rc;
4489 + int i;
4490 + struct fsg_lun *curlun;
4491 + struct usb_ep *ep;
4492 + struct usb_request *req;
4493 + char *pathbuf, *p;
4494 +
4495 + fsg->gadget = gadget;
4496 + set_gadget_data(gadget, fsg);
4497 + fsg->ep0 = gadget->ep0;
4498 + fsg->ep0->driver_data = fsg;
4499 +
4500 + if ((rc = check_parameters(fsg)) != 0)
4501 + goto out;
4502 +
4503 + if (mod_data.removable) { // Enable the store_xxx attributes
4504 + dev_attr_file.attr.mode = 0644;
4505 + dev_attr_file.store = fsg_store_file;
4506 + if (!mod_data.cdrom) {
4507 + dev_attr_ro.attr.mode = 0644;
4508 + dev_attr_ro.store = fsg_store_ro;
4509 + }
4510 + }
4511 +
4512 + /* Only for removable media? */
4513 + dev_attr_nofua.attr.mode = 0644;
4514 + dev_attr_nofua.store = fsg_store_nofua;
4515 +
4516 + /* Find out how many LUNs there should be */
4517 + i = mod_data.nluns;
4518 + if (i == 0)
4519 + i = max(mod_data.num_filenames, 1u);
4520 + if (i > FSG_MAX_LUNS) {
4521 + ERROR(fsg, "invalid number of LUNs: %d\n", i);
4522 + rc = -EINVAL;
4523 + goto out;
4524 + }
4525 +
4526 + /* Create the LUNs, open their backing files, and register the
4527 + * LUN devices in sysfs. */
4528 + fsg->luns = kzalloc(i * sizeof(struct fsg_lun), GFP_KERNEL);
4529 + if (!fsg->luns) {
4530 + rc = -ENOMEM;
4531 + goto out;
4532 + }
4533 + fsg->nluns = i;
4534 +
4535 + for (i = 0; i < fsg->nluns; ++i) {
4536 + curlun = &fsg->luns[i];
4537 + curlun->cdrom = !!mod_data.cdrom;
4538 + curlun->ro = mod_data.cdrom || mod_data.ro[i];
4539 + curlun->initially_ro = curlun->ro;
4540 + curlun->removable = mod_data.removable;
4541 + curlun->nofua = mod_data.nofua[i];
4542 + curlun->dev.release = lun_release;
4543 + curlun->dev.parent = &gadget->dev;
4544 + curlun->dev.driver = &fsg_driver.driver;
4545 + dev_set_drvdata(&curlun->dev, &fsg->filesem);
4546 + dev_set_name(&curlun->dev,"%s-lun%d",
4547 + dev_name(&gadget->dev), i);
4548 +
4549 + kref_get(&fsg->ref);
4550 + rc = device_register(&curlun->dev);
4551 + if (rc) {
4552 + INFO(fsg, "failed to register LUN%d: %d\n", i, rc);
4553 + put_device(&curlun->dev);
4554 + goto out;
4555 + }
4556 + curlun->registered = 1;
4557 +
4558 + rc = device_create_file(&curlun->dev, &dev_attr_ro);
4559 + if (rc)
4560 + goto out;
4561 + rc = device_create_file(&curlun->dev, &dev_attr_nofua);
4562 + if (rc)
4563 + goto out;
4564 + rc = device_create_file(&curlun->dev, &dev_attr_file);
4565 + if (rc)
4566 + goto out;
4567 +
4568 + if (mod_data.file[i] && *mod_data.file[i]) {
4569 + rc = fsg_lun_open(curlun, mod_data.file[i]);
4570 + if (rc)
4571 + goto out;
4572 + } else if (!mod_data.removable) {
4573 + ERROR(fsg, "no file given for LUN%d\n", i);
4574 + rc = -EINVAL;
4575 + goto out;
4576 + }
4577 + }
4578 +
4579 + /* Find all the endpoints we will use */
4580 + usb_ep_autoconfig_reset(gadget);
4581 + ep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_in_desc);
4582 + if (!ep)
4583 + goto autoconf_fail;
4584 + ep->driver_data = fsg; // claim the endpoint
4585 + fsg->bulk_in = ep;
4586 +
4587 + ep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_out_desc);
4588 + if (!ep)
4589 + goto autoconf_fail;
4590 + ep->driver_data = fsg; // claim the endpoint
4591 + fsg->bulk_out = ep;
4592 +
4593 + if (transport_is_cbi()) {
4594 + ep = usb_ep_autoconfig(gadget, &fsg_fs_intr_in_desc);
4595 + if (!ep)
4596 + goto autoconf_fail;
4597 + ep->driver_data = fsg; // claim the endpoint
4598 + fsg->intr_in = ep;
4599 + }
4600 +
4601 + /* Fix up the descriptors */
4602 + device_desc.idVendor = cpu_to_le16(mod_data.vendor);
4603 + device_desc.idProduct = cpu_to_le16(mod_data.product);
4604 + device_desc.bcdDevice = cpu_to_le16(mod_data.release);
4605 +
4606 + i = (transport_is_cbi() ? 3 : 2); // Number of endpoints
4607 + fsg_intf_desc.bNumEndpoints = i;
4608 + fsg_intf_desc.bInterfaceSubClass = mod_data.protocol_type;
4609 + fsg_intf_desc.bInterfaceProtocol = mod_data.transport_type;
4610 + fsg_fs_function[i + FSG_FS_FUNCTION_PRE_EP_ENTRIES] = NULL;
4611 +
4612 + if (gadget_is_dualspeed(gadget)) {
4613 + fsg_hs_function[i + FSG_HS_FUNCTION_PRE_EP_ENTRIES] = NULL;
4614 +
4615 + /* Assume endpoint addresses are the same for both speeds */
4616 + fsg_hs_bulk_in_desc.bEndpointAddress =
4617 + fsg_fs_bulk_in_desc.bEndpointAddress;
4618 + fsg_hs_bulk_out_desc.bEndpointAddress =
4619 + fsg_fs_bulk_out_desc.bEndpointAddress;
4620 + fsg_hs_intr_in_desc.bEndpointAddress =
4621 + fsg_fs_intr_in_desc.bEndpointAddress;
4622 + }
4623 +
4624 + if (gadget_is_superspeed(gadget)) {
4625 + unsigned max_burst;
4626 +
4627 + fsg_ss_function[i + FSG_SS_FUNCTION_PRE_EP_ENTRIES] = NULL;
4628 +
4629 + /* Calculate bMaxBurst, we know packet size is 1024 */
4630 + max_burst = min_t(unsigned, mod_data.buflen / 1024, 15);
4631 +
4632 + /* Assume endpoint addresses are the same for both speeds */
4633 + fsg_ss_bulk_in_desc.bEndpointAddress =
4634 + fsg_fs_bulk_in_desc.bEndpointAddress;
4635 + fsg_ss_bulk_in_comp_desc.bMaxBurst = max_burst;
4636 +
4637 + fsg_ss_bulk_out_desc.bEndpointAddress =
4638 + fsg_fs_bulk_out_desc.bEndpointAddress;
4639 + fsg_ss_bulk_out_comp_desc.bMaxBurst = max_burst;
4640 + }
4641 +
4642 + if (gadget_is_otg(gadget))
4643 + fsg_otg_desc.bmAttributes |= USB_OTG_HNP;
4644 +
4645 + rc = -ENOMEM;
4646 +
4647 + /* Allocate the request and buffer for endpoint 0 */
4648 + fsg->ep0req = req = usb_ep_alloc_request(fsg->ep0, GFP_KERNEL);
4649 + if (!req)
4650 + goto out;
4651 + req->buf = kmalloc(EP0_BUFSIZE, GFP_KERNEL);
4652 + if (!req->buf)
4653 + goto out;
4654 + req->complete = ep0_complete;
4655 +
4656 + /* Allocate the data buffers */
4657 + for (i = 0; i < fsg_num_buffers; ++i) {
4658 + struct fsg_buffhd *bh = &fsg->buffhds[i];
4659 +
4660 + /* Allocate for the bulk-in endpoint. We assume that
4661 + * the buffer will also work with the bulk-out (and
4662 + * interrupt-in) endpoint. */
4663 + bh->buf = kmalloc(mod_data.buflen, GFP_KERNEL);
4664 + if (!bh->buf)
4665 + goto out;
4666 + bh->next = bh + 1;
4667 + }
4668 + fsg->buffhds[fsg_num_buffers - 1].next = &fsg->buffhds[0];
4669 +
4670 + /* This should reflect the actual gadget power source */
4671 + usb_gadget_set_selfpowered(gadget);
4672 +
4673 + snprintf(fsg_string_manufacturer, sizeof fsg_string_manufacturer,
4674 + "%s %s with %s",
4675 + init_utsname()->sysname, init_utsname()->release,
4676 + gadget->name);
4677 +
4678 + fsg->thread_task = kthread_create(fsg_main_thread, fsg,
4679 + "file-storage-gadget");
4680 + if (IS_ERR(fsg->thread_task)) {
4681 + rc = PTR_ERR(fsg->thread_task);
4682 + goto out;
4683 + }
4684 +
4685 + INFO(fsg, DRIVER_DESC ", version: " DRIVER_VERSION "\n");
4686 + INFO(fsg, "NOTE: This driver is deprecated. "
4687 + "Consider using g_mass_storage instead.\n");
4688 + INFO(fsg, "Number of LUNs=%d\n", fsg->nluns);
4689 +
4690 + pathbuf = kmalloc(PATH_MAX, GFP_KERNEL);
4691 + for (i = 0; i < fsg->nluns; ++i) {
4692 + curlun = &fsg->luns[i];
4693 + if (fsg_lun_is_open(curlun)) {
4694 + p = NULL;
4695 + if (pathbuf) {
4696 + p = d_path(&curlun->filp->f_path,
4697 + pathbuf, PATH_MAX);
4698 + if (IS_ERR(p))
4699 + p = NULL;
4700 + }
4701 + LINFO(curlun, "ro=%d, nofua=%d, file: %s\n",
4702 + curlun->ro, curlun->nofua, (p ? p : "(error)"));
4703 + }
4704 + }
4705 + kfree(pathbuf);
4706 +
4707 + DBG(fsg, "transport=%s (x%02x)\n",
4708 + mod_data.transport_name, mod_data.transport_type);
4709 + DBG(fsg, "protocol=%s (x%02x)\n",
4710 + mod_data.protocol_name, mod_data.protocol_type);
4711 + DBG(fsg, "VendorID=x%04x, ProductID=x%04x, Release=x%04x\n",
4712 + mod_data.vendor, mod_data.product, mod_data.release);
4713 + DBG(fsg, "removable=%d, stall=%d, cdrom=%d, buflen=%u\n",
4714 + mod_data.removable, mod_data.can_stall,
4715 + mod_data.cdrom, mod_data.buflen);
4716 + DBG(fsg, "I/O thread pid: %d\n", task_pid_nr(fsg->thread_task));
4717 +
4718 + set_bit(REGISTERED, &fsg->atomic_bitflags);
4719 +
4720 + /* Tell the thread to start working */
4721 + wake_up_process(fsg->thread_task);
4722 + return 0;
4723 +
4724 +autoconf_fail:
4725 + ERROR(fsg, "unable to autoconfigure all endpoints\n");
4726 + rc = -ENOTSUPP;
4727 +
4728 +out:
4729 + fsg->state = FSG_STATE_TERMINATED; // The thread is dead
4730 + fsg_unbind(gadget);
4731 + complete(&fsg->thread_notifier);
4732 + return rc;
4733 +}
4734 +
4735 +
4736 +/*-------------------------------------------------------------------------*/
4737 +
4738 +static void fsg_suspend(struct usb_gadget *gadget)
4739 +{
4740 + struct fsg_dev *fsg = get_gadget_data(gadget);
4741 +
4742 + DBG(fsg, "suspend\n");
4743 + set_bit(SUSPENDED, &fsg->atomic_bitflags);
4744 +}
4745 +
4746 +static void fsg_resume(struct usb_gadget *gadget)
4747 +{
4748 + struct fsg_dev *fsg = get_gadget_data(gadget);
4749 +
4750 + DBG(fsg, "resume\n");
4751 + clear_bit(SUSPENDED, &fsg->atomic_bitflags);
4752 +}
4753 +
4754 +
4755 +/*-------------------------------------------------------------------------*/
4756 +
4757 +static struct usb_gadget_driver fsg_driver = {
4758 + .max_speed = USB_SPEED_SUPER,
4759 + .function = (char *) fsg_string_product,
4760 + .unbind = fsg_unbind,
4761 + .disconnect = fsg_disconnect,
4762 + .setup = fsg_setup,
4763 + .suspend = fsg_suspend,
4764 + .resume = fsg_resume,
4765 +
4766 + .driver = {
4767 + .name = DRIVER_NAME,
4768 + .owner = THIS_MODULE,
4769 + // .release = ...
4770 + // .suspend = ...
4771 + // .resume = ...
4772 + },
4773 +};
4774 +
4775 +
4776 +static int __init fsg_alloc(void)
4777 +{
4778 + struct fsg_dev *fsg;
4779 +
4780 + fsg = kzalloc(sizeof *fsg +
4781 + fsg_num_buffers * sizeof *(fsg->buffhds), GFP_KERNEL);
4782 +
4783 + if (!fsg)
4784 + return -ENOMEM;
4785 + spin_lock_init(&fsg->lock);
4786 + init_rwsem(&fsg->filesem);
4787 + kref_init(&fsg->ref);
4788 + init_completion(&fsg->thread_notifier);
4789 +
4790 + the_fsg = fsg;
4791 + return 0;
4792 +}
4793 +
4794 +
4795 +static int __init fsg_init(void)
4796 +{
4797 + int rc;
4798 + struct fsg_dev *fsg;
4799 +
4800 + rc = fsg_num_buffers_validate();
4801 + if (rc != 0)
4802 + return rc;
4803 +
4804 + if ((rc = fsg_alloc()) != 0)
4805 + return rc;
4806 + fsg = the_fsg;
4807 + if ((rc = usb_gadget_probe_driver(&fsg_driver, fsg_bind)) != 0)
4808 + kref_put(&fsg->ref, fsg_release);
4809 + return rc;
4810 +}
4811 +module_init(fsg_init);
4812 +
4813 +
4814 +static void __exit fsg_cleanup(void)
4815 +{
4816 + struct fsg_dev *fsg = the_fsg;
4817 +
4818 + /* Unregister the driver iff the thread hasn't already done so */
4819 + if (test_and_clear_bit(REGISTERED, &fsg->atomic_bitflags))
4820 + usb_gadget_unregister_driver(&fsg_driver);
4821 +
4822 + /* Wait for the thread to finish up */
4823 + wait_for_completion(&fsg->thread_notifier);
4824 +
4825 + kref_put(&fsg->ref, fsg_release);
4826 +}
4827 +module_exit(fsg_cleanup);
4828 --- a/drivers/usb/host/Kconfig
4829 +++ b/drivers/usb/host/Kconfig
4830 @@ -745,6 +745,19 @@ config USB_HWA_HCD
4831 To compile this driver a module, choose M here: the module
4832 will be called "hwa-hc".
4833
4834 +config USB_DWCOTG
4835 + tristate "Synopsis DWC host support"
4836 + depends on USB
4837 + help
4838 + The Synopsis DWC controller is a dual-role
4839 + host/peripheral/OTG ("On The Go") USB controllers.
4840 +
4841 + Enable this option to support this IP in host controller mode.
4842 + If unsure, say N.
4843 +
4844 + To compile this driver as a module, choose M here: the
4845 + modules built will be called dwc_otg and dwc_common_port.
4846 +
4847 config USB_IMX21_HCD
4848 tristate "i.MX21 HCD support"
4849 depends on ARM && ARCH_MXC
4850 --- a/drivers/usb/host/Makefile
4851 +++ b/drivers/usb/host/Makefile
4852 @@ -68,6 +68,8 @@ obj-$(CONFIG_USB_SL811_CS) += sl811_cs.o
4853 obj-$(CONFIG_USB_U132_HCD) += u132-hcd.o
4854 obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
4855 obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o
4856 +
4857 +obj-$(CONFIG_USB_DWCOTG) += dwc_otg/ dwc_common_port/
4858 obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o
4859 obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o
4860 obj-$(CONFIG_USB_HCD_BCMA) += bcma-hcd.o
4861 --- /dev/null
4862 +++ b/drivers/usb/host/dwc_common_port/Makefile
4863 @@ -0,0 +1,58 @@
4864 +#
4865 +# Makefile for DWC_common library
4866 +#
4867 +
4868 +ifneq ($(KERNELRELEASE),)
4869 +
4870 +ccflags-y += -DDWC_LINUX
4871 +#ccflags-y += -DDEBUG
4872 +#ccflags-y += -DDWC_DEBUG_REGS
4873 +#ccflags-y += -DDWC_DEBUG_MEMORY
4874 +
4875 +ccflags-y += -DDWC_LIBMODULE
4876 +ccflags-y += -DDWC_CCLIB
4877 +#ccflags-y += -DDWC_CRYPTOLIB
4878 +ccflags-y += -DDWC_NOTIFYLIB
4879 +ccflags-y += -DDWC_UTFLIB
4880 +
4881 +obj-$(CONFIG_USB_DWCOTG) += dwc_common_port_lib.o
4882 +dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \
4883 + dwc_crypto.o dwc_notifier.o \
4884 + dwc_common_linux.o dwc_mem.o
4885 +
4886 +kernrelwd := $(subst ., ,$(KERNELRELEASE))
4887 +kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd))
4888 +
4889 +ifneq ($(kernrel3),2.6.20)
4890 +# grayg - I only know that we use ccflags-y in 2.6.31 actually
4891 +ccflags-y += $(CPPFLAGS)
4892 +endif
4893 +
4894 +else
4895 +
4896 +#ifeq ($(KDIR),)
4897 +#$(error Must give "KDIR=/path/to/kernel/source" on command line or in environment)
4898 +#endif
4899 +
4900 +ifeq ($(ARCH),)
4901 +$(error Must give "ARCH=<arch>" on command line or in environment. Also, if \
4902 + cross-compiling, must give "CROSS_COMPILE=/path/to/compiler/plus/tool-prefix-")
4903 +endif
4904 +
4905 +ifeq ($(DOXYGEN),)
4906 +DOXYGEN := doxygen
4907 +endif
4908 +
4909 +default:
4910 + $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
4911 +
4912 +docs: $(wildcard *.[hc]) doc/doxygen.cfg
4913 + $(DOXYGEN) doc/doxygen.cfg
4914 +
4915 +tags: $(wildcard *.[hc])
4916 + $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
4917 +
4918 +endif
4919 +
4920 +clean:
4921 + rm -rf *.o *.ko .*.cmd *.mod.c .*.o.d .*.o.tmp modules.order Module.markers Module.symvers .tmp_versions/
4922 --- /dev/null
4923 +++ b/drivers/usb/host/dwc_common_port/Makefile.fbsd
4924 @@ -0,0 +1,17 @@
4925 +CFLAGS += -I/sys/i386/compile/GENERIC -I/sys/i386/include -I/usr/include
4926 +CFLAGS += -DDWC_FREEBSD
4927 +CFLAGS += -DDEBUG
4928 +#CFLAGS += -DDWC_DEBUG_REGS
4929 +#CFLAGS += -DDWC_DEBUG_MEMORY
4930 +
4931 +#CFLAGS += -DDWC_LIBMODULE
4932 +#CFLAGS += -DDWC_CCLIB
4933 +#CFLAGS += -DDWC_CRYPTOLIB
4934 +#CFLAGS += -DDWC_NOTIFYLIB
4935 +#CFLAGS += -DDWC_UTFLIB
4936 +
4937 +KMOD = dwc_common_port_lib
4938 +SRCS = dwc_cc.c dwc_modpow.c dwc_dh.c dwc_crypto.c dwc_notifier.c \
4939 + dwc_common_fbsd.c dwc_mem.c
4940 +
4941 +.include <bsd.kmod.mk>
4942 --- /dev/null
4943 +++ b/drivers/usb/host/dwc_common_port/Makefile.linux
4944 @@ -0,0 +1,49 @@
4945 +#
4946 +# Makefile for DWC_common library
4947 +#
4948 +ifneq ($(KERNELRELEASE),)
4949 +
4950 +ccflags-y += -DDWC_LINUX
4951 +#ccflags-y += -DDEBUG
4952 +#ccflags-y += -DDWC_DEBUG_REGS
4953 +#ccflags-y += -DDWC_DEBUG_MEMORY
4954 +
4955 +ccflags-y += -DDWC_LIBMODULE
4956 +ccflags-y += -DDWC_CCLIB
4957 +ccflags-y += -DDWC_CRYPTOLIB
4958 +ccflags-y += -DDWC_NOTIFYLIB
4959 +ccflags-y += -DDWC_UTFLIB
4960 +
4961 +obj-m := dwc_common_port_lib.o
4962 +dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \
4963 + dwc_crypto.o dwc_notifier.o \
4964 + dwc_common_linux.o dwc_mem.o
4965 +
4966 +else
4967 +
4968 +ifeq ($(KDIR),)
4969 +$(error Must give "KDIR=/path/to/kernel/source" on command line or in environment)
4970 +endif
4971 +
4972 +ifeq ($(ARCH),)
4973 +$(error Must give "ARCH=<arch>" on command line or in environment. Also, if \
4974 + cross-compiling, must give "CROSS_COMPILE=/path/to/compiler/plus/tool-prefix-")
4975 +endif
4976 +
4977 +ifeq ($(DOXYGEN),)
4978 +DOXYGEN := doxygen
4979 +endif
4980 +
4981 +default:
4982 + $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
4983 +
4984 +docs: $(wildcard *.[hc]) doc/doxygen.cfg
4985 + $(DOXYGEN) doc/doxygen.cfg
4986 +
4987 +tags: $(wildcard *.[hc])
4988 + $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
4989 +
4990 +endif
4991 +
4992 +clean:
4993 + rm -rf *.o *.ko .*.cmd *.mod.c .*.o.d .*.o.tmp modules.order Module.markers Module.symvers .tmp_versions/
4994 --- /dev/null
4995 +++ b/drivers/usb/host/dwc_common_port/changes.txt
4996 @@ -0,0 +1,174 @@
4997 +
4998 +dwc_read_reg32() and friends now take an additional parameter, a pointer to an
4999 +IO context struct. The IO context struct should live in an os-dependent struct
5000 +in your driver. As an example, the dwc_usb3 driver has an os-dependent struct
5001 +named 'os_dep' embedded in the main device struct. So there these calls look
5002 +like this:
5003 +
5004 + dwc_read_reg32(&usb3_dev->os_dep.ioctx, &pcd->dev_global_regs->dcfg);
5005 +
5006 + dwc_write_reg32(&usb3_dev->os_dep.ioctx,
5007 + &pcd->dev_global_regs->dcfg, 0);
5008 +
5009 +Note that for the existing Linux driver ports, it is not necessary to actually
5010 +define the 'ioctx' member in the os-dependent struct. Since Linux does not
5011 +require an IO context, its macros for dwc_read_reg32() and friends do not
5012 +use the context pointer, so it is optimized away by the compiler. But it is
5013 +necessary to add the pointer parameter to all of the call sites, to be ready
5014 +for any future ports (such as FreeBSD) which do require an IO context.
5015 +
5016 +
5017 +Similarly, dwc_alloc(), dwc_alloc_atomic(), dwc_strdup(), and dwc_free() now
5018 +take an additional parameter, a pointer to a memory context. Examples:
5019 +
5020 + addr = dwc_alloc(&usb3_dev->os_dep.memctx, size);
5021 +
5022 + dwc_free(&usb3_dev->os_dep.memctx, addr);
5023 +
5024 +Again, for the Linux ports, it is not necessary to actually define the memctx
5025 +member, but it is necessary to add the pointer parameter to all of the call
5026 +sites.
5027 +
5028 +
5029 +Same for dwc_dma_alloc() and dwc_dma_free(). Examples:
5030 +
5031 + virt_addr = dwc_dma_alloc(&usb3_dev->os_dep.dmactx, size, &phys_addr);
5032 +
5033 + dwc_dma_free(&usb3_dev->os_dep.dmactx, size, virt_addr, phys_addr);
5034 +
5035 +
5036 +Same for dwc_mutex_alloc() and dwc_mutex_free(). Examples:
5037 +
5038 + mutex = dwc_mutex_alloc(&usb3_dev->os_dep.mtxctx);
5039 +
5040 + dwc_mutex_free(&usb3_dev->os_dep.mtxctx, mutex);
5041 +
5042 +
5043 +Same for dwc_spinlock_alloc() and dwc_spinlock_free(). Examples:
5044 +
5045 + lock = dwc_spinlock_alloc(&usb3_dev->osdep.splctx);
5046 +
5047 + dwc_spinlock_free(&usb3_dev->osdep.splctx, lock);
5048 +
5049 +
5050 +Same for dwc_timer_alloc(). Example:
5051 +
5052 + timer = dwc_timer_alloc(&usb3_dev->os_dep.tmrctx, "dwc_usb3_tmr1",
5053 + cb_func, cb_data);
5054 +
5055 +
5056 +Same for dwc_waitq_alloc(). Example:
5057 +
5058 + waitq = dwc_waitq_alloc(&usb3_dev->os_dep.wtqctx);
5059 +
5060 +
5061 +Same for dwc_thread_run(). Example:
5062 +
5063 + thread = dwc_thread_run(&usb3_dev->os_dep.thdctx, func,
5064 + "dwc_usb3_thd1", data);
5065 +
5066 +
5067 +Same for dwc_workq_alloc(). Example:
5068 +
5069 + workq = dwc_workq_alloc(&usb3_dev->osdep.wkqctx, "dwc_usb3_wkq1");
5070 +
5071 +
5072 +Same for dwc_task_alloc(). Example:
5073 +
5074 + task = dwc_task_alloc(&usb3_dev->os_dep.tskctx, "dwc_usb3_tsk1",
5075 + cb_func, cb_data);
5076 +
5077 +
5078 +In addition to the context pointer additions, a few core functions have had
5079 +other changes made to their parameters:
5080 +
5081 +The 'flags' parameter to dwc_spinlock_irqsave() and dwc_spinunlock_irqrestore()
5082 +has been changed from a uint64_t to a dwc_irqflags_t.
5083 +
5084 +dwc_thread_should_stop() now takes a 'dwc_thread_t *' parameter, because the
5085 +FreeBSD equivalent of that function requires it.
5086 +
5087 +And, in addition to the context pointer, dwc_task_alloc() also adds a
5088 +'char *name' parameter, to be consistent with dwc_thread_run() and
5089 +dwc_workq_alloc(), and because the FreeBSD equivalent of that function
5090 +requires a unique name.
5091 +
5092 +
5093 +Here is a complete list of the core functions that now take a pointer to a
5094 +context as their first parameter:
5095 +
5096 + dwc_read_reg32
5097 + dwc_read_reg64
5098 + dwc_write_reg32
5099 + dwc_write_reg64
5100 + dwc_modify_reg32
5101 + dwc_modify_reg64
5102 + dwc_alloc
5103 + dwc_alloc_atomic
5104 + dwc_strdup
5105 + dwc_free
5106 + dwc_dma_alloc
5107 + dwc_dma_free
5108 + dwc_mutex_alloc
5109 + dwc_mutex_free
5110 + dwc_spinlock_alloc
5111 + dwc_spinlock_free
5112 + dwc_timer_alloc
5113 + dwc_waitq_alloc
5114 + dwc_thread_run
5115 + dwc_workq_alloc
5116 + dwc_task_alloc Also adds a 'char *name' as its 2nd parameter
5117 +
5118 +And here are the core functions that have other changes to their parameters:
5119 +
5120 + dwc_spinlock_irqsave 'flags' param is now a 'dwc_irqflags_t *'
5121 + dwc_spinunlock_irqrestore 'flags' param is now a 'dwc_irqflags_t'
5122 + dwc_thread_should_stop Adds a 'dwc_thread_t *' parameter
5123 +
5124 +
5125 +
5126 +The changes to the core functions also require some of the other library
5127 +functions to change:
5128 +
5129 + dwc_cc_if_alloc() and dwc_cc_if_free() now take a 'void *memctx'
5130 + (for memory allocation) as the 1st param and a 'void *mtxctx'
5131 + (for mutex allocation) as the 2nd param.
5132 +
5133 + dwc_cc_clear(), dwc_cc_add(), dwc_cc_change(), dwc_cc_remove(),
5134 + dwc_cc_data_for_save(), and dwc_cc_restore_from_data() now take a
5135 + 'void *memctx' as the 1st param.
5136 +
5137 + dwc_dh_modpow(), dwc_dh_pk(), and dwc_dh_derive_keys() now take a
5138 + 'void *memctx' as the 1st param.
5139 +
5140 + dwc_modpow() now takes a 'void *memctx' as the 1st param.
5141 +
5142 + dwc_alloc_notification_manager() now takes a 'void *memctx' as the
5143 + 1st param and a 'void *wkqctx' (for work queue allocation) as the 2nd
5144 + param, and also now returns an integer value that is non-zero if
5145 + allocation of its data structures or work queue fails.
5146 +
5147 + dwc_register_notifier() now takes a 'void *memctx' as the 1st param.
5148 +
5149 + dwc_memory_debug_start() now takes a 'void *mem_ctx' as the first
5150 + param, and also now returns an integer value that is non-zero if
5151 + allocation of its data structures fails.
5152 +
5153 +
5154 +
5155 +Other miscellaneous changes:
5156 +
5157 +The DEBUG_MEMORY and DEBUG_REGS #define's have been renamed to
5158 +DWC_DEBUG_MEMORY and DWC_DEBUG_REGS.
5159 +
5160 +The following #define's have been added to allow selectively compiling library
5161 +features:
5162 +
5163 + DWC_CCLIB
5164 + DWC_CRYPTOLIB
5165 + DWC_NOTIFYLIB
5166 + DWC_UTFLIB
5167 +
5168 +A DWC_LIBMODULE #define has also been added. If this is not defined, then the
5169 +module code in dwc_common_linux.c is not compiled in. This allows linking the
5170 +library code directly into a driver module, instead of as a standalone module.
5171 --- /dev/null
5172 +++ b/drivers/usb/host/dwc_common_port/doc/doxygen.cfg
5173 @@ -0,0 +1,270 @@
5174 +# Doxyfile 1.4.5
5175 +
5176 +#---------------------------------------------------------------------------
5177 +# Project related configuration options
5178 +#---------------------------------------------------------------------------
5179 +PROJECT_NAME = "Synopsys DWC Portability and Common Library for UWB"
5180 +PROJECT_NUMBER =
5181 +OUTPUT_DIRECTORY = doc
5182 +CREATE_SUBDIRS = NO
5183 +OUTPUT_LANGUAGE = English
5184 +BRIEF_MEMBER_DESC = YES
5185 +REPEAT_BRIEF = YES
5186 +ABBREVIATE_BRIEF = "The $name class" \
5187 + "The $name widget" \
5188 + "The $name file" \
5189 + is \
5190 + provides \
5191 + specifies \
5192 + contains \
5193 + represents \
5194 + a \
5195 + an \
5196 + the
5197 +ALWAYS_DETAILED_SEC = YES
5198 +INLINE_INHERITED_MEMB = NO
5199 +FULL_PATH_NAMES = NO
5200 +STRIP_FROM_PATH = ..
5201 +STRIP_FROM_INC_PATH =
5202 +SHORT_NAMES = NO
5203 +JAVADOC_AUTOBRIEF = YES
5204 +MULTILINE_CPP_IS_BRIEF = NO
5205 +DETAILS_AT_TOP = YES
5206 +INHERIT_DOCS = YES
5207 +SEPARATE_MEMBER_PAGES = NO
5208 +TAB_SIZE = 8
5209 +ALIASES =
5210 +OPTIMIZE_OUTPUT_FOR_C = YES
5211 +OPTIMIZE_OUTPUT_JAVA = NO
5212 +BUILTIN_STL_SUPPORT = NO
5213 +DISTRIBUTE_GROUP_DOC = NO
5214 +SUBGROUPING = NO
5215 +#---------------------------------------------------------------------------
5216 +# Build related configuration options
5217 +#---------------------------------------------------------------------------
5218 +EXTRACT_ALL = NO
5219 +EXTRACT_PRIVATE = NO
5220 +EXTRACT_STATIC = YES
5221 +EXTRACT_LOCAL_CLASSES = NO
5222 +EXTRACT_LOCAL_METHODS = NO
5223 +HIDE_UNDOC_MEMBERS = NO
5224 +HIDE_UNDOC_CLASSES = NO
5225 +HIDE_FRIEND_COMPOUNDS = NO
5226 +HIDE_IN_BODY_DOCS = NO
5227 +INTERNAL_DOCS = NO
5228 +CASE_SENSE_NAMES = YES
5229 +HIDE_SCOPE_NAMES = NO
5230 +SHOW_INCLUDE_FILES = NO
5231 +INLINE_INFO = YES
5232 +SORT_MEMBER_DOCS = NO
5233 +SORT_BRIEF_DOCS = NO
5234 +SORT_BY_SCOPE_NAME = NO
5235 +GENERATE_TODOLIST = YES
5236 +GENERATE_TESTLIST = YES
5237 +GENERATE_BUGLIST = YES
5238 +GENERATE_DEPRECATEDLIST= YES
5239 +ENABLED_SECTIONS =
5240 +MAX_INITIALIZER_LINES = 30
5241 +SHOW_USED_FILES = YES
5242 +SHOW_DIRECTORIES = YES
5243 +FILE_VERSION_FILTER =
5244 +#---------------------------------------------------------------------------
5245 +# configuration options related to warning and progress messages
5246 +#---------------------------------------------------------------------------
5247 +QUIET = YES
5248 +WARNINGS = YES
5249 +WARN_IF_UNDOCUMENTED = NO
5250 +WARN_IF_DOC_ERROR = YES
5251 +WARN_NO_PARAMDOC = YES
5252 +WARN_FORMAT = "$file:$line: $text"
5253 +WARN_LOGFILE =
5254 +#---------------------------------------------------------------------------
5255 +# configuration options related to the input files
5256 +#---------------------------------------------------------------------------
5257 +INPUT = .
5258 +FILE_PATTERNS = *.c \
5259 + *.cc \
5260 + *.cxx \
5261 + *.cpp \
5262 + *.c++ \
5263 + *.d \
5264 + *.java \
5265 + *.ii \
5266 + *.ixx \
5267 + *.ipp \
5268 + *.i++ \
5269 + *.inl \
5270 + *.h \
5271 + *.hh \
5272 + *.hxx \
5273 + *.hpp \
5274 + *.h++ \
5275 + *.idl \
5276 + *.odl \
5277 + *.cs \
5278 + *.php \
5279 + *.php3 \
5280 + *.inc \
5281 + *.m \
5282 + *.mm \
5283 + *.dox \
5284 + *.py \
5285 + *.C \
5286 + *.CC \
5287 + *.C++ \
5288 + *.II \
5289 + *.I++ \
5290 + *.H \
5291 + *.HH \
5292 + *.H++ \
5293 + *.CS \
5294 + *.PHP \
5295 + *.PHP3 \
5296 + *.M \
5297 + *.MM \
5298 + *.PY
5299 +RECURSIVE = NO
5300 +EXCLUDE =
5301 +EXCLUDE_SYMLINKS = NO
5302 +EXCLUDE_PATTERNS =
5303 +EXAMPLE_PATH =
5304 +EXAMPLE_PATTERNS = *
5305 +EXAMPLE_RECURSIVE = NO
5306 +IMAGE_PATH =
5307 +INPUT_FILTER =
5308 +FILTER_PATTERNS =
5309 +FILTER_SOURCE_FILES = NO
5310 +#---------------------------------------------------------------------------
5311 +# configuration options related to source browsing
5312 +#---------------------------------------------------------------------------
5313 +SOURCE_BROWSER = NO
5314 +INLINE_SOURCES = NO
5315 +STRIP_CODE_COMMENTS = YES
5316 +REFERENCED_BY_RELATION = YES
5317 +REFERENCES_RELATION = YES
5318 +USE_HTAGS = NO
5319 +VERBATIM_HEADERS = NO
5320 +#---------------------------------------------------------------------------
5321 +# configuration options related to the alphabetical class index
5322 +#---------------------------------------------------------------------------
5323 +ALPHABETICAL_INDEX = NO
5324 +COLS_IN_ALPHA_INDEX = 5
5325 +IGNORE_PREFIX =
5326 +#---------------------------------------------------------------------------
5327 +# configuration options related to the HTML output
5328 +#---------------------------------------------------------------------------
5329 +GENERATE_HTML = YES
5330 +HTML_OUTPUT = html
5331 +HTML_FILE_EXTENSION = .html
5332 +HTML_HEADER =
5333 +HTML_FOOTER =
5334 +HTML_STYLESHEET =
5335 +HTML_ALIGN_MEMBERS = YES
5336 +GENERATE_HTMLHELP = NO
5337 +CHM_FILE =
5338 +HHC_LOCATION =
5339 +GENERATE_CHI = NO
5340 +BINARY_TOC = NO
5341 +TOC_EXPAND = NO
5342 +DISABLE_INDEX = NO
5343 +ENUM_VALUES_PER_LINE = 4
5344 +GENERATE_TREEVIEW = YES
5345 +TREEVIEW_WIDTH = 250
5346 +#---------------------------------------------------------------------------
5347 +# configuration options related to the LaTeX output
5348 +#---------------------------------------------------------------------------
5349 +GENERATE_LATEX = NO
5350 +LATEX_OUTPUT = latex
5351 +LATEX_CMD_NAME = latex
5352 +MAKEINDEX_CMD_NAME = makeindex
5353 +COMPACT_LATEX = NO
5354 +PAPER_TYPE = a4wide
5355 +EXTRA_PACKAGES =
5356 +LATEX_HEADER =
5357 +PDF_HYPERLINKS = NO
5358 +USE_PDFLATEX = NO
5359 +LATEX_BATCHMODE = NO
5360 +LATEX_HIDE_INDICES = NO
5361 +#---------------------------------------------------------------------------
5362 +# configuration options related to the RTF output
5363 +#---------------------------------------------------------------------------
5364 +GENERATE_RTF = NO
5365 +RTF_OUTPUT = rtf
5366 +COMPACT_RTF = NO
5367 +RTF_HYPERLINKS = NO
5368 +RTF_STYLESHEET_FILE =
5369 +RTF_EXTENSIONS_FILE =
5370 +#---------------------------------------------------------------------------
5371 +# configuration options related to the man page output
5372 +#---------------------------------------------------------------------------
5373 +GENERATE_MAN = NO
5374 +MAN_OUTPUT = man
5375 +MAN_EXTENSION = .3
5376 +MAN_LINKS = NO
5377 +#---------------------------------------------------------------------------
5378 +# configuration options related to the XML output
5379 +#---------------------------------------------------------------------------
5380 +GENERATE_XML = NO
5381 +XML_OUTPUT = xml
5382 +XML_SCHEMA =
5383 +XML_DTD =
5384 +XML_PROGRAMLISTING = YES
5385 +#---------------------------------------------------------------------------
5386 +# configuration options for the AutoGen Definitions output
5387 +#---------------------------------------------------------------------------
5388 +GENERATE_AUTOGEN_DEF = NO
5389 +#---------------------------------------------------------------------------
5390 +# configuration options related to the Perl module output
5391 +#---------------------------------------------------------------------------
5392 +GENERATE_PERLMOD = NO
5393 +PERLMOD_LATEX = NO
5394 +PERLMOD_PRETTY = YES
5395 +PERLMOD_MAKEVAR_PREFIX =
5396 +#---------------------------------------------------------------------------
5397 +# Configuration options related to the preprocessor
5398 +#---------------------------------------------------------------------------
5399 +ENABLE_PREPROCESSING = YES
5400 +MACRO_EXPANSION = NO
5401 +EXPAND_ONLY_PREDEF = NO
5402 +SEARCH_INCLUDES = YES
5403 +INCLUDE_PATH =
5404 +INCLUDE_FILE_PATTERNS =
5405 +PREDEFINED = DEBUG DEBUG_MEMORY
5406 +EXPAND_AS_DEFINED =
5407 +SKIP_FUNCTION_MACROS = YES
5408 +#---------------------------------------------------------------------------
5409 +# Configuration::additions related to external references
5410 +#---------------------------------------------------------------------------
5411 +TAGFILES =
5412 +GENERATE_TAGFILE =
5413 +ALLEXTERNALS = NO
5414 +EXTERNAL_GROUPS = YES
5415 +PERL_PATH = /usr/bin/perl
5416 +#---------------------------------------------------------------------------
5417 +# Configuration options related to the dot tool
5418 +#---------------------------------------------------------------------------
5419 +CLASS_DIAGRAMS = YES
5420 +HIDE_UNDOC_RELATIONS = YES
5421 +HAVE_DOT = NO
5422 +CLASS_GRAPH = YES
5423 +COLLABORATION_GRAPH = YES
5424 +GROUP_GRAPHS = YES
5425 +UML_LOOK = NO
5426 +TEMPLATE_RELATIONS = NO
5427 +INCLUDE_GRAPH = NO
5428 +INCLUDED_BY_GRAPH = YES
5429 +CALL_GRAPH = NO
5430 +GRAPHICAL_HIERARCHY = YES
5431 +DIRECTORY_GRAPH = YES
5432 +DOT_IMAGE_FORMAT = png
5433 +DOT_PATH =
5434 +DOTFILE_DIRS =
5435 +MAX_DOT_GRAPH_DEPTH = 1000
5436 +DOT_TRANSPARENT = NO
5437 +DOT_MULTI_TARGETS = NO
5438 +GENERATE_LEGEND = YES
5439 +DOT_CLEANUP = YES
5440 +#---------------------------------------------------------------------------
5441 +# Configuration::additions related to the search engine
5442 +#---------------------------------------------------------------------------
5443 +SEARCHENGINE = NO
5444 --- /dev/null
5445 +++ b/drivers/usb/host/dwc_common_port/dwc_cc.c
5446 @@ -0,0 +1,532 @@
5447 +/* =========================================================================
5448 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_cc.c $
5449 + * $Revision: #4 $
5450 + * $Date: 2010/11/04 $
5451 + * $Change: 1621692 $
5452 + *
5453 + * Synopsys Portability Library Software and documentation
5454 + * (hereinafter, "Software") is an Unsupported proprietary work of
5455 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
5456 + * between Synopsys and you.
5457 + *
5458 + * The Software IS NOT an item of Licensed Software or Licensed Product
5459 + * under any End User Software License Agreement or Agreement for
5460 + * Licensed Product with Synopsys or any supplement thereto. You are
5461 + * permitted to use and redistribute this Software in source and binary
5462 + * forms, with or without modification, provided that redistributions
5463 + * of source code must retain this notice. You may not view, use,
5464 + * disclose, copy or distribute this file or any information contained
5465 + * herein except pursuant to this license grant from Synopsys. If you
5466 + * do not agree with this notice, including the disclaimer below, then
5467 + * you are not authorized to use the Software.
5468 + *
5469 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
5470 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
5471 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
5472 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
5473 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
5474 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
5475 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
5476 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
5477 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5478 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
5479 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
5480 + * DAMAGE.
5481 + * ========================================================================= */
5482 +#ifdef DWC_CCLIB
5483 +
5484 +#include "dwc_cc.h"
5485 +
5486 +typedef struct dwc_cc
5487 +{
5488 + uint32_t uid;
5489 + uint8_t chid[16];
5490 + uint8_t cdid[16];
5491 + uint8_t ck[16];
5492 + uint8_t *name;
5493 + uint8_t length;
5494 + DWC_CIRCLEQ_ENTRY(dwc_cc) list_entry;
5495 +} dwc_cc_t;
5496 +
5497 +DWC_CIRCLEQ_HEAD(context_list, dwc_cc);
5498 +
5499 +/** The main structure for CC management. */
5500 +struct dwc_cc_if
5501 +{
5502 + dwc_mutex_t *mutex;
5503 + char *filename;
5504 +
5505 + unsigned is_host:1;
5506 +
5507 + dwc_notifier_t *notifier;
5508 +
5509 + struct context_list list;
5510 +};
5511 +
5512 +#ifdef DEBUG
5513 +static inline void dump_bytes(char *name, uint8_t *bytes, int len)
5514 +{
5515 + int i;
5516 + DWC_PRINTF("%s: ", name);
5517 + for (i=0; i<len; i++) {
5518 + DWC_PRINTF("%02x ", bytes[i]);
5519 + }
5520 + DWC_PRINTF("\n");
5521 +}
5522 +#else
5523 +#define dump_bytes(x...)
5524 +#endif
5525 +
5526 +static dwc_cc_t *alloc_cc(void *mem_ctx, uint8_t *name, uint32_t length)
5527 +{
5528 + dwc_cc_t *cc = dwc_alloc(mem_ctx, sizeof(dwc_cc_t));
5529 + if (!cc) {
5530 + return NULL;
5531 + }
5532 + DWC_MEMSET(cc, 0, sizeof(dwc_cc_t));
5533 +
5534 + if (name) {
5535 + cc->length = length;
5536 + cc->name = dwc_alloc(mem_ctx, length);
5537 + if (!cc->name) {
5538 + dwc_free(mem_ctx, cc);
5539 + return NULL;
5540 + }
5541 +
5542 + DWC_MEMCPY(cc->name, name, length);
5543 + }
5544 +
5545 + return cc;
5546 +}
5547 +
5548 +static void free_cc(void *mem_ctx, dwc_cc_t *cc)
5549 +{
5550 + if (cc->name) {
5551 + dwc_free(mem_ctx, cc->name);
5552 + }
5553 + dwc_free(mem_ctx, cc);
5554 +}
5555 +
5556 +static uint32_t next_uid(dwc_cc_if_t *cc_if)
5557 +{
5558 + uint32_t uid = 0;
5559 + dwc_cc_t *cc;
5560 + DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
5561 + if (cc->uid > uid) {
5562 + uid = cc->uid;
5563 + }
5564 + }
5565 +
5566 + if (uid == 0) {
5567 + uid = 255;
5568 + }
5569 +
5570 + return uid + 1;
5571 +}
5572 +
5573 +static dwc_cc_t *cc_find(dwc_cc_if_t *cc_if, uint32_t uid)
5574 +{
5575 + dwc_cc_t *cc;
5576 + DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
5577 + if (cc->uid == uid) {
5578 + return cc;
5579 + }
5580 + }
5581 + return NULL;
5582 +}
5583 +
5584 +static unsigned int cc_data_size(dwc_cc_if_t *cc_if)
5585 +{
5586 + unsigned int size = 0;
5587 + dwc_cc_t *cc;
5588 + DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
5589 + size += (48 + 1);
5590 + if (cc->name) {
5591 + size += cc->length;
5592 + }
5593 + }
5594 + return size;
5595 +}
5596 +
5597 +static uint32_t cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid)
5598 +{
5599 + uint32_t uid = 0;
5600 + dwc_cc_t *cc;
5601 +
5602 + DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
5603 + if (DWC_MEMCMP(cc->chid, chid, 16) == 0) {
5604 + uid = cc->uid;
5605 + break;
5606 + }
5607 + }
5608 + return uid;
5609 +}
5610 +static uint32_t cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid)
5611 +{
5612 + uint32_t uid = 0;
5613 + dwc_cc_t *cc;
5614 +
5615 + DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
5616 + if (DWC_MEMCMP(cc->cdid, cdid, 16) == 0) {
5617 + uid = cc->uid;
5618 + break;
5619 + }
5620 + }
5621 + return uid;
5622 +}
5623 +
5624 +/* Internal cc_add */
5625 +static int32_t cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,
5626 + uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
5627 +{
5628 + dwc_cc_t *cc;
5629 + uint32_t uid;
5630 +
5631 + if (cc_if->is_host) {
5632 + uid = cc_match_cdid(cc_if, cdid);
5633 + }
5634 + else {
5635 + uid = cc_match_chid(cc_if, chid);
5636 + }
5637 +
5638 + if (uid) {
5639 + DWC_DEBUGC("Replacing previous connection context id=%d name=%p name_len=%d", uid, name, length);
5640 + cc = cc_find(cc_if, uid);
5641 + }
5642 + else {
5643 + cc = alloc_cc(mem_ctx, name, length);
5644 + cc->uid = next_uid(cc_if);
5645 + DWC_CIRCLEQ_INSERT_TAIL(&cc_if->list, cc, list_entry);
5646 + }
5647 +
5648 + DWC_MEMCPY(&(cc->chid[0]), chid, 16);
5649 + DWC_MEMCPY(&(cc->cdid[0]), cdid, 16);
5650 + DWC_MEMCPY(&(cc->ck[0]), ck, 16);
5651 +
5652 + DWC_DEBUGC("Added connection context id=%d name=%p name_len=%d", cc->uid, name, length);
5653 + dump_bytes("CHID", cc->chid, 16);
5654 + dump_bytes("CDID", cc->cdid, 16);
5655 + dump_bytes("CK", cc->ck, 16);
5656 + return cc->uid;
5657 +}
5658 +
5659 +/* Internal cc_clear */
5660 +static void cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if)
5661 +{
5662 + while (!DWC_CIRCLEQ_EMPTY(&cc_if->list)) {
5663 + dwc_cc_t *cc = DWC_CIRCLEQ_FIRST(&cc_if->list);
5664 + DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry);
5665 + free_cc(mem_ctx, cc);
5666 + }
5667 +}
5668 +
5669 +dwc_cc_if_t *dwc_cc_if_alloc(void *mem_ctx, void *mtx_ctx,
5670 + dwc_notifier_t *notifier, unsigned is_host)
5671 +{
5672 + dwc_cc_if_t *cc_if = NULL;
5673 +
5674 + /* Allocate a common_cc_if structure */
5675 + cc_if = dwc_alloc(mem_ctx, sizeof(dwc_cc_if_t));
5676 +
5677 + if (!cc_if)
5678 + return NULL;
5679 +
5680 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
5681 + DWC_MUTEX_ALLOC_LINUX_DEBUG(cc_if->mutex);
5682 +#else
5683 + cc_if->mutex = dwc_mutex_alloc(mtx_ctx);
5684 +#endif
5685 + if (!cc_if->mutex) {
5686 + dwc_free(mem_ctx, cc_if);
5687 + return NULL;
5688 + }
5689 +
5690 + DWC_CIRCLEQ_INIT(&cc_if->list);
5691 + cc_if->is_host = is_host;
5692 + cc_if->notifier = notifier;
5693 + return cc_if;
5694 +}
5695 +
5696 +void dwc_cc_if_free(void *mem_ctx, void *mtx_ctx, dwc_cc_if_t *cc_if)
5697 +{
5698 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
5699 + DWC_MUTEX_FREE(cc_if->mutex);
5700 +#else
5701 + dwc_mutex_free(mtx_ctx, cc_if->mutex);
5702 +#endif
5703 + cc_clear(mem_ctx, cc_if);
5704 + dwc_free(mem_ctx, cc_if);
5705 +}
5706 +
5707 +static void cc_changed(dwc_cc_if_t *cc_if)
5708 +{
5709 + if (cc_if->notifier) {
5710 + dwc_notify(cc_if->notifier, DWC_CC_LIST_CHANGED_NOTIFICATION, cc_if);
5711 + }
5712 +}
5713 +
5714 +void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if)
5715 +{
5716 + DWC_MUTEX_LOCK(cc_if->mutex);
5717 + cc_clear(mem_ctx, cc_if);
5718 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5719 + cc_changed(cc_if);
5720 +}
5721 +
5722 +int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,
5723 + uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
5724 +{
5725 + uint32_t uid;
5726 +
5727 + DWC_MUTEX_LOCK(cc_if->mutex);
5728 + uid = cc_add(mem_ctx, cc_if, chid, cdid, ck, name, length);
5729 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5730 + cc_changed(cc_if);
5731 +
5732 + return uid;
5733 +}
5734 +
5735 +void dwc_cc_change(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id, uint8_t *chid,
5736 + uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
5737 +{
5738 + dwc_cc_t* cc;
5739 +
5740 + DWC_DEBUGC("Change connection context %d", id);
5741 +
5742 + DWC_MUTEX_LOCK(cc_if->mutex);
5743 + cc = cc_find(cc_if, id);
5744 + if (!cc) {
5745 + DWC_ERROR("Uid %d not found in cc list\n", id);
5746 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5747 + return;
5748 + }
5749 +
5750 + if (chid) {
5751 + DWC_MEMCPY(&(cc->chid[0]), chid, 16);
5752 + }
5753 + if (cdid) {
5754 + DWC_MEMCPY(&(cc->cdid[0]), cdid, 16);
5755 + }
5756 + if (ck) {
5757 + DWC_MEMCPY(&(cc->ck[0]), ck, 16);
5758 + }
5759 +
5760 + if (name) {
5761 + if (cc->name) {
5762 + dwc_free(mem_ctx, cc->name);
5763 + }
5764 + cc->name = dwc_alloc(mem_ctx, length);
5765 + if (!cc->name) {
5766 + DWC_ERROR("Out of memory in dwc_cc_change()\n");
5767 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5768 + return;
5769 + }
5770 + cc->length = length;
5771 + DWC_MEMCPY(cc->name, name, length);
5772 + }
5773 +
5774 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5775 +
5776 + cc_changed(cc_if);
5777 +
5778 + DWC_DEBUGC("Changed connection context id=%d\n", id);
5779 + dump_bytes("New CHID", cc->chid, 16);
5780 + dump_bytes("New CDID", cc->cdid, 16);
5781 + dump_bytes("New CK", cc->ck, 16);
5782 +}
5783 +
5784 +void dwc_cc_remove(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id)
5785 +{
5786 + dwc_cc_t *cc;
5787 +
5788 + DWC_DEBUGC("Removing connection context %d", id);
5789 +
5790 + DWC_MUTEX_LOCK(cc_if->mutex);
5791 + cc = cc_find(cc_if, id);
5792 + if (!cc) {
5793 + DWC_ERROR("Uid %d not found in cc list\n", id);
5794 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5795 + return;
5796 + }
5797 +
5798 + DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry);
5799 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5800 + free_cc(mem_ctx, cc);
5801 +
5802 + cc_changed(cc_if);
5803 +}
5804 +
5805 +uint8_t *dwc_cc_data_for_save(void *mem_ctx, dwc_cc_if_t *cc_if, unsigned int *length)
5806 +{
5807 + uint8_t *buf, *x;
5808 + uint8_t zero = 0;
5809 + dwc_cc_t *cc;
5810 +
5811 + DWC_MUTEX_LOCK(cc_if->mutex);
5812 + *length = cc_data_size(cc_if);
5813 + if (!(*length)) {
5814 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5815 + return NULL;
5816 + }
5817 +
5818 + DWC_DEBUGC("Creating data for saving (length=%d)", *length);
5819 +
5820 + buf = dwc_alloc(mem_ctx, *length);
5821 + if (!buf) {
5822 + *length = 0;
5823 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5824 + return NULL;
5825 + }
5826 +
5827 + x = buf;
5828 + DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
5829 + DWC_MEMCPY(x, cc->chid, 16);
5830 + x += 16;
5831 + DWC_MEMCPY(x, cc->cdid, 16);
5832 + x += 16;
5833 + DWC_MEMCPY(x, cc->ck, 16);
5834 + x += 16;
5835 + if (cc->name) {
5836 + DWC_MEMCPY(x, &cc->length, 1);
5837 + x += 1;
5838 + DWC_MEMCPY(x, cc->name, cc->length);
5839 + x += cc->length;
5840 + }
5841 + else {
5842 + DWC_MEMCPY(x, &zero, 1);
5843 + x += 1;
5844 + }
5845 + }
5846 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5847 +
5848 + return buf;
5849 +}
5850 +
5851 +void dwc_cc_restore_from_data(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *data, uint32_t length)
5852 +{
5853 + uint8_t name_length;
5854 + uint8_t *name;
5855 + uint8_t *chid;
5856 + uint8_t *cdid;
5857 + uint8_t *ck;
5858 + uint32_t i = 0;
5859 +
5860 + DWC_MUTEX_LOCK(cc_if->mutex);
5861 + cc_clear(mem_ctx, cc_if);
5862 +
5863 + while (i < length) {
5864 + chid = &data[i];
5865 + i += 16;
5866 + cdid = &data[i];
5867 + i += 16;
5868 + ck = &data[i];
5869 + i += 16;
5870 +
5871 + name_length = data[i];
5872 + i ++;
5873 +
5874 + if (name_length) {
5875 + name = &data[i];
5876 + i += name_length;
5877 + }
5878 + else {
5879 + name = NULL;
5880 + }
5881 +
5882 + /* check to see if we haven't overflown the buffer */
5883 + if (i > length) {
5884 + DWC_ERROR("Data format error while attempting to load CCs "
5885 + "(nlen=%d, iter=%d, buflen=%d).\n", name_length, i, length);
5886 + break;
5887 + }
5888 +
5889 + cc_add(mem_ctx, cc_if, chid, cdid, ck, name, name_length);
5890 + }
5891 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5892 +
5893 + cc_changed(cc_if);
5894 +}
5895 +
5896 +uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid)
5897 +{
5898 + uint32_t uid = 0;
5899 +
5900 + DWC_MUTEX_LOCK(cc_if->mutex);
5901 + uid = cc_match_chid(cc_if, chid);
5902 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5903 + return uid;
5904 +}
5905 +uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid)
5906 +{
5907 + uint32_t uid = 0;
5908 +
5909 + DWC_MUTEX_LOCK(cc_if->mutex);
5910 + uid = cc_match_cdid(cc_if, cdid);
5911 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5912 + return uid;
5913 +}
5914 +
5915 +uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id)
5916 +{
5917 + uint8_t *ck = NULL;
5918 + dwc_cc_t *cc;
5919 +
5920 + DWC_MUTEX_LOCK(cc_if->mutex);
5921 + cc = cc_find(cc_if, id);
5922 + if (cc) {
5923 + ck = cc->ck;
5924 + }
5925 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5926 +
5927 + return ck;
5928 +
5929 +}
5930 +
5931 +uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id)
5932 +{
5933 + uint8_t *retval = NULL;
5934 + dwc_cc_t *cc;
5935 +
5936 + DWC_MUTEX_LOCK(cc_if->mutex);
5937 + cc = cc_find(cc_if, id);
5938 + if (cc) {
5939 + retval = cc->chid;
5940 + }
5941 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5942 +
5943 + return retval;
5944 +}
5945 +
5946 +uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id)
5947 +{
5948 + uint8_t *retval = NULL;
5949 + dwc_cc_t *cc;
5950 +
5951 + DWC_MUTEX_LOCK(cc_if->mutex);
5952 + cc = cc_find(cc_if, id);
5953 + if (cc) {
5954 + retval = cc->cdid;
5955 + }
5956 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5957 +
5958 + return retval;
5959 +}
5960 +
5961 +uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length)
5962 +{
5963 + uint8_t *retval = NULL;
5964 + dwc_cc_t *cc;
5965 +
5966 + DWC_MUTEX_LOCK(cc_if->mutex);
5967 + *length = 0;
5968 + cc = cc_find(cc_if, id);
5969 + if (cc) {
5970 + *length = cc->length;
5971 + retval = cc->name;
5972 + }
5973 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5974 +
5975 + return retval;
5976 +}
5977 +
5978 +#endif /* DWC_CCLIB */
5979 --- /dev/null
5980 +++ b/drivers/usb/host/dwc_common_port/dwc_cc.h
5981 @@ -0,0 +1,224 @@
5982 +/* =========================================================================
5983 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_cc.h $
5984 + * $Revision: #4 $
5985 + * $Date: 2010/09/28 $
5986 + * $Change: 1596182 $
5987 + *
5988 + * Synopsys Portability Library Software and documentation
5989 + * (hereinafter, "Software") is an Unsupported proprietary work of
5990 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
5991 + * between Synopsys and you.
5992 + *
5993 + * The Software IS NOT an item of Licensed Software or Licensed Product
5994 + * under any End User Software License Agreement or Agreement for
5995 + * Licensed Product with Synopsys or any supplement thereto. You are
5996 + * permitted to use and redistribute this Software in source and binary
5997 + * forms, with or without modification, provided that redistributions
5998 + * of source code must retain this notice. You may not view, use,
5999 + * disclose, copy or distribute this file or any information contained
6000 + * herein except pursuant to this license grant from Synopsys. If you
6001 + * do not agree with this notice, including the disclaimer below, then
6002 + * you are not authorized to use the Software.
6003 + *
6004 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
6005 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
6006 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
6007 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
6008 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
6009 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
6010 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
6011 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
6012 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6013 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
6014 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
6015 + * DAMAGE.
6016 + * ========================================================================= */
6017 +#ifndef _DWC_CC_H_
6018 +#define _DWC_CC_H_
6019 +
6020 +#ifdef __cplusplus
6021 +extern "C" {
6022 +#endif
6023 +
6024 +/** @file
6025 + *
6026 + * This file defines the Context Context library.
6027 + *
6028 + * The main data structure is dwc_cc_if_t which is returned by either the
6029 + * dwc_cc_if_alloc function or returned by the module to the user via a provided
6030 + * function. The data structure is opaque and should only be manipulated via the
6031 + * functions provied in this API.
6032 + *
6033 + * It manages a list of connection contexts and operations can be performed to
6034 + * add, remove, query, search, and change, those contexts. Additionally,
6035 + * a dwc_notifier_t object can be requested from the manager so that
6036 + * the user can be notified whenever the context list has changed.
6037 + */
6038 +
6039 +#include "dwc_os.h"
6040 +#include "dwc_list.h"
6041 +#include "dwc_notifier.h"
6042 +
6043 +
6044 +/* Notifications */
6045 +#define DWC_CC_LIST_CHANGED_NOTIFICATION "DWC_CC_LIST_CHANGED_NOTIFICATION"
6046 +
6047 +struct dwc_cc_if;
6048 +typedef struct dwc_cc_if dwc_cc_if_t;
6049 +
6050 +
6051 +/** @name Connection Context Operations */
6052 +/** @{ */
6053 +
6054 +/** This function allocates memory for a dwc_cc_if_t structure, initializes
6055 + * fields to default values, and returns a pointer to the structure or NULL on
6056 + * error. */
6057 +extern dwc_cc_if_t *dwc_cc_if_alloc(void *mem_ctx, void *mtx_ctx,
6058 + dwc_notifier_t *notifier, unsigned is_host);
6059 +
6060 +/** Frees the memory for the specified CC structure allocated from
6061 + * dwc_cc_if_alloc(). */
6062 +extern void dwc_cc_if_free(void *mem_ctx, void *mtx_ctx, dwc_cc_if_t *cc_if);
6063 +
6064 +/** Removes all contexts from the connection context list */
6065 +extern void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if);
6066 +
6067 +/** Adds a connection context (CHID, CK, CDID, Name) to the connection context list.
6068 + * If a CHID already exists, the CK and name are overwritten. Statistics are
6069 + * not overwritten.
6070 + *
6071 + * @param cc_if The cc_if structure.
6072 + * @param chid A pointer to the 16-byte CHID. This value will be copied.
6073 + * @param ck A pointer to the 16-byte CK. This value will be copied.
6074 + * @param cdid A pointer to the 16-byte CDID. This value will be copied.
6075 + * @param name An optional host friendly name as defined in the association model
6076 + * spec. Must be a UTF16-LE unicode string. Can be NULL to indicated no name.
6077 + * @param length The length othe unicode string.
6078 + * @return A unique identifier used to refer to this context that is valid for
6079 + * as long as this context is still in the list. */
6080 +extern int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,
6081 + uint8_t *cdid, uint8_t *ck, uint8_t *name,
6082 + uint8_t length);
6083 +
6084 +/** Changes the CHID, CK, CDID, or Name values of a connection context in the
6085 + * list, preserving any accumulated statistics. This would typically be called
6086 + * if the host decideds to change the context with a SET_CONNECTION request.
6087 + *
6088 + * @param cc_if The cc_if structure.
6089 + * @param id The identifier of the connection context.
6090 + * @param chid A pointer to the 16-byte CHID. This value will be copied. NULL
6091 + * indicates no change.
6092 + * @param cdid A pointer to the 16-byte CDID. This value will be copied. NULL
6093 + * indicates no change.
6094 + * @param ck A pointer to the 16-byte CK. This value will be copied. NULL
6095 + * indicates no change.
6096 + * @param name Host friendly name UTF16-LE. NULL indicates no change.
6097 + * @param length Length of name. */
6098 +extern void dwc_cc_change(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id,
6099 + uint8_t *chid, uint8_t *cdid, uint8_t *ck,
6100 + uint8_t *name, uint8_t length);
6101 +
6102 +/** Remove the specified connection context.
6103 + * @param cc_if The cc_if structure.
6104 + * @param id The identifier of the connection context to remove. */
6105 +extern void dwc_cc_remove(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id);
6106 +
6107 +/** Get a binary block of data for the connection context list and attributes.
6108 + * This data can be used by the OS specific driver to save the connection
6109 + * context list into non-volatile memory.
6110 + *
6111 + * @param cc_if The cc_if structure.
6112 + * @param length Return the length of the data buffer.
6113 + * @return A pointer to the data buffer. The memory for this buffer should be
6114 + * freed with DWC_FREE() after use. */
6115 +extern uint8_t *dwc_cc_data_for_save(void *mem_ctx, dwc_cc_if_t *cc_if,
6116 + unsigned int *length);
6117 +
6118 +/** Restore the connection context list from the binary data that was previously
6119 + * returned from a call to dwc_cc_data_for_save. This can be used by the OS specific
6120 + * driver to load a connection context list from non-volatile memory.
6121 + *
6122 + * @param cc_if The cc_if structure.
6123 + * @param data The data bytes as returned from dwc_cc_data_for_save.
6124 + * @param length The length of the data. */
6125 +extern void dwc_cc_restore_from_data(void *mem_ctx, dwc_cc_if_t *cc_if,
6126 + uint8_t *data, unsigned int length);
6127 +
6128 +/** Find the connection context from the specified CHID.
6129 + *
6130 + * @param cc_if The cc_if structure.
6131 + * @param chid A pointer to the CHID data.
6132 + * @return A non-zero identifier of the connection context if the CHID matches.
6133 + * Otherwise returns 0. */
6134 +extern uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid);
6135 +
6136 +/** Find the connection context from the specified CDID.
6137 + *
6138 + * @param cc_if The cc_if structure.
6139 + * @param cdid A pointer to the CDID data.
6140 + * @return A non-zero identifier of the connection context if the CHID matches.
6141 + * Otherwise returns 0. */
6142 +extern uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid);
6143 +
6144 +/** Retrieve the CK from the specified connection context.
6145 + *
6146 + * @param cc_if The cc_if structure.
6147 + * @param id The identifier of the connection context.
6148 + * @return A pointer to the CK data. The memory does not need to be freed. */
6149 +extern uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id);
6150 +
6151 +/** Retrieve the CHID from the specified connection context.
6152 + *
6153 + * @param cc_if The cc_if structure.
6154 + * @param id The identifier of the connection context.
6155 + * @return A pointer to the CHID data. The memory does not need to be freed. */
6156 +extern uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id);
6157 +
6158 +/** Retrieve the CDID from the specified connection context.
6159 + *
6160 + * @param cc_if The cc_if structure.
6161 + * @param id The identifier of the connection context.
6162 + * @return A pointer to the CDID data. The memory does not need to be freed. */
6163 +extern uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id);
6164 +
6165 +extern uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length);
6166 +
6167 +/** Checks a buffer for non-zero.
6168 + * @param id A pointer to a 16 byte buffer.
6169 + * @return true if the 16 byte value is non-zero. */
6170 +static inline unsigned dwc_assoc_is_not_zero_id(uint8_t *id) {
6171 + int i;
6172 + for (i=0; i<16; i++) {
6173 + if (id[i]) return 1;
6174 + }
6175 + return 0;
6176 +}
6177 +
6178 +/** Checks a buffer for zero.
6179 + * @param id A pointer to a 16 byte buffer.
6180 + * @return true if the 16 byte value is zero. */
6181 +static inline unsigned dwc_assoc_is_zero_id(uint8_t *id) {
6182 + return !dwc_assoc_is_not_zero_id(id);
6183 +}
6184 +
6185 +/** Prints an ASCII representation for the 16-byte chid, cdid, or ck, into
6186 + * buffer. */
6187 +static inline int dwc_print_id_string(char *buffer, uint8_t *id) {
6188 + char *ptr = buffer;
6189 + int i;
6190 + for (i=0; i<16; i++) {
6191 + ptr += DWC_SPRINTF(ptr, "%02x", id[i]);
6192 + if (i < 15) {
6193 + ptr += DWC_SPRINTF(ptr, " ");
6194 + }
6195 + }
6196 + return ptr - buffer;
6197 +}
6198 +
6199 +/** @} */
6200 +
6201 +#ifdef __cplusplus
6202 +}
6203 +#endif
6204 +
6205 +#endif /* _DWC_CC_H_ */
6206 --- /dev/null
6207 +++ b/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c
6208 @@ -0,0 +1,1308 @@
6209 +#include "dwc_os.h"
6210 +#include "dwc_list.h"
6211 +
6212 +#ifdef DWC_CCLIB
6213 +# include "dwc_cc.h"
6214 +#endif
6215 +
6216 +#ifdef DWC_CRYPTOLIB
6217 +# include "dwc_modpow.h"
6218 +# include "dwc_dh.h"
6219 +# include "dwc_crypto.h"
6220 +#endif
6221 +
6222 +#ifdef DWC_NOTIFYLIB
6223 +# include "dwc_notifier.h"
6224 +#endif
6225 +
6226 +/* OS-Level Implementations */
6227 +
6228 +/* This is the FreeBSD 7.0 kernel implementation of the DWC platform library. */
6229 +
6230 +
6231 +/* MISC */
6232 +
6233 +void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)
6234 +{
6235 + return memset(dest, byte, size);
6236 +}
6237 +
6238 +void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)
6239 +{
6240 + return memcpy(dest, src, size);
6241 +}
6242 +
6243 +void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)
6244 +{
6245 + bcopy(src, dest, size);
6246 + return dest;
6247 +}
6248 +
6249 +int DWC_MEMCMP(void *m1, void *m2, uint32_t size)
6250 +{
6251 + return memcmp(m1, m2, size);
6252 +}
6253 +
6254 +int DWC_STRNCMP(void *s1, void *s2, uint32_t size)
6255 +{
6256 + return strncmp(s1, s2, size);
6257 +}
6258 +
6259 +int DWC_STRCMP(void *s1, void *s2)
6260 +{
6261 + return strcmp(s1, s2);
6262 +}
6263 +
6264 +int DWC_STRLEN(char const *str)
6265 +{
6266 + return strlen(str);
6267 +}
6268 +
6269 +char *DWC_STRCPY(char *to, char const *from)
6270 +{
6271 + return strcpy(to, from);
6272 +}
6273 +
6274 +char *DWC_STRDUP(char const *str)
6275 +{
6276 + int len = DWC_STRLEN(str) + 1;
6277 + char *new = DWC_ALLOC_ATOMIC(len);
6278 +
6279 + if (!new) {
6280 + return NULL;
6281 + }
6282 +
6283 + DWC_MEMCPY(new, str, len);
6284 + return new;
6285 +}
6286 +
6287 +int DWC_ATOI(char *str, int32_t *value)
6288 +{
6289 + char *end = NULL;
6290 +
6291 + *value = strtol(str, &end, 0);
6292 + if (*end == '\0') {
6293 + return 0;
6294 + }
6295 +
6296 + return -1;
6297 +}
6298 +
6299 +int DWC_ATOUI(char *str, uint32_t *value)
6300 +{
6301 + char *end = NULL;
6302 +
6303 + *value = strtoul(str, &end, 0);
6304 + if (*end == '\0') {
6305 + return 0;
6306 + }
6307 +
6308 + return -1;
6309 +}
6310 +
6311 +
6312 +#ifdef DWC_UTFLIB
6313 +/* From usbstring.c */
6314 +
6315 +int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)
6316 +{
6317 + int count = 0;
6318 + u8 c;
6319 + u16 uchar;
6320 +
6321 + /* this insists on correct encodings, though not minimal ones.
6322 + * BUT it currently rejects legit 4-byte UTF-8 code points,
6323 + * which need surrogate pairs. (Unicode 3.1 can use them.)
6324 + */
6325 + while (len != 0 && (c = (u8) *s++) != 0) {
6326 + if (unlikely(c & 0x80)) {
6327 + // 2-byte sequence:
6328 + // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
6329 + if ((c & 0xe0) == 0xc0) {
6330 + uchar = (c & 0x1f) << 6;
6331 +
6332 + c = (u8) *s++;
6333 + if ((c & 0xc0) != 0xc0)
6334 + goto fail;
6335 + c &= 0x3f;
6336 + uchar |= c;
6337 +
6338 + // 3-byte sequence (most CJKV characters):
6339 + // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
6340 + } else if ((c & 0xf0) == 0xe0) {
6341 + uchar = (c & 0x0f) << 12;
6342 +
6343 + c = (u8) *s++;
6344 + if ((c & 0xc0) != 0xc0)
6345 + goto fail;
6346 + c &= 0x3f;
6347 + uchar |= c << 6;
6348 +
6349 + c = (u8) *s++;
6350 + if ((c & 0xc0) != 0xc0)
6351 + goto fail;
6352 + c &= 0x3f;
6353 + uchar |= c;
6354 +
6355 + /* no bogus surrogates */
6356 + if (0xd800 <= uchar && uchar <= 0xdfff)
6357 + goto fail;
6358 +
6359 + // 4-byte sequence (surrogate pairs, currently rare):
6360 + // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
6361 + // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
6362 + // (uuuuu = wwww + 1)
6363 + // FIXME accept the surrogate code points (only)
6364 + } else
6365 + goto fail;
6366 + } else
6367 + uchar = c;
6368 + put_unaligned (cpu_to_le16 (uchar), cp++);
6369 + count++;
6370 + len--;
6371 + }
6372 + return count;
6373 +fail:
6374 + return -1;
6375 +}
6376 +
6377 +#endif /* DWC_UTFLIB */
6378 +
6379 +
6380 +/* dwc_debug.h */
6381 +
6382 +dwc_bool_t DWC_IN_IRQ(void)
6383 +{
6384 +// return in_irq();
6385 + return 0;
6386 +}
6387 +
6388 +dwc_bool_t DWC_IN_BH(void)
6389 +{
6390 +// return in_softirq();
6391 + return 0;
6392 +}
6393 +
6394 +void DWC_VPRINTF(char *format, va_list args)
6395 +{
6396 + vprintf(format, args);
6397 +}
6398 +
6399 +int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)
6400 +{
6401 + return vsnprintf(str, size, format, args);
6402 +}
6403 +
6404 +void DWC_PRINTF(char *format, ...)
6405 +{
6406 + va_list args;
6407 +
6408 + va_start(args, format);
6409 + DWC_VPRINTF(format, args);
6410 + va_end(args);
6411 +}
6412 +
6413 +int DWC_SPRINTF(char *buffer, char *format, ...)
6414 +{
6415 + int retval;
6416 + va_list args;
6417 +
6418 + va_start(args, format);
6419 + retval = vsprintf(buffer, format, args);
6420 + va_end(args);
6421 + return retval;
6422 +}
6423 +
6424 +int DWC_SNPRINTF(char *buffer, int size, char *format, ...)
6425 +{
6426 + int retval;
6427 + va_list args;
6428 +
6429 + va_start(args, format);
6430 + retval = vsnprintf(buffer, size, format, args);
6431 + va_end(args);
6432 + return retval;
6433 +}
6434 +
6435 +void __DWC_WARN(char *format, ...)
6436 +{
6437 + va_list args;
6438 +
6439 + va_start(args, format);
6440 + DWC_VPRINTF(format, args);
6441 + va_end(args);
6442 +}
6443 +
6444 +void __DWC_ERROR(char *format, ...)
6445 +{
6446 + va_list args;
6447 +
6448 + va_start(args, format);
6449 + DWC_VPRINTF(format, args);
6450 + va_end(args);
6451 +}
6452 +
6453 +void DWC_EXCEPTION(char *format, ...)
6454 +{
6455 + va_list args;
6456 +
6457 + va_start(args, format);
6458 + DWC_VPRINTF(format, args);
6459 + va_end(args);
6460 +// BUG_ON(1); ???
6461 +}
6462 +
6463 +#ifdef DEBUG
6464 +void __DWC_DEBUG(char *format, ...)
6465 +{
6466 + va_list args;
6467 +
6468 + va_start(args, format);
6469 + DWC_VPRINTF(format, args);
6470 + va_end(args);
6471 +}
6472 +#endif
6473 +
6474 +
6475 +/* dwc_mem.h */
6476 +
6477 +#if 0
6478 +dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,
6479 + uint32_t align,
6480 + uint32_t alloc)
6481 +{
6482 + struct dma_pool *pool = dma_pool_create("Pool", NULL,
6483 + size, align, alloc);
6484 + return (dwc_pool_t *)pool;
6485 +}
6486 +
6487 +void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)
6488 +{
6489 + dma_pool_destroy((struct dma_pool *)pool);
6490 +}
6491 +
6492 +void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
6493 +{
6494 +// return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);
6495 + return dma_pool_alloc((struct dma_pool *)pool, M_WAITOK, dma_addr);
6496 +}
6497 +
6498 +void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
6499 +{
6500 + void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);
6501 + memset(..);
6502 +}
6503 +
6504 +void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)
6505 +{
6506 + dma_pool_free(pool, vaddr, daddr);
6507 +}
6508 +#endif
6509 +
6510 +static void dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
6511 +{
6512 + if (error)
6513 + return;
6514 + *(bus_addr_t *)arg = segs[0].ds_addr;
6515 +}
6516 +
6517 +void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
6518 +{
6519 + dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
6520 + int error;
6521 +
6522 + error = bus_dma_tag_create(
6523 +#if __FreeBSD_version >= 700000
6524 + bus_get_dma_tag(dma->dev), /* parent */
6525 +#else
6526 + NULL, /* parent */
6527 +#endif
6528 + 4, 0, /* alignment, bounds */
6529 + BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
6530 + BUS_SPACE_MAXADDR, /* highaddr */
6531 + NULL, NULL, /* filter, filterarg */
6532 + size, /* maxsize */
6533 + 1, /* nsegments */
6534 + size, /* maxsegsize */
6535 + 0, /* flags */
6536 + NULL, /* lockfunc */
6537 + NULL, /* lockarg */
6538 + &dma->dma_tag);
6539 + if (error) {
6540 + device_printf(dma->dev, "%s: bus_dma_tag_create failed: %d\n",
6541 + __func__, error);
6542 + goto fail_0;
6543 + }
6544 +
6545 + error = bus_dmamem_alloc(dma->dma_tag, &dma->dma_vaddr,
6546 + BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map);
6547 + if (error) {
6548 + device_printf(dma->dev, "%s: bus_dmamem_alloc(%ju) failed: %d\n",
6549 + __func__, (uintmax_t)size, error);
6550 + goto fail_1;
6551 + }
6552 +
6553 + dma->dma_paddr = 0;
6554 + error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, size,
6555 + dmamap_cb, &dma->dma_paddr, BUS_DMA_NOWAIT);
6556 + if (error || dma->dma_paddr == 0) {
6557 + device_printf(dma->dev, "%s: bus_dmamap_load failed: %d\n",
6558 + __func__, error);
6559 + goto fail_2;
6560 + }
6561 +
6562 + *dma_addr = dma->dma_paddr;
6563 + return dma->dma_vaddr;
6564 +
6565 +fail_2:
6566 + bus_dmamap_unload(dma->dma_tag, dma->dma_map);
6567 +fail_1:
6568 + bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
6569 + bus_dma_tag_destroy(dma->dma_tag);
6570 +fail_0:
6571 + dma->dma_map = NULL;
6572 + dma->dma_tag = NULL;
6573 +
6574 + return NULL;
6575 +}
6576 +
6577 +void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
6578 +{
6579 + dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
6580 +
6581 + if (dma->dma_tag == NULL)
6582 + return;
6583 + if (dma->dma_map != NULL) {
6584 + bus_dmamap_sync(dma->dma_tag, dma->dma_map,
6585 + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6586 + bus_dmamap_unload(dma->dma_tag, dma->dma_map);
6587 + bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
6588 + dma->dma_map = NULL;
6589 + }
6590 +
6591 + bus_dma_tag_destroy(dma->dma_tag);
6592 + dma->dma_tag = NULL;
6593 +}
6594 +
6595 +void *__DWC_ALLOC(void *mem_ctx, uint32_t size)
6596 +{
6597 + return malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
6598 +}
6599 +
6600 +void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)
6601 +{
6602 + return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
6603 +}
6604 +
6605 +void __DWC_FREE(void *mem_ctx, void *addr)
6606 +{
6607 + free(addr, M_DEVBUF);
6608 +}
6609 +
6610 +
6611 +#ifdef DWC_CRYPTOLIB
6612 +/* dwc_crypto.h */
6613 +
6614 +void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)
6615 +{
6616 + get_random_bytes(buffer, length);
6617 +}
6618 +
6619 +int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
6620 +{
6621 + struct crypto_blkcipher *tfm;
6622 + struct blkcipher_desc desc;
6623 + struct scatterlist sgd;
6624 + struct scatterlist sgs;
6625 +
6626 + tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
6627 + if (tfm == NULL) {
6628 + printk("failed to load transform for aes CBC\n");
6629 + return -1;
6630 + }
6631 +
6632 + crypto_blkcipher_setkey(tfm, key, keylen);
6633 + crypto_blkcipher_set_iv(tfm, iv, 16);
6634 +
6635 + sg_init_one(&sgd, out, messagelen);
6636 + sg_init_one(&sgs, message, messagelen);
6637 +
6638 + desc.tfm = tfm;
6639 + desc.flags = 0;
6640 +
6641 + if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {
6642 + crypto_free_blkcipher(tfm);
6643 + DWC_ERROR("AES CBC encryption failed");
6644 + return -1;
6645 + }
6646 +
6647 + crypto_free_blkcipher(tfm);
6648 + return 0;
6649 +}
6650 +
6651 +int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)
6652 +{
6653 + struct crypto_hash *tfm;
6654 + struct hash_desc desc;
6655 + struct scatterlist sg;
6656 +
6657 + tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC);
6658 + if (IS_ERR(tfm)) {
6659 + DWC_ERROR("Failed to load transform for sha256: %ld", PTR_ERR(tfm));
6660 + return 0;
6661 + }
6662 + desc.tfm = tfm;
6663 + desc.flags = 0;
6664 +
6665 + sg_init_one(&sg, message, len);
6666 + crypto_hash_digest(&desc, &sg, len, out);
6667 + crypto_free_hash(tfm);
6668 +
6669 + return 1;
6670 +}
6671 +
6672 +int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,
6673 + uint8_t *key, uint32_t keylen, uint8_t *out)
6674 +{
6675 + struct crypto_hash *tfm;
6676 + struct hash_desc desc;
6677 + struct scatterlist sg;
6678 +
6679 + tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC);
6680 + if (IS_ERR(tfm)) {
6681 + DWC_ERROR("Failed to load transform for hmac(sha256): %ld", PTR_ERR(tfm));
6682 + return 0;
6683 + }
6684 + desc.tfm = tfm;
6685 + desc.flags = 0;
6686 +
6687 + sg_init_one(&sg, message, messagelen);
6688 + crypto_hash_setkey(tfm, key, keylen);
6689 + crypto_hash_digest(&desc, &sg, messagelen, out);
6690 + crypto_free_hash(tfm);
6691 +
6692 + return 1;
6693 +}
6694 +
6695 +#endif /* DWC_CRYPTOLIB */
6696 +
6697 +
6698 +/* Byte Ordering Conversions */
6699 +
6700 +uint32_t DWC_CPU_TO_LE32(uint32_t *p)
6701 +{
6702 +#ifdef __LITTLE_ENDIAN
6703 + return *p;
6704 +#else
6705 + uint8_t *u_p = (uint8_t *)p;
6706 +
6707 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
6708 +#endif
6709 +}
6710 +
6711 +uint32_t DWC_CPU_TO_BE32(uint32_t *p)
6712 +{
6713 +#ifdef __BIG_ENDIAN
6714 + return *p;
6715 +#else
6716 + uint8_t *u_p = (uint8_t *)p;
6717 +
6718 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
6719 +#endif
6720 +}
6721 +
6722 +uint32_t DWC_LE32_TO_CPU(uint32_t *p)
6723 +{
6724 +#ifdef __LITTLE_ENDIAN
6725 + return *p;
6726 +#else
6727 + uint8_t *u_p = (uint8_t *)p;
6728 +
6729 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
6730 +#endif
6731 +}
6732 +
6733 +uint32_t DWC_BE32_TO_CPU(uint32_t *p)
6734 +{
6735 +#ifdef __BIG_ENDIAN
6736 + return *p;
6737 +#else
6738 + uint8_t *u_p = (uint8_t *)p;
6739 +
6740 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
6741 +#endif
6742 +}
6743 +
6744 +uint16_t DWC_CPU_TO_LE16(uint16_t *p)
6745 +{
6746 +#ifdef __LITTLE_ENDIAN
6747 + return *p;
6748 +#else
6749 + uint8_t *u_p = (uint8_t *)p;
6750 + return (u_p[1] | (u_p[0] << 8));
6751 +#endif
6752 +}
6753 +
6754 +uint16_t DWC_CPU_TO_BE16(uint16_t *p)
6755 +{
6756 +#ifdef __BIG_ENDIAN
6757 + return *p;
6758 +#else
6759 + uint8_t *u_p = (uint8_t *)p;
6760 + return (u_p[1] | (u_p[0] << 8));
6761 +#endif
6762 +}
6763 +
6764 +uint16_t DWC_LE16_TO_CPU(uint16_t *p)
6765 +{
6766 +#ifdef __LITTLE_ENDIAN
6767 + return *p;
6768 +#else
6769 + uint8_t *u_p = (uint8_t *)p;
6770 + return (u_p[1] | (u_p[0] << 8));
6771 +#endif
6772 +}
6773 +
6774 +uint16_t DWC_BE16_TO_CPU(uint16_t *p)
6775 +{
6776 +#ifdef __BIG_ENDIAN
6777 + return *p;
6778 +#else
6779 + uint8_t *u_p = (uint8_t *)p;
6780 + return (u_p[1] | (u_p[0] << 8));
6781 +#endif
6782 +}
6783 +
6784 +
6785 +/* Registers */
6786 +
6787 +uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg)
6788 +{
6789 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
6790 + bus_size_t ior = (bus_size_t)reg;
6791 +
6792 + return bus_space_read_4(io->iot, io->ioh, ior);
6793 +}
6794 +
6795 +#if 0
6796 +uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg)
6797 +{
6798 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
6799 + bus_size_t ior = (bus_size_t)reg;
6800 +
6801 + return bus_space_read_8(io->iot, io->ioh, ior);
6802 +}
6803 +#endif
6804 +
6805 +void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value)
6806 +{
6807 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
6808 + bus_size_t ior = (bus_size_t)reg;
6809 +
6810 + bus_space_write_4(io->iot, io->ioh, ior, value);
6811 +}
6812 +
6813 +#if 0
6814 +void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value)
6815 +{
6816 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
6817 + bus_size_t ior = (bus_size_t)reg;
6818 +
6819 + bus_space_write_8(io->iot, io->ioh, ior, value);
6820 +}
6821 +#endif
6822 +
6823 +void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask,
6824 + uint32_t set_mask)
6825 +{
6826 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
6827 + bus_size_t ior = (bus_size_t)reg;
6828 +
6829 + bus_space_write_4(io->iot, io->ioh, ior,
6830 + (bus_space_read_4(io->iot, io->ioh, ior) &
6831 + ~clear_mask) | set_mask);
6832 +}
6833 +
6834 +#if 0
6835 +void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask,
6836 + uint64_t set_mask)
6837 +{
6838 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
6839 + bus_size_t ior = (bus_size_t)reg;
6840 +
6841 + bus_space_write_8(io->iot, io->ioh, ior,
6842 + (bus_space_read_8(io->iot, io->ioh, ior) &
6843 + ~clear_mask) | set_mask);
6844 +}
6845 +#endif
6846 +
6847 +
6848 +/* Locking */
6849 +
6850 +dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)
6851 +{
6852 + struct mtx *sl = DWC_ALLOC(sizeof(*sl));
6853 +
6854 + if (!sl) {
6855 + DWC_ERROR("Cannot allocate memory for spinlock");
6856 + return NULL;
6857 + }
6858 +
6859 + mtx_init(sl, "dw3spn", NULL, MTX_SPIN);
6860 + return (dwc_spinlock_t *)sl;
6861 +}
6862 +
6863 +void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)
6864 +{
6865 + struct mtx *sl = (struct mtx *)lock;
6866 +
6867 + mtx_destroy(sl);
6868 + DWC_FREE(sl);
6869 +}
6870 +
6871 +void DWC_SPINLOCK(dwc_spinlock_t *lock)
6872 +{
6873 + mtx_lock_spin((struct mtx *)lock); // ???
6874 +}
6875 +
6876 +void DWC_SPINUNLOCK(dwc_spinlock_t *lock)
6877 +{
6878 + mtx_unlock_spin((struct mtx *)lock); // ???
6879 +}
6880 +
6881 +void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)
6882 +{
6883 + mtx_lock_spin((struct mtx *)lock);
6884 +}
6885 +
6886 +void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)
6887 +{
6888 + mtx_unlock_spin((struct mtx *)lock);
6889 +}
6890 +
6891 +dwc_mutex_t *DWC_MUTEX_ALLOC(void)
6892 +{
6893 + struct mtx *m;
6894 + dwc_mutex_t *mutex = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mtx));
6895 +
6896 + if (!mutex) {
6897 + DWC_ERROR("Cannot allocate memory for mutex");
6898 + return NULL;
6899 + }
6900 +
6901 + m = (struct mtx *)mutex;
6902 + mtx_init(m, "dw3mtx", NULL, MTX_DEF);
6903 + return mutex;
6904 +}
6905 +
6906 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
6907 +#else
6908 +void DWC_MUTEX_FREE(dwc_mutex_t *mutex)
6909 +{
6910 + mtx_destroy((struct mtx *)mutex);
6911 + DWC_FREE(mutex);
6912 +}
6913 +#endif
6914 +
6915 +void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)
6916 +{
6917 + struct mtx *m = (struct mtx *)mutex;
6918 +
6919 + mtx_lock(m);
6920 +}
6921 +
6922 +int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)
6923 +{
6924 + struct mtx *m = (struct mtx *)mutex;
6925 +
6926 + return mtx_trylock(m);
6927 +}
6928 +
6929 +void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)
6930 +{
6931 + struct mtx *m = (struct mtx *)mutex;
6932 +
6933 + mtx_unlock(m);
6934 +}
6935 +
6936 +
6937 +/* Timing */
6938 +
6939 +void DWC_UDELAY(uint32_t usecs)
6940 +{
6941 + DELAY(usecs);
6942 +}
6943 +
6944 +void DWC_MDELAY(uint32_t msecs)
6945 +{
6946 + do {
6947 + DELAY(1000);
6948 + } while (--msecs);
6949 +}
6950 +
6951 +void DWC_MSLEEP(uint32_t msecs)
6952 +{
6953 + struct timeval tv;
6954 +
6955 + tv.tv_sec = msecs / 1000;
6956 + tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
6957 + pause("dw3slp", tvtohz(&tv));
6958 +}
6959 +
6960 +uint32_t DWC_TIME(void)
6961 +{
6962 + struct timeval tv;
6963 +
6964 + microuptime(&tv); // or getmicrouptime? (less precise, but faster)
6965 + return tv.tv_sec * 1000 + tv.tv_usec / 1000;
6966 +}
6967 +
6968 +
6969 +/* Timers */
6970 +
6971 +struct dwc_timer {
6972 + struct callout t;
6973 + char *name;
6974 + dwc_spinlock_t *lock;
6975 + dwc_timer_callback_t cb;
6976 + void *data;
6977 +};
6978 +
6979 +dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)
6980 +{
6981 + dwc_timer_t *t = DWC_ALLOC(sizeof(*t));
6982 +
6983 + if (!t) {
6984 + DWC_ERROR("Cannot allocate memory for timer");
6985 + return NULL;
6986 + }
6987 +
6988 + callout_init(&t->t, 1);
6989 +
6990 + t->name = DWC_STRDUP(name);
6991 + if (!t->name) {
6992 + DWC_ERROR("Cannot allocate memory for timer->name");
6993 + goto no_name;
6994 + }
6995 +
6996 + t->lock = DWC_SPINLOCK_ALLOC();
6997 + if (!t->lock) {
6998 + DWC_ERROR("Cannot allocate memory for lock");
6999 + goto no_lock;
7000 + }
7001 +
7002 + t->cb = cb;
7003 + t->data = data;
7004 +
7005 + return t;
7006 +
7007 + no_lock:
7008 + DWC_FREE(t->name);
7009 + no_name:
7010 + DWC_FREE(t);
7011 +
7012 + return NULL;
7013 +}
7014 +
7015 +void DWC_TIMER_FREE(dwc_timer_t *timer)
7016 +{
7017 + callout_stop(&timer->t);
7018 + DWC_SPINLOCK_FREE(timer->lock);
7019 + DWC_FREE(timer->name);
7020 + DWC_FREE(timer);
7021 +}
7022 +
7023 +void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)
7024 +{
7025 + struct timeval tv;
7026 +
7027 + tv.tv_sec = time / 1000;
7028 + tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
7029 + callout_reset(&timer->t, tvtohz(&tv), timer->cb, timer->data);
7030 +}
7031 +
7032 +void DWC_TIMER_CANCEL(dwc_timer_t *timer)
7033 +{
7034 + callout_stop(&timer->t);
7035 +}
7036 +
7037 +
7038 +/* Wait Queues */
7039 +
7040 +struct dwc_waitq {
7041 + struct mtx lock;
7042 + int abort;
7043 +};
7044 +
7045 +dwc_waitq_t *DWC_WAITQ_ALLOC(void)
7046 +{
7047 + dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));
7048 +
7049 + if (!wq) {
7050 + DWC_ERROR("Cannot allocate memory for waitqueue");
7051 + return NULL;
7052 + }
7053 +
7054 + mtx_init(&wq->lock, "dw3wtq", NULL, MTX_DEF);
7055 + wq->abort = 0;
7056 +
7057 + return wq;
7058 +}
7059 +
7060 +void DWC_WAITQ_FREE(dwc_waitq_t *wq)
7061 +{
7062 + mtx_destroy(&wq->lock);
7063 + DWC_FREE(wq);
7064 +}
7065 +
7066 +int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)
7067 +{
7068 +// intrmask_t ipl;
7069 + int result = 0;
7070 +
7071 + mtx_lock(&wq->lock);
7072 +// ipl = splbio();
7073 +
7074 + /* Skip the sleep if already aborted or triggered */
7075 + if (!wq->abort && !cond(data)) {
7076 +// splx(ipl);
7077 + result = msleep(wq, &wq->lock, PCATCH, "dw3wat", 0); // infinite timeout
7078 +// ipl = splbio();
7079 + }
7080 +
7081 + if (result == ERESTART) { // signaled - restart
7082 + result = -DWC_E_RESTART;
7083 +
7084 + } else if (result == EINTR) { // signaled - interrupt
7085 + result = -DWC_E_ABORT;
7086 +
7087 + } else if (wq->abort) {
7088 + result = -DWC_E_ABORT;
7089 +
7090 + } else {
7091 + result = 0;
7092 + }
7093 +
7094 + wq->abort = 0;
7095 +// splx(ipl);
7096 + mtx_unlock(&wq->lock);
7097 + return result;
7098 +}
7099 +
7100 +int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
7101 + void *data, int32_t msecs)
7102 +{
7103 + struct timeval tv, tv1, tv2;
7104 +// intrmask_t ipl;
7105 + int result = 0;
7106 +
7107 + tv.tv_sec = msecs / 1000;
7108 + tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
7109 +
7110 + mtx_lock(&wq->lock);
7111 +// ipl = splbio();
7112 +
7113 + /* Skip the sleep if already aborted or triggered */
7114 + if (!wq->abort && !cond(data)) {
7115 +// splx(ipl);
7116 + getmicrouptime(&tv1);
7117 + result = msleep(wq, &wq->lock, PCATCH, "dw3wto", tvtohz(&tv));
7118 + getmicrouptime(&tv2);
7119 +// ipl = splbio();
7120 + }
7121 +
7122 + if (result == 0) { // awoken
7123 + if (wq->abort) {
7124 + result = -DWC_E_ABORT;
7125 + } else {
7126 + tv2.tv_usec -= tv1.tv_usec;
7127 + if (tv2.tv_usec < 0) {
7128 + tv2.tv_usec += 1000000;
7129 + tv2.tv_sec--;
7130 + }
7131 +
7132 + tv2.tv_sec -= tv1.tv_sec;
7133 + result = tv2.tv_sec * 1000 + tv2.tv_usec / 1000;
7134 + result = msecs - result;
7135 + if (result <= 0)
7136 + result = 1;
7137 + }
7138 + } else if (result == ERESTART) { // signaled - restart
7139 + result = -DWC_E_RESTART;
7140 +
7141 + } else if (result == EINTR) { // signaled - interrupt
7142 + result = -DWC_E_ABORT;
7143 +
7144 + } else { // timed out
7145 + result = -DWC_E_TIMEOUT;
7146 + }
7147 +
7148 + wq->abort = 0;
7149 +// splx(ipl);
7150 + mtx_unlock(&wq->lock);
7151 + return result;
7152 +}
7153 +
7154 +void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)
7155 +{
7156 + wakeup(wq);
7157 +}
7158 +
7159 +void DWC_WAITQ_ABORT(dwc_waitq_t *wq)
7160 +{
7161 +// intrmask_t ipl;
7162 +
7163 + mtx_lock(&wq->lock);
7164 +// ipl = splbio();
7165 + wq->abort = 1;
7166 + wakeup(wq);
7167 +// splx(ipl);
7168 + mtx_unlock(&wq->lock);
7169 +}
7170 +
7171 +
7172 +/* Threading */
7173 +
7174 +struct dwc_thread {
7175 + struct proc *proc;
7176 + int abort;
7177 +};
7178 +
7179 +dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)
7180 +{
7181 + int retval;
7182 + dwc_thread_t *thread = DWC_ALLOC(sizeof(*thread));
7183 +
7184 + if (!thread) {
7185 + return NULL;
7186 + }
7187 +
7188 + thread->abort = 0;
7189 + retval = kthread_create((void (*)(void *))func, data, &thread->proc,
7190 + RFPROC | RFNOWAIT, 0, "%s", name);
7191 + if (retval) {
7192 + DWC_FREE(thread);
7193 + return NULL;
7194 + }
7195 +
7196 + return thread;
7197 +}
7198 +
7199 +int DWC_THREAD_STOP(dwc_thread_t *thread)
7200 +{
7201 + int retval;
7202 +
7203 + thread->abort = 1;
7204 + retval = tsleep(&thread->abort, 0, "dw3stp", 60 * hz);
7205 +
7206 + if (retval == 0) {
7207 + /* DWC_THREAD_EXIT() will free the thread struct */
7208 + return 0;
7209 + }
7210 +
7211 + /* NOTE: We leak the thread struct if thread doesn't die */
7212 +
7213 + if (retval == EWOULDBLOCK) {
7214 + return -DWC_E_TIMEOUT;
7215 + }
7216 +
7217 + return -DWC_E_UNKNOWN;
7218 +}
7219 +
7220 +dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread)
7221 +{
7222 + return thread->abort;
7223 +}
7224 +
7225 +void DWC_THREAD_EXIT(dwc_thread_t *thread)
7226 +{
7227 + wakeup(&thread->abort);
7228 + DWC_FREE(thread);
7229 + kthread_exit(0);
7230 +}
7231 +
7232 +
7233 +/* tasklets
7234 + - Runs in interrupt context (cannot sleep)
7235 + - Each tasklet runs on a single CPU [ How can we ensure this on FreeBSD? Does it matter? ]
7236 + - Different tasklets can be running simultaneously on different CPUs [ shouldn't matter ]
7237 + */
7238 +struct dwc_tasklet {
7239 + struct task t;
7240 + dwc_tasklet_callback_t cb;
7241 + void *data;
7242 +};
7243 +
7244 +static void tasklet_callback(void *data, int pending) // what to do with pending ???
7245 +{
7246 + dwc_tasklet_t *task = (dwc_tasklet_t *)data;
7247 +
7248 + task->cb(task->data);
7249 +}
7250 +
7251 +dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)
7252 +{
7253 + dwc_tasklet_t *task = DWC_ALLOC(sizeof(*task));
7254 +
7255 + if (task) {
7256 + task->cb = cb;
7257 + task->data = data;
7258 + TASK_INIT(&task->t, 0, tasklet_callback, task);
7259 + } else {
7260 + DWC_ERROR("Cannot allocate memory for tasklet");
7261 + }
7262 +
7263 + return task;
7264 +}
7265 +
7266 +void DWC_TASK_FREE(dwc_tasklet_t *task)
7267 +{
7268 + taskqueue_drain(taskqueue_fast, &task->t); // ???
7269 + DWC_FREE(task);
7270 +}
7271 +
7272 +void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)
7273 +{
7274 + /* Uses predefined system queue */
7275 + taskqueue_enqueue_fast(taskqueue_fast, &task->t);
7276 +}
7277 +
7278 +
7279 +/* workqueues
7280 + - Runs in process context (can sleep)
7281 + */
7282 +typedef struct work_container {
7283 + dwc_work_callback_t cb;
7284 + void *data;
7285 + dwc_workq_t *wq;
7286 + char *name;
7287 + int hz;
7288 +
7289 +#ifdef DEBUG
7290 + DWC_CIRCLEQ_ENTRY(work_container) entry;
7291 +#endif
7292 + struct task task;
7293 +} work_container_t;
7294 +
7295 +#ifdef DEBUG
7296 +DWC_CIRCLEQ_HEAD(work_container_queue, work_container);
7297 +#endif
7298 +
7299 +struct dwc_workq {
7300 + struct taskqueue *taskq;
7301 + dwc_spinlock_t *lock;
7302 + dwc_waitq_t *waitq;
7303 + int pending;
7304 +
7305 +#ifdef DEBUG
7306 + struct work_container_queue entries;
7307 +#endif
7308 +};
7309 +
7310 +static void do_work(void *data, int pending) // what to do with pending ???
7311 +{
7312 + work_container_t *container = (work_container_t *)data;
7313 + dwc_workq_t *wq = container->wq;
7314 + dwc_irqflags_t flags;
7315 +
7316 + if (container->hz) {
7317 + pause("dw3wrk", container->hz);
7318 + }
7319 +
7320 + container->cb(container->data);
7321 + DWC_DEBUG("Work done: %s, container=%p", container->name, container);
7322 +
7323 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
7324 +
7325 +#ifdef DEBUG
7326 + DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry);
7327 +#endif
7328 + if (container->name)
7329 + DWC_FREE(container->name);
7330 + DWC_FREE(container);
7331 + wq->pending--;
7332 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
7333 + DWC_WAITQ_TRIGGER(wq->waitq);
7334 +}
7335 +
7336 +static int work_done(void *data)
7337 +{
7338 + dwc_workq_t *workq = (dwc_workq_t *)data;
7339 +
7340 + return workq->pending == 0;
7341 +}
7342 +
7343 +int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)
7344 +{
7345 + return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);
7346 +}
7347 +
7348 +dwc_workq_t *DWC_WORKQ_ALLOC(char *name)
7349 +{
7350 + dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));
7351 +
7352 + if (!wq) {
7353 + DWC_ERROR("Cannot allocate memory for workqueue");
7354 + return NULL;
7355 + }
7356 +
7357 + wq->taskq = taskqueue_create(name, M_NOWAIT, taskqueue_thread_enqueue, &wq->taskq);
7358 + if (!wq->taskq) {
7359 + DWC_ERROR("Cannot allocate memory for taskqueue");
7360 + goto no_taskq;
7361 + }
7362 +
7363 + wq->pending = 0;
7364 +
7365 + wq->lock = DWC_SPINLOCK_ALLOC();
7366 + if (!wq->lock) {
7367 + DWC_ERROR("Cannot allocate memory for spinlock");
7368 + goto no_lock;
7369 + }
7370 +
7371 + wq->waitq = DWC_WAITQ_ALLOC();
7372 + if (!wq->waitq) {
7373 + DWC_ERROR("Cannot allocate memory for waitqueue");
7374 + goto no_waitq;
7375 + }
7376 +
7377 + taskqueue_start_threads(&wq->taskq, 1, PWAIT, "%s taskq", "dw3tsk");
7378 +
7379 +#ifdef DEBUG
7380 + DWC_CIRCLEQ_INIT(&wq->entries);
7381 +#endif
7382 + return wq;
7383 +
7384 + no_waitq:
7385 + DWC_SPINLOCK_FREE(wq->lock);
7386 + no_lock:
7387 + taskqueue_free(wq->taskq);
7388 + no_taskq:
7389 + DWC_FREE(wq);
7390 +
7391 + return NULL;
7392 +}
7393 +
7394 +void DWC_WORKQ_FREE(dwc_workq_t *wq)
7395 +{
7396 +#ifdef DEBUG
7397 + dwc_irqflags_t flags;
7398 +
7399 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
7400 +
7401 + if (wq->pending != 0) {
7402 + struct work_container *container;
7403 +
7404 + DWC_ERROR("Destroying work queue with pending work");
7405 +
7406 + DWC_CIRCLEQ_FOREACH(container, &wq->entries, entry) {
7407 + DWC_ERROR("Work %s still pending", container->name);
7408 + }
7409 + }
7410 +
7411 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
7412 +#endif
7413 + DWC_WAITQ_FREE(wq->waitq);
7414 + DWC_SPINLOCK_FREE(wq->lock);
7415 + taskqueue_free(wq->taskq);
7416 + DWC_FREE(wq);
7417 +}
7418 +
7419 +void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,
7420 + char *format, ...)
7421 +{
7422 + dwc_irqflags_t flags;
7423 + work_container_t *container;
7424 + static char name[128];
7425 + va_list args;
7426 +
7427 + va_start(args, format);
7428 + DWC_VSNPRINTF(name, 128, format, args);
7429 + va_end(args);
7430 +
7431 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
7432 + wq->pending++;
7433 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
7434 + DWC_WAITQ_TRIGGER(wq->waitq);
7435 +
7436 + container = DWC_ALLOC_ATOMIC(sizeof(*container));
7437 + if (!container) {
7438 + DWC_ERROR("Cannot allocate memory for container");
7439 + return;
7440 + }
7441 +
7442 + container->name = DWC_STRDUP(name);
7443 + if (!container->name) {
7444 + DWC_ERROR("Cannot allocate memory for container->name");
7445 + DWC_FREE(container);
7446 + return;
7447 + }
7448 +
7449 + container->cb = cb;
7450 + container->data = data;
7451 + container->wq = wq;
7452 + container->hz = 0;
7453 +
7454 + DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
7455 +
7456 + TASK_INIT(&container->task, 0, do_work, container);
7457 +
7458 +#ifdef DEBUG
7459 + DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
7460 +#endif
7461 + taskqueue_enqueue_fast(wq->taskq, &container->task);
7462 +}
7463 +
7464 +void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,
7465 + void *data, uint32_t time, char *format, ...)
7466 +{
7467 + dwc_irqflags_t flags;
7468 + work_container_t *container;
7469 + static char name[128];
7470 + struct timeval tv;
7471 + va_list args;
7472 +
7473 + va_start(args, format);
7474 + DWC_VSNPRINTF(name, 128, format, args);
7475 + va_end(args);
7476 +
7477 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
7478 + wq->pending++;
7479 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
7480 + DWC_WAITQ_TRIGGER(wq->waitq);
7481 +
7482 + container = DWC_ALLOC_ATOMIC(sizeof(*container));
7483 + if (!container) {
7484 + DWC_ERROR("Cannot allocate memory for container");
7485 + return;
7486 + }
7487 +
7488 + container->name = DWC_STRDUP(name);
7489 + if (!container->name) {
7490 + DWC_ERROR("Cannot allocate memory for container->name");
7491 + DWC_FREE(container);
7492 + return;
7493 + }
7494 +
7495 + container->cb = cb;
7496 + container->data = data;
7497 + container->wq = wq;
7498 +
7499 + tv.tv_sec = time / 1000;
7500 + tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
7501 + container->hz = tvtohz(&tv);
7502 +
7503 + DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
7504 +
7505 + TASK_INIT(&container->task, 0, do_work, container);
7506 +
7507 +#ifdef DEBUG
7508 + DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
7509 +#endif
7510 + taskqueue_enqueue_fast(wq->taskq, &container->task);
7511 +}
7512 +
7513 +int DWC_WORKQ_PENDING(dwc_workq_t *wq)
7514 +{
7515 + return wq->pending;
7516 +}
7517 --- /dev/null
7518 +++ b/drivers/usb/host/dwc_common_port/dwc_common_linux.c
7519 @@ -0,0 +1,1434 @@
7520 +#include <linux/kernel.h>
7521 +#include <linux/init.h>
7522 +#include <linux/module.h>
7523 +#include <linux/kthread.h>
7524 +
7525 +#ifdef DWC_CCLIB
7526 +# include "dwc_cc.h"
7527 +#endif
7528 +
7529 +#ifdef DWC_CRYPTOLIB
7530 +# include "dwc_modpow.h"
7531 +# include "dwc_dh.h"
7532 +# include "dwc_crypto.h"
7533 +#endif
7534 +
7535 +#ifdef DWC_NOTIFYLIB
7536 +# include "dwc_notifier.h"
7537 +#endif
7538 +
7539 +/* OS-Level Implementations */
7540 +
7541 +/* This is the Linux kernel implementation of the DWC platform library. */
7542 +#include <linux/moduleparam.h>
7543 +#include <linux/ctype.h>
7544 +#include <linux/crypto.h>
7545 +#include <linux/delay.h>
7546 +#include <linux/device.h>
7547 +#include <linux/dma-mapping.h>
7548 +#include <linux/cdev.h>
7549 +#include <linux/errno.h>
7550 +#include <linux/interrupt.h>
7551 +#include <linux/jiffies.h>
7552 +#include <linux/list.h>
7553 +#include <linux/pci.h>
7554 +#include <linux/random.h>
7555 +#include <linux/scatterlist.h>
7556 +#include <linux/slab.h>
7557 +#include <linux/stat.h>
7558 +#include <linux/string.h>
7559 +#include <linux/timer.h>
7560 +#include <linux/usb.h>
7561 +
7562 +#include <linux/version.h>
7563 +
7564 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
7565 +# include <linux/usb/gadget.h>
7566 +#else
7567 +# include <linux/usb_gadget.h>
7568 +#endif
7569 +
7570 +#include <asm/io.h>
7571 +#include <asm/page.h>
7572 +#include <asm/uaccess.h>
7573 +#include <asm/unaligned.h>
7574 +
7575 +#include "dwc_os.h"
7576 +#include "dwc_list.h"
7577 +
7578 +
7579 +/* MISC */
7580 +
7581 +void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)
7582 +{
7583 + return memset(dest, byte, size);
7584 +}
7585 +
7586 +void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)
7587 +{
7588 + return memcpy(dest, src, size);
7589 +}
7590 +
7591 +void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)
7592 +{
7593 + return memmove(dest, src, size);
7594 +}
7595 +
7596 +int DWC_MEMCMP(void *m1, void *m2, uint32_t size)
7597 +{
7598 + return memcmp(m1, m2, size);
7599 +}
7600 +
7601 +int DWC_STRNCMP(void *s1, void *s2, uint32_t size)
7602 +{
7603 + return strncmp(s1, s2, size);
7604 +}
7605 +
7606 +int DWC_STRCMP(void *s1, void *s2)
7607 +{
7608 + return strcmp(s1, s2);
7609 +}
7610 +
7611 +int DWC_STRLEN(char const *str)
7612 +{
7613 + return strlen(str);
7614 +}
7615 +
7616 +char *DWC_STRCPY(char *to, char const *from)
7617 +{
7618 + return strcpy(to, from);
7619 +}
7620 +
7621 +char *DWC_STRDUP(char const *str)
7622 +{
7623 + int len = DWC_STRLEN(str) + 1;
7624 + char *new = DWC_ALLOC_ATOMIC(len);
7625 +
7626 + if (!new) {
7627 + return NULL;
7628 + }
7629 +
7630 + DWC_MEMCPY(new, str, len);
7631 + return new;
7632 +}
7633 +
7634 +int DWC_ATOI(const char *str, int32_t *value)
7635 +{
7636 + char *end = NULL;
7637 +
7638 + *value = simple_strtol(str, &end, 0);
7639 + if (*end == '\0') {
7640 + return 0;
7641 + }
7642 +
7643 + return -1;
7644 +}
7645 +
7646 +int DWC_ATOUI(const char *str, uint32_t *value)
7647 +{
7648 + char *end = NULL;
7649 +
7650 + *value = simple_strtoul(str, &end, 0);
7651 + if (*end == '\0') {
7652 + return 0;
7653 + }
7654 +
7655 + return -1;
7656 +}
7657 +
7658 +
7659 +#ifdef DWC_UTFLIB
7660 +/* From usbstring.c */
7661 +
7662 +int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)
7663 +{
7664 + int count = 0;
7665 + u8 c;
7666 + u16 uchar;
7667 +
7668 + /* this insists on correct encodings, though not minimal ones.
7669 + * BUT it currently rejects legit 4-byte UTF-8 code points,
7670 + * which need surrogate pairs. (Unicode 3.1 can use them.)
7671 + */
7672 + while (len != 0 && (c = (u8) *s++) != 0) {
7673 + if (unlikely(c & 0x80)) {
7674 + // 2-byte sequence:
7675 + // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
7676 + if ((c & 0xe0) == 0xc0) {
7677 + uchar = (c & 0x1f) << 6;
7678 +
7679 + c = (u8) *s++;
7680 + if ((c & 0xc0) != 0xc0)
7681 + goto fail;
7682 + c &= 0x3f;
7683 + uchar |= c;
7684 +
7685 + // 3-byte sequence (most CJKV characters):
7686 + // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
7687 + } else if ((c & 0xf0) == 0xe0) {
7688 + uchar = (c & 0x0f) << 12;
7689 +
7690 + c = (u8) *s++;
7691 + if ((c & 0xc0) != 0xc0)
7692 + goto fail;
7693 + c &= 0x3f;
7694 + uchar |= c << 6;
7695 +
7696 + c = (u8) *s++;
7697 + if ((c & 0xc0) != 0xc0)
7698 + goto fail;
7699 + c &= 0x3f;
7700 + uchar |= c;
7701 +
7702 + /* no bogus surrogates */
7703 + if (0xd800 <= uchar && uchar <= 0xdfff)
7704 + goto fail;
7705 +
7706 + // 4-byte sequence (surrogate pairs, currently rare):
7707 + // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
7708 + // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
7709 + // (uuuuu = wwww + 1)
7710 + // FIXME accept the surrogate code points (only)
7711 + } else
7712 + goto fail;
7713 + } else
7714 + uchar = c;
7715 + put_unaligned (cpu_to_le16 (uchar), cp++);
7716 + count++;
7717 + len--;
7718 + }
7719 + return count;
7720 +fail:
7721 + return -1;
7722 +}
7723 +#endif /* DWC_UTFLIB */
7724 +
7725 +
7726 +/* dwc_debug.h */
7727 +
7728 +dwc_bool_t DWC_IN_IRQ(void)
7729 +{
7730 + return in_irq();
7731 +}
7732 +
7733 +dwc_bool_t DWC_IN_BH(void)
7734 +{
7735 + return in_softirq();
7736 +}
7737 +
7738 +void DWC_VPRINTF(char *format, va_list args)
7739 +{
7740 + vprintk(format, args);
7741 +}
7742 +
7743 +int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)
7744 +{
7745 + return vsnprintf(str, size, format, args);
7746 +}
7747 +
7748 +void DWC_PRINTF(char *format, ...)
7749 +{
7750 + va_list args;
7751 +
7752 + va_start(args, format);
7753 + DWC_VPRINTF(format, args);
7754 + va_end(args);
7755 +}
7756 +
7757 +int DWC_SPRINTF(char *buffer, char *format, ...)
7758 +{
7759 + int retval;
7760 + va_list args;
7761 +
7762 + va_start(args, format);
7763 + retval = vsprintf(buffer, format, args);
7764 + va_end(args);
7765 + return retval;
7766 +}
7767 +
7768 +int DWC_SNPRINTF(char *buffer, int size, char *format, ...)
7769 +{
7770 + int retval;
7771 + va_list args;
7772 +
7773 + va_start(args, format);
7774 + retval = vsnprintf(buffer, size, format, args);
7775 + va_end(args);
7776 + return retval;
7777 +}
7778 +
7779 +void __DWC_WARN(char *format, ...)
7780 +{
7781 + va_list args;
7782 +
7783 + va_start(args, format);
7784 + DWC_PRINTF(KERN_WARNING);
7785 + DWC_VPRINTF(format, args);
7786 + va_end(args);
7787 +}
7788 +
7789 +void __DWC_ERROR(char *format, ...)
7790 +{
7791 + va_list args;
7792 +
7793 + va_start(args, format);
7794 + DWC_PRINTF(KERN_ERR);
7795 + DWC_VPRINTF(format, args);
7796 + va_end(args);
7797 +}
7798 +
7799 +void DWC_EXCEPTION(char *format, ...)
7800 +{
7801 + va_list args;
7802 +
7803 + va_start(args, format);
7804 + DWC_PRINTF(KERN_ERR);
7805 + DWC_VPRINTF(format, args);
7806 + va_end(args);
7807 + BUG_ON(1);
7808 +}
7809 +
7810 +#ifdef DEBUG
7811 +void __DWC_DEBUG(char *format, ...)
7812 +{
7813 + va_list args;
7814 +
7815 + va_start(args, format);
7816 + DWC_PRINTF(KERN_DEBUG);
7817 + DWC_VPRINTF(format, args);
7818 + va_end(args);
7819 +}
7820 +#endif
7821 +
7822 +
7823 +/* dwc_mem.h */
7824 +
7825 +#if 0
7826 +dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,
7827 + uint32_t align,
7828 + uint32_t alloc)
7829 +{
7830 + struct dma_pool *pool = dma_pool_create("Pool", NULL,
7831 + size, align, alloc);
7832 + return (dwc_pool_t *)pool;
7833 +}
7834 +
7835 +void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)
7836 +{
7837 + dma_pool_destroy((struct dma_pool *)pool);
7838 +}
7839 +
7840 +void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
7841 +{
7842 + return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);
7843 +}
7844 +
7845 +void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
7846 +{
7847 + void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);
7848 + memset(..);
7849 +}
7850 +
7851 +void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)
7852 +{
7853 + dma_pool_free(pool, vaddr, daddr);
7854 +}
7855 +#endif
7856 +
7857 +void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
7858 +{
7859 +#ifdef xxCOSIM /* Only works for 32-bit cosim */
7860 + void *buf = dma_alloc_coherent(dma_ctx, (size_t)size, dma_addr, GFP_KERNEL);
7861 +#else
7862 + void *buf = dma_alloc_coherent(dma_ctx, (size_t)size, dma_addr, GFP_KERNEL | GFP_DMA32);
7863 +#endif
7864 + if (!buf) {
7865 + return NULL;
7866 + }
7867 +
7868 + memset(buf, 0, (size_t)size);
7869 + return buf;
7870 +}
7871 +
7872 +void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
7873 +{
7874 + void *buf = dma_alloc_coherent(NULL, (size_t)size, dma_addr, GFP_ATOMIC);
7875 + if (!buf) {
7876 + return NULL;
7877 + }
7878 + memset(buf, 0, (size_t)size);
7879 + return buf;
7880 +}
7881 +
7882 +void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
7883 +{
7884 + dma_free_coherent(dma_ctx, size, virt_addr, dma_addr);
7885 +}
7886 +
7887 +void *__DWC_ALLOC(void *mem_ctx, uint32_t size)
7888 +{
7889 + return kzalloc(size, GFP_KERNEL);
7890 +}
7891 +
7892 +void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)
7893 +{
7894 + return kzalloc(size, GFP_ATOMIC);
7895 +}
7896 +
7897 +void __DWC_FREE(void *mem_ctx, void *addr)
7898 +{
7899 + kfree(addr);
7900 +}
7901 +
7902 +
7903 +#ifdef DWC_CRYPTOLIB
7904 +/* dwc_crypto.h */
7905 +
7906 +void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)
7907 +{
7908 + get_random_bytes(buffer, length);
7909 +}
7910 +
7911 +int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
7912 +{
7913 + struct crypto_blkcipher *tfm;
7914 + struct blkcipher_desc desc;
7915 + struct scatterlist sgd;
7916 + struct scatterlist sgs;
7917 +
7918 + tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
7919 + if (tfm == NULL) {
7920 + printk("failed to load transform for aes CBC\n");
7921 + return -1;
7922 + }
7923 +
7924 + crypto_blkcipher_setkey(tfm, key, keylen);
7925 + crypto_blkcipher_set_iv(tfm, iv, 16);
7926 +
7927 + sg_init_one(&sgd, out, messagelen);
7928 + sg_init_one(&sgs, message, messagelen);
7929 +
7930 + desc.tfm = tfm;
7931 + desc.flags = 0;
7932 +
7933 + if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {
7934 + crypto_free_blkcipher(tfm);
7935 + DWC_ERROR("AES CBC encryption failed");
7936 + return -1;
7937 + }
7938 +
7939 + crypto_free_blkcipher(tfm);
7940 + return 0;
7941 +}
7942 +
7943 +int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)
7944 +{
7945 + struct crypto_hash *tfm;
7946 + struct hash_desc desc;
7947 + struct scatterlist sg;
7948 +
7949 + tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC);
7950 + if (IS_ERR(tfm)) {
7951 + DWC_ERROR("Failed to load transform for sha256: %ld\n", PTR_ERR(tfm));
7952 + return 0;
7953 + }
7954 + desc.tfm = tfm;
7955 + desc.flags = 0;
7956 +
7957 + sg_init_one(&sg, message, len);
7958 + crypto_hash_digest(&desc, &sg, len, out);
7959 + crypto_free_hash(tfm);
7960 +
7961 + return 1;
7962 +}
7963 +
7964 +int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,
7965 + uint8_t *key, uint32_t keylen, uint8_t *out)
7966 +{
7967 + struct crypto_hash *tfm;
7968 + struct hash_desc desc;
7969 + struct scatterlist sg;
7970 +
7971 + tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC);
7972 + if (IS_ERR(tfm)) {
7973 + DWC_ERROR("Failed to load transform for hmac(sha256): %ld\n", PTR_ERR(tfm));
7974 + return 0;
7975 + }
7976 + desc.tfm = tfm;
7977 + desc.flags = 0;
7978 +
7979 + sg_init_one(&sg, message, messagelen);
7980 + crypto_hash_setkey(tfm, key, keylen);
7981 + crypto_hash_digest(&desc, &sg, messagelen, out);
7982 + crypto_free_hash(tfm);
7983 +
7984 + return 1;
7985 +}
7986 +#endif /* DWC_CRYPTOLIB */
7987 +
7988 +
7989 +/* Byte Ordering Conversions */
7990 +
7991 +uint32_t DWC_CPU_TO_LE32(uint32_t *p)
7992 +{
7993 +#ifdef __LITTLE_ENDIAN
7994 + return *p;
7995 +#else
7996 + uint8_t *u_p = (uint8_t *)p;
7997 +
7998 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
7999 +#endif
8000 +}
8001 +
8002 +uint32_t DWC_CPU_TO_BE32(uint32_t *p)
8003 +{
8004 +#ifdef __BIG_ENDIAN
8005 + return *p;
8006 +#else
8007 + uint8_t *u_p = (uint8_t *)p;
8008 +
8009 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
8010 +#endif
8011 +}
8012 +
8013 +uint32_t DWC_LE32_TO_CPU(uint32_t *p)
8014 +{
8015 +#ifdef __LITTLE_ENDIAN
8016 + return *p;
8017 +#else
8018 + uint8_t *u_p = (uint8_t *)p;
8019 +
8020 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
8021 +#endif
8022 +}
8023 +
8024 +uint32_t DWC_BE32_TO_CPU(uint32_t *p)
8025 +{
8026 +#ifdef __BIG_ENDIAN
8027 + return *p;
8028 +#else
8029 + uint8_t *u_p = (uint8_t *)p;
8030 +
8031 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
8032 +#endif
8033 +}
8034 +
8035 +uint16_t DWC_CPU_TO_LE16(uint16_t *p)
8036 +{
8037 +#ifdef __LITTLE_ENDIAN
8038 + return *p;
8039 +#else
8040 + uint8_t *u_p = (uint8_t *)p;
8041 + return (u_p[1] | (u_p[0] << 8));
8042 +#endif
8043 +}
8044 +
8045 +uint16_t DWC_CPU_TO_BE16(uint16_t *p)
8046 +{
8047 +#ifdef __BIG_ENDIAN
8048 + return *p;
8049 +#else
8050 + uint8_t *u_p = (uint8_t *)p;
8051 + return (u_p[1] | (u_p[0] << 8));
8052 +#endif
8053 +}
8054 +
8055 +uint16_t DWC_LE16_TO_CPU(uint16_t *p)
8056 +{
8057 +#ifdef __LITTLE_ENDIAN
8058 + return *p;
8059 +#else
8060 + uint8_t *u_p = (uint8_t *)p;
8061 + return (u_p[1] | (u_p[0] << 8));
8062 +#endif
8063 +}
8064 +
8065 +uint16_t DWC_BE16_TO_CPU(uint16_t *p)
8066 +{
8067 +#ifdef __BIG_ENDIAN
8068 + return *p;
8069 +#else
8070 + uint8_t *u_p = (uint8_t *)p;
8071 + return (u_p[1] | (u_p[0] << 8));
8072 +#endif
8073 +}
8074 +
8075 +
8076 +/* Registers */
8077 +
8078 +uint32_t DWC_READ_REG32(uint32_t volatile *reg)
8079 +{
8080 + return readl(reg);
8081 +}
8082 +
8083 +#if 0
8084 +uint64_t DWC_READ_REG64(uint64_t volatile *reg)
8085 +{
8086 +}
8087 +#endif
8088 +
8089 +void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value)
8090 +{
8091 + writel(value, reg);
8092 +}
8093 +
8094 +#if 0
8095 +void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value)
8096 +{
8097 +}
8098 +#endif
8099 +
8100 +void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask)
8101 +{
8102 + writel((readl(reg) & ~clear_mask) | set_mask, reg);
8103 +}
8104 +
8105 +#if 0
8106 +void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask)
8107 +{
8108 +}
8109 +#endif
8110 +
8111 +
8112 +/* Locking */
8113 +
8114 +dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)
8115 +{
8116 + spinlock_t *sl = (spinlock_t *)1;
8117 +
8118 +#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
8119 + sl = DWC_ALLOC(sizeof(*sl));
8120 + if (!sl) {
8121 + DWC_ERROR("Cannot allocate memory for spinlock\n");
8122 + return NULL;
8123 + }
8124 +
8125 + spin_lock_init(sl);
8126 +#endif
8127 + return (dwc_spinlock_t *)sl;
8128 +}
8129 +
8130 +void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)
8131 +{
8132 +#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
8133 + DWC_FREE(lock);
8134 +#endif
8135 +}
8136 +
8137 +void DWC_SPINLOCK(dwc_spinlock_t *lock)
8138 +{
8139 +#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
8140 + spin_lock((spinlock_t *)lock);
8141 +#endif
8142 +}
8143 +
8144 +void DWC_SPINUNLOCK(dwc_spinlock_t *lock)
8145 +{
8146 +#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
8147 + spin_unlock((spinlock_t *)lock);
8148 +#endif
8149 +}
8150 +
8151 +void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)
8152 +{
8153 + dwc_irqflags_t f;
8154 +
8155 +#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
8156 + spin_lock_irqsave((spinlock_t *)lock, f);
8157 +#else
8158 + local_irq_save(f);
8159 +#endif
8160 + *flags = f;
8161 +}
8162 +
8163 +void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)
8164 +{
8165 +#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
8166 + spin_unlock_irqrestore((spinlock_t *)lock, flags);
8167 +#else
8168 + local_irq_restore(flags);
8169 +#endif
8170 +}
8171 +
8172 +dwc_mutex_t *DWC_MUTEX_ALLOC(void)
8173 +{
8174 + struct mutex *m;
8175 + dwc_mutex_t *mutex = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex));
8176 +
8177 + if (!mutex) {
8178 + DWC_ERROR("Cannot allocate memory for mutex\n");
8179 + return NULL;
8180 + }
8181 +
8182 + m = (struct mutex *)mutex;
8183 + mutex_init(m);
8184 + return mutex;
8185 +}
8186 +
8187 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
8188 +#else
8189 +void DWC_MUTEX_FREE(dwc_mutex_t *mutex)
8190 +{
8191 + mutex_destroy((struct mutex *)mutex);
8192 + DWC_FREE(mutex);
8193 +}
8194 +#endif
8195 +
8196 +void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)
8197 +{
8198 + struct mutex *m = (struct mutex *)mutex;
8199 + mutex_lock(m);
8200 +}
8201 +
8202 +int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)
8203 +{
8204 + struct mutex *m = (struct mutex *)mutex;
8205 + return mutex_trylock(m);
8206 +}
8207 +
8208 +void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)
8209 +{
8210 + struct mutex *m = (struct mutex *)mutex;
8211 + mutex_unlock(m);
8212 +}
8213 +
8214 +
8215 +/* Timing */
8216 +
8217 +void DWC_UDELAY(uint32_t usecs)
8218 +{
8219 + udelay(usecs);
8220 +}
8221 +
8222 +void DWC_MDELAY(uint32_t msecs)
8223 +{
8224 + mdelay(msecs);
8225 +}
8226 +
8227 +void DWC_MSLEEP(uint32_t msecs)
8228 +{
8229 + msleep(msecs);
8230 +}
8231 +
8232 +uint32_t DWC_TIME(void)
8233 +{
8234 + return jiffies_to_msecs(jiffies);
8235 +}
8236 +
8237 +
8238 +/* Timers */
8239 +
8240 +struct dwc_timer {
8241 + struct timer_list *t;
8242 + char *name;
8243 + dwc_timer_callback_t cb;
8244 + void *data;
8245 + uint8_t scheduled;
8246 + dwc_spinlock_t *lock;
8247 +};
8248 +
8249 +static void timer_callback(unsigned long data)
8250 +{
8251 + dwc_timer_t *timer = (dwc_timer_t *)data;
8252 + dwc_irqflags_t flags;
8253 +
8254 + DWC_SPINLOCK_IRQSAVE(timer->lock, &flags);
8255 + timer->scheduled = 0;
8256 + DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);
8257 + DWC_DEBUGC("Timer %s callback", timer->name);
8258 + timer->cb(timer->data);
8259 +}
8260 +
8261 +dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)
8262 +{
8263 + dwc_timer_t *t = DWC_ALLOC(sizeof(*t));
8264 +
8265 + if (!t) {
8266 + DWC_ERROR("Cannot allocate memory for timer");
8267 + return NULL;
8268 + }
8269 +
8270 + t->t = DWC_ALLOC(sizeof(*t->t));
8271 + if (!t->t) {
8272 + DWC_ERROR("Cannot allocate memory for timer->t");
8273 + goto no_timer;
8274 + }
8275 +
8276 + t->name = DWC_STRDUP(name);
8277 + if (!t->name) {
8278 + DWC_ERROR("Cannot allocate memory for timer->name");
8279 + goto no_name;
8280 + }
8281 +
8282 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))
8283 + DWC_SPINLOCK_ALLOC_LINUX_DEBUG(t->lock);
8284 +#else
8285 + t->lock = DWC_SPINLOCK_ALLOC();
8286 +#endif
8287 + if (!t->lock) {
8288 + DWC_ERROR("Cannot allocate memory for lock");
8289 + goto no_lock;
8290 + }
8291 +
8292 + t->scheduled = 0;
8293 + t->t->base = &boot_tvec_bases;
8294 + t->t->expires = jiffies;
8295 + setup_timer(t->t, timer_callback, (unsigned long)t);
8296 +
8297 + t->cb = cb;
8298 + t->data = data;
8299 +
8300 + return t;
8301 +
8302 + no_lock:
8303 + DWC_FREE(t->name);
8304 + no_name:
8305 + DWC_FREE(t->t);
8306 + no_timer:
8307 + DWC_FREE(t);
8308 + return NULL;
8309 +}
8310 +
8311 +void DWC_TIMER_FREE(dwc_timer_t *timer)
8312 +{
8313 + dwc_irqflags_t flags;
8314 +
8315 + DWC_SPINLOCK_IRQSAVE(timer->lock, &flags);
8316 +
8317 + if (timer->scheduled) {
8318 + del_timer(timer->t);
8319 + timer->scheduled = 0;
8320 + }
8321 +
8322 + DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);
8323 + DWC_SPINLOCK_FREE(timer->lock);
8324 + DWC_FREE(timer->t);
8325 + DWC_FREE(timer->name);
8326 + DWC_FREE(timer);
8327 +}
8328 +
8329 +void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)
8330 +{
8331 + dwc_irqflags_t flags;
8332 +
8333 + DWC_SPINLOCK_IRQSAVE(timer->lock, &flags);
8334 +
8335 + if (!timer->scheduled) {
8336 + timer->scheduled = 1;
8337 + DWC_DEBUGC("Scheduling timer %s to expire in +%d msec", timer->name, time);
8338 + timer->t->expires = jiffies + msecs_to_jiffies(time);
8339 + add_timer(timer->t);
8340 + } else {
8341 + DWC_DEBUGC("Modifying timer %s to expire in +%d msec", timer->name, time);
8342 + mod_timer(timer->t, jiffies + msecs_to_jiffies(time));
8343 + }
8344 +
8345 + DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);
8346 +}
8347 +
8348 +void DWC_TIMER_CANCEL(dwc_timer_t *timer)
8349 +{
8350 + del_timer(timer->t);
8351 +}
8352 +
8353 +
8354 +/* Wait Queues */
8355 +
8356 +struct dwc_waitq {
8357 + wait_queue_head_t queue;
8358 + int abort;
8359 +};
8360 +
8361 +dwc_waitq_t *DWC_WAITQ_ALLOC(void)
8362 +{
8363 + dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));
8364 +
8365 + if (!wq) {
8366 + DWC_ERROR("Cannot allocate memory for waitqueue\n");
8367 + return NULL;
8368 + }
8369 +
8370 + init_waitqueue_head(&wq->queue);
8371 + wq->abort = 0;
8372 + return wq;
8373 +}
8374 +
8375 +void DWC_WAITQ_FREE(dwc_waitq_t *wq)
8376 +{
8377 + DWC_FREE(wq);
8378 +}
8379 +
8380 +int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)
8381 +{
8382 + int result = wait_event_interruptible(wq->queue,
8383 + cond(data) || wq->abort);
8384 + if (result == -ERESTARTSYS) {
8385 + wq->abort = 0;
8386 + return -DWC_E_RESTART;
8387 + }
8388 +
8389 + if (wq->abort == 1) {
8390 + wq->abort = 0;
8391 + return -DWC_E_ABORT;
8392 + }
8393 +
8394 + wq->abort = 0;
8395 +
8396 + if (result == 0) {
8397 + return 0;
8398 + }
8399 +
8400 + return -DWC_E_UNKNOWN;
8401 +}
8402 +
8403 +int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
8404 + void *data, int32_t msecs)
8405 +{
8406 + int32_t tmsecs;
8407 + int result = wait_event_interruptible_timeout(wq->queue,
8408 + cond(data) || wq->abort,
8409 + msecs_to_jiffies(msecs));
8410 + if (result == -ERESTARTSYS) {
8411 + wq->abort = 0;
8412 + return -DWC_E_RESTART;
8413 + }
8414 +
8415 + if (wq->abort == 1) {
8416 + wq->abort = 0;
8417 + return -DWC_E_ABORT;
8418 + }
8419 +
8420 + wq->abort = 0;
8421 +
8422 + if (result > 0) {
8423 + tmsecs = jiffies_to_msecs(result);
8424 + if (!tmsecs) {
8425 + return 1;
8426 + }
8427 +
8428 + return tmsecs;
8429 + }
8430 +
8431 + if (result == 0) {
8432 + return -DWC_E_TIMEOUT;
8433 + }
8434 +
8435 + return -DWC_E_UNKNOWN;
8436 +}
8437 +
8438 +void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)
8439 +{
8440 + wq->abort = 0;
8441 + wake_up_interruptible(&wq->queue);
8442 +}
8443 +
8444 +void DWC_WAITQ_ABORT(dwc_waitq_t *wq)
8445 +{
8446 + wq->abort = 1;
8447 + wake_up_interruptible(&wq->queue);
8448 +}
8449 +
8450 +
8451 +/* Threading */
8452 +
8453 +dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)
8454 +{
8455 + struct task_struct *thread = kthread_run(func, data, name);
8456 +
8457 + if (thread == ERR_PTR(-ENOMEM)) {
8458 + return NULL;
8459 + }
8460 +
8461 + return (dwc_thread_t *)thread;
8462 +}
8463 +
8464 +int DWC_THREAD_STOP(dwc_thread_t *thread)
8465 +{
8466 + return kthread_stop((struct task_struct *)thread);
8467 +}
8468 +
8469 +dwc_bool_t DWC_THREAD_SHOULD_STOP(void)
8470 +{
8471 + return kthread_should_stop();
8472 +}
8473 +
8474 +
8475 +/* tasklets
8476 + - run in interrupt context (cannot sleep)
8477 + - each tasklet runs on a single CPU
8478 + - different tasklets can be running simultaneously on different CPUs
8479 + */
8480 +struct dwc_tasklet {
8481 + struct tasklet_struct t;
8482 + dwc_tasklet_callback_t cb;
8483 + void *data;
8484 +};
8485 +
8486 +static void tasklet_callback(unsigned long data)
8487 +{
8488 + dwc_tasklet_t *t = (dwc_tasklet_t *)data;
8489 + t->cb(t->data);
8490 +}
8491 +
8492 +dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)
8493 +{
8494 + dwc_tasklet_t *t = DWC_ALLOC(sizeof(*t));
8495 +
8496 + if (t) {
8497 + t->cb = cb;
8498 + t->data = data;
8499 + tasklet_init(&t->t, tasklet_callback, (unsigned long)t);
8500 + } else {
8501 + DWC_ERROR("Cannot allocate memory for tasklet\n");
8502 + }
8503 +
8504 + return t;
8505 +}
8506 +
8507 +void DWC_TASK_FREE(dwc_tasklet_t *task)
8508 +{
8509 + DWC_FREE(task);
8510 +}
8511 +
8512 +void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)
8513 +{
8514 + tasklet_schedule(&task->t);
8515 +}
8516 +
8517 +void DWC_TASK_HI_SCHEDULE(dwc_tasklet_t *task)
8518 +{
8519 + tasklet_hi_schedule(&task->t);
8520 +}
8521 +
8522 +
8523 +/* workqueues
8524 + - run in process context (can sleep)
8525 + */
8526 +typedef struct work_container {
8527 + dwc_work_callback_t cb;
8528 + void *data;
8529 + dwc_workq_t *wq;
8530 + char *name;
8531 +
8532 +#ifdef DEBUG
8533 + DWC_CIRCLEQ_ENTRY(work_container) entry;
8534 +#endif
8535 + struct delayed_work work;
8536 +} work_container_t;
8537 +
8538 +#ifdef DEBUG
8539 +DWC_CIRCLEQ_HEAD(work_container_queue, work_container);
8540 +#endif
8541 +
8542 +struct dwc_workq {
8543 + struct workqueue_struct *wq;
8544 + dwc_spinlock_t *lock;
8545 + dwc_waitq_t *waitq;
8546 + int pending;
8547 +
8548 +#ifdef DEBUG
8549 + struct work_container_queue entries;
8550 +#endif
8551 +};
8552 +
8553 +static void do_work(struct work_struct *work)
8554 +{
8555 + dwc_irqflags_t flags;
8556 + struct delayed_work *dw = container_of(work, struct delayed_work, work);
8557 + work_container_t *container = container_of(dw, struct work_container, work);
8558 + dwc_workq_t *wq = container->wq;
8559 +
8560 + container->cb(container->data);
8561 +
8562 +#ifdef DEBUG
8563 + DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry);
8564 +#endif
8565 + DWC_DEBUGC("Work done: %s, container=%p", container->name, container);
8566 + if (container->name) {
8567 + DWC_FREE(container->name);
8568 + }
8569 + DWC_FREE(container);
8570 +
8571 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
8572 + wq->pending--;
8573 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
8574 + DWC_WAITQ_TRIGGER(wq->waitq);
8575 +}
8576 +
8577 +static int work_done(void *data)
8578 +{
8579 + dwc_workq_t *workq = (dwc_workq_t *)data;
8580 + return workq->pending == 0;
8581 +}
8582 +
8583 +int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)
8584 +{
8585 + return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);
8586 +}
8587 +
8588 +dwc_workq_t *DWC_WORKQ_ALLOC(char *name)
8589 +{
8590 + dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));
8591 +
8592 + if (!wq) {
8593 + return NULL;
8594 + }
8595 +
8596 + wq->wq = create_singlethread_workqueue(name);
8597 + if (!wq->wq) {
8598 + goto no_wq;
8599 + }
8600 +
8601 + wq->pending = 0;
8602 +
8603 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))
8604 + DWC_SPINLOCK_ALLOC_LINUX_DEBUG(wq->lock);
8605 +#else
8606 + wq->lock = DWC_SPINLOCK_ALLOC();
8607 +#endif
8608 + if (!wq->lock) {
8609 + goto no_lock;
8610 + }
8611 +
8612 + wq->waitq = DWC_WAITQ_ALLOC();
8613 + if (!wq->waitq) {
8614 + goto no_waitq;
8615 + }
8616 +
8617 +#ifdef DEBUG
8618 + DWC_CIRCLEQ_INIT(&wq->entries);
8619 +#endif
8620 + return wq;
8621 +
8622 + no_waitq:
8623 + DWC_SPINLOCK_FREE(wq->lock);
8624 + no_lock:
8625 + destroy_workqueue(wq->wq);
8626 + no_wq:
8627 + DWC_FREE(wq);
8628 +
8629 + return NULL;
8630 +}
8631 +
8632 +void DWC_WORKQ_FREE(dwc_workq_t *wq)
8633 +{
8634 +#ifdef DEBUG
8635 + if (wq->pending != 0) {
8636 + struct work_container *wc;
8637 + DWC_ERROR("Destroying work queue with pending work");
8638 + DWC_CIRCLEQ_FOREACH(wc, &wq->entries, entry) {
8639 + DWC_ERROR("Work %s still pending", wc->name);
8640 + }
8641 + }
8642 +#endif
8643 + destroy_workqueue(wq->wq);
8644 + DWC_SPINLOCK_FREE(wq->lock);
8645 + DWC_WAITQ_FREE(wq->waitq);
8646 + DWC_FREE(wq);
8647 +}
8648 +
8649 +void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,
8650 + char *format, ...)
8651 +{
8652 + dwc_irqflags_t flags;
8653 + work_container_t *container;
8654 + static char name[128];
8655 + va_list args;
8656 +
8657 + va_start(args, format);
8658 + DWC_VSNPRINTF(name, 128, format, args);
8659 + va_end(args);
8660 +
8661 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
8662 + wq->pending++;
8663 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
8664 + DWC_WAITQ_TRIGGER(wq->waitq);
8665 +
8666 + container = DWC_ALLOC_ATOMIC(sizeof(*container));
8667 + if (!container) {
8668 + DWC_ERROR("Cannot allocate memory for container\n");
8669 + return;
8670 + }
8671 +
8672 + container->name = DWC_STRDUP(name);
8673 + if (!container->name) {
8674 + DWC_ERROR("Cannot allocate memory for container->name\n");
8675 + DWC_FREE(container);
8676 + return;
8677 + }
8678 +
8679 + container->cb = cb;
8680 + container->data = data;
8681 + container->wq = wq;
8682 + DWC_DEBUGC("Queueing work: %s, container=%p", container->name, container);
8683 + INIT_WORK(&container->work.work, do_work);
8684 +
8685 +#ifdef DEBUG
8686 + DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
8687 +#endif
8688 + queue_work(wq->wq, &container->work.work);
8689 +}
8690 +
8691 +void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,
8692 + void *data, uint32_t time, char *format, ...)
8693 +{
8694 + dwc_irqflags_t flags;
8695 + work_container_t *container;
8696 + static char name[128];
8697 + va_list args;
8698 +
8699 + va_start(args, format);
8700 + DWC_VSNPRINTF(name, 128, format, args);
8701 + va_end(args);
8702 +
8703 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
8704 + wq->pending++;
8705 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
8706 + DWC_WAITQ_TRIGGER(wq->waitq);
8707 +
8708 + container = DWC_ALLOC_ATOMIC(sizeof(*container));
8709 + if (!container) {
8710 + DWC_ERROR("Cannot allocate memory for container\n");
8711 + return;
8712 + }
8713 +
8714 + container->name = DWC_STRDUP(name);
8715 + if (!container->name) {
8716 + DWC_ERROR("Cannot allocate memory for container->name\n");
8717 + DWC_FREE(container);
8718 + return;
8719 + }
8720 +
8721 + container->cb = cb;
8722 + container->data = data;
8723 + container->wq = wq;
8724 + DWC_DEBUGC("Queueing work: %s, container=%p", container->name, container);
8725 + INIT_DELAYED_WORK(&container->work, do_work);
8726 +
8727 +#ifdef DEBUG
8728 + DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
8729 +#endif
8730 + queue_delayed_work(wq->wq, &container->work, msecs_to_jiffies(time));
8731 +}
8732 +
8733 +int DWC_WORKQ_PENDING(dwc_workq_t *wq)
8734 +{
8735 + return wq->pending;
8736 +}
8737 +
8738 +
8739 +#ifdef DWC_LIBMODULE
8740 +
8741 +#ifdef DWC_CCLIB
8742 +/* CC */
8743 +EXPORT_SYMBOL(dwc_cc_if_alloc);
8744 +EXPORT_SYMBOL(dwc_cc_if_free);
8745 +EXPORT_SYMBOL(dwc_cc_clear);
8746 +EXPORT_SYMBOL(dwc_cc_add);
8747 +EXPORT_SYMBOL(dwc_cc_remove);
8748 +EXPORT_SYMBOL(dwc_cc_change);
8749 +EXPORT_SYMBOL(dwc_cc_data_for_save);
8750 +EXPORT_SYMBOL(dwc_cc_restore_from_data);
8751 +EXPORT_SYMBOL(dwc_cc_match_chid);
8752 +EXPORT_SYMBOL(dwc_cc_match_cdid);
8753 +EXPORT_SYMBOL(dwc_cc_ck);
8754 +EXPORT_SYMBOL(dwc_cc_chid);
8755 +EXPORT_SYMBOL(dwc_cc_cdid);
8756 +EXPORT_SYMBOL(dwc_cc_name);
8757 +#endif /* DWC_CCLIB */
8758 +
8759 +#ifdef DWC_CRYPTOLIB
8760 +# ifndef CONFIG_MACH_IPMATE
8761 +/* Modpow */
8762 +EXPORT_SYMBOL(dwc_modpow);
8763 +
8764 +/* DH */
8765 +EXPORT_SYMBOL(dwc_dh_modpow);
8766 +EXPORT_SYMBOL(dwc_dh_derive_keys);
8767 +EXPORT_SYMBOL(dwc_dh_pk);
8768 +# endif /* CONFIG_MACH_IPMATE */
8769 +
8770 +/* Crypto */
8771 +EXPORT_SYMBOL(dwc_wusb_aes_encrypt);
8772 +EXPORT_SYMBOL(dwc_wusb_cmf);
8773 +EXPORT_SYMBOL(dwc_wusb_prf);
8774 +EXPORT_SYMBOL(dwc_wusb_fill_ccm_nonce);
8775 +EXPORT_SYMBOL(dwc_wusb_gen_nonce);
8776 +EXPORT_SYMBOL(dwc_wusb_gen_key);
8777 +EXPORT_SYMBOL(dwc_wusb_gen_mic);
8778 +#endif /* DWC_CRYPTOLIB */
8779 +
8780 +/* Notification */
8781 +#ifdef DWC_NOTIFYLIB
8782 +EXPORT_SYMBOL(dwc_alloc_notification_manager);
8783 +EXPORT_SYMBOL(dwc_free_notification_manager);
8784 +EXPORT_SYMBOL(dwc_register_notifier);
8785 +EXPORT_SYMBOL(dwc_unregister_notifier);
8786 +EXPORT_SYMBOL(dwc_add_observer);
8787 +EXPORT_SYMBOL(dwc_remove_observer);
8788 +EXPORT_SYMBOL(dwc_notify);
8789 +#endif
8790 +
8791 +/* Memory Debugging Routines */
8792 +#ifdef DWC_DEBUG_MEMORY
8793 +EXPORT_SYMBOL(dwc_alloc_debug);
8794 +EXPORT_SYMBOL(dwc_alloc_atomic_debug);
8795 +EXPORT_SYMBOL(dwc_free_debug);
8796 +EXPORT_SYMBOL(dwc_dma_alloc_debug);
8797 +EXPORT_SYMBOL(dwc_dma_free_debug);
8798 +#endif
8799 +
8800 +EXPORT_SYMBOL(DWC_MEMSET);
8801 +EXPORT_SYMBOL(DWC_MEMCPY);
8802 +EXPORT_SYMBOL(DWC_MEMMOVE);
8803 +EXPORT_SYMBOL(DWC_MEMCMP);
8804 +EXPORT_SYMBOL(DWC_STRNCMP);
8805 +EXPORT_SYMBOL(DWC_STRCMP);
8806 +EXPORT_SYMBOL(DWC_STRLEN);
8807 +EXPORT_SYMBOL(DWC_STRCPY);
8808 +EXPORT_SYMBOL(DWC_STRDUP);
8809 +EXPORT_SYMBOL(DWC_ATOI);
8810 +EXPORT_SYMBOL(DWC_ATOUI);
8811 +
8812 +#ifdef DWC_UTFLIB
8813 +EXPORT_SYMBOL(DWC_UTF8_TO_UTF16LE);
8814 +#endif /* DWC_UTFLIB */
8815 +
8816 +EXPORT_SYMBOL(DWC_IN_IRQ);
8817 +EXPORT_SYMBOL(DWC_IN_BH);
8818 +EXPORT_SYMBOL(DWC_VPRINTF);
8819 +EXPORT_SYMBOL(DWC_VSNPRINTF);
8820 +EXPORT_SYMBOL(DWC_PRINTF);
8821 +EXPORT_SYMBOL(DWC_SPRINTF);
8822 +EXPORT_SYMBOL(DWC_SNPRINTF);
8823 +EXPORT_SYMBOL(__DWC_WARN);
8824 +EXPORT_SYMBOL(__DWC_ERROR);
8825 +EXPORT_SYMBOL(DWC_EXCEPTION);
8826 +
8827 +#ifdef DEBUG
8828 +EXPORT_SYMBOL(__DWC_DEBUG);
8829 +#endif
8830 +
8831 +EXPORT_SYMBOL(__DWC_DMA_ALLOC);
8832 +EXPORT_SYMBOL(__DWC_DMA_ALLOC_ATOMIC);
8833 +EXPORT_SYMBOL(__DWC_DMA_FREE);
8834 +EXPORT_SYMBOL(__DWC_ALLOC);
8835 +EXPORT_SYMBOL(__DWC_ALLOC_ATOMIC);
8836 +EXPORT_SYMBOL(__DWC_FREE);
8837 +
8838 +#ifdef DWC_CRYPTOLIB
8839 +EXPORT_SYMBOL(DWC_RANDOM_BYTES);
8840 +EXPORT_SYMBOL(DWC_AES_CBC);
8841 +EXPORT_SYMBOL(DWC_SHA256);
8842 +EXPORT_SYMBOL(DWC_HMAC_SHA256);
8843 +#endif
8844 +
8845 +EXPORT_SYMBOL(DWC_CPU_TO_LE32);
8846 +EXPORT_SYMBOL(DWC_CPU_TO_BE32);
8847 +EXPORT_SYMBOL(DWC_LE32_TO_CPU);
8848 +EXPORT_SYMBOL(DWC_BE32_TO_CPU);
8849 +EXPORT_SYMBOL(DWC_CPU_TO_LE16);
8850 +EXPORT_SYMBOL(DWC_CPU_TO_BE16);
8851 +EXPORT_SYMBOL(DWC_LE16_TO_CPU);
8852 +EXPORT_SYMBOL(DWC_BE16_TO_CPU);
8853 +EXPORT_SYMBOL(DWC_READ_REG32);
8854 +EXPORT_SYMBOL(DWC_WRITE_REG32);
8855 +EXPORT_SYMBOL(DWC_MODIFY_REG32);
8856 +
8857 +#if 0
8858 +EXPORT_SYMBOL(DWC_READ_REG64);
8859 +EXPORT_SYMBOL(DWC_WRITE_REG64);
8860 +EXPORT_SYMBOL(DWC_MODIFY_REG64);
8861 +#endif
8862 +
8863 +EXPORT_SYMBOL(DWC_SPINLOCK_ALLOC);
8864 +EXPORT_SYMBOL(DWC_SPINLOCK_FREE);
8865 +EXPORT_SYMBOL(DWC_SPINLOCK);
8866 +EXPORT_SYMBOL(DWC_SPINUNLOCK);
8867 +EXPORT_SYMBOL(DWC_SPINLOCK_IRQSAVE);
8868 +EXPORT_SYMBOL(DWC_SPINUNLOCK_IRQRESTORE);
8869 +EXPORT_SYMBOL(DWC_MUTEX_ALLOC);
8870 +
8871 +#if (!defined(DWC_LINUX) || !defined(CONFIG_DEBUG_MUTEXES))
8872 +EXPORT_SYMBOL(DWC_MUTEX_FREE);
8873 +#endif
8874 +
8875 +EXPORT_SYMBOL(DWC_MUTEX_LOCK);
8876 +EXPORT_SYMBOL(DWC_MUTEX_TRYLOCK);
8877 +EXPORT_SYMBOL(DWC_MUTEX_UNLOCK);
8878 +EXPORT_SYMBOL(DWC_UDELAY);
8879 +EXPORT_SYMBOL(DWC_MDELAY);
8880 +EXPORT_SYMBOL(DWC_MSLEEP);
8881 +EXPORT_SYMBOL(DWC_TIME);
8882 +EXPORT_SYMBOL(DWC_TIMER_ALLOC);
8883 +EXPORT_SYMBOL(DWC_TIMER_FREE);
8884 +EXPORT_SYMBOL(DWC_TIMER_SCHEDULE);
8885 +EXPORT_SYMBOL(DWC_TIMER_CANCEL);
8886 +EXPORT_SYMBOL(DWC_WAITQ_ALLOC);
8887 +EXPORT_SYMBOL(DWC_WAITQ_FREE);
8888 +EXPORT_SYMBOL(DWC_WAITQ_WAIT);
8889 +EXPORT_SYMBOL(DWC_WAITQ_WAIT_TIMEOUT);
8890 +EXPORT_SYMBOL(DWC_WAITQ_TRIGGER);
8891 +EXPORT_SYMBOL(DWC_WAITQ_ABORT);
8892 +EXPORT_SYMBOL(DWC_THREAD_RUN);
8893 +EXPORT_SYMBOL(DWC_THREAD_STOP);
8894 +EXPORT_SYMBOL(DWC_THREAD_SHOULD_STOP);
8895 +EXPORT_SYMBOL(DWC_TASK_ALLOC);
8896 +EXPORT_SYMBOL(DWC_TASK_FREE);
8897 +EXPORT_SYMBOL(DWC_TASK_SCHEDULE);
8898 +EXPORT_SYMBOL(DWC_WORKQ_WAIT_WORK_DONE);
8899 +EXPORT_SYMBOL(DWC_WORKQ_ALLOC);
8900 +EXPORT_SYMBOL(DWC_WORKQ_FREE);
8901 +EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE);
8902 +EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE_DELAYED);
8903 +EXPORT_SYMBOL(DWC_WORKQ_PENDING);
8904 +
8905 +static int dwc_common_port_init_module(void)
8906 +{
8907 + int result = 0;
8908 +
8909 + printk(KERN_DEBUG "Module dwc_common_port init\n" );
8910 +
8911 +#ifdef DWC_DEBUG_MEMORY
8912 + result = dwc_memory_debug_start(NULL);
8913 + if (result) {
8914 + printk(KERN_ERR
8915 + "dwc_memory_debug_start() failed with error %d\n",
8916 + result);
8917 + return result;
8918 + }
8919 +#endif
8920 +
8921 +#ifdef DWC_NOTIFYLIB
8922 + result = dwc_alloc_notification_manager(NULL, NULL);
8923 + if (result) {
8924 + printk(KERN_ERR
8925 + "dwc_alloc_notification_manager() failed with error %d\n",
8926 + result);
8927 + return result;
8928 + }
8929 +#endif
8930 + return result;
8931 +}
8932 +
8933 +static void dwc_common_port_exit_module(void)
8934 +{
8935 + printk(KERN_DEBUG "Module dwc_common_port exit\n" );
8936 +
8937 +#ifdef DWC_NOTIFYLIB
8938 + dwc_free_notification_manager();
8939 +#endif
8940 +
8941 +#ifdef DWC_DEBUG_MEMORY
8942 + dwc_memory_debug_stop();
8943 +#endif
8944 +}
8945 +
8946 +module_init(dwc_common_port_init_module);
8947 +module_exit(dwc_common_port_exit_module);
8948 +
8949 +MODULE_DESCRIPTION("DWC Common Library - Portable version");
8950 +MODULE_AUTHOR("Synopsys Inc.");
8951 +MODULE_LICENSE ("GPL");
8952 +
8953 +#endif /* DWC_LIBMODULE */
8954 --- /dev/null
8955 +++ b/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c
8956 @@ -0,0 +1,1275 @@
8957 +#include "dwc_os.h"
8958 +#include "dwc_list.h"
8959 +
8960 +#ifdef DWC_CCLIB
8961 +# include "dwc_cc.h"
8962 +#endif
8963 +
8964 +#ifdef DWC_CRYPTOLIB
8965 +# include "dwc_modpow.h"
8966 +# include "dwc_dh.h"
8967 +# include "dwc_crypto.h"
8968 +#endif
8969 +
8970 +#ifdef DWC_NOTIFYLIB
8971 +# include "dwc_notifier.h"
8972 +#endif
8973 +
8974 +/* OS-Level Implementations */
8975 +
8976 +/* This is the NetBSD 4.0.1 kernel implementation of the DWC platform library. */
8977 +
8978 +
8979 +/* MISC */
8980 +
8981 +void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)
8982 +{
8983 + return memset(dest, byte, size);
8984 +}
8985 +
8986 +void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)
8987 +{
8988 + return memcpy(dest, src, size);
8989 +}
8990 +
8991 +void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)
8992 +{
8993 + bcopy(src, dest, size);
8994 + return dest;
8995 +}
8996 +
8997 +int DWC_MEMCMP(void *m1, void *m2, uint32_t size)
8998 +{
8999 + return memcmp(m1, m2, size);
9000 +}
9001 +
9002 +int DWC_STRNCMP(void *s1, void *s2, uint32_t size)
9003 +{
9004 + return strncmp(s1, s2, size);
9005 +}
9006 +
9007 +int DWC_STRCMP(void *s1, void *s2)
9008 +{
9009 + return strcmp(s1, s2);
9010 +}
9011 +
9012 +int DWC_STRLEN(char const *str)
9013 +{
9014 + return strlen(str);
9015 +}
9016 +
9017 +char *DWC_STRCPY(char *to, char const *from)
9018 +{
9019 + return strcpy(to, from);
9020 +}
9021 +
9022 +char *DWC_STRDUP(char const *str)
9023 +{
9024 + int len = DWC_STRLEN(str) + 1;
9025 + char *new = DWC_ALLOC_ATOMIC(len);
9026 +
9027 + if (!new) {
9028 + return NULL;
9029 + }
9030 +
9031 + DWC_MEMCPY(new, str, len);
9032 + return new;
9033 +}
9034 +
9035 +int DWC_ATOI(char *str, int32_t *value)
9036 +{
9037 + char *end = NULL;
9038 +
9039 + /* NetBSD doesn't have 'strtol' in the kernel, but 'strtoul'
9040 + * should be equivalent on 2's complement machines
9041 + */
9042 + *value = strtoul(str, &end, 0);
9043 + if (*end == '\0') {
9044 + return 0;
9045 + }
9046 +
9047 + return -1;
9048 +}
9049 +
9050 +int DWC_ATOUI(char *str, uint32_t *value)
9051 +{
9052 + char *end = NULL;
9053 +
9054 + *value = strtoul(str, &end, 0);
9055 + if (*end == '\0') {
9056 + return 0;
9057 + }
9058 +
9059 + return -1;
9060 +}
9061 +
9062 +
9063 +#ifdef DWC_UTFLIB
9064 +/* From usbstring.c */
9065 +
9066 +int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)
9067 +{
9068 + int count = 0;
9069 + u8 c;
9070 + u16 uchar;
9071 +
9072 + /* this insists on correct encodings, though not minimal ones.
9073 + * BUT it currently rejects legit 4-byte UTF-8 code points,
9074 + * which need surrogate pairs. (Unicode 3.1 can use them.)
9075 + */
9076 + while (len != 0 && (c = (u8) *s++) != 0) {
9077 + if (unlikely(c & 0x80)) {
9078 + // 2-byte sequence:
9079 + // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
9080 + if ((c & 0xe0) == 0xc0) {
9081 + uchar = (c & 0x1f) << 6;
9082 +
9083 + c = (u8) *s++;
9084 + if ((c & 0xc0) != 0xc0)
9085 + goto fail;
9086 + c &= 0x3f;
9087 + uchar |= c;
9088 +
9089 + // 3-byte sequence (most CJKV characters):
9090 + // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
9091 + } else if ((c & 0xf0) == 0xe0) {
9092 + uchar = (c & 0x0f) << 12;
9093 +
9094 + c = (u8) *s++;
9095 + if ((c & 0xc0) != 0xc0)
9096 + goto fail;
9097 + c &= 0x3f;
9098 + uchar |= c << 6;
9099 +
9100 + c = (u8) *s++;
9101 + if ((c & 0xc0) != 0xc0)
9102 + goto fail;
9103 + c &= 0x3f;
9104 + uchar |= c;
9105 +
9106 + /* no bogus surrogates */
9107 + if (0xd800 <= uchar && uchar <= 0xdfff)
9108 + goto fail;
9109 +
9110 + // 4-byte sequence (surrogate pairs, currently rare):
9111 + // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
9112 + // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
9113 + // (uuuuu = wwww + 1)
9114 + // FIXME accept the surrogate code points (only)
9115 + } else
9116 + goto fail;
9117 + } else
9118 + uchar = c;
9119 + put_unaligned (cpu_to_le16 (uchar), cp++);
9120 + count++;
9121 + len--;
9122 + }
9123 + return count;
9124 +fail:
9125 + return -1;
9126 +}
9127 +
9128 +#endif /* DWC_UTFLIB */
9129 +
9130 +
9131 +/* dwc_debug.h */
9132 +
9133 +dwc_bool_t DWC_IN_IRQ(void)
9134 +{
9135 +// return in_irq();
9136 + return 0;
9137 +}
9138 +
9139 +dwc_bool_t DWC_IN_BH(void)
9140 +{
9141 +// return in_softirq();
9142 + return 0;
9143 +}
9144 +
9145 +void DWC_VPRINTF(char *format, va_list args)
9146 +{
9147 + vprintf(format, args);
9148 +}
9149 +
9150 +int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)
9151 +{
9152 + return vsnprintf(str, size, format, args);
9153 +}
9154 +
9155 +void DWC_PRINTF(char *format, ...)
9156 +{
9157 + va_list args;
9158 +
9159 + va_start(args, format);
9160 + DWC_VPRINTF(format, args);
9161 + va_end(args);
9162 +}
9163 +
9164 +int DWC_SPRINTF(char *buffer, char *format, ...)
9165 +{
9166 + int retval;
9167 + va_list args;
9168 +
9169 + va_start(args, format);
9170 + retval = vsprintf(buffer, format, args);
9171 + va_end(args);
9172 + return retval;
9173 +}
9174 +
9175 +int DWC_SNPRINTF(char *buffer, int size, char *format, ...)
9176 +{
9177 + int retval;
9178 + va_list args;
9179 +
9180 + va_start(args, format);
9181 + retval = vsnprintf(buffer, size, format, args);
9182 + va_end(args);
9183 + return retval;
9184 +}
9185 +
9186 +void __DWC_WARN(char *format, ...)
9187 +{
9188 + va_list args;
9189 +
9190 + va_start(args, format);
9191 + DWC_VPRINTF(format, args);
9192 + va_end(args);
9193 +}
9194 +
9195 +void __DWC_ERROR(char *format, ...)
9196 +{
9197 + va_list args;
9198 +
9199 + va_start(args, format);
9200 + DWC_VPRINTF(format, args);
9201 + va_end(args);
9202 +}
9203 +
9204 +void DWC_EXCEPTION(char *format, ...)
9205 +{
9206 + va_list args;
9207 +
9208 + va_start(args, format);
9209 + DWC_VPRINTF(format, args);
9210 + va_end(args);
9211 +// BUG_ON(1); ???
9212 +}
9213 +
9214 +#ifdef DEBUG
9215 +void __DWC_DEBUG(char *format, ...)
9216 +{
9217 + va_list args;
9218 +
9219 + va_start(args, format);
9220 + DWC_VPRINTF(format, args);
9221 + va_end(args);
9222 +}
9223 +#endif
9224 +
9225 +
9226 +/* dwc_mem.h */
9227 +
9228 +#if 0
9229 +dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,
9230 + uint32_t align,
9231 + uint32_t alloc)
9232 +{
9233 + struct dma_pool *pool = dma_pool_create("Pool", NULL,
9234 + size, align, alloc);
9235 + return (dwc_pool_t *)pool;
9236 +}
9237 +
9238 +void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)
9239 +{
9240 + dma_pool_destroy((struct dma_pool *)pool);
9241 +}
9242 +
9243 +void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
9244 +{
9245 +// return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);
9246 + return dma_pool_alloc((struct dma_pool *)pool, M_WAITOK, dma_addr);
9247 +}
9248 +
9249 +void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
9250 +{
9251 + void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);
9252 + memset(..);
9253 +}
9254 +
9255 +void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)
9256 +{
9257 + dma_pool_free(pool, vaddr, daddr);
9258 +}
9259 +#endif
9260 +
9261 +void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
9262 +{
9263 + dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
9264 + int error;
9265 +
9266 + error = bus_dmamem_alloc(dma->dma_tag, size, 1, size, dma->segs,
9267 + sizeof(dma->segs) / sizeof(dma->segs[0]),
9268 + &dma->nsegs, BUS_DMA_NOWAIT);
9269 + if (error) {
9270 + printf("%s: bus_dmamem_alloc(%ju) failed: %d\n", __func__,
9271 + (uintmax_t)size, error);
9272 + goto fail_0;
9273 + }
9274 +
9275 + error = bus_dmamem_map(dma->dma_tag, dma->segs, dma->nsegs, size,
9276 + (caddr_t *)&dma->dma_vaddr,
9277 + BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
9278 + if (error) {
9279 + printf("%s: bus_dmamem_map failed: %d\n", __func__, error);
9280 + goto fail_1;
9281 + }
9282 +
9283 + error = bus_dmamap_create(dma->dma_tag, size, 1, size, 0,
9284 + BUS_DMA_NOWAIT, &dma->dma_map);
9285 + if (error) {
9286 + printf("%s: bus_dmamap_create failed: %d\n", __func__, error);
9287 + goto fail_2;
9288 + }
9289 +
9290 + error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,
9291 + size, NULL, BUS_DMA_NOWAIT);
9292 + if (error) {
9293 + printf("%s: bus_dmamap_load failed: %d\n", __func__, error);
9294 + goto fail_3;
9295 + }
9296 +
9297 + dma->dma_paddr = (bus_addr_t)dma->segs[0].ds_addr;
9298 + *dma_addr = dma->dma_paddr;
9299 + return dma->dma_vaddr;
9300 +
9301 +fail_3:
9302 + bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
9303 +fail_2:
9304 + bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size);
9305 +fail_1:
9306 + bus_dmamem_free(dma->dma_tag, dma->segs, dma->nsegs);
9307 +fail_0:
9308 + dma->dma_map = NULL;
9309 + dma->dma_vaddr = NULL;
9310 + dma->nsegs = 0;
9311 +
9312 + return NULL;
9313 +}
9314 +
9315 +void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
9316 +{
9317 + dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
9318 +
9319 + if (dma->dma_map != NULL) {
9320 + bus_dmamap_sync(dma->dma_tag, dma->dma_map, 0, size,
9321 + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
9322 + bus_dmamap_unload(dma->dma_tag, dma->dma_map);
9323 + bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
9324 + bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size);
9325 + bus_dmamem_free(dma->dma_tag, dma->segs, dma->nsegs);
9326 + dma->dma_paddr = 0;
9327 + dma->dma_map = NULL;
9328 + dma->dma_vaddr = NULL;
9329 + dma->nsegs = 0;
9330 + }
9331 +}
9332 +
9333 +void *__DWC_ALLOC(void *mem_ctx, uint32_t size)
9334 +{
9335 + return malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
9336 +}
9337 +
9338 +void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)
9339 +{
9340 + return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
9341 +}
9342 +
9343 +void __DWC_FREE(void *mem_ctx, void *addr)
9344 +{
9345 + free(addr, M_DEVBUF);
9346 +}
9347 +
9348 +
9349 +#ifdef DWC_CRYPTOLIB
9350 +/* dwc_crypto.h */
9351 +
9352 +void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)
9353 +{
9354 + get_random_bytes(buffer, length);
9355 +}
9356 +
9357 +int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
9358 +{
9359 + struct crypto_blkcipher *tfm;
9360 + struct blkcipher_desc desc;
9361 + struct scatterlist sgd;
9362 + struct scatterlist sgs;
9363 +
9364 + tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
9365 + if (tfm == NULL) {
9366 + printk("failed to load transform for aes CBC\n");
9367 + return -1;
9368 + }
9369 +
9370 + crypto_blkcipher_setkey(tfm, key, keylen);
9371 + crypto_blkcipher_set_iv(tfm, iv, 16);
9372 +
9373 + sg_init_one(&sgd, out, messagelen);
9374 + sg_init_one(&sgs, message, messagelen);
9375 +
9376 + desc.tfm = tfm;
9377 + desc.flags = 0;
9378 +
9379 + if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {
9380 + crypto_free_blkcipher(tfm);
9381 + DWC_ERROR("AES CBC encryption failed");
9382 + return -1;
9383 + }
9384 +
9385 + crypto_free_blkcipher(tfm);
9386 + return 0;
9387 +}
9388 +
9389 +int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)
9390 +{
9391 + struct crypto_hash *tfm;
9392 + struct hash_desc desc;
9393 + struct scatterlist sg;
9394 +
9395 + tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC);
9396 + if (IS_ERR(tfm)) {
9397 + DWC_ERROR("Failed to load transform for sha256: %ld", PTR_ERR(tfm));
9398 + return 0;
9399 + }
9400 + desc.tfm = tfm;
9401 + desc.flags = 0;
9402 +
9403 + sg_init_one(&sg, message, len);
9404 + crypto_hash_digest(&desc, &sg, len, out);
9405 + crypto_free_hash(tfm);
9406 +
9407 + return 1;
9408 +}
9409 +
9410 +int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,
9411 + uint8_t *key, uint32_t keylen, uint8_t *out)
9412 +{
9413 + struct crypto_hash *tfm;
9414 + struct hash_desc desc;
9415 + struct scatterlist sg;
9416 +
9417 + tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC);
9418 + if (IS_ERR(tfm)) {
9419 + DWC_ERROR("Failed to load transform for hmac(sha256): %ld", PTR_ERR(tfm));
9420 + return 0;
9421 + }
9422 + desc.tfm = tfm;
9423 + desc.flags = 0;
9424 +
9425 + sg_init_one(&sg, message, messagelen);
9426 + crypto_hash_setkey(tfm, key, keylen);
9427 + crypto_hash_digest(&desc, &sg, messagelen, out);
9428 + crypto_free_hash(tfm);
9429 +
9430 + return 1;
9431 +}
9432 +
9433 +#endif /* DWC_CRYPTOLIB */
9434 +
9435 +
9436 +/* Byte Ordering Conversions */
9437 +
9438 +uint32_t DWC_CPU_TO_LE32(uint32_t *p)
9439 +{
9440 +#ifdef __LITTLE_ENDIAN
9441 + return *p;
9442 +#else
9443 + uint8_t *u_p = (uint8_t *)p;
9444 +
9445 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
9446 +#endif
9447 +}
9448 +
9449 +uint32_t DWC_CPU_TO_BE32(uint32_t *p)
9450 +{
9451 +#ifdef __BIG_ENDIAN
9452 + return *p;
9453 +#else
9454 + uint8_t *u_p = (uint8_t *)p;
9455 +
9456 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
9457 +#endif
9458 +}
9459 +
9460 +uint32_t DWC_LE32_TO_CPU(uint32_t *p)
9461 +{
9462 +#ifdef __LITTLE_ENDIAN
9463 + return *p;
9464 +#else
9465 + uint8_t *u_p = (uint8_t *)p;
9466 +
9467 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
9468 +#endif
9469 +}
9470 +
9471 +uint32_t DWC_BE32_TO_CPU(uint32_t *p)
9472 +{
9473 +#ifdef __BIG_ENDIAN
9474 + return *p;
9475 +#else
9476 + uint8_t *u_p = (uint8_t *)p;
9477 +
9478 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
9479 +#endif
9480 +}
9481 +
9482 +uint16_t DWC_CPU_TO_LE16(uint16_t *p)
9483 +{
9484 +#ifdef __LITTLE_ENDIAN
9485 + return *p;
9486 +#else
9487 + uint8_t *u_p = (uint8_t *)p;
9488 + return (u_p[1] | (u_p[0] << 8));
9489 +#endif
9490 +}
9491 +
9492 +uint16_t DWC_CPU_TO_BE16(uint16_t *p)
9493 +{
9494 +#ifdef __BIG_ENDIAN
9495 + return *p;
9496 +#else
9497 + uint8_t *u_p = (uint8_t *)p;
9498 + return (u_p[1] | (u_p[0] << 8));
9499 +#endif
9500 +}
9501 +
9502 +uint16_t DWC_LE16_TO_CPU(uint16_t *p)
9503 +{
9504 +#ifdef __LITTLE_ENDIAN
9505 + return *p;
9506 +#else
9507 + uint8_t *u_p = (uint8_t *)p;
9508 + return (u_p[1] | (u_p[0] << 8));
9509 +#endif
9510 +}
9511 +
9512 +uint16_t DWC_BE16_TO_CPU(uint16_t *p)
9513 +{
9514 +#ifdef __BIG_ENDIAN
9515 + return *p;
9516 +#else
9517 + uint8_t *u_p = (uint8_t *)p;
9518 + return (u_p[1] | (u_p[0] << 8));
9519 +#endif
9520 +}
9521 +
9522 +
9523 +/* Registers */
9524 +
9525 +uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg)
9526 +{
9527 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
9528 + bus_size_t ior = (bus_size_t)reg;
9529 +
9530 + return bus_space_read_4(io->iot, io->ioh, ior);
9531 +}
9532 +
9533 +#if 0
9534 +uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg)
9535 +{
9536 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
9537 + bus_size_t ior = (bus_size_t)reg;
9538 +
9539 + return bus_space_read_8(io->iot, io->ioh, ior);
9540 +}
9541 +#endif
9542 +
9543 +void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value)
9544 +{
9545 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
9546 + bus_size_t ior = (bus_size_t)reg;
9547 +
9548 + bus_space_write_4(io->iot, io->ioh, ior, value);
9549 +}
9550 +
9551 +#if 0
9552 +void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value)
9553 +{
9554 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
9555 + bus_size_t ior = (bus_size_t)reg;
9556 +
9557 + bus_space_write_8(io->iot, io->ioh, ior, value);
9558 +}
9559 +#endif
9560 +
9561 +void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask,
9562 + uint32_t set_mask)
9563 +{
9564 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
9565 + bus_size_t ior = (bus_size_t)reg;
9566 +
9567 + bus_space_write_4(io->iot, io->ioh, ior,
9568 + (bus_space_read_4(io->iot, io->ioh, ior) &
9569 + ~clear_mask) | set_mask);
9570 +}
9571 +
9572 +#if 0
9573 +void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask,
9574 + uint64_t set_mask)
9575 +{
9576 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
9577 + bus_size_t ior = (bus_size_t)reg;
9578 +
9579 + bus_space_write_8(io->iot, io->ioh, ior,
9580 + (bus_space_read_8(io->iot, io->ioh, ior) &
9581 + ~clear_mask) | set_mask);
9582 +}
9583 +#endif
9584 +
9585 +
9586 +/* Locking */
9587 +
9588 +dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)
9589 +{
9590 + struct simplelock *sl = DWC_ALLOC(sizeof(*sl));
9591 +
9592 + if (!sl) {
9593 + DWC_ERROR("Cannot allocate memory for spinlock");
9594 + return NULL;
9595 + }
9596 +
9597 + simple_lock_init(sl);
9598 + return (dwc_spinlock_t *)sl;
9599 +}
9600 +
9601 +void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)
9602 +{
9603 + struct simplelock *sl = (struct simplelock *)lock;
9604 +
9605 + DWC_FREE(sl);
9606 +}
9607 +
9608 +void DWC_SPINLOCK(dwc_spinlock_t *lock)
9609 +{
9610 + simple_lock((struct simplelock *)lock);
9611 +}
9612 +
9613 +void DWC_SPINUNLOCK(dwc_spinlock_t *lock)
9614 +{
9615 + simple_unlock((struct simplelock *)lock);
9616 +}
9617 +
9618 +void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)
9619 +{
9620 + simple_lock((struct simplelock *)lock);
9621 + *flags = splbio();
9622 +}
9623 +
9624 +void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)
9625 +{
9626 + splx(flags);
9627 + simple_unlock((struct simplelock *)lock);
9628 +}
9629 +
9630 +dwc_mutex_t *DWC_MUTEX_ALLOC(void)
9631 +{
9632 + dwc_mutex_t *mutex = DWC_ALLOC(sizeof(struct lock));
9633 +
9634 + if (!mutex) {
9635 + DWC_ERROR("Cannot allocate memory for mutex");
9636 + return NULL;
9637 + }
9638 +
9639 + lockinit((struct lock *)mutex, 0, "dw3mtx", 0, 0);
9640 + return mutex;
9641 +}
9642 +
9643 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
9644 +#else
9645 +void DWC_MUTEX_FREE(dwc_mutex_t *mutex)
9646 +{
9647 + DWC_FREE(mutex);
9648 +}
9649 +#endif
9650 +
9651 +void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)
9652 +{
9653 + lockmgr((struct lock *)mutex, LK_EXCLUSIVE, NULL);
9654 +}
9655 +
9656 +int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)
9657 +{
9658 + int status;
9659 +
9660 + status = lockmgr((struct lock *)mutex, LK_EXCLUSIVE | LK_NOWAIT, NULL);
9661 + return status == 0;
9662 +}
9663 +
9664 +void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)
9665 +{
9666 + lockmgr((struct lock *)mutex, LK_RELEASE, NULL);
9667 +}
9668 +
9669 +
9670 +/* Timing */
9671 +
9672 +void DWC_UDELAY(uint32_t usecs)
9673 +{
9674 + DELAY(usecs);
9675 +}
9676 +
9677 +void DWC_MDELAY(uint32_t msecs)
9678 +{
9679 + do {
9680 + DELAY(1000);
9681 + } while (--msecs);
9682 +}
9683 +
9684 +void DWC_MSLEEP(uint32_t msecs)
9685 +{
9686 + struct timeval tv;
9687 +
9688 + tv.tv_sec = msecs / 1000;
9689 + tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
9690 + tsleep(&tv, 0, "dw3slp", tvtohz(&tv));
9691 +}
9692 +
9693 +uint32_t DWC_TIME(void)
9694 +{
9695 + struct timeval tv;
9696 +
9697 + microuptime(&tv); // or getmicrouptime? (less precise, but faster)
9698 + return tv.tv_sec * 1000 + tv.tv_usec / 1000;
9699 +}
9700 +
9701 +
9702 +/* Timers */
9703 +
9704 +struct dwc_timer {
9705 + struct callout t;
9706 + char *name;
9707 + dwc_spinlock_t *lock;
9708 + dwc_timer_callback_t cb;
9709 + void *data;
9710 +};
9711 +
9712 +dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)
9713 +{
9714 + dwc_timer_t *t = DWC_ALLOC(sizeof(*t));
9715 +
9716 + if (!t) {
9717 + DWC_ERROR("Cannot allocate memory for timer");
9718 + return NULL;
9719 + }
9720 +
9721 + callout_init(&t->t);
9722 +
9723 + t->name = DWC_STRDUP(name);
9724 + if (!t->name) {
9725 + DWC_ERROR("Cannot allocate memory for timer->name");
9726 + goto no_name;
9727 + }
9728 +
9729 + t->lock = DWC_SPINLOCK_ALLOC();
9730 + if (!t->lock) {
9731 + DWC_ERROR("Cannot allocate memory for timer->lock");
9732 + goto no_lock;
9733 + }
9734 +
9735 + t->cb = cb;
9736 + t->data = data;
9737 +
9738 + return t;
9739 +
9740 + no_lock:
9741 + DWC_FREE(t->name);
9742 + no_name:
9743 + DWC_FREE(t);
9744 +
9745 + return NULL;
9746 +}
9747 +
9748 +void DWC_TIMER_FREE(dwc_timer_t *timer)
9749 +{
9750 + callout_stop(&timer->t);
9751 + DWC_SPINLOCK_FREE(timer->lock);
9752 + DWC_FREE(timer->name);
9753 + DWC_FREE(timer);
9754 +}
9755 +
9756 +void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)
9757 +{
9758 + struct timeval tv;
9759 +
9760 + tv.tv_sec = time / 1000;
9761 + tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
9762 + callout_reset(&timer->t, tvtohz(&tv), timer->cb, timer->data);
9763 +}
9764 +
9765 +void DWC_TIMER_CANCEL(dwc_timer_t *timer)
9766 +{
9767 + callout_stop(&timer->t);
9768 +}
9769 +
9770 +
9771 +/* Wait Queues */
9772 +
9773 +struct dwc_waitq {
9774 + struct simplelock lock;
9775 + int abort;
9776 +};
9777 +
9778 +dwc_waitq_t *DWC_WAITQ_ALLOC(void)
9779 +{
9780 + dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));
9781 +
9782 + if (!wq) {
9783 + DWC_ERROR("Cannot allocate memory for waitqueue");
9784 + return NULL;
9785 + }
9786 +
9787 + simple_lock_init(&wq->lock);
9788 + wq->abort = 0;
9789 +
9790 + return wq;
9791 +}
9792 +
9793 +void DWC_WAITQ_FREE(dwc_waitq_t *wq)
9794 +{
9795 + DWC_FREE(wq);
9796 +}
9797 +
9798 +int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)
9799 +{
9800 + int ipl;
9801 + int result = 0;
9802 +
9803 + simple_lock(&wq->lock);
9804 + ipl = splbio();
9805 +
9806 + /* Skip the sleep if already aborted or triggered */
9807 + if (!wq->abort && !cond(data)) {
9808 + splx(ipl);
9809 + result = ltsleep(wq, PCATCH, "dw3wat", 0, &wq->lock); // infinite timeout
9810 + ipl = splbio();
9811 + }
9812 +
9813 + if (result == 0) { // awoken
9814 + if (wq->abort) {
9815 + wq->abort = 0;
9816 + result = -DWC_E_ABORT;
9817 + } else {
9818 + result = 0;
9819 + }
9820 +
9821 + splx(ipl);
9822 + simple_unlock(&wq->lock);
9823 + } else {
9824 + wq->abort = 0;
9825 + splx(ipl);
9826 + simple_unlock(&wq->lock);
9827 +
9828 + if (result == ERESTART) { // signaled - restart
9829 + result = -DWC_E_RESTART;
9830 + } else { // signaled - must be EINTR
9831 + result = -DWC_E_ABORT;
9832 + }
9833 + }
9834 +
9835 + return result;
9836 +}
9837 +
9838 +int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
9839 + void *data, int32_t msecs)
9840 +{
9841 + struct timeval tv, tv1, tv2;
9842 + int ipl;
9843 + int result = 0;
9844 +
9845 + tv.tv_sec = msecs / 1000;
9846 + tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
9847 +
9848 + simple_lock(&wq->lock);
9849 + ipl = splbio();
9850 +
9851 + /* Skip the sleep if already aborted or triggered */
9852 + if (!wq->abort && !cond(data)) {
9853 + splx(ipl);
9854 + getmicrouptime(&tv1);
9855 + result = ltsleep(wq, PCATCH, "dw3wto", tvtohz(&tv), &wq->lock);
9856 + getmicrouptime(&tv2);
9857 + ipl = splbio();
9858 + }
9859 +
9860 + if (result == 0) { // awoken
9861 + if (wq->abort) {
9862 + wq->abort = 0;
9863 + splx(ipl);
9864 + simple_unlock(&wq->lock);
9865 + result = -DWC_E_ABORT;
9866 + } else {
9867 + splx(ipl);
9868 + simple_unlock(&wq->lock);
9869 +
9870 + tv2.tv_usec -= tv1.tv_usec;
9871 + if (tv2.tv_usec < 0) {
9872 + tv2.tv_usec += 1000000;
9873 + tv2.tv_sec--;
9874 + }
9875 +
9876 + tv2.tv_sec -= tv1.tv_sec;
9877 + result = tv2.tv_sec * 1000 + tv2.tv_usec / 1000;
9878 + result = msecs - result;
9879 + if (result <= 0)
9880 + result = 1;
9881 + }
9882 + } else {
9883 + wq->abort = 0;
9884 + splx(ipl);
9885 + simple_unlock(&wq->lock);
9886 +
9887 + if (result == ERESTART) { // signaled - restart
9888 + result = -DWC_E_RESTART;
9889 +
9890 + } else if (result == EINTR) { // signaled - interrupt
9891 + result = -DWC_E_ABORT;
9892 +
9893 + } else { // timed out
9894 + result = -DWC_E_TIMEOUT;
9895 + }
9896 + }
9897 +
9898 + return result;
9899 +}
9900 +
9901 +void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)
9902 +{
9903 + wakeup(wq);
9904 +}
9905 +
9906 +void DWC_WAITQ_ABORT(dwc_waitq_t *wq)
9907 +{
9908 + int ipl;
9909 +
9910 + simple_lock(&wq->lock);
9911 + ipl = splbio();
9912 + wq->abort = 1;
9913 + wakeup(wq);
9914 + splx(ipl);
9915 + simple_unlock(&wq->lock);
9916 +}
9917 +
9918 +
9919 +/* Threading */
9920 +
9921 +struct dwc_thread {
9922 + struct proc *proc;
9923 + int abort;
9924 +};
9925 +
9926 +dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)
9927 +{
9928 + int retval;
9929 + dwc_thread_t *thread = DWC_ALLOC(sizeof(*thread));
9930 +
9931 + if (!thread) {
9932 + return NULL;
9933 + }
9934 +
9935 + thread->abort = 0;
9936 + retval = kthread_create1((void (*)(void *))func, data, &thread->proc,
9937 + "%s", name);
9938 + if (retval) {
9939 + DWC_FREE(thread);
9940 + return NULL;
9941 + }
9942 +
9943 + return thread;
9944 +}
9945 +
9946 +int DWC_THREAD_STOP(dwc_thread_t *thread)
9947 +{
9948 + int retval;
9949 +
9950 + thread->abort = 1;
9951 + retval = tsleep(&thread->abort, 0, "dw3stp", 60 * hz);
9952 +
9953 + if (retval == 0) {
9954 + /* DWC_THREAD_EXIT() will free the thread struct */
9955 + return 0;
9956 + }
9957 +
9958 + /* NOTE: We leak the thread struct if thread doesn't die */
9959 +
9960 + if (retval == EWOULDBLOCK) {
9961 + return -DWC_E_TIMEOUT;
9962 + }
9963 +
9964 + return -DWC_E_UNKNOWN;
9965 +}
9966 +
9967 +dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread)
9968 +{
9969 + return thread->abort;
9970 +}
9971 +
9972 +void DWC_THREAD_EXIT(dwc_thread_t *thread)
9973 +{
9974 + wakeup(&thread->abort);
9975 + DWC_FREE(thread);
9976 + kthread_exit(0);
9977 +}
9978 +
9979 +/* tasklets
9980 + - Runs in interrupt context (cannot sleep)
9981 + - Each tasklet runs on a single CPU
9982 + - Different tasklets can be running simultaneously on different CPUs
9983 + [ On NetBSD there is no corresponding mechanism, drivers don't have bottom-
9984 + halves. So we just call the callback directly from DWC_TASK_SCHEDULE() ]
9985 + */
9986 +struct dwc_tasklet {
9987 + dwc_tasklet_callback_t cb;
9988 + void *data;
9989 +};
9990 +
9991 +static void tasklet_callback(void *data)
9992 +{
9993 + dwc_tasklet_t *task = (dwc_tasklet_t *)data;
9994 +
9995 + task->cb(task->data);
9996 +}
9997 +
9998 +dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)
9999 +{
10000 + dwc_tasklet_t *task = DWC_ALLOC(sizeof(*task));
10001 +
10002 + if (task) {
10003 + task->cb = cb;
10004 + task->data = data;
10005 + } else {
10006 + DWC_ERROR("Cannot allocate memory for tasklet");
10007 + }
10008 +
10009 + return task;
10010 +}
10011 +
10012 +void DWC_TASK_FREE(dwc_tasklet_t *task)
10013 +{
10014 + DWC_FREE(task);
10015 +}
10016 +
10017 +void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)
10018 +{
10019 + tasklet_callback(task);
10020 +}
10021 +
10022 +
10023 +/* workqueues
10024 + - Runs in process context (can sleep)
10025 + */
10026 +typedef struct work_container {
10027 + dwc_work_callback_t cb;
10028 + void *data;
10029 + dwc_workq_t *wq;
10030 + char *name;
10031 + int hz;
10032 + struct work task;
10033 +} work_container_t;
10034 +
10035 +struct dwc_workq {
10036 + struct workqueue *taskq;
10037 + dwc_spinlock_t *lock;
10038 + dwc_waitq_t *waitq;
10039 + int pending;
10040 + struct work_container *container;
10041 +};
10042 +
10043 +static void do_work(struct work *task, void *data)
10044 +{
10045 + dwc_workq_t *wq = (dwc_workq_t *)data;
10046 + work_container_t *container = wq->container;
10047 + dwc_irqflags_t flags;
10048 +
10049 + if (container->hz) {
10050 + tsleep(container, 0, "dw3wrk", container->hz);
10051 + }
10052 +
10053 + container->cb(container->data);
10054 + DWC_DEBUG("Work done: %s, container=%p", container->name, container);
10055 +
10056 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
10057 + if (container->name)
10058 + DWC_FREE(container->name);
10059 + DWC_FREE(container);
10060 + wq->pending--;
10061 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
10062 + DWC_WAITQ_TRIGGER(wq->waitq);
10063 +}
10064 +
10065 +static int work_done(void *data)
10066 +{
10067 + dwc_workq_t *workq = (dwc_workq_t *)data;
10068 +
10069 + return workq->pending == 0;
10070 +}
10071 +
10072 +int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)
10073 +{
10074 + return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);
10075 +}
10076 +
10077 +dwc_workq_t *DWC_WORKQ_ALLOC(char *name)
10078 +{
10079 + int result;
10080 + dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));
10081 +
10082 + if (!wq) {
10083 + DWC_ERROR("Cannot allocate memory for workqueue");
10084 + return NULL;
10085 + }
10086 +
10087 + result = workqueue_create(&wq->taskq, name, do_work, wq, 0 /*PWAIT*/,
10088 + IPL_BIO, 0);
10089 + if (result) {
10090 + DWC_ERROR("Cannot create workqueue");
10091 + goto no_taskq;
10092 + }
10093 +
10094 + wq->pending = 0;
10095 +
10096 + wq->lock = DWC_SPINLOCK_ALLOC();
10097 + if (!wq->lock) {
10098 + DWC_ERROR("Cannot allocate memory for spinlock");
10099 + goto no_lock;
10100 + }
10101 +
10102 + wq->waitq = DWC_WAITQ_ALLOC();
10103 + if (!wq->waitq) {
10104 + DWC_ERROR("Cannot allocate memory for waitqueue");
10105 + goto no_waitq;
10106 + }
10107 +
10108 + return wq;
10109 +
10110 + no_waitq:
10111 + DWC_SPINLOCK_FREE(wq->lock);
10112 + no_lock:
10113 + workqueue_destroy(wq->taskq);
10114 + no_taskq:
10115 + DWC_FREE(wq);
10116 +
10117 + return NULL;
10118 +}
10119 +
10120 +void DWC_WORKQ_FREE(dwc_workq_t *wq)
10121 +{
10122 +#ifdef DEBUG
10123 + dwc_irqflags_t flags;
10124 +
10125 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
10126 +
10127 + if (wq->pending != 0) {
10128 + struct work_container *container = wq->container;
10129 +
10130 + DWC_ERROR("Destroying work queue with pending work");
10131 +
10132 + if (container && container->name) {
10133 + DWC_ERROR("Work %s still pending", container->name);
10134 + }
10135 + }
10136 +
10137 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
10138 +#endif
10139 + DWC_WAITQ_FREE(wq->waitq);
10140 + DWC_SPINLOCK_FREE(wq->lock);
10141 + workqueue_destroy(wq->taskq);
10142 + DWC_FREE(wq);
10143 +}
10144 +
10145 +void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,
10146 + char *format, ...)
10147 +{
10148 + dwc_irqflags_t flags;
10149 + work_container_t *container;
10150 + static char name[128];
10151 + va_list args;
10152 +
10153 + va_start(args, format);
10154 + DWC_VSNPRINTF(name, 128, format, args);
10155 + va_end(args);
10156 +
10157 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
10158 + wq->pending++;
10159 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
10160 + DWC_WAITQ_TRIGGER(wq->waitq);
10161 +
10162 + container = DWC_ALLOC_ATOMIC(sizeof(*container));
10163 + if (!container) {
10164 + DWC_ERROR("Cannot allocate memory for container");
10165 + return;
10166 + }
10167 +
10168 + container->name = DWC_STRDUP(name);
10169 + if (!container->name) {
10170 + DWC_ERROR("Cannot allocate memory for container->name");
10171 + DWC_FREE(container);
10172 + return;
10173 + }
10174 +
10175 + container->cb = cb;
10176 + container->data = data;
10177 + container->wq = wq;
10178 + container->hz = 0;
10179 + wq->container = container;
10180 +
10181 + DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
10182 + workqueue_enqueue(wq->taskq, &container->task);
10183 +}
10184 +
10185 +void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,
10186 + void *data, uint32_t time, char *format, ...)
10187 +{
10188 + dwc_irqflags_t flags;
10189 + work_container_t *container;
10190 + static char name[128];
10191 + struct timeval tv;
10192 + va_list args;
10193 +
10194 + va_start(args, format);
10195 + DWC_VSNPRINTF(name, 128, format, args);
10196 + va_end(args);
10197 +
10198 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
10199 + wq->pending++;
10200 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
10201 + DWC_WAITQ_TRIGGER(wq->waitq);
10202 +
10203 + container = DWC_ALLOC_ATOMIC(sizeof(*container));
10204 + if (!container) {
10205 + DWC_ERROR("Cannot allocate memory for container");
10206 + return;
10207 + }
10208 +
10209 + container->name = DWC_STRDUP(name);
10210 + if (!container->name) {
10211 + DWC_ERROR("Cannot allocate memory for container->name");
10212 + DWC_FREE(container);
10213 + return;
10214 + }
10215 +
10216 + container->cb = cb;
10217 + container->data = data;
10218 + container->wq = wq;
10219 + tv.tv_sec = time / 1000;
10220 + tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
10221 + container->hz = tvtohz(&tv);
10222 + wq->container = container;
10223 +
10224 + DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
10225 + workqueue_enqueue(wq->taskq, &container->task);
10226 +}
10227 +
10228 +int DWC_WORKQ_PENDING(dwc_workq_t *wq)
10229 +{
10230 + return wq->pending;
10231 +}
10232 --- /dev/null
10233 +++ b/drivers/usb/host/dwc_common_port/dwc_crypto.c
10234 @@ -0,0 +1,308 @@
10235 +/* =========================================================================
10236 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_crypto.c $
10237 + * $Revision: #5 $
10238 + * $Date: 2010/09/28 $
10239 + * $Change: 1596182 $
10240 + *
10241 + * Synopsys Portability Library Software and documentation
10242 + * (hereinafter, "Software") is an Unsupported proprietary work of
10243 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
10244 + * between Synopsys and you.
10245 + *
10246 + * The Software IS NOT an item of Licensed Software or Licensed Product
10247 + * under any End User Software License Agreement or Agreement for
10248 + * Licensed Product with Synopsys or any supplement thereto. You are
10249 + * permitted to use and redistribute this Software in source and binary
10250 + * forms, with or without modification, provided that redistributions
10251 + * of source code must retain this notice. You may not view, use,
10252 + * disclose, copy or distribute this file or any information contained
10253 + * herein except pursuant to this license grant from Synopsys. If you
10254 + * do not agree with this notice, including the disclaimer below, then
10255 + * you are not authorized to use the Software.
10256 + *
10257 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
10258 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
10259 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
10260 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
10261 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
10262 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
10263 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
10264 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
10265 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10266 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
10267 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
10268 + * DAMAGE.
10269 + * ========================================================================= */
10270 +
10271 +/** @file
10272 + * This file contains the WUSB cryptographic routines.
10273 + */
10274 +
10275 +#ifdef DWC_CRYPTOLIB
10276 +
10277 +#include "dwc_crypto.h"
10278 +#include "usb.h"
10279 +
10280 +#ifdef DEBUG
10281 +static inline void dump_bytes(char *name, uint8_t *bytes, int len)
10282 +{
10283 + int i;
10284 + DWC_PRINTF("%s: ", name);
10285 + for (i=0; i<len; i++) {
10286 + DWC_PRINTF("%02x ", bytes[i]);
10287 + }
10288 + DWC_PRINTF("\n");
10289 +}
10290 +#else
10291 +#define dump_bytes(x...)
10292 +#endif
10293 +
10294 +/* Display a block */
10295 +void show_block(const u8 *blk, const char *prefix, const char *suffix, int a)
10296 +{
10297 +#ifdef DWC_DEBUG_CRYPTO
10298 + int i, blksize = 16;
10299 +
10300 + DWC_DEBUG("%s", prefix);
10301 +
10302 + if (suffix == NULL) {
10303 + suffix = "\n";
10304 + blksize = a;
10305 + }
10306 +
10307 + for (i = 0; i < blksize; i++)
10308 + DWC_PRINT("%02x%s", *blk++, ((i & 3) == 3) ? " " : " ");
10309 + DWC_PRINT(suffix);
10310 +#endif
10311 +}
10312 +
10313 +/**
10314 + * Encrypts an array of bytes using the AES encryption engine.
10315 + * If <code>dst</code> == <code>src</code>, then the bytes will be encrypted
10316 + * in-place.
10317 + *
10318 + * @return 0 on success, negative error code on error.
10319 + */
10320 +int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst)
10321 +{
10322 + u8 block_t[16];
10323 + DWC_MEMSET(block_t, 0, 16);
10324 +
10325 + return DWC_AES_CBC(src, 16, key, 16, block_t, dst);
10326 +}
10327 +
10328 +/**
10329 + * The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec.
10330 + * This function takes a data string and returns the encrypted CBC
10331 + * Counter-mode MIC.
10332 + *
10333 + * @param key The 128-bit symmetric key.
10334 + * @param nonce The CCM nonce.
10335 + * @param label The unique 14-byte ASCII text label.
10336 + * @param bytes The byte array to be encrypted.
10337 + * @param len Length of the byte array.
10338 + * @param result Byte array to receive the 8-byte encrypted MIC.
10339 + */
10340 +void dwc_wusb_cmf(u8 *key, u8 *nonce,
10341 + char *label, u8 *bytes, int len, u8 *result)
10342 +{
10343 + u8 block_m[16];
10344 + u8 block_x[16];
10345 + u8 block_t[8];
10346 + int idx, blkNum;
10347 + u16 la = (u16)(len + 14);
10348 +
10349 + /* Set the AES-128 key */
10350 + //dwc_aes_setkey(tfm, key, 16);
10351 +
10352 + /* Fill block B0 from flags = 0x59, N, and l(m) = 0 */
10353 + block_m[0] = 0x59;
10354 + for (idx = 0; idx < 13; idx++)
10355 + block_m[idx + 1] = nonce[idx];
10356 + block_m[14] = 0;
10357 + block_m[15] = 0;
10358 +
10359 + /* Produce the CBC IV */
10360 + dwc_wusb_aes_encrypt(block_m, key, block_x);
10361 + show_block(block_m, "CBC IV in: ", "\n", 0);
10362 + show_block(block_x, "CBC IV out:", "\n", 0);
10363 +
10364 + /* Fill block B1 from l(a) = Blen + 14, and A */
10365 + block_x[0] ^= (u8)(la >> 8);
10366 + block_x[1] ^= (u8)la;
10367 + for (idx = 0; idx < 14; idx++)
10368 + block_x[idx + 2] ^= label[idx];
10369 + show_block(block_x, "After xor: ", "b1\n", 16);
10370 +
10371 + dwc_wusb_aes_encrypt(block_x, key, block_x);
10372 + show_block(block_x, "After AES: ", "b1\n", 16);
10373 +
10374 + idx = 0;
10375 + blkNum = 0;
10376 +
10377 + /* Fill remaining blocks with B */
10378 + while (len-- > 0) {
10379 + block_x[idx] ^= *bytes++;
10380 + if (++idx >= 16) {
10381 + idx = 0;
10382 + show_block(block_x, "After xor: ", "\n", blkNum);
10383 + dwc_wusb_aes_encrypt(block_x, key, block_x);
10384 + show_block(block_x, "After AES: ", "\n", blkNum);
10385 + blkNum++;
10386 + }
10387 + }
10388 +
10389 + /* Handle partial last block */
10390 + if (idx > 0) {
10391 + show_block(block_x, "After xor: ", "\n", blkNum);
10392 + dwc_wusb_aes_encrypt(block_x, key, block_x);
10393 + show_block(block_x, "After AES: ", "\n", blkNum);
10394 + }
10395 +
10396 + /* Save the MIC tag */
10397 + DWC_MEMCPY(block_t, block_x, 8);
10398 + show_block(block_t, "MIC tag : ", NULL, 8);
10399 +
10400 + /* Fill block A0 from flags = 0x01, N, and counter = 0 */
10401 + block_m[0] = 0x01;
10402 + block_m[14] = 0;
10403 + block_m[15] = 0;
10404 +
10405 + /* Encrypt the counter */
10406 + dwc_wusb_aes_encrypt(block_m, key, block_x);
10407 + show_block(block_x, "CTR[MIC] : ", NULL, 8);
10408 +
10409 + /* XOR with MIC tag */
10410 + for (idx = 0; idx < 8; idx++) {
10411 + block_t[idx] ^= block_x[idx];
10412 + }
10413 +
10414 + /* Return result to caller */
10415 + DWC_MEMCPY(result, block_t, 8);
10416 + show_block(result, "CCM-MIC : ", NULL, 8);
10417 +
10418 +}
10419 +
10420 +/**
10421 + * The PRF function described in section 6.5 of the WUSB spec. This function
10422 + * concatenates MIC values returned from dwc_cmf() to create a value of
10423 + * the requested length.
10424 + *
10425 + * @param prf_len Length of the PRF function in bits (64, 128, or 256).
10426 + * @param key, nonce, label, bytes, len Same as for dwc_cmf().
10427 + * @param result Byte array to receive the result.
10428 + */
10429 +void dwc_wusb_prf(int prf_len, u8 *key,
10430 + u8 *nonce, char *label, u8 *bytes, int len, u8 *result)
10431 +{
10432 + int i;
10433 +
10434 + nonce[0] = 0;
10435 + for (i = 0; i < prf_len >> 6; i++, nonce[0]++) {
10436 + dwc_wusb_cmf(key, nonce, label, bytes, len, result);
10437 + result += 8;
10438 + }
10439 +}
10440 +
10441 +/**
10442 + * Fills in CCM Nonce per the WUSB spec.
10443 + *
10444 + * @param[in] haddr Host address.
10445 + * @param[in] daddr Device address.
10446 + * @param[in] tkid Session Key(PTK) identifier.
10447 + * @param[out] nonce Pointer to where the CCM Nonce output is to be written.
10448 + */
10449 +void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid,
10450 + uint8_t *nonce)
10451 +{
10452 +
10453 + DWC_DEBUG("%s %x %x\n", __func__, daddr, haddr);
10454 +
10455 + DWC_MEMSET(&nonce[0], 0, 16);
10456 +
10457 + DWC_MEMCPY(&nonce[6], tkid, 3);
10458 + nonce[9] = daddr & 0xFF;
10459 + nonce[10] = (daddr >> 8) & 0xFF;
10460 + nonce[11] = haddr & 0xFF;
10461 + nonce[12] = (haddr >> 8) & 0xFF;
10462 +
10463 + dump_bytes("CCM nonce", nonce, 16);
10464 +}
10465 +
10466 +/**
10467 + * Generates a 16-byte cryptographic-grade random number for the Host/Device
10468 + * Nonce.
10469 + */
10470 +void dwc_wusb_gen_nonce(uint16_t addr, uint8_t *nonce)
10471 +{
10472 + uint8_t inonce[16];
10473 + uint32_t temp[4];
10474 +
10475 + /* Fill in the Nonce */
10476 + DWC_MEMSET(&inonce[0], 0, sizeof(inonce));
10477 + inonce[9] = addr & 0xFF;
10478 + inonce[10] = (addr >> 8) & 0xFF;
10479 + inonce[11] = inonce[9];
10480 + inonce[12] = inonce[10];
10481 +
10482 + /* Collect "randomness samples" */
10483 + DWC_RANDOM_BYTES((uint8_t *)temp, 16);
10484 +
10485 + dwc_wusb_prf_128((uint8_t *)temp, nonce,
10486 + "Random Numbers", (uint8_t *)temp, sizeof(temp),
10487 + nonce);
10488 +}
10489 +
10490 +/**
10491 + * Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the
10492 + * WUSB spec.
10493 + *
10494 + * @param[in] ccm_nonce Pointer to CCM Nonce.
10495 + * @param[in] mk Master Key to derive the session from
10496 + * @param[in] hnonce Pointer to Host Nonce.
10497 + * @param[in] dnonce Pointer to Device Nonce.
10498 + * @param[out] kck Pointer to where the KCK output is to be written.
10499 + * @param[out] ptk Pointer to where the PTK output is to be written.
10500 + */
10501 +void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk, uint8_t *hnonce,
10502 + uint8_t *dnonce, uint8_t *kck, uint8_t *ptk)
10503 +{
10504 + uint8_t idata[32];
10505 + uint8_t odata[32];
10506 +
10507 + dump_bytes("ck", mk, 16);
10508 + dump_bytes("hnonce", hnonce, 16);
10509 + dump_bytes("dnonce", dnonce, 16);
10510 +
10511 + /* The data is the HNonce and DNonce concatenated */
10512 + DWC_MEMCPY(&idata[0], hnonce, 16);
10513 + DWC_MEMCPY(&idata[16], dnonce, 16);
10514 +
10515 + dwc_wusb_prf_256(mk, ccm_nonce, "Pair-wise keys", idata, 32, odata);
10516 +
10517 + /* Low 16 bytes of the result is the KCK, high 16 is the PTK */
10518 + DWC_MEMCPY(kck, &odata[0], 16);
10519 + DWC_MEMCPY(ptk, &odata[16], 16);
10520 +
10521 + dump_bytes("kck", kck, 16);
10522 + dump_bytes("ptk", ptk, 16);
10523 +}
10524 +
10525 +/**
10526 + * Generates the Message Integrity Code over the Handshake data per the
10527 + * WUSB spec.
10528 + *
10529 + * @param ccm_nonce Pointer to CCM Nonce.
10530 + * @param kck Pointer to Key Confirmation Key.
10531 + * @param data Pointer to Handshake data to be checked.
10532 + * @param mic Pointer to where the MIC output is to be written.
10533 + */
10534 +void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t *kck,
10535 + uint8_t *data, uint8_t *mic)
10536 +{
10537 +
10538 + dwc_wusb_prf_64(kck, ccm_nonce, "out-of-bandMIC",
10539 + data, WUSB_HANDSHAKE_LEN_FOR_MIC, mic);
10540 +}
10541 +
10542 +#endif /* DWC_CRYPTOLIB */
10543 --- /dev/null
10544 +++ b/drivers/usb/host/dwc_common_port/dwc_crypto.h
10545 @@ -0,0 +1,111 @@
10546 +/* =========================================================================
10547 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_crypto.h $
10548 + * $Revision: #3 $
10549 + * $Date: 2010/09/28 $
10550 + * $Change: 1596182 $
10551 + *
10552 + * Synopsys Portability Library Software and documentation
10553 + * (hereinafter, "Software") is an Unsupported proprietary work of
10554 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
10555 + * between Synopsys and you.
10556 + *
10557 + * The Software IS NOT an item of Licensed Software or Licensed Product
10558 + * under any End User Software License Agreement or Agreement for
10559 + * Licensed Product with Synopsys or any supplement thereto. You are
10560 + * permitted to use and redistribute this Software in source and binary
10561 + * forms, with or without modification, provided that redistributions
10562 + * of source code must retain this notice. You may not view, use,
10563 + * disclose, copy or distribute this file or any information contained
10564 + * herein except pursuant to this license grant from Synopsys. If you
10565 + * do not agree with this notice, including the disclaimer below, then
10566 + * you are not authorized to use the Software.
10567 + *
10568 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
10569 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
10570 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
10571 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
10572 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
10573 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
10574 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
10575 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
10576 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10577 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
10578 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
10579 + * DAMAGE.
10580 + * ========================================================================= */
10581 +
10582 +#ifndef _DWC_CRYPTO_H_
10583 +#define _DWC_CRYPTO_H_
10584 +
10585 +#ifdef __cplusplus
10586 +extern "C" {
10587 +#endif
10588 +
10589 +/** @file
10590 + *
10591 + * This file contains declarations for the WUSB Cryptographic routines as
10592 + * defined in the WUSB spec. They are only to be used internally by the DWC UWB
10593 + * modules.
10594 + */
10595 +
10596 +#include "dwc_os.h"
10597 +
10598 +int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst);
10599 +
10600 +void dwc_wusb_cmf(u8 *key, u8 *nonce,
10601 + char *label, u8 *bytes, int len, u8 *result);
10602 +void dwc_wusb_prf(int prf_len, u8 *key,
10603 + u8 *nonce, char *label, u8 *bytes, int len, u8 *result);
10604 +
10605 +/**
10606 + * The PRF-64 function described in section 6.5 of the WUSB spec.
10607 + *
10608 + * @param key, nonce, label, bytes, len, result Same as for dwc_prf().
10609 + */
10610 +static inline void dwc_wusb_prf_64(u8 *key, u8 *nonce,
10611 + char *label, u8 *bytes, int len, u8 *result)
10612 +{
10613 + dwc_wusb_prf(64, key, nonce, label, bytes, len, result);
10614 +}
10615 +
10616 +/**
10617 + * The PRF-128 function described in section 6.5 of the WUSB spec.
10618 + *
10619 + * @param key, nonce, label, bytes, len, result Same as for dwc_prf().
10620 + */
10621 +static inline void dwc_wusb_prf_128(u8 *key, u8 *nonce,
10622 + char *label, u8 *bytes, int len, u8 *result)
10623 +{
10624 + dwc_wusb_prf(128, key, nonce, label, bytes, len, result);
10625 +}
10626 +
10627 +/**
10628 + * The PRF-256 function described in section 6.5 of the WUSB spec.
10629 + *
10630 + * @param key, nonce, label, bytes, len, result Same as for dwc_prf().
10631 + */
10632 +static inline void dwc_wusb_prf_256(u8 *key, u8 *nonce,
10633 + char *label, u8 *bytes, int len, u8 *result)
10634 +{
10635 + dwc_wusb_prf(256, key, nonce, label, bytes, len, result);
10636 +}
10637 +
10638 +
10639 +void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid,
10640 + uint8_t *nonce);
10641 +void dwc_wusb_gen_nonce(uint16_t addr,
10642 + uint8_t *nonce);
10643 +
10644 +void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk,
10645 + uint8_t *hnonce, uint8_t *dnonce,
10646 + uint8_t *kck, uint8_t *ptk);
10647 +
10648 +
10649 +void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t
10650 + *kck, uint8_t *data, uint8_t *mic);
10651 +
10652 +#ifdef __cplusplus
10653 +}
10654 +#endif
10655 +
10656 +#endif /* _DWC_CRYPTO_H_ */
10657 --- /dev/null
10658 +++ b/drivers/usb/host/dwc_common_port/dwc_dh.c
10659 @@ -0,0 +1,291 @@
10660 +/* =========================================================================
10661 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_dh.c $
10662 + * $Revision: #3 $
10663 + * $Date: 2010/09/28 $
10664 + * $Change: 1596182 $
10665 + *
10666 + * Synopsys Portability Library Software and documentation
10667 + * (hereinafter, "Software") is an Unsupported proprietary work of
10668 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
10669 + * between Synopsys and you.
10670 + *
10671 + * The Software IS NOT an item of Licensed Software or Licensed Product
10672 + * under any End User Software License Agreement or Agreement for
10673 + * Licensed Product with Synopsys or any supplement thereto. You are
10674 + * permitted to use and redistribute this Software in source and binary
10675 + * forms, with or without modification, provided that redistributions
10676 + * of source code must retain this notice. You may not view, use,
10677 + * disclose, copy or distribute this file or any information contained
10678 + * herein except pursuant to this license grant from Synopsys. If you
10679 + * do not agree with this notice, including the disclaimer below, then
10680 + * you are not authorized to use the Software.
10681 + *
10682 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
10683 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
10684 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
10685 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
10686 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
10687 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
10688 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
10689 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
10690 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10691 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
10692 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
10693 + * DAMAGE.
10694 + * ========================================================================= */
10695 +#ifdef DWC_CRYPTOLIB
10696 +
10697 +#ifndef CONFIG_MACH_IPMATE
10698 +
10699 +#include "dwc_dh.h"
10700 +#include "dwc_modpow.h"
10701 +
10702 +#ifdef DEBUG
10703 +/* This function prints out a buffer in the format described in the Association
10704 + * Model specification. */
10705 +static void dh_dump(char *str, void *_num, int len)
10706 +{
10707 + uint8_t *num = _num;
10708 + int i;
10709 + DWC_PRINTF("%s\n", str);
10710 + for (i = 0; i < len; i ++) {
10711 + DWC_PRINTF("%02x", num[i]);
10712 + if (((i + 1) % 2) == 0) DWC_PRINTF(" ");
10713 + if (((i + 1) % 26) == 0) DWC_PRINTF("\n");
10714 + }
10715 +
10716 + DWC_PRINTF("\n");
10717 +}
10718 +#else
10719 +#define dh_dump(_x...) do {; } while(0)
10720 +#endif
10721 +
10722 +/* Constant g value */
10723 +static __u32 dh_g[] = {
10724 + 0x02000000,
10725 +};
10726 +
10727 +/* Constant p value */
10728 +static __u32 dh_p[] = {
10729 + 0xFFFFFFFF, 0xFFFFFFFF, 0xA2DA0FC9, 0x34C26821, 0x8B62C6C4, 0xD11CDC80, 0x084E0229, 0x74CC678A,
10730 + 0xA6BE0B02, 0x229B133B, 0x79084A51, 0xDD04348E, 0xB31995EF, 0x1B433ACD, 0x6D0A2B30, 0x37145FF2,
10731 + 0x6D35E14F, 0x45C2516D, 0x76B585E4, 0xC67E5E62, 0xE9424CF4, 0x6BED37A6, 0xB65CFF0B, 0xEDB706F4,
10732 + 0xFB6B38EE, 0xA59F895A, 0x11249FAE, 0xE61F4B7C, 0x51662849, 0x3D5BE4EC, 0xB87C00C2, 0x05BF63A1,
10733 + 0x3648DA98, 0x9AD3551C, 0xA83F1669, 0x5FCF24FD, 0x235D6583, 0x96ADA3DC, 0x56F3621C, 0xBB528520,
10734 + 0x0729D59E, 0x6D969670, 0x4E350C67, 0x0498BC4A, 0x086C74F1, 0x7C2118CA, 0x465E9032, 0x3BCE362E,
10735 + 0x2C779EE3, 0x03860E18, 0xA283279B, 0x8FA207EC, 0xF05DC5B5, 0xC9524C6F, 0xF6CB2BDE, 0x18175895,
10736 + 0x7C499539, 0xE56A95EA, 0x1826D215, 0x1005FA98, 0x5A8E7215, 0x2DC4AA8A, 0x0D1733AD, 0x337A5004,
10737 + 0xAB2155A8, 0x64BA1CDF, 0x0485FBEC, 0x0AEFDB58, 0x5771EA8A, 0x7D0C065D, 0x850F97B3, 0xC7E4E1A6,
10738 + 0x8CAEF5AB, 0xD73309DB, 0xE0948C1E, 0x9D61254A, 0x26D2E3CE, 0x6BEED21A, 0x06FA2FF1, 0x64088AD9,
10739 + 0x730276D8, 0x646AC83E, 0x182B1F52, 0x0C207B17, 0x5717E1BB, 0x6C5D617A, 0xC0880977, 0xE246D9BA,
10740 + 0xA04FE208, 0x31ABE574, 0xFC5BDB43, 0x8E10FDE0, 0x20D1824B, 0xCAD23AA9, 0xFFFFFFFF, 0xFFFFFFFF,
10741 +};
10742 +
10743 +static void dh_swap_bytes(void *_in, void *_out, uint32_t len)
10744 +{
10745 + uint8_t *in = _in;
10746 + uint8_t *out = _out;
10747 + int i;
10748 + for (i=0; i<len; i++) {
10749 + out[i] = in[len-1-i];
10750 + }
10751 +}
10752 +
10753 +/* Computes the modular exponentiation (num^exp % mod). num, exp, and mod are
10754 + * big endian numbers of size len, in bytes. Each len value must be a multiple
10755 + * of 4. */
10756 +int dwc_dh_modpow(void *mem_ctx, void *num, uint32_t num_len,
10757 + void *exp, uint32_t exp_len,
10758 + void *mod, uint32_t mod_len,
10759 + void *out)
10760 +{
10761 + /* modpow() takes little endian numbers. AM uses big-endian. This
10762 + * function swaps bytes of numbers before passing onto modpow. */
10763 +
10764 + int retval = 0;
10765 + uint32_t *result;
10766 +
10767 + uint32_t *bignum_num = dwc_alloc(mem_ctx, num_len + 4);
10768 + uint32_t *bignum_exp = dwc_alloc(mem_ctx, exp_len + 4);
10769 + uint32_t *bignum_mod = dwc_alloc(mem_ctx, mod_len + 4);
10770 +
10771 + dh_swap_bytes(num, &bignum_num[1], num_len);
10772 + bignum_num[0] = num_len / 4;
10773 +
10774 + dh_swap_bytes(exp, &bignum_exp[1], exp_len);
10775 + bignum_exp[0] = exp_len / 4;
10776 +
10777 + dh_swap_bytes(mod, &bignum_mod[1], mod_len);
10778 + bignum_mod[0] = mod_len / 4;
10779 +
10780 + result = dwc_modpow(mem_ctx, bignum_num, bignum_exp, bignum_mod);
10781 + if (!result) {
10782 + retval = -1;
10783 + goto dh_modpow_nomem;
10784 + }
10785 +
10786 + dh_swap_bytes(&result[1], out, result[0] * 4);
10787 + dwc_free(mem_ctx, result);
10788 +
10789 + dh_modpow_nomem:
10790 + dwc_free(mem_ctx, bignum_num);
10791 + dwc_free(mem_ctx, bignum_exp);
10792 + dwc_free(mem_ctx, bignum_mod);
10793 + return retval;
10794 +}
10795 +
10796 +
10797 +int dwc_dh_pk(void *mem_ctx, uint8_t nd, uint8_t *exp, uint8_t *pk, uint8_t *hash)
10798 +{
10799 + int retval;
10800 + uint8_t m3[385];
10801 +
10802 +#ifndef DH_TEST_VECTORS
10803 + DWC_RANDOM_BYTES(exp, 32);
10804 +#endif
10805 +
10806 + /* Compute the pkd */
10807 + if ((retval = dwc_dh_modpow(mem_ctx, dh_g, 4,
10808 + exp, 32,
10809 + dh_p, 384, pk))) {
10810 + return retval;
10811 + }
10812 +
10813 + m3[384] = nd;
10814 + DWC_MEMCPY(&m3[0], pk, 384);
10815 + DWC_SHA256(m3, 385, hash);
10816 +
10817 + dh_dump("PK", pk, 384);
10818 + dh_dump("SHA-256(M3)", hash, 32);
10819 + return 0;
10820 +}
10821 +
10822 +int dwc_dh_derive_keys(void *mem_ctx, uint8_t nd, uint8_t *pkh, uint8_t *pkd,
10823 + uint8_t *exp, int is_host,
10824 + char *dd, uint8_t *ck, uint8_t *kdk)
10825 +{
10826 + int retval;
10827 + uint8_t mv[784];
10828 + uint8_t sha_result[32];
10829 + uint8_t dhkey[384];
10830 + uint8_t shared_secret[384];
10831 + char *message;
10832 + uint32_t vd;
10833 +
10834 + uint8_t *pk;
10835 +
10836 + if (is_host) {
10837 + pk = pkd;
10838 + }
10839 + else {
10840 + pk = pkh;
10841 + }
10842 +
10843 + if ((retval = dwc_dh_modpow(mem_ctx, pk, 384,
10844 + exp, 32,
10845 + dh_p, 384, shared_secret))) {
10846 + return retval;
10847 + }
10848 + dh_dump("Shared Secret", shared_secret, 384);
10849 +
10850 + DWC_SHA256(shared_secret, 384, dhkey);
10851 + dh_dump("DHKEY", dhkey, 384);
10852 +
10853 + DWC_MEMCPY(&mv[0], pkd, 384);
10854 + DWC_MEMCPY(&mv[384], pkh, 384);
10855 + DWC_MEMCPY(&mv[768], "displayed digest", 16);
10856 + dh_dump("MV", mv, 784);
10857 +
10858 + DWC_SHA256(mv, 784, sha_result);
10859 + dh_dump("SHA-256(MV)", sha_result, 32);
10860 + dh_dump("First 32-bits of SHA-256(MV)", sha_result, 4);
10861 +
10862 + dh_swap_bytes(sha_result, &vd, 4);
10863 +#ifdef DEBUG
10864 + DWC_PRINTF("Vd (decimal) = %d\n", vd);
10865 +#endif
10866 +
10867 + switch (nd) {
10868 + case 2:
10869 + vd = vd % 100;
10870 + DWC_SPRINTF(dd, "%02d", vd);
10871 + break;
10872 + case 3:
10873 + vd = vd % 1000;
10874 + DWC_SPRINTF(dd, "%03d", vd);
10875 + break;
10876 + case 4:
10877 + vd = vd % 10000;
10878 + DWC_SPRINTF(dd, "%04d", vd);
10879 + break;
10880 + }
10881 +#ifdef DEBUG
10882 + DWC_PRINTF("Display Digits: %s\n", dd);
10883 +#endif
10884 +
10885 + message = "connection key";
10886 + DWC_HMAC_SHA256(message, DWC_STRLEN(message), dhkey, 32, sha_result);
10887 + dh_dump("HMAC(SHA-256, DHKey, connection key)", sha_result, 32);
10888 + DWC_MEMCPY(ck, sha_result, 16);
10889 +
10890 + message = "key derivation key";
10891 + DWC_HMAC_SHA256(message, DWC_STRLEN(message), dhkey, 32, sha_result);
10892 + dh_dump("HMAC(SHA-256, DHKey, key derivation key)", sha_result, 32);
10893 + DWC_MEMCPY(kdk, sha_result, 32);
10894 +
10895 + return 0;
10896 +}
10897 +
10898 +
10899 +#ifdef DH_TEST_VECTORS
10900 +
10901 +static __u8 dh_a[] = {
10902 + 0x44, 0x00, 0x51, 0xd6,
10903 + 0xf0, 0xb5, 0x5e, 0xa9,
10904 + 0x67, 0xab, 0x31, 0xc6,
10905 + 0x8a, 0x8b, 0x5e, 0x37,
10906 + 0xd9, 0x10, 0xda, 0xe0,
10907 + 0xe2, 0xd4, 0x59, 0xa4,
10908 + 0x86, 0x45, 0x9c, 0xaa,
10909 + 0xdf, 0x36, 0x75, 0x16,
10910 +};
10911 +
10912 +static __u8 dh_b[] = {
10913 + 0x5d, 0xae, 0xc7, 0x86,
10914 + 0x79, 0x80, 0xa3, 0x24,
10915 + 0x8c, 0xe3, 0x57, 0x8f,
10916 + 0xc7, 0x5f, 0x1b, 0x0f,
10917 + 0x2d, 0xf8, 0x9d, 0x30,
10918 + 0x6f, 0xa4, 0x52, 0xcd,
10919 + 0xe0, 0x7a, 0x04, 0x8a,
10920 + 0xde, 0xd9, 0x26, 0x56,
10921 +};
10922 +
10923 +void dwc_run_dh_test_vectors(void *mem_ctx)
10924 +{
10925 + uint8_t pkd[384];
10926 + uint8_t pkh[384];
10927 + uint8_t hashd[32];
10928 + uint8_t hashh[32];
10929 + uint8_t ck[16];
10930 + uint8_t kdk[32];
10931 + char dd[5];
10932 +
10933 + DWC_PRINTF("\n\n\nDH_TEST_VECTORS\n\n");
10934 +
10935 + /* compute the PKd and SHA-256(PKd || Nd) */
10936 + DWC_PRINTF("Computing PKd\n");
10937 + dwc_dh_pk(mem_ctx, 2, dh_a, pkd, hashd);
10938 +
10939 + /* compute the PKd and SHA-256(PKh || Nd) */
10940 + DWC_PRINTF("Computing PKh\n");
10941 + dwc_dh_pk(mem_ctx, 2, dh_b, pkh, hashh);
10942 +
10943 + /* compute the dhkey */
10944 + dwc_dh_derive_keys(mem_ctx, 2, pkh, pkd, dh_a, 0, dd, ck, kdk);
10945 +}
10946 +#endif /* DH_TEST_VECTORS */
10947 +
10948 +#endif /* !CONFIG_MACH_IPMATE */
10949 +
10950 +#endif /* DWC_CRYPTOLIB */
10951 --- /dev/null
10952 +++ b/drivers/usb/host/dwc_common_port/dwc_dh.h
10953 @@ -0,0 +1,106 @@
10954 +/* =========================================================================
10955 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_dh.h $
10956 + * $Revision: #4 $
10957 + * $Date: 2010/09/28 $
10958 + * $Change: 1596182 $
10959 + *
10960 + * Synopsys Portability Library Software and documentation
10961 + * (hereinafter, "Software") is an Unsupported proprietary work of
10962 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
10963 + * between Synopsys and you.
10964 + *
10965 + * The Software IS NOT an item of Licensed Software or Licensed Product
10966 + * under any End User Software License Agreement or Agreement for
10967 + * Licensed Product with Synopsys or any supplement thereto. You are
10968 + * permitted to use and redistribute this Software in source and binary
10969 + * forms, with or without modification, provided that redistributions
10970 + * of source code must retain this notice. You may not view, use,
10971 + * disclose, copy or distribute this file or any information contained
10972 + * herein except pursuant to this license grant from Synopsys. If you
10973 + * do not agree with this notice, including the disclaimer below, then
10974 + * you are not authorized to use the Software.
10975 + *
10976 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
10977 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
10978 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
10979 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
10980 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
10981 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
10982 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
10983 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
10984 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10985 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
10986 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
10987 + * DAMAGE.
10988 + * ========================================================================= */
10989 +#ifndef _DWC_DH_H_
10990 +#define _DWC_DH_H_
10991 +
10992 +#ifdef __cplusplus
10993 +extern "C" {
10994 +#endif
10995 +
10996 +#include "dwc_os.h"
10997 +
10998 +/** @file
10999 + *
11000 + * This file defines the common functions on device and host for performing
11001 + * numeric association as defined in the WUSB spec. They are only to be
11002 + * used internally by the DWC UWB modules. */
11003 +
11004 +extern int dwc_dh_sha256(uint8_t *message, uint32_t len, uint8_t *out);
11005 +extern int dwc_dh_hmac_sha256(uint8_t *message, uint32_t messagelen,
11006 + uint8_t *key, uint32_t keylen,
11007 + uint8_t *out);
11008 +extern int dwc_dh_modpow(void *mem_ctx, void *num, uint32_t num_len,
11009 + void *exp, uint32_t exp_len,
11010 + void *mod, uint32_t mod_len,
11011 + void *out);
11012 +
11013 +/** Computes PKD or PKH, and SHA-256(PKd || Nd)
11014 + *
11015 + * PK = g^exp mod p.
11016 + *
11017 + * Input:
11018 + * Nd = Number of digits on the device.
11019 + *
11020 + * Output:
11021 + * exp = A 32-byte buffer to be filled with a randomly generated number.
11022 + * used as either A or B.
11023 + * pk = A 384-byte buffer to be filled with the PKH or PKD.
11024 + * hash = A 32-byte buffer to be filled with SHA-256(PK || ND).
11025 + */
11026 +extern int dwc_dh_pk(void *mem_ctx, uint8_t nd, uint8_t *exp, uint8_t *pkd, uint8_t *hash);
11027 +
11028 +/** Computes the DHKEY, and VD.
11029 + *
11030 + * If called from host, then it will comput DHKEY=PKD^exp % p.
11031 + * If called from device, then it will comput DHKEY=PKH^exp % p.
11032 + *
11033 + * Input:
11034 + * pkd = The PKD value.
11035 + * pkh = The PKH value.
11036 + * exp = The A value (if device) or B value (if host) generated in dwc_wudev_dh_pk.
11037 + * is_host = Set to non zero if a WUSB host is calling this function.
11038 + *
11039 + * Output:
11040 +
11041 + * dd = A pointer to an buffer to be set to the displayed digits string to be shown
11042 + * to the user. This buffer should be at 5 bytes long to hold 4 digits plus a
11043 + * null termination character. This buffer can be used directly for display.
11044 + * ck = A 16-byte buffer to be filled with the CK.
11045 + * kdk = A 32-byte buffer to be filled with the KDK.
11046 + */
11047 +extern int dwc_dh_derive_keys(void *mem_ctx, uint8_t nd, uint8_t *pkh, uint8_t *pkd,
11048 + uint8_t *exp, int is_host,
11049 + char *dd, uint8_t *ck, uint8_t *kdk);
11050 +
11051 +#ifdef DH_TEST_VECTORS
11052 +extern void dwc_run_dh_test_vectors(void);
11053 +#endif
11054 +
11055 +#ifdef __cplusplus
11056 +}
11057 +#endif
11058 +
11059 +#endif /* _DWC_DH_H_ */
11060 --- /dev/null
11061 +++ b/drivers/usb/host/dwc_common_port/dwc_list.h
11062 @@ -0,0 +1,594 @@
11063 +/* $OpenBSD: queue.h,v 1.26 2004/05/04 16:59:32 grange Exp $ */
11064 +/* $NetBSD: queue.h,v 1.11 1996/05/16 05:17:14 mycroft Exp $ */
11065 +
11066 +/*
11067 + * Copyright (c) 1991, 1993
11068 + * The Regents of the University of California. All rights reserved.
11069 + *
11070 + * Redistribution and use in source and binary forms, with or without
11071 + * modification, are permitted provided that the following conditions
11072 + * are met:
11073 + * 1. Redistributions of source code must retain the above copyright
11074 + * notice, this list of conditions and the following disclaimer.
11075 + * 2. Redistributions in binary form must reproduce the above copyright
11076 + * notice, this list of conditions and the following disclaimer in the
11077 + * documentation and/or other materials provided with the distribution.
11078 + * 3. Neither the name of the University nor the names of its contributors
11079 + * may be used to endorse or promote products derived from this software
11080 + * without specific prior written permission.
11081 + *
11082 + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
11083 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
11084 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
11085 + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
11086 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
11087 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
11088 + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
11089 + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
11090 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
11091 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
11092 + * SUCH DAMAGE.
11093 + *
11094 + * @(#)queue.h 8.5 (Berkeley) 8/20/94
11095 + */
11096 +
11097 +#ifndef _DWC_LIST_H_
11098 +#define _DWC_LIST_H_
11099 +
11100 +#ifdef __cplusplus
11101 +extern "C" {
11102 +#endif
11103 +
11104 +/** @file
11105 + *
11106 + * This file defines linked list operations. It is derived from BSD with
11107 + * only the MACRO names being prefixed with DWC_. This is because a few of
11108 + * these names conflict with those on Linux. For documentation on use, see the
11109 + * inline comments in the source code. The original license for this source
11110 + * code applies and is preserved in the dwc_list.h source file.
11111 + */
11112 +
11113 +/*
11114 + * This file defines five types of data structures: singly-linked lists,
11115 + * lists, simple queues, tail queues, and circular queues.
11116 + *
11117 + *
11118 + * A singly-linked list is headed by a single forward pointer. The elements
11119 + * are singly linked for minimum space and pointer manipulation overhead at
11120 + * the expense of O(n) removal for arbitrary elements. New elements can be
11121 + * added to the list after an existing element or at the head of the list.
11122 + * Elements being removed from the head of the list should use the explicit
11123 + * macro for this purpose for optimum efficiency. A singly-linked list may
11124 + * only be traversed in the forward direction. Singly-linked lists are ideal
11125 + * for applications with large datasets and few or no removals or for
11126 + * implementing a LIFO queue.
11127 + *
11128 + * A list is headed by a single forward pointer (or an array of forward
11129 + * pointers for a hash table header). The elements are doubly linked
11130 + * so that an arbitrary element can be removed without a need to
11131 + * traverse the list. New elements can be added to the list before
11132 + * or after an existing element or at the head of the list. A list
11133 + * may only be traversed in the forward direction.
11134 + *
11135 + * A simple queue is headed by a pair of pointers, one the head of the
11136 + * list and the other to the tail of the list. The elements are singly
11137 + * linked to save space, so elements can only be removed from the
11138 + * head of the list. New elements can be added to the list before or after
11139 + * an existing element, at the head of the list, or at the end of the
11140 + * list. A simple queue may only be traversed in the forward direction.
11141 + *
11142 + * A tail queue is headed by a pair of pointers, one to the head of the
11143 + * list and the other to the tail of the list. The elements are doubly
11144 + * linked so that an arbitrary element can be removed without a need to
11145 + * traverse the list. New elements can be added to the list before or
11146 + * after an existing element, at the head of the list, or at the end of
11147 + * the list. A tail queue may be traversed in either direction.
11148 + *
11149 + * A circle queue is headed by a pair of pointers, one to the head of the
11150 + * list and the other to the tail of the list. The elements are doubly
11151 + * linked so that an arbitrary element can be removed without a need to
11152 + * traverse the list. New elements can be added to the list before or after
11153 + * an existing element, at the head of the list, or at the end of the list.
11154 + * A circle queue may be traversed in either direction, but has a more
11155 + * complex end of list detection.
11156 + *
11157 + * For details on the use of these macros, see the queue(3) manual page.
11158 + */
11159 +
11160 +/*
11161 + * Double-linked List.
11162 + */
11163 +
11164 +typedef struct dwc_list_link {
11165 + struct dwc_list_link *next;
11166 + struct dwc_list_link *prev;
11167 +} dwc_list_link_t;
11168 +
11169 +#define DWC_LIST_INIT(link) do { \
11170 + (link)->next = (link); \
11171 + (link)->prev = (link); \
11172 +} while (0)
11173 +
11174 +#define DWC_LIST_FIRST(link) ((link)->next)
11175 +#define DWC_LIST_LAST(link) ((link)->prev)
11176 +#define DWC_LIST_END(link) (link)
11177 +#define DWC_LIST_NEXT(link) ((link)->next)
11178 +#define DWC_LIST_PREV(link) ((link)->prev)
11179 +#define DWC_LIST_EMPTY(link) \
11180 + (DWC_LIST_FIRST(link) == DWC_LIST_END(link))
11181 +#define DWC_LIST_ENTRY(link, type, field) \
11182 + (type *)((uint8_t *)(link) - (size_t)(&((type *)0)->field))
11183 +
11184 +#if 0
11185 +#define DWC_LIST_INSERT_HEAD(list, link) do { \
11186 + (link)->next = (list)->next; \
11187 + (link)->prev = (list); \
11188 + (list)->next->prev = (link); \
11189 + (list)->next = (link); \
11190 +} while (0)
11191 +
11192 +#define DWC_LIST_INSERT_TAIL(list, link) do { \
11193 + (link)->next = (list); \
11194 + (link)->prev = (list)->prev; \
11195 + (list)->prev->next = (link); \
11196 + (list)->prev = (link); \
11197 +} while (0)
11198 +#else
11199 +#define DWC_LIST_INSERT_HEAD(list, link) do { \
11200 + dwc_list_link_t *__next__ = (list)->next; \
11201 + __next__->prev = (link); \
11202 + (link)->next = __next__; \
11203 + (link)->prev = (list); \
11204 + (list)->next = (link); \
11205 +} while (0)
11206 +
11207 +#define DWC_LIST_INSERT_TAIL(list, link) do { \
11208 + dwc_list_link_t *__prev__ = (list)->prev; \
11209 + (list)->prev = (link); \
11210 + (link)->next = (list); \
11211 + (link)->prev = __prev__; \
11212 + __prev__->next = (link); \
11213 +} while (0)
11214 +#endif
11215 +
11216 +#if 0
11217 +static inline void __list_add(struct list_head *new,
11218 + struct list_head *prev,
11219 + struct list_head *next)
11220 +{
11221 + next->prev = new;
11222 + new->next = next;
11223 + new->prev = prev;
11224 + prev->next = new;
11225 +}
11226 +
11227 +static inline void list_add(struct list_head *new, struct list_head *head)
11228 +{
11229 + __list_add(new, head, head->next);
11230 +}
11231 +
11232 +static inline void list_add_tail(struct list_head *new, struct list_head *head)
11233 +{
11234 + __list_add(new, head->prev, head);
11235 +}
11236 +
11237 +static inline void __list_del(struct list_head * prev, struct list_head * next)
11238 +{
11239 + next->prev = prev;
11240 + prev->next = next;
11241 +}
11242 +
11243 +static inline void list_del(struct list_head *entry)
11244 +{
11245 + __list_del(entry->prev, entry->next);
11246 + entry->next = LIST_POISON1;
11247 + entry->prev = LIST_POISON2;
11248 +}
11249 +#endif
11250 +
11251 +#define DWC_LIST_REMOVE(link) do { \
11252 + (link)->next->prev = (link)->prev; \
11253 + (link)->prev->next = (link)->next; \
11254 +} while (0)
11255 +
11256 +#define DWC_LIST_REMOVE_INIT(link) do { \
11257 + DWC_LIST_REMOVE(link); \
11258 + DWC_LIST_INIT(link); \
11259 +} while (0)
11260 +
11261 +#define DWC_LIST_MOVE_HEAD(list, link) do { \
11262 + DWC_LIST_REMOVE(link); \
11263 + DWC_LIST_INSERT_HEAD(list, link); \
11264 +} while (0)
11265 +
11266 +#define DWC_LIST_MOVE_TAIL(list, link) do { \
11267 + DWC_LIST_REMOVE(link); \
11268 + DWC_LIST_INSERT_TAIL(list, link); \
11269 +} while (0)
11270 +
11271 +#define DWC_LIST_FOREACH(var, list) \
11272 + for((var) = DWC_LIST_FIRST(list); \
11273 + (var) != DWC_LIST_END(list); \
11274 + (var) = DWC_LIST_NEXT(var))
11275 +
11276 +#define DWC_LIST_FOREACH_SAFE(var, var2, list) \
11277 + for((var) = DWC_LIST_FIRST(list), (var2) = DWC_LIST_NEXT(var); \
11278 + (var) != DWC_LIST_END(list); \
11279 + (var) = (var2), (var2) = DWC_LIST_NEXT(var2))
11280 +
11281 +#define DWC_LIST_FOREACH_REVERSE(var, list) \
11282 + for((var) = DWC_LIST_LAST(list); \
11283 + (var) != DWC_LIST_END(list); \
11284 + (var) = DWC_LIST_PREV(var))
11285 +
11286 +/*
11287 + * Singly-linked List definitions.
11288 + */
11289 +#define DWC_SLIST_HEAD(name, type) \
11290 +struct name { \
11291 + struct type *slh_first; /* first element */ \
11292 +}
11293 +
11294 +#define DWC_SLIST_HEAD_INITIALIZER(head) \
11295 + { NULL }
11296 +
11297 +#define DWC_SLIST_ENTRY(type) \
11298 +struct { \
11299 + struct type *sle_next; /* next element */ \
11300 +}
11301 +
11302 +/*
11303 + * Singly-linked List access methods.
11304 + */
11305 +#define DWC_SLIST_FIRST(head) ((head)->slh_first)
11306 +#define DWC_SLIST_END(head) NULL
11307 +#define DWC_SLIST_EMPTY(head) (SLIST_FIRST(head) == SLIST_END(head))
11308 +#define DWC_SLIST_NEXT(elm, field) ((elm)->field.sle_next)
11309 +
11310 +#define DWC_SLIST_FOREACH(var, head, field) \
11311 + for((var) = SLIST_FIRST(head); \
11312 + (var) != SLIST_END(head); \
11313 + (var) = SLIST_NEXT(var, field))
11314 +
11315 +#define DWC_SLIST_FOREACH_PREVPTR(var, varp, head, field) \
11316 + for((varp) = &SLIST_FIRST((head)); \
11317 + ((var) = *(varp)) != SLIST_END(head); \
11318 + (varp) = &SLIST_NEXT((var), field))
11319 +
11320 +/*
11321 + * Singly-linked List functions.
11322 + */
11323 +#define DWC_SLIST_INIT(head) { \
11324 + SLIST_FIRST(head) = SLIST_END(head); \
11325 +}
11326 +
11327 +#define DWC_SLIST_INSERT_AFTER(slistelm, elm, field) do { \
11328 + (elm)->field.sle_next = (slistelm)->field.sle_next; \
11329 + (slistelm)->field.sle_next = (elm); \
11330 +} while (0)
11331 +
11332 +#define DWC_SLIST_INSERT_HEAD(head, elm, field) do { \
11333 + (elm)->field.sle_next = (head)->slh_first; \
11334 + (head)->slh_first = (elm); \
11335 +} while (0)
11336 +
11337 +#define DWC_SLIST_REMOVE_NEXT(head, elm, field) do { \
11338 + (elm)->field.sle_next = (elm)->field.sle_next->field.sle_next; \
11339 +} while (0)
11340 +
11341 +#define DWC_SLIST_REMOVE_HEAD(head, field) do { \
11342 + (head)->slh_first = (head)->slh_first->field.sle_next; \
11343 +} while (0)
11344 +
11345 +#define DWC_SLIST_REMOVE(head, elm, type, field) do { \
11346 + if ((head)->slh_first == (elm)) { \
11347 + SLIST_REMOVE_HEAD((head), field); \
11348 + } \
11349 + else { \
11350 + struct type *curelm = (head)->slh_first; \
11351 + while( curelm->field.sle_next != (elm) ) \
11352 + curelm = curelm->field.sle_next; \
11353 + curelm->field.sle_next = \
11354 + curelm->field.sle_next->field.sle_next; \
11355 + } \
11356 +} while (0)
11357 +
11358 +/*
11359 + * Simple queue definitions.
11360 + */
11361 +#define DWC_SIMPLEQ_HEAD(name, type) \
11362 +struct name { \
11363 + struct type *sqh_first; /* first element */ \
11364 + struct type **sqh_last; /* addr of last next element */ \
11365 +}
11366 +
11367 +#define DWC_SIMPLEQ_HEAD_INITIALIZER(head) \
11368 + { NULL, &(head).sqh_first }
11369 +
11370 +#define DWC_SIMPLEQ_ENTRY(type) \
11371 +struct { \
11372 + struct type *sqe_next; /* next element */ \
11373 +}
11374 +
11375 +/*
11376 + * Simple queue access methods.
11377 + */
11378 +#define DWC_SIMPLEQ_FIRST(head) ((head)->sqh_first)
11379 +#define DWC_SIMPLEQ_END(head) NULL
11380 +#define DWC_SIMPLEQ_EMPTY(head) (SIMPLEQ_FIRST(head) == SIMPLEQ_END(head))
11381 +#define DWC_SIMPLEQ_NEXT(elm, field) ((elm)->field.sqe_next)
11382 +
11383 +#define DWC_SIMPLEQ_FOREACH(var, head, field) \
11384 + for((var) = SIMPLEQ_FIRST(head); \
11385 + (var) != SIMPLEQ_END(head); \
11386 + (var) = SIMPLEQ_NEXT(var, field))
11387 +
11388 +/*
11389 + * Simple queue functions.
11390 + */
11391 +#define DWC_SIMPLEQ_INIT(head) do { \
11392 + (head)->sqh_first = NULL; \
11393 + (head)->sqh_last = &(head)->sqh_first; \
11394 +} while (0)
11395 +
11396 +#define DWC_SIMPLEQ_INSERT_HEAD(head, elm, field) do { \
11397 + if (((elm)->field.sqe_next = (head)->sqh_first) == NULL) \
11398 + (head)->sqh_last = &(elm)->field.sqe_next; \
11399 + (head)->sqh_first = (elm); \
11400 +} while (0)
11401 +
11402 +#define DWC_SIMPLEQ_INSERT_TAIL(head, elm, field) do { \
11403 + (elm)->field.sqe_next = NULL; \
11404 + *(head)->sqh_last = (elm); \
11405 + (head)->sqh_last = &(elm)->field.sqe_next; \
11406 +} while (0)
11407 +
11408 +#define DWC_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \
11409 + if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\
11410 + (head)->sqh_last = &(elm)->field.sqe_next; \
11411 + (listelm)->field.sqe_next = (elm); \
11412 +} while (0)
11413 +
11414 +#define DWC_SIMPLEQ_REMOVE_HEAD(head, field) do { \
11415 + if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \
11416 + (head)->sqh_last = &(head)->sqh_first; \
11417 +} while (0)
11418 +
11419 +/*
11420 + * Tail queue definitions.
11421 + */
11422 +#define DWC_TAILQ_HEAD(name, type) \
11423 +struct name { \
11424 + struct type *tqh_first; /* first element */ \
11425 + struct type **tqh_last; /* addr of last next element */ \
11426 +}
11427 +
11428 +#define DWC_TAILQ_HEAD_INITIALIZER(head) \
11429 + { NULL, &(head).tqh_first }
11430 +
11431 +#define DWC_TAILQ_ENTRY(type) \
11432 +struct { \
11433 + struct type *tqe_next; /* next element */ \
11434 + struct type **tqe_prev; /* address of previous next element */ \
11435 +}
11436 +
11437 +/*
11438 + * tail queue access methods
11439 + */
11440 +#define DWC_TAILQ_FIRST(head) ((head)->tqh_first)
11441 +#define DWC_TAILQ_END(head) NULL
11442 +#define DWC_TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
11443 +#define DWC_TAILQ_LAST(head, headname) \
11444 + (*(((struct headname *)((head)->tqh_last))->tqh_last))
11445 +/* XXX */
11446 +#define DWC_TAILQ_PREV(elm, headname, field) \
11447 + (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
11448 +#define DWC_TAILQ_EMPTY(head) \
11449 + (DWC_TAILQ_FIRST(head) == DWC_TAILQ_END(head))
11450 +
11451 +#define DWC_TAILQ_FOREACH(var, head, field) \
11452 + for ((var) = DWC_TAILQ_FIRST(head); \
11453 + (var) != DWC_TAILQ_END(head); \
11454 + (var) = DWC_TAILQ_NEXT(var, field))
11455 +
11456 +#define DWC_TAILQ_FOREACH_REVERSE(var, head, headname, field) \
11457 + for ((var) = DWC_TAILQ_LAST(head, headname); \
11458 + (var) != DWC_TAILQ_END(head); \
11459 + (var) = DWC_TAILQ_PREV(var, headname, field))
11460 +
11461 +/*
11462 + * Tail queue functions.
11463 + */
11464 +#define DWC_TAILQ_INIT(head) do { \
11465 + (head)->tqh_first = NULL; \
11466 + (head)->tqh_last = &(head)->tqh_first; \
11467 +} while (0)
11468 +
11469 +#define DWC_TAILQ_INSERT_HEAD(head, elm, field) do { \
11470 + if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \
11471 + (head)->tqh_first->field.tqe_prev = \
11472 + &(elm)->field.tqe_next; \
11473 + else \
11474 + (head)->tqh_last = &(elm)->field.tqe_next; \
11475 + (head)->tqh_first = (elm); \
11476 + (elm)->field.tqe_prev = &(head)->tqh_first; \
11477 +} while (0)
11478 +
11479 +#define DWC_TAILQ_INSERT_TAIL(head, elm, field) do { \
11480 + (elm)->field.tqe_next = NULL; \
11481 + (elm)->field.tqe_prev = (head)->tqh_last; \
11482 + *(head)->tqh_last = (elm); \
11483 + (head)->tqh_last = &(elm)->field.tqe_next; \
11484 +} while (0)
11485 +
11486 +#define DWC_TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \
11487 + if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\
11488 + (elm)->field.tqe_next->field.tqe_prev = \
11489 + &(elm)->field.tqe_next; \
11490 + else \
11491 + (head)->tqh_last = &(elm)->field.tqe_next; \
11492 + (listelm)->field.tqe_next = (elm); \
11493 + (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \
11494 +} while (0)
11495 +
11496 +#define DWC_TAILQ_INSERT_BEFORE(listelm, elm, field) do { \
11497 + (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \
11498 + (elm)->field.tqe_next = (listelm); \
11499 + *(listelm)->field.tqe_prev = (elm); \
11500 + (listelm)->field.tqe_prev = &(elm)->field.tqe_next; \
11501 +} while (0)
11502 +
11503 +#define DWC_TAILQ_REMOVE(head, elm, field) do { \
11504 + if (((elm)->field.tqe_next) != NULL) \
11505 + (elm)->field.tqe_next->field.tqe_prev = \
11506 + (elm)->field.tqe_prev; \
11507 + else \
11508 + (head)->tqh_last = (elm)->field.tqe_prev; \
11509 + *(elm)->field.tqe_prev = (elm)->field.tqe_next; \
11510 +} while (0)
11511 +
11512 +#define DWC_TAILQ_REPLACE(head, elm, elm2, field) do { \
11513 + if (((elm2)->field.tqe_next = (elm)->field.tqe_next) != NULL) \
11514 + (elm2)->field.tqe_next->field.tqe_prev = \
11515 + &(elm2)->field.tqe_next; \
11516 + else \
11517 + (head)->tqh_last = &(elm2)->field.tqe_next; \
11518 + (elm2)->field.tqe_prev = (elm)->field.tqe_prev; \
11519 + *(elm2)->field.tqe_prev = (elm2); \
11520 +} while (0)
11521 +
11522 +/*
11523 + * Circular queue definitions.
11524 + */
11525 +#define DWC_CIRCLEQ_HEAD(name, type) \
11526 +struct name { \
11527 + struct type *cqh_first; /* first element */ \
11528 + struct type *cqh_last; /* last element */ \
11529 +}
11530 +
11531 +#define DWC_CIRCLEQ_HEAD_INITIALIZER(head) \
11532 + { DWC_CIRCLEQ_END(&head), DWC_CIRCLEQ_END(&head) }
11533 +
11534 +#define DWC_CIRCLEQ_ENTRY(type) \
11535 +struct { \
11536 + struct type *cqe_next; /* next element */ \
11537 + struct type *cqe_prev; /* previous element */ \
11538 +}
11539 +
11540 +/*
11541 + * Circular queue access methods
11542 + */
11543 +#define DWC_CIRCLEQ_FIRST(head) ((head)->cqh_first)
11544 +#define DWC_CIRCLEQ_LAST(head) ((head)->cqh_last)
11545 +#define DWC_CIRCLEQ_END(head) ((void *)(head))
11546 +#define DWC_CIRCLEQ_NEXT(elm, field) ((elm)->field.cqe_next)
11547 +#define DWC_CIRCLEQ_PREV(elm, field) ((elm)->field.cqe_prev)
11548 +#define DWC_CIRCLEQ_EMPTY(head) \
11549 + (DWC_CIRCLEQ_FIRST(head) == DWC_CIRCLEQ_END(head))
11550 +
11551 +#define DWC_CIRCLEQ_EMPTY_ENTRY(elm, field) (((elm)->field.cqe_next == NULL) && ((elm)->field.cqe_prev == NULL))
11552 +
11553 +#define DWC_CIRCLEQ_FOREACH(var, head, field) \
11554 + for((var) = DWC_CIRCLEQ_FIRST(head); \
11555 + (var) != DWC_CIRCLEQ_END(head); \
11556 + (var) = DWC_CIRCLEQ_NEXT(var, field))
11557 +
11558 +#define DWC_CIRCLEQ_FOREACH_SAFE(var, var2, head, field) \
11559 + for((var) = DWC_CIRCLEQ_FIRST(head), var2 = DWC_CIRCLEQ_NEXT(var, field); \
11560 + (var) != DWC_CIRCLEQ_END(head); \
11561 + (var) = var2, var2 = DWC_CIRCLEQ_NEXT(var, field))
11562 +
11563 +#define DWC_CIRCLEQ_FOREACH_REVERSE(var, head, field) \
11564 + for((var) = DWC_CIRCLEQ_LAST(head); \
11565 + (var) != DWC_CIRCLEQ_END(head); \
11566 + (var) = DWC_CIRCLEQ_PREV(var, field))
11567 +
11568 +/*
11569 + * Circular queue functions.
11570 + */
11571 +#define DWC_CIRCLEQ_INIT(head) do { \
11572 + (head)->cqh_first = DWC_CIRCLEQ_END(head); \
11573 + (head)->cqh_last = DWC_CIRCLEQ_END(head); \
11574 +} while (0)
11575 +
11576 +#define DWC_CIRCLEQ_INIT_ENTRY(elm, field) do { \
11577 + (elm)->field.cqe_next = NULL; \
11578 + (elm)->field.cqe_prev = NULL; \
11579 +} while (0)
11580 +
11581 +#define DWC_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \
11582 + (elm)->field.cqe_next = (listelm)->field.cqe_next; \
11583 + (elm)->field.cqe_prev = (listelm); \
11584 + if ((listelm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \
11585 + (head)->cqh_last = (elm); \
11586 + else \
11587 + (listelm)->field.cqe_next->field.cqe_prev = (elm); \
11588 + (listelm)->field.cqe_next = (elm); \
11589 +} while (0)
11590 +
11591 +#define DWC_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \
11592 + (elm)->field.cqe_next = (listelm); \
11593 + (elm)->field.cqe_prev = (listelm)->field.cqe_prev; \
11594 + if ((listelm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \
11595 + (head)->cqh_first = (elm); \
11596 + else \
11597 + (listelm)->field.cqe_prev->field.cqe_next = (elm); \
11598 + (listelm)->field.cqe_prev = (elm); \
11599 +} while (0)
11600 +
11601 +#define DWC_CIRCLEQ_INSERT_HEAD(head, elm, field) do { \
11602 + (elm)->field.cqe_next = (head)->cqh_first; \
11603 + (elm)->field.cqe_prev = DWC_CIRCLEQ_END(head); \
11604 + if ((head)->cqh_last == DWC_CIRCLEQ_END(head)) \
11605 + (head)->cqh_last = (elm); \
11606 + else \
11607 + (head)->cqh_first->field.cqe_prev = (elm); \
11608 + (head)->cqh_first = (elm); \
11609 +} while (0)
11610 +
11611 +#define DWC_CIRCLEQ_INSERT_TAIL(head, elm, field) do { \
11612 + (elm)->field.cqe_next = DWC_CIRCLEQ_END(head); \
11613 + (elm)->field.cqe_prev = (head)->cqh_last; \
11614 + if ((head)->cqh_first == DWC_CIRCLEQ_END(head)) \
11615 + (head)->cqh_first = (elm); \
11616 + else \
11617 + (head)->cqh_last->field.cqe_next = (elm); \
11618 + (head)->cqh_last = (elm); \
11619 +} while (0)
11620 +
11621 +#define DWC_CIRCLEQ_REMOVE(head, elm, field) do { \
11622 + if ((elm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \
11623 + (head)->cqh_last = (elm)->field.cqe_prev; \
11624 + else \
11625 + (elm)->field.cqe_next->field.cqe_prev = \
11626 + (elm)->field.cqe_prev; \
11627 + if ((elm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \
11628 + (head)->cqh_first = (elm)->field.cqe_next; \
11629 + else \
11630 + (elm)->field.cqe_prev->field.cqe_next = \
11631 + (elm)->field.cqe_next; \
11632 +} while (0)
11633 +
11634 +#define DWC_CIRCLEQ_REMOVE_INIT(head, elm, field) do { \
11635 + DWC_CIRCLEQ_REMOVE(head, elm, field); \
11636 + DWC_CIRCLEQ_INIT_ENTRY(elm, field); \
11637 +} while (0)
11638 +
11639 +#define DWC_CIRCLEQ_REPLACE(head, elm, elm2, field) do { \
11640 + if (((elm2)->field.cqe_next = (elm)->field.cqe_next) == \
11641 + DWC_CIRCLEQ_END(head)) \
11642 + (head).cqh_last = (elm2); \
11643 + else \
11644 + (elm2)->field.cqe_next->field.cqe_prev = (elm2); \
11645 + if (((elm2)->field.cqe_prev = (elm)->field.cqe_prev) == \
11646 + DWC_CIRCLEQ_END(head)) \
11647 + (head).cqh_first = (elm2); \
11648 + else \
11649 + (elm2)->field.cqe_prev->field.cqe_next = (elm2); \
11650 +} while (0)
11651 +
11652 +#ifdef __cplusplus
11653 +}
11654 +#endif
11655 +
11656 +#endif /* _DWC_LIST_H_ */
11657 --- /dev/null
11658 +++ b/drivers/usb/host/dwc_common_port/dwc_mem.c
11659 @@ -0,0 +1,245 @@
11660 +/* Memory Debugging */
11661 +#ifdef DWC_DEBUG_MEMORY
11662 +
11663 +#include "dwc_os.h"
11664 +#include "dwc_list.h"
11665 +
11666 +struct allocation {
11667 + void *addr;
11668 + void *ctx;
11669 + char *func;
11670 + int line;
11671 + uint32_t size;
11672 + int dma;
11673 + DWC_CIRCLEQ_ENTRY(allocation) entry;
11674 +};
11675 +
11676 +DWC_CIRCLEQ_HEAD(allocation_queue, allocation);
11677 +
11678 +struct allocation_manager {
11679 + void *mem_ctx;
11680 + struct allocation_queue allocations;
11681 +
11682 + /* statistics */
11683 + int num;
11684 + int num_freed;
11685 + int num_active;
11686 + uint32_t total;
11687 + uint32_t cur;
11688 + uint32_t max;
11689 +};
11690 +
11691 +static struct allocation_manager *manager = NULL;
11692 +
11693 +static int add_allocation(void *ctx, uint32_t size, char const *func, int line, void *addr,
11694 + int dma)
11695 +{
11696 + struct allocation *a;
11697 +
11698 + DWC_ASSERT(manager != NULL, "manager not allocated");
11699 +
11700 + a = __DWC_ALLOC_ATOMIC(manager->mem_ctx, sizeof(*a));
11701 + if (!a) {
11702 + return -DWC_E_NO_MEMORY;
11703 + }
11704 +
11705 + a->func = __DWC_ALLOC_ATOMIC(manager->mem_ctx, DWC_STRLEN(func) + 1);
11706 + if (!a->func) {
11707 + __DWC_FREE(manager->mem_ctx, a);
11708 + return -DWC_E_NO_MEMORY;
11709 + }
11710 +
11711 + DWC_MEMCPY(a->func, func, DWC_STRLEN(func) + 1);
11712 + a->addr = addr;
11713 + a->ctx = ctx;
11714 + a->line = line;
11715 + a->size = size;
11716 + a->dma = dma;
11717 + DWC_CIRCLEQ_INSERT_TAIL(&manager->allocations, a, entry);
11718 +
11719 + /* Update stats */
11720 + manager->num++;
11721 + manager->num_active++;
11722 + manager->total += size;
11723 + manager->cur += size;
11724 +
11725 + if (manager->max < manager->cur) {
11726 + manager->max = manager->cur;
11727 + }
11728 +
11729 + return 0;
11730 +}
11731 +
11732 +static struct allocation *find_allocation(void *ctx, void *addr)
11733 +{
11734 + struct allocation *a;
11735 +
11736 + DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
11737 + if (a->ctx == ctx && a->addr == addr) {
11738 + return a;
11739 + }
11740 + }
11741 +
11742 + return NULL;
11743 +}
11744 +
11745 +static void free_allocation(void *ctx, void *addr, char const *func, int line)
11746 +{
11747 + struct allocation *a = find_allocation(ctx, addr);
11748 +
11749 + if (!a) {
11750 + DWC_ASSERT(0,
11751 + "Free of address %p that was never allocated or already freed %s:%d",
11752 + addr, func, line);
11753 + return;
11754 + }
11755 +
11756 + DWC_CIRCLEQ_REMOVE(&manager->allocations, a, entry);
11757 +
11758 + manager->num_active--;
11759 + manager->num_freed++;
11760 + manager->cur -= a->size;
11761 + __DWC_FREE(manager->mem_ctx, a->func);
11762 + __DWC_FREE(manager->mem_ctx, a);
11763 +}
11764 +
11765 +int dwc_memory_debug_start(void *mem_ctx)
11766 +{
11767 + DWC_ASSERT(manager == NULL, "Memory debugging has already started\n");
11768 +
11769 + if (manager) {
11770 + return -DWC_E_BUSY;
11771 + }
11772 +
11773 + manager = __DWC_ALLOC(mem_ctx, sizeof(*manager));
11774 + if (!manager) {
11775 + return -DWC_E_NO_MEMORY;
11776 + }
11777 +
11778 + DWC_CIRCLEQ_INIT(&manager->allocations);
11779 + manager->mem_ctx = mem_ctx;
11780 + manager->num = 0;
11781 + manager->num_freed = 0;
11782 + manager->num_active = 0;
11783 + manager->total = 0;
11784 + manager->cur = 0;
11785 + manager->max = 0;
11786 +
11787 + return 0;
11788 +}
11789 +
11790 +void dwc_memory_debug_stop(void)
11791 +{
11792 + struct allocation *a;
11793 +
11794 + dwc_memory_debug_report();
11795 +
11796 + DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
11797 + DWC_ERROR("Memory leaked from %s:%d\n", a->func, a->line);
11798 + free_allocation(a->ctx, a->addr, NULL, -1);
11799 + }
11800 +
11801 + __DWC_FREE(manager->mem_ctx, manager);
11802 +}
11803 +
11804 +void dwc_memory_debug_report(void)
11805 +{
11806 + struct allocation *a;
11807 +
11808 + DWC_PRINTF("\n\n\n----------------- Memory Debugging Report -----------------\n\n");
11809 + DWC_PRINTF("Num Allocations = %d\n", manager->num);
11810 + DWC_PRINTF("Freed = %d\n", manager->num_freed);
11811 + DWC_PRINTF("Active = %d\n", manager->num_active);
11812 + DWC_PRINTF("Current Memory Used = %d\n", manager->cur);
11813 + DWC_PRINTF("Total Memory Used = %d\n", manager->total);
11814 + DWC_PRINTF("Maximum Memory Used at Once = %d\n", manager->max);
11815 + DWC_PRINTF("Unfreed allocations:\n");
11816 +
11817 + DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
11818 + DWC_PRINTF(" addr=%p, size=%d from %s:%d, DMA=%d\n",
11819 + a->addr, a->size, a->func, a->line, a->dma);
11820 + }
11821 +}
11822 +
11823 +/* The replacement functions */
11824 +void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line)
11825 +{
11826 + void *addr = __DWC_ALLOC(mem_ctx, size);
11827 +
11828 + if (!addr) {
11829 + return NULL;
11830 + }
11831 +
11832 + if (add_allocation(mem_ctx, size, func, line, addr, 0)) {
11833 + __DWC_FREE(mem_ctx, addr);
11834 + return NULL;
11835 + }
11836 +
11837 + return addr;
11838 +}
11839 +
11840 +void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func,
11841 + int line)
11842 +{
11843 + void *addr = __DWC_ALLOC_ATOMIC(mem_ctx, size);
11844 +
11845 + if (!addr) {
11846 + return NULL;
11847 + }
11848 +
11849 + if (add_allocation(mem_ctx, size, func, line, addr, 0)) {
11850 + __DWC_FREE(mem_ctx, addr);
11851 + return NULL;
11852 + }
11853 +
11854 + return addr;
11855 +}
11856 +
11857 +void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line)
11858 +{
11859 + free_allocation(mem_ctx, addr, func, line);
11860 + __DWC_FREE(mem_ctx, addr);
11861 +}
11862 +
11863 +void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
11864 + char const *func, int line)
11865 +{
11866 + void *addr = __DWC_DMA_ALLOC(dma_ctx, size, dma_addr);
11867 +
11868 + if (!addr) {
11869 + return NULL;
11870 + }
11871 +
11872 + if (add_allocation(dma_ctx, size, func, line, addr, 1)) {
11873 + __DWC_DMA_FREE(dma_ctx, size, addr, *dma_addr);
11874 + return NULL;
11875 + }
11876 +
11877 + return addr;
11878 +}
11879 +
11880 +void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size,
11881 + dwc_dma_t *dma_addr, char const *func, int line)
11882 +{
11883 + void *addr = __DWC_DMA_ALLOC_ATOMIC(dma_ctx, size, dma_addr);
11884 +
11885 + if (!addr) {
11886 + return NULL;
11887 + }
11888 +
11889 + if (add_allocation(dma_ctx, size, func, line, addr, 1)) {
11890 + __DWC_DMA_FREE(dma_ctx, size, addr, *dma_addr);
11891 + return NULL;
11892 + }
11893 +
11894 + return addr;
11895 +}
11896 +
11897 +void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr,
11898 + dwc_dma_t dma_addr, char const *func, int line)
11899 +{
11900 + free_allocation(dma_ctx, virt_addr, func, line);
11901 + __DWC_DMA_FREE(dma_ctx, size, virt_addr, dma_addr);
11902 +}
11903 +
11904 +#endif /* DWC_DEBUG_MEMORY */
11905 --- /dev/null
11906 +++ b/drivers/usb/host/dwc_common_port/dwc_modpow.c
11907 @@ -0,0 +1,636 @@
11908 +/* Bignum routines adapted from PUTTY sources. PuTTY copyright notice follows.
11909 + *
11910 + * PuTTY is copyright 1997-2007 Simon Tatham.
11911 + *
11912 + * Portions copyright Robert de Bath, Joris van Rantwijk, Delian
11913 + * Delchev, Andreas Schultz, Jeroen Massar, Wez Furlong, Nicolas Barry,
11914 + * Justin Bradford, Ben Harris, Malcolm Smith, Ahmad Khalifa, Markus
11915 + * Kuhn, and CORE SDI S.A.
11916 + *
11917 + * Permission is hereby granted, free of charge, to any person
11918 + * obtaining a copy of this software and associated documentation files
11919 + * (the "Software"), to deal in the Software without restriction,
11920 + * including without limitation the rights to use, copy, modify, merge,
11921 + * publish, distribute, sublicense, and/or sell copies of the Software,
11922 + * and to permit persons to whom the Software is furnished to do so,
11923 + * subject to the following conditions:
11924 + *
11925 + * The above copyright notice and this permission notice shall be
11926 + * included in all copies or substantial portions of the Software.
11927 +
11928 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11929 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
11930 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
11931 + * NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE
11932 + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
11933 + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
11934 + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
11935 + *
11936 + */
11937 +#ifdef DWC_CRYPTOLIB
11938 +
11939 +#ifndef CONFIG_MACH_IPMATE
11940 +
11941 +#include "dwc_modpow.h"
11942 +
11943 +#define BIGNUM_INT_MASK 0xFFFFFFFFUL
11944 +#define BIGNUM_TOP_BIT 0x80000000UL
11945 +#define BIGNUM_INT_BITS 32
11946 +
11947 +
11948 +static void *snmalloc(void *mem_ctx, size_t n, size_t size)
11949 +{
11950 + void *p;
11951 + size *= n;
11952 + if (size == 0) size = 1;
11953 + p = dwc_alloc(mem_ctx, size);
11954 + return p;
11955 +}
11956 +
11957 +#define snewn(ctx, n, type) ((type *)snmalloc((ctx), (n), sizeof(type)))
11958 +#define sfree dwc_free
11959 +
11960 +/*
11961 + * Usage notes:
11962 + * * Do not call the DIVMOD_WORD macro with expressions such as array
11963 + * subscripts, as some implementations object to this (see below).
11964 + * * Note that none of the division methods below will cope if the
11965 + * quotient won't fit into BIGNUM_INT_BITS. Callers should be careful
11966 + * to avoid this case.
11967 + * If this condition occurs, in the case of the x86 DIV instruction,
11968 + * an overflow exception will occur, which (according to a correspondent)
11969 + * will manifest on Windows as something like
11970 + * 0xC0000095: Integer overflow
11971 + * The C variant won't give the right answer, either.
11972 + */
11973 +
11974 +#define MUL_WORD(w1, w2) ((BignumDblInt)w1 * w2)
11975 +
11976 +#if defined __GNUC__ && defined __i386__
11977 +#define DIVMOD_WORD(q, r, hi, lo, w) \
11978 + __asm__("div %2" : \
11979 + "=d" (r), "=a" (q) : \
11980 + "r" (w), "d" (hi), "a" (lo))
11981 +#else
11982 +#define DIVMOD_WORD(q, r, hi, lo, w) do { \
11983 + BignumDblInt n = (((BignumDblInt)hi) << BIGNUM_INT_BITS) | lo; \
11984 + q = n / w; \
11985 + r = n % w; \
11986 +} while (0)
11987 +#endif
11988 +
11989 +// q = n / w;
11990 +// r = n % w;
11991 +
11992 +#define BIGNUM_INT_BYTES (BIGNUM_INT_BITS / 8)
11993 +
11994 +#define BIGNUM_INTERNAL
11995 +
11996 +static Bignum newbn(void *mem_ctx, int length)
11997 +{
11998 + Bignum b = snewn(mem_ctx, length + 1, BignumInt);
11999 + //if (!b)
12000 + //abort(); /* FIXME */
12001 + DWC_MEMSET(b, 0, (length + 1) * sizeof(*b));
12002 + b[0] = length;
12003 + return b;
12004 +}
12005 +
12006 +void freebn(void *mem_ctx, Bignum b)
12007 +{
12008 + /*
12009 + * Burn the evidence, just in case.
12010 + */
12011 + DWC_MEMSET(b, 0, sizeof(b[0]) * (b[0] + 1));
12012 + sfree(mem_ctx, b);
12013 +}
12014 +
12015 +/*
12016 + * Compute c = a * b.
12017 + * Input is in the first len words of a and b.
12018 + * Result is returned in the first 2*len words of c.
12019 + */
12020 +static void internal_mul(BignumInt *a, BignumInt *b,
12021 + BignumInt *c, int len)
12022 +{
12023 + int i, j;
12024 + BignumDblInt t;
12025 +
12026 + for (j = 0; j < 2 * len; j++)
12027 + c[j] = 0;
12028 +
12029 + for (i = len - 1; i >= 0; i--) {
12030 + t = 0;
12031 + for (j = len - 1; j >= 0; j--) {
12032 + t += MUL_WORD(a[i], (BignumDblInt) b[j]);
12033 + t += (BignumDblInt) c[i + j + 1];
12034 + c[i + j + 1] = (BignumInt) t;
12035 + t = t >> BIGNUM_INT_BITS;
12036 + }
12037 + c[i] = (BignumInt) t;
12038 + }
12039 +}
12040 +
12041 +static void internal_add_shifted(BignumInt *number,
12042 + unsigned n, int shift)
12043 +{
12044 + int word = 1 + (shift / BIGNUM_INT_BITS);
12045 + int bshift = shift % BIGNUM_INT_BITS;
12046 + BignumDblInt addend;
12047 +
12048 + addend = (BignumDblInt)n << bshift;
12049 +
12050 + while (addend) {
12051 + addend += number[word];
12052 + number[word] = (BignumInt) addend & BIGNUM_INT_MASK;
12053 + addend >>= BIGNUM_INT_BITS;
12054 + word++;
12055 + }
12056 +}
12057 +
12058 +/*
12059 + * Compute a = a % m.
12060 + * Input in first alen words of a and first mlen words of m.
12061 + * Output in first alen words of a
12062 + * (of which first alen-mlen words will be zero).
12063 + * The MSW of m MUST have its high bit set.
12064 + * Quotient is accumulated in the `quotient' array, which is a Bignum
12065 + * rather than the internal bigendian format. Quotient parts are shifted
12066 + * left by `qshift' before adding into quot.
12067 + */
12068 +static void internal_mod(BignumInt *a, int alen,
12069 + BignumInt *m, int mlen,
12070 + BignumInt *quot, int qshift)
12071 +{
12072 + BignumInt m0, m1;
12073 + unsigned int h;
12074 + int i, k;
12075 +
12076 + m0 = m[0];
12077 + if (mlen > 1)
12078 + m1 = m[1];
12079 + else
12080 + m1 = 0;
12081 +
12082 + for (i = 0; i <= alen - mlen; i++) {
12083 + BignumDblInt t;
12084 + unsigned int q, r, c, ai1;
12085 +
12086 + if (i == 0) {
12087 + h = 0;
12088 + } else {
12089 + h = a[i - 1];
12090 + a[i - 1] = 0;
12091 + }
12092 +
12093 + if (i == alen - 1)
12094 + ai1 = 0;
12095 + else
12096 + ai1 = a[i + 1];
12097 +
12098 + /* Find q = h:a[i] / m0 */
12099 + if (h >= m0) {
12100 + /*
12101 + * Special case.
12102 + *
12103 + * To illustrate it, suppose a BignumInt is 8 bits, and
12104 + * we are dividing (say) A1:23:45:67 by A1:B2:C3. Then
12105 + * our initial division will be 0xA123 / 0xA1, which
12106 + * will give a quotient of 0x100 and a divide overflow.
12107 + * However, the invariants in this division algorithm
12108 + * are not violated, since the full number A1:23:... is
12109 + * _less_ than the quotient prefix A1:B2:... and so the
12110 + * following correction loop would have sorted it out.
12111 + *
12112 + * In this situation we set q to be the largest
12113 + * quotient we _can_ stomach (0xFF, of course).
12114 + */
12115 + q = BIGNUM_INT_MASK;
12116 + } else {
12117 + /* Macro doesn't want an array subscript expression passed
12118 + * into it (see definition), so use a temporary. */
12119 + BignumInt tmplo = a[i];
12120 + DIVMOD_WORD(q, r, h, tmplo, m0);
12121 +
12122 + /* Refine our estimate of q by looking at
12123 + h:a[i]:a[i+1] / m0:m1 */
12124 + t = MUL_WORD(m1, q);
12125 + if (t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) {
12126 + q--;
12127 + t -= m1;
12128 + r = (r + m0) & BIGNUM_INT_MASK; /* overflow? */
12129 + if (r >= (BignumDblInt) m0 &&
12130 + t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) q--;
12131 + }
12132 + }
12133 +
12134 + /* Subtract q * m from a[i...] */
12135 + c = 0;
12136 + for (k = mlen - 1; k >= 0; k--) {
12137 + t = MUL_WORD(q, m[k]);
12138 + t += c;
12139 + c = (unsigned)(t >> BIGNUM_INT_BITS);
12140 + if ((BignumInt) t > a[i + k])
12141 + c++;
12142 + a[i + k] -= (BignumInt) t;
12143 + }
12144 +
12145 + /* Add back m in case of borrow */
12146 + if (c != h) {
12147 + t = 0;
12148 + for (k = mlen - 1; k >= 0; k--) {
12149 + t += m[k];
12150 + t += a[i + k];
12151 + a[i + k] = (BignumInt) t;
12152 + t = t >> BIGNUM_INT_BITS;
12153 + }
12154 + q--;
12155 + }
12156 + if (quot)
12157 + internal_add_shifted(quot, q, qshift + BIGNUM_INT_BITS * (alen - mlen - i));
12158 + }
12159 +}
12160 +
12161 +/*
12162 + * Compute p % mod.
12163 + * The most significant word of mod MUST be non-zero.
12164 + * We assume that the result array is the same size as the mod array.
12165 + * We optionally write out a quotient if `quotient' is non-NULL.
12166 + * We can avoid writing out the result if `result' is NULL.
12167 + */
12168 +void bigdivmod(void *mem_ctx, Bignum p, Bignum mod, Bignum result, Bignum quotient)
12169 +{
12170 + BignumInt *n, *m;
12171 + int mshift;
12172 + int plen, mlen, i, j;
12173 +
12174 + /* Allocate m of size mlen, copy mod to m */
12175 + /* We use big endian internally */
12176 + mlen = mod[0];
12177 + m = snewn(mem_ctx, mlen, BignumInt);
12178 + //if (!m)
12179 + //abort(); /* FIXME */
12180 + for (j = 0; j < mlen; j++)
12181 + m[j] = mod[mod[0] - j];
12182 +
12183 + /* Shift m left to make msb bit set */
12184 + for (mshift = 0; mshift < BIGNUM_INT_BITS-1; mshift++)
12185 + if ((m[0] << mshift) & BIGNUM_TOP_BIT)
12186 + break;
12187 + if (mshift) {
12188 + for (i = 0; i < mlen - 1; i++)
12189 + m[i] = (m[i] << mshift) | (m[i + 1] >> (BIGNUM_INT_BITS - mshift));
12190 + m[mlen - 1] = m[mlen - 1] << mshift;
12191 + }
12192 +
12193 + plen = p[0];
12194 + /* Ensure plen > mlen */
12195 + if (plen <= mlen)
12196 + plen = mlen + 1;
12197 +
12198 + /* Allocate n of size plen, copy p to n */
12199 + n = snewn(mem_ctx, plen, BignumInt);
12200 + //if (!n)
12201 + //abort(); /* FIXME */
12202 + for (j = 0; j < plen; j++)
12203 + n[j] = 0;
12204 + for (j = 1; j <= (int)p[0]; j++)
12205 + n[plen - j] = p[j];
12206 +
12207 + /* Main computation */
12208 + internal_mod(n, plen, m, mlen, quotient, mshift);
12209 +
12210 + /* Fixup result in case the modulus was shifted */
12211 + if (mshift) {
12212 + for (i = plen - mlen - 1; i < plen - 1; i++)
12213 + n[i] = (n[i] << mshift) | (n[i + 1] >> (BIGNUM_INT_BITS - mshift));
12214 + n[plen - 1] = n[plen - 1] << mshift;
12215 + internal_mod(n, plen, m, mlen, quotient, 0);
12216 + for (i = plen - 1; i >= plen - mlen; i--)
12217 + n[i] = (n[i] >> mshift) | (n[i - 1] << (BIGNUM_INT_BITS - mshift));
12218 + }
12219 +
12220 + /* Copy result to buffer */
12221 + if (result) {
12222 + for (i = 1; i <= (int)result[0]; i++) {
12223 + int j = plen - i;
12224 + result[i] = j >= 0 ? n[j] : 0;
12225 + }
12226 + }
12227 +
12228 + /* Free temporary arrays */
12229 + for (i = 0; i < mlen; i++)
12230 + m[i] = 0;
12231 + sfree(mem_ctx, m);
12232 + for (i = 0; i < plen; i++)
12233 + n[i] = 0;
12234 + sfree(mem_ctx, n);
12235 +}
12236 +
12237 +/*
12238 + * Simple remainder.
12239 + */
12240 +Bignum bigmod(void *mem_ctx, Bignum a, Bignum b)
12241 +{
12242 + Bignum r = newbn(mem_ctx, b[0]);
12243 + bigdivmod(mem_ctx, a, b, r, NULL);
12244 + return r;
12245 +}
12246 +
12247 +/*
12248 + * Compute (base ^ exp) % mod.
12249 + */
12250 +Bignum dwc_modpow(void *mem_ctx, Bignum base_in, Bignum exp, Bignum mod)
12251 +{
12252 + BignumInt *a, *b, *n, *m;
12253 + int mshift;
12254 + int mlen, i, j;
12255 + Bignum base, result;
12256 +
12257 + /*
12258 + * The most significant word of mod needs to be non-zero. It
12259 + * should already be, but let's make sure.
12260 + */
12261 + //assert(mod[mod[0]] != 0);
12262 +
12263 + /*
12264 + * Make sure the base is smaller than the modulus, by reducing
12265 + * it modulo the modulus if not.
12266 + */
12267 + base = bigmod(mem_ctx, base_in, mod);
12268 +
12269 + /* Allocate m of size mlen, copy mod to m */
12270 + /* We use big endian internally */
12271 + mlen = mod[0];
12272 + m = snewn(mem_ctx, mlen, BignumInt);
12273 + //if (!m)
12274 + //abort(); /* FIXME */
12275 + for (j = 0; j < mlen; j++)
12276 + m[j] = mod[mod[0] - j];
12277 +
12278 + /* Shift m left to make msb bit set */
12279 + for (mshift = 0; mshift < BIGNUM_INT_BITS - 1; mshift++)
12280 + if ((m[0] << mshift) & BIGNUM_TOP_BIT)
12281 + break;
12282 + if (mshift) {
12283 + for (i = 0; i < mlen - 1; i++)
12284 + m[i] =
12285 + (m[i] << mshift) | (m[i + 1] >>
12286 + (BIGNUM_INT_BITS - mshift));
12287 + m[mlen - 1] = m[mlen - 1] << mshift;
12288 + }
12289 +
12290 + /* Allocate n of size mlen, copy base to n */
12291 + n = snewn(mem_ctx, mlen, BignumInt);
12292 + //if (!n)
12293 + //abort(); /* FIXME */
12294 + i = mlen - base[0];
12295 + for (j = 0; j < i; j++)
12296 + n[j] = 0;
12297 + for (j = 0; j < base[0]; j++)
12298 + n[i + j] = base[base[0] - j];
12299 +
12300 + /* Allocate a and b of size 2*mlen. Set a = 1 */
12301 + a = snewn(mem_ctx, 2 * mlen, BignumInt);
12302 + //if (!a)
12303 + //abort(); /* FIXME */
12304 + b = snewn(mem_ctx, 2 * mlen, BignumInt);
12305 + //if (!b)
12306 + //abort(); /* FIXME */
12307 + for (i = 0; i < 2 * mlen; i++)
12308 + a[i] = 0;
12309 + a[2 * mlen - 1] = 1;
12310 +
12311 + /* Skip leading zero bits of exp. */
12312 + i = 0;
12313 + j = BIGNUM_INT_BITS - 1;
12314 + while (i < exp[0] && (exp[exp[0] - i] & (1 << j)) == 0) {
12315 + j--;
12316 + if (j < 0) {
12317 + i++;
12318 + j = BIGNUM_INT_BITS - 1;
12319 + }
12320 + }
12321 +
12322 + /* Main computation */
12323 + while (i < exp[0]) {
12324 + while (j >= 0) {
12325 + internal_mul(a + mlen, a + mlen, b, mlen);
12326 + internal_mod(b, mlen * 2, m, mlen, NULL, 0);
12327 + if ((exp[exp[0] - i] & (1 << j)) != 0) {
12328 + internal_mul(b + mlen, n, a, mlen);
12329 + internal_mod(a, mlen * 2, m, mlen, NULL, 0);
12330 + } else {
12331 + BignumInt *t;
12332 + t = a;
12333 + a = b;
12334 + b = t;
12335 + }
12336 + j--;
12337 + }
12338 + i++;
12339 + j = BIGNUM_INT_BITS - 1;
12340 + }
12341 +
12342 + /* Fixup result in case the modulus was shifted */
12343 + if (mshift) {
12344 + for (i = mlen - 1; i < 2 * mlen - 1; i++)
12345 + a[i] =
12346 + (a[i] << mshift) | (a[i + 1] >>
12347 + (BIGNUM_INT_BITS - mshift));
12348 + a[2 * mlen - 1] = a[2 * mlen - 1] << mshift;
12349 + internal_mod(a, mlen * 2, m, mlen, NULL, 0);
12350 + for (i = 2 * mlen - 1; i >= mlen; i--)
12351 + a[i] =
12352 + (a[i] >> mshift) | (a[i - 1] <<
12353 + (BIGNUM_INT_BITS - mshift));
12354 + }
12355 +
12356 + /* Copy result to buffer */
12357 + result = newbn(mem_ctx, mod[0]);
12358 + for (i = 0; i < mlen; i++)
12359 + result[result[0] - i] = a[i + mlen];
12360 + while (result[0] > 1 && result[result[0]] == 0)
12361 + result[0]--;
12362 +
12363 + /* Free temporary arrays */
12364 + for (i = 0; i < 2 * mlen; i++)
12365 + a[i] = 0;
12366 + sfree(mem_ctx, a);
12367 + for (i = 0; i < 2 * mlen; i++)
12368 + b[i] = 0;
12369 + sfree(mem_ctx, b);
12370 + for (i = 0; i < mlen; i++)
12371 + m[i] = 0;
12372 + sfree(mem_ctx, m);
12373 + for (i = 0; i < mlen; i++)
12374 + n[i] = 0;
12375 + sfree(mem_ctx, n);
12376 +
12377 + freebn(mem_ctx, base);
12378 +
12379 + return result;
12380 +}
12381 +
12382 +
12383 +#ifdef UNITTEST
12384 +
12385 +static __u32 dh_p[] = {
12386 + 96,
12387 + 0xFFFFFFFF,
12388 + 0xFFFFFFFF,
12389 + 0xA93AD2CA,
12390 + 0x4B82D120,
12391 + 0xE0FD108E,
12392 + 0x43DB5BFC,
12393 + 0x74E5AB31,
12394 + 0x08E24FA0,
12395 + 0xBAD946E2,
12396 + 0x770988C0,
12397 + 0x7A615D6C,
12398 + 0xBBE11757,
12399 + 0x177B200C,
12400 + 0x521F2B18,
12401 + 0x3EC86A64,
12402 + 0xD8760273,
12403 + 0xD98A0864,
12404 + 0xF12FFA06,
12405 + 0x1AD2EE6B,
12406 + 0xCEE3D226,
12407 + 0x4A25619D,
12408 + 0x1E8C94E0,
12409 + 0xDB0933D7,
12410 + 0xABF5AE8C,
12411 + 0xA6E1E4C7,
12412 + 0xB3970F85,
12413 + 0x5D060C7D,
12414 + 0x8AEA7157,
12415 + 0x58DBEF0A,
12416 + 0xECFB8504,
12417 + 0xDF1CBA64,
12418 + 0xA85521AB,
12419 + 0x04507A33,
12420 + 0xAD33170D,
12421 + 0x8AAAC42D,
12422 + 0x15728E5A,
12423 + 0x98FA0510,
12424 + 0x15D22618,
12425 + 0xEA956AE5,
12426 + 0x3995497C,
12427 + 0x95581718,
12428 + 0xDE2BCBF6,
12429 + 0x6F4C52C9,
12430 + 0xB5C55DF0,
12431 + 0xEC07A28F,
12432 + 0x9B2783A2,
12433 + 0x180E8603,
12434 + 0xE39E772C,
12435 + 0x2E36CE3B,
12436 + 0x32905E46,
12437 + 0xCA18217C,
12438 + 0xF1746C08,
12439 + 0x4ABC9804,
12440 + 0x670C354E,
12441 + 0x7096966D,
12442 + 0x9ED52907,
12443 + 0x208552BB,
12444 + 0x1C62F356,
12445 + 0xDCA3AD96,
12446 + 0x83655D23,
12447 + 0xFD24CF5F,
12448 + 0x69163FA8,
12449 + 0x1C55D39A,
12450 + 0x98DA4836,
12451 + 0xA163BF05,
12452 + 0xC2007CB8,
12453 + 0xECE45B3D,
12454 + 0x49286651,
12455 + 0x7C4B1FE6,
12456 + 0xAE9F2411,
12457 + 0x5A899FA5,
12458 + 0xEE386BFB,
12459 + 0xF406B7ED,
12460 + 0x0BFF5CB6,
12461 + 0xA637ED6B,
12462 + 0xF44C42E9,
12463 + 0x625E7EC6,
12464 + 0xE485B576,
12465 + 0x6D51C245,
12466 + 0x4FE1356D,
12467 + 0xF25F1437,
12468 + 0x302B0A6D,
12469 + 0xCD3A431B,
12470 + 0xEF9519B3,
12471 + 0x8E3404DD,
12472 + 0x514A0879,
12473 + 0x3B139B22,
12474 + 0x020BBEA6,
12475 + 0x8A67CC74,
12476 + 0x29024E08,
12477 + 0x80DC1CD1,
12478 + 0xC4C6628B,
12479 + 0x2168C234,
12480 + 0xC90FDAA2,
12481 + 0xFFFFFFFF,
12482 + 0xFFFFFFFF,
12483 +};
12484 +
12485 +static __u32 dh_a[] = {
12486 + 8,
12487 + 0xdf367516,
12488 + 0x86459caa,
12489 + 0xe2d459a4,
12490 + 0xd910dae0,
12491 + 0x8a8b5e37,
12492 + 0x67ab31c6,
12493 + 0xf0b55ea9,
12494 + 0x440051d6,
12495 +};
12496 +
12497 +static __u32 dh_b[] = {
12498 + 8,
12499 + 0xded92656,
12500 + 0xe07a048a,
12501 + 0x6fa452cd,
12502 + 0x2df89d30,
12503 + 0xc75f1b0f,
12504 + 0x8ce3578f,
12505 + 0x7980a324,
12506 + 0x5daec786,
12507 +};
12508 +
12509 +static __u32 dh_g[] = {
12510 + 1,
12511 + 2,
12512 +};
12513 +
12514 +int main(void)
12515 +{
12516 + int i;
12517 + __u32 *k;
12518 + k = dwc_modpow(NULL, dh_g, dh_a, dh_p);
12519 +
12520 + printf("\n\n");
12521 + for (i=0; i<k[0]; i++) {
12522 + __u32 word32 = k[k[0] - i];
12523 + __u16 l = word32 & 0xffff;
12524 + __u16 m = (word32 & 0xffff0000) >> 16;
12525 + printf("%04x %04x ", m, l);
12526 + if (!((i + 1)%13)) printf("\n");
12527 + }
12528 + printf("\n\n");
12529 +
12530 + if ((k[0] == 0x60) && (k[1] == 0x28e490e5) && (k[0x60] == 0x5a0d3d4e)) {
12531 + printf("PASS\n\n");
12532 + }
12533 + else {
12534 + printf("FAIL\n\n");
12535 + }
12536 +
12537 +}
12538 +
12539 +#endif /* UNITTEST */
12540 +
12541 +#endif /* CONFIG_MACH_IPMATE */
12542 +
12543 +#endif /*DWC_CRYPTOLIB */
12544 --- /dev/null
12545 +++ b/drivers/usb/host/dwc_common_port/dwc_modpow.h
12546 @@ -0,0 +1,34 @@
12547 +/*
12548 + * dwc_modpow.h
12549 + * See dwc_modpow.c for license and changes
12550 + */
12551 +#ifndef _DWC_MODPOW_H
12552 +#define _DWC_MODPOW_H
12553 +
12554 +#ifdef __cplusplus
12555 +extern "C" {
12556 +#endif
12557 +
12558 +#include "dwc_os.h"
12559 +
12560 +/** @file
12561 + *
12562 + * This file defines the module exponentiation function which is only used
12563 + * internally by the DWC UWB modules for calculation of PKs during numeric
12564 + * association. The routine is taken from the PUTTY, an open source terminal
12565 + * emulator. The PUTTY License is preserved in the dwc_modpow.c file.
12566 + *
12567 + */
12568 +
12569 +typedef uint32_t BignumInt;
12570 +typedef uint64_t BignumDblInt;
12571 +typedef BignumInt *Bignum;
12572 +
12573 +/* Compute modular exponentiaion */
12574 +extern Bignum dwc_modpow(void *mem_ctx, Bignum base_in, Bignum exp, Bignum mod);
12575 +
12576 +#ifdef __cplusplus
12577 +}
12578 +#endif
12579 +
12580 +#endif /* _LINUX_BIGNUM_H */
12581 --- /dev/null
12582 +++ b/drivers/usb/host/dwc_common_port/dwc_notifier.c
12583 @@ -0,0 +1,319 @@
12584 +#ifdef DWC_NOTIFYLIB
12585 +
12586 +#include "dwc_notifier.h"
12587 +#include "dwc_list.h"
12588 +
12589 +typedef struct dwc_observer {
12590 + void *observer;
12591 + dwc_notifier_callback_t callback;
12592 + void *data;
12593 + char *notification;
12594 + DWC_CIRCLEQ_ENTRY(dwc_observer) list_entry;
12595 +} observer_t;
12596 +
12597 +DWC_CIRCLEQ_HEAD(observer_queue, dwc_observer);
12598 +
12599 +typedef struct dwc_notifier {
12600 + void *mem_ctx;
12601 + void *object;
12602 + struct observer_queue observers;
12603 + DWC_CIRCLEQ_ENTRY(dwc_notifier) list_entry;
12604 +} notifier_t;
12605 +
12606 +DWC_CIRCLEQ_HEAD(notifier_queue, dwc_notifier);
12607 +
12608 +typedef struct manager {
12609 + void *mem_ctx;
12610 + void *wkq_ctx;
12611 + dwc_workq_t *wq;
12612 +// dwc_mutex_t *mutex;
12613 + struct notifier_queue notifiers;
12614 +} manager_t;
12615 +
12616 +static manager_t *manager = NULL;
12617 +
12618 +static int create_manager(void *mem_ctx, void *wkq_ctx)
12619 +{
12620 + manager = dwc_alloc(mem_ctx, sizeof(manager_t));
12621 + if (!manager) {
12622 + return -DWC_E_NO_MEMORY;
12623 + }
12624 +
12625 + DWC_CIRCLEQ_INIT(&manager->notifiers);
12626 +
12627 + manager->wq = dwc_workq_alloc(wkq_ctx, "DWC Notification WorkQ");
12628 + if (!manager->wq) {
12629 + return -DWC_E_NO_MEMORY;
12630 + }
12631 +
12632 + return 0;
12633 +}
12634 +
12635 +static void free_manager(void)
12636 +{
12637 + dwc_workq_free(manager->wq);
12638 +
12639 + /* All notifiers must have unregistered themselves before this module
12640 + * can be removed. Hitting this assertion indicates a programmer
12641 + * error. */
12642 + DWC_ASSERT(DWC_CIRCLEQ_EMPTY(&manager->notifiers),
12643 + "Notification manager being freed before all notifiers have been removed");
12644 + dwc_free(manager->mem_ctx, manager);
12645 +}
12646 +
12647 +#ifdef DEBUG
12648 +static void dump_manager(void)
12649 +{
12650 + notifier_t *n;
12651 + observer_t *o;
12652 +
12653 + DWC_ASSERT(manager, "Notification manager not found");
12654 +
12655 + DWC_DEBUG("List of all notifiers and observers:\n");
12656 + DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) {
12657 + DWC_DEBUG("Notifier %p has observers:\n", n->object);
12658 + DWC_CIRCLEQ_FOREACH(o, &n->observers, list_entry) {
12659 + DWC_DEBUG(" %p watching %s\n", o->observer, o->notification);
12660 + }
12661 + }
12662 +}
12663 +#else
12664 +#define dump_manager(...)
12665 +#endif
12666 +
12667 +static observer_t *alloc_observer(void *mem_ctx, void *observer, char *notification,
12668 + dwc_notifier_callback_t callback, void *data)
12669 +{
12670 + observer_t *new_observer = dwc_alloc(mem_ctx, sizeof(observer_t));
12671 +
12672 + if (!new_observer) {
12673 + return NULL;
12674 + }
12675 +
12676 + DWC_CIRCLEQ_INIT_ENTRY(new_observer, list_entry);
12677 + new_observer->observer = observer;
12678 + new_observer->notification = notification;
12679 + new_observer->callback = callback;
12680 + new_observer->data = data;
12681 + return new_observer;
12682 +}
12683 +
12684 +static void free_observer(void *mem_ctx, observer_t *observer)
12685 +{
12686 + dwc_free(mem_ctx, observer);
12687 +}
12688 +
12689 +static notifier_t *alloc_notifier(void *mem_ctx, void *object)
12690 +{
12691 + notifier_t *notifier;
12692 +
12693 + if (!object) {
12694 + return NULL;
12695 + }
12696 +
12697 + notifier = dwc_alloc(mem_ctx, sizeof(notifier_t));
12698 + if (!notifier) {
12699 + return NULL;
12700 + }
12701 +
12702 + DWC_CIRCLEQ_INIT(&notifier->observers);
12703 + DWC_CIRCLEQ_INIT_ENTRY(notifier, list_entry);
12704 +
12705 + notifier->mem_ctx = mem_ctx;
12706 + notifier->object = object;
12707 + return notifier;
12708 +}
12709 +
12710 +static void free_notifier(notifier_t *notifier)
12711 +{
12712 + observer_t *observer;
12713 +
12714 + DWC_CIRCLEQ_FOREACH(observer, &notifier->observers, list_entry) {
12715 + free_observer(notifier->mem_ctx, observer);
12716 + }
12717 +
12718 + dwc_free(notifier->mem_ctx, notifier);
12719 +}
12720 +
12721 +static notifier_t *find_notifier(void *object)
12722 +{
12723 + notifier_t *notifier;
12724 +
12725 + DWC_ASSERT(manager, "Notification manager not found");
12726 +
12727 + if (!object) {
12728 + return NULL;
12729 + }
12730 +
12731 + DWC_CIRCLEQ_FOREACH(notifier, &manager->notifiers, list_entry) {
12732 + if (notifier->object == object) {
12733 + return notifier;
12734 + }
12735 + }
12736 +
12737 + return NULL;
12738 +}
12739 +
12740 +int dwc_alloc_notification_manager(void *mem_ctx, void *wkq_ctx)
12741 +{
12742 + return create_manager(mem_ctx, wkq_ctx);
12743 +}
12744 +
12745 +void dwc_free_notification_manager(void)
12746 +{
12747 + free_manager();
12748 +}
12749 +
12750 +dwc_notifier_t *dwc_register_notifier(void *mem_ctx, void *object)
12751 +{
12752 + notifier_t *notifier;
12753 +
12754 + DWC_ASSERT(manager, "Notification manager not found");
12755 +
12756 + notifier = find_notifier(object);
12757 + if (notifier) {
12758 + DWC_ERROR("Notifier %p is already registered\n", object);
12759 + return NULL;
12760 + }
12761 +
12762 + notifier = alloc_notifier(mem_ctx, object);
12763 + if (!notifier) {
12764 + return NULL;
12765 + }
12766 +
12767 + DWC_CIRCLEQ_INSERT_TAIL(&manager->notifiers, notifier, list_entry);
12768 +
12769 + DWC_INFO("Notifier %p registered", object);
12770 + dump_manager();
12771 +
12772 + return notifier;
12773 +}
12774 +
12775 +void dwc_unregister_notifier(dwc_notifier_t *notifier)
12776 +{
12777 + DWC_ASSERT(manager, "Notification manager not found");
12778 +
12779 + if (!DWC_CIRCLEQ_EMPTY(&notifier->observers)) {
12780 + observer_t *o;
12781 +
12782 + DWC_ERROR("Notifier %p has active observers when removing\n", notifier->object);
12783 + DWC_CIRCLEQ_FOREACH(o, &notifier->observers, list_entry) {
12784 + DWC_DEBUGC(" %p watching %s\n", o->observer, o->notification);
12785 + }
12786 +
12787 + DWC_ASSERT(DWC_CIRCLEQ_EMPTY(&notifier->observers),
12788 + "Notifier %p has active observers when removing", notifier);
12789 + }
12790 +
12791 + DWC_CIRCLEQ_REMOVE_INIT(&manager->notifiers, notifier, list_entry);
12792 + free_notifier(notifier);
12793 +
12794 + DWC_INFO("Notifier unregistered");
12795 + dump_manager();
12796 +}
12797 +
12798 +/* Add an observer to observe the notifier for a particular state, event, or notification. */
12799 +int dwc_add_observer(void *observer, void *object, char *notification,
12800 + dwc_notifier_callback_t callback, void *data)
12801 +{
12802 + notifier_t *notifier = find_notifier(object);
12803 + observer_t *new_observer;
12804 +
12805 + if (!notifier) {
12806 + DWC_ERROR("Notifier %p is not found when adding observer\n", object);
12807 + return -DWC_E_INVALID;
12808 + }
12809 +
12810 + new_observer = alloc_observer(notifier->mem_ctx, observer, notification, callback, data);
12811 + if (!new_observer) {
12812 + return -DWC_E_NO_MEMORY;
12813 + }
12814 +
12815 + DWC_CIRCLEQ_INSERT_TAIL(&notifier->observers, new_observer, list_entry);
12816 +
12817 + DWC_INFO("Added observer %p to notifier %p observing notification %s, callback=%p, data=%p",
12818 + observer, object, notification, callback, data);
12819 +
12820 + dump_manager();
12821 + return 0;
12822 +}
12823 +
12824 +int dwc_remove_observer(void *observer)
12825 +{
12826 + notifier_t *n;
12827 +
12828 + DWC_ASSERT(manager, "Notification manager not found");
12829 +
12830 + DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) {
12831 + observer_t *o;
12832 + observer_t *o2;
12833 +
12834 + DWC_CIRCLEQ_FOREACH_SAFE(o, o2, &n->observers, list_entry) {
12835 + if (o->observer == observer) {
12836 + DWC_CIRCLEQ_REMOVE_INIT(&n->observers, o, list_entry);
12837 + DWC_INFO("Removing observer %p from notifier %p watching notification %s:",
12838 + o->observer, n->object, o->notification);
12839 + free_observer(n->mem_ctx, o);
12840 + }
12841 + }
12842 + }
12843 +
12844 + dump_manager();
12845 + return 0;
12846 +}
12847 +
12848 +typedef struct callback_data {
12849 + void *mem_ctx;
12850 + dwc_notifier_callback_t cb;
12851 + void *observer;
12852 + void *data;
12853 + void *object;
12854 + char *notification;
12855 + void *notification_data;
12856 +} cb_data_t;
12857 +
12858 +static void cb_task(void *data)
12859 +{
12860 + cb_data_t *cb = (cb_data_t *)data;
12861 +
12862 + cb->cb(cb->object, cb->notification, cb->observer, cb->notification_data, cb->data);
12863 + dwc_free(cb->mem_ctx, cb);
12864 +}
12865 +
12866 +void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data)
12867 +{
12868 + observer_t *o;
12869 +
12870 + DWC_ASSERT(manager, "Notification manager not found");
12871 +
12872 + DWC_CIRCLEQ_FOREACH(o, &notifier->observers, list_entry) {
12873 + int len = DWC_STRLEN(notification);
12874 +
12875 + if (DWC_STRLEN(o->notification) != len) {
12876 + continue;
12877 + }
12878 +
12879 + if (DWC_STRNCMP(o->notification, notification, len) == 0) {
12880 + cb_data_t *cb_data = dwc_alloc(notifier->mem_ctx, sizeof(cb_data_t));
12881 +
12882 + if (!cb_data) {
12883 + DWC_ERROR("Failed to allocate callback data\n");
12884 + return;
12885 + }
12886 +
12887 + cb_data->mem_ctx = notifier->mem_ctx;
12888 + cb_data->cb = o->callback;
12889 + cb_data->observer = o->observer;
12890 + cb_data->data = o->data;
12891 + cb_data->object = notifier->object;
12892 + cb_data->notification = notification;
12893 + cb_data->notification_data = notification_data;
12894 + DWC_DEBUGC("Observer found %p for notification %s\n", o->observer, notification);
12895 + DWC_WORKQ_SCHEDULE(manager->wq, cb_task, cb_data,
12896 + "Notify callback from %p for Notification %s, to observer %p",
12897 + cb_data->object, notification, cb_data->observer);
12898 + }
12899 + }
12900 +}
12901 +
12902 +#endif /* DWC_NOTIFYLIB */
12903 --- /dev/null
12904 +++ b/drivers/usb/host/dwc_common_port/dwc_notifier.h
12905 @@ -0,0 +1,122 @@
12906 +
12907 +#ifndef __DWC_NOTIFIER_H__
12908 +#define __DWC_NOTIFIER_H__
12909 +
12910 +#ifdef __cplusplus
12911 +extern "C" {
12912 +#endif
12913 +
12914 +#include "dwc_os.h"
12915 +
12916 +/** @file
12917 + *
12918 + * A simple implementation of the Observer pattern. Any "module" can
12919 + * register as an observer or notifier. The notion of "module" is abstract and
12920 + * can mean anything used to identify either an observer or notifier. Usually
12921 + * it will be a pointer to a data structure which contains some state, ie an
12922 + * object.
12923 + *
12924 + * Before any notifiers can be added, the global notification manager must be
12925 + * brought up with dwc_alloc_notification_manager().
12926 + * dwc_free_notification_manager() will bring it down and free all resources.
12927 + * These would typically be called upon module load and unload. The
12928 + * notification manager is a single global instance that handles all registered
12929 + * observable modules and observers so this should be done only once.
12930 + *
12931 + * A module can be observable by using Notifications to publicize some general
12932 + * information about it's state or operation. It does not care who listens, or
12933 + * even if anyone listens, or what they do with the information. The observable
12934 + * modules do not need to know any information about it's observers or their
12935 + * interface, or their state or data.
12936 + *
12937 + * Any module can register to emit Notifications. It should publish a list of
12938 + * notifications that it can emit and their behavior, such as when they will get
12939 + * triggered, and what information will be provided to the observer. Then it
12940 + * should register itself as an observable module. See dwc_register_notifier().
12941 + *
12942 + * Any module can observe any observable, registered module, provided it has a
12943 + * handle to the other module and knows what notifications to observe. See
12944 + * dwc_add_observer().
12945 + *
12946 + * A function of type dwc_notifier_callback_t is called whenever a notification
12947 + * is triggered with one or more observers observing it. This function is
12948 + * called in it's own process so it may sleep or block if needed. It is
12949 + * guaranteed to be called sometime after the notification has occurred and will
12950 + * be called once per each time the notification is triggered. It will NOT be
12951 + * called in the same process context used to trigger the notification.
12952 + *
12953 + * @section Limitiations
12954 + *
12955 + * Keep in mind that Notifications that can be triggered in rapid sucession may
12956 + * schedule too many processes too handle. Be aware of this limitation when
12957 + * designing to use notifications, and only add notifications for appropriate
12958 + * observable information.
12959 + *
12960 + * Also Notification callbacks are not synchronous. If you need to synchronize
12961 + * the behavior between module/observer you must use other means. And perhaps
12962 + * that will mean Notifications are not the proper solution.
12963 + */
12964 +
12965 +struct dwc_notifier;
12966 +typedef struct dwc_notifier dwc_notifier_t;
12967 +
12968 +/** The callback function must be of this type.
12969 + *
12970 + * @param object This is the object that is being observed.
12971 + * @param notification This is the notification that was triggered.
12972 + * @param observer This is the observer
12973 + * @param notification_data This is notification-specific data that the notifier
12974 + * has included in this notification. The value of this should be published in
12975 + * the documentation of the observable module with the notifications.
12976 + * @param user_data This is any custom data that the observer provided when
12977 + * adding itself as an observer to the notification. */
12978 +typedef void (*dwc_notifier_callback_t)(void *object, char *notification, void *observer,
12979 + void *notification_data, void *user_data);
12980 +
12981 +/** Brings up the notification manager. */
12982 +extern int dwc_alloc_notification_manager(void *mem_ctx, void *wkq_ctx);
12983 +/** Brings down the notification manager. */
12984 +extern void dwc_free_notification_manager(void);
12985 +
12986 +/** This function registers an observable module. A dwc_notifier_t object is
12987 + * returned to the observable module. This is an opaque object that is used by
12988 + * the observable module to trigger notifications. This object should only be
12989 + * accessible to functions that are authorized to trigger notifications for this
12990 + * module. Observers do not need this object. */
12991 +extern dwc_notifier_t *dwc_register_notifier(void *mem_ctx, void *object);
12992 +
12993 +/** This function unregisters an observable module. All observers have to be
12994 + * removed prior to unregistration. */
12995 +extern void dwc_unregister_notifier(dwc_notifier_t *notifier);
12996 +
12997 +/** Add a module as an observer to the observable module. The observable module
12998 + * needs to have previously registered with the notification manager.
12999 + *
13000 + * @param observer The observer module
13001 + * @param object The module to observe
13002 + * @param notification The notification to observe
13003 + * @param callback The callback function to call
13004 + * @param user_data Any additional user data to pass into the callback function */
13005 +extern int dwc_add_observer(void *observer, void *object, char *notification,
13006 + dwc_notifier_callback_t callback, void *user_data);
13007 +
13008 +/** Removes the specified observer from all notifications that it is currently
13009 + * observing. */
13010 +extern int dwc_remove_observer(void *observer);
13011 +
13012 +/** This function triggers a Notification. It should be called by the
13013 + * observable module, or any module or library which the observable module
13014 + * allows to trigger notification on it's behalf. Such as the dwc_cc_t.
13015 + *
13016 + * dwc_notify is a non-blocking function. Callbacks are scheduled called in
13017 + * their own process context for each trigger. Callbacks can be blocking.
13018 + * dwc_notify can be called from interrupt context if needed.
13019 + *
13020 + */
13021 +void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data);
13022 +
13023 +#ifdef __cplusplus
13024 +}
13025 +#endif
13026 +
13027 +#endif /* __DWC_NOTIFIER_H__ */
13028 --- /dev/null
13029 +++ b/drivers/usb/host/dwc_common_port/dwc_os.h
13030 @@ -0,0 +1,1276 @@
13031 +/* =========================================================================
13032 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_os.h $
13033 + * $Revision: #14 $
13034 + * $Date: 2010/11/04 $
13035 + * $Change: 1621695 $
13036 + *
13037 + * Synopsys Portability Library Software and documentation
13038 + * (hereinafter, "Software") is an Unsupported proprietary work of
13039 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
13040 + * between Synopsys and you.
13041 + *
13042 + * The Software IS NOT an item of Licensed Software or Licensed Product
13043 + * under any End User Software License Agreement or Agreement for
13044 + * Licensed Product with Synopsys or any supplement thereto. You are
13045 + * permitted to use and redistribute this Software in source and binary
13046 + * forms, with or without modification, provided that redistributions
13047 + * of source code must retain this notice. You may not view, use,
13048 + * disclose, copy or distribute this file or any information contained
13049 + * herein except pursuant to this license grant from Synopsys. If you
13050 + * do not agree with this notice, including the disclaimer below, then
13051 + * you are not authorized to use the Software.
13052 + *
13053 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
13054 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
13055 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
13056 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
13057 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
13058 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
13059 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
13060 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
13061 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
13062 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
13063 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
13064 + * DAMAGE.
13065 + * ========================================================================= */
13066 +#ifndef _DWC_OS_H_
13067 +#define _DWC_OS_H_
13068 +
13069 +#ifdef __cplusplus
13070 +extern "C" {
13071 +#endif
13072 +
13073 +/** @file
13074 + *
13075 + * DWC portability library, low level os-wrapper functions
13076 + *
13077 + */
13078 +
13079 +/* These basic types need to be defined by some OS header file or custom header
13080 + * file for your specific target architecture.
13081 + *
13082 + * uint8_t, int8_t, uint16_t, int16_t, uint32_t, int32_t, uint64_t, int64_t
13083 + *
13084 + * Any custom or alternate header file must be added and enabled here.
13085 + */
13086 +
13087 +#ifdef DWC_LINUX
13088 +# include <linux/types.h>
13089 +# ifdef CONFIG_DEBUG_MUTEXES
13090 +# include <linux/mutex.h>
13091 +# endif
13092 +# include <linux/spinlock.h>
13093 +# include <linux/errno.h>
13094 +# include <stdarg.h>
13095 +#endif
13096 +
13097 +#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
13098 +# include <os_dep.h>
13099 +#endif
13100 +
13101 +
13102 +/** @name Primitive Types and Values */
13103 +
13104 +/** We define a boolean type for consistency. Can be either YES or NO */
13105 +typedef uint8_t dwc_bool_t;
13106 +#define YES 1
13107 +#define NO 0
13108 +
13109 +#ifdef DWC_LINUX
13110 +
13111 +/** @name Error Codes */
13112 +#define DWC_E_INVALID EINVAL
13113 +#define DWC_E_NO_MEMORY ENOMEM
13114 +#define DWC_E_NO_DEVICE ENODEV
13115 +#define DWC_E_NOT_SUPPORTED EOPNOTSUPP
13116 +#define DWC_E_TIMEOUT ETIMEDOUT
13117 +#define DWC_E_BUSY EBUSY
13118 +#define DWC_E_AGAIN EAGAIN
13119 +#define DWC_E_RESTART ERESTART
13120 +#define DWC_E_ABORT ECONNABORTED
13121 +#define DWC_E_SHUTDOWN ESHUTDOWN
13122 +#define DWC_E_NO_DATA ENODATA
13123 +#define DWC_E_DISCONNECT ECONNRESET
13124 +#define DWC_E_UNKNOWN EINVAL
13125 +#define DWC_E_NO_STREAM_RES ENOSR
13126 +#define DWC_E_COMMUNICATION ECOMM
13127 +#define DWC_E_OVERFLOW EOVERFLOW
13128 +#define DWC_E_PROTOCOL EPROTO
13129 +#define DWC_E_IN_PROGRESS EINPROGRESS
13130 +#define DWC_E_PIPE EPIPE
13131 +#define DWC_E_IO EIO
13132 +#define DWC_E_NO_SPACE ENOSPC
13133 +
13134 +#else
13135 +
13136 +/** @name Error Codes */
13137 +#define DWC_E_INVALID 1001
13138 +#define DWC_E_NO_MEMORY 1002
13139 +#define DWC_E_NO_DEVICE 1003
13140 +#define DWC_E_NOT_SUPPORTED 1004
13141 +#define DWC_E_TIMEOUT 1005
13142 +#define DWC_E_BUSY 1006
13143 +#define DWC_E_AGAIN 1007
13144 +#define DWC_E_RESTART 1008
13145 +#define DWC_E_ABORT 1009
13146 +#define DWC_E_SHUTDOWN 1010
13147 +#define DWC_E_NO_DATA 1011
13148 +#define DWC_E_DISCONNECT 2000
13149 +#define DWC_E_UNKNOWN 3000
13150 +#define DWC_E_NO_STREAM_RES 4001
13151 +#define DWC_E_COMMUNICATION 4002
13152 +#define DWC_E_OVERFLOW 4003
13153 +#define DWC_E_PROTOCOL 4004
13154 +#define DWC_E_IN_PROGRESS 4005
13155 +#define DWC_E_PIPE 4006
13156 +#define DWC_E_IO 4007
13157 +#define DWC_E_NO_SPACE 4008
13158 +
13159 +#endif
13160 +
13161 +
13162 +/** @name Tracing/Logging Functions
13163 + *
13164 + * These function provide the capability to add tracing, debugging, and error
13165 + * messages, as well exceptions as assertions. The WUDEV uses these
13166 + * extensively. These could be logged to the main console, the serial port, an
13167 + * internal buffer, etc. These functions could also be no-op if they are too
13168 + * expensive on your system. By default undefining the DEBUG macro already
13169 + * no-ops some of these functions. */
13170 +
13171 +/** Returns non-zero if in interrupt context. */
13172 +extern dwc_bool_t DWC_IN_IRQ(void);
13173 +#define dwc_in_irq DWC_IN_IRQ
13174 +
13175 +/** Returns "IRQ" if DWC_IN_IRQ is true. */
13176 +static inline char *dwc_irq(void) {
13177 + return DWC_IN_IRQ() ? "IRQ" : "";
13178 +}
13179 +
13180 +/** Returns non-zero if in bottom-half context. */
13181 +extern dwc_bool_t DWC_IN_BH(void);
13182 +#define dwc_in_bh DWC_IN_BH
13183 +
13184 +/** Returns "BH" if DWC_IN_BH is true. */
13185 +static inline char *dwc_bh(void) {
13186 + return DWC_IN_BH() ? "BH" : "";
13187 +}
13188 +
13189 +/**
13190 + * A vprintf() clone. Just call vprintf if you've got it.
13191 + */
13192 +extern void DWC_VPRINTF(char *format, va_list args);
13193 +#define dwc_vprintf DWC_VPRINTF
13194 +
13195 +/**
13196 + * A vsnprintf() clone. Just call vprintf if you've got it.
13197 + */
13198 +extern int DWC_VSNPRINTF(char *str, int size, char *format, va_list args);
13199 +#define dwc_vsnprintf DWC_VSNPRINTF
13200 +
13201 +/**
13202 + * printf() clone. Just call printf if you've go it.
13203 + */
13204 +extern void DWC_PRINTF(char *format, ...)
13205 +/* This provides compiler level static checking of the parameters if you're
13206 + * using GCC. */
13207 +#ifdef __GNUC__
13208 + __attribute__ ((format(printf, 1, 2)));
13209 +#else
13210 + ;
13211 +#endif
13212 +#define dwc_printf DWC_PRINTF
13213 +
13214 +/**
13215 + * sprintf() clone. Just call sprintf if you've got it.
13216 + */
13217 +extern int DWC_SPRINTF(char *string, char *format, ...)
13218 +#ifdef __GNUC__
13219 + __attribute__ ((format(printf, 2, 3)));
13220 +#else
13221 + ;
13222 +#endif
13223 +#define dwc_sprintf DWC_SPRINTF
13224 +
13225 +/**
13226 + * snprintf() clone. Just call snprintf if you've got it.
13227 + */
13228 +extern int DWC_SNPRINTF(char *string, int size, char *format, ...)
13229 +#ifdef __GNUC__
13230 + __attribute__ ((format(printf, 3, 4)));
13231 +#else
13232 + ;
13233 +#endif
13234 +#define dwc_snprintf DWC_SNPRINTF
13235 +
13236 +/**
13237 + * Prints a WARNING message. On systems that don't differentiate between
13238 + * warnings and regular log messages, just print it. Indicates that something
13239 + * may be wrong with the driver. Works like printf().
13240 + *
13241 + * Use the DWC_WARN macro to call this function.
13242 + */
13243 +extern void __DWC_WARN(char *format, ...)
13244 +#ifdef __GNUC__
13245 + __attribute__ ((format(printf, 1, 2)));
13246 +#else
13247 + ;
13248 +#endif
13249 +
13250 +/**
13251 + * Prints an error message. On systems that don't differentiate between errors
13252 + * and regular log messages, just print it. Indicates that something went wrong
13253 + * with the driver. Works like printf().
13254 + *
13255 + * Use the DWC_ERROR macro to call this function.
13256 + */
13257 +extern void __DWC_ERROR(char *format, ...)
13258 +#ifdef __GNUC__
13259 + __attribute__ ((format(printf, 1, 2)));
13260 +#else
13261 + ;
13262 +#endif
13263 +
13264 +/**
13265 + * Prints an exception error message and takes some user-defined action such as
13266 + * print out a backtrace or trigger a breakpoint. Indicates that something went
13267 + * abnormally wrong with the driver such as programmer error, or other
13268 + * exceptional condition. It should not be ignored so even on systems without
13269 + * printing capability, some action should be taken to notify the developer of
13270 + * it. Works like printf().
13271 + */
13272 +extern void DWC_EXCEPTION(char *format, ...)
13273 +#ifdef __GNUC__
13274 + __attribute__ ((format(printf, 1, 2)));
13275 +#else
13276 + ;
13277 +#endif
13278 +#define dwc_exception DWC_EXCEPTION
13279 +
13280 +#ifndef DWC_OTG_DEBUG_LEV
13281 +#define DWC_OTG_DEBUG_LEV 0
13282 +#endif
13283 +
13284 +#ifdef DEBUG
13285 +/**
13286 + * Prints out a debug message. Used for logging/trace messages.
13287 + *
13288 + * Use the DWC_DEBUG macro to call this function
13289 + */
13290 +extern void __DWC_DEBUG(char *format, ...)
13291 +#ifdef __GNUC__
13292 + __attribute__ ((format(printf, 1, 2)));
13293 +#else
13294 + ;
13295 +#endif
13296 +#else
13297 +#define __DWC_DEBUG printk
13298 +#endif
13299 +
13300 +/**
13301 + * Prints out a Debug message.
13302 + */
13303 +#define DWC_DEBUG(_format, _args...) __DWC_DEBUG("DEBUG:%s:%s: " _format "\n", \
13304 + __func__, dwc_irq(), ## _args)
13305 +#define dwc_debug DWC_DEBUG
13306 +/**
13307 + * Prints out a Debug message if enabled at compile time.
13308 + */
13309 +#if DWC_OTG_DEBUG_LEV > 0
13310 +#define DWC_DEBUGC(_format, _args...) DWC_DEBUG(_format, ##_args )
13311 +#else
13312 +#define DWC_DEBUGC(_format, _args...)
13313 +#endif
13314 +#define dwc_debugc DWC_DEBUGC
13315 +/**
13316 + * Prints out an informative message.
13317 + */
13318 +#define DWC_INFO(_format, _args...) DWC_PRINTF("INFO:%s: " _format "\n", \
13319 + dwc_irq(), ## _args)
13320 +#define dwc_info DWC_INFO
13321 +/**
13322 + * Prints out an informative message if enabled at compile time.
13323 + */
13324 +#if DWC_OTG_DEBUG_LEV > 1
13325 +#define DWC_INFOC(_format, _args...) DWC_INFO(_format, ##_args )
13326 +#else
13327 +#define DWC_INFOC(_format, _args...)
13328 +#endif
13329 +#define dwc_infoc DWC_INFOC
13330 +/**
13331 + * Prints out a warning message.
13332 + */
13333 +#define DWC_WARN(_format, _args...) __DWC_WARN("WARN:%s:%s:%d: " _format "\n", \
13334 + dwc_irq(), __func__, __LINE__, ## _args)
13335 +#define dwc_warn DWC_WARN
13336 +/**
13337 + * Prints out an error message.
13338 + */
13339 +#define DWC_ERROR(_format, _args...) __DWC_ERROR("ERROR:%s:%s:%d: " _format "\n", \
13340 + dwc_irq(), __func__, __LINE__, ## _args)
13341 +#define dwc_error DWC_ERROR
13342 +
13343 +#define DWC_PROTO_ERROR(_format, _args...) __DWC_WARN("ERROR:%s:%s:%d: " _format "\n", \
13344 + dwc_irq(), __func__, __LINE__, ## _args)
13345 +#define dwc_proto_error DWC_PROTO_ERROR
13346 +
13347 +#ifdef DEBUG
13348 +/** Prints out a exception error message if the _expr expression fails. Disabled
13349 + * if DEBUG is not enabled. */
13350 +#define DWC_ASSERT(_expr, _format, _args...) do { \
13351 + if (!(_expr)) { DWC_EXCEPTION("%s:%s:%d: " _format "\n", dwc_irq(), \
13352 + __FILE__, __LINE__, ## _args); } \
13353 + } while (0)
13354 +#else
13355 +#define DWC_ASSERT(_x...)
13356 +#endif
13357 +#define dwc_assert DWC_ASSERT
13358 +
13359 +
13360 +/** @name Byte Ordering
13361 + * The following functions are for conversions between processor's byte ordering
13362 + * and specific ordering you want.
13363 + */
13364 +
13365 +/** Converts 32 bit data in CPU byte ordering to little endian. */
13366 +extern uint32_t DWC_CPU_TO_LE32(uint32_t *p);
13367 +#define dwc_cpu_to_le32 DWC_CPU_TO_LE32
13368 +
13369 +/** Converts 32 bit data in CPU byte orderint to big endian. */
13370 +extern uint32_t DWC_CPU_TO_BE32(uint32_t *p);
13371 +#define dwc_cpu_to_be32 DWC_CPU_TO_BE32
13372 +
13373 +/** Converts 32 bit little endian data to CPU byte ordering. */
13374 +extern uint32_t DWC_LE32_TO_CPU(uint32_t *p);
13375 +#define dwc_le32_to_cpu DWC_LE32_TO_CPU
13376 +
13377 +/** Converts 32 bit big endian data to CPU byte ordering. */
13378 +extern uint32_t DWC_BE32_TO_CPU(uint32_t *p);
13379 +#define dwc_be32_to_cpu DWC_BE32_TO_CPU
13380 +
13381 +/** Converts 16 bit data in CPU byte ordering to little endian. */
13382 +extern uint16_t DWC_CPU_TO_LE16(uint16_t *p);
13383 +#define dwc_cpu_to_le16 DWC_CPU_TO_LE16
13384 +
13385 +/** Converts 16 bit data in CPU byte orderint to big endian. */
13386 +extern uint16_t DWC_CPU_TO_BE16(uint16_t *p);
13387 +#define dwc_cpu_to_be16 DWC_CPU_TO_BE16
13388 +
13389 +/** Converts 16 bit little endian data to CPU byte ordering. */
13390 +extern uint16_t DWC_LE16_TO_CPU(uint16_t *p);
13391 +#define dwc_le16_to_cpu DWC_LE16_TO_CPU
13392 +
13393 +/** Converts 16 bit bi endian data to CPU byte ordering. */
13394 +extern uint16_t DWC_BE16_TO_CPU(uint16_t *p);
13395 +#define dwc_be16_to_cpu DWC_BE16_TO_CPU
13396 +
13397 +
13398 +/** @name Register Read/Write
13399 + *
13400 + * The following six functions should be implemented to read/write registers of
13401 + * 32-bit and 64-bit sizes. All modules use this to read/write register values.
13402 + * The reg value is a pointer to the register calculated from the void *base
13403 + * variable passed into the driver when it is started. */
13404 +
13405 +#ifdef DWC_LINUX
13406 +/* Linux doesn't need any extra parameters for register read/write, so we
13407 + * just throw away the IO context parameter.
13408 + */
13409 +/** Reads the content of a 32-bit register. */
13410 +extern uint32_t DWC_READ_REG32(uint32_t volatile *reg);
13411 +#define dwc_read_reg32(_ctx_,_reg_) DWC_READ_REG32(_reg_)
13412 +
13413 +/** Reads the content of a 64-bit register. */
13414 +extern uint64_t DWC_READ_REG64(uint64_t volatile *reg);
13415 +#define dwc_read_reg64(_ctx_,_reg_) DWC_READ_REG64(_reg_)
13416 +
13417 +/** Writes to a 32-bit register. */
13418 +extern void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value);
13419 +#define dwc_write_reg32(_ctx_,_reg_,_val_) DWC_WRITE_REG32(_reg_, _val_)
13420 +
13421 +/** Writes to a 64-bit register. */
13422 +extern void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value);
13423 +#define dwc_write_reg64(_ctx_,_reg_,_val_) DWC_WRITE_REG64(_reg_, _val_)
13424 +
13425 +/**
13426 + * Modify bit values in a register. Using the
13427 + * algorithm: (reg_contents & ~clear_mask) | set_mask.
13428 + */
13429 +extern void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask);
13430 +#define dwc_modify_reg32(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG32(_reg_,_cmsk_,_smsk_)
13431 +extern void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask);
13432 +#define dwc_modify_reg64(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG64(_reg_,_cmsk_,_smsk_)
13433 +
13434 +#endif /* DWC_LINUX */
13435 +
13436 +#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
13437 +typedef struct dwc_ioctx {
13438 + struct device *dev;
13439 + bus_space_tag_t iot;
13440 + bus_space_handle_t ioh;
13441 +} dwc_ioctx_t;
13442 +
13443 +/** BSD needs two extra parameters for register read/write, so we pass
13444 + * them in using the IO context parameter.
13445 + */
13446 +/** Reads the content of a 32-bit register. */
13447 +extern uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg);
13448 +#define dwc_read_reg32 DWC_READ_REG32
13449 +
13450 +/** Reads the content of a 64-bit register. */
13451 +extern uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg);
13452 +#define dwc_read_reg64 DWC_READ_REG64
13453 +
13454 +/** Writes to a 32-bit register. */
13455 +extern void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value);
13456 +#define dwc_write_reg32 DWC_WRITE_REG32
13457 +
13458 +/** Writes to a 64-bit register. */
13459 +extern void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value);
13460 +#define dwc_write_reg64 DWC_WRITE_REG64
13461 +
13462 +/**
13463 + * Modify bit values in a register. Using the
13464 + * algorithm: (reg_contents & ~clear_mask) | set_mask.
13465 + */
13466 +extern void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask);
13467 +#define dwc_modify_reg32 DWC_MODIFY_REG32
13468 +extern void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask);
13469 +#define dwc_modify_reg64 DWC_MODIFY_REG64
13470 +
13471 +#endif /* DWC_FREEBSD || DWC_NETBSD */
13472 +
13473 +/** @cond */
13474 +
13475 +/** @name Some convenience MACROS used internally. Define DWC_DEBUG_REGS to log the
13476 + * register writes. */
13477 +
13478 +#ifdef DWC_LINUX
13479 +
13480 +# ifdef DWC_DEBUG_REGS
13481 +
13482 +#define dwc_define_read_write_reg_n(_reg,_container_type) \
13483 +static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \
13484 + return DWC_READ_REG32(&container->regs->_reg[num]); \
13485 +} \
13486 +static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \
13487 + DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \
13488 + &(((uint32_t*)container->regs->_reg)[num]), data); \
13489 + DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \
13490 +}
13491 +
13492 +#define dwc_define_read_write_reg(_reg,_container_type) \
13493 +static inline uint32_t dwc_read_##_reg(_container_type *container) { \
13494 + return DWC_READ_REG32(&container->regs->_reg); \
13495 +} \
13496 +static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \
13497 + DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \
13498 + DWC_WRITE_REG32(&container->regs->_reg, data); \
13499 +}
13500 +
13501 +# else /* DWC_DEBUG_REGS */
13502 +
13503 +#define dwc_define_read_write_reg_n(_reg,_container_type) \
13504 +static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \
13505 + return DWC_READ_REG32(&container->regs->_reg[num]); \
13506 +} \
13507 +static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \
13508 + DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \
13509 +}
13510 +
13511 +#define dwc_define_read_write_reg(_reg,_container_type) \
13512 +static inline uint32_t dwc_read_##_reg(_container_type *container) { \
13513 + return DWC_READ_REG32(&container->regs->_reg); \
13514 +} \
13515 +static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \
13516 + DWC_WRITE_REG32(&container->regs->_reg, data); \
13517 +}
13518 +
13519 +# endif /* DWC_DEBUG_REGS */
13520 +
13521 +#endif /* DWC_LINUX */
13522 +
13523 +#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
13524 +
13525 +# ifdef DWC_DEBUG_REGS
13526 +
13527 +#define dwc_define_read_write_reg_n(_reg,_container_type) \
13528 +static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \
13529 + return DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \
13530 +} \
13531 +static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \
13532 + DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \
13533 + &(((uint32_t*)container->regs->_reg)[num]), data); \
13534 + DWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \
13535 +}
13536 +
13537 +#define dwc_define_read_write_reg(_reg,_container_type) \
13538 +static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \
13539 + return DWC_READ_REG32(io_ctx, &container->regs->_reg); \
13540 +} \
13541 +static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \
13542 + DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \
13543 + DWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \
13544 +}
13545 +
13546 +# else /* DWC_DEBUG_REGS */
13547 +
13548 +#define dwc_define_read_write_reg_n(_reg,_container_type) \
13549 +static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \
13550 + return DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \
13551 +} \
13552 +static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \
13553 + DWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \
13554 +}
13555 +
13556 +#define dwc_define_read_write_reg(_reg,_container_type) \
13557 +static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \
13558 + return DWC_READ_REG32(io_ctx, &container->regs->_reg); \
13559 +} \
13560 +static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \
13561 + DWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \
13562 +}
13563 +
13564 +# endif /* DWC_DEBUG_REGS */
13565 +
13566 +#endif /* DWC_FREEBSD || DWC_NETBSD */
13567 +
13568 +/** @endcond */
13569 +
13570 +
13571 +#ifdef DWC_CRYPTOLIB
13572 +/** @name Crypto Functions
13573 + *
13574 + * These are the low-level cryptographic functions used by the driver. */
13575 +
13576 +/** Perform AES CBC */
13577 +extern int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out);
13578 +#define dwc_aes_cbc DWC_AES_CBC
13579 +
13580 +/** Fill the provided buffer with random bytes. These should be cryptographic grade random numbers. */
13581 +extern void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length);
13582 +#define dwc_random_bytes DWC_RANDOM_BYTES
13583 +
13584 +/** Perform the SHA-256 hash function */
13585 +extern int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out);
13586 +#define dwc_sha256 DWC_SHA256
13587 +
13588 +/** Calculated the HMAC-SHA256 */
13589 +extern int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t *out);
13590 +#define dwc_hmac_sha256 DWC_HMAC_SHA256
13591 +
13592 +#endif /* DWC_CRYPTOLIB */
13593 +
13594 +
13595 +/** @name Memory Allocation
13596 + *
13597 + * These function provide access to memory allocation. There are only 2 DMA
13598 + * functions and 3 Regular memory functions that need to be implemented. None
13599 + * of the memory debugging routines need to be implemented. The allocation
13600 + * routines all ZERO the contents of the memory.
13601 + *
13602 + * Defining DWC_DEBUG_MEMORY turns on memory debugging and statistic gathering.
13603 + * This checks for memory leaks, keeping track of alloc/free pairs. It also
13604 + * keeps track of how much memory the driver is using at any given time. */
13605 +
13606 +#define DWC_PAGE_SIZE 4096
13607 +#define DWC_PAGE_OFFSET(addr) (((uint32_t)addr) & 0xfff)
13608 +#define DWC_PAGE_ALIGNED(addr) ((((uint32_t)addr) & 0xfff) == 0)
13609 +
13610 +#define DWC_INVALID_DMA_ADDR 0x0
13611 +
13612 +#ifdef DWC_LINUX
13613 +/** Type for a DMA address */
13614 +typedef dma_addr_t dwc_dma_t;
13615 +#endif
13616 +
13617 +#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
13618 +typedef bus_addr_t dwc_dma_t;
13619 +#endif
13620 +
13621 +#ifdef DWC_FREEBSD
13622 +typedef struct dwc_dmactx {
13623 + struct device *dev;
13624 + bus_dma_tag_t dma_tag;
13625 + bus_dmamap_t dma_map;
13626 + bus_addr_t dma_paddr;
13627 + void *dma_vaddr;
13628 +} dwc_dmactx_t;
13629 +#endif
13630 +
13631 +#ifdef DWC_NETBSD
13632 +typedef struct dwc_dmactx {
13633 + struct device *dev;
13634 + bus_dma_tag_t dma_tag;
13635 + bus_dmamap_t dma_map;
13636 + bus_dma_segment_t segs[1];
13637 + int nsegs;
13638 + bus_addr_t dma_paddr;
13639 + void *dma_vaddr;
13640 +} dwc_dmactx_t;
13641 +#endif
13642 +
13643 +/* @todo these functions will be added in the future */
13644 +#if 0
13645 +/**
13646 + * Creates a DMA pool from which you can allocate DMA buffers. Buffers
13647 + * allocated from this pool will be guaranteed to meet the size, alignment, and
13648 + * boundary requirements specified.
13649 + *
13650 + * @param[in] size Specifies the size of the buffers that will be allocated from
13651 + * this pool.
13652 + * @param[in] align Specifies the byte alignment requirements of the buffers
13653 + * allocated from this pool. Must be a power of 2.
13654 + * @param[in] boundary Specifies the N-byte boundary that buffers allocated from
13655 + * this pool must not cross.
13656 + *
13657 + * @returns A pointer to an internal opaque structure which is not to be
13658 + * accessed outside of these library functions. Use this handle to specify
13659 + * which pools to allocate/free DMA buffers from and also to destroy the pool,
13660 + * when you are done with it.
13661 + */
13662 +extern dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, uint32_t align, uint32_t boundary);
13663 +
13664 +/**
13665 + * Destroy a DMA pool. All buffers allocated from that pool must be freed first.
13666 + */
13667 +extern void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool);
13668 +
13669 +/**
13670 + * Allocate a buffer from the specified DMA pool and zeros its contents.
13671 + */
13672 +extern void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr);
13673 +
13674 +/**
13675 + * Free a previously allocated buffer from the DMA pool.
13676 + */
13677 +extern void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr);
13678 +#endif
13679 +
13680 +/** Allocates a DMA capable buffer and zeroes its contents. */
13681 +extern void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr);
13682 +
13683 +/** Allocates a DMA capable buffer and zeroes its contents in atomic contest */
13684 +extern void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr);
13685 +
13686 +/** Frees a previously allocated buffer. */
13687 +extern void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr);
13688 +
13689 +/** Allocates a block of memory and zeroes its contents. */
13690 +extern void *__DWC_ALLOC(void *mem_ctx, uint32_t size);
13691 +
13692 +/** Allocates a block of memory and zeroes its contents, in an atomic manner
13693 + * which can be used inside interrupt context. The size should be sufficiently
13694 + * small, a few KB at most, such that failures are not likely to occur. Can just call
13695 + * __DWC_ALLOC if it is atomic. */
13696 +extern void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size);
13697 +
13698 +/** Frees a previously allocated buffer. */
13699 +extern void __DWC_FREE(void *mem_ctx, void *addr);
13700 +
13701 +#ifndef DWC_DEBUG_MEMORY
13702 +
13703 +#define DWC_ALLOC(_size_) __DWC_ALLOC(NULL, _size_)
13704 +#define DWC_ALLOC_ATOMIC(_size_) __DWC_ALLOC_ATOMIC(NULL, _size_)
13705 +#define DWC_FREE(_addr_) __DWC_FREE(NULL, _addr_)
13706 +
13707 +# ifdef DWC_LINUX
13708 +#define DWC_DMA_ALLOC(_size_,_dma_) __DWC_DMA_ALLOC(NULL, _size_, _dma_)
13709 +#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) __DWC_DMA_ALLOC_ATOMIC(NULL, _size_,_dma_)
13710 +#define DWC_DMA_FREE(_size_,_virt_,_dma_) __DWC_DMA_FREE(NULL, _size_, _virt_, _dma_)
13711 +# endif
13712 +
13713 +# if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
13714 +#define DWC_DMA_ALLOC __DWC_DMA_ALLOC
13715 +#define DWC_DMA_FREE __DWC_DMA_FREE
13716 +# endif
13717 +extern void *dwc_dma_alloc_atomic_debug(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line);
13718 +
13719 +#else /* DWC_DEBUG_MEMORY */
13720 +
13721 +extern void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line);
13722 +extern void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func, int line);
13723 +extern void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line);
13724 +extern void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
13725 + char const *func, int line);
13726 +extern void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
13727 + char const *func, int line);
13728 +extern void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr,
13729 + dwc_dma_t dma_addr, char const *func, int line);
13730 +
13731 +extern int dwc_memory_debug_start(void *mem_ctx);
13732 +extern void dwc_memory_debug_stop(void);
13733 +extern void dwc_memory_debug_report(void);
13734 +
13735 +#define DWC_ALLOC(_size_) dwc_alloc_debug(NULL, _size_, __func__, __LINE__)
13736 +#define DWC_ALLOC_ATOMIC(_size_) dwc_alloc_atomic_debug(NULL, _size_, \
13737 + __func__, __LINE__)
13738 +#define DWC_FREE(_addr_) dwc_free_debug(NULL, _addr_, __func__, __LINE__)
13739 +
13740 +# ifdef DWC_LINUX
13741 +#define DWC_DMA_ALLOC(_size_,_dma_) dwc_dma_alloc_debug(NULL, _size_, \
13742 + _dma_, __func__, __LINE__)
13743 +#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) dwc_dma_alloc_atomic_debug(NULL, _size_, \
13744 + _dma_, __func__, __LINE__)
13745 +#define DWC_DMA_FREE(_size_,_virt_,_dma_) dwc_dma_free_debug(NULL, _size_, \
13746 + _virt_, _dma_, __func__, __LINE__)
13747 +# endif
13748 +
13749 +# if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
13750 +#define DWC_DMA_ALLOC(_ctx_,_size_,_dma_) dwc_dma_alloc_debug(_ctx_, _size_, \
13751 + _dma_, __func__, __LINE__)
13752 +#define DWC_DMA_FREE(_ctx_,_size_,_virt_,_dma_) dwc_dma_free_debug(_ctx_, _size_, \
13753 + _virt_, _dma_, __func__, __LINE__)
13754 +# endif
13755 +
13756 +#endif /* DWC_DEBUG_MEMORY */
13757 +
13758 +#define dwc_alloc(_ctx_,_size_) DWC_ALLOC(_size_)
13759 +#define dwc_alloc_atomic(_ctx_,_size_) DWC_ALLOC_ATOMIC(_size_)
13760 +#define dwc_free(_ctx_,_addr_) DWC_FREE(_addr_)
13761 +
13762 +#ifdef DWC_LINUX
13763 +/* Linux doesn't need any extra parameters for DMA buffer allocation, so we
13764 + * just throw away the DMA context parameter.
13765 + */
13766 +#define dwc_dma_alloc(_ctx_,_size_,_dma_) DWC_DMA_ALLOC(_size_, _dma_)
13767 +#define dwc_dma_alloc_atomic(_ctx_,_size_,_dma_) DWC_DMA_ALLOC_ATOMIC(_size_, _dma_)
13768 +#define dwc_dma_free(_ctx_,_size_,_virt_,_dma_) DWC_DMA_FREE(_size_, _virt_, _dma_)
13769 +#endif
13770 +
13771 +#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
13772 +/** BSD needs several extra parameters for DMA buffer allocation, so we pass
13773 + * them in using the DMA context parameter.
13774 + */
13775 +#define dwc_dma_alloc DWC_DMA_ALLOC
13776 +#define dwc_dma_free DWC_DMA_FREE
13777 +#endif
13778 +
13779 +
13780 +/** @name Memory and String Processing */
13781 +
13782 +/** memset() clone */
13783 +extern void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size);
13784 +#define dwc_memset DWC_MEMSET
13785 +
13786 +/** memcpy() clone */
13787 +extern void *DWC_MEMCPY(void *dest, void const *src, uint32_t size);
13788 +#define dwc_memcpy DWC_MEMCPY
13789 +
13790 +/** memmove() clone */
13791 +extern void *DWC_MEMMOVE(void *dest, void *src, uint32_t size);
13792 +#define dwc_memmove DWC_MEMMOVE
13793 +
13794 +/** memcmp() clone */
13795 +extern int DWC_MEMCMP(void *m1, void *m2, uint32_t size);
13796 +#define dwc_memcmp DWC_MEMCMP
13797 +
13798 +/** strcmp() clone */
13799 +extern int DWC_STRCMP(void *s1, void *s2);
13800 +#define dwc_strcmp DWC_STRCMP
13801 +
13802 +/** strncmp() clone */
13803 +extern int DWC_STRNCMP(void *s1, void *s2, uint32_t size);
13804 +#define dwc_strncmp DWC_STRNCMP
13805 +
13806 +/** strlen() clone, for NULL terminated ASCII strings */
13807 +extern int DWC_STRLEN(char const *str);
13808 +#define dwc_strlen DWC_STRLEN
13809 +
13810 +/** strcpy() clone, for NULL terminated ASCII strings */
13811 +extern char *DWC_STRCPY(char *to, const char *from);
13812 +#define dwc_strcpy DWC_STRCPY
13813 +
13814 +/** strdup() clone. If you wish to use memory allocation debugging, this
13815 + * implementation of strdup should use the DWC_* memory routines instead of
13816 + * calling a predefined strdup. Otherwise the memory allocated by this routine
13817 + * will not be seen by the debugging routines. */
13818 +extern char *DWC_STRDUP(char const *str);
13819 +#define dwc_strdup(_ctx_,_str_) DWC_STRDUP(_str_)
13820 +
13821 +/** NOT an atoi() clone. Read the description carefully. Returns an integer
13822 + * converted from the string str in base 10 unless the string begins with a "0x"
13823 + * in which case it is base 16. String must be a NULL terminated sequence of
13824 + * ASCII characters and may optionally begin with whitespace, a + or -, and a
13825 + * "0x" prefix if base 16. The remaining characters must be valid digits for
13826 + * the number and end with a NULL character. If any invalid characters are
13827 + * encountered or it returns with a negative error code and the results of the
13828 + * conversion are undefined. On sucess it returns 0. Overflow conditions are
13829 + * undefined. An example implementation using atoi() can be referenced from the
13830 + * Linux implementation. */
13831 +extern int DWC_ATOI(const char *str, int32_t *value);
13832 +#define dwc_atoi DWC_ATOI
13833 +
13834 +/** Same as above but for unsigned. */
13835 +extern int DWC_ATOUI(const char *str, uint32_t *value);
13836 +#define dwc_atoui DWC_ATOUI
13837 +
13838 +#ifdef DWC_UTFLIB
13839 +/** This routine returns a UTF16LE unicode encoded string from a UTF8 string. */
13840 +extern int DWC_UTF8_TO_UTF16LE(uint8_t const *utf8string, uint16_t *utf16string, unsigned len);
13841 +#define dwc_utf8_to_utf16le DWC_UTF8_TO_UTF16LE
13842 +#endif
13843 +
13844 +
13845 +/** @name Wait queues
13846 + *
13847 + * Wait queues provide a means of synchronizing between threads or processes. A
13848 + * process can block on a waitq if some condition is not true, waiting for it to
13849 + * become true. When the waitq is triggered all waiting process will get
13850 + * unblocked and the condition will be check again. Waitqs should be triggered
13851 + * every time a condition can potentially change.*/
13852 +struct dwc_waitq;
13853 +
13854 +/** Type for a waitq */
13855 +typedef struct dwc_waitq dwc_waitq_t;
13856 +
13857 +/** The type of waitq condition callback function. This is called every time
13858 + * condition is evaluated. */
13859 +typedef int (*dwc_waitq_condition_t)(void *data);
13860 +
13861 +/** Allocate a waitq */
13862 +extern dwc_waitq_t *DWC_WAITQ_ALLOC(void);
13863 +#define dwc_waitq_alloc(_ctx_) DWC_WAITQ_ALLOC()
13864 +
13865 +/** Free a waitq */
13866 +extern void DWC_WAITQ_FREE(dwc_waitq_t *wq);
13867 +#define dwc_waitq_free DWC_WAITQ_FREE
13868 +
13869 +/** Check the condition and if it is false, block on the waitq. When unblocked, check the
13870 + * condition again. The function returns when the condition becomes true. The return value
13871 + * is 0 on condition true, DWC_WAITQ_ABORTED on abort or killed, or DWC_WAITQ_UNKNOWN on error. */
13872 +extern int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data);
13873 +#define dwc_waitq_wait DWC_WAITQ_WAIT
13874 +
13875 +/** Check the condition and if it is false, block on the waitq. When unblocked,
13876 + * check the condition again. The function returns when the condition become
13877 + * true or the timeout has passed. The return value is 0 on condition true or
13878 + * DWC_TIMED_OUT on timeout, or DWC_WAITQ_ABORTED, or DWC_WAITQ_UNKNOWN on
13879 + * error. */
13880 +extern int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
13881 + void *data, int32_t msecs);
13882 +#define dwc_waitq_wait_timeout DWC_WAITQ_WAIT_TIMEOUT
13883 +
13884 +/** Trigger a waitq, unblocking all processes. This should be called whenever a condition
13885 + * has potentially changed. */
13886 +extern void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq);
13887 +#define dwc_waitq_trigger DWC_WAITQ_TRIGGER
13888 +
13889 +/** Unblock all processes waiting on the waitq with an ABORTED result. */
13890 +extern void DWC_WAITQ_ABORT(dwc_waitq_t *wq);
13891 +#define dwc_waitq_abort DWC_WAITQ_ABORT
13892 +
13893 +
13894 +/** @name Threads
13895 + *
13896 + * A thread must be explicitly stopped. It must check DWC_THREAD_SHOULD_STOP
13897 + * whenever it is woken up, and then return. The DWC_THREAD_STOP function
13898 + * returns the value from the thread.
13899 + */
13900 +
13901 +struct dwc_thread;
13902 +
13903 +/** Type for a thread */
13904 +typedef struct dwc_thread dwc_thread_t;
13905 +
13906 +/** The thread function */
13907 +typedef int (*dwc_thread_function_t)(void *data);
13908 +
13909 +/** Create a thread and start it running the thread_function. Returns a handle
13910 + * to the thread */
13911 +extern dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data);
13912 +#define dwc_thread_run(_ctx_,_func_,_name_,_data_) DWC_THREAD_RUN(_func_, _name_, _data_)
13913 +
13914 +/** Stops a thread. Return the value returned by the thread. Or will return
13915 + * DWC_ABORT if the thread never started. */
13916 +extern int DWC_THREAD_STOP(dwc_thread_t *thread);
13917 +#define dwc_thread_stop DWC_THREAD_STOP
13918 +
13919 +/** Signifies to the thread that it must stop. */
13920 +#ifdef DWC_LINUX
13921 +/* Linux doesn't need any parameters for kthread_should_stop() */
13922 +extern dwc_bool_t DWC_THREAD_SHOULD_STOP(void);
13923 +#define dwc_thread_should_stop(_thrd_) DWC_THREAD_SHOULD_STOP()
13924 +
13925 +/* No thread_exit function in Linux */
13926 +#define dwc_thread_exit(_thrd_)
13927 +#endif
13928 +
13929 +#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
13930 +/** BSD needs the thread pointer for kthread_suspend_check() */
13931 +extern dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread);
13932 +#define dwc_thread_should_stop DWC_THREAD_SHOULD_STOP
13933 +
13934 +/** The thread must call this to exit. */
13935 +extern void DWC_THREAD_EXIT(dwc_thread_t *thread);
13936 +#define dwc_thread_exit DWC_THREAD_EXIT
13937 +#endif
13938 +
13939 +
13940 +/** @name Work queues
13941 + *
13942 + * Workqs are used to queue a callback function to be called at some later time,
13943 + * in another thread. */
13944 +struct dwc_workq;
13945 +
13946 +/** Type for a workq */
13947 +typedef struct dwc_workq dwc_workq_t;
13948 +
13949 +/** The type of the callback function to be called. */
13950 +typedef void (*dwc_work_callback_t)(void *data);
13951 +
13952 +/** Allocate a workq */
13953 +extern dwc_workq_t *DWC_WORKQ_ALLOC(char *name);
13954 +#define dwc_workq_alloc(_ctx_,_name_) DWC_WORKQ_ALLOC(_name_)
13955 +
13956 +/** Free a workq. All work must be completed before being freed. */
13957 +extern void DWC_WORKQ_FREE(dwc_workq_t *workq);
13958 +#define dwc_workq_free DWC_WORKQ_FREE
13959 +
13960 +/** Schedule a callback on the workq, passing in data. The function will be
13961 + * scheduled at some later time. */
13962 +extern void DWC_WORKQ_SCHEDULE(dwc_workq_t *workq, dwc_work_callback_t cb,
13963 + void *data, char *format, ...)
13964 +#ifdef __GNUC__
13965 + __attribute__ ((format(printf, 4, 5)));
13966 +#else
13967 + ;
13968 +#endif
13969 +#define dwc_workq_schedule DWC_WORKQ_SCHEDULE
13970 +
13971 +/** Schedule a callback on the workq, that will be called until at least
13972 + * given number miliseconds have passed. */
13973 +extern void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *workq, dwc_work_callback_t cb,
13974 + void *data, uint32_t time, char *format, ...)
13975 +#ifdef __GNUC__
13976 + __attribute__ ((format(printf, 5, 6)));
13977 +#else
13978 + ;
13979 +#endif
13980 +#define dwc_workq_schedule_delayed DWC_WORKQ_SCHEDULE_DELAYED
13981 +
13982 +/** The number of processes in the workq */
13983 +extern int DWC_WORKQ_PENDING(dwc_workq_t *workq);
13984 +#define dwc_workq_pending DWC_WORKQ_PENDING
13985 +
13986 +/** Blocks until all the work in the workq is complete or timed out. Returns <
13987 + * 0 on timeout. */
13988 +extern int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout);
13989 +#define dwc_workq_wait_work_done DWC_WORKQ_WAIT_WORK_DONE
13990 +
13991 +
13992 +/** @name Tasklets
13993 + *
13994 + */
13995 +struct dwc_tasklet;
13996 +
13997 +/** Type for a tasklet */
13998 +typedef struct dwc_tasklet dwc_tasklet_t;
13999 +
14000 +/** The type of the callback function to be called */
14001 +typedef void (*dwc_tasklet_callback_t)(void *data);
14002 +
14003 +/** Allocates a tasklet */
14004 +extern dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data);
14005 +#define dwc_task_alloc(_ctx_,_name_,_cb_,_data_) DWC_TASK_ALLOC(_name_, _cb_, _data_)
14006 +
14007 +/** Frees a tasklet */
14008 +extern void DWC_TASK_FREE(dwc_tasklet_t *task);
14009 +#define dwc_task_free DWC_TASK_FREE
14010 +
14011 +/** Schedules a tasklet to run */
14012 +extern void DWC_TASK_SCHEDULE(dwc_tasklet_t *task);
14013 +#define dwc_task_schedule DWC_TASK_SCHEDULE
14014 +
14015 +extern void DWC_TASK_HI_SCHEDULE(dwc_tasklet_t *task);
14016 +#define dwc_task_hi_schedule DWC_TASK_HI_SCHEDULE
14017 +
14018 +/** @name Timer
14019 + *
14020 + * Callbacks must be small and atomic.
14021 + */
14022 +struct dwc_timer;
14023 +
14024 +/** Type for a timer */
14025 +typedef struct dwc_timer dwc_timer_t;
14026 +
14027 +/** The type of the callback function to be called */
14028 +typedef void (*dwc_timer_callback_t)(void *data);
14029 +
14030 +/** Allocates a timer */
14031 +extern dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data);
14032 +#define dwc_timer_alloc(_ctx_,_name_,_cb_,_data_) DWC_TIMER_ALLOC(_name_,_cb_,_data_)
14033 +
14034 +/** Frees a timer */
14035 +extern void DWC_TIMER_FREE(dwc_timer_t *timer);
14036 +#define dwc_timer_free DWC_TIMER_FREE
14037 +
14038 +/** Schedules the timer to run at time ms from now. And will repeat at every
14039 + * repeat_interval msec therafter
14040 + *
14041 + * Modifies a timer that is still awaiting execution to a new expiration time.
14042 + * The mod_time is added to the old time. */
14043 +extern void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time);
14044 +#define dwc_timer_schedule DWC_TIMER_SCHEDULE
14045 +
14046 +/** Disables the timer from execution. */
14047 +extern void DWC_TIMER_CANCEL(dwc_timer_t *timer);
14048 +#define dwc_timer_cancel DWC_TIMER_CANCEL
14049 +
14050 +
14051 +/** @name Spinlocks
14052 + *
14053 + * These locks are used when the work between the lock/unlock is atomic and
14054 + * short. Interrupts are also disabled during the lock/unlock and thus they are
14055 + * suitable to lock between interrupt/non-interrupt context. They also lock
14056 + * between processes if you have multiple CPUs or Preemption. If you don't have
14057 + * multiple CPUS or Preemption, then the you can simply implement the
14058 + * DWC_SPINLOCK and DWC_SPINUNLOCK to disable and enable interrupts. Because
14059 + * the work between the lock/unlock is atomic, the process context will never
14060 + * change, and so you never have to lock between processes. */
14061 +
14062 +struct dwc_spinlock;
14063 +
14064 +/** Type for a spinlock */
14065 +typedef struct dwc_spinlock dwc_spinlock_t;
14066 +
14067 +/** Type for the 'flags' argument to spinlock funtions */
14068 +typedef unsigned long dwc_irqflags_t;
14069 +
14070 +/** Returns an initialized lock variable. This function should allocate and
14071 + * initialize the OS-specific data structure used for locking. This data
14072 + * structure is to be used for the DWC_LOCK and DWC_UNLOCK functions and should
14073 + * be freed by the DWC_FREE_LOCK when it is no longer used.
14074 + *
14075 + * For Linux Spinlock Debugging make it macro because the debugging routines use
14076 + * the symbol name to determine recursive locking. Using a wrapper function
14077 + * makes it falsely think recursive locking occurs. */
14078 +#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)
14079 +#define DWC_SPINLOCK_ALLOC_LINUX_DEBUG(lock) ({ \
14080 + lock = DWC_ALLOC(sizeof(spinlock_t)); \
14081 + if (lock) { \
14082 + spin_lock_init((spinlock_t *)lock); \
14083 + } \
14084 +})
14085 +#else
14086 +extern dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void);
14087 +#define dwc_spinlock_alloc(_ctx_) DWC_SPINLOCK_ALLOC()
14088 +#endif
14089 +
14090 +/** Frees an initialized lock variable. */
14091 +extern void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock);
14092 +#define dwc_spinlock_free(_ctx_,_lock_) DWC_SPINLOCK_FREE(_lock_)
14093 +
14094 +/** Disables interrupts and blocks until it acquires the lock.
14095 + *
14096 + * @param lock Pointer to the spinlock.
14097 + * @param flags Unsigned long for irq flags storage.
14098 + */
14099 +extern void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags);
14100 +#define dwc_spinlock_irqsave DWC_SPINLOCK_IRQSAVE
14101 +
14102 +/** Re-enables the interrupt and releases the lock.
14103 + *
14104 + * @param lock Pointer to the spinlock.
14105 + * @param flags Unsigned long for irq flags storage. Must be the same as was
14106 + * passed into DWC_LOCK.
14107 + */
14108 +extern void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags);
14109 +#define dwc_spinunlock_irqrestore DWC_SPINUNLOCK_IRQRESTORE
14110 +
14111 +/** Blocks until it acquires the lock.
14112 + *
14113 + * @param lock Pointer to the spinlock.
14114 + */
14115 +extern void DWC_SPINLOCK(dwc_spinlock_t *lock);
14116 +#define dwc_spinlock DWC_SPINLOCK
14117 +
14118 +/** Releases the lock.
14119 + *
14120 + * @param lock Pointer to the spinlock.
14121 + */
14122 +extern void DWC_SPINUNLOCK(dwc_spinlock_t *lock);
14123 +#define dwc_spinunlock DWC_SPINUNLOCK
14124 +
14125 +
14126 +/** @name Mutexes
14127 + *
14128 + * Unlike spinlocks Mutexes lock only between processes and the work between the
14129 + * lock/unlock CAN block, therefore it CANNOT be called from interrupt context.
14130 + */
14131 +
14132 +struct dwc_mutex;
14133 +
14134 +/** Type for a mutex */
14135 +typedef struct dwc_mutex dwc_mutex_t;
14136 +
14137 +/* For Linux Mutex Debugging make it inline because the debugging routines use
14138 + * the symbol to determine recursive locking. This makes it falsely think
14139 + * recursive locking occurs. */
14140 +#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)
14141 +#define DWC_MUTEX_ALLOC_LINUX_DEBUG(__mutexp) ({ \
14142 + __mutexp = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex)); \
14143 + mutex_init((struct mutex *)__mutexp); \
14144 +})
14145 +#endif
14146 +
14147 +/** Allocate a mutex */
14148 +extern dwc_mutex_t *DWC_MUTEX_ALLOC(void);
14149 +#define dwc_mutex_alloc(_ctx_) DWC_MUTEX_ALLOC()
14150 +
14151 +/* For memory leak debugging when using Linux Mutex Debugging */
14152 +#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)
14153 +#define DWC_MUTEX_FREE(__mutexp) do { \
14154 + mutex_destroy((struct mutex *)__mutexp); \
14155 + DWC_FREE(__mutexp); \
14156 +} while(0)
14157 +#else
14158 +/** Free a mutex */
14159 +extern void DWC_MUTEX_FREE(dwc_mutex_t *mutex);
14160 +#define dwc_mutex_free(_ctx_,_mutex_) DWC_MUTEX_FREE(_mutex_)
14161 +#endif
14162 +
14163 +/** Lock a mutex */
14164 +extern void DWC_MUTEX_LOCK(dwc_mutex_t *mutex);
14165 +#define dwc_mutex_lock DWC_MUTEX_LOCK
14166 +
14167 +/** Non-blocking lock returns 1 on successful lock. */
14168 +extern int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex);
14169 +#define dwc_mutex_trylock DWC_MUTEX_TRYLOCK
14170 +
14171 +/** Unlock a mutex */
14172 +extern void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex);
14173 +#define dwc_mutex_unlock DWC_MUTEX_UNLOCK
14174 +
14175 +
14176 +/** @name Time */
14177 +
14178 +/** Microsecond delay.
14179 + *
14180 + * @param usecs Microseconds to delay.
14181 + */
14182 +extern void DWC_UDELAY(uint32_t usecs);
14183 +#define dwc_udelay DWC_UDELAY
14184 +
14185 +/** Millisecond delay.
14186 + *
14187 + * @param msecs Milliseconds to delay.
14188 + */
14189 +extern void DWC_MDELAY(uint32_t msecs);
14190 +#define dwc_mdelay DWC_MDELAY
14191 +
14192 +/** Non-busy waiting.
14193 + * Sleeps for specified number of milliseconds.
14194 + *
14195 + * @param msecs Milliseconds to sleep.
14196 + */
14197 +extern void DWC_MSLEEP(uint32_t msecs);
14198 +#define dwc_msleep DWC_MSLEEP
14199 +
14200 +/**
14201 + * Returns number of milliseconds since boot.
14202 + */
14203 +extern uint32_t DWC_TIME(void);
14204 +#define dwc_time DWC_TIME
14205 +
14206 +
14207 +
14208 +
14209 +/* @mainpage DWC Portability and Common Library
14210 + *
14211 + * This is the documentation for the DWC Portability and Common Library.
14212 + *
14213 + * @section intro Introduction
14214 + *
14215 + * The DWC Portability library consists of wrapper calls and data structures to
14216 + * all low-level functions which are typically provided by the OS. The WUDEV
14217 + * driver uses only these functions. In order to port the WUDEV driver, only
14218 + * the functions in this library need to be re-implemented, with the same
14219 + * behavior as documented here.
14220 + *
14221 + * The Common library consists of higher level functions, which rely only on
14222 + * calling the functions from the DWC Portability library. These common
14223 + * routines are shared across modules. Some of the common libraries need to be
14224 + * used directly by the driver programmer when porting WUDEV. Such as the
14225 + * parameter and notification libraries.
14226 + *
14227 + * @section low Portability Library OS Wrapper Functions
14228 + *
14229 + * Any function starting with DWC and in all CAPS is a low-level OS-wrapper that
14230 + * needs to be implemented when porting, for example DWC_MUTEX_ALLOC(). All of
14231 + * these functions are included in the dwc_os.h file.
14232 + *
14233 + * There are many functions here covering a wide array of OS services. Please
14234 + * see dwc_os.h for details, and implementation notes for each function.
14235 + *
14236 + * @section common Common Library Functions
14237 + *
14238 + * Any function starting with dwc and in all lowercase is a common library
14239 + * routine. These functions have a portable implementation and do not need to
14240 + * be reimplemented when porting. The common routines can be used by any
14241 + * driver, and some must be used by the end user to control the drivers. For
14242 + * example, you must use the Parameter common library in order to set the
14243 + * parameters in the WUDEV module.
14244 + *
14245 + * The common libraries consist of the following:
14246 + *
14247 + * - Connection Contexts - Used internally and can be used by end-user. See dwc_cc.h
14248 + * - Parameters - Used internally and can be used by end-user. See dwc_params.h
14249 + * - Notifications - Used internally and can be used by end-user. See dwc_notifier.h
14250 + * - Lists - Used internally and can be used by end-user. See dwc_list.h
14251 + * - Memory Debugging - Used internally and can be used by end-user. See dwc_os.h
14252 + * - Modpow - Used internally only. See dwc_modpow.h
14253 + * - DH - Used internally only. See dwc_dh.h
14254 + * - Crypto - Used internally only. See dwc_crypto.h
14255 + *
14256 + *
14257 + * @section prereq Prerequistes For dwc_os.h
14258 + * @subsection types Data Types
14259 + *
14260 + * The dwc_os.h file assumes that several low-level data types are pre defined for the
14261 + * compilation environment. These data types are:
14262 + *
14263 + * - uint8_t - unsigned 8-bit data type
14264 + * - int8_t - signed 8-bit data type
14265 + * - uint16_t - unsigned 16-bit data type
14266 + * - int16_t - signed 16-bit data type
14267 + * - uint32_t - unsigned 32-bit data type
14268 + * - int32_t - signed 32-bit data type
14269 + * - uint64_t - unsigned 64-bit data type
14270 + * - int64_t - signed 64-bit data type
14271 + *
14272 + * Ensure that these are defined before using dwc_os.h. The easiest way to do
14273 + * that is to modify the top of the file to include the appropriate header.
14274 + * This is already done for the Linux environment. If the DWC_LINUX macro is
14275 + * defined, the correct header will be added. A standard header <stdint.h> is
14276 + * also used for environments where standard C headers are available.
14277 + *
14278 + * @subsection stdarg Variable Arguments
14279 + *
14280 + * Variable arguments are provided by a standard C header <stdarg.h>. it is
14281 + * available in Both the Linux and ANSI C enviornment. An equivalent must be
14282 + * provided in your enviornment in order to use dwc_os.h with the debug and
14283 + * tracing message functionality.
14284 + *
14285 + * @subsection thread Threading
14286 + *
14287 + * WUDEV Core must be run on an operating system that provides for multiple
14288 + * threads/processes. Threading can be implemented in many ways, even in
14289 + * embedded systems without an operating system. At the bare minimum, the
14290 + * system should be able to start any number of processes at any time to handle
14291 + * special work. It need not be a pre-emptive system. Process context can
14292 + * change upon a call to a blocking function. The hardware interrupt context
14293 + * that calls the module's ISR() function must be differentiable from process
14294 + * context, even if your processes are impemented via a hardware interrupt.
14295 + * Further locking mechanism between process must exist (or be implemented), and
14296 + * process context must have a way to disable interrupts for a period of time to
14297 + * lock them out. If all of this exists, the functions in dwc_os.h related to
14298 + * threading should be able to be implemented with the defined behavior.
14299 + *
14300 + */
14301 +
14302 +#ifdef __cplusplus
14303 +}
14304 +#endif
14305 +
14306 +#endif /* _DWC_OS_H_ */
14307 --- /dev/null
14308 +++ b/drivers/usb/host/dwc_common_port/usb.h
14309 @@ -0,0 +1,946 @@
14310 +/*
14311 + * Copyright (c) 1998 The NetBSD Foundation, Inc.
14312 + * All rights reserved.
14313 + *
14314 + * This code is derived from software contributed to The NetBSD Foundation
14315 + * by Lennart Augustsson (lennart@augustsson.net) at
14316 + * Carlstedt Research & Technology.
14317 + *
14318 + * Redistribution and use in source and binary forms, with or without
14319 + * modification, are permitted provided that the following conditions
14320 + * are met:
14321 + * 1. Redistributions of source code must retain the above copyright
14322 + * notice, this list of conditions and the following disclaimer.
14323 + * 2. Redistributions in binary form must reproduce the above copyright
14324 + * notice, this list of conditions and the following disclaimer in the
14325 + * documentation and/or other materials provided with the distribution.
14326 + * 3. All advertising materials mentioning features or use of this software
14327 + * must display the following acknowledgement:
14328 + * This product includes software developed by the NetBSD
14329 + * Foundation, Inc. and its contributors.
14330 + * 4. Neither the name of The NetBSD Foundation nor the names of its
14331 + * contributors may be used to endorse or promote products derived
14332 + * from this software without specific prior written permission.
14333 + *
14334 + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
14335 + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
14336 + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
14337 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
14338 + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
14339 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
14340 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
14341 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
14342 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
14343 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
14344 + * POSSIBILITY OF SUCH DAMAGE.
14345 + */
14346 +
14347 +/* Modified by Synopsys, Inc, 12/12/2007 */
14348 +
14349 +
14350 +#ifndef _USB_H_
14351 +#define _USB_H_
14352 +
14353 +#ifdef __cplusplus
14354 +extern "C" {
14355 +#endif
14356 +
14357 +/*
14358 + * The USB records contain some unaligned little-endian word
14359 + * components. The U[SG]ETW macros take care of both the alignment
14360 + * and endian problem and should always be used to access non-byte
14361 + * values.
14362 + */
14363 +typedef u_int8_t uByte;
14364 +typedef u_int8_t uWord[2];
14365 +typedef u_int8_t uDWord[4];
14366 +
14367 +#define USETW2(w,h,l) ((w)[0] = (u_int8_t)(l), (w)[1] = (u_int8_t)(h))
14368 +#define UCONSTW(x) { (x) & 0xff, ((x) >> 8) & 0xff }
14369 +#define UCONSTDW(x) { (x) & 0xff, ((x) >> 8) & 0xff, \
14370 + ((x) >> 16) & 0xff, ((x) >> 24) & 0xff }
14371 +
14372 +#if 1
14373 +#define UGETW(w) ((w)[0] | ((w)[1] << 8))
14374 +#define USETW(w,v) ((w)[0] = (u_int8_t)(v), (w)[1] = (u_int8_t)((v) >> 8))
14375 +#define UGETDW(w) ((w)[0] | ((w)[1] << 8) | ((w)[2] << 16) | ((w)[3] << 24))
14376 +#define USETDW(w,v) ((w)[0] = (u_int8_t)(v), \
14377 + (w)[1] = (u_int8_t)((v) >> 8), \
14378 + (w)[2] = (u_int8_t)((v) >> 16), \
14379 + (w)[3] = (u_int8_t)((v) >> 24))
14380 +#else
14381 +/*
14382 + * On little-endian machines that can handle unanliged accesses
14383 + * (e.g. i386) these macros can be replaced by the following.
14384 + */
14385 +#define UGETW(w) (*(u_int16_t *)(w))
14386 +#define USETW(w,v) (*(u_int16_t *)(w) = (v))
14387 +#define UGETDW(w) (*(u_int32_t *)(w))
14388 +#define USETDW(w,v) (*(u_int32_t *)(w) = (v))
14389 +#endif
14390 +
14391 +/*
14392 + * Macros for accessing UAS IU fields, which are big-endian
14393 + */
14394 +#define IUSETW2(w,h,l) ((w)[0] = (u_int8_t)(h), (w)[1] = (u_int8_t)(l))
14395 +#define IUCONSTW(x) { ((x) >> 8) & 0xff, (x) & 0xff }
14396 +#define IUCONSTDW(x) { ((x) >> 24) & 0xff, ((x) >> 16) & 0xff, \
14397 + ((x) >> 8) & 0xff, (x) & 0xff }
14398 +#define IUGETW(w) (((w)[0] << 8) | (w)[1])
14399 +#define IUSETW(w,v) ((w)[0] = (u_int8_t)((v) >> 8), (w)[1] = (u_int8_t)(v))
14400 +#define IUGETDW(w) (((w)[0] << 24) | ((w)[1] << 16) | ((w)[2] << 8) | (w)[3])
14401 +#define IUSETDW(w,v) ((w)[0] = (u_int8_t)((v) >> 24), \
14402 + (w)[1] = (u_int8_t)((v) >> 16), \
14403 + (w)[2] = (u_int8_t)((v) >> 8), \
14404 + (w)[3] = (u_int8_t)(v))
14405 +
14406 +#define UPACKED __attribute__((__packed__))
14407 +
14408 +typedef struct {
14409 + uByte bmRequestType;
14410 + uByte bRequest;
14411 + uWord wValue;
14412 + uWord wIndex;
14413 + uWord wLength;
14414 +} UPACKED usb_device_request_t;
14415 +
14416 +#define UT_GET_DIR(a) ((a) & 0x80)
14417 +#define UT_WRITE 0x00
14418 +#define UT_READ 0x80
14419 +
14420 +#define UT_GET_TYPE(a) ((a) & 0x60)
14421 +#define UT_STANDARD 0x00
14422 +#define UT_CLASS 0x20
14423 +#define UT_VENDOR 0x40
14424 +
14425 +#define UT_GET_RECIPIENT(a) ((a) & 0x1f)
14426 +#define UT_DEVICE 0x00
14427 +#define UT_INTERFACE 0x01
14428 +#define UT_ENDPOINT 0x02
14429 +#define UT_OTHER 0x03
14430 +
14431 +#define UT_READ_DEVICE (UT_READ | UT_STANDARD | UT_DEVICE)
14432 +#define UT_READ_INTERFACE (UT_READ | UT_STANDARD | UT_INTERFACE)
14433 +#define UT_READ_ENDPOINT (UT_READ | UT_STANDARD | UT_ENDPOINT)
14434 +#define UT_WRITE_DEVICE (UT_WRITE | UT_STANDARD | UT_DEVICE)
14435 +#define UT_WRITE_INTERFACE (UT_WRITE | UT_STANDARD | UT_INTERFACE)
14436 +#define UT_WRITE_ENDPOINT (UT_WRITE | UT_STANDARD | UT_ENDPOINT)
14437 +#define UT_READ_CLASS_DEVICE (UT_READ | UT_CLASS | UT_DEVICE)
14438 +#define UT_READ_CLASS_INTERFACE (UT_READ | UT_CLASS | UT_INTERFACE)
14439 +#define UT_READ_CLASS_OTHER (UT_READ | UT_CLASS | UT_OTHER)
14440 +#define UT_READ_CLASS_ENDPOINT (UT_READ | UT_CLASS | UT_ENDPOINT)
14441 +#define UT_WRITE_CLASS_DEVICE (UT_WRITE | UT_CLASS | UT_DEVICE)
14442 +#define UT_WRITE_CLASS_INTERFACE (UT_WRITE | UT_CLASS | UT_INTERFACE)
14443 +#define UT_WRITE_CLASS_OTHER (UT_WRITE | UT_CLASS | UT_OTHER)
14444 +#define UT_WRITE_CLASS_ENDPOINT (UT_WRITE | UT_CLASS | UT_ENDPOINT)
14445 +#define UT_READ_VENDOR_DEVICE (UT_READ | UT_VENDOR | UT_DEVICE)
14446 +#define UT_READ_VENDOR_INTERFACE (UT_READ | UT_VENDOR | UT_INTERFACE)
14447 +#define UT_READ_VENDOR_OTHER (UT_READ | UT_VENDOR | UT_OTHER)
14448 +#define UT_READ_VENDOR_ENDPOINT (UT_READ | UT_VENDOR | UT_ENDPOINT)
14449 +#define UT_WRITE_VENDOR_DEVICE (UT_WRITE | UT_VENDOR | UT_DEVICE)
14450 +#define UT_WRITE_VENDOR_INTERFACE (UT_WRITE | UT_VENDOR | UT_INTERFACE)
14451 +#define UT_WRITE_VENDOR_OTHER (UT_WRITE | UT_VENDOR | UT_OTHER)
14452 +#define UT_WRITE_VENDOR_ENDPOINT (UT_WRITE | UT_VENDOR | UT_ENDPOINT)
14453 +
14454 +/* Requests */
14455 +#define UR_GET_STATUS 0x00
14456 +#define USTAT_STANDARD_STATUS 0x00
14457 +#define WUSTAT_WUSB_FEATURE 0x01
14458 +#define WUSTAT_CHANNEL_INFO 0x02
14459 +#define WUSTAT_RECEIVED_DATA 0x03
14460 +#define WUSTAT_MAS_AVAILABILITY 0x04
14461 +#define WUSTAT_CURRENT_TRANSMIT_POWER 0x05
14462 +#define UR_CLEAR_FEATURE 0x01
14463 +#define UR_SET_FEATURE 0x03
14464 +#define UR_SET_AND_TEST_FEATURE 0x0c
14465 +#define UR_SET_ADDRESS 0x05
14466 +#define UR_GET_DESCRIPTOR 0x06
14467 +#define UDESC_DEVICE 0x01
14468 +#define UDESC_CONFIG 0x02
14469 +#define UDESC_STRING 0x03
14470 +#define UDESC_INTERFACE 0x04
14471 +#define UDESC_ENDPOINT 0x05
14472 +#define UDESC_SS_USB_COMPANION 0x30
14473 +#define UDESC_DEVICE_QUALIFIER 0x06
14474 +#define UDESC_OTHER_SPEED_CONFIGURATION 0x07
14475 +#define UDESC_INTERFACE_POWER 0x08
14476 +#define UDESC_OTG 0x09
14477 +#define WUDESC_SECURITY 0x0c
14478 +#define WUDESC_KEY 0x0d
14479 +#define WUD_GET_KEY_INDEX(_wValue_) ((_wValue_) & 0xf)
14480 +#define WUD_GET_KEY_TYPE(_wValue_) (((_wValue_) & 0x30) >> 4)
14481 +#define WUD_KEY_TYPE_ASSOC 0x01
14482 +#define WUD_KEY_TYPE_GTK 0x02
14483 +#define WUD_GET_KEY_ORIGIN(_wValue_) (((_wValue_) & 0x40) >> 6)
14484 +#define WUD_KEY_ORIGIN_HOST 0x00
14485 +#define WUD_KEY_ORIGIN_DEVICE 0x01
14486 +#define WUDESC_ENCRYPTION_TYPE 0x0e
14487 +#define WUDESC_BOS 0x0f
14488 +#define WUDESC_DEVICE_CAPABILITY 0x10
14489 +#define WUDESC_WIRELESS_ENDPOINT_COMPANION 0x11
14490 +#define UDESC_BOS 0x0f
14491 +#define UDESC_DEVICE_CAPABILITY 0x10
14492 +#define UDESC_CS_DEVICE 0x21 /* class specific */
14493 +#define UDESC_CS_CONFIG 0x22
14494 +#define UDESC_CS_STRING 0x23
14495 +#define UDESC_CS_INTERFACE 0x24
14496 +#define UDESC_CS_ENDPOINT 0x25
14497 +#define UDESC_HUB 0x29
14498 +#define UR_SET_DESCRIPTOR 0x07
14499 +#define UR_GET_CONFIG 0x08
14500 +#define UR_SET_CONFIG 0x09
14501 +#define UR_GET_INTERFACE 0x0a
14502 +#define UR_SET_INTERFACE 0x0b
14503 +#define UR_SYNCH_FRAME 0x0c
14504 +#define WUR_SET_ENCRYPTION 0x0d
14505 +#define WUR_GET_ENCRYPTION 0x0e
14506 +#define WUR_SET_HANDSHAKE 0x0f
14507 +#define WUR_GET_HANDSHAKE 0x10
14508 +#define WUR_SET_CONNECTION 0x11
14509 +#define WUR_SET_SECURITY_DATA 0x12
14510 +#define WUR_GET_SECURITY_DATA 0x13
14511 +#define WUR_SET_WUSB_DATA 0x14
14512 +#define WUDATA_DRPIE_INFO 0x01
14513 +#define WUDATA_TRANSMIT_DATA 0x02
14514 +#define WUDATA_TRANSMIT_PARAMS 0x03
14515 +#define WUDATA_RECEIVE_PARAMS 0x04
14516 +#define WUDATA_TRANSMIT_POWER 0x05
14517 +#define WUR_LOOPBACK_DATA_WRITE 0x15
14518 +#define WUR_LOOPBACK_DATA_READ 0x16
14519 +#define WUR_SET_INTERFACE_DS 0x17
14520 +
14521 +/* Feature numbers */
14522 +#define UF_ENDPOINT_HALT 0
14523 +#define UF_DEVICE_REMOTE_WAKEUP 1
14524 +#define UF_TEST_MODE 2
14525 +#define UF_DEVICE_B_HNP_ENABLE 3
14526 +#define UF_DEVICE_A_HNP_SUPPORT 4
14527 +#define UF_DEVICE_A_ALT_HNP_SUPPORT 5
14528 +#define WUF_WUSB 3
14529 +#define WUF_TX_DRPIE 0x0
14530 +#define WUF_DEV_XMIT_PACKET 0x1
14531 +#define WUF_COUNT_PACKETS 0x2
14532 +#define WUF_CAPTURE_PACKETS 0x3
14533 +#define UF_FUNCTION_SUSPEND 0
14534 +#define UF_U1_ENABLE 48
14535 +#define UF_U2_ENABLE 49
14536 +#define UF_LTM_ENABLE 50
14537 +
14538 +/* Class requests from the USB 2.0 hub spec, table 11-15 */
14539 +#define UCR_CLEAR_HUB_FEATURE (0x2000 | UR_CLEAR_FEATURE)
14540 +#define UCR_CLEAR_PORT_FEATURE (0x2300 | UR_CLEAR_FEATURE)
14541 +#define UCR_GET_HUB_DESCRIPTOR (0xa000 | UR_GET_DESCRIPTOR)
14542 +#define UCR_GET_HUB_STATUS (0xa000 | UR_GET_STATUS)
14543 +#define UCR_GET_PORT_STATUS (0xa300 | UR_GET_STATUS)
14544 +#define UCR_SET_HUB_FEATURE (0x2000 | UR_SET_FEATURE)
14545 +#define UCR_SET_PORT_FEATURE (0x2300 | UR_SET_FEATURE)
14546 +#define UCR_SET_AND_TEST_PORT_FEATURE (0xa300 | UR_SET_AND_TEST_FEATURE)
14547 +
14548 +#ifdef _MSC_VER
14549 +#include <pshpack1.h>
14550 +#endif
14551 +
14552 +typedef struct {
14553 + uByte bLength;
14554 + uByte bDescriptorType;
14555 + uByte bDescriptorSubtype;
14556 +} UPACKED usb_descriptor_t;
14557 +
14558 +typedef struct {
14559 + uByte bLength;
14560 + uByte bDescriptorType;
14561 +} UPACKED usb_descriptor_header_t;
14562 +
14563 +typedef struct {
14564 + uByte bLength;
14565 + uByte bDescriptorType;
14566 + uWord bcdUSB;
14567 +#define UD_USB_2_0 0x0200
14568 +#define UD_IS_USB2(d) (UGETW((d)->bcdUSB) >= UD_USB_2_0)
14569 + uByte bDeviceClass;
14570 + uByte bDeviceSubClass;
14571 + uByte bDeviceProtocol;
14572 + uByte bMaxPacketSize;
14573 + /* The fields below are not part of the initial descriptor. */
14574 + uWord idVendor;
14575 + uWord idProduct;
14576 + uWord bcdDevice;
14577 + uByte iManufacturer;
14578 + uByte iProduct;
14579 + uByte iSerialNumber;
14580 + uByte bNumConfigurations;
14581 +} UPACKED usb_device_descriptor_t;
14582 +#define USB_DEVICE_DESCRIPTOR_SIZE 18
14583 +
14584 +typedef struct {
14585 + uByte bLength;
14586 + uByte bDescriptorType;
14587 + uWord wTotalLength;
14588 + uByte bNumInterface;
14589 + uByte bConfigurationValue;
14590 + uByte iConfiguration;
14591 +#define UC_ATT_ONE (1 << 7) /* must be set */
14592 +#define UC_ATT_SELFPOWER (1 << 6) /* self powered */
14593 +#define UC_ATT_WAKEUP (1 << 5) /* can wakeup */
14594 +#define UC_ATT_BATTERY (1 << 4) /* battery powered */
14595 + uByte bmAttributes;
14596 +#define UC_BUS_POWERED 0x80
14597 +#define UC_SELF_POWERED 0x40
14598 +#define UC_REMOTE_WAKEUP 0x20
14599 + uByte bMaxPower; /* max current in 2 mA units */
14600 +#define UC_POWER_FACTOR 2
14601 +} UPACKED usb_config_descriptor_t;
14602 +#define USB_CONFIG_DESCRIPTOR_SIZE 9
14603 +
14604 +typedef struct {
14605 + uByte bLength;
14606 + uByte bDescriptorType;
14607 + uByte bInterfaceNumber;
14608 + uByte bAlternateSetting;
14609 + uByte bNumEndpoints;
14610 + uByte bInterfaceClass;
14611 + uByte bInterfaceSubClass;
14612 + uByte bInterfaceProtocol;
14613 + uByte iInterface;
14614 +} UPACKED usb_interface_descriptor_t;
14615 +#define USB_INTERFACE_DESCRIPTOR_SIZE 9
14616 +
14617 +typedef struct {
14618 + uByte bLength;
14619 + uByte bDescriptorType;
14620 + uByte bEndpointAddress;
14621 +#define UE_GET_DIR(a) ((a) & 0x80)
14622 +#define UE_SET_DIR(a,d) ((a) | (((d)&1) << 7))
14623 +#define UE_DIR_IN 0x80
14624 +#define UE_DIR_OUT 0x00
14625 +#define UE_ADDR 0x0f
14626 +#define UE_GET_ADDR(a) ((a) & UE_ADDR)
14627 + uByte bmAttributes;
14628 +#define UE_XFERTYPE 0x03
14629 +#define UE_CONTROL 0x00
14630 +#define UE_ISOCHRONOUS 0x01
14631 +#define UE_BULK 0x02
14632 +#define UE_INTERRUPT 0x03
14633 +#define UE_GET_XFERTYPE(a) ((a) & UE_XFERTYPE)
14634 +#define UE_ISO_TYPE 0x0c
14635 +#define UE_ISO_ASYNC 0x04
14636 +#define UE_ISO_ADAPT 0x08
14637 +#define UE_ISO_SYNC 0x0c
14638 +#define UE_GET_ISO_TYPE(a) ((a) & UE_ISO_TYPE)
14639 + uWord wMaxPacketSize;
14640 + uByte bInterval;
14641 +} UPACKED usb_endpoint_descriptor_t;
14642 +#define USB_ENDPOINT_DESCRIPTOR_SIZE 7
14643 +
14644 +typedef struct ss_endpoint_companion_descriptor {
14645 + uByte bLength;
14646 + uByte bDescriptorType;
14647 + uByte bMaxBurst;
14648 +#define USSE_GET_MAX_STREAMS(a) ((a) & 0x1f)
14649 +#define USSE_SET_MAX_STREAMS(a, b) ((a) | ((b) & 0x1f))
14650 +#define USSE_GET_MAX_PACKET_NUM(a) ((a) & 0x03)
14651 +#define USSE_SET_MAX_PACKET_NUM(a, b) ((a) | ((b) & 0x03))
14652 + uByte bmAttributes;
14653 + uWord wBytesPerInterval;
14654 +} UPACKED ss_endpoint_companion_descriptor_t;
14655 +#define USB_SS_ENDPOINT_COMPANION_DESCRIPTOR_SIZE 6
14656 +
14657 +typedef struct {
14658 + uByte bLength;
14659 + uByte bDescriptorType;
14660 + uWord bString[127];
14661 +} UPACKED usb_string_descriptor_t;
14662 +#define USB_MAX_STRING_LEN 128
14663 +#define USB_LANGUAGE_TABLE 0 /* # of the string language id table */
14664 +
14665 +/* Hub specific request */
14666 +#define UR_GET_BUS_STATE 0x02
14667 +#define UR_CLEAR_TT_BUFFER 0x08
14668 +#define UR_RESET_TT 0x09
14669 +#define UR_GET_TT_STATE 0x0a
14670 +#define UR_STOP_TT 0x0b
14671 +
14672 +/* Hub features */
14673 +#define UHF_C_HUB_LOCAL_POWER 0
14674 +#define UHF_C_HUB_OVER_CURRENT 1
14675 +#define UHF_PORT_CONNECTION 0
14676 +#define UHF_PORT_ENABLE 1
14677 +#define UHF_PORT_SUSPEND 2
14678 +#define UHF_PORT_OVER_CURRENT 3
14679 +#define UHF_PORT_RESET 4
14680 +#define UHF_PORT_L1 5
14681 +#define UHF_PORT_POWER 8
14682 +#define UHF_PORT_LOW_SPEED 9
14683 +#define UHF_PORT_HIGH_SPEED 10
14684 +#define UHF_C_PORT_CONNECTION 16
14685 +#define UHF_C_PORT_ENABLE 17
14686 +#define UHF_C_PORT_SUSPEND 18
14687 +#define UHF_C_PORT_OVER_CURRENT 19
14688 +#define UHF_C_PORT_RESET 20
14689 +#define UHF_C_PORT_L1 23
14690 +#define UHF_PORT_TEST 21
14691 +#define UHF_PORT_INDICATOR 22
14692 +
14693 +typedef struct {
14694 + uByte bDescLength;
14695 + uByte bDescriptorType;
14696 + uByte bNbrPorts;
14697 + uWord wHubCharacteristics;
14698 +#define UHD_PWR 0x0003
14699 +#define UHD_PWR_GANGED 0x0000
14700 +#define UHD_PWR_INDIVIDUAL 0x0001
14701 +#define UHD_PWR_NO_SWITCH 0x0002
14702 +#define UHD_COMPOUND 0x0004
14703 +#define UHD_OC 0x0018
14704 +#define UHD_OC_GLOBAL 0x0000
14705 +#define UHD_OC_INDIVIDUAL 0x0008
14706 +#define UHD_OC_NONE 0x0010
14707 +#define UHD_TT_THINK 0x0060
14708 +#define UHD_TT_THINK_8 0x0000
14709 +#define UHD_TT_THINK_16 0x0020
14710 +#define UHD_TT_THINK_24 0x0040
14711 +#define UHD_TT_THINK_32 0x0060
14712 +#define UHD_PORT_IND 0x0080
14713 + uByte bPwrOn2PwrGood; /* delay in 2 ms units */
14714 +#define UHD_PWRON_FACTOR 2
14715 + uByte bHubContrCurrent;
14716 + uByte DeviceRemovable[32]; /* max 255 ports */
14717 +#define UHD_NOT_REMOV(desc, i) \
14718 + (((desc)->DeviceRemovable[(i)/8] >> ((i) % 8)) & 1)
14719 + /* deprecated */ uByte PortPowerCtrlMask[1];
14720 +} UPACKED usb_hub_descriptor_t;
14721 +#define USB_HUB_DESCRIPTOR_SIZE 9 /* includes deprecated PortPowerCtrlMask */
14722 +
14723 +typedef struct {
14724 + uByte bLength;
14725 + uByte bDescriptorType;
14726 + uWord bcdUSB;
14727 + uByte bDeviceClass;
14728 + uByte bDeviceSubClass;
14729 + uByte bDeviceProtocol;
14730 + uByte bMaxPacketSize0;
14731 + uByte bNumConfigurations;
14732 + uByte bReserved;
14733 +} UPACKED usb_device_qualifier_t;
14734 +#define USB_DEVICE_QUALIFIER_SIZE 10
14735 +
14736 +typedef struct {
14737 + uByte bLength;
14738 + uByte bDescriptorType;
14739 + uByte bmAttributes;
14740 +#define UOTG_SRP 0x01
14741 +#define UOTG_HNP 0x02
14742 +} UPACKED usb_otg_descriptor_t;
14743 +
14744 +/* OTG feature selectors */
14745 +#define UOTG_B_HNP_ENABLE 3
14746 +#define UOTG_A_HNP_SUPPORT 4
14747 +#define UOTG_A_ALT_HNP_SUPPORT 5
14748 +
14749 +typedef struct {
14750 + uWord wStatus;
14751 +/* Device status flags */
14752 +#define UDS_SELF_POWERED 0x0001
14753 +#define UDS_REMOTE_WAKEUP 0x0002
14754 +/* Endpoint status flags */
14755 +#define UES_HALT 0x0001
14756 +} UPACKED usb_status_t;
14757 +
14758 +typedef struct {
14759 + uWord wHubStatus;
14760 +#define UHS_LOCAL_POWER 0x0001
14761 +#define UHS_OVER_CURRENT 0x0002
14762 + uWord wHubChange;
14763 +} UPACKED usb_hub_status_t;
14764 +
14765 +typedef struct {
14766 + uWord wPortStatus;
14767 +#define UPS_CURRENT_CONNECT_STATUS 0x0001
14768 +#define UPS_PORT_ENABLED 0x0002
14769 +#define UPS_SUSPEND 0x0004
14770 +#define UPS_OVERCURRENT_INDICATOR 0x0008
14771 +#define UPS_RESET 0x0010
14772 +#define UPS_PORT_POWER 0x0100
14773 +#define UPS_LOW_SPEED 0x0200
14774 +#define UPS_HIGH_SPEED 0x0400
14775 +#define UPS_PORT_TEST 0x0800
14776 +#define UPS_PORT_INDICATOR 0x1000
14777 + uWord wPortChange;
14778 +#define UPS_C_CONNECT_STATUS 0x0001
14779 +#define UPS_C_PORT_ENABLED 0x0002
14780 +#define UPS_C_SUSPEND 0x0004
14781 +#define UPS_C_OVERCURRENT_INDICATOR 0x0008
14782 +#define UPS_C_PORT_RESET 0x0010
14783 +} UPACKED usb_port_status_t;
14784 +
14785 +#ifdef _MSC_VER
14786 +#include <poppack.h>
14787 +#endif
14788 +
14789 +/* Device class codes */
14790 +#define UDCLASS_IN_INTERFACE 0x00
14791 +#define UDCLASS_COMM 0x02
14792 +#define UDCLASS_HUB 0x09
14793 +#define UDSUBCLASS_HUB 0x00
14794 +#define UDPROTO_FSHUB 0x00
14795 +#define UDPROTO_HSHUBSTT 0x01
14796 +#define UDPROTO_HSHUBMTT 0x02
14797 +#define UDCLASS_DIAGNOSTIC 0xdc
14798 +#define UDCLASS_WIRELESS 0xe0
14799 +#define UDSUBCLASS_RF 0x01
14800 +#define UDPROTO_BLUETOOTH 0x01
14801 +#define UDCLASS_VENDOR 0xff
14802 +
14803 +/* Interface class codes */
14804 +#define UICLASS_UNSPEC 0x00
14805 +
14806 +#define UICLASS_AUDIO 0x01
14807 +#define UISUBCLASS_AUDIOCONTROL 1
14808 +#define UISUBCLASS_AUDIOSTREAM 2
14809 +#define UISUBCLASS_MIDISTREAM 3
14810 +
14811 +#define UICLASS_CDC 0x02 /* communication */
14812 +#define UISUBCLASS_DIRECT_LINE_CONTROL_MODEL 1
14813 +#define UISUBCLASS_ABSTRACT_CONTROL_MODEL 2
14814 +#define UISUBCLASS_TELEPHONE_CONTROL_MODEL 3
14815 +#define UISUBCLASS_MULTICHANNEL_CONTROL_MODEL 4
14816 +#define UISUBCLASS_CAPI_CONTROLMODEL 5
14817 +#define UISUBCLASS_ETHERNET_NETWORKING_CONTROL_MODEL 6
14818 +#define UISUBCLASS_ATM_NETWORKING_CONTROL_MODEL 7
14819 +#define UIPROTO_CDC_AT 1
14820 +
14821 +#define UICLASS_HID 0x03
14822 +#define UISUBCLASS_BOOT 1
14823 +#define UIPROTO_BOOT_KEYBOARD 1
14824 +
14825 +#define UICLASS_PHYSICAL 0x05
14826 +
14827 +#define UICLASS_IMAGE 0x06
14828 +
14829 +#define UICLASS_PRINTER 0x07
14830 +#define UISUBCLASS_PRINTER 1
14831 +#define UIPROTO_PRINTER_UNI 1
14832 +#define UIPROTO_PRINTER_BI 2
14833 +#define UIPROTO_PRINTER_1284 3
14834 +
14835 +#define UICLASS_MASS 0x08
14836 +#define UISUBCLASS_RBC 1
14837 +#define UISUBCLASS_SFF8020I 2
14838 +#define UISUBCLASS_QIC157 3
14839 +#define UISUBCLASS_UFI 4
14840 +#define UISUBCLASS_SFF8070I 5
14841 +#define UISUBCLASS_SCSI 6
14842 +#define UIPROTO_MASS_CBI_I 0
14843 +#define UIPROTO_MASS_CBI 1
14844 +#define UIPROTO_MASS_BBB_OLD 2 /* Not in the spec anymore */
14845 +#define UIPROTO_MASS_BBB 80 /* 'P' for the Iomega Zip drive */
14846 +
14847 +#define UICLASS_HUB 0x09
14848 +#define UISUBCLASS_HUB 0
14849 +#define UIPROTO_FSHUB 0
14850 +#define UIPROTO_HSHUBSTT 0 /* Yes, same as previous */
14851 +#define UIPROTO_HSHUBMTT 1
14852 +
14853 +#define UICLASS_CDC_DATA 0x0a
14854 +#define UISUBCLASS_DATA 0
14855 +#define UIPROTO_DATA_ISDNBRI 0x30 /* Physical iface */
14856 +#define UIPROTO_DATA_HDLC 0x31 /* HDLC */
14857 +#define UIPROTO_DATA_TRANSPARENT 0x32 /* Transparent */
14858 +#define UIPROTO_DATA_Q921M 0x50 /* Management for Q921 */
14859 +#define UIPROTO_DATA_Q921 0x51 /* Data for Q921 */
14860 +#define UIPROTO_DATA_Q921TM 0x52 /* TEI multiplexer for Q921 */
14861 +#define UIPROTO_DATA_V42BIS 0x90 /* Data compression */
14862 +#define UIPROTO_DATA_Q931 0x91 /* Euro-ISDN */
14863 +#define UIPROTO_DATA_V120 0x92 /* V.24 rate adaption */
14864 +#define UIPROTO_DATA_CAPI 0x93 /* CAPI 2.0 commands */
14865 +#define UIPROTO_DATA_HOST_BASED 0xfd /* Host based driver */
14866 +#define UIPROTO_DATA_PUF 0xfe /* see Prot. Unit Func. Desc.*/
14867 +#define UIPROTO_DATA_VENDOR 0xff /* Vendor specific */
14868 +
14869 +#define UICLASS_SMARTCARD 0x0b
14870 +
14871 +/*#define UICLASS_FIRM_UPD 0x0c*/
14872 +
14873 +#define UICLASS_SECURITY 0x0d
14874 +
14875 +#define UICLASS_DIAGNOSTIC 0xdc
14876 +
14877 +#define UICLASS_WIRELESS 0xe0
14878 +#define UISUBCLASS_RF 0x01
14879 +#define UIPROTO_BLUETOOTH 0x01
14880 +
14881 +#define UICLASS_APPL_SPEC 0xfe
14882 +#define UISUBCLASS_FIRMWARE_DOWNLOAD 1
14883 +#define UISUBCLASS_IRDA 2
14884 +#define UIPROTO_IRDA 0
14885 +
14886 +#define UICLASS_VENDOR 0xff
14887 +
14888 +#define USB_HUB_MAX_DEPTH 5
14889 +
14890 +/*
14891 + * Minimum time a device needs to be powered down to go through
14892 + * a power cycle. XXX Are these time in the spec?
14893 + */
14894 +#define USB_POWER_DOWN_TIME 200 /* ms */
14895 +#define USB_PORT_POWER_DOWN_TIME 100 /* ms */
14896 +
14897 +#if 0
14898 +/* These are the values from the spec. */
14899 +#define USB_PORT_RESET_DELAY 10 /* ms */
14900 +#define USB_PORT_ROOT_RESET_DELAY 50 /* ms */
14901 +#define USB_PORT_RESET_RECOVERY 10 /* ms */
14902 +#define USB_PORT_POWERUP_DELAY 100 /* ms */
14903 +#define USB_SET_ADDRESS_SETTLE 2 /* ms */
14904 +#define USB_RESUME_DELAY (20*5) /* ms */
14905 +#define USB_RESUME_WAIT 10 /* ms */
14906 +#define USB_RESUME_RECOVERY 10 /* ms */
14907 +#define USB_EXTRA_POWER_UP_TIME 0 /* ms */
14908 +#else
14909 +/* Allow for marginal (i.e. non-conforming) devices. */
14910 +#define USB_PORT_RESET_DELAY 50 /* ms */
14911 +#define USB_PORT_ROOT_RESET_DELAY 250 /* ms */
14912 +#define USB_PORT_RESET_RECOVERY 250 /* ms */
14913 +#define USB_PORT_POWERUP_DELAY 300 /* ms */
14914 +#define USB_SET_ADDRESS_SETTLE 10 /* ms */
14915 +#define USB_RESUME_DELAY (50*5) /* ms */
14916 +#define USB_RESUME_WAIT 50 /* ms */
14917 +#define USB_RESUME_RECOVERY 50 /* ms */
14918 +#define USB_EXTRA_POWER_UP_TIME 20 /* ms */
14919 +#endif
14920 +
14921 +#define USB_MIN_POWER 100 /* mA */
14922 +#define USB_MAX_POWER 500 /* mA */
14923 +
14924 +#define USB_BUS_RESET_DELAY 100 /* ms XXX?*/
14925 +
14926 +#define USB_UNCONFIG_NO 0
14927 +#define USB_UNCONFIG_INDEX (-1)
14928 +
14929 +/*** ioctl() related stuff ***/
14930 +
14931 +struct usb_ctl_request {
14932 + int ucr_addr;
14933 + usb_device_request_t ucr_request;
14934 + void *ucr_data;
14935 + int ucr_flags;
14936 +#define USBD_SHORT_XFER_OK 0x04 /* allow short reads */
14937 + int ucr_actlen; /* actual length transferred */
14938 +};
14939 +
14940 +struct usb_alt_interface {
14941 + int uai_config_index;
14942 + int uai_interface_index;
14943 + int uai_alt_no;
14944 +};
14945 +
14946 +#define USB_CURRENT_CONFIG_INDEX (-1)
14947 +#define USB_CURRENT_ALT_INDEX (-1)
14948 +
14949 +struct usb_config_desc {
14950 + int ucd_config_index;
14951 + usb_config_descriptor_t ucd_desc;
14952 +};
14953 +
14954 +struct usb_interface_desc {
14955 + int uid_config_index;
14956 + int uid_interface_index;
14957 + int uid_alt_index;
14958 + usb_interface_descriptor_t uid_desc;
14959 +};
14960 +
14961 +struct usb_endpoint_desc {
14962 + int ued_config_index;
14963 + int ued_interface_index;
14964 + int ued_alt_index;
14965 + int ued_endpoint_index;
14966 + usb_endpoint_descriptor_t ued_desc;
14967 +};
14968 +
14969 +struct usb_full_desc {
14970 + int ufd_config_index;
14971 + u_int ufd_size;
14972 + u_char *ufd_data;
14973 +};
14974 +
14975 +struct usb_string_desc {
14976 + int usd_string_index;
14977 + int usd_language_id;
14978 + usb_string_descriptor_t usd_desc;
14979 +};
14980 +
14981 +struct usb_ctl_report_desc {
14982 + int ucrd_size;
14983 + u_char ucrd_data[1024]; /* filled data size will vary */
14984 +};
14985 +
14986 +typedef struct { u_int32_t cookie; } usb_event_cookie_t;
14987 +
14988 +#define USB_MAX_DEVNAMES 4
14989 +#define USB_MAX_DEVNAMELEN 16
14990 +struct usb_device_info {
14991 + u_int8_t udi_bus;
14992 + u_int8_t udi_addr; /* device address */
14993 + usb_event_cookie_t udi_cookie;
14994 + char udi_product[USB_MAX_STRING_LEN];
14995 + char udi_vendor[USB_MAX_STRING_LEN];
14996 + char udi_release[8];
14997 + u_int16_t udi_productNo;
14998 + u_int16_t udi_vendorNo;
14999 + u_int16_t udi_releaseNo;
15000 + u_int8_t udi_class;
15001 + u_int8_t udi_subclass;
15002 + u_int8_t udi_protocol;
15003 + u_int8_t udi_config;
15004 + u_int8_t udi_speed;
15005 +#define USB_SPEED_UNKNOWN 0
15006 +#define USB_SPEED_LOW 1
15007 +#define USB_SPEED_FULL 2
15008 +#define USB_SPEED_HIGH 3
15009 +#define USB_SPEED_VARIABLE 4
15010 +#define USB_SPEED_SUPER 5
15011 + int udi_power; /* power consumption in mA, 0 if selfpowered */
15012 + int udi_nports;
15013 + char udi_devnames[USB_MAX_DEVNAMES][USB_MAX_DEVNAMELEN];
15014 + u_int8_t udi_ports[16];/* hub only: addresses of devices on ports */
15015 +#define USB_PORT_ENABLED 0xff
15016 +#define USB_PORT_SUSPENDED 0xfe
15017 +#define USB_PORT_POWERED 0xfd
15018 +#define USB_PORT_DISABLED 0xfc
15019 +};
15020 +
15021 +struct usb_ctl_report {
15022 + int ucr_report;
15023 + u_char ucr_data[1024]; /* filled data size will vary */
15024 +};
15025 +
15026 +struct usb_device_stats {
15027 + u_long uds_requests[4]; /* indexed by transfer type UE_* */
15028 +};
15029 +
15030 +#define WUSB_MIN_IE 0x80
15031 +#define WUSB_WCTA_IE 0x80
15032 +#define WUSB_WCONNECTACK_IE 0x81
15033 +#define WUSB_WHOSTINFO_IE 0x82
15034 +#define WUHI_GET_CA(_bmAttributes_) ((_bmAttributes_) & 0x3)
15035 +#define WUHI_CA_RECONN 0x00
15036 +#define WUHI_CA_LIMITED 0x01
15037 +#define WUHI_CA_ALL 0x03
15038 +#define WUHI_GET_MLSI(_bmAttributes_) (((_bmAttributes_) & 0x38) >> 3)
15039 +#define WUSB_WCHCHANGEANNOUNCE_IE 0x83
15040 +#define WUSB_WDEV_DISCONNECT_IE 0x84
15041 +#define WUSB_WHOST_DISCONNECT_IE 0x85
15042 +#define WUSB_WRELEASE_CHANNEL_IE 0x86
15043 +#define WUSB_WWORK_IE 0x87
15044 +#define WUSB_WCHANNEL_STOP_IE 0x88
15045 +#define WUSB_WDEV_KEEPALIVE_IE 0x89
15046 +#define WUSB_WISOCH_DISCARD_IE 0x8A
15047 +#define WUSB_WRESETDEVICE_IE 0x8B
15048 +#define WUSB_WXMIT_PACKET_ADJUST_IE 0x8C
15049 +#define WUSB_MAX_IE 0x8C
15050 +
15051 +/* Device Notification Types */
15052 +
15053 +#define WUSB_DN_MIN 0x01
15054 +#define WUSB_DN_CONNECT 0x01
15055 +# define WUSB_DA_OLDCONN 0x00
15056 +# define WUSB_DA_NEWCONN 0x01
15057 +# define WUSB_DA_SELF_BEACON 0x02
15058 +# define WUSB_DA_DIR_BEACON 0x04
15059 +# define WUSB_DA_NO_BEACON 0x06
15060 +#define WUSB_DN_DISCONNECT 0x02
15061 +#define WUSB_DN_EPRDY 0x03
15062 +#define WUSB_DN_MASAVAILCHANGED 0x04
15063 +#define WUSB_DN_REMOTEWAKEUP 0x05
15064 +#define WUSB_DN_SLEEP 0x06
15065 +#define WUSB_DN_ALIVE 0x07
15066 +#define WUSB_DN_MAX 0x07
15067 +
15068 +#ifdef _MSC_VER
15069 +#include <pshpack1.h>
15070 +#endif
15071 +
15072 +/* WUSB Handshake Data. Used during the SET/GET HANDSHAKE requests */
15073 +typedef struct wusb_hndshk_data {
15074 + uByte bMessageNumber;
15075 + uByte bStatus;
15076 + uByte tTKID[3];
15077 + uByte bReserved;
15078 + uByte CDID[16];
15079 + uByte Nonce[16];
15080 + uByte MIC[8];
15081 +} UPACKED wusb_hndshk_data_t;
15082 +#define WUSB_HANDSHAKE_LEN_FOR_MIC 38
15083 +
15084 +/* WUSB Connection Context */
15085 +typedef struct wusb_conn_context {
15086 + uByte CHID [16];
15087 + uByte CDID [16];
15088 + uByte CK [16];
15089 +} UPACKED wusb_conn_context_t;
15090 +
15091 +/* WUSB Security Descriptor */
15092 +typedef struct wusb_security_desc {
15093 + uByte bLength;
15094 + uByte bDescriptorType;
15095 + uWord wTotalLength;
15096 + uByte bNumEncryptionTypes;
15097 +} UPACKED wusb_security_desc_t;
15098 +
15099 +/* WUSB Encryption Type Descriptor */
15100 +typedef struct wusb_encrypt_type_desc {
15101 + uByte bLength;
15102 + uByte bDescriptorType;
15103 +
15104 + uByte bEncryptionType;
15105 +#define WUETD_UNSECURE 0
15106 +#define WUETD_WIRED 1
15107 +#define WUETD_CCM_1 2
15108 +#define WUETD_RSA_1 3
15109 +
15110 + uByte bEncryptionValue;
15111 + uByte bAuthKeyIndex;
15112 +} UPACKED wusb_encrypt_type_desc_t;
15113 +
15114 +/* WUSB Key Descriptor */
15115 +typedef struct wusb_key_desc {
15116 + uByte bLength;
15117 + uByte bDescriptorType;
15118 + uByte tTKID[3];
15119 + uByte bReserved;
15120 + uByte KeyData[1]; /* variable length */
15121 +} UPACKED wusb_key_desc_t;
15122 +
15123 +/* WUSB BOS Descriptor (Binary device Object Store) */
15124 +typedef struct wusb_bos_desc {
15125 + uByte bLength;
15126 + uByte bDescriptorType;
15127 + uWord wTotalLength;
15128 + uByte bNumDeviceCaps;
15129 +} UPACKED wusb_bos_desc_t;
15130 +
15131 +#define USB_DEVICE_CAPABILITY_20_EXTENSION 0x02
15132 +typedef struct usb_dev_cap_20_ext_desc {
15133 + uByte bLength;
15134 + uByte bDescriptorType;
15135 + uByte bDevCapabilityType;
15136 +#define USB_20_EXT_LPM 0x02
15137 + uDWord bmAttributes;
15138 +} UPACKED usb_dev_cap_20_ext_desc_t;
15139 +
15140 +#define USB_DEVICE_CAPABILITY_SS_USB 0x03
15141 +typedef struct usb_dev_cap_ss_usb {
15142 + uByte bLength;
15143 + uByte bDescriptorType;
15144 + uByte bDevCapabilityType;
15145 +#define USB_DC_SS_USB_LTM_CAPABLE 0x02
15146 + uByte bmAttributes;
15147 +#define USB_DC_SS_USB_SPEED_SUPPORT_LOW 0x01
15148 +#define USB_DC_SS_USB_SPEED_SUPPORT_FULL 0x02
15149 +#define USB_DC_SS_USB_SPEED_SUPPORT_HIGH 0x04
15150 +#define USB_DC_SS_USB_SPEED_SUPPORT_SS 0x08
15151 + uWord wSpeedsSupported;
15152 + uByte bFunctionalitySupport;
15153 + uByte bU1DevExitLat;
15154 + uWord wU2DevExitLat;
15155 +} UPACKED usb_dev_cap_ss_usb_t;
15156 +
15157 +#define USB_DEVICE_CAPABILITY_CONTAINER_ID 0x04
15158 +typedef struct usb_dev_cap_container_id {
15159 + uByte bLength;
15160 + uByte bDescriptorType;
15161 + uByte bDevCapabilityType;
15162 + uByte bReserved;
15163 + uByte containerID[16];
15164 +} UPACKED usb_dev_cap_container_id_t;
15165 +
15166 +/* Device Capability Type Codes */
15167 +#define WUSB_DEVICE_CAPABILITY_WIRELESS_USB 0x01
15168 +
15169 +/* Device Capability Descriptor */
15170 +typedef struct wusb_dev_cap_desc {
15171 + uByte bLength;
15172 + uByte bDescriptorType;
15173 + uByte bDevCapabilityType;
15174 + uByte caps[1]; /* Variable length */
15175 +} UPACKED wusb_dev_cap_desc_t;
15176 +
15177 +/* Device Capability Descriptor */
15178 +typedef struct wusb_dev_cap_uwb_desc {
15179 + uByte bLength;
15180 + uByte bDescriptorType;
15181 + uByte bDevCapabilityType;
15182 + uByte bmAttributes;
15183 + uWord wPHYRates; /* Bitmap */
15184 + uByte bmTFITXPowerInfo;
15185 + uByte bmFFITXPowerInfo;
15186 + uWord bmBandGroup;
15187 + uByte bReserved;
15188 +} UPACKED wusb_dev_cap_uwb_desc_t;
15189 +
15190 +/* Wireless USB Endpoint Companion Descriptor */
15191 +typedef struct wusb_endpoint_companion_desc {
15192 + uByte bLength;
15193 + uByte bDescriptorType;
15194 + uByte bMaxBurst;
15195 + uByte bMaxSequence;
15196 + uWord wMaxStreamDelay;
15197 + uWord wOverTheAirPacketSize;
15198 + uByte bOverTheAirInterval;
15199 + uByte bmCompAttributes;
15200 +} UPACKED wusb_endpoint_companion_desc_t;
15201 +
15202 +/* Wireless USB Numeric Association M1 Data Structure */
15203 +typedef struct wusb_m1_data {
15204 + uByte version;
15205 + uWord langId;
15206 + uByte deviceFriendlyNameLength;
15207 + uByte sha_256_m3[32];
15208 + uByte deviceFriendlyName[256];
15209 +} UPACKED wusb_m1_data_t;
15210 +
15211 +typedef struct wusb_m2_data {
15212 + uByte version;
15213 + uWord langId;
15214 + uByte hostFriendlyNameLength;
15215 + uByte pkh[384];
15216 + uByte hostFriendlyName[256];
15217 +} UPACKED wusb_m2_data_t;
15218 +
15219 +typedef struct wusb_m3_data {
15220 + uByte pkd[384];
15221 + uByte nd;
15222 +} UPACKED wusb_m3_data_t;
15223 +
15224 +typedef struct wusb_m4_data {
15225 + uDWord _attributeTypeIdAndLength_1;
15226 + uWord associationTypeId;
15227 +
15228 + uDWord _attributeTypeIdAndLength_2;
15229 + uWord associationSubTypeId;
15230 +
15231 + uDWord _attributeTypeIdAndLength_3;
15232 + uDWord length;
15233 +
15234 + uDWord _attributeTypeIdAndLength_4;
15235 + uDWord associationStatus;
15236 +
15237 + uDWord _attributeTypeIdAndLength_5;
15238 + uByte chid[16];
15239 +
15240 + uDWord _attributeTypeIdAndLength_6;
15241 + uByte cdid[16];
15242 +
15243 + uDWord _attributeTypeIdAndLength_7;
15244 + uByte bandGroups[2];
15245 +} UPACKED wusb_m4_data_t;
15246 +
15247 +#ifdef _MSC_VER
15248 +#include <poppack.h>
15249 +#endif
15250 +
15251 +#ifdef __cplusplus
15252 +}
15253 +#endif
15254 +
15255 +#endif /* _USB_H_ */
15256 --- /dev/null
15257 +++ b/drivers/usb/host/dwc_otg/Makefile
15258 @@ -0,0 +1,82 @@
15259 +#
15260 +# Makefile for DWC_otg Highspeed USB controller driver
15261 +#
15262 +
15263 +ifneq ($(KERNELRELEASE),)
15264 +
15265 +# Use the BUS_INTERFACE variable to compile the software for either
15266 +# PCI(PCI_INTERFACE) or LM(LM_INTERFACE) bus.
15267 +ifeq ($(BUS_INTERFACE),)
15268 +# BUS_INTERFACE = -DPCI_INTERFACE
15269 +# BUS_INTERFACE = -DLM_INTERFACE
15270 + BUS_INTERFACE = -DPLATFORM_INTERFACE
15271 +endif
15272 +
15273 +#ccflags-y += -DDEBUG
15274 +#ccflags-y += -DDWC_OTG_DEBUGLEV=1 # reduce common debug msgs
15275 +
15276 +# Use one of the following flags to compile the software in host-only or
15277 +# device-only mode.
15278 +#ccflags-y += -DDWC_HOST_ONLY
15279 +#ccflags-y += -DDWC_DEVICE_ONLY
15280 +
15281 +ccflags-y += -Dlinux -DDWC_HS_ELECT_TST
15282 +#ccflags-y += -DDWC_EN_ISOC
15283 +ccflags-y += -I$(obj)/../dwc_common_port
15284 +#ccflags-y += -I$(PORTLIB)
15285 +ccflags-y += -DDWC_LINUX
15286 +ccflags-y += $(CFI)
15287 +ccflags-y += $(BUS_INTERFACE)
15288 +#ccflags-y += -DDWC_DEV_SRPCAP
15289 +
15290 +obj-$(CONFIG_USB_DWCOTG) += dwc_otg.o
15291 +
15292 +dwc_otg-objs := dwc_otg_driver.o dwc_otg_attr.o
15293 +dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o
15294 +dwc_otg-objs += dwc_otg_pcd_linux.o dwc_otg_pcd.o dwc_otg_pcd_intr.o
15295 +dwc_otg-objs += dwc_otg_hcd.o dwc_otg_hcd_linux.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o dwc_otg_hcd_ddma.o
15296 +dwc_otg-objs += dwc_otg_adp.o
15297 +dwc_otg-objs += dwc_otg_fiq_fsm.o
15298 +dwc_otg-objs += dwc_otg_fiq_stub.o
15299 +ifneq ($(CFI),)
15300 +dwc_otg-objs += dwc_otg_cfi.o
15301 +endif
15302 +
15303 +kernrelwd := $(subst ., ,$(KERNELRELEASE))
15304 +kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd))
15305 +
15306 +ifneq ($(kernrel3),2.6.20)
15307 +ccflags-y += $(CPPFLAGS)
15308 +endif
15309 +
15310 +else
15311 +
15312 +PWD := $(shell pwd)
15313 +PORTLIB := $(PWD)/../dwc_common_port
15314 +
15315 +# Command paths
15316 +CTAGS := $(CTAGS)
15317 +DOXYGEN := $(DOXYGEN)
15318 +
15319 +default: portlib
15320 + $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
15321 +
15322 +install: default
15323 + $(MAKE) -C$(KDIR) M=$(PORTLIB) modules_install
15324 + $(MAKE) -C$(KDIR) M=$(PWD) modules_install
15325 +
15326 +portlib:
15327 + $(MAKE) -C$(KDIR) M=$(PORTLIB) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
15328 + cp $(PORTLIB)/Module.symvers $(PWD)/
15329 +
15330 +docs: $(wildcard *.[hc]) doc/doxygen.cfg
15331 + $(DOXYGEN) doc/doxygen.cfg
15332 +
15333 +tags: $(wildcard *.[hc])
15334 + $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
15335 +
15336 +
15337 +clean:
15338 + rm -rf *.o *.ko .*cmd *.mod.c .tmp_versions Module.symvers
15339 +
15340 +endif
15341 --- /dev/null
15342 +++ b/drivers/usb/host/dwc_otg/doc/doxygen.cfg
15343 @@ -0,0 +1,224 @@
15344 +# Doxyfile 1.3.9.1
15345 +
15346 +#---------------------------------------------------------------------------
15347 +# Project related configuration options
15348 +#---------------------------------------------------------------------------
15349 +PROJECT_NAME = "DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver"
15350 +PROJECT_NUMBER = v3.00a
15351 +OUTPUT_DIRECTORY = ./doc/
15352 +CREATE_SUBDIRS = NO
15353 +OUTPUT_LANGUAGE = English
15354 +BRIEF_MEMBER_DESC = YES
15355 +REPEAT_BRIEF = YES
15356 +ABBREVIATE_BRIEF = "The $name class" \
15357 + "The $name widget" \
15358 + "The $name file" \
15359 + is \
15360 + provides \
15361 + specifies \
15362 + contains \
15363 + represents \
15364 + a \
15365 + an \
15366 + the
15367 +ALWAYS_DETAILED_SEC = NO
15368 +INLINE_INHERITED_MEMB = NO
15369 +FULL_PATH_NAMES = NO
15370 +STRIP_FROM_PATH =
15371 +STRIP_FROM_INC_PATH =
15372 +SHORT_NAMES = NO
15373 +JAVADOC_AUTOBRIEF = YES
15374 +MULTILINE_CPP_IS_BRIEF = NO
15375 +INHERIT_DOCS = YES
15376 +DISTRIBUTE_GROUP_DOC = NO
15377 +TAB_SIZE = 8
15378 +ALIASES =
15379 +OPTIMIZE_OUTPUT_FOR_C = YES
15380 +OPTIMIZE_OUTPUT_JAVA = NO
15381 +SUBGROUPING = YES
15382 +#---------------------------------------------------------------------------
15383 +# Build related configuration options
15384 +#---------------------------------------------------------------------------
15385 +EXTRACT_ALL = NO
15386 +EXTRACT_PRIVATE = YES
15387 +EXTRACT_STATIC = YES
15388 +EXTRACT_LOCAL_CLASSES = YES
15389 +EXTRACT_LOCAL_METHODS = NO
15390 +HIDE_UNDOC_MEMBERS = NO
15391 +HIDE_UNDOC_CLASSES = NO
15392 +HIDE_FRIEND_COMPOUNDS = NO
15393 +HIDE_IN_BODY_DOCS = NO
15394 +INTERNAL_DOCS = NO
15395 +CASE_SENSE_NAMES = NO
15396 +HIDE_SCOPE_NAMES = NO
15397 +SHOW_INCLUDE_FILES = YES
15398 +INLINE_INFO = YES
15399 +SORT_MEMBER_DOCS = NO
15400 +SORT_BRIEF_DOCS = NO
15401 +SORT_BY_SCOPE_NAME = NO
15402 +GENERATE_TODOLIST = YES
15403 +GENERATE_TESTLIST = YES
15404 +GENERATE_BUGLIST = YES
15405 +GENERATE_DEPRECATEDLIST= YES
15406 +ENABLED_SECTIONS =
15407 +MAX_INITIALIZER_LINES = 30
15408 +SHOW_USED_FILES = YES
15409 +SHOW_DIRECTORIES = YES
15410 +#---------------------------------------------------------------------------
15411 +# configuration options related to warning and progress messages
15412 +#---------------------------------------------------------------------------
15413 +QUIET = YES
15414 +WARNINGS = YES
15415 +WARN_IF_UNDOCUMENTED = NO
15416 +WARN_IF_DOC_ERROR = YES
15417 +WARN_FORMAT = "$file:$line: $text"
15418 +WARN_LOGFILE =
15419 +#---------------------------------------------------------------------------
15420 +# configuration options related to the input files
15421 +#---------------------------------------------------------------------------
15422 +INPUT = .
15423 +FILE_PATTERNS = *.c \
15424 + *.h \
15425 + ./linux/*.c \
15426 + ./linux/*.h
15427 +RECURSIVE = NO
15428 +EXCLUDE = ./test/ \
15429 + ./dwc_otg/.AppleDouble/
15430 +EXCLUDE_SYMLINKS = YES
15431 +EXCLUDE_PATTERNS = *.mod.*
15432 +EXAMPLE_PATH =
15433 +EXAMPLE_PATTERNS = *
15434 +EXAMPLE_RECURSIVE = NO
15435 +IMAGE_PATH =
15436 +INPUT_FILTER =
15437 +FILTER_PATTERNS =
15438 +FILTER_SOURCE_FILES = NO
15439 +#---------------------------------------------------------------------------
15440 +# configuration options related to source browsing
15441 +#---------------------------------------------------------------------------
15442 +SOURCE_BROWSER = YES
15443 +INLINE_SOURCES = NO
15444 +STRIP_CODE_COMMENTS = YES
15445 +REFERENCED_BY_RELATION = NO
15446 +REFERENCES_RELATION = NO
15447 +VERBATIM_HEADERS = NO
15448 +#---------------------------------------------------------------------------
15449 +# configuration options related to the alphabetical class index
15450 +#---------------------------------------------------------------------------
15451 +ALPHABETICAL_INDEX = NO
15452 +COLS_IN_ALPHA_INDEX = 5
15453 +IGNORE_PREFIX =
15454 +#---------------------------------------------------------------------------
15455 +# configuration options related to the HTML output
15456 +#---------------------------------------------------------------------------
15457 +GENERATE_HTML = YES
15458 +HTML_OUTPUT = html
15459 +HTML_FILE_EXTENSION = .html
15460 +HTML_HEADER =
15461 +HTML_FOOTER =
15462 +HTML_STYLESHEET =
15463 +HTML_ALIGN_MEMBERS = YES
15464 +GENERATE_HTMLHELP = NO
15465 +CHM_FILE =
15466 +HHC_LOCATION =
15467 +GENERATE_CHI = NO
15468 +BINARY_TOC = NO
15469 +TOC_EXPAND = NO
15470 +DISABLE_INDEX = NO
15471 +ENUM_VALUES_PER_LINE = 4
15472 +GENERATE_TREEVIEW = YES
15473 +TREEVIEW_WIDTH = 250
15474 +#---------------------------------------------------------------------------
15475 +# configuration options related to the LaTeX output
15476 +#---------------------------------------------------------------------------
15477 +GENERATE_LATEX = NO
15478 +LATEX_OUTPUT = latex
15479 +LATEX_CMD_NAME = latex
15480 +MAKEINDEX_CMD_NAME = makeindex
15481 +COMPACT_LATEX = NO
15482 +PAPER_TYPE = a4wide
15483 +EXTRA_PACKAGES =
15484 +LATEX_HEADER =
15485 +PDF_HYPERLINKS = NO
15486 +USE_PDFLATEX = NO
15487 +LATEX_BATCHMODE = NO
15488 +LATEX_HIDE_INDICES = NO
15489 +#---------------------------------------------------------------------------
15490 +# configuration options related to the RTF output
15491 +#---------------------------------------------------------------------------
15492 +GENERATE_RTF = NO
15493 +RTF_OUTPUT = rtf
15494 +COMPACT_RTF = NO
15495 +RTF_HYPERLINKS = NO
15496 +RTF_STYLESHEET_FILE =
15497 +RTF_EXTENSIONS_FILE =
15498 +#---------------------------------------------------------------------------
15499 +# configuration options related to the man page output
15500 +#---------------------------------------------------------------------------
15501 +GENERATE_MAN = NO
15502 +MAN_OUTPUT = man
15503 +MAN_EXTENSION = .3
15504 +MAN_LINKS = NO
15505 +#---------------------------------------------------------------------------
15506 +# configuration options related to the XML output
15507 +#---------------------------------------------------------------------------
15508 +GENERATE_XML = NO
15509 +XML_OUTPUT = xml
15510 +XML_SCHEMA =
15511 +XML_DTD =
15512 +XML_PROGRAMLISTING = YES
15513 +#---------------------------------------------------------------------------
15514 +# configuration options for the AutoGen Definitions output
15515 +#---------------------------------------------------------------------------
15516 +GENERATE_AUTOGEN_DEF = NO
15517 +#---------------------------------------------------------------------------
15518 +# configuration options related to the Perl module output
15519 +#---------------------------------------------------------------------------
15520 +GENERATE_PERLMOD = NO
15521 +PERLMOD_LATEX = NO
15522 +PERLMOD_PRETTY = YES
15523 +PERLMOD_MAKEVAR_PREFIX =
15524 +#---------------------------------------------------------------------------
15525 +# Configuration options related to the preprocessor
15526 +#---------------------------------------------------------------------------
15527 +ENABLE_PREPROCESSING = YES
15528 +MACRO_EXPANSION = YES
15529 +EXPAND_ONLY_PREDEF = YES
15530 +SEARCH_INCLUDES = YES
15531 +INCLUDE_PATH =
15532 +INCLUDE_FILE_PATTERNS =
15533 +PREDEFINED = DEVICE_ATTR DWC_EN_ISOC
15534 +EXPAND_AS_DEFINED = DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW DWC_OTG_DEVICE_ATTR_BITFIELD_STORE DWC_OTG_DEVICE_ATTR_BITFIELD_RW DWC_OTG_DEVICE_ATTR_BITFIELD_RO DWC_OTG_DEVICE_ATTR_REG_SHOW DWC_OTG_DEVICE_ATTR_REG_STORE DWC_OTG_DEVICE_ATTR_REG32_RW DWC_OTG_DEVICE_ATTR_REG32_RO DWC_EN_ISOC
15535 +SKIP_FUNCTION_MACROS = NO
15536 +#---------------------------------------------------------------------------
15537 +# Configuration::additions related to external references
15538 +#---------------------------------------------------------------------------
15539 +TAGFILES =
15540 +GENERATE_TAGFILE =
15541 +ALLEXTERNALS = NO
15542 +EXTERNAL_GROUPS = YES
15543 +PERL_PATH = /usr/bin/perl
15544 +#---------------------------------------------------------------------------
15545 +# Configuration options related to the dot tool
15546 +#---------------------------------------------------------------------------
15547 +CLASS_DIAGRAMS = YES
15548 +HIDE_UNDOC_RELATIONS = YES
15549 +HAVE_DOT = NO
15550 +CLASS_GRAPH = YES
15551 +COLLABORATION_GRAPH = YES
15552 +UML_LOOK = NO
15553 +TEMPLATE_RELATIONS = NO
15554 +INCLUDE_GRAPH = YES
15555 +INCLUDED_BY_GRAPH = YES
15556 +CALL_GRAPH = NO
15557 +GRAPHICAL_HIERARCHY = YES
15558 +DOT_IMAGE_FORMAT = png
15559 +DOT_PATH =
15560 +DOTFILE_DIRS =
15561 +MAX_DOT_GRAPH_DEPTH = 1000
15562 +GENERATE_LEGEND = YES
15563 +DOT_CLEANUP = YES
15564 +#---------------------------------------------------------------------------
15565 +# Configuration::additions related to the search engine
15566 +#---------------------------------------------------------------------------
15567 +SEARCHENGINE = NO
15568 --- /dev/null
15569 +++ b/drivers/usb/host/dwc_otg/dummy_audio.c
15570 @@ -0,0 +1,1575 @@
15571 +/*
15572 + * zero.c -- Gadget Zero, for USB development
15573 + *
15574 + * Copyright (C) 2003-2004 David Brownell
15575 + * All rights reserved.
15576 + *
15577 + * Redistribution and use in source and binary forms, with or without
15578 + * modification, are permitted provided that the following conditions
15579 + * are met:
15580 + * 1. Redistributions of source code must retain the above copyright
15581 + * notice, this list of conditions, and the following disclaimer,
15582 + * without modification.
15583 + * 2. Redistributions in binary form must reproduce the above copyright
15584 + * notice, this list of conditions and the following disclaimer in the
15585 + * documentation and/or other materials provided with the distribution.
15586 + * 3. The names of the above-listed copyright holders may not be used
15587 + * to endorse or promote products derived from this software without
15588 + * specific prior written permission.
15589 + *
15590 + * ALTERNATIVELY, this software may be distributed under the terms of the
15591 + * GNU General Public License ("GPL") as published by the Free Software
15592 + * Foundation, either version 2 of that License or (at your option) any
15593 + * later version.
15594 + *
15595 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
15596 + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
15597 + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
15598 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
15599 + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
15600 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
15601 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
15602 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
15603 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
15604 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
15605 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15606 + */
15607 +
15608 +
15609 +/*
15610 + * Gadget Zero only needs two bulk endpoints, and is an example of how you
15611 + * can write a hardware-agnostic gadget driver running inside a USB device.
15612 + *
15613 + * Hardware details are visible (see CONFIG_USB_ZERO_* below) but don't
15614 + * affect most of the driver.
15615 + *
15616 + * Use it with the Linux host/master side "usbtest" driver to get a basic
15617 + * functional test of your device-side usb stack, or with "usb-skeleton".
15618 + *
15619 + * It supports two similar configurations. One sinks whatever the usb host
15620 + * writes, and in return sources zeroes. The other loops whatever the host
15621 + * writes back, so the host can read it. Module options include:
15622 + *
15623 + * buflen=N default N=4096, buffer size used
15624 + * qlen=N default N=32, how many buffers in the loopback queue
15625 + * loopdefault default false, list loopback config first
15626 + *
15627 + * Many drivers will only have one configuration, letting them be much
15628 + * simpler if they also don't support high speed operation (like this
15629 + * driver does).
15630 + */
15631 +
15632 +#include <linux/config.h>
15633 +#include <linux/module.h>
15634 +#include <linux/kernel.h>
15635 +#include <linux/delay.h>
15636 +#include <linux/ioport.h>
15637 +#include <linux/sched.h>
15638 +#include <linux/slab.h>
15639 +#include <linux/smp_lock.h>
15640 +#include <linux/errno.h>
15641 +#include <linux/init.h>
15642 +#include <linux/timer.h>
15643 +#include <linux/list.h>
15644 +#include <linux/interrupt.h>
15645 +#include <linux/uts.h>
15646 +#include <linux/version.h>
15647 +#include <linux/device.h>
15648 +#include <linux/moduleparam.h>
15649 +#include <linux/proc_fs.h>
15650 +
15651 +#include <asm/byteorder.h>
15652 +#include <asm/io.h>
15653 +#include <asm/irq.h>
15654 +#include <asm/system.h>
15655 +#include <asm/unaligned.h>
15656 +
15657 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
15658 +# include <linux/usb/ch9.h>
15659 +#else
15660 +# include <linux/usb_ch9.h>
15661 +#endif
15662 +
15663 +#include <linux/usb_gadget.h>
15664 +
15665 +
15666 +/*-------------------------------------------------------------------------*/
15667 +/*-------------------------------------------------------------------------*/
15668 +
15669 +
15670 +static int utf8_to_utf16le(const char *s, u16 *cp, unsigned len)
15671 +{
15672 + int count = 0;
15673 + u8 c;
15674 + u16 uchar;
15675 +
15676 + /* this insists on correct encodings, though not minimal ones.
15677 + * BUT it currently rejects legit 4-byte UTF-8 code points,
15678 + * which need surrogate pairs. (Unicode 3.1 can use them.)
15679 + */
15680 + while (len != 0 && (c = (u8) *s++) != 0) {
15681 + if (unlikely(c & 0x80)) {
15682 + // 2-byte sequence:
15683 + // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
15684 + if ((c & 0xe0) == 0xc0) {
15685 + uchar = (c & 0x1f) << 6;
15686 +
15687 + c = (u8) *s++;
15688 + if ((c & 0xc0) != 0xc0)
15689 + goto fail;
15690 + c &= 0x3f;
15691 + uchar |= c;
15692 +
15693 + // 3-byte sequence (most CJKV characters):
15694 + // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
15695 + } else if ((c & 0xf0) == 0xe0) {
15696 + uchar = (c & 0x0f) << 12;
15697 +
15698 + c = (u8) *s++;
15699 + if ((c & 0xc0) != 0xc0)
15700 + goto fail;
15701 + c &= 0x3f;
15702 + uchar |= c << 6;
15703 +
15704 + c = (u8) *s++;
15705 + if ((c & 0xc0) != 0xc0)
15706 + goto fail;
15707 + c &= 0x3f;
15708 + uchar |= c;
15709 +
15710 + /* no bogus surrogates */
15711 + if (0xd800 <= uchar && uchar <= 0xdfff)
15712 + goto fail;
15713 +
15714 + // 4-byte sequence (surrogate pairs, currently rare):
15715 + // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
15716 + // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
15717 + // (uuuuu = wwww + 1)
15718 + // FIXME accept the surrogate code points (only)
15719 +
15720 + } else
15721 + goto fail;
15722 + } else
15723 + uchar = c;
15724 + put_unaligned (cpu_to_le16 (uchar), cp++);
15725 + count++;
15726 + len--;
15727 + }
15728 + return count;
15729 +fail:
15730 + return -1;
15731 +}
15732 +
15733 +
15734 +/**
15735 + * usb_gadget_get_string - fill out a string descriptor
15736 + * @table: of c strings encoded using UTF-8
15737 + * @id: string id, from low byte of wValue in get string descriptor
15738 + * @buf: at least 256 bytes
15739 + *
15740 + * Finds the UTF-8 string matching the ID, and converts it into a
15741 + * string descriptor in utf16-le.
15742 + * Returns length of descriptor (always even) or negative errno
15743 + *
15744 + * If your driver needs stings in multiple languages, you'll probably
15745 + * "switch (wIndex) { ... }" in your ep0 string descriptor logic,
15746 + * using this routine after choosing which set of UTF-8 strings to use.
15747 + * Note that US-ASCII is a strict subset of UTF-8; any string bytes with
15748 + * the eighth bit set will be multibyte UTF-8 characters, not ISO-8859/1
15749 + * characters (which are also widely used in C strings).
15750 + */
15751 +int
15752 +usb_gadget_get_string (struct usb_gadget_strings *table, int id, u8 *buf)
15753 +{
15754 + struct usb_string *s;
15755 + int len;
15756 +
15757 + /* descriptor 0 has the language id */
15758 + if (id == 0) {
15759 + buf [0] = 4;
15760 + buf [1] = USB_DT_STRING;
15761 + buf [2] = (u8) table->language;
15762 + buf [3] = (u8) (table->language >> 8);
15763 + return 4;
15764 + }
15765 + for (s = table->strings; s && s->s; s++)
15766 + if (s->id == id)
15767 + break;
15768 +
15769 + /* unrecognized: stall. */
15770 + if (!s || !s->s)
15771 + return -EINVAL;
15772 +
15773 + /* string descriptors have length, tag, then UTF16-LE text */
15774 + len = min ((size_t) 126, strlen (s->s));
15775 + memset (buf + 2, 0, 2 * len); /* zero all the bytes */
15776 + len = utf8_to_utf16le(s->s, (u16 *)&buf[2], len);
15777 + if (len < 0)
15778 + return -EINVAL;
15779 + buf [0] = (len + 1) * 2;
15780 + buf [1] = USB_DT_STRING;
15781 + return buf [0];
15782 +}
15783 +
15784 +
15785 +/*-------------------------------------------------------------------------*/
15786 +/*-------------------------------------------------------------------------*/
15787 +
15788 +
15789 +/**
15790 + * usb_descriptor_fillbuf - fill buffer with descriptors
15791 + * @buf: Buffer to be filled
15792 + * @buflen: Size of buf
15793 + * @src: Array of descriptor pointers, terminated by null pointer.
15794 + *
15795 + * Copies descriptors into the buffer, returning the length or a
15796 + * negative error code if they can't all be copied. Useful when
15797 + * assembling descriptors for an associated set of interfaces used
15798 + * as part of configuring a composite device; or in other cases where
15799 + * sets of descriptors need to be marshaled.
15800 + */
15801 +int
15802 +usb_descriptor_fillbuf(void *buf, unsigned buflen,
15803 + const struct usb_descriptor_header **src)
15804 +{
15805 + u8 *dest = buf;
15806 +
15807 + if (!src)
15808 + return -EINVAL;
15809 +
15810 + /* fill buffer from src[] until null descriptor ptr */
15811 + for (; 0 != *src; src++) {
15812 + unsigned len = (*src)->bLength;
15813 +
15814 + if (len > buflen)
15815 + return -EINVAL;
15816 + memcpy(dest, *src, len);
15817 + buflen -= len;
15818 + dest += len;
15819 + }
15820 + return dest - (u8 *)buf;
15821 +}
15822 +
15823 +
15824 +/**
15825 + * usb_gadget_config_buf - builts a complete configuration descriptor
15826 + * @config: Header for the descriptor, including characteristics such
15827 + * as power requirements and number of interfaces.
15828 + * @desc: Null-terminated vector of pointers to the descriptors (interface,
15829 + * endpoint, etc) defining all functions in this device configuration.
15830 + * @buf: Buffer for the resulting configuration descriptor.
15831 + * @length: Length of buffer. If this is not big enough to hold the
15832 + * entire configuration descriptor, an error code will be returned.
15833 + *
15834 + * This copies descriptors into the response buffer, building a descriptor
15835 + * for that configuration. It returns the buffer length or a negative
15836 + * status code. The config.wTotalLength field is set to match the length
15837 + * of the result, but other descriptor fields (including power usage and
15838 + * interface count) must be set by the caller.
15839 + *
15840 + * Gadget drivers could use this when constructing a config descriptor
15841 + * in response to USB_REQ_GET_DESCRIPTOR. They will need to patch the
15842 + * resulting bDescriptorType value if USB_DT_OTHER_SPEED_CONFIG is needed.
15843 + */
15844 +int usb_gadget_config_buf(
15845 + const struct usb_config_descriptor *config,
15846 + void *buf,
15847 + unsigned length,
15848 + const struct usb_descriptor_header **desc
15849 +)
15850 +{
15851 + struct usb_config_descriptor *cp = buf;
15852 + int len;
15853 +
15854 + /* config descriptor first */
15855 + if (length < USB_DT_CONFIG_SIZE || !desc)
15856 + return -EINVAL;
15857 + *cp = *config;
15858 +
15859 + /* then interface/endpoint/class/vendor/... */
15860 + len = usb_descriptor_fillbuf(USB_DT_CONFIG_SIZE + (u8*)buf,
15861 + length - USB_DT_CONFIG_SIZE, desc);
15862 + if (len < 0)
15863 + return len;
15864 + len += USB_DT_CONFIG_SIZE;
15865 + if (len > 0xffff)
15866 + return -EINVAL;
15867 +
15868 + /* patch up the config descriptor */
15869 + cp->bLength = USB_DT_CONFIG_SIZE;
15870 + cp->bDescriptorType = USB_DT_CONFIG;
15871 + cp->wTotalLength = cpu_to_le16(len);
15872 + cp->bmAttributes |= USB_CONFIG_ATT_ONE;
15873 + return len;
15874 +}
15875 +
15876 +/*-------------------------------------------------------------------------*/
15877 +/*-------------------------------------------------------------------------*/
15878 +
15879 +
15880 +#define RBUF_LEN (1024*1024)
15881 +static int rbuf_start;
15882 +static int rbuf_len;
15883 +static __u8 rbuf[RBUF_LEN];
15884 +
15885 +/*-------------------------------------------------------------------------*/
15886 +
15887 +#define DRIVER_VERSION "St Patrick's Day 2004"
15888 +
15889 +static const char shortname [] = "zero";
15890 +static const char longname [] = "YAMAHA YST-MS35D USB Speaker ";
15891 +
15892 +static const char source_sink [] = "source and sink data";
15893 +static const char loopback [] = "loop input to output";
15894 +
15895 +/*-------------------------------------------------------------------------*/
15896 +
15897 +/*
15898 + * driver assumes self-powered hardware, and
15899 + * has no way for users to trigger remote wakeup.
15900 + *
15901 + * this version autoconfigures as much as possible,
15902 + * which is reasonable for most "bulk-only" drivers.
15903 + */
15904 +static const char *EP_IN_NAME; /* source */
15905 +static const char *EP_OUT_NAME; /* sink */
15906 +
15907 +/*-------------------------------------------------------------------------*/
15908 +
15909 +/* big enough to hold our biggest descriptor */
15910 +#define USB_BUFSIZ 512
15911 +
15912 +struct zero_dev {
15913 + spinlock_t lock;
15914 + struct usb_gadget *gadget;
15915 + struct usb_request *req; /* for control responses */
15916 +
15917 + /* when configured, we have one of two configs:
15918 + * - source data (in to host) and sink it (out from host)
15919 + * - or loop it back (out from host back in to host)
15920 + */
15921 + u8 config;
15922 + struct usb_ep *in_ep, *out_ep;
15923 +
15924 + /* autoresume timer */
15925 + struct timer_list resume;
15926 +};
15927 +
15928 +#define xprintk(d,level,fmt,args...) \
15929 + dev_printk(level , &(d)->gadget->dev , fmt , ## args)
15930 +
15931 +#ifdef DEBUG
15932 +#define DBG(dev,fmt,args...) \
15933 + xprintk(dev , KERN_DEBUG , fmt , ## args)
15934 +#else
15935 +#define DBG(dev,fmt,args...) \
15936 + do { } while (0)
15937 +#endif /* DEBUG */
15938 +
15939 +#ifdef VERBOSE
15940 +#define VDBG DBG
15941 +#else
15942 +#define VDBG(dev,fmt,args...) \
15943 + do { } while (0)
15944 +#endif /* VERBOSE */
15945 +
15946 +#define ERROR(dev,fmt,args...) \
15947 + xprintk(dev , KERN_ERR , fmt , ## args)
15948 +#define WARN(dev,fmt,args...) \
15949 + xprintk(dev , KERN_WARNING , fmt , ## args)
15950 +#define INFO(dev,fmt,args...) \
15951 + xprintk(dev , KERN_INFO , fmt , ## args)
15952 +
15953 +/*-------------------------------------------------------------------------*/
15954 +
15955 +static unsigned buflen = 4096;
15956 +static unsigned qlen = 32;
15957 +static unsigned pattern = 0;
15958 +
15959 +module_param (buflen, uint, S_IRUGO|S_IWUSR);
15960 +module_param (qlen, uint, S_IRUGO|S_IWUSR);
15961 +module_param (pattern, uint, S_IRUGO|S_IWUSR);
15962 +
15963 +/*
15964 + * if it's nonzero, autoresume says how many seconds to wait
15965 + * before trying to wake up the host after suspend.
15966 + */
15967 +static unsigned autoresume = 0;
15968 +module_param (autoresume, uint, 0);
15969 +
15970 +/*
15971 + * Normally the "loopback" configuration is second (index 1) so
15972 + * it's not the default. Here's where to change that order, to
15973 + * work better with hosts where config changes are problematic.
15974 + * Or controllers (like superh) that only support one config.
15975 + */
15976 +static int loopdefault = 0;
15977 +
15978 +module_param (loopdefault, bool, S_IRUGO|S_IWUSR);
15979 +
15980 +/*-------------------------------------------------------------------------*/
15981 +
15982 +/* Thanks to NetChip Technologies for donating this product ID.
15983 + *
15984 + * DO NOT REUSE THESE IDs with a protocol-incompatible driver!! Ever!!
15985 + * Instead: allocate your own, using normal USB-IF procedures.
15986 + */
15987 +#ifndef CONFIG_USB_ZERO_HNPTEST
15988 +#define DRIVER_VENDOR_NUM 0x0525 /* NetChip */
15989 +#define DRIVER_PRODUCT_NUM 0xa4a0 /* Linux-USB "Gadget Zero" */
15990 +#else
15991 +#define DRIVER_VENDOR_NUM 0x1a0a /* OTG test device IDs */
15992 +#define DRIVER_PRODUCT_NUM 0xbadd
15993 +#endif
15994 +
15995 +/*-------------------------------------------------------------------------*/
15996 +
15997 +/*
15998 + * DESCRIPTORS ... most are static, but strings and (full)
15999 + * configuration descriptors are built on demand.
16000 + */
16001 +
16002 +/*
16003 +#define STRING_MANUFACTURER 25
16004 +#define STRING_PRODUCT 42
16005 +#define STRING_SERIAL 101
16006 +*/
16007 +#define STRING_MANUFACTURER 1
16008 +#define STRING_PRODUCT 2
16009 +#define STRING_SERIAL 3
16010 +
16011 +#define STRING_SOURCE_SINK 250
16012 +#define STRING_LOOPBACK 251
16013 +
16014 +/*
16015 + * This device advertises two configurations; these numbers work
16016 + * on a pxa250 as well as more flexible hardware.
16017 + */
16018 +#define CONFIG_SOURCE_SINK 3
16019 +#define CONFIG_LOOPBACK 2
16020 +
16021 +/*
16022 +static struct usb_device_descriptor
16023 +device_desc = {
16024 + .bLength = sizeof device_desc,
16025 + .bDescriptorType = USB_DT_DEVICE,
16026 +
16027 + .bcdUSB = __constant_cpu_to_le16 (0x0200),
16028 + .bDeviceClass = USB_CLASS_VENDOR_SPEC,
16029 +
16030 + .idVendor = __constant_cpu_to_le16 (DRIVER_VENDOR_NUM),
16031 + .idProduct = __constant_cpu_to_le16 (DRIVER_PRODUCT_NUM),
16032 + .iManufacturer = STRING_MANUFACTURER,
16033 + .iProduct = STRING_PRODUCT,
16034 + .iSerialNumber = STRING_SERIAL,
16035 + .bNumConfigurations = 2,
16036 +};
16037 +*/
16038 +static struct usb_device_descriptor
16039 +device_desc = {
16040 + .bLength = sizeof device_desc,
16041 + .bDescriptorType = USB_DT_DEVICE,
16042 + .bcdUSB = __constant_cpu_to_le16 (0x0100),
16043 + .bDeviceClass = USB_CLASS_PER_INTERFACE,
16044 + .bDeviceSubClass = 0,
16045 + .bDeviceProtocol = 0,
16046 + .bMaxPacketSize0 = 64,
16047 + .bcdDevice = __constant_cpu_to_le16 (0x0100),
16048 + .idVendor = __constant_cpu_to_le16 (0x0499),
16049 + .idProduct = __constant_cpu_to_le16 (0x3002),
16050 + .iManufacturer = STRING_MANUFACTURER,
16051 + .iProduct = STRING_PRODUCT,
16052 + .iSerialNumber = STRING_SERIAL,
16053 + .bNumConfigurations = 1,
16054 +};
16055 +
16056 +static struct usb_config_descriptor
16057 +z_config = {
16058 + .bLength = sizeof z_config,
16059 + .bDescriptorType = USB_DT_CONFIG,
16060 +
16061 + /* compute wTotalLength on the fly */
16062 + .bNumInterfaces = 2,
16063 + .bConfigurationValue = 1,
16064 + .iConfiguration = 0,
16065 + .bmAttributes = 0x40,
16066 + .bMaxPower = 0, /* self-powered */
16067 +};
16068 +
16069 +
16070 +static struct usb_otg_descriptor
16071 +otg_descriptor = {
16072 + .bLength = sizeof otg_descriptor,
16073 + .bDescriptorType = USB_DT_OTG,
16074 +
16075 + .bmAttributes = USB_OTG_SRP,
16076 +};
16077 +
16078 +/* one interface in each configuration */
16079 +#ifdef CONFIG_USB_GADGET_DUALSPEED
16080 +
16081 +/*
16082 + * usb 2.0 devices need to expose both high speed and full speed
16083 + * descriptors, unless they only run at full speed.
16084 + *
16085 + * that means alternate endpoint descriptors (bigger packets)
16086 + * and a "device qualifier" ... plus more construction options
16087 + * for the config descriptor.
16088 + */
16089 +
16090 +static struct usb_qualifier_descriptor
16091 +dev_qualifier = {
16092 + .bLength = sizeof dev_qualifier,
16093 + .bDescriptorType = USB_DT_DEVICE_QUALIFIER,
16094 +
16095 + .bcdUSB = __constant_cpu_to_le16 (0x0200),
16096 + .bDeviceClass = USB_CLASS_VENDOR_SPEC,
16097 +
16098 + .bNumConfigurations = 2,
16099 +};
16100 +
16101 +
16102 +struct usb_cs_as_general_descriptor {
16103 + __u8 bLength;
16104 + __u8 bDescriptorType;
16105 +
16106 + __u8 bDescriptorSubType;
16107 + __u8 bTerminalLink;
16108 + __u8 bDelay;
16109 + __u16 wFormatTag;
16110 +} __attribute__ ((packed));
16111 +
16112 +struct usb_cs_as_format_descriptor {
16113 + __u8 bLength;
16114 + __u8 bDescriptorType;
16115 +
16116 + __u8 bDescriptorSubType;
16117 + __u8 bFormatType;
16118 + __u8 bNrChannels;
16119 + __u8 bSubframeSize;
16120 + __u8 bBitResolution;
16121 + __u8 bSamfreqType;
16122 + __u8 tLowerSamFreq[3];
16123 + __u8 tUpperSamFreq[3];
16124 +} __attribute__ ((packed));
16125 +
16126 +static const struct usb_interface_descriptor
16127 +z_audio_control_if_desc = {
16128 + .bLength = sizeof z_audio_control_if_desc,
16129 + .bDescriptorType = USB_DT_INTERFACE,
16130 + .bInterfaceNumber = 0,
16131 + .bAlternateSetting = 0,
16132 + .bNumEndpoints = 0,
16133 + .bInterfaceClass = USB_CLASS_AUDIO,
16134 + .bInterfaceSubClass = 0x1,
16135 + .bInterfaceProtocol = 0,
16136 + .iInterface = 0,
16137 +};
16138 +
16139 +static const struct usb_interface_descriptor
16140 +z_audio_if_desc = {
16141 + .bLength = sizeof z_audio_if_desc,
16142 + .bDescriptorType = USB_DT_INTERFACE,
16143 + .bInterfaceNumber = 1,
16144 + .bAlternateSetting = 0,
16145 + .bNumEndpoints = 0,
16146 + .bInterfaceClass = USB_CLASS_AUDIO,
16147 + .bInterfaceSubClass = 0x2,
16148 + .bInterfaceProtocol = 0,
16149 + .iInterface = 0,
16150 +};
16151 +
16152 +static const struct usb_interface_descriptor
16153 +z_audio_if_desc2 = {
16154 + .bLength = sizeof z_audio_if_desc,
16155 + .bDescriptorType = USB_DT_INTERFACE,
16156 + .bInterfaceNumber = 1,
16157 + .bAlternateSetting = 1,
16158 + .bNumEndpoints = 1,
16159 + .bInterfaceClass = USB_CLASS_AUDIO,
16160 + .bInterfaceSubClass = 0x2,
16161 + .bInterfaceProtocol = 0,
16162 + .iInterface = 0,
16163 +};
16164 +
16165 +static const struct usb_cs_as_general_descriptor
16166 +z_audio_cs_as_if_desc = {
16167 + .bLength = 7,
16168 + .bDescriptorType = 0x24,
16169 +
16170 + .bDescriptorSubType = 0x01,
16171 + .bTerminalLink = 0x01,
16172 + .bDelay = 0x0,
16173 + .wFormatTag = __constant_cpu_to_le16 (0x0001)
16174 +};
16175 +
16176 +
16177 +static const struct usb_cs_as_format_descriptor
16178 +z_audio_cs_as_format_desc = {
16179 + .bLength = 0xe,
16180 + .bDescriptorType = 0x24,
16181 +
16182 + .bDescriptorSubType = 2,
16183 + .bFormatType = 1,
16184 + .bNrChannels = 1,
16185 + .bSubframeSize = 1,
16186 + .bBitResolution = 8,
16187 + .bSamfreqType = 0,
16188 + .tLowerSamFreq = {0x7e, 0x13, 0x00},
16189 + .tUpperSamFreq = {0xe2, 0xd6, 0x00},
16190 +};
16191 +
16192 +static const struct usb_endpoint_descriptor
16193 +z_iso_ep = {
16194 + .bLength = 0x09,
16195 + .bDescriptorType = 0x05,
16196 + .bEndpointAddress = 0x04,
16197 + .bmAttributes = 0x09,
16198 + .wMaxPacketSize = 0x0038,
16199 + .bInterval = 0x01,
16200 + .bRefresh = 0x00,
16201 + .bSynchAddress = 0x00,
16202 +};
16203 +
16204 +static char z_iso_ep2[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
16205 +
16206 +// 9 bytes
16207 +static char z_ac_interface_header_desc[] =
16208 +{ 0x09, 0x24, 0x01, 0x00, 0x01, 0x2b, 0x00, 0x01, 0x01 };
16209 +
16210 +// 12 bytes
16211 +static char z_0[] = {0x0c, 0x24, 0x02, 0x01, 0x01, 0x01, 0x00, 0x02,
16212 + 0x03, 0x00, 0x00, 0x00};
16213 +// 13 bytes
16214 +static char z_1[] = {0x0d, 0x24, 0x06, 0x02, 0x01, 0x02, 0x15, 0x00,
16215 + 0x02, 0x00, 0x02, 0x00, 0x00};
16216 +// 9 bytes
16217 +static char z_2[] = {0x09, 0x24, 0x03, 0x03, 0x01, 0x03, 0x00, 0x02,
16218 + 0x00};
16219 +
16220 +static char za_0[] = {0x09, 0x04, 0x01, 0x02, 0x01, 0x01, 0x02, 0x00,
16221 + 0x00};
16222 +
16223 +static char za_1[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
16224 +
16225 +static char za_2[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x01, 0x08, 0x00,
16226 + 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
16227 +
16228 +static char za_3[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
16229 + 0x00};
16230 +
16231 +static char za_4[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
16232 +
16233 +static char za_5[] = {0x09, 0x04, 0x01, 0x03, 0x01, 0x01, 0x02, 0x00,
16234 + 0x00};
16235 +
16236 +static char za_6[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
16237 +
16238 +static char za_7[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x02, 0x10, 0x00,
16239 + 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
16240 +
16241 +static char za_8[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
16242 + 0x00};
16243 +
16244 +static char za_9[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
16245 +
16246 +static char za_10[] = {0x09, 0x04, 0x01, 0x04, 0x01, 0x01, 0x02, 0x00,
16247 + 0x00};
16248 +
16249 +static char za_11[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
16250 +
16251 +static char za_12[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x02, 0x10, 0x00,
16252 + 0x73, 0x13, 0x00, 0xe2, 0xd6, 0x00};
16253 +
16254 +static char za_13[] = {0x09, 0x05, 0x04, 0x09, 0xe0, 0x00, 0x01, 0x00,
16255 + 0x00};
16256 +
16257 +static char za_14[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
16258 +
16259 +static char za_15[] = {0x09, 0x04, 0x01, 0x05, 0x01, 0x01, 0x02, 0x00,
16260 + 0x00};
16261 +
16262 +static char za_16[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
16263 +
16264 +static char za_17[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x03, 0x14, 0x00,
16265 + 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
16266 +
16267 +static char za_18[] = {0x09, 0x05, 0x04, 0x09, 0xa8, 0x00, 0x01, 0x00,
16268 + 0x00};
16269 +
16270 +static char za_19[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
16271 +
16272 +static char za_20[] = {0x09, 0x04, 0x01, 0x06, 0x01, 0x01, 0x02, 0x00,
16273 + 0x00};
16274 +
16275 +static char za_21[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
16276 +
16277 +static char za_22[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x03, 0x14, 0x00,
16278 + 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
16279 +
16280 +static char za_23[] = {0x09, 0x05, 0x04, 0x09, 0x50, 0x01, 0x01, 0x00,
16281 + 0x00};
16282 +
16283 +static char za_24[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
16284 +
16285 +
16286 +
16287 +static const struct usb_descriptor_header *z_function [] = {
16288 + (struct usb_descriptor_header *) &z_audio_control_if_desc,
16289 + (struct usb_descriptor_header *) &z_ac_interface_header_desc,
16290 + (struct usb_descriptor_header *) &z_0,
16291 + (struct usb_descriptor_header *) &z_1,
16292 + (struct usb_descriptor_header *) &z_2,
16293 + (struct usb_descriptor_header *) &z_audio_if_desc,
16294 + (struct usb_descriptor_header *) &z_audio_if_desc2,
16295 + (struct usb_descriptor_header *) &z_audio_cs_as_if_desc,
16296 + (struct usb_descriptor_header *) &z_audio_cs_as_format_desc,
16297 + (struct usb_descriptor_header *) &z_iso_ep,
16298 + (struct usb_descriptor_header *) &z_iso_ep2,
16299 + (struct usb_descriptor_header *) &za_0,
16300 + (struct usb_descriptor_header *) &za_1,
16301 + (struct usb_descriptor_header *) &za_2,
16302 + (struct usb_descriptor_header *) &za_3,
16303 + (struct usb_descriptor_header *) &za_4,
16304 + (struct usb_descriptor_header *) &za_5,
16305 + (struct usb_descriptor_header *) &za_6,
16306 + (struct usb_descriptor_header *) &za_7,
16307 + (struct usb_descriptor_header *) &za_8,
16308 + (struct usb_descriptor_header *) &za_9,
16309 + (struct usb_descriptor_header *) &za_10,
16310 + (struct usb_descriptor_header *) &za_11,
16311 + (struct usb_descriptor_header *) &za_12,
16312 + (struct usb_descriptor_header *) &za_13,
16313 + (struct usb_descriptor_header *) &za_14,
16314 + (struct usb_descriptor_header *) &za_15,
16315 + (struct usb_descriptor_header *) &za_16,
16316 + (struct usb_descriptor_header *) &za_17,
16317 + (struct usb_descriptor_header *) &za_18,
16318 + (struct usb_descriptor_header *) &za_19,
16319 + (struct usb_descriptor_header *) &za_20,
16320 + (struct usb_descriptor_header *) &za_21,
16321 + (struct usb_descriptor_header *) &za_22,
16322 + (struct usb_descriptor_header *) &za_23,
16323 + (struct usb_descriptor_header *) &za_24,
16324 + NULL,
16325 +};
16326 +
16327 +/* maxpacket and other transfer characteristics vary by speed. */
16328 +#define ep_desc(g,hs,fs) (((g)->speed==USB_SPEED_HIGH)?(hs):(fs))
16329 +
16330 +#else
16331 +
16332 +/* if there's no high speed support, maxpacket doesn't change. */
16333 +#define ep_desc(g,hs,fs) fs
16334 +
16335 +#endif /* !CONFIG_USB_GADGET_DUALSPEED */
16336 +
16337 +static char manufacturer [40];
16338 +//static char serial [40];
16339 +static char serial [] = "Ser 00 em";
16340 +
16341 +/* static strings, in UTF-8 */
16342 +static struct usb_string strings [] = {
16343 + { STRING_MANUFACTURER, manufacturer, },
16344 + { STRING_PRODUCT, longname, },
16345 + { STRING_SERIAL, serial, },
16346 + { STRING_LOOPBACK, loopback, },
16347 + { STRING_SOURCE_SINK, source_sink, },
16348 + { } /* end of list */
16349 +};
16350 +
16351 +static struct usb_gadget_strings stringtab = {
16352 + .language = 0x0409, /* en-us */
16353 + .strings = strings,
16354 +};
16355 +
16356 +/*
16357 + * config descriptors are also handcrafted. these must agree with code
16358 + * that sets configurations, and with code managing interfaces and their
16359 + * altsettings. other complexity may come from:
16360 + *
16361 + * - high speed support, including "other speed config" rules
16362 + * - multiple configurations
16363 + * - interfaces with alternate settings
16364 + * - embedded class or vendor-specific descriptors
16365 + *
16366 + * this handles high speed, and has a second config that could as easily
16367 + * have been an alternate interface setting (on most hardware).
16368 + *
16369 + * NOTE: to demonstrate (and test) more USB capabilities, this driver
16370 + * should include an altsetting to test interrupt transfers, including
16371 + * high bandwidth modes at high speed. (Maybe work like Intel's test
16372 + * device?)
16373 + */
16374 +static int
16375 +config_buf (struct usb_gadget *gadget, u8 *buf, u8 type, unsigned index)
16376 +{
16377 + int len;
16378 + const struct usb_descriptor_header **function;
16379 +
16380 + function = z_function;
16381 + len = usb_gadget_config_buf (&z_config, buf, USB_BUFSIZ, function);
16382 + if (len < 0)
16383 + return len;
16384 + ((struct usb_config_descriptor *) buf)->bDescriptorType = type;
16385 + return len;
16386 +}
16387 +
16388 +/*-------------------------------------------------------------------------*/
16389 +
16390 +static struct usb_request *
16391 +alloc_ep_req (struct usb_ep *ep, unsigned length)
16392 +{
16393 + struct usb_request *req;
16394 +
16395 + req = usb_ep_alloc_request (ep, GFP_ATOMIC);
16396 + if (req) {
16397 + req->length = length;
16398 + req->buf = usb_ep_alloc_buffer (ep, length,
16399 + &req->dma, GFP_ATOMIC);
16400 + if (!req->buf) {
16401 + usb_ep_free_request (ep, req);
16402 + req = NULL;
16403 + }
16404 + }
16405 + return req;
16406 +}
16407 +
16408 +static void free_ep_req (struct usb_ep *ep, struct usb_request *req)
16409 +{
16410 + if (req->buf)
16411 + usb_ep_free_buffer (ep, req->buf, req->dma, req->length);
16412 + usb_ep_free_request (ep, req);
16413 +}
16414 +
16415 +/*-------------------------------------------------------------------------*/
16416 +
16417 +/* optionally require specific source/sink data patterns */
16418 +
16419 +static int
16420 +check_read_data (
16421 + struct zero_dev *dev,
16422 + struct usb_ep *ep,
16423 + struct usb_request *req
16424 +)
16425 +{
16426 + unsigned i;
16427 + u8 *buf = req->buf;
16428 +
16429 + for (i = 0; i < req->actual; i++, buf++) {
16430 + switch (pattern) {
16431 + /* all-zeroes has no synchronization issues */
16432 + case 0:
16433 + if (*buf == 0)
16434 + continue;
16435 + break;
16436 + /* mod63 stays in sync with short-terminated transfers,
16437 + * or otherwise when host and gadget agree on how large
16438 + * each usb transfer request should be. resync is done
16439 + * with set_interface or set_config.
16440 + */
16441 + case 1:
16442 + if (*buf == (u8)(i % 63))
16443 + continue;
16444 + break;
16445 + }
16446 + ERROR (dev, "bad OUT byte, buf [%d] = %d\n", i, *buf);
16447 + usb_ep_set_halt (ep);
16448 + return -EINVAL;
16449 + }
16450 + return 0;
16451 +}
16452 +
16453 +/*-------------------------------------------------------------------------*/
16454 +
16455 +static void zero_reset_config (struct zero_dev *dev)
16456 +{
16457 + if (dev->config == 0)
16458 + return;
16459 +
16460 + DBG (dev, "reset config\n");
16461 +
16462 + /* just disable endpoints, forcing completion of pending i/o.
16463 + * all our completion handlers free their requests in this case.
16464 + */
16465 + if (dev->in_ep) {
16466 + usb_ep_disable (dev->in_ep);
16467 + dev->in_ep = NULL;
16468 + }
16469 + if (dev->out_ep) {
16470 + usb_ep_disable (dev->out_ep);
16471 + dev->out_ep = NULL;
16472 + }
16473 + dev->config = 0;
16474 + del_timer (&dev->resume);
16475 +}
16476 +
16477 +#define _write(f, buf, sz) (f->f_op->write(f, buf, sz, &f->f_pos))
16478 +
16479 +static void
16480 +zero_isoc_complete (struct usb_ep *ep, struct usb_request *req)
16481 +{
16482 + struct zero_dev *dev = ep->driver_data;
16483 + int status = req->status;
16484 + int i, j;
16485 +
16486 + switch (status) {
16487 +
16488 + case 0: /* normal completion? */
16489 + //printk ("\nzero ---------------> isoc normal completion %d bytes\n", req->actual);
16490 + for (i=0, j=rbuf_start; i<req->actual; i++) {
16491 + //printk ("%02x ", ((__u8*)req->buf)[i]);
16492 + rbuf[j] = ((__u8*)req->buf)[i];
16493 + j++;
16494 + if (j >= RBUF_LEN) j=0;
16495 + }
16496 + rbuf_start = j;
16497 + //printk ("\n\n");
16498 +
16499 + if (rbuf_len < RBUF_LEN) {
16500 + rbuf_len += req->actual;
16501 + if (rbuf_len > RBUF_LEN) {
16502 + rbuf_len = RBUF_LEN;
16503 + }
16504 + }
16505 +
16506 + break;
16507 +
16508 + /* this endpoint is normally active while we're configured */
16509 + case -ECONNABORTED: /* hardware forced ep reset */
16510 + case -ECONNRESET: /* request dequeued */
16511 + case -ESHUTDOWN: /* disconnect from host */
16512 + VDBG (dev, "%s gone (%d), %d/%d\n", ep->name, status,
16513 + req->actual, req->length);
16514 + if (ep == dev->out_ep)
16515 + check_read_data (dev, ep, req);
16516 + free_ep_req (ep, req);
16517 + return;
16518 +
16519 + case -EOVERFLOW: /* buffer overrun on read means that
16520 + * we didn't provide a big enough
16521 + * buffer.
16522 + */
16523 + default:
16524 +#if 1
16525 + DBG (dev, "%s complete --> %d, %d/%d\n", ep->name,
16526 + status, req->actual, req->length);
16527 +#endif
16528 + case -EREMOTEIO: /* short read */
16529 + break;
16530 + }
16531 +
16532 + status = usb_ep_queue (ep, req, GFP_ATOMIC);
16533 + if (status) {
16534 + ERROR (dev, "kill %s: resubmit %d bytes --> %d\n",
16535 + ep->name, req->length, status);
16536 + usb_ep_set_halt (ep);
16537 + /* FIXME recover later ... somehow */
16538 + }
16539 +}
16540 +
16541 +static struct usb_request *
16542 +zero_start_isoc_ep (struct usb_ep *ep, int gfp_flags)
16543 +{
16544 + struct usb_request *req;
16545 + int status;
16546 +
16547 + req = alloc_ep_req (ep, 512);
16548 + if (!req)
16549 + return NULL;
16550 +
16551 + req->complete = zero_isoc_complete;
16552 +
16553 + status = usb_ep_queue (ep, req, gfp_flags);
16554 + if (status) {
16555 + struct zero_dev *dev = ep->driver_data;
16556 +
16557 + ERROR (dev, "start %s --> %d\n", ep->name, status);
16558 + free_ep_req (ep, req);
16559 + req = NULL;
16560 + }
16561 +
16562 + return req;
16563 +}
16564 +
16565 +/* change our operational config. this code must agree with the code
16566 + * that returns config descriptors, and altsetting code.
16567 + *
16568 + * it's also responsible for power management interactions. some
16569 + * configurations might not work with our current power sources.
16570 + *
16571 + * note that some device controller hardware will constrain what this
16572 + * code can do, perhaps by disallowing more than one configuration or
16573 + * by limiting configuration choices (like the pxa2xx).
16574 + */
16575 +static int
16576 +zero_set_config (struct zero_dev *dev, unsigned number, int gfp_flags)
16577 +{
16578 + int result = 0;
16579 + struct usb_gadget *gadget = dev->gadget;
16580 + const struct usb_endpoint_descriptor *d;
16581 + struct usb_ep *ep;
16582 +
16583 + if (number == dev->config)
16584 + return 0;
16585 +
16586 + zero_reset_config (dev);
16587 +
16588 + gadget_for_each_ep (ep, gadget) {
16589 +
16590 + if (strcmp (ep->name, "ep4") == 0) {
16591 +
16592 + d = (struct usb_endpoint_descripter *)&za_23; // isoc ep desc for audio i/f alt setting 6
16593 + result = usb_ep_enable (ep, d);
16594 +
16595 + if (result == 0) {
16596 + ep->driver_data = dev;
16597 + dev->in_ep = ep;
16598 +
16599 + if (zero_start_isoc_ep (ep, gfp_flags) != 0) {
16600 +
16601 + dev->in_ep = ep;
16602 + continue;
16603 + }
16604 +
16605 + usb_ep_disable (ep);
16606 + result = -EIO;
16607 + }
16608 + }
16609 +
16610 + }
16611 +
16612 + dev->config = number;
16613 + return result;
16614 +}
16615 +
16616 +/*-------------------------------------------------------------------------*/
16617 +
16618 +static void zero_setup_complete (struct usb_ep *ep, struct usb_request *req)
16619 +{
16620 + if (req->status || req->actual != req->length)
16621 + DBG ((struct zero_dev *) ep->driver_data,
16622 + "setup complete --> %d, %d/%d\n",
16623 + req->status, req->actual, req->length);
16624 +}
16625 +
16626 +/*
16627 + * The setup() callback implements all the ep0 functionality that's
16628 + * not handled lower down, in hardware or the hardware driver (like
16629 + * device and endpoint feature flags, and their status). It's all
16630 + * housekeeping for the gadget function we're implementing. Most of
16631 + * the work is in config-specific setup.
16632 + */
16633 +static int
16634 +zero_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
16635 +{
16636 + struct zero_dev *dev = get_gadget_data (gadget);
16637 + struct usb_request *req = dev->req;
16638 + int value = -EOPNOTSUPP;
16639 +
16640 + /* usually this stores reply data in the pre-allocated ep0 buffer,
16641 + * but config change events will reconfigure hardware.
16642 + */
16643 + req->zero = 0;
16644 + switch (ctrl->bRequest) {
16645 +
16646 + case USB_REQ_GET_DESCRIPTOR:
16647 +
16648 + switch (ctrl->wValue >> 8) {
16649 +
16650 + case USB_DT_DEVICE:
16651 + value = min (ctrl->wLength, (u16) sizeof device_desc);
16652 + memcpy (req->buf, &device_desc, value);
16653 + break;
16654 +#ifdef CONFIG_USB_GADGET_DUALSPEED
16655 + case USB_DT_DEVICE_QUALIFIER:
16656 + if (!gadget->is_dualspeed)
16657 + break;
16658 + value = min (ctrl->wLength, (u16) sizeof dev_qualifier);
16659 + memcpy (req->buf, &dev_qualifier, value);
16660 + break;
16661 +
16662 + case USB_DT_OTHER_SPEED_CONFIG:
16663 + if (!gadget->is_dualspeed)
16664 + break;
16665 + // FALLTHROUGH
16666 +#endif /* CONFIG_USB_GADGET_DUALSPEED */
16667 + case USB_DT_CONFIG:
16668 + value = config_buf (gadget, req->buf,
16669 + ctrl->wValue >> 8,
16670 + ctrl->wValue & 0xff);
16671 + if (value >= 0)
16672 + value = min (ctrl->wLength, (u16) value);
16673 + break;
16674 +
16675 + case USB_DT_STRING:
16676 + /* wIndex == language code.
16677 + * this driver only handles one language, you can
16678 + * add string tables for other languages, using
16679 + * any UTF-8 characters
16680 + */
16681 + value = usb_gadget_get_string (&stringtab,
16682 + ctrl->wValue & 0xff, req->buf);
16683 + if (value >= 0) {
16684 + value = min (ctrl->wLength, (u16) value);
16685 + }
16686 + break;
16687 + }
16688 + break;
16689 +
16690 + /* currently two configs, two speeds */
16691 + case USB_REQ_SET_CONFIGURATION:
16692 + if (ctrl->bRequestType != 0)
16693 + goto unknown;
16694 +
16695 + spin_lock (&dev->lock);
16696 + value = zero_set_config (dev, ctrl->wValue, GFP_ATOMIC);
16697 + spin_unlock (&dev->lock);
16698 + break;
16699 + case USB_REQ_GET_CONFIGURATION:
16700 + if (ctrl->bRequestType != USB_DIR_IN)
16701 + goto unknown;
16702 + *(u8 *)req->buf = dev->config;
16703 + value = min (ctrl->wLength, (u16) 1);
16704 + break;
16705 +
16706 + /* until we add altsetting support, or other interfaces,
16707 + * only 0/0 are possible. pxa2xx only supports 0/0 (poorly)
16708 + * and already killed pending endpoint I/O.
16709 + */
16710 + case USB_REQ_SET_INTERFACE:
16711 +
16712 + if (ctrl->bRequestType != USB_RECIP_INTERFACE)
16713 + goto unknown;
16714 + spin_lock (&dev->lock);
16715 + if (dev->config) {
16716 + u8 config = dev->config;
16717 +
16718 + /* resets interface configuration, forgets about
16719 + * previous transaction state (queued bufs, etc)
16720 + * and re-inits endpoint state (toggle etc)
16721 + * no response queued, just zero status == success.
16722 + * if we had more than one interface we couldn't
16723 + * use this "reset the config" shortcut.
16724 + */
16725 + zero_reset_config (dev);
16726 + zero_set_config (dev, config, GFP_ATOMIC);
16727 + value = 0;
16728 + }
16729 + spin_unlock (&dev->lock);
16730 + break;
16731 + case USB_REQ_GET_INTERFACE:
16732 + if ((ctrl->bRequestType == 0x21) && (ctrl->wIndex == 0x02)) {
16733 + value = ctrl->wLength;
16734 + break;
16735 + }
16736 + else {
16737 + if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE))
16738 + goto unknown;
16739 + if (!dev->config)
16740 + break;
16741 + if (ctrl->wIndex != 0) {
16742 + value = -EDOM;
16743 + break;
16744 + }
16745 + *(u8 *)req->buf = 0;
16746 + value = min (ctrl->wLength, (u16) 1);
16747 + }
16748 + break;
16749 +
16750 + /*
16751 + * These are the same vendor-specific requests supported by
16752 + * Intel's USB 2.0 compliance test devices. We exceed that
16753 + * device spec by allowing multiple-packet requests.
16754 + */
16755 + case 0x5b: /* control WRITE test -- fill the buffer */
16756 + if (ctrl->bRequestType != (USB_DIR_OUT|USB_TYPE_VENDOR))
16757 + goto unknown;
16758 + if (ctrl->wValue || ctrl->wIndex)
16759 + break;
16760 + /* just read that many bytes into the buffer */
16761 + if (ctrl->wLength > USB_BUFSIZ)
16762 + break;
16763 + value = ctrl->wLength;
16764 + break;
16765 + case 0x5c: /* control READ test -- return the buffer */
16766 + if (ctrl->bRequestType != (USB_DIR_IN|USB_TYPE_VENDOR))
16767 + goto unknown;
16768 + if (ctrl->wValue || ctrl->wIndex)
16769 + break;
16770 + /* expect those bytes are still in the buffer; send back */
16771 + if (ctrl->wLength > USB_BUFSIZ
16772 + || ctrl->wLength != req->length)
16773 + break;
16774 + value = ctrl->wLength;
16775 + break;
16776 +
16777 + case 0x01: // SET_CUR
16778 + case 0x02:
16779 + case 0x03:
16780 + case 0x04:
16781 + case 0x05:
16782 + value = ctrl->wLength;
16783 + break;
16784 + case 0x81:
16785 + switch (ctrl->wValue) {
16786 + case 0x0201:
16787 + case 0x0202:
16788 + ((u8*)req->buf)[0] = 0x00;
16789 + ((u8*)req->buf)[1] = 0xe3;
16790 + break;
16791 + case 0x0300:
16792 + case 0x0500:
16793 + ((u8*)req->buf)[0] = 0x00;
16794 + break;
16795 + }
16796 + //((u8*)req->buf)[0] = 0x81;
16797 + //((u8*)req->buf)[1] = 0x81;
16798 + value = ctrl->wLength;
16799 + break;
16800 + case 0x82:
16801 + switch (ctrl->wValue) {
16802 + case 0x0201:
16803 + case 0x0202:
16804 + ((u8*)req->buf)[0] = 0x00;
16805 + ((u8*)req->buf)[1] = 0xc3;
16806 + break;
16807 + case 0x0300:
16808 + case 0x0500:
16809 + ((u8*)req->buf)[0] = 0x00;
16810 + break;
16811 + }
16812 + //((u8*)req->buf)[0] = 0x82;
16813 + //((u8*)req->buf)[1] = 0x82;
16814 + value = ctrl->wLength;
16815 + break;
16816 + case 0x83:
16817 + switch (ctrl->wValue) {
16818 + case 0x0201:
16819 + case 0x0202:
16820 + ((u8*)req->buf)[0] = 0x00;
16821 + ((u8*)req->buf)[1] = 0x00;
16822 + break;
16823 + case 0x0300:
16824 + ((u8*)req->buf)[0] = 0x60;
16825 + break;
16826 + case 0x0500:
16827 + ((u8*)req->buf)[0] = 0x18;
16828 + break;
16829 + }
16830 + //((u8*)req->buf)[0] = 0x83;
16831 + //((u8*)req->buf)[1] = 0x83;
16832 + value = ctrl->wLength;
16833 + break;
16834 + case 0x84:
16835 + switch (ctrl->wValue) {
16836 + case 0x0201:
16837 + case 0x0202:
16838 + ((u8*)req->buf)[0] = 0x00;
16839 + ((u8*)req->buf)[1] = 0x01;
16840 + break;
16841 + case 0x0300:
16842 + case 0x0500:
16843 + ((u8*)req->buf)[0] = 0x08;
16844 + break;
16845 + }
16846 + //((u8*)req->buf)[0] = 0x84;
16847 + //((u8*)req->buf)[1] = 0x84;
16848 + value = ctrl->wLength;
16849 + break;
16850 + case 0x85:
16851 + ((u8*)req->buf)[0] = 0x85;
16852 + ((u8*)req->buf)[1] = 0x85;
16853 + value = ctrl->wLength;
16854 + break;
16855 +
16856 +
16857 + default:
16858 +unknown:
16859 + printk("unknown control req%02x.%02x v%04x i%04x l%d\n",
16860 + ctrl->bRequestType, ctrl->bRequest,
16861 + ctrl->wValue, ctrl->wIndex, ctrl->wLength);
16862 + }
16863 +
16864 + /* respond with data transfer before status phase? */
16865 + if (value >= 0) {
16866 + req->length = value;
16867 + req->zero = value < ctrl->wLength
16868 + && (value % gadget->ep0->maxpacket) == 0;
16869 + value = usb_ep_queue (gadget->ep0, req, GFP_ATOMIC);
16870 + if (value < 0) {
16871 + DBG (dev, "ep_queue < 0 --> %d\n", value);
16872 + req->status = 0;
16873 + zero_setup_complete (gadget->ep0, req);
16874 + }
16875 + }
16876 +
16877 + /* device either stalls (value < 0) or reports success */
16878 + return value;
16879 +}
16880 +
16881 +static void
16882 +zero_disconnect (struct usb_gadget *gadget)
16883 +{
16884 + struct zero_dev *dev = get_gadget_data (gadget);
16885 + unsigned long flags;
16886 +
16887 + spin_lock_irqsave (&dev->lock, flags);
16888 + zero_reset_config (dev);
16889 +
16890 + /* a more significant application might have some non-usb
16891 + * activities to quiesce here, saving resources like power
16892 + * or pushing the notification up a network stack.
16893 + */
16894 + spin_unlock_irqrestore (&dev->lock, flags);
16895 +
16896 + /* next we may get setup() calls to enumerate new connections;
16897 + * or an unbind() during shutdown (including removing module).
16898 + */
16899 +}
16900 +
16901 +static void
16902 +zero_autoresume (unsigned long _dev)
16903 +{
16904 + struct zero_dev *dev = (struct zero_dev *) _dev;
16905 + int status;
16906 +
16907 + /* normally the host would be woken up for something
16908 + * more significant than just a timer firing...
16909 + */
16910 + if (dev->gadget->speed != USB_SPEED_UNKNOWN) {
16911 + status = usb_gadget_wakeup (dev->gadget);
16912 + DBG (dev, "wakeup --> %d\n", status);
16913 + }
16914 +}
16915 +
16916 +/*-------------------------------------------------------------------------*/
16917 +
16918 +static void
16919 +zero_unbind (struct usb_gadget *gadget)
16920 +{
16921 + struct zero_dev *dev = get_gadget_data (gadget);
16922 +
16923 + DBG (dev, "unbind\n");
16924 +
16925 + /* we've already been disconnected ... no i/o is active */
16926 + if (dev->req)
16927 + free_ep_req (gadget->ep0, dev->req);
16928 + del_timer_sync (&dev->resume);
16929 + kfree (dev);
16930 + set_gadget_data (gadget, NULL);
16931 +}
16932 +
16933 +static int
16934 +zero_bind (struct usb_gadget *gadget)
16935 +{
16936 + struct zero_dev *dev;
16937 + //struct usb_ep *ep;
16938 +
16939 + printk("binding\n");
16940 + /*
16941 + * DRIVER POLICY CHOICE: you may want to do this differently.
16942 + * One thing to avoid is reusing a bcdDevice revision code
16943 + * with different host-visible configurations or behavior
16944 + * restrictions -- using ep1in/ep2out vs ep1out/ep3in, etc
16945 + */
16946 + //device_desc.bcdDevice = __constant_cpu_to_le16 (0x0201);
16947 +
16948 +
16949 + /* ok, we made sense of the hardware ... */
16950 + dev = kmalloc (sizeof *dev, SLAB_KERNEL);
16951 + if (!dev)
16952 + return -ENOMEM;
16953 + memset (dev, 0, sizeof *dev);
16954 + spin_lock_init (&dev->lock);
16955 + dev->gadget = gadget;
16956 + set_gadget_data (gadget, dev);
16957 +
16958 + /* preallocate control response and buffer */
16959 + dev->req = usb_ep_alloc_request (gadget->ep0, GFP_KERNEL);
16960 + if (!dev->req)
16961 + goto enomem;
16962 + dev->req->buf = usb_ep_alloc_buffer (gadget->ep0, USB_BUFSIZ,
16963 + &dev->req->dma, GFP_KERNEL);
16964 + if (!dev->req->buf)
16965 + goto enomem;
16966 +
16967 + dev->req->complete = zero_setup_complete;
16968 +
16969 + device_desc.bMaxPacketSize0 = gadget->ep0->maxpacket;
16970 +
16971 +#ifdef CONFIG_USB_GADGET_DUALSPEED
16972 + /* assume ep0 uses the same value for both speeds ... */
16973 + dev_qualifier.bMaxPacketSize0 = device_desc.bMaxPacketSize0;
16974 +
16975 + /* and that all endpoints are dual-speed */
16976 + //hs_source_desc.bEndpointAddress = fs_source_desc.bEndpointAddress;
16977 + //hs_sink_desc.bEndpointAddress = fs_sink_desc.bEndpointAddress;
16978 +#endif
16979 +
16980 + usb_gadget_set_selfpowered (gadget);
16981 +
16982 + init_timer (&dev->resume);
16983 + dev->resume.function = zero_autoresume;
16984 + dev->resume.data = (unsigned long) dev;
16985 +
16986 + gadget->ep0->driver_data = dev;
16987 +
16988 + INFO (dev, "%s, version: " DRIVER_VERSION "\n", longname);
16989 + INFO (dev, "using %s, OUT %s IN %s\n", gadget->name,
16990 + EP_OUT_NAME, EP_IN_NAME);
16991 +
16992 + snprintf (manufacturer, sizeof manufacturer,
16993 + UTS_SYSNAME " " UTS_RELEASE " with %s",
16994 + gadget->name);
16995 +
16996 + return 0;
16997 +
16998 +enomem:
16999 + zero_unbind (gadget);
17000 + return -ENOMEM;
17001 +}
17002 +
17003 +/*-------------------------------------------------------------------------*/
17004 +
17005 +static void
17006 +zero_suspend (struct usb_gadget *gadget)
17007 +{
17008 + struct zero_dev *dev = get_gadget_data (gadget);
17009 +
17010 + if (gadget->speed == USB_SPEED_UNKNOWN)
17011 + return;
17012 +
17013 + if (autoresume) {
17014 + mod_timer (&dev->resume, jiffies + (HZ * autoresume));
17015 + DBG (dev, "suspend, wakeup in %d seconds\n", autoresume);
17016 + } else
17017 + DBG (dev, "suspend\n");
17018 +}
17019 +
17020 +static void
17021 +zero_resume (struct usb_gadget *gadget)
17022 +{
17023 + struct zero_dev *dev = get_gadget_data (gadget);
17024 +
17025 + DBG (dev, "resume\n");
17026 + del_timer (&dev->resume);
17027 +}
17028 +
17029 +
17030 +/*-------------------------------------------------------------------------*/
17031 +
17032 +static struct usb_gadget_driver zero_driver = {
17033 +#ifdef CONFIG_USB_GADGET_DUALSPEED
17034 + .speed = USB_SPEED_HIGH,
17035 +#else
17036 + .speed = USB_SPEED_FULL,
17037 +#endif
17038 + .function = (char *) longname,
17039 + .bind = zero_bind,
17040 + .unbind = zero_unbind,
17041 +
17042 + .setup = zero_setup,
17043 + .disconnect = zero_disconnect,
17044 +
17045 + .suspend = zero_suspend,
17046 + .resume = zero_resume,
17047 +
17048 + .driver = {
17049 + .name = (char *) shortname,
17050 + // .shutdown = ...
17051 + // .suspend = ...
17052 + // .resume = ...
17053 + },
17054 +};
17055 +
17056 +MODULE_AUTHOR ("David Brownell");
17057 +MODULE_LICENSE ("Dual BSD/GPL");
17058 +
17059 +static struct proc_dir_entry *pdir, *pfile;
17060 +
17061 +static int isoc_read_data (char *page, char **start,
17062 + off_t off, int count,
17063 + int *eof, void *data)
17064 +{
17065 + int i;
17066 + static int c = 0;
17067 + static int done = 0;
17068 + static int s = 0;
17069 +
17070 +/*
17071 + printk ("\ncount: %d\n", count);
17072 + printk ("rbuf_start: %d\n", rbuf_start);
17073 + printk ("rbuf_len: %d\n", rbuf_len);
17074 + printk ("off: %d\n", off);
17075 + printk ("start: %p\n\n", *start);
17076 +*/
17077 + if (done) {
17078 + c = 0;
17079 + done = 0;
17080 + *eof = 1;
17081 + return 0;
17082 + }
17083 +
17084 + if (c == 0) {
17085 + if (rbuf_len == RBUF_LEN)
17086 + s = rbuf_start;
17087 + else s = 0;
17088 + }
17089 +
17090 + for (i=0; i<count && c<rbuf_len; i++, c++) {
17091 + page[i] = rbuf[(c+s) % RBUF_LEN];
17092 + }
17093 + *start = page;
17094 +
17095 + if (c >= rbuf_len) {
17096 + *eof = 1;
17097 + done = 1;
17098 + }
17099 +
17100 +
17101 + return i;
17102 +}
17103 +
17104 +static int __init init (void)
17105 +{
17106 +
17107 + int retval = 0;
17108 +
17109 + pdir = proc_mkdir("isoc_test", NULL);
17110 + if(pdir == NULL) {
17111 + retval = -ENOMEM;
17112 + printk("Error creating dir\n");
17113 + goto done;
17114 + }
17115 + pdir->owner = THIS_MODULE;
17116 +
17117 + pfile = create_proc_read_entry("isoc_data",
17118 + 0444, pdir,
17119 + isoc_read_data,
17120 + NULL);
17121 + if (pfile == NULL) {
17122 + retval = -ENOMEM;
17123 + printk("Error creating file\n");
17124 + goto no_file;
17125 + }
17126 + pfile->owner = THIS_MODULE;
17127 +
17128 + return usb_gadget_register_driver (&zero_driver);
17129 +
17130 + no_file:
17131 + remove_proc_entry("isoc_data", NULL);
17132 + done:
17133 + return retval;
17134 +}
17135 +module_init (init);
17136 +
17137 +static void __exit cleanup (void)
17138 +{
17139 +
17140 + usb_gadget_unregister_driver (&zero_driver);
17141 +
17142 + remove_proc_entry("isoc_data", pdir);
17143 + remove_proc_entry("isoc_test", NULL);
17144 +}
17145 +module_exit (cleanup);
17146 --- /dev/null
17147 +++ b/drivers/usb/host/dwc_otg/dwc_cfi_common.h
17148 @@ -0,0 +1,142 @@
17149 +/* ==========================================================================
17150 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
17151 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
17152 + * otherwise expressly agreed to in writing between Synopsys and you.
17153 + *
17154 + * The Software IS NOT an item of Licensed Software or Licensed Product under
17155 + * any End User Software License Agreement or Agreement for Licensed Product
17156 + * with Synopsys or any supplement thereto. You are permitted to use and
17157 + * redistribute this Software in source and binary forms, with or without
17158 + * modification, provided that redistributions of source code must retain this
17159 + * notice. You may not view, use, disclose, copy or distribute this file or
17160 + * any information contained herein except pursuant to this license grant from
17161 + * Synopsys. If you do not agree with this notice, including the disclaimer
17162 + * below, then you are not authorized to use the Software.
17163 + *
17164 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
17165 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17166 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17167 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
17168 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
17169 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
17170 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
17171 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
17172 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
17173 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
17174 + * DAMAGE.
17175 + * ========================================================================== */
17176 +
17177 +#if !defined(__DWC_CFI_COMMON_H__)
17178 +#define __DWC_CFI_COMMON_H__
17179 +
17180 +//#include <linux/types.h>
17181 +
17182 +/**
17183 + * @file
17184 + *
17185 + * This file contains the CFI specific common constants, interfaces
17186 + * (functions and macros) and structures for Linux. No PCD specific
17187 + * data structure or definition is to be included in this file.
17188 + *
17189 + */
17190 +
17191 +/** This is a request for all Core Features */
17192 +#define VEN_CORE_GET_FEATURES 0xB1
17193 +
17194 +/** This is a request to get the value of a specific Core Feature */
17195 +#define VEN_CORE_GET_FEATURE 0xB2
17196 +
17197 +/** This command allows the host to set the value of a specific Core Feature */
17198 +#define VEN_CORE_SET_FEATURE 0xB3
17199 +
17200 +/** This command allows the host to set the default values of
17201 + * either all or any specific Core Feature
17202 + */
17203 +#define VEN_CORE_RESET_FEATURES 0xB4
17204 +
17205 +/** This command forces the PCD to write the deferred values of a Core Features */
17206 +#define VEN_CORE_ACTIVATE_FEATURES 0xB5
17207 +
17208 +/** This request reads a DWORD value from a register at the specified offset */
17209 +#define VEN_CORE_READ_REGISTER 0xB6
17210 +
17211 +/** This request writes a DWORD value into a register at the specified offset */
17212 +#define VEN_CORE_WRITE_REGISTER 0xB7
17213 +
17214 +/** This structure is the header of the Core Features dataset returned to
17215 + * the Host
17216 + */
17217 +struct cfi_all_features_header {
17218 +/** The features header structure length is */
17219 +#define CFI_ALL_FEATURES_HDR_LEN 8
17220 + /**
17221 + * The total length of the features dataset returned to the Host
17222 + */
17223 + uint16_t wTotalLen;
17224 +
17225 + /**
17226 + * CFI version number inBinary-Coded Decimal (i.e., 1.00 is 100H).
17227 + * This field identifies the version of the CFI Specification with which
17228 + * the device is compliant.
17229 + */
17230 + uint16_t wVersion;
17231 +
17232 + /** The ID of the Core */
17233 + uint16_t wCoreID;
17234 +#define CFI_CORE_ID_UDC 1
17235 +#define CFI_CORE_ID_OTG 2
17236 +#define CFI_CORE_ID_WUDEV 3
17237 +
17238 + /** Number of features returned by VEN_CORE_GET_FEATURES request */
17239 + uint16_t wNumFeatures;
17240 +} UPACKED;
17241 +
17242 +typedef struct cfi_all_features_header cfi_all_features_header_t;
17243 +
17244 +/** This structure is a header of the Core Feature descriptor dataset returned to
17245 + * the Host after the VEN_CORE_GET_FEATURES request
17246 + */
17247 +struct cfi_feature_desc_header {
17248 +#define CFI_FEATURE_DESC_HDR_LEN 8
17249 +
17250 + /** The feature ID */
17251 + uint16_t wFeatureID;
17252 +
17253 + /** Length of this feature descriptor in bytes - including the
17254 + * length of the feature name string
17255 + */
17256 + uint16_t wLength;
17257 +
17258 + /** The data length of this feature in bytes */
17259 + uint16_t wDataLength;
17260 +
17261 + /**
17262 + * Attributes of this features
17263 + * D0: Access rights
17264 + * 0 - Read/Write
17265 + * 1 - Read only
17266 + */
17267 + uint8_t bmAttributes;
17268 +#define CFI_FEATURE_ATTR_RO 1
17269 +#define CFI_FEATURE_ATTR_RW 0
17270 +
17271 + /** Length of the feature name in bytes */
17272 + uint8_t bNameLen;
17273 +
17274 + /** The feature name buffer */
17275 + //uint8_t *name;
17276 +} UPACKED;
17277 +
17278 +typedef struct cfi_feature_desc_header cfi_feature_desc_header_t;
17279 +
17280 +/**
17281 + * This structure describes a NULL terminated string referenced by its id field.
17282 + * It is very similar to usb_string structure but has the id field type set to 16-bit.
17283 + */
17284 +struct cfi_string {
17285 + uint16_t id;
17286 + const uint8_t *s;
17287 +};
17288 +typedef struct cfi_string cfi_string_t;
17289 +
17290 +#endif
17291 --- /dev/null
17292 +++ b/drivers/usb/host/dwc_otg/dwc_otg_adp.c
17293 @@ -0,0 +1,854 @@
17294 +/* ==========================================================================
17295 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.c $
17296 + * $Revision: #12 $
17297 + * $Date: 2011/10/26 $
17298 + * $Change: 1873028 $
17299 + *
17300 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
17301 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
17302 + * otherwise expressly agreed to in writing between Synopsys and you.
17303 + *
17304 + * The Software IS NOT an item of Licensed Software or Licensed Product under
17305 + * any End User Software License Agreement or Agreement for Licensed Product
17306 + * with Synopsys or any supplement thereto. You are permitted to use and
17307 + * redistribute this Software in source and binary forms, with or without
17308 + * modification, provided that redistributions of source code must retain this
17309 + * notice. You may not view, use, disclose, copy or distribute this file or
17310 + * any information contained herein except pursuant to this license grant from
17311 + * Synopsys. If you do not agree with this notice, including the disclaimer
17312 + * below, then you are not authorized to use the Software.
17313 + *
17314 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
17315 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17316 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17317 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
17318 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
17319 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
17320 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
17321 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
17322 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
17323 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
17324 + * DAMAGE.
17325 + * ========================================================================== */
17326 +
17327 +#include "dwc_os.h"
17328 +#include "dwc_otg_regs.h"
17329 +#include "dwc_otg_cil.h"
17330 +#include "dwc_otg_adp.h"
17331 +
17332 +/** @file
17333 + *
17334 + * This file contains the most of the Attach Detect Protocol implementation for
17335 + * the driver to support OTG Rev2.0.
17336 + *
17337 + */
17338 +
17339 +void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value)
17340 +{
17341 + adpctl_data_t adpctl;
17342 +
17343 + adpctl.d32 = value;
17344 + adpctl.b.ar = 0x2;
17345 +
17346 + DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32);
17347 +
17348 + while (adpctl.b.ar) {
17349 + adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl);
17350 + }
17351 +
17352 +}
17353 +
17354 +/**
17355 + * Function is called to read ADP registers
17356 + */
17357 +uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if)
17358 +{
17359 + adpctl_data_t adpctl;
17360 +
17361 + adpctl.d32 = 0;
17362 + adpctl.b.ar = 0x1;
17363 +
17364 + DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32);
17365 +
17366 + while (adpctl.b.ar) {
17367 + adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl);
17368 + }
17369 +
17370 + return adpctl.d32;
17371 +}
17372 +
17373 +/**
17374 + * Function is called to read ADPCTL register and filter Write-clear bits
17375 + */
17376 +uint32_t dwc_otg_adp_read_reg_filter(dwc_otg_core_if_t * core_if)
17377 +{
17378 + adpctl_data_t adpctl;
17379 +
17380 + adpctl.d32 = dwc_otg_adp_read_reg(core_if);
17381 + adpctl.b.adp_tmout_int = 0;
17382 + adpctl.b.adp_prb_int = 0;
17383 + adpctl.b.adp_tmout_int = 0;
17384 +
17385 + return adpctl.d32;
17386 +}
17387 +
17388 +/**
17389 + * Function is called to write ADP registers
17390 + */
17391 +void dwc_otg_adp_modify_reg(dwc_otg_core_if_t * core_if, uint32_t clr,
17392 + uint32_t set)
17393 +{
17394 + dwc_otg_adp_write_reg(core_if,
17395 + (dwc_otg_adp_read_reg(core_if) & (~clr)) | set);
17396 +}
17397 +
17398 +static void adp_sense_timeout(void *ptr)
17399 +{
17400 + dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
17401 + core_if->adp.sense_timer_started = 0;
17402 + DWC_PRINTF("ADP SENSE TIMEOUT\n");
17403 + if (core_if->adp_enable) {
17404 + dwc_otg_adp_sense_stop(core_if);
17405 + dwc_otg_adp_probe_start(core_if);
17406 + }
17407 +}
17408 +
17409 +/**
17410 + * This function is called when the ADP vbus timer expires. Timeout is 1.1s.
17411 + */
17412 +static void adp_vbuson_timeout(void *ptr)
17413 +{
17414 + gpwrdn_data_t gpwrdn;
17415 + dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
17416 + hprt0_data_t hprt0 = {.d32 = 0 };
17417 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
17418 + DWC_PRINTF("%s: 1.1 seconds expire after turning on VBUS\n",__FUNCTION__);
17419 + if (core_if) {
17420 + core_if->adp.vbuson_timer_started = 0;
17421 + /* Turn off vbus */
17422 + hprt0.b.prtpwr = 1;
17423 + DWC_MODIFY_REG32(core_if->host_if->hprt0, hprt0.d32, 0);
17424 + gpwrdn.d32 = 0;
17425 +
17426 + /* Power off the core */
17427 + if (core_if->power_down == 2) {
17428 + /* Enable Wakeup Logic */
17429 +// gpwrdn.b.wkupactiv = 1;
17430 + gpwrdn.b.pmuactv = 0;
17431 + gpwrdn.b.pwrdnrstn = 1;
17432 + gpwrdn.b.pwrdnclmp = 1;
17433 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
17434 + gpwrdn.d32);
17435 +
17436 + /* Suspend the Phy Clock */
17437 + pcgcctl.b.stoppclk = 1;
17438 + DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
17439 +
17440 + /* Switch on VDD */
17441 +// gpwrdn.b.wkupactiv = 1;
17442 + gpwrdn.b.pmuactv = 1;
17443 + gpwrdn.b.pwrdnrstn = 1;
17444 + gpwrdn.b.pwrdnclmp = 1;
17445 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
17446 + gpwrdn.d32);
17447 + } else {
17448 + /* Enable Power Down Logic */
17449 + gpwrdn.b.pmuintsel = 1;
17450 + gpwrdn.b.pmuactv = 1;
17451 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
17452 + }
17453 +
17454 + /* Power off the core */
17455 + if (core_if->power_down == 2) {
17456 + gpwrdn.d32 = 0;
17457 + gpwrdn.b.pwrdnswtch = 1;
17458 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn,
17459 + gpwrdn.d32, 0);
17460 + }
17461 +
17462 + /* Unmask SRP detected interrupt from Power Down Logic */
17463 + gpwrdn.d32 = 0;
17464 + gpwrdn.b.srp_det_msk = 1;
17465 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
17466 +
17467 + dwc_otg_adp_probe_start(core_if);
17468 + dwc_otg_dump_global_registers(core_if);
17469 + dwc_otg_dump_host_registers(core_if);
17470 + }
17471 +
17472 +}
17473 +
17474 +/**
17475 + * Start the ADP Initial Probe timer to detect if Port Connected interrupt is
17476 + * not asserted within 1.1 seconds.
17477 + *
17478 + * @param core_if the pointer to core_if strucure.
17479 + */
17480 +void dwc_otg_adp_vbuson_timer_start(dwc_otg_core_if_t * core_if)
17481 +{
17482 + core_if->adp.vbuson_timer_started = 1;
17483 + if (core_if->adp.vbuson_timer)
17484 + {
17485 + DWC_PRINTF("SCHEDULING VBUSON TIMER\n");
17486 + /* 1.1 secs + 60ms necessary for cil_hcd_start*/
17487 + DWC_TIMER_SCHEDULE(core_if->adp.vbuson_timer, 1160);
17488 + } else {
17489 + DWC_WARN("VBUSON_TIMER = %p\n",core_if->adp.vbuson_timer);
17490 + }
17491 +}
17492 +
17493 +#if 0
17494 +/**
17495 + * Masks all DWC OTG core interrupts
17496 + *
17497 + */
17498 +static void mask_all_interrupts(dwc_otg_core_if_t * core_if)
17499 +{
17500 + int i;
17501 + gahbcfg_data_t ahbcfg = {.d32 = 0 };
17502 +
17503 + /* Mask Host Interrupts */
17504 +
17505 + /* Clear and disable HCINTs */
17506 + for (i = 0; i < core_if->core_params->host_channels; i++) {
17507 + DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk, 0);
17508 + DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcint, 0xFFFFFFFF);
17509 +
17510 + }
17511 +
17512 + /* Clear and disable HAINT */
17513 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk, 0x0000);
17514 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haint, 0xFFFFFFFF);
17515 +
17516 + /* Mask Device Interrupts */
17517 + if (!core_if->multiproc_int_enable) {
17518 + /* Clear and disable IN Endpoint interrupts */
17519 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, 0);
17520 + for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
17521 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->
17522 + diepint, 0xFFFFFFFF);
17523 + }
17524 +
17525 + /* Clear and disable OUT Endpoint interrupts */
17526 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, 0);
17527 + for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
17528 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
17529 + doepint, 0xFFFFFFFF);
17530 + }
17531 +
17532 + /* Clear and disable DAINT */
17533 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daint,
17534 + 0xFFFFFFFF);
17535 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, 0);
17536 + } else {
17537 + for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
17538 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
17539 + diepeachintmsk[i], 0);
17540 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->
17541 + diepint, 0xFFFFFFFF);
17542 + }
17543 +
17544 + for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
17545 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
17546 + doepeachintmsk[i], 0);
17547 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
17548 + doepint, 0xFFFFFFFF);
17549 + }
17550 +
17551 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,
17552 + 0);
17553 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachint,
17554 + 0xFFFFFFFF);
17555 +
17556 + }
17557 +
17558 + /* Disable interrupts */
17559 + ahbcfg.b.glblintrmsk = 1;
17560 + DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
17561 +
17562 + /* Disable all interrupts. */
17563 + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);
17564 +
17565 + /* Clear any pending interrupts */
17566 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
17567 +
17568 + /* Clear any pending OTG Interrupts */
17569 + DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, 0xFFFFFFFF);
17570 +}
17571 +
17572 +/**
17573 + * Unmask Port Connection Detected interrupt
17574 + *
17575 + */
17576 +static void unmask_conn_det_intr(dwc_otg_core_if_t * core_if)
17577 +{
17578 + gintmsk_data_t gintmsk = {.d32 = 0,.b.portintr = 1 };
17579 +
17580 + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
17581 +}
17582 +#endif
17583 +
17584 +/**
17585 + * Starts the ADP Probing
17586 + *
17587 + * @param core_if the pointer to core_if structure.
17588 + */
17589 +uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if)
17590 +{
17591 +
17592 + adpctl_data_t adpctl = {.d32 = 0};
17593 + gpwrdn_data_t gpwrdn;
17594 +#if 0
17595 + adpctl_data_t adpctl_int = {.d32 = 0, .b.adp_prb_int = 1,
17596 + .b.adp_sns_int = 1, b.adp_tmout_int};
17597 +#endif
17598 + dwc_otg_disable_global_interrupts(core_if);
17599 + DWC_PRINTF("ADP Probe Start\n");
17600 + core_if->adp.probe_enabled = 1;
17601 +
17602 + adpctl.b.adpres = 1;
17603 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
17604 +
17605 + while (adpctl.b.adpres) {
17606 + adpctl.d32 = dwc_otg_adp_read_reg(core_if);
17607 + }
17608 +
17609 + adpctl.d32 = 0;
17610 + gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
17611 +
17612 + /* In Host mode unmask SRP detected interrupt */
17613 + gpwrdn.d32 = 0;
17614 + gpwrdn.b.sts_chngint_msk = 1;
17615 + if (!gpwrdn.b.idsts) {
17616 + gpwrdn.b.srp_det_msk = 1;
17617 + }
17618 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
17619 +
17620 + adpctl.b.adp_tmout_int_msk = 1;
17621 + adpctl.b.adp_prb_int_msk = 1;
17622 + adpctl.b.prb_dschg = 1;
17623 + adpctl.b.prb_delta = 1;
17624 + adpctl.b.prb_per = 1;
17625 + adpctl.b.adpen = 1;
17626 + adpctl.b.enaprb = 1;
17627 +
17628 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
17629 + DWC_PRINTF("ADP Probe Finish\n");
17630 + return 0;
17631 +}
17632 +
17633 +/**
17634 + * Starts the ADP Sense timer to detect if ADP Sense interrupt is not asserted
17635 + * within 3 seconds.
17636 + *
17637 + * @param core_if the pointer to core_if strucure.
17638 + */
17639 +void dwc_otg_adp_sense_timer_start(dwc_otg_core_if_t * core_if)
17640 +{
17641 + core_if->adp.sense_timer_started = 1;
17642 + DWC_TIMER_SCHEDULE(core_if->adp.sense_timer, 3000 /* 3 secs */ );
17643 +}
17644 +
17645 +/**
17646 + * Starts the ADP Sense
17647 + *
17648 + * @param core_if the pointer to core_if strucure.
17649 + */
17650 +uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if)
17651 +{
17652 + adpctl_data_t adpctl;
17653 +
17654 + DWC_PRINTF("ADP Sense Start\n");
17655 +
17656 + /* Unmask ADP sense interrupt and mask all other from the core */
17657 + adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
17658 + adpctl.b.adp_sns_int_msk = 1;
17659 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
17660 + dwc_otg_disable_global_interrupts(core_if); // vahrama
17661 +
17662 + /* Set ADP reset bit*/
17663 + adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
17664 + adpctl.b.adpres = 1;
17665 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
17666 +
17667 + while (adpctl.b.adpres) {
17668 + adpctl.d32 = dwc_otg_adp_read_reg(core_if);
17669 + }
17670 +
17671 + adpctl.b.adpres = 0;
17672 + adpctl.b.adpen = 1;
17673 + adpctl.b.enasns = 1;
17674 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
17675 +
17676 + dwc_otg_adp_sense_timer_start(core_if);
17677 +
17678 + return 0;
17679 +}
17680 +
17681 +/**
17682 + * Stops the ADP Probing
17683 + *
17684 + * @param core_if the pointer to core_if strucure.
17685 + */
17686 +uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if)
17687 +{
17688 +
17689 + adpctl_data_t adpctl;
17690 + DWC_PRINTF("Stop ADP probe\n");
17691 + core_if->adp.probe_enabled = 0;
17692 + core_if->adp.probe_counter = 0;
17693 + adpctl.d32 = dwc_otg_adp_read_reg(core_if);
17694 +
17695 + adpctl.b.adpen = 0;
17696 + adpctl.b.adp_prb_int = 1;
17697 + adpctl.b.adp_tmout_int = 1;
17698 + adpctl.b.adp_sns_int = 1;
17699 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
17700 +
17701 + return 0;
17702 +}
17703 +
17704 +/**
17705 + * Stops the ADP Sensing
17706 + *
17707 + * @param core_if the pointer to core_if strucure.
17708 + */
17709 +uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if)
17710 +{
17711 + adpctl_data_t adpctl;
17712 +
17713 + core_if->adp.sense_enabled = 0;
17714 +
17715 + adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
17716 + adpctl.b.enasns = 0;
17717 + adpctl.b.adp_sns_int = 1;
17718 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
17719 +
17720 + return 0;
17721 +}
17722 +
17723 +/**
17724 + * Called to turn on the VBUS after initial ADP probe in host mode.
17725 + * If port power was already enabled in cil_hcd_start function then
17726 + * only schedule a timer.
17727 + *
17728 + * @param core_if the pointer to core_if structure.
17729 + */
17730 +void dwc_otg_adp_turnon_vbus(dwc_otg_core_if_t * core_if)
17731 +{
17732 + hprt0_data_t hprt0 = {.d32 = 0 };
17733 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
17734 + DWC_PRINTF("Turn on VBUS for 1.1s, port power is %d\n", hprt0.b.prtpwr);
17735 +
17736 + if (hprt0.b.prtpwr == 0) {
17737 + hprt0.b.prtpwr = 1;
17738 + //DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
17739 + }
17740 +
17741 + dwc_otg_adp_vbuson_timer_start(core_if);
17742 +}
17743 +
17744 +/**
17745 + * Called right after driver is loaded
17746 + * to perform initial actions for ADP
17747 + *
17748 + * @param core_if the pointer to core_if structure.
17749 + * @param is_host - flag for current mode of operation either from GINTSTS or GPWRDN
17750 + */
17751 +void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host)
17752 +{
17753 + gpwrdn_data_t gpwrdn;
17754 +
17755 + DWC_PRINTF("ADP Initial Start\n");
17756 + core_if->adp.adp_started = 1;
17757 +
17758 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
17759 + dwc_otg_disable_global_interrupts(core_if);
17760 + if (is_host) {
17761 + DWC_PRINTF("HOST MODE\n");
17762 + /* Enable Power Down Logic Interrupt*/
17763 + gpwrdn.d32 = 0;
17764 + gpwrdn.b.pmuintsel = 1;
17765 + gpwrdn.b.pmuactv = 1;
17766 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
17767 + /* Initialize first ADP probe to obtain Ramp Time value */
17768 + core_if->adp.initial_probe = 1;
17769 + dwc_otg_adp_probe_start(core_if);
17770 + } else {
17771 + gotgctl_data_t gotgctl;
17772 + gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
17773 + DWC_PRINTF("DEVICE MODE\n");
17774 + if (gotgctl.b.bsesvld == 0) {
17775 + /* Enable Power Down Logic Interrupt*/
17776 + gpwrdn.d32 = 0;
17777 + DWC_PRINTF("VBUS is not valid - start ADP probe\n");
17778 + gpwrdn.b.pmuintsel = 1;
17779 + gpwrdn.b.pmuactv = 1;
17780 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
17781 + core_if->adp.initial_probe = 1;
17782 + dwc_otg_adp_probe_start(core_if);
17783 + } else {
17784 + DWC_PRINTF("VBUS is valid - initialize core as a Device\n");
17785 + core_if->op_state = B_PERIPHERAL;
17786 + dwc_otg_core_init(core_if);
17787 + dwc_otg_enable_global_interrupts(core_if);
17788 + cil_pcd_start(core_if);
17789 + dwc_otg_dump_global_registers(core_if);
17790 + dwc_otg_dump_dev_registers(core_if);
17791 + }
17792 + }
17793 +}
17794 +
17795 +void dwc_otg_adp_init(dwc_otg_core_if_t * core_if)
17796 +{
17797 + core_if->adp.adp_started = 0;
17798 + core_if->adp.initial_probe = 0;
17799 + core_if->adp.probe_timer_values[0] = -1;
17800 + core_if->adp.probe_timer_values[1] = -1;
17801 + core_if->adp.probe_enabled = 0;
17802 + core_if->adp.sense_enabled = 0;
17803 + core_if->adp.sense_timer_started = 0;
17804 + core_if->adp.vbuson_timer_started = 0;
17805 + core_if->adp.probe_counter = 0;
17806 + core_if->adp.gpwrdn = 0;
17807 + core_if->adp.attached = DWC_OTG_ADP_UNKOWN;
17808 + /* Initialize timers */
17809 + core_if->adp.sense_timer =
17810 + DWC_TIMER_ALLOC("ADP SENSE TIMER", adp_sense_timeout, core_if);
17811 + core_if->adp.vbuson_timer =
17812 + DWC_TIMER_ALLOC("ADP VBUS ON TIMER", adp_vbuson_timeout, core_if);
17813 + if (!core_if->adp.sense_timer || !core_if->adp.vbuson_timer)
17814 + {
17815 + DWC_ERROR("Could not allocate memory for ADP timers\n");
17816 + }
17817 +}
17818 +
17819 +void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if)
17820 +{
17821 + gpwrdn_data_t gpwrdn = { .d32 = 0 };
17822 + gpwrdn.b.pmuintsel = 1;
17823 + gpwrdn.b.pmuactv = 1;
17824 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
17825 +
17826 + if (core_if->adp.probe_enabled)
17827 + dwc_otg_adp_probe_stop(core_if);
17828 + if (core_if->adp.sense_enabled)
17829 + dwc_otg_adp_sense_stop(core_if);
17830 + if (core_if->adp.sense_timer_started)
17831 + DWC_TIMER_CANCEL(core_if->adp.sense_timer);
17832 + if (core_if->adp.vbuson_timer_started)
17833 + DWC_TIMER_CANCEL(core_if->adp.vbuson_timer);
17834 + DWC_TIMER_FREE(core_if->adp.sense_timer);
17835 + DWC_TIMER_FREE(core_if->adp.vbuson_timer);
17836 +}
17837 +
17838 +/////////////////////////////////////////////////////////////////////
17839 +////////////// ADP Interrupt Handlers ///////////////////////////////
17840 +/////////////////////////////////////////////////////////////////////
17841 +/**
17842 + * This function sets Ramp Timer values
17843 + */
17844 +static uint32_t set_timer_value(dwc_otg_core_if_t * core_if, uint32_t val)
17845 +{
17846 + if (core_if->adp.probe_timer_values[0] == -1) {
17847 + core_if->adp.probe_timer_values[0] = val;
17848 + core_if->adp.probe_timer_values[1] = -1;
17849 + return 1;
17850 + } else {
17851 + core_if->adp.probe_timer_values[1] =
17852 + core_if->adp.probe_timer_values[0];
17853 + core_if->adp.probe_timer_values[0] = val;
17854 + return 0;
17855 + }
17856 +}
17857 +
17858 +/**
17859 + * This function compares Ramp Timer values
17860 + */
17861 +static uint32_t compare_timer_values(dwc_otg_core_if_t * core_if)
17862 +{
17863 + uint32_t diff;
17864 + if (core_if->adp.probe_timer_values[0]>=core_if->adp.probe_timer_values[1])
17865 + diff = core_if->adp.probe_timer_values[0]-core_if->adp.probe_timer_values[1];
17866 + else
17867 + diff = core_if->adp.probe_timer_values[1]-core_if->adp.probe_timer_values[0];
17868 + if(diff < 2) {
17869 + return 0;
17870 + } else {
17871 + return 1;
17872 + }
17873 +}
17874 +
17875 +/**
17876 + * This function handles ADP Probe Interrupts
17877 + */
17878 +static int32_t dwc_otg_adp_handle_prb_intr(dwc_otg_core_if_t * core_if,
17879 + uint32_t val)
17880 +{
17881 + adpctl_data_t adpctl = {.d32 = 0 };
17882 + gpwrdn_data_t gpwrdn, temp;
17883 + adpctl.d32 = val;
17884 +
17885 + temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
17886 + core_if->adp.probe_counter++;
17887 + core_if->adp.gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
17888 + if (adpctl.b.rtim == 0 && !temp.b.idsts){
17889 + DWC_PRINTF("RTIM value is 0\n");
17890 + goto exit;
17891 + }
17892 + if (set_timer_value(core_if, adpctl.b.rtim) &&
17893 + core_if->adp.initial_probe) {
17894 + core_if->adp.initial_probe = 0;
17895 + dwc_otg_adp_probe_stop(core_if);
17896 + gpwrdn.d32 = 0;
17897 + gpwrdn.b.pmuactv = 1;
17898 + gpwrdn.b.pmuintsel = 1;
17899 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
17900 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
17901 +
17902 + /* check which value is for device mode and which for Host mode */
17903 + if (!temp.b.idsts) { /* considered host mode value is 0 */
17904 + /*
17905 + * Turn on VBUS after initial ADP probe.
17906 + */
17907 + core_if->op_state = A_HOST;
17908 + dwc_otg_enable_global_interrupts(core_if);
17909 + DWC_SPINUNLOCK(core_if->lock);
17910 + cil_hcd_start(core_if);
17911 + dwc_otg_adp_turnon_vbus(core_if);
17912 + DWC_SPINLOCK(core_if->lock);
17913 + } else {
17914 + /*
17915 + * Initiate SRP after initial ADP probe.
17916 + */
17917 + dwc_otg_enable_global_interrupts(core_if);
17918 + dwc_otg_initiate_srp(core_if);
17919 + }
17920 + } else if (core_if->adp.probe_counter > 2){
17921 + gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
17922 + if (compare_timer_values(core_if)) {
17923 + DWC_PRINTF("Difference in timer values !!! \n");
17924 +// core_if->adp.attached = DWC_OTG_ADP_ATTACHED;
17925 + dwc_otg_adp_probe_stop(core_if);
17926 +
17927 + /* Power on the core */
17928 + if (core_if->power_down == 2) {
17929 + gpwrdn.b.pwrdnswtch = 1;
17930 + DWC_MODIFY_REG32(&core_if->core_global_regs->
17931 + gpwrdn, 0, gpwrdn.d32);
17932 + }
17933 +
17934 + /* check which value is for device mode and which for Host mode */
17935 + if (!temp.b.idsts) { /* considered host mode value is 0 */
17936 + /* Disable Interrupt from Power Down Logic */
17937 + gpwrdn.d32 = 0;
17938 + gpwrdn.b.pmuintsel = 1;
17939 + gpwrdn.b.pmuactv = 1;
17940 + DWC_MODIFY_REG32(&core_if->core_global_regs->
17941 + gpwrdn, gpwrdn.d32, 0);
17942 +
17943 + /*
17944 + * Initialize the Core for Host mode.
17945 + */
17946 + core_if->op_state = A_HOST;
17947 + dwc_otg_core_init(core_if);
17948 + dwc_otg_enable_global_interrupts(core_if);
17949 + cil_hcd_start(core_if);
17950 + } else {
17951 + gotgctl_data_t gotgctl;
17952 + /* Mask SRP detected interrupt from Power Down Logic */
17953 + gpwrdn.d32 = 0;
17954 + gpwrdn.b.srp_det_msk = 1;
17955 + DWC_MODIFY_REG32(&core_if->core_global_regs->
17956 + gpwrdn, gpwrdn.d32, 0);
17957 +
17958 + /* Disable Power Down Logic */
17959 + gpwrdn.d32 = 0;
17960 + gpwrdn.b.pmuintsel = 1;
17961 + gpwrdn.b.pmuactv = 1;
17962 + DWC_MODIFY_REG32(&core_if->core_global_regs->
17963 + gpwrdn, gpwrdn.d32, 0);
17964 +
17965 + /*
17966 + * Initialize the Core for Device mode.
17967 + */
17968 + core_if->op_state = B_PERIPHERAL;
17969 + dwc_otg_core_init(core_if);
17970 + dwc_otg_enable_global_interrupts(core_if);
17971 + cil_pcd_start(core_if);
17972 +
17973 + gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
17974 + if (!gotgctl.b.bsesvld) {
17975 + dwc_otg_initiate_srp(core_if);
17976 + }
17977 + }
17978 + }
17979 + if (core_if->power_down == 2) {
17980 + if (gpwrdn.b.bsessvld) {
17981 + /* Mask SRP detected interrupt from Power Down Logic */
17982 + gpwrdn.d32 = 0;
17983 + gpwrdn.b.srp_det_msk = 1;
17984 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
17985 +
17986 + /* Disable Power Down Logic */
17987 + gpwrdn.d32 = 0;
17988 + gpwrdn.b.pmuactv = 1;
17989 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
17990 +
17991 + /*
17992 + * Initialize the Core for Device mode.
17993 + */
17994 + core_if->op_state = B_PERIPHERAL;
17995 + dwc_otg_core_init(core_if);
17996 + dwc_otg_enable_global_interrupts(core_if);
17997 + cil_pcd_start(core_if);
17998 + }
17999 + }
18000 + }
18001 +exit:
18002 + /* Clear interrupt */
18003 + adpctl.d32 = dwc_otg_adp_read_reg(core_if);
18004 + adpctl.b.adp_prb_int = 1;
18005 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
18006 +
18007 + return 0;
18008 +}
18009 +
18010 +/**
18011 + * This function hadles ADP Sense Interrupt
18012 + */
18013 +static int32_t dwc_otg_adp_handle_sns_intr(dwc_otg_core_if_t * core_if)
18014 +{
18015 + adpctl_data_t adpctl;
18016 + /* Stop ADP Sense timer */
18017 + DWC_TIMER_CANCEL(core_if->adp.sense_timer);
18018 +
18019 + /* Restart ADP Sense timer */
18020 + dwc_otg_adp_sense_timer_start(core_if);
18021 +
18022 + /* Clear interrupt */
18023 + adpctl.d32 = dwc_otg_adp_read_reg(core_if);
18024 + adpctl.b.adp_sns_int = 1;
18025 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
18026 +
18027 + return 0;
18028 +}
18029 +
18030 +/**
18031 + * This function handles ADP Probe Interrupts
18032 + */
18033 +static int32_t dwc_otg_adp_handle_prb_tmout_intr(dwc_otg_core_if_t * core_if,
18034 + uint32_t val)
18035 +{
18036 + adpctl_data_t adpctl = {.d32 = 0 };
18037 + adpctl.d32 = val;
18038 + set_timer_value(core_if, adpctl.b.rtim);
18039 +
18040 + /* Clear interrupt */
18041 + adpctl.d32 = dwc_otg_adp_read_reg(core_if);
18042 + adpctl.b.adp_tmout_int = 1;
18043 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
18044 +
18045 + return 0;
18046 +}
18047 +
18048 +/**
18049 + * ADP Interrupt handler.
18050 + *
18051 + */
18052 +int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if)
18053 +{
18054 + int retval = 0;
18055 + adpctl_data_t adpctl = {.d32 = 0};
18056 +
18057 + adpctl.d32 = dwc_otg_adp_read_reg(core_if);
18058 + DWC_PRINTF("ADPCTL = %08x\n",adpctl.d32);
18059 +
18060 + if (adpctl.b.adp_sns_int & adpctl.b.adp_sns_int_msk) {
18061 + DWC_PRINTF("ADP Sense interrupt\n");
18062 + retval |= dwc_otg_adp_handle_sns_intr(core_if);
18063 + }
18064 + if (adpctl.b.adp_tmout_int & adpctl.b.adp_tmout_int_msk) {
18065 + DWC_PRINTF("ADP timeout interrupt\n");
18066 + retval |= dwc_otg_adp_handle_prb_tmout_intr(core_if, adpctl.d32);
18067 + }
18068 + if (adpctl.b.adp_prb_int & adpctl.b.adp_prb_int_msk) {
18069 + DWC_PRINTF("ADP Probe interrupt\n");
18070 + adpctl.b.adp_prb_int = 1;
18071 + retval |= dwc_otg_adp_handle_prb_intr(core_if, adpctl.d32);
18072 + }
18073 +
18074 +// dwc_otg_adp_modify_reg(core_if, adpctl.d32, 0);
18075 + //dwc_otg_adp_write_reg(core_if, adpctl.d32);
18076 + DWC_PRINTF("RETURN FROM ADP ISR\n");
18077 +
18078 + return retval;
18079 +}
18080 +
18081 +/**
18082 + *
18083 + * @param core_if Programming view of DWC_otg controller.
18084 + */
18085 +int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if)
18086 +{
18087 +
18088 +#ifndef DWC_HOST_ONLY
18089 + hprt0_data_t hprt0;
18090 + gpwrdn_data_t gpwrdn;
18091 + DWC_DEBUGPL(DBG_ANY, "++ Power Down Logic Session Request Interrupt++\n");
18092 +
18093 + gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
18094 + /* check which value is for device mode and which for Host mode */
18095 + if (!gpwrdn.b.idsts) { /* considered host mode value is 0 */
18096 + DWC_PRINTF("SRP: Host mode\n");
18097 +
18098 + if (core_if->adp_enable) {
18099 + dwc_otg_adp_probe_stop(core_if);
18100 +
18101 + /* Power on the core */
18102 + if (core_if->power_down == 2) {
18103 + gpwrdn.b.pwrdnswtch = 1;
18104 + DWC_MODIFY_REG32(&core_if->core_global_regs->
18105 + gpwrdn, 0, gpwrdn.d32);
18106 + }
18107 +
18108 + core_if->op_state = A_HOST;
18109 + dwc_otg_core_init(core_if);
18110 + dwc_otg_enable_global_interrupts(core_if);
18111 + cil_hcd_start(core_if);
18112 + }
18113 +
18114 + /* Turn on the port power bit. */
18115 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
18116 + hprt0.b.prtpwr = 1;
18117 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
18118 +
18119 + /* Start the Connection timer. So a message can be displayed
18120 + * if connect does not occur within 10 seconds. */
18121 + cil_hcd_session_start(core_if);
18122 + } else {
18123 + DWC_PRINTF("SRP: Device mode %s\n", __FUNCTION__);
18124 + if (core_if->adp_enable) {
18125 + dwc_otg_adp_probe_stop(core_if);
18126 +
18127 + /* Power on the core */
18128 + if (core_if->power_down == 2) {
18129 + gpwrdn.b.pwrdnswtch = 1;
18130 + DWC_MODIFY_REG32(&core_if->core_global_regs->
18131 + gpwrdn, 0, gpwrdn.d32);
18132 + }
18133 +
18134 + gpwrdn.d32 = 0;
18135 + gpwrdn.b.pmuactv = 0;
18136 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
18137 + gpwrdn.d32);
18138 +
18139 + core_if->op_state = B_PERIPHERAL;
18140 + dwc_otg_core_init(core_if);
18141 + dwc_otg_enable_global_interrupts(core_if);
18142 + cil_pcd_start(core_if);
18143 + }
18144 + }
18145 +#endif
18146 + return 1;
18147 +}
18148 --- /dev/null
18149 +++ b/drivers/usb/host/dwc_otg/dwc_otg_adp.h
18150 @@ -0,0 +1,80 @@
18151 +/* ==========================================================================
18152 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.h $
18153 + * $Revision: #7 $
18154 + * $Date: 2011/10/24 $
18155 + * $Change: 1871159 $
18156 + *
18157 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
18158 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
18159 + * otherwise expressly agreed to in writing between Synopsys and you.
18160 + *
18161 + * The Software IS NOT an item of Licensed Software or Licensed Product under
18162 + * any End User Software License Agreement or Agreement for Licensed Product
18163 + * with Synopsys or any supplement thereto. You are permitted to use and
18164 + * redistribute this Software in source and binary forms, with or without
18165 + * modification, provided that redistributions of source code must retain this
18166 + * notice. You may not view, use, disclose, copy or distribute this file or
18167 + * any information contained herein except pursuant to this license grant from
18168 + * Synopsys. If you do not agree with this notice, including the disclaimer
18169 + * below, then you are not authorized to use the Software.
18170 + *
18171 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
18172 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18173 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18174 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
18175 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18176 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
18177 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
18178 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
18179 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
18180 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
18181 + * DAMAGE.
18182 + * ========================================================================== */
18183 +
18184 +#ifndef __DWC_OTG_ADP_H__
18185 +#define __DWC_OTG_ADP_H__
18186 +
18187 +/**
18188 + * @file
18189 + *
18190 + * This file contains the Attach Detect Protocol interfaces and defines
18191 + * (functions) and structures for Linux.
18192 + *
18193 + */
18194 +
18195 +#define DWC_OTG_ADP_UNATTACHED 0
18196 +#define DWC_OTG_ADP_ATTACHED 1
18197 +#define DWC_OTG_ADP_UNKOWN 2
18198 +
18199 +typedef struct dwc_otg_adp {
18200 + uint32_t adp_started;
18201 + uint32_t initial_probe;
18202 + int32_t probe_timer_values[2];
18203 + uint32_t probe_enabled;
18204 + uint32_t sense_enabled;
18205 + dwc_timer_t *sense_timer;
18206 + uint32_t sense_timer_started;
18207 + dwc_timer_t *vbuson_timer;
18208 + uint32_t vbuson_timer_started;
18209 + uint32_t attached;
18210 + uint32_t probe_counter;
18211 + uint32_t gpwrdn;
18212 +} dwc_otg_adp_t;
18213 +
18214 +/**
18215 + * Attach Detect Protocol functions
18216 + */
18217 +
18218 +extern void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value);
18219 +extern uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if);
18220 +extern uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if);
18221 +extern uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if);
18222 +extern uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if);
18223 +extern uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if);
18224 +extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
18225 +extern void dwc_otg_adp_init(dwc_otg_core_if_t * core_if);
18226 +extern void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if);
18227 +extern int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if);
18228 +extern int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if);
18229 +
18230 +#endif //__DWC_OTG_ADP_H__
18231 --- /dev/null
18232 +++ b/drivers/usb/host/dwc_otg/dwc_otg_attr.c
18233 @@ -0,0 +1,1210 @@
18234 +/* ==========================================================================
18235 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $
18236 + * $Revision: #44 $
18237 + * $Date: 2010/11/29 $
18238 + * $Change: 1636033 $
18239 + *
18240 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
18241 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
18242 + * otherwise expressly agreed to in writing between Synopsys and you.
18243 + *
18244 + * The Software IS NOT an item of Licensed Software or Licensed Product under
18245 + * any End User Software License Agreement or Agreement for Licensed Product
18246 + * with Synopsys or any supplement thereto. You are permitted to use and
18247 + * redistribute this Software in source and binary forms, with or without
18248 + * modification, provided that redistributions of source code must retain this
18249 + * notice. You may not view, use, disclose, copy or distribute this file or
18250 + * any information contained herein except pursuant to this license grant from
18251 + * Synopsys. If you do not agree with this notice, including the disclaimer
18252 + * below, then you are not authorized to use the Software.
18253 + *
18254 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
18255 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18256 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18257 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
18258 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18259 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
18260 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
18261 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
18262 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
18263 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
18264 + * DAMAGE.
18265 + * ========================================================================== */
18266 +
18267 +/** @file
18268 + *
18269 + * The diagnostic interface will provide access to the controller for
18270 + * bringing up the hardware and testing. The Linux driver attributes
18271 + * feature will be used to provide the Linux Diagnostic
18272 + * Interface. These attributes are accessed through sysfs.
18273 + */
18274 +
18275 +/** @page "Linux Module Attributes"
18276 + *
18277 + * The Linux module attributes feature is used to provide the Linux
18278 + * Diagnostic Interface. These attributes are accessed through sysfs.
18279 + * The diagnostic interface will provide access to the controller for
18280 + * bringing up the hardware and testing.
18281 +
18282 + The following table shows the attributes.
18283 + <table>
18284 + <tr>
18285 + <td><b> Name</b></td>
18286 + <td><b> Description</b></td>
18287 + <td><b> Access</b></td>
18288 + </tr>
18289 +
18290 + <tr>
18291 + <td> mode </td>
18292 + <td> Returns the current mode: 0 for device mode, 1 for host mode</td>
18293 + <td> Read</td>
18294 + </tr>
18295 +
18296 + <tr>
18297 + <td> hnpcapable </td>
18298 + <td> Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register.
18299 + Read returns the current value.</td>
18300 + <td> Read/Write</td>
18301 + </tr>
18302 +
18303 + <tr>
18304 + <td> srpcapable </td>
18305 + <td> Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register.
18306 + Read returns the current value.</td>
18307 + <td> Read/Write</td>
18308 + </tr>
18309 +
18310 + <tr>
18311 + <td> hsic_connect </td>
18312 + <td> Gets or sets the "HSIC-Connect" bit in the GLPMCFG Register.
18313 + Read returns the current value.</td>
18314 + <td> Read/Write</td>
18315 + </tr>
18316 +
18317 + <tr>
18318 + <td> inv_sel_hsic </td>
18319 + <td> Gets or sets the "Invert Select HSIC" bit in the GLPMFG Register.
18320 + Read returns the current value.</td>
18321 + <td> Read/Write</td>
18322 + </tr>
18323 +
18324 + <tr>
18325 + <td> hnp </td>
18326 + <td> Initiates the Host Negotiation Protocol. Read returns the status.</td>
18327 + <td> Read/Write</td>
18328 + </tr>
18329 +
18330 + <tr>
18331 + <td> srp </td>
18332 + <td> Initiates the Session Request Protocol. Read returns the status.</td>
18333 + <td> Read/Write</td>
18334 + </tr>
18335 +
18336 + <tr>
18337 + <td> buspower </td>
18338 + <td> Gets or sets the Power State of the bus (0 - Off or 1 - On)</td>
18339 + <td> Read/Write</td>
18340 + </tr>
18341 +
18342 + <tr>
18343 + <td> bussuspend </td>
18344 + <td> Suspends the USB bus.</td>
18345 + <td> Read/Write</td>
18346 + </tr>
18347 +
18348 + <tr>
18349 + <td> busconnected </td>
18350 + <td> Gets the connection status of the bus</td>
18351 + <td> Read</td>
18352 + </tr>
18353 +
18354 + <tr>
18355 + <td> gotgctl </td>
18356 + <td> Gets or sets the Core Control Status Register.</td>
18357 + <td> Read/Write</td>
18358 + </tr>
18359 +
18360 + <tr>
18361 + <td> gusbcfg </td>
18362 + <td> Gets or sets the Core USB Configuration Register</td>
18363 + <td> Read/Write</td>
18364 + </tr>
18365 +
18366 + <tr>
18367 + <td> grxfsiz </td>
18368 + <td> Gets or sets the Receive FIFO Size Register</td>
18369 + <td> Read/Write</td>
18370 + </tr>
18371 +
18372 + <tr>
18373 + <td> gnptxfsiz </td>
18374 + <td> Gets or sets the non-periodic Transmit Size Register</td>
18375 + <td> Read/Write</td>
18376 + </tr>
18377 +
18378 + <tr>
18379 + <td> gpvndctl </td>
18380 + <td> Gets or sets the PHY Vendor Control Register</td>
18381 + <td> Read/Write</td>
18382 + </tr>
18383 +
18384 + <tr>
18385 + <td> ggpio </td>
18386 + <td> Gets the value in the lower 16-bits of the General Purpose IO Register
18387 + or sets the upper 16 bits.</td>
18388 + <td> Read/Write</td>
18389 + </tr>
18390 +
18391 + <tr>
18392 + <td> guid </td>
18393 + <td> Gets or sets the value of the User ID Register</td>
18394 + <td> Read/Write</td>
18395 + </tr>
18396 +
18397 + <tr>
18398 + <td> gsnpsid </td>
18399 + <td> Gets the value of the Synopsys ID Regester</td>
18400 + <td> Read</td>
18401 + </tr>
18402 +
18403 + <tr>
18404 + <td> devspeed </td>
18405 + <td> Gets or sets the device speed setting in the DCFG register</td>
18406 + <td> Read/Write</td>
18407 + </tr>
18408 +
18409 + <tr>
18410 + <td> enumspeed </td>
18411 + <td> Gets the device enumeration Speed.</td>
18412 + <td> Read</td>
18413 + </tr>
18414 +
18415 + <tr>
18416 + <td> hptxfsiz </td>
18417 + <td> Gets the value of the Host Periodic Transmit FIFO</td>
18418 + <td> Read</td>
18419 + </tr>
18420 +
18421 + <tr>
18422 + <td> hprt0 </td>
18423 + <td> Gets or sets the value in the Host Port Control and Status Register</td>
18424 + <td> Read/Write</td>
18425 + </tr>
18426 +
18427 + <tr>
18428 + <td> regoffset </td>
18429 + <td> Sets the register offset for the next Register Access</td>
18430 + <td> Read/Write</td>
18431 + </tr>
18432 +
18433 + <tr>
18434 + <td> regvalue </td>
18435 + <td> Gets or sets the value of the register at the offset in the regoffset attribute.</td>
18436 + <td> Read/Write</td>
18437 + </tr>
18438 +
18439 + <tr>
18440 + <td> remote_wakeup </td>
18441 + <td> On read, shows the status of Remote Wakeup. On write, initiates a remote
18442 + wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote
18443 + Wakeup signalling bit in the Device Control Register is set for 1
18444 + milli-second.</td>
18445 + <td> Read/Write</td>
18446 + </tr>
18447 +
18448 + <tr>
18449 + <td> rem_wakeup_pwrdn </td>
18450 + <td> On read, shows the status core - hibernated or not. On write, initiates
18451 + a remote wakeup of the device from Hibernation. </td>
18452 + <td> Read/Write</td>
18453 + </tr>
18454 +
18455 + <tr>
18456 + <td> mode_ch_tim_en </td>
18457 + <td> This bit is used to enable or disable the host core to wait for 200 PHY
18458 + clock cycles at the end of Resume to change the opmode signal to the PHY to 00
18459 + after Suspend or LPM. </td>
18460 + <td> Read/Write</td>
18461 + </tr>
18462 +
18463 + <tr>
18464 + <td> fr_interval </td>
18465 + <td> On read, shows the value of HFIR Frame Interval. On write, dynamically
18466 + reload HFIR register during runtime. The application can write a value to this
18467 + register only after the Port Enable bit of the Host Port Control and Status
18468 + register (HPRT.PrtEnaPort) has been set </td>
18469 + <td> Read/Write</td>
18470 + </tr>
18471 +
18472 + <tr>
18473 + <td> disconnect_us </td>
18474 + <td> On read, shows the status of disconnect_device_us. On write, sets disconnect_us
18475 + which causes soft disconnect for 100us. Applicable only for device mode of operation.</td>
18476 + <td> Read/Write</td>
18477 + </tr>
18478 +
18479 + <tr>
18480 + <td> regdump </td>
18481 + <td> Dumps the contents of core registers.</td>
18482 + <td> Read</td>
18483 + </tr>
18484 +
18485 + <tr>
18486 + <td> spramdump </td>
18487 + <td> Dumps the contents of core registers.</td>
18488 + <td> Read</td>
18489 + </tr>
18490 +
18491 + <tr>
18492 + <td> hcddump </td>
18493 + <td> Dumps the current HCD state.</td>
18494 + <td> Read</td>
18495 + </tr>
18496 +
18497 + <tr>
18498 + <td> hcd_frrem </td>
18499 + <td> Shows the average value of the Frame Remaining
18500 + field in the Host Frame Number/Frame Remaining register when an SOF interrupt
18501 + occurs. This can be used to determine the average interrupt latency. Also
18502 + shows the average Frame Remaining value for start_transfer and the "a" and
18503 + "b" sample points. The "a" and "b" sample points may be used during debugging
18504 + bto determine how long it takes to execute a section of the HCD code.</td>
18505 + <td> Read</td>
18506 + </tr>
18507 +
18508 + <tr>
18509 + <td> rd_reg_test </td>
18510 + <td> Displays the time required to read the GNPTXFSIZ register many times
18511 + (the output shows the number of times the register is read).
18512 + <td> Read</td>
18513 + </tr>
18514 +
18515 + <tr>
18516 + <td> wr_reg_test </td>
18517 + <td> Displays the time required to write the GNPTXFSIZ register many times
18518 + (the output shows the number of times the register is written).
18519 + <td> Read</td>
18520 + </tr>
18521 +
18522 + <tr>
18523 + <td> lpm_response </td>
18524 + <td> Gets or sets lpm_response mode. Applicable only in device mode.
18525 + <td> Write</td>
18526 + </tr>
18527 +
18528 + <tr>
18529 + <td> sleep_status </td>
18530 + <td> Shows sleep status of device.
18531 + <td> Read</td>
18532 + </tr>
18533 +
18534 + </table>
18535 +
18536 + Example usage:
18537 + To get the current mode:
18538 + cat /sys/devices/lm0/mode
18539 +
18540 + To power down the USB:
18541 + echo 0 > /sys/devices/lm0/buspower
18542 + */
18543 +
18544 +#include "dwc_otg_os_dep.h"
18545 +#include "dwc_os.h"
18546 +#include "dwc_otg_driver.h"
18547 +#include "dwc_otg_attr.h"
18548 +#include "dwc_otg_core_if.h"
18549 +#include "dwc_otg_pcd_if.h"
18550 +#include "dwc_otg_hcd_if.h"
18551 +
18552 +/*
18553 + * MACROs for defining sysfs attribute
18554 + */
18555 +#ifdef LM_INTERFACE
18556 +
18557 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
18558 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
18559 +{ \
18560 + struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
18561 + dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
18562 + uint32_t val; \
18563 + val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
18564 + return sprintf (buf, "%s = 0x%x\n", _string_, val); \
18565 +}
18566 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
18567 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
18568 + const char *buf, size_t count) \
18569 +{ \
18570 + struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
18571 + dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
18572 + uint32_t set = simple_strtoul(buf, NULL, 16); \
18573 + dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
18574 + return count; \
18575 +}
18576 +
18577 +#elif defined(PCI_INTERFACE)
18578 +
18579 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
18580 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
18581 +{ \
18582 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
18583 + uint32_t val; \
18584 + val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
18585 + return sprintf (buf, "%s = 0x%x\n", _string_, val); \
18586 +}
18587 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
18588 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
18589 + const char *buf, size_t count) \
18590 +{ \
18591 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
18592 + uint32_t set = simple_strtoul(buf, NULL, 16); \
18593 + dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
18594 + return count; \
18595 +}
18596 +
18597 +#elif defined(PLATFORM_INTERFACE)
18598 +
18599 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
18600 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
18601 +{ \
18602 + struct platform_device *platform_dev = \
18603 + container_of(_dev, struct platform_device, dev); \
18604 + dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
18605 + uint32_t val; \
18606 + DWC_PRINTF("%s(%p) -> platform_dev %p, otg_dev %p\n", \
18607 + __func__, _dev, platform_dev, otg_dev); \
18608 + val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
18609 + return sprintf (buf, "%s = 0x%x\n", _string_, val); \
18610 +}
18611 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
18612 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
18613 + const char *buf, size_t count) \
18614 +{ \
18615 + struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
18616 + dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
18617 + uint32_t set = simple_strtoul(buf, NULL, 16); \
18618 + dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
18619 + return count; \
18620 +}
18621 +#endif
18622 +
18623 +/*
18624 + * MACROs for defining sysfs attribute for 32-bit registers
18625 + */
18626 +#ifdef LM_INTERFACE
18627 +#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
18628 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
18629 +{ \
18630 + struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
18631 + dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
18632 + uint32_t val; \
18633 + val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
18634 + return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
18635 +}
18636 +#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
18637 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
18638 + const char *buf, size_t count) \
18639 +{ \
18640 + struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
18641 + dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
18642 + uint32_t val = simple_strtoul(buf, NULL, 16); \
18643 + dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
18644 + return count; \
18645 +}
18646 +#elif defined(PCI_INTERFACE)
18647 +#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
18648 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
18649 +{ \
18650 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
18651 + uint32_t val; \
18652 + val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
18653 + return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
18654 +}
18655 +#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
18656 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
18657 + const char *buf, size_t count) \
18658 +{ \
18659 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
18660 + uint32_t val = simple_strtoul(buf, NULL, 16); \
18661 + dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
18662 + return count; \
18663 +}
18664 +
18665 +#elif defined(PLATFORM_INTERFACE)
18666 +#include "dwc_otg_dbg.h"
18667 +#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
18668 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
18669 +{ \
18670 + struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
18671 + dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
18672 + uint32_t val; \
18673 + DWC_PRINTF("%s(%p) -> platform_dev %p, otg_dev %p\n", \
18674 + __func__, _dev, platform_dev, otg_dev); \
18675 + val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
18676 + return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
18677 +}
18678 +#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
18679 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
18680 + const char *buf, size_t count) \
18681 +{ \
18682 + struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
18683 + dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
18684 + uint32_t val = simple_strtoul(buf, NULL, 16); \
18685 + dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
18686 + return count; \
18687 +}
18688 +
18689 +#endif
18690 +
18691 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_string_) \
18692 +DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
18693 +DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
18694 +DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
18695 +
18696 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_string_) \
18697 +DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
18698 +DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
18699 +
18700 +#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \
18701 +DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
18702 +DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
18703 +DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
18704 +
18705 +#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \
18706 +DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
18707 +DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
18708 +
18709 +/** @name Functions for Show/Store of Attributes */
18710 +/**@{*/
18711 +
18712 +/**
18713 + * Helper function returning the otg_device structure of the given device
18714 + */
18715 +static dwc_otg_device_t *dwc_otg_drvdev(struct device *_dev)
18716 +{
18717 + dwc_otg_device_t *otg_dev;
18718 + DWC_OTG_GETDRVDEV(otg_dev, _dev);
18719 + return otg_dev;
18720 +}
18721 +
18722 +/**
18723 + * Show the register offset of the Register Access.
18724 + */
18725 +static ssize_t regoffset_show(struct device *_dev,
18726 + struct device_attribute *attr, char *buf)
18727 +{
18728 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18729 + return snprintf(buf, sizeof("0xFFFFFFFF\n") + 1, "0x%08x\n",
18730 + otg_dev->os_dep.reg_offset);
18731 +}
18732 +
18733 +/**
18734 + * Set the register offset for the next Register Access Read/Write
18735 + */
18736 +static ssize_t regoffset_store(struct device *_dev,
18737 + struct device_attribute *attr,
18738 + const char *buf, size_t count)
18739 +{
18740 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18741 + uint32_t offset = simple_strtoul(buf, NULL, 16);
18742 +#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
18743 + if (offset < SZ_256K) {
18744 +#elif defined(PCI_INTERFACE)
18745 + if (offset < 0x00040000) {
18746 +#endif
18747 + otg_dev->os_dep.reg_offset = offset;
18748 + } else {
18749 + dev_err(_dev, "invalid offset\n");
18750 + }
18751 +
18752 + return count;
18753 +}
18754 +
18755 +DEVICE_ATTR(regoffset, S_IRUGO | S_IWUSR, regoffset_show, regoffset_store);
18756 +
18757 +/**
18758 + * Show the value of the register at the offset in the reg_offset
18759 + * attribute.
18760 + */
18761 +static ssize_t regvalue_show(struct device *_dev,
18762 + struct device_attribute *attr, char *buf)
18763 +{
18764 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18765 + uint32_t val;
18766 + volatile uint32_t *addr;
18767 +
18768 + if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) {
18769 + /* Calculate the address */
18770 + addr = (uint32_t *) (otg_dev->os_dep.reg_offset +
18771 + (uint8_t *) otg_dev->os_dep.base);
18772 + val = DWC_READ_REG32(addr);
18773 + return snprintf(buf,
18774 + sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n") + 1,
18775 + "Reg@0x%06x = 0x%08x\n", otg_dev->os_dep.reg_offset,
18776 + val);
18777 + } else {
18778 + dev_err(_dev, "Invalid offset (0x%0x)\n", otg_dev->os_dep.reg_offset);
18779 + return sprintf(buf, "invalid offset\n");
18780 + }
18781 +}
18782 +
18783 +/**
18784 + * Store the value in the register at the offset in the reg_offset
18785 + * attribute.
18786 + *
18787 + */
18788 +static ssize_t regvalue_store(struct device *_dev,
18789 + struct device_attribute *attr,
18790 + const char *buf, size_t count)
18791 +{
18792 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18793 + volatile uint32_t *addr;
18794 + uint32_t val = simple_strtoul(buf, NULL, 16);
18795 + //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val);
18796 + if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) {
18797 + /* Calculate the address */
18798 + addr = (uint32_t *) (otg_dev->os_dep.reg_offset +
18799 + (uint8_t *) otg_dev->os_dep.base);
18800 + DWC_WRITE_REG32(addr, val);
18801 + } else {
18802 + dev_err(_dev, "Invalid Register Offset (0x%08x)\n",
18803 + otg_dev->os_dep.reg_offset);
18804 + }
18805 + return count;
18806 +}
18807 +
18808 +DEVICE_ATTR(regvalue, S_IRUGO | S_IWUSR, regvalue_show, regvalue_store);
18809 +
18810 +/*
18811 + * Attributes
18812 + */
18813 +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode, "Mode");
18814 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable, "HNPCapable");
18815 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable, "SRPCapable");
18816 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hsic_connect, "HSIC Connect");
18817 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(inv_sel_hsic, "Invert Select HSIC");
18818 +
18819 +//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
18820 +//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
18821 +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected, "Bus Connected");
18822 +
18823 +DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl, 0, "GOTGCTL");
18824 +DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,
18825 + &(otg_dev->core_if->core_global_regs->gusbcfg),
18826 + "GUSBCFG");
18827 +DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,
18828 + &(otg_dev->core_if->core_global_regs->grxfsiz),
18829 + "GRXFSIZ");
18830 +DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,
18831 + &(otg_dev->core_if->core_global_regs->gnptxfsiz),
18832 + "GNPTXFSIZ");
18833 +DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,
18834 + &(otg_dev->core_if->core_global_regs->gpvndctl),
18835 + "GPVNDCTL");
18836 +DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,
18837 + &(otg_dev->core_if->core_global_regs->ggpio),
18838 + "GGPIO");
18839 +DWC_OTG_DEVICE_ATTR_REG32_RW(guid, &(otg_dev->core_if->core_global_regs->guid),
18840 + "GUID");
18841 +DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,
18842 + &(otg_dev->core_if->core_global_regs->gsnpsid),
18843 + "GSNPSID");
18844 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed, "Device Speed");
18845 +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed, "Device Enumeration Speed");
18846 +
18847 +DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,
18848 + &(otg_dev->core_if->core_global_regs->hptxfsiz),
18849 + "HPTXFSIZ");
18850 +DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0, otg_dev->core_if->host_if->hprt0, "HPRT0");
18851 +
18852 +/**
18853 + * @todo Add code to initiate the HNP.
18854 + */
18855 +/**
18856 + * Show the HNP status bit
18857 + */
18858 +static ssize_t hnp_show(struct device *_dev,
18859 + struct device_attribute *attr, char *buf)
18860 +{
18861 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18862 + return sprintf(buf, "HstNegScs = 0x%x\n",
18863 + dwc_otg_get_hnpstatus(otg_dev->core_if));
18864 +}
18865 +
18866 +/**
18867 + * Set the HNP Request bit
18868 + */
18869 +static ssize_t hnp_store(struct device *_dev,
18870 + struct device_attribute *attr,
18871 + const char *buf, size_t count)
18872 +{
18873 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18874 + uint32_t in = simple_strtoul(buf, NULL, 16);
18875 + dwc_otg_set_hnpreq(otg_dev->core_if, in);
18876 + return count;
18877 +}
18878 +
18879 +DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);
18880 +
18881 +/**
18882 + * @todo Add code to initiate the SRP.
18883 + */
18884 +/**
18885 + * Show the SRP status bit
18886 + */
18887 +static ssize_t srp_show(struct device *_dev,
18888 + struct device_attribute *attr, char *buf)
18889 +{
18890 +#ifndef DWC_HOST_ONLY
18891 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18892 + return sprintf(buf, "SesReqScs = 0x%x\n",
18893 + dwc_otg_get_srpstatus(otg_dev->core_if));
18894 +#else
18895 + return sprintf(buf, "Host Only Mode!\n");
18896 +#endif
18897 +}
18898 +
18899 +/**
18900 + * Set the SRP Request bit
18901 + */
18902 +static ssize_t srp_store(struct device *_dev,
18903 + struct device_attribute *attr,
18904 + const char *buf, size_t count)
18905 +{
18906 +#ifndef DWC_HOST_ONLY
18907 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18908 + dwc_otg_pcd_initiate_srp(otg_dev->pcd);
18909 +#endif
18910 + return count;
18911 +}
18912 +
18913 +DEVICE_ATTR(srp, 0644, srp_show, srp_store);
18914 +
18915 +/**
18916 + * @todo Need to do more for power on/off?
18917 + */
18918 +/**
18919 + * Show the Bus Power status
18920 + */
18921 +static ssize_t buspower_show(struct device *_dev,
18922 + struct device_attribute *attr, char *buf)
18923 +{
18924 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18925 + return sprintf(buf, "Bus Power = 0x%x\n",
18926 + dwc_otg_get_prtpower(otg_dev->core_if));
18927 +}
18928 +
18929 +/**
18930 + * Set the Bus Power status
18931 + */
18932 +static ssize_t buspower_store(struct device *_dev,
18933 + struct device_attribute *attr,
18934 + const char *buf, size_t count)
18935 +{
18936 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18937 + uint32_t on = simple_strtoul(buf, NULL, 16);
18938 + dwc_otg_set_prtpower(otg_dev->core_if, on);
18939 + return count;
18940 +}
18941 +
18942 +DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);
18943 +
18944 +/**
18945 + * @todo Need to do more for suspend?
18946 + */
18947 +/**
18948 + * Show the Bus Suspend status
18949 + */
18950 +static ssize_t bussuspend_show(struct device *_dev,
18951 + struct device_attribute *attr, char *buf)
18952 +{
18953 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18954 + return sprintf(buf, "Bus Suspend = 0x%x\n",
18955 + dwc_otg_get_prtsuspend(otg_dev->core_if));
18956 +}
18957 +
18958 +/**
18959 + * Set the Bus Suspend status
18960 + */
18961 +static ssize_t bussuspend_store(struct device *_dev,
18962 + struct device_attribute *attr,
18963 + const char *buf, size_t count)
18964 +{
18965 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18966 + uint32_t in = simple_strtoul(buf, NULL, 16);
18967 + dwc_otg_set_prtsuspend(otg_dev->core_if, in);
18968 + return count;
18969 +}
18970 +
18971 +DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);
18972 +
18973 +/**
18974 + * Show the Mode Change Ready Timer status
18975 + */
18976 +static ssize_t mode_ch_tim_en_show(struct device *_dev,
18977 + struct device_attribute *attr, char *buf)
18978 +{
18979 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18980 + return sprintf(buf, "Mode Change Ready Timer Enable = 0x%x\n",
18981 + dwc_otg_get_mode_ch_tim(otg_dev->core_if));
18982 +}
18983 +
18984 +/**
18985 + * Set the Mode Change Ready Timer status
18986 + */
18987 +static ssize_t mode_ch_tim_en_store(struct device *_dev,
18988 + struct device_attribute *attr,
18989 + const char *buf, size_t count)
18990 +{
18991 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18992 + uint32_t in = simple_strtoul(buf, NULL, 16);
18993 + dwc_otg_set_mode_ch_tim(otg_dev->core_if, in);
18994 + return count;
18995 +}
18996 +
18997 +DEVICE_ATTR(mode_ch_tim_en, 0644, mode_ch_tim_en_show, mode_ch_tim_en_store);
18998 +
18999 +/**
19000 + * Show the value of HFIR Frame Interval bitfield
19001 + */
19002 +static ssize_t fr_interval_show(struct device *_dev,
19003 + struct device_attribute *attr, char *buf)
19004 +{
19005 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19006 + return sprintf(buf, "Frame Interval = 0x%x\n",
19007 + dwc_otg_get_fr_interval(otg_dev->core_if));
19008 +}
19009 +
19010 +/**
19011 + * Set the HFIR Frame Interval value
19012 + */
19013 +static ssize_t fr_interval_store(struct device *_dev,
19014 + struct device_attribute *attr,
19015 + const char *buf, size_t count)
19016 +{
19017 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19018 + uint32_t in = simple_strtoul(buf, NULL, 10);
19019 + dwc_otg_set_fr_interval(otg_dev->core_if, in);
19020 + return count;
19021 +}
19022 +
19023 +DEVICE_ATTR(fr_interval, 0644, fr_interval_show, fr_interval_store);
19024 +
19025 +/**
19026 + * Show the status of Remote Wakeup.
19027 + */
19028 +static ssize_t remote_wakeup_show(struct device *_dev,
19029 + struct device_attribute *attr, char *buf)
19030 +{
19031 +#ifndef DWC_HOST_ONLY
19032 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19033 +
19034 + return sprintf(buf,
19035 + "Remote Wakeup Sig = %d Enabled = %d LPM Remote Wakeup = %d\n",
19036 + dwc_otg_get_remotewakesig(otg_dev->core_if),
19037 + dwc_otg_pcd_get_rmwkup_enable(otg_dev->pcd),
19038 + dwc_otg_get_lpm_remotewakeenabled(otg_dev->core_if));
19039 +#else
19040 + return sprintf(buf, "Host Only Mode!\n");
19041 +#endif /* DWC_HOST_ONLY */
19042 +}
19043 +
19044 +/**
19045 + * Initiate a remote wakeup of the host. The Device control register
19046 + * Remote Wakeup Signal bit is written if the PCD Remote wakeup enable
19047 + * flag is set.
19048 + *
19049 + */
19050 +static ssize_t remote_wakeup_store(struct device *_dev,
19051 + struct device_attribute *attr,
19052 + const char *buf, size_t count)
19053 +{
19054 +#ifndef DWC_HOST_ONLY
19055 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19056 + uint32_t val = simple_strtoul(buf, NULL, 16);
19057 +
19058 + if (val & 1) {
19059 + dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
19060 + } else {
19061 + dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);
19062 + }
19063 +#endif /* DWC_HOST_ONLY */
19064 + return count;
19065 +}
19066 +
19067 +DEVICE_ATTR(remote_wakeup, S_IRUGO | S_IWUSR, remote_wakeup_show,
19068 + remote_wakeup_store);
19069 +
19070 +/**
19071 + * Show the whether core is hibernated or not.
19072 + */
19073 +static ssize_t rem_wakeup_pwrdn_show(struct device *_dev,
19074 + struct device_attribute *attr, char *buf)
19075 +{
19076 +#ifndef DWC_HOST_ONLY
19077 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19078 +
19079 + if (dwc_otg_get_core_state(otg_dev->core_if)) {
19080 + DWC_PRINTF("Core is in hibernation\n");
19081 + } else {
19082 + DWC_PRINTF("Core is not in hibernation\n");
19083 + }
19084 +#endif /* DWC_HOST_ONLY */
19085 + return 0;
19086 +}
19087 +
19088 +extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
19089 + int rem_wakeup, int reset);
19090 +
19091 +/**
19092 + * Initiate a remote wakeup of the device to exit from hibernation.
19093 + */
19094 +static ssize_t rem_wakeup_pwrdn_store(struct device *_dev,
19095 + struct device_attribute *attr,
19096 + const char *buf, size_t count)
19097 +{
19098 +#ifndef DWC_HOST_ONLY
19099 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19100 + dwc_otg_device_hibernation_restore(otg_dev->core_if, 1, 0);
19101 +#endif
19102 + return count;
19103 +}
19104 +
19105 +DEVICE_ATTR(rem_wakeup_pwrdn, S_IRUGO | S_IWUSR, rem_wakeup_pwrdn_show,
19106 + rem_wakeup_pwrdn_store);
19107 +
19108 +static ssize_t disconnect_us(struct device *_dev,
19109 + struct device_attribute *attr,
19110 + const char *buf, size_t count)
19111 +{
19112 +
19113 +#ifndef DWC_HOST_ONLY
19114 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19115 + uint32_t val = simple_strtoul(buf, NULL, 16);
19116 + DWC_PRINTF("The Passed value is %04x\n", val);
19117 +
19118 + dwc_otg_pcd_disconnect_us(otg_dev->pcd, 50);
19119 +
19120 +#endif /* DWC_HOST_ONLY */
19121 + return count;
19122 +}
19123 +
19124 +DEVICE_ATTR(disconnect_us, S_IWUSR, 0, disconnect_us);
19125 +
19126 +/**
19127 + * Dump global registers and either host or device registers (depending on the
19128 + * current mode of the core).
19129 + */
19130 +static ssize_t regdump_show(struct device *_dev,
19131 + struct device_attribute *attr, char *buf)
19132 +{
19133 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19134 +
19135 + dwc_otg_dump_global_registers(otg_dev->core_if);
19136 + if (dwc_otg_is_host_mode(otg_dev->core_if)) {
19137 + dwc_otg_dump_host_registers(otg_dev->core_if);
19138 + } else {
19139 + dwc_otg_dump_dev_registers(otg_dev->core_if);
19140 +
19141 + }
19142 + return sprintf(buf, "Register Dump\n");
19143 +}
19144 +
19145 +DEVICE_ATTR(regdump, S_IRUGO, regdump_show, 0);
19146 +
19147 +/**
19148 + * Dump global registers and either host or device registers (depending on the
19149 + * current mode of the core).
19150 + */
19151 +static ssize_t spramdump_show(struct device *_dev,
19152 + struct device_attribute *attr, char *buf)
19153 +{
19154 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19155 +
19156 + //dwc_otg_dump_spram(otg_dev->core_if);
19157 +
19158 + return sprintf(buf, "SPRAM Dump\n");
19159 +}
19160 +
19161 +DEVICE_ATTR(spramdump, S_IRUGO, spramdump_show, 0);
19162 +
19163 +/**
19164 + * Dump the current hcd state.
19165 + */
19166 +static ssize_t hcddump_show(struct device *_dev,
19167 + struct device_attribute *attr, char *buf)
19168 +{
19169 +#ifndef DWC_DEVICE_ONLY
19170 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19171 + dwc_otg_hcd_dump_state(otg_dev->hcd);
19172 +#endif /* DWC_DEVICE_ONLY */
19173 + return sprintf(buf, "HCD Dump\n");
19174 +}
19175 +
19176 +DEVICE_ATTR(hcddump, S_IRUGO, hcddump_show, 0);
19177 +
19178 +/**
19179 + * Dump the average frame remaining at SOF. This can be used to
19180 + * determine average interrupt latency. Frame remaining is also shown for
19181 + * start transfer and two additional sample points.
19182 + */
19183 +static ssize_t hcd_frrem_show(struct device *_dev,
19184 + struct device_attribute *attr, char *buf)
19185 +{
19186 +#ifndef DWC_DEVICE_ONLY
19187 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19188 +
19189 + dwc_otg_hcd_dump_frrem(otg_dev->hcd);
19190 +#endif /* DWC_DEVICE_ONLY */
19191 + return sprintf(buf, "HCD Dump Frame Remaining\n");
19192 +}
19193 +
19194 +DEVICE_ATTR(hcd_frrem, S_IRUGO, hcd_frrem_show, 0);
19195 +
19196 +/**
19197 + * Displays the time required to read the GNPTXFSIZ register many times (the
19198 + * output shows the number of times the register is read).
19199 + */
19200 +#define RW_REG_COUNT 10000000
19201 +#define MSEC_PER_JIFFIE 1000/HZ
19202 +static ssize_t rd_reg_test_show(struct device *_dev,
19203 + struct device_attribute *attr, char *buf)
19204 +{
19205 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19206 + int i;
19207 + int time;
19208 + int start_jiffies;
19209 +
19210 + printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
19211 + HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
19212 + start_jiffies = jiffies;
19213 + for (i = 0; i < RW_REG_COUNT; i++) {
19214 + dwc_otg_get_gnptxfsiz(otg_dev->core_if);
19215 + }
19216 + time = jiffies - start_jiffies;
19217 + return sprintf(buf,
19218 + "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
19219 + RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
19220 +}
19221 +
19222 +DEVICE_ATTR(rd_reg_test, S_IRUGO, rd_reg_test_show, 0);
19223 +
19224 +/**
19225 + * Displays the time required to write the GNPTXFSIZ register many times (the
19226 + * output shows the number of times the register is written).
19227 + */
19228 +static ssize_t wr_reg_test_show(struct device *_dev,
19229 + struct device_attribute *attr, char *buf)
19230 +{
19231 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19232 + uint32_t reg_val;
19233 + int i;
19234 + int time;
19235 + int start_jiffies;
19236 +
19237 + printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
19238 + HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
19239 + reg_val = dwc_otg_get_gnptxfsiz(otg_dev->core_if);
19240 + start_jiffies = jiffies;
19241 + for (i = 0; i < RW_REG_COUNT; i++) {
19242 + dwc_otg_set_gnptxfsiz(otg_dev->core_if, reg_val);
19243 + }
19244 + time = jiffies - start_jiffies;
19245 + return sprintf(buf,
19246 + "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
19247 + RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
19248 +}
19249 +
19250 +DEVICE_ATTR(wr_reg_test, S_IRUGO, wr_reg_test_show, 0);
19251 +
19252 +#ifdef CONFIG_USB_DWC_OTG_LPM
19253 +
19254 +/**
19255 +* Show the lpm_response attribute.
19256 +*/
19257 +static ssize_t lpmresp_show(struct device *_dev,
19258 + struct device_attribute *attr, char *buf)
19259 +{
19260 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19261 +
19262 + if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if))
19263 + return sprintf(buf, "** LPM is DISABLED **\n");
19264 +
19265 + if (!dwc_otg_is_device_mode(otg_dev->core_if)) {
19266 + return sprintf(buf, "** Current mode is not device mode\n");
19267 + }
19268 + return sprintf(buf, "lpm_response = %d\n",
19269 + dwc_otg_get_lpmresponse(otg_dev->core_if));
19270 +}
19271 +
19272 +/**
19273 +* Store the lpm_response attribute.
19274 +*/
19275 +static ssize_t lpmresp_store(struct device *_dev,
19276 + struct device_attribute *attr,
19277 + const char *buf, size_t count)
19278 +{
19279 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19280 + uint32_t val = simple_strtoul(buf, NULL, 16);
19281 +
19282 + if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if)) {
19283 + return 0;
19284 + }
19285 +
19286 + if (!dwc_otg_is_device_mode(otg_dev->core_if)) {
19287 + return 0;
19288 + }
19289 +
19290 + dwc_otg_set_lpmresponse(otg_dev->core_if, val);
19291 + return count;
19292 +}
19293 +
19294 +DEVICE_ATTR(lpm_response, S_IRUGO | S_IWUSR, lpmresp_show, lpmresp_store);
19295 +
19296 +/**
19297 +* Show the sleep_status attribute.
19298 +*/
19299 +static ssize_t sleepstatus_show(struct device *_dev,
19300 + struct device_attribute *attr, char *buf)
19301 +{
19302 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19303 + return sprintf(buf, "Sleep Status = %d\n",
19304 + dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if));
19305 +}
19306 +
19307 +/**
19308 + * Store the sleep_status attribure.
19309 + */
19310 +static ssize_t sleepstatus_store(struct device *_dev,
19311 + struct device_attribute *attr,
19312 + const char *buf, size_t count)
19313 +{
19314 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19315 + dwc_otg_core_if_t *core_if = otg_dev->core_if;
19316 +
19317 + if (dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)) {
19318 + if (dwc_otg_is_host_mode(core_if)) {
19319 +
19320 + DWC_PRINTF("Host initiated resume\n");
19321 + dwc_otg_set_prtresume(otg_dev->core_if, 1);
19322 + }
19323 + }
19324 +
19325 + return count;
19326 +}
19327 +
19328 +DEVICE_ATTR(sleep_status, S_IRUGO | S_IWUSR, sleepstatus_show,
19329 + sleepstatus_store);
19330 +
19331 +#endif /* CONFIG_USB_DWC_OTG_LPM_ENABLE */
19332 +
19333 +/**@}*/
19334 +
19335 +/**
19336 + * Create the device files
19337 + */
19338 +void dwc_otg_attr_create(
19339 +#ifdef LM_INTERFACE
19340 + struct lm_device *dev
19341 +#elif defined(PCI_INTERFACE)
19342 + struct pci_dev *dev
19343 +#elif defined(PLATFORM_INTERFACE)
19344 + struct platform_device *dev
19345 +#endif
19346 + )
19347 +{
19348 + int error;
19349 +
19350 + error = device_create_file(&dev->dev, &dev_attr_regoffset);
19351 + error = device_create_file(&dev->dev, &dev_attr_regvalue);
19352 + error = device_create_file(&dev->dev, &dev_attr_mode);
19353 + error = device_create_file(&dev->dev, &dev_attr_hnpcapable);
19354 + error = device_create_file(&dev->dev, &dev_attr_srpcapable);
19355 + error = device_create_file(&dev->dev, &dev_attr_hsic_connect);
19356 + error = device_create_file(&dev->dev, &dev_attr_inv_sel_hsic);
19357 + error = device_create_file(&dev->dev, &dev_attr_hnp);
19358 + error = device_create_file(&dev->dev, &dev_attr_srp);
19359 + error = device_create_file(&dev->dev, &dev_attr_buspower);
19360 + error = device_create_file(&dev->dev, &dev_attr_bussuspend);
19361 + error = device_create_file(&dev->dev, &dev_attr_mode_ch_tim_en);
19362 + error = device_create_file(&dev->dev, &dev_attr_fr_interval);
19363 + error = device_create_file(&dev->dev, &dev_attr_busconnected);
19364 + error = device_create_file(&dev->dev, &dev_attr_gotgctl);
19365 + error = device_create_file(&dev->dev, &dev_attr_gusbcfg);
19366 + error = device_create_file(&dev->dev, &dev_attr_grxfsiz);
19367 + error = device_create_file(&dev->dev, &dev_attr_gnptxfsiz);
19368 + error = device_create_file(&dev->dev, &dev_attr_gpvndctl);
19369 + error = device_create_file(&dev->dev, &dev_attr_ggpio);
19370 + error = device_create_file(&dev->dev, &dev_attr_guid);
19371 + error = device_create_file(&dev->dev, &dev_attr_gsnpsid);
19372 + error = device_create_file(&dev->dev, &dev_attr_devspeed);
19373 + error = device_create_file(&dev->dev, &dev_attr_enumspeed);
19374 + error = device_create_file(&dev->dev, &dev_attr_hptxfsiz);
19375 + error = device_create_file(&dev->dev, &dev_attr_hprt0);
19376 + error = device_create_file(&dev->dev, &dev_attr_remote_wakeup);
19377 + error = device_create_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn);
19378 + error = device_create_file(&dev->dev, &dev_attr_disconnect_us);
19379 + error = device_create_file(&dev->dev, &dev_attr_regdump);
19380 + error = device_create_file(&dev->dev, &dev_attr_spramdump);
19381 + error = device_create_file(&dev->dev, &dev_attr_hcddump);
19382 + error = device_create_file(&dev->dev, &dev_attr_hcd_frrem);
19383 + error = device_create_file(&dev->dev, &dev_attr_rd_reg_test);
19384 + error = device_create_file(&dev->dev, &dev_attr_wr_reg_test);
19385 +#ifdef CONFIG_USB_DWC_OTG_LPM
19386 + error = device_create_file(&dev->dev, &dev_attr_lpm_response);
19387 + error = device_create_file(&dev->dev, &dev_attr_sleep_status);
19388 +#endif
19389 +}
19390 +
19391 +/**
19392 + * Remove the device files
19393 + */
19394 +void dwc_otg_attr_remove(
19395 +#ifdef LM_INTERFACE
19396 + struct lm_device *dev
19397 +#elif defined(PCI_INTERFACE)
19398 + struct pci_dev *dev
19399 +#elif defined(PLATFORM_INTERFACE)
19400 + struct platform_device *dev
19401 +#endif
19402 + )
19403 +{
19404 + device_remove_file(&dev->dev, &dev_attr_regoffset);
19405 + device_remove_file(&dev->dev, &dev_attr_regvalue);
19406 + device_remove_file(&dev->dev, &dev_attr_mode);
19407 + device_remove_file(&dev->dev, &dev_attr_hnpcapable);
19408 + device_remove_file(&dev->dev, &dev_attr_srpcapable);
19409 + device_remove_file(&dev->dev, &dev_attr_hsic_connect);
19410 + device_remove_file(&dev->dev, &dev_attr_inv_sel_hsic);
19411 + device_remove_file(&dev->dev, &dev_attr_hnp);
19412 + device_remove_file(&dev->dev, &dev_attr_srp);
19413 + device_remove_file(&dev->dev, &dev_attr_buspower);
19414 + device_remove_file(&dev->dev, &dev_attr_bussuspend);
19415 + device_remove_file(&dev->dev, &dev_attr_mode_ch_tim_en);
19416 + device_remove_file(&dev->dev, &dev_attr_fr_interval);
19417 + device_remove_file(&dev->dev, &dev_attr_busconnected);
19418 + device_remove_file(&dev->dev, &dev_attr_gotgctl);
19419 + device_remove_file(&dev->dev, &dev_attr_gusbcfg);
19420 + device_remove_file(&dev->dev, &dev_attr_grxfsiz);
19421 + device_remove_file(&dev->dev, &dev_attr_gnptxfsiz);
19422 + device_remove_file(&dev->dev, &dev_attr_gpvndctl);
19423 + device_remove_file(&dev->dev, &dev_attr_ggpio);
19424 + device_remove_file(&dev->dev, &dev_attr_guid);
19425 + device_remove_file(&dev->dev, &dev_attr_gsnpsid);
19426 + device_remove_file(&dev->dev, &dev_attr_devspeed);
19427 + device_remove_file(&dev->dev, &dev_attr_enumspeed);
19428 + device_remove_file(&dev->dev, &dev_attr_hptxfsiz);
19429 + device_remove_file(&dev->dev, &dev_attr_hprt0);
19430 + device_remove_file(&dev->dev, &dev_attr_remote_wakeup);
19431 + device_remove_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn);
19432 + device_remove_file(&dev->dev, &dev_attr_disconnect_us);
19433 + device_remove_file(&dev->dev, &dev_attr_regdump);
19434 + device_remove_file(&dev->dev, &dev_attr_spramdump);
19435 + device_remove_file(&dev->dev, &dev_attr_hcddump);
19436 + device_remove_file(&dev->dev, &dev_attr_hcd_frrem);
19437 + device_remove_file(&dev->dev, &dev_attr_rd_reg_test);
19438 + device_remove_file(&dev->dev, &dev_attr_wr_reg_test);
19439 +#ifdef CONFIG_USB_DWC_OTG_LPM
19440 + device_remove_file(&dev->dev, &dev_attr_lpm_response);
19441 + device_remove_file(&dev->dev, &dev_attr_sleep_status);
19442 +#endif
19443 +}
19444 --- /dev/null
19445 +++ b/drivers/usb/host/dwc_otg/dwc_otg_attr.h
19446 @@ -0,0 +1,89 @@
19447 +/* ==========================================================================
19448 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $
19449 + * $Revision: #13 $
19450 + * $Date: 2010/06/21 $
19451 + * $Change: 1532021 $
19452 + *
19453 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
19454 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
19455 + * otherwise expressly agreed to in writing between Synopsys and you.
19456 + *
19457 + * The Software IS NOT an item of Licensed Software or Licensed Product under
19458 + * any End User Software License Agreement or Agreement for Licensed Product
19459 + * with Synopsys or any supplement thereto. You are permitted to use and
19460 + * redistribute this Software in source and binary forms, with or without
19461 + * modification, provided that redistributions of source code must retain this
19462 + * notice. You may not view, use, disclose, copy or distribute this file or
19463 + * any information contained herein except pursuant to this license grant from
19464 + * Synopsys. If you do not agree with this notice, including the disclaimer
19465 + * below, then you are not authorized to use the Software.
19466 + *
19467 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
19468 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19469 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19470 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
19471 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19472 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19473 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
19474 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
19475 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
19476 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
19477 + * DAMAGE.
19478 + * ========================================================================== */
19479 +
19480 +#if !defined(__DWC_OTG_ATTR_H__)
19481 +#define __DWC_OTG_ATTR_H__
19482 +
19483 +/** @file
19484 + * This file contains the interface to the Linux device attributes.
19485 + */
19486 +extern struct device_attribute dev_attr_regoffset;
19487 +extern struct device_attribute dev_attr_regvalue;
19488 +
19489 +extern struct device_attribute dev_attr_mode;
19490 +extern struct device_attribute dev_attr_hnpcapable;
19491 +extern struct device_attribute dev_attr_srpcapable;
19492 +extern struct device_attribute dev_attr_hnp;
19493 +extern struct device_attribute dev_attr_srp;
19494 +extern struct device_attribute dev_attr_buspower;
19495 +extern struct device_attribute dev_attr_bussuspend;
19496 +extern struct device_attribute dev_attr_mode_ch_tim_en;
19497 +extern struct device_attribute dev_attr_fr_interval;
19498 +extern struct device_attribute dev_attr_busconnected;
19499 +extern struct device_attribute dev_attr_gotgctl;
19500 +extern struct device_attribute dev_attr_gusbcfg;
19501 +extern struct device_attribute dev_attr_grxfsiz;
19502 +extern struct device_attribute dev_attr_gnptxfsiz;
19503 +extern struct device_attribute dev_attr_gpvndctl;
19504 +extern struct device_attribute dev_attr_ggpio;
19505 +extern struct device_attribute dev_attr_guid;
19506 +extern struct device_attribute dev_attr_gsnpsid;
19507 +extern struct device_attribute dev_attr_devspeed;
19508 +extern struct device_attribute dev_attr_enumspeed;
19509 +extern struct device_attribute dev_attr_hptxfsiz;
19510 +extern struct device_attribute dev_attr_hprt0;
19511 +#ifdef CONFIG_USB_DWC_OTG_LPM
19512 +extern struct device_attribute dev_attr_lpm_response;
19513 +extern struct device_attribute devi_attr_sleep_status;
19514 +#endif
19515 +
19516 +void dwc_otg_attr_create(
19517 +#ifdef LM_INTERFACE
19518 + struct lm_device *dev
19519 +#elif defined(PCI_INTERFACE)
19520 + struct pci_dev *dev
19521 +#elif defined(PLATFORM_INTERFACE)
19522 + struct platform_device *dev
19523 +#endif
19524 + );
19525 +
19526 +void dwc_otg_attr_remove(
19527 +#ifdef LM_INTERFACE
19528 + struct lm_device *dev
19529 +#elif defined(PCI_INTERFACE)
19530 + struct pci_dev *dev
19531 +#elif defined(PLATFORM_INTERFACE)
19532 + struct platform_device *dev
19533 +#endif
19534 + );
19535 +#endif
19536 --- /dev/null
19537 +++ b/drivers/usb/host/dwc_otg/dwc_otg_cfi.c
19538 @@ -0,0 +1,1876 @@
19539 +/* ==========================================================================
19540 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
19541 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
19542 + * otherwise expressly agreed to in writing between Synopsys and you.
19543 + *
19544 + * The Software IS NOT an item of Licensed Software or Licensed Product under
19545 + * any End User Software License Agreement or Agreement for Licensed Product
19546 + * with Synopsys or any supplement thereto. You are permitted to use and
19547 + * redistribute this Software in source and binary forms, with or without
19548 + * modification, provided that redistributions of source code must retain this
19549 + * notice. You may not view, use, disclose, copy or distribute this file or
19550 + * any information contained herein except pursuant to this license grant from
19551 + * Synopsys. If you do not agree with this notice, including the disclaimer
19552 + * below, then you are not authorized to use the Software.
19553 + *
19554 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
19555 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19556 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19557 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
19558 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19559 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19560 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
19561 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
19562 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
19563 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
19564 + * DAMAGE.
19565 + * ========================================================================== */
19566 +
19567 +/** @file
19568 + *
19569 + * This file contains the most of the CFI(Core Feature Interface)
19570 + * implementation for the OTG.
19571 + */
19572 +
19573 +#ifdef DWC_UTE_CFI
19574 +
19575 +#include "dwc_otg_pcd.h"
19576 +#include "dwc_otg_cfi.h"
19577 +
19578 +/** This definition should actually migrate to the Portability Library */
19579 +#define DWC_CONSTANT_CPU_TO_LE16(x) (x)
19580 +
19581 +extern dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex);
19582 +
19583 +static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen);
19584 +static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
19585 + struct dwc_otg_pcd *pcd,
19586 + struct cfi_usb_ctrlrequest *ctrl_req);
19587 +static int cfi_set_feature_value(struct dwc_otg_pcd *pcd);
19588 +static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
19589 + struct cfi_usb_ctrlrequest *req);
19590 +static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
19591 + struct cfi_usb_ctrlrequest *req);
19592 +static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
19593 + struct cfi_usb_ctrlrequest *req);
19594 +static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,
19595 + struct cfi_usb_ctrlrequest *req);
19596 +static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep);
19597 +
19598 +static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if);
19599 +static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue);
19600 +static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue);
19601 +
19602 +static uint8_t resize_fifos(dwc_otg_core_if_t * core_if);
19603 +
19604 +/** This is the header of the all features descriptor */
19605 +static cfi_all_features_header_t all_props_desc_header = {
19606 + .wVersion = DWC_CONSTANT_CPU_TO_LE16(0x100),
19607 + .wCoreID = DWC_CONSTANT_CPU_TO_LE16(CFI_CORE_ID_OTG),
19608 + .wNumFeatures = DWC_CONSTANT_CPU_TO_LE16(9),
19609 +};
19610 +
19611 +/** This is an array of statically allocated feature descriptors */
19612 +static cfi_feature_desc_header_t prop_descs[] = {
19613 +
19614 + /* FT_ID_DMA_MODE */
19615 + {
19616 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_MODE),
19617 + .bmAttributes = CFI_FEATURE_ATTR_RW,
19618 + .wDataLength = DWC_CONSTANT_CPU_TO_LE16(1),
19619 + },
19620 +
19621 + /* FT_ID_DMA_BUFFER_SETUP */
19622 + {
19623 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFFER_SETUP),
19624 + .bmAttributes = CFI_FEATURE_ATTR_RW,
19625 + .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
19626 + },
19627 +
19628 + /* FT_ID_DMA_BUFF_ALIGN */
19629 + {
19630 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFF_ALIGN),
19631 + .bmAttributes = CFI_FEATURE_ATTR_RW,
19632 + .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
19633 + },
19634 +
19635 + /* FT_ID_DMA_CONCAT_SETUP */
19636 + {
19637 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CONCAT_SETUP),
19638 + .bmAttributes = CFI_FEATURE_ATTR_RW,
19639 + //.wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
19640 + },
19641 +
19642 + /* FT_ID_DMA_CIRCULAR */
19643 + {
19644 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CIRCULAR),
19645 + .bmAttributes = CFI_FEATURE_ATTR_RW,
19646 + .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
19647 + },
19648 +
19649 + /* FT_ID_THRESHOLD_SETUP */
19650 + {
19651 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_THRESHOLD_SETUP),
19652 + .bmAttributes = CFI_FEATURE_ATTR_RW,
19653 + .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
19654 + },
19655 +
19656 + /* FT_ID_DFIFO_DEPTH */
19657 + {
19658 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DFIFO_DEPTH),
19659 + .bmAttributes = CFI_FEATURE_ATTR_RO,
19660 + .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
19661 + },
19662 +
19663 + /* FT_ID_TX_FIFO_DEPTH */
19664 + {
19665 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_TX_FIFO_DEPTH),
19666 + .bmAttributes = CFI_FEATURE_ATTR_RW,
19667 + .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
19668 + },
19669 +
19670 + /* FT_ID_RX_FIFO_DEPTH */
19671 + {
19672 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_RX_FIFO_DEPTH),
19673 + .bmAttributes = CFI_FEATURE_ATTR_RW,
19674 + .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
19675 + }
19676 +};
19677 +
19678 +/** The table of feature names */
19679 +cfi_string_t prop_name_table[] = {
19680 + {FT_ID_DMA_MODE, "dma_mode"},
19681 + {FT_ID_DMA_BUFFER_SETUP, "buffer_setup"},
19682 + {FT_ID_DMA_BUFF_ALIGN, "buffer_align"},
19683 + {FT_ID_DMA_CONCAT_SETUP, "concat_setup"},
19684 + {FT_ID_DMA_CIRCULAR, "buffer_circular"},
19685 + {FT_ID_THRESHOLD_SETUP, "threshold_setup"},
19686 + {FT_ID_DFIFO_DEPTH, "dfifo_depth"},
19687 + {FT_ID_TX_FIFO_DEPTH, "txfifo_depth"},
19688 + {FT_ID_RX_FIFO_DEPTH, "rxfifo_depth"},
19689 + {}
19690 +};
19691 +
19692 +/************************************************************************/
19693 +
19694 +/**
19695 + * Returns the name of the feature by its ID
19696 + * or NULL if no featute ID matches.
19697 + *
19698 + */
19699 +const uint8_t *get_prop_name(uint16_t prop_id, int *len)
19700 +{
19701 + cfi_string_t *pstr;
19702 + *len = 0;
19703 +
19704 + for (pstr = prop_name_table; pstr && pstr->s; pstr++) {
19705 + if (pstr->id == prop_id) {
19706 + *len = DWC_STRLEN(pstr->s);
19707 + return pstr->s;
19708 + }
19709 + }
19710 + return NULL;
19711 +}
19712 +
19713 +/**
19714 + * This function handles all CFI specific control requests.
19715 + *
19716 + * Return a negative value to stall the DCE.
19717 + */
19718 +int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl)
19719 +{
19720 + int retval = 0;
19721 + dwc_otg_pcd_ep_t *ep = NULL;
19722 + cfiobject_t *cfi = pcd->cfi;
19723 + struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);
19724 + uint16_t wLen = DWC_LE16_TO_CPU(&ctrl->wLength);
19725 + uint16_t wValue = DWC_LE16_TO_CPU(&ctrl->wValue);
19726 + uint16_t wIndex = DWC_LE16_TO_CPU(&ctrl->wIndex);
19727 + uint32_t regaddr = 0;
19728 + uint32_t regval = 0;
19729 +
19730 + /* Save this Control Request in the CFI object.
19731 + * The data field will be assigned in the data stage completion CB function.
19732 + */
19733 + cfi->ctrl_req = *ctrl;
19734 + cfi->ctrl_req.data = NULL;
19735 +
19736 + cfi->need_gadget_att = 0;
19737 + cfi->need_status_in_complete = 0;
19738 +
19739 + switch (ctrl->bRequest) {
19740 + case VEN_CORE_GET_FEATURES:
19741 + retval = cfi_core_features_buf(cfi->buf_in.buf, CFI_IN_BUF_LEN);
19742 + if (retval >= 0) {
19743 + //dump_msg(cfi->buf_in.buf, retval);
19744 + ep = &pcd->ep0;
19745 +
19746 + retval = min((uint16_t) retval, wLen);
19747 + /* Transfer this buffer to the host through the EP0-IN EP */
19748 + ep->dwc_ep.dma_addr = cfi->buf_in.addr;
19749 + ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
19750 + ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
19751 + ep->dwc_ep.xfer_len = retval;
19752 + ep->dwc_ep.xfer_count = 0;
19753 + ep->dwc_ep.sent_zlp = 0;
19754 + ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
19755 +
19756 + pcd->ep0_pending = 1;
19757 + dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
19758 + }
19759 + retval = 0;
19760 + break;
19761 +
19762 + case VEN_CORE_GET_FEATURE:
19763 + CFI_INFO("VEN_CORE_GET_FEATURE\n");
19764 + retval = cfi_get_feature_value(cfi->buf_in.buf, CFI_IN_BUF_LEN,
19765 + pcd, ctrl);
19766 + if (retval >= 0) {
19767 + ep = &pcd->ep0;
19768 +
19769 + retval = min((uint16_t) retval, wLen);
19770 + /* Transfer this buffer to the host through the EP0-IN EP */
19771 + ep->dwc_ep.dma_addr = cfi->buf_in.addr;
19772 + ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
19773 + ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
19774 + ep->dwc_ep.xfer_len = retval;
19775 + ep->dwc_ep.xfer_count = 0;
19776 + ep->dwc_ep.sent_zlp = 0;
19777 + ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
19778 +
19779 + pcd->ep0_pending = 1;
19780 + dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
19781 + }
19782 + CFI_INFO("VEN_CORE_GET_FEATURE=%d\n", retval);
19783 + dump_msg(cfi->buf_in.buf, retval);
19784 + break;
19785 +
19786 + case VEN_CORE_SET_FEATURE:
19787 + CFI_INFO("VEN_CORE_SET_FEATURE\n");
19788 + /* Set up an XFER to get the data stage of the control request,
19789 + * which is the new value of the feature to be modified.
19790 + */
19791 + ep = &pcd->ep0;
19792 + ep->dwc_ep.is_in = 0;
19793 + ep->dwc_ep.dma_addr = cfi->buf_out.addr;
19794 + ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;
19795 + ep->dwc_ep.xfer_buff = cfi->buf_out.buf;
19796 + ep->dwc_ep.xfer_len = wLen;
19797 + ep->dwc_ep.xfer_count = 0;
19798 + ep->dwc_ep.sent_zlp = 0;
19799 + ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
19800 +
19801 + pcd->ep0_pending = 1;
19802 + /* Read the control write's data stage */
19803 + dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
19804 + retval = 0;
19805 + break;
19806 +
19807 + case VEN_CORE_RESET_FEATURES:
19808 + CFI_INFO("VEN_CORE_RESET_FEATURES\n");
19809 + cfi->need_gadget_att = 1;
19810 + cfi->need_status_in_complete = 1;
19811 + retval = cfi_preproc_reset(pcd, ctrl);
19812 + CFI_INFO("VEN_CORE_RESET_FEATURES = (%d)\n", retval);
19813 + break;
19814 +
19815 + case VEN_CORE_ACTIVATE_FEATURES:
19816 + CFI_INFO("VEN_CORE_ACTIVATE_FEATURES\n");
19817 + break;
19818 +
19819 + case VEN_CORE_READ_REGISTER:
19820 + CFI_INFO("VEN_CORE_READ_REGISTER\n");
19821 + /* wValue optionally contains the HI WORD of the register offset and
19822 + * wIndex contains the LOW WORD of the register offset
19823 + */
19824 + if (wValue == 0) {
19825 + /* @TODO - MAS - fix the access to the base field */
19826 + regaddr = 0;
19827 + //regaddr = (uint32_t) pcd->otg_dev->os_dep.base;
19828 + //GET_CORE_IF(pcd)->co
19829 + regaddr |= wIndex;
19830 + } else {
19831 + regaddr = (wValue << 16) | wIndex;
19832 + }
19833 +
19834 + /* Read a 32-bit value of the memory at the regaddr */
19835 + regval = DWC_READ_REG32((uint32_t *) regaddr);
19836 +
19837 + ep = &pcd->ep0;
19838 + dwc_memcpy(cfi->buf_in.buf, &regval, sizeof(uint32_t));
19839 + ep->dwc_ep.is_in = 1;
19840 + ep->dwc_ep.dma_addr = cfi->buf_in.addr;
19841 + ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
19842 + ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
19843 + ep->dwc_ep.xfer_len = wLen;
19844 + ep->dwc_ep.xfer_count = 0;
19845 + ep->dwc_ep.sent_zlp = 0;
19846 + ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
19847 +
19848 + pcd->ep0_pending = 1;
19849 + dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
19850 + cfi->need_gadget_att = 0;
19851 + retval = 0;
19852 + break;
19853 +
19854 + case VEN_CORE_WRITE_REGISTER:
19855 + CFI_INFO("VEN_CORE_WRITE_REGISTER\n");
19856 + /* Set up an XFER to get the data stage of the control request,
19857 + * which is the new value of the register to be modified.
19858 + */
19859 + ep = &pcd->ep0;
19860 + ep->dwc_ep.is_in = 0;
19861 + ep->dwc_ep.dma_addr = cfi->buf_out.addr;
19862 + ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;
19863 + ep->dwc_ep.xfer_buff = cfi->buf_out.buf;
19864 + ep->dwc_ep.xfer_len = wLen;
19865 + ep->dwc_ep.xfer_count = 0;
19866 + ep->dwc_ep.sent_zlp = 0;
19867 + ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
19868 +
19869 + pcd->ep0_pending = 1;
19870 + /* Read the control write's data stage */
19871 + dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
19872 + retval = 0;
19873 + break;
19874 +
19875 + default:
19876 + retval = -DWC_E_NOT_SUPPORTED;
19877 + break;
19878 + }
19879 +
19880 + return retval;
19881 +}
19882 +
19883 +/**
19884 + * This function prepares the core features descriptors and copies its
19885 + * raw representation into the buffer <buf>.
19886 + *
19887 + * The buffer structure is as follows:
19888 + * all_features_header (8 bytes)
19889 + * features_#1 (8 bytes + feature name string length)
19890 + * features_#2 (8 bytes + feature name string length)
19891 + * .....
19892 + * features_#n - where n=the total count of feature descriptors
19893 + */
19894 +static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen)
19895 +{
19896 + cfi_feature_desc_header_t *prop_hdr = prop_descs;
19897 + cfi_feature_desc_header_t *prop;
19898 + cfi_all_features_header_t *all_props_hdr = &all_props_desc_header;
19899 + cfi_all_features_header_t *tmp;
19900 + uint8_t *tmpbuf = buf;
19901 + const uint8_t *pname = NULL;
19902 + int i, j, namelen = 0, totlen;
19903 +
19904 + /* Prepare and copy the core features into the buffer */
19905 + CFI_INFO("%s:\n", __func__);
19906 +
19907 + tmp = (cfi_all_features_header_t *) tmpbuf;
19908 + *tmp = *all_props_hdr;
19909 + tmpbuf += CFI_ALL_FEATURES_HDR_LEN;
19910 +
19911 + j = sizeof(prop_descs) / sizeof(cfi_all_features_header_t);
19912 + for (i = 0; i < j; i++, prop_hdr++) {
19913 + pname = get_prop_name(prop_hdr->wFeatureID, &namelen);
19914 + prop = (cfi_feature_desc_header_t *) tmpbuf;
19915 + *prop = *prop_hdr;
19916 +
19917 + prop->bNameLen = namelen;
19918 + prop->wLength =
19919 + DWC_CONSTANT_CPU_TO_LE16(CFI_FEATURE_DESC_HDR_LEN +
19920 + namelen);
19921 +
19922 + tmpbuf += CFI_FEATURE_DESC_HDR_LEN;
19923 + dwc_memcpy(tmpbuf, pname, namelen);
19924 + tmpbuf += namelen;
19925 + }
19926 +
19927 + totlen = tmpbuf - buf;
19928 +
19929 + if (totlen > 0) {
19930 + tmp = (cfi_all_features_header_t *) buf;
19931 + tmp->wTotalLen = DWC_CONSTANT_CPU_TO_LE16(totlen);
19932 + }
19933 +
19934 + return totlen;
19935 +}
19936 +
19937 +/**
19938 + * This function releases all the dynamic memory in the CFI object.
19939 + */
19940 +static void cfi_release(cfiobject_t * cfiobj)
19941 +{
19942 + cfi_ep_t *cfiep;
19943 + dwc_list_link_t *tmp;
19944 +
19945 + CFI_INFO("%s\n", __func__);
19946 +
19947 + if (cfiobj->buf_in.buf) {
19948 + DWC_DMA_FREE(CFI_IN_BUF_LEN, cfiobj->buf_in.buf,
19949 + cfiobj->buf_in.addr);
19950 + cfiobj->buf_in.buf = NULL;
19951 + }
19952 +
19953 + if (cfiobj->buf_out.buf) {
19954 + DWC_DMA_FREE(CFI_OUT_BUF_LEN, cfiobj->buf_out.buf,
19955 + cfiobj->buf_out.addr);
19956 + cfiobj->buf_out.buf = NULL;
19957 + }
19958 +
19959 + /* Free the Buffer Setup values for each EP */
19960 + //list_for_each_entry(cfiep, &cfiobj->active_eps, lh) {
19961 + DWC_LIST_FOREACH(tmp, &cfiobj->active_eps) {
19962 + cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
19963 + cfi_free_ep_bs_dyn_data(cfiep);
19964 + }
19965 +}
19966 +
19967 +/**
19968 + * This function frees the dynamically allocated EP buffer setup data.
19969 + */
19970 +static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep)
19971 +{
19972 + if (cfiep->bm_sg) {
19973 + DWC_FREE(cfiep->bm_sg);
19974 + cfiep->bm_sg = NULL;
19975 + }
19976 +
19977 + if (cfiep->bm_align) {
19978 + DWC_FREE(cfiep->bm_align);
19979 + cfiep->bm_align = NULL;
19980 + }
19981 +
19982 + if (cfiep->bm_concat) {
19983 + if (NULL != cfiep->bm_concat->wTxBytes) {
19984 + DWC_FREE(cfiep->bm_concat->wTxBytes);
19985 + cfiep->bm_concat->wTxBytes = NULL;
19986 + }
19987 + DWC_FREE(cfiep->bm_concat);
19988 + cfiep->bm_concat = NULL;
19989 + }
19990 +}
19991 +
19992 +/**
19993 + * This function initializes the default values of the features
19994 + * for a specific endpoint and should be called only once when
19995 + * the EP is enabled first time.
19996 + */
19997 +static int cfi_ep_init_defaults(struct dwc_otg_pcd *pcd, cfi_ep_t * cfiep)
19998 +{
19999 + int retval = 0;
20000 +
20001 + cfiep->bm_sg = DWC_ALLOC(sizeof(ddma_sg_buffer_setup_t));
20002 + if (NULL == cfiep->bm_sg) {
20003 + CFI_INFO("Failed to allocate memory for SG feature value\n");
20004 + return -DWC_E_NO_MEMORY;
20005 + }
20006 + dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
20007 +
20008 + /* For the Concatenation feature's default value we do not allocate
20009 + * memory for the wTxBytes field - it will be done in the set_feature_value
20010 + * request handler.
20011 + */
20012 + cfiep->bm_concat = DWC_ALLOC(sizeof(ddma_concat_buffer_setup_t));
20013 + if (NULL == cfiep->bm_concat) {
20014 + CFI_INFO
20015 + ("Failed to allocate memory for CONCATENATION feature value\n");
20016 + DWC_FREE(cfiep->bm_sg);
20017 + return -DWC_E_NO_MEMORY;
20018 + }
20019 + dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));
20020 +
20021 + cfiep->bm_align = DWC_ALLOC(sizeof(ddma_align_buffer_setup_t));
20022 + if (NULL == cfiep->bm_align) {
20023 + CFI_INFO
20024 + ("Failed to allocate memory for Alignment feature value\n");
20025 + DWC_FREE(cfiep->bm_sg);
20026 + DWC_FREE(cfiep->bm_concat);
20027 + return -DWC_E_NO_MEMORY;
20028 + }
20029 + dwc_memset(cfiep->bm_align, 0, sizeof(ddma_align_buffer_setup_t));
20030 +
20031 + return retval;
20032 +}
20033 +
20034 +/**
20035 + * The callback function that notifies the CFI on the activation of
20036 + * an endpoint in the PCD. The following steps are done in this function:
20037 + *
20038 + * Create a dynamically allocated cfi_ep_t object (a CFI wrapper to the PCD's
20039 + * active endpoint)
20040 + * Create MAX_DMA_DESCS_PER_EP count DMA Descriptors for the EP
20041 + * Set the Buffer Mode to standard
20042 + * Initialize the default values for all EP modes (SG, Circular, Concat, Align)
20043 + * Add the cfi_ep_t object to the list of active endpoints in the CFI object
20044 + */
20045 +static int cfi_ep_enable(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,
20046 + struct dwc_otg_pcd_ep *ep)
20047 +{
20048 + cfi_ep_t *cfiep;
20049 + int retval = -DWC_E_NOT_SUPPORTED;
20050 +
20051 + CFI_INFO("%s: epname=%s; epnum=0x%02x\n", __func__,
20052 + "EP_" /*ep->ep.name */ , ep->desc->bEndpointAddress);
20053 + /* MAS - Check whether this endpoint already is in the list */
20054 + cfiep = get_cfi_ep_by_pcd_ep(cfi, ep);
20055 +
20056 + if (NULL == cfiep) {
20057 + /* Allocate a cfi_ep_t object */
20058 + cfiep = DWC_ALLOC(sizeof(cfi_ep_t));
20059 + if (NULL == cfiep) {
20060 + CFI_INFO
20061 + ("Unable to allocate memory for <cfiep> in function %s\n",
20062 + __func__);
20063 + return -DWC_E_NO_MEMORY;
20064 + }
20065 + dwc_memset(cfiep, 0, sizeof(cfi_ep_t));
20066 +
20067 + /* Save the dwc_otg_pcd_ep pointer in the cfiep object */
20068 + cfiep->ep = ep;
20069 +
20070 + /* Allocate the DMA Descriptors chain of MAX_DMA_DESCS_PER_EP count */
20071 + ep->dwc_ep.descs =
20072 + DWC_DMA_ALLOC(MAX_DMA_DESCS_PER_EP *
20073 + sizeof(dwc_otg_dma_desc_t),
20074 + &ep->dwc_ep.descs_dma_addr);
20075 +
20076 + if (NULL == ep->dwc_ep.descs) {
20077 + DWC_FREE(cfiep);
20078 + return -DWC_E_NO_MEMORY;
20079 + }
20080 +
20081 + DWC_LIST_INIT(&cfiep->lh);
20082 +
20083 + /* Set the buffer mode to BM_STANDARD. It will be modified
20084 + * when building descriptors for a specific buffer mode */
20085 + ep->dwc_ep.buff_mode = BM_STANDARD;
20086 +
20087 + /* Create and initialize the default values for this EP's Buffer modes */
20088 + if ((retval = cfi_ep_init_defaults(pcd, cfiep)) < 0)
20089 + return retval;
20090 +
20091 + /* Add the cfi_ep_t object to the CFI object's list of active endpoints */
20092 + DWC_LIST_INSERT_TAIL(&cfi->active_eps, &cfiep->lh);
20093 + retval = 0;
20094 + } else { /* The sought EP already is in the list */
20095 + CFI_INFO("%s: The sought EP already is in the list\n",
20096 + __func__);
20097 + }
20098 +
20099 + return retval;
20100 +}
20101 +
20102 +/**
20103 + * This function is called when the data stage of a 3-stage Control Write request
20104 + * is complete.
20105 + *
20106 + */
20107 +static int cfi_ctrl_write_complete(struct cfiobject *cfi,
20108 + struct dwc_otg_pcd *pcd)
20109 +{
20110 + uint32_t addr, reg_value;
20111 + uint16_t wIndex, wValue;
20112 + uint8_t bRequest;
20113 + uint8_t *buf = cfi->buf_out.buf;
20114 + //struct usb_ctrlrequest *ctrl_req = &cfi->ctrl_req_saved;
20115 + struct cfi_usb_ctrlrequest *ctrl_req = &cfi->ctrl_req;
20116 + int retval = -DWC_E_NOT_SUPPORTED;
20117 +
20118 + CFI_INFO("%s\n", __func__);
20119 +
20120 + bRequest = ctrl_req->bRequest;
20121 + wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);
20122 + wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);
20123 +
20124 + /*
20125 + * Save the pointer to the data stage in the ctrl_req's <data> field.
20126 + * The request should be already saved in the command stage by now.
20127 + */
20128 + ctrl_req->data = cfi->buf_out.buf;
20129 + cfi->need_status_in_complete = 0;
20130 + cfi->need_gadget_att = 0;
20131 +
20132 + switch (bRequest) {
20133 + case VEN_CORE_WRITE_REGISTER:
20134 + /* The buffer contains raw data of the new value for the register */
20135 + reg_value = *((uint32_t *) buf);
20136 + if (wValue == 0) {
20137 + addr = 0;
20138 + //addr = (uint32_t) pcd->otg_dev->os_dep.base;
20139 + addr += wIndex;
20140 + } else {
20141 + addr = (wValue << 16) | wIndex;
20142 + }
20143 +
20144 + //writel(reg_value, addr);
20145 +
20146 + retval = 0;
20147 + cfi->need_status_in_complete = 1;
20148 + break;
20149 +
20150 + case VEN_CORE_SET_FEATURE:
20151 + /* The buffer contains raw data of the new value of the feature */
20152 + retval = cfi_set_feature_value(pcd);
20153 + if (retval < 0)
20154 + return retval;
20155 +
20156 + cfi->need_status_in_complete = 1;
20157 + break;
20158 +
20159 + default:
20160 + break;
20161 + }
20162 +
20163 + return retval;
20164 +}
20165 +
20166 +/**
20167 + * This function builds the DMA descriptors for the SG buffer mode.
20168 + */
20169 +static void cfi_build_sg_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
20170 + dwc_otg_pcd_request_t * req)
20171 +{
20172 + struct dwc_otg_pcd_ep *ep = cfiep->ep;
20173 + ddma_sg_buffer_setup_t *sgval = cfiep->bm_sg;
20174 + struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
20175 + struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;
20176 + dma_addr_t buff_addr = req->dma;
20177 + int i;
20178 + uint32_t txsize, off;
20179 +
20180 + txsize = sgval->wSize;
20181 + off = sgval->bOffset;
20182 +
20183 +// CFI_INFO("%s: %s TXSIZE=0x%08x; OFFSET=0x%08x\n",
20184 +// __func__, cfiep->ep->ep.name, txsize, off);
20185 +
20186 + for (i = 0; i < sgval->bCount; i++) {
20187 + desc->status.b.bs = BS_HOST_BUSY;
20188 + desc->buf = buff_addr;
20189 + desc->status.b.l = 0;
20190 + desc->status.b.ioc = 0;
20191 + desc->status.b.sp = 0;
20192 + desc->status.b.bytes = txsize;
20193 + desc->status.b.bs = BS_HOST_READY;
20194 +
20195 + /* Set the next address of the buffer */
20196 + buff_addr += txsize + off;
20197 + desc_last = desc;
20198 + desc++;
20199 + }
20200 +
20201 + /* Set the last, ioc and sp bits on the Last DMA Descriptor */
20202 + desc_last->status.b.l = 1;
20203 + desc_last->status.b.ioc = 1;
20204 + desc_last->status.b.sp = ep->dwc_ep.sent_zlp;
20205 + /* Save the last DMA descriptor pointer */
20206 + cfiep->dma_desc_last = desc_last;
20207 + cfiep->desc_count = sgval->bCount;
20208 +}
20209 +
20210 +/**
20211 + * This function builds the DMA descriptors for the Concatenation buffer mode.
20212 + */
20213 +static void cfi_build_concat_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
20214 + dwc_otg_pcd_request_t * req)
20215 +{
20216 + struct dwc_otg_pcd_ep *ep = cfiep->ep;
20217 + ddma_concat_buffer_setup_t *concatval = cfiep->bm_concat;
20218 + struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
20219 + struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;
20220 + dma_addr_t buff_addr = req->dma;
20221 + int i;
20222 + uint16_t *txsize;
20223 +
20224 + txsize = concatval->wTxBytes;
20225 +
20226 + for (i = 0; i < concatval->hdr.bDescCount; i++) {
20227 + desc->buf = buff_addr;
20228 + desc->status.b.bs = BS_HOST_BUSY;
20229 + desc->status.b.l = 0;
20230 + desc->status.b.ioc = 0;
20231 + desc->status.b.sp = 0;
20232 + desc->status.b.bytes = *txsize;
20233 + desc->status.b.bs = BS_HOST_READY;
20234 +
20235 + txsize++;
20236 + /* Set the next address of the buffer */
20237 + buff_addr += UGETW(ep->desc->wMaxPacketSize);
20238 + desc_last = desc;
20239 + desc++;
20240 + }
20241 +
20242 + /* Set the last, ioc and sp bits on the Last DMA Descriptor */
20243 + desc_last->status.b.l = 1;
20244 + desc_last->status.b.ioc = 1;
20245 + desc_last->status.b.sp = ep->dwc_ep.sent_zlp;
20246 + cfiep->dma_desc_last = desc_last;
20247 + cfiep->desc_count = concatval->hdr.bDescCount;
20248 +}
20249 +
20250 +/**
20251 + * This function builds the DMA descriptors for the Circular buffer mode
20252 + */
20253 +static void cfi_build_circ_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
20254 + dwc_otg_pcd_request_t * req)
20255 +{
20256 + /* @todo: MAS - add implementation when this feature needs to be tested */
20257 +}
20258 +
20259 +/**
20260 + * This function builds the DMA descriptors for the Alignment buffer mode
20261 + */
20262 +static void cfi_build_align_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
20263 + dwc_otg_pcd_request_t * req)
20264 +{
20265 + struct dwc_otg_pcd_ep *ep = cfiep->ep;
20266 + ddma_align_buffer_setup_t *alignval = cfiep->bm_align;
20267 + struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
20268 + dma_addr_t buff_addr = req->dma;
20269 +
20270 + desc->status.b.bs = BS_HOST_BUSY;
20271 + desc->status.b.l = 1;
20272 + desc->status.b.ioc = 1;
20273 + desc->status.b.sp = ep->dwc_ep.sent_zlp;
20274 + desc->status.b.bytes = req->length;
20275 + /* Adjust the buffer alignment */
20276 + desc->buf = (buff_addr + alignval->bAlign);
20277 + desc->status.b.bs = BS_HOST_READY;
20278 + cfiep->dma_desc_last = desc;
20279 + cfiep->desc_count = 1;
20280 +}
20281 +
20282 +/**
20283 + * This function builds the DMA descriptors chain for different modes of the
20284 + * buffer setup of an endpoint.
20285 + */
20286 +static void cfi_build_descriptors(struct cfiobject *cfi,
20287 + struct dwc_otg_pcd *pcd,
20288 + struct dwc_otg_pcd_ep *ep,
20289 + dwc_otg_pcd_request_t * req)
20290 +{
20291 + cfi_ep_t *cfiep;
20292 +
20293 + /* Get the cfiep by the dwc_otg_pcd_ep */
20294 + cfiep = get_cfi_ep_by_pcd_ep(cfi, ep);
20295 + if (NULL == cfiep) {
20296 + CFI_INFO("%s: Unable to find a matching active endpoint\n",
20297 + __func__);
20298 + return;
20299 + }
20300 +
20301 + cfiep->xfer_len = req->length;
20302 +
20303 + /* Iterate through all the DMA descriptors */
20304 + switch (cfiep->ep->dwc_ep.buff_mode) {
20305 + case BM_SG:
20306 + cfi_build_sg_descs(cfi, cfiep, req);
20307 + break;
20308 +
20309 + case BM_CONCAT:
20310 + cfi_build_concat_descs(cfi, cfiep, req);
20311 + break;
20312 +
20313 + case BM_CIRCULAR:
20314 + cfi_build_circ_descs(cfi, cfiep, req);
20315 + break;
20316 +
20317 + case BM_ALIGN:
20318 + cfi_build_align_descs(cfi, cfiep, req);
20319 + break;
20320 +
20321 + default:
20322 + break;
20323 + }
20324 +}
20325 +
20326 +/**
20327 + * Allocate DMA buffer for different Buffer modes.
20328 + */
20329 +static void *cfi_ep_alloc_buf(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,
20330 + struct dwc_otg_pcd_ep *ep, dma_addr_t * dma,
20331 + unsigned size, gfp_t flags)
20332 +{
20333 + return DWC_DMA_ALLOC(size, dma);
20334 +}
20335 +
20336 +/**
20337 + * This function initializes the CFI object.
20338 + */
20339 +int init_cfi(cfiobject_t * cfiobj)
20340 +{
20341 + CFI_INFO("%s\n", __func__);
20342 +
20343 + /* Allocate a buffer for IN XFERs */
20344 + cfiobj->buf_in.buf =
20345 + DWC_DMA_ALLOC(CFI_IN_BUF_LEN, &cfiobj->buf_in.addr);
20346 + if (NULL == cfiobj->buf_in.buf) {
20347 + CFI_INFO("Unable to allocate buffer for INs\n");
20348 + return -DWC_E_NO_MEMORY;
20349 + }
20350 +
20351 + /* Allocate a buffer for OUT XFERs */
20352 + cfiobj->buf_out.buf =
20353 + DWC_DMA_ALLOC(CFI_OUT_BUF_LEN, &cfiobj->buf_out.addr);
20354 + if (NULL == cfiobj->buf_out.buf) {
20355 + CFI_INFO("Unable to allocate buffer for OUT\n");
20356 + return -DWC_E_NO_MEMORY;
20357 + }
20358 +
20359 + /* Initialize the callback function pointers */
20360 + cfiobj->ops.release = cfi_release;
20361 + cfiobj->ops.ep_enable = cfi_ep_enable;
20362 + cfiobj->ops.ctrl_write_complete = cfi_ctrl_write_complete;
20363 + cfiobj->ops.build_descriptors = cfi_build_descriptors;
20364 + cfiobj->ops.ep_alloc_buf = cfi_ep_alloc_buf;
20365 +
20366 + /* Initialize the list of active endpoints in the CFI object */
20367 + DWC_LIST_INIT(&cfiobj->active_eps);
20368 +
20369 + return 0;
20370 +}
20371 +
20372 +/**
20373 + * This function reads the required feature's current value into the buffer
20374 + *
20375 + * @retval: Returns negative as error, or the data length of the feature
20376 + */
20377 +static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
20378 + struct dwc_otg_pcd *pcd,
20379 + struct cfi_usb_ctrlrequest *ctrl_req)
20380 +{
20381 + int retval = -DWC_E_NOT_SUPPORTED;
20382 + struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);
20383 + uint16_t dfifo, rxfifo, txfifo;
20384 +
20385 + switch (ctrl_req->wIndex) {
20386 + /* Whether the DDMA is enabled or not */
20387 + case FT_ID_DMA_MODE:
20388 + *buf = (coreif->dma_enable && coreif->dma_desc_enable) ? 1 : 0;
20389 + retval = 1;
20390 + break;
20391 +
20392 + case FT_ID_DMA_BUFFER_SETUP:
20393 + retval = cfi_ep_get_sg_val(buf, pcd, ctrl_req);
20394 + break;
20395 +
20396 + case FT_ID_DMA_BUFF_ALIGN:
20397 + retval = cfi_ep_get_align_val(buf, pcd, ctrl_req);
20398 + break;
20399 +
20400 + case FT_ID_DMA_CONCAT_SETUP:
20401 + retval = cfi_ep_get_concat_val(buf, pcd, ctrl_req);
20402 + break;
20403 +
20404 + case FT_ID_DMA_CIRCULAR:
20405 + CFI_INFO("GetFeature value (FT_ID_DMA_CIRCULAR)\n");
20406 + break;
20407 +
20408 + case FT_ID_THRESHOLD_SETUP:
20409 + CFI_INFO("GetFeature value (FT_ID_THRESHOLD_SETUP)\n");
20410 + break;
20411 +
20412 + case FT_ID_DFIFO_DEPTH:
20413 + dfifo = get_dfifo_size(coreif);
20414 + *((uint16_t *) buf) = dfifo;
20415 + retval = sizeof(uint16_t);
20416 + break;
20417 +
20418 + case FT_ID_TX_FIFO_DEPTH:
20419 + retval = get_txfifo_size(pcd, ctrl_req->wValue);
20420 + if (retval >= 0) {
20421 + txfifo = retval;
20422 + *((uint16_t *) buf) = txfifo;
20423 + retval = sizeof(uint16_t);
20424 + }
20425 + break;
20426 +
20427 + case FT_ID_RX_FIFO_DEPTH:
20428 + retval = get_rxfifo_size(coreif, ctrl_req->wValue);
20429 + if (retval >= 0) {
20430 + rxfifo = retval;
20431 + *((uint16_t *) buf) = rxfifo;
20432 + retval = sizeof(uint16_t);
20433 + }
20434 + break;
20435 + }
20436 +
20437 + return retval;
20438 +}
20439 +
20440 +/**
20441 + * This function resets the SG for the specified EP to its default value
20442 + */
20443 +static int cfi_reset_sg_val(cfi_ep_t * cfiep)
20444 +{
20445 + dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
20446 + return 0;
20447 +}
20448 +
20449 +/**
20450 + * This function resets the Alignment for the specified EP to its default value
20451 + */
20452 +static int cfi_reset_align_val(cfi_ep_t * cfiep)
20453 +{
20454 + dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
20455 + return 0;
20456 +}
20457 +
20458 +/**
20459 + * This function resets the Concatenation for the specified EP to its default value
20460 + * This function will also set the value of the wTxBytes field to NULL after
20461 + * freeing the memory previously allocated for this field.
20462 + */
20463 +static int cfi_reset_concat_val(cfi_ep_t * cfiep)
20464 +{
20465 + /* First we need to free the wTxBytes field */
20466 + if (cfiep->bm_concat->wTxBytes) {
20467 + DWC_FREE(cfiep->bm_concat->wTxBytes);
20468 + cfiep->bm_concat->wTxBytes = NULL;
20469 + }
20470 +
20471 + dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));
20472 + return 0;
20473 +}
20474 +
20475 +/**
20476 + * This function resets all the buffer setups of the specified endpoint
20477 + */
20478 +static int cfi_ep_reset_all_setup_vals(cfi_ep_t * cfiep)
20479 +{
20480 + cfi_reset_sg_val(cfiep);
20481 + cfi_reset_align_val(cfiep);
20482 + cfi_reset_concat_val(cfiep);
20483 + return 0;
20484 +}
20485 +
20486 +static int cfi_handle_reset_fifo_val(struct dwc_otg_pcd *pcd, uint8_t ep_addr,
20487 + uint8_t rx_rst, uint8_t tx_rst)
20488 +{
20489 + int retval = -DWC_E_INVALID;
20490 + uint16_t tx_siz[15];
20491 + uint16_t rx_siz = 0;
20492 + dwc_otg_pcd_ep_t *ep = NULL;
20493 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
20494 + dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
20495 +
20496 + if (rx_rst) {
20497 + rx_siz = params->dev_rx_fifo_size;
20498 + params->dev_rx_fifo_size = GET_CORE_IF(pcd)->init_rxfsiz;
20499 + }
20500 +
20501 + if (tx_rst) {
20502 + if (ep_addr == 0) {
20503 + int i;
20504 +
20505 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
20506 + tx_siz[i] =
20507 + core_if->core_params->dev_tx_fifo_size[i];
20508 + core_if->core_params->dev_tx_fifo_size[i] =
20509 + core_if->init_txfsiz[i];
20510 + }
20511 + } else {
20512 +
20513 + ep = get_ep_by_addr(pcd, ep_addr);
20514 +
20515 + if (NULL == ep) {
20516 + CFI_INFO
20517 + ("%s: Unable to get the endpoint addr=0x%02x\n",
20518 + __func__, ep_addr);
20519 + return -DWC_E_INVALID;
20520 + }
20521 +
20522 + tx_siz[0] =
20523 + params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num -
20524 + 1];
20525 + params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] =
20526 + GET_CORE_IF(pcd)->init_txfsiz[ep->
20527 + dwc_ep.tx_fifo_num -
20528 + 1];
20529 + }
20530 + }
20531 +
20532 + if (resize_fifos(GET_CORE_IF(pcd))) {
20533 + retval = 0;
20534 + } else {
20535 + CFI_INFO
20536 + ("%s: Error resetting the feature Reset All(FIFO size)\n",
20537 + __func__);
20538 + if (rx_rst) {
20539 + params->dev_rx_fifo_size = rx_siz;
20540 + }
20541 +
20542 + if (tx_rst) {
20543 + if (ep_addr == 0) {
20544 + int i;
20545 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps;
20546 + i++) {
20547 + core_if->
20548 + core_params->dev_tx_fifo_size[i] =
20549 + tx_siz[i];
20550 + }
20551 + } else {
20552 + params->dev_tx_fifo_size[ep->
20553 + dwc_ep.tx_fifo_num -
20554 + 1] = tx_siz[0];
20555 + }
20556 + }
20557 + retval = -DWC_E_INVALID;
20558 + }
20559 + return retval;
20560 +}
20561 +
20562 +static int cfi_handle_reset_all(struct dwc_otg_pcd *pcd, uint8_t addr)
20563 +{
20564 + int retval = 0;
20565 + cfi_ep_t *cfiep;
20566 + cfiobject_t *cfi = pcd->cfi;
20567 + dwc_list_link_t *tmp;
20568 +
20569 + retval = cfi_handle_reset_fifo_val(pcd, addr, 1, 1);
20570 + if (retval < 0) {
20571 + return retval;
20572 + }
20573 +
20574 + /* If the EP address is known then reset the features for only that EP */
20575 + if (addr) {
20576 + cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
20577 + if (NULL == cfiep) {
20578 + CFI_INFO("%s: Error getting the EP address 0x%02x\n",
20579 + __func__, addr);
20580 + return -DWC_E_INVALID;
20581 + }
20582 + retval = cfi_ep_reset_all_setup_vals(cfiep);
20583 + cfiep->ep->dwc_ep.buff_mode = BM_STANDARD;
20584 + }
20585 + /* Otherwise (wValue == 0), reset all features of all EP's */
20586 + else {
20587 + /* Traverse all the active EP's and reset the feature(s) value(s) */
20588 + //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
20589 + DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
20590 + cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
20591 + retval = cfi_ep_reset_all_setup_vals(cfiep);
20592 + cfiep->ep->dwc_ep.buff_mode = BM_STANDARD;
20593 + if (retval < 0) {
20594 + CFI_INFO
20595 + ("%s: Error resetting the feature Reset All\n",
20596 + __func__);
20597 + return retval;
20598 + }
20599 + }
20600 + }
20601 + return retval;
20602 +}
20603 +
20604 +static int cfi_handle_reset_dma_buff_setup(struct dwc_otg_pcd *pcd,
20605 + uint8_t addr)
20606 +{
20607 + int retval = 0;
20608 + cfi_ep_t *cfiep;
20609 + cfiobject_t *cfi = pcd->cfi;
20610 + dwc_list_link_t *tmp;
20611 +
20612 + /* If the EP address is known then reset the features for only that EP */
20613 + if (addr) {
20614 + cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
20615 + if (NULL == cfiep) {
20616 + CFI_INFO("%s: Error getting the EP address 0x%02x\n",
20617 + __func__, addr);
20618 + return -DWC_E_INVALID;
20619 + }
20620 + retval = cfi_reset_sg_val(cfiep);
20621 + }
20622 + /* Otherwise (wValue == 0), reset all features of all EP's */
20623 + else {
20624 + /* Traverse all the active EP's and reset the feature(s) value(s) */
20625 + //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
20626 + DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
20627 + cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
20628 + retval = cfi_reset_sg_val(cfiep);
20629 + if (retval < 0) {
20630 + CFI_INFO
20631 + ("%s: Error resetting the feature Buffer Setup\n",
20632 + __func__);
20633 + return retval;
20634 + }
20635 + }
20636 + }
20637 + return retval;
20638 +}
20639 +
20640 +static int cfi_handle_reset_concat_val(struct dwc_otg_pcd *pcd, uint8_t addr)
20641 +{
20642 + int retval = 0;
20643 + cfi_ep_t *cfiep;
20644 + cfiobject_t *cfi = pcd->cfi;
20645 + dwc_list_link_t *tmp;
20646 +
20647 + /* If the EP address is known then reset the features for only that EP */
20648 + if (addr) {
20649 + cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
20650 + if (NULL == cfiep) {
20651 + CFI_INFO("%s: Error getting the EP address 0x%02x\n",
20652 + __func__, addr);
20653 + return -DWC_E_INVALID;
20654 + }
20655 + retval = cfi_reset_concat_val(cfiep);
20656 + }
20657 + /* Otherwise (wValue == 0), reset all features of all EP's */
20658 + else {
20659 + /* Traverse all the active EP's and reset the feature(s) value(s) */
20660 + //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
20661 + DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
20662 + cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
20663 + retval = cfi_reset_concat_val(cfiep);
20664 + if (retval < 0) {
20665 + CFI_INFO
20666 + ("%s: Error resetting the feature Concatenation Value\n",
20667 + __func__);
20668 + return retval;
20669 + }
20670 + }
20671 + }
20672 + return retval;
20673 +}
20674 +
20675 +static int cfi_handle_reset_align_val(struct dwc_otg_pcd *pcd, uint8_t addr)
20676 +{
20677 + int retval = 0;
20678 + cfi_ep_t *cfiep;
20679 + cfiobject_t *cfi = pcd->cfi;
20680 + dwc_list_link_t *tmp;
20681 +
20682 + /* If the EP address is known then reset the features for only that EP */
20683 + if (addr) {
20684 + cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
20685 + if (NULL == cfiep) {
20686 + CFI_INFO("%s: Error getting the EP address 0x%02x\n",
20687 + __func__, addr);
20688 + return -DWC_E_INVALID;
20689 + }
20690 + retval = cfi_reset_align_val(cfiep);
20691 + }
20692 + /* Otherwise (wValue == 0), reset all features of all EP's */
20693 + else {
20694 + /* Traverse all the active EP's and reset the feature(s) value(s) */
20695 + //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
20696 + DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
20697 + cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
20698 + retval = cfi_reset_align_val(cfiep);
20699 + if (retval < 0) {
20700 + CFI_INFO
20701 + ("%s: Error resetting the feature Aliignment Value\n",
20702 + __func__);
20703 + return retval;
20704 + }
20705 + }
20706 + }
20707 + return retval;
20708 +
20709 +}
20710 +
20711 +static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,
20712 + struct cfi_usb_ctrlrequest *req)
20713 +{
20714 + int retval = 0;
20715 +
20716 + switch (req->wIndex) {
20717 + case 0:
20718 + /* Reset all features */
20719 + retval = cfi_handle_reset_all(pcd, req->wValue & 0xff);
20720 + break;
20721 +
20722 + case FT_ID_DMA_BUFFER_SETUP:
20723 + /* Reset the SG buffer setup */
20724 + retval =
20725 + cfi_handle_reset_dma_buff_setup(pcd, req->wValue & 0xff);
20726 + break;
20727 +
20728 + case FT_ID_DMA_CONCAT_SETUP:
20729 + /* Reset the Concatenation buffer setup */
20730 + retval = cfi_handle_reset_concat_val(pcd, req->wValue & 0xff);
20731 + break;
20732 +
20733 + case FT_ID_DMA_BUFF_ALIGN:
20734 + /* Reset the Alignment buffer setup */
20735 + retval = cfi_handle_reset_align_val(pcd, req->wValue & 0xff);
20736 + break;
20737 +
20738 + case FT_ID_TX_FIFO_DEPTH:
20739 + retval =
20740 + cfi_handle_reset_fifo_val(pcd, req->wValue & 0xff, 0, 1);
20741 + pcd->cfi->need_gadget_att = 0;
20742 + break;
20743 +
20744 + case FT_ID_RX_FIFO_DEPTH:
20745 + retval = cfi_handle_reset_fifo_val(pcd, 0, 1, 0);
20746 + pcd->cfi->need_gadget_att = 0;
20747 + break;
20748 + default:
20749 + break;
20750 + }
20751 + return retval;
20752 +}
20753 +
20754 +/**
20755 + * This function sets a new value for the SG buffer setup.
20756 + */
20757 +static int cfi_ep_set_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
20758 +{
20759 + uint8_t inaddr, outaddr;
20760 + cfi_ep_t *epin, *epout;
20761 + ddma_sg_buffer_setup_t *psgval;
20762 + uint32_t desccount, size;
20763 +
20764 + CFI_INFO("%s\n", __func__);
20765 +
20766 + psgval = (ddma_sg_buffer_setup_t *) buf;
20767 + desccount = (uint32_t) psgval->bCount;
20768 + size = (uint32_t) psgval->wSize;
20769 +
20770 + /* Check the DMA descriptor count */
20771 + if ((desccount > MAX_DMA_DESCS_PER_EP) || (desccount == 0)) {
20772 + CFI_INFO
20773 + ("%s: The count of DMA Descriptors should be between 1 and %d\n",
20774 + __func__, MAX_DMA_DESCS_PER_EP);
20775 + return -DWC_E_INVALID;
20776 + }
20777 +
20778 + /* Check the DMA descriptor count */
20779 +
20780 + if (size == 0) {
20781 +
20782 + CFI_INFO("%s: The transfer size should be at least 1 byte\n",
20783 + __func__);
20784 +
20785 + return -DWC_E_INVALID;
20786 +
20787 + }
20788 +
20789 + inaddr = psgval->bInEndpointAddress;
20790 + outaddr = psgval->bOutEndpointAddress;
20791 +
20792 + epin = get_cfi_ep_by_addr(pcd->cfi, inaddr);
20793 + epout = get_cfi_ep_by_addr(pcd->cfi, outaddr);
20794 +
20795 + if (NULL == epin || NULL == epout) {
20796 + CFI_INFO
20797 + ("%s: Unable to get the endpoints inaddr=0x%02x outaddr=0x%02x\n",
20798 + __func__, inaddr, outaddr);
20799 + return -DWC_E_INVALID;
20800 + }
20801 +
20802 + epin->ep->dwc_ep.buff_mode = BM_SG;
20803 + dwc_memcpy(epin->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));
20804 +
20805 + epout->ep->dwc_ep.buff_mode = BM_SG;
20806 + dwc_memcpy(epout->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));
20807 +
20808 + return 0;
20809 +}
20810 +
20811 +/**
20812 + * This function sets a new value for the buffer Alignment setup.
20813 + */
20814 +static int cfi_ep_set_alignment_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
20815 +{
20816 + cfi_ep_t *ep;
20817 + uint8_t addr;
20818 + ddma_align_buffer_setup_t *palignval;
20819 +
20820 + palignval = (ddma_align_buffer_setup_t *) buf;
20821 + addr = palignval->bEndpointAddress;
20822 +
20823 + ep = get_cfi_ep_by_addr(pcd->cfi, addr);
20824 +
20825 + if (NULL == ep) {
20826 + CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
20827 + __func__, addr);
20828 + return -DWC_E_INVALID;
20829 + }
20830 +
20831 + ep->ep->dwc_ep.buff_mode = BM_ALIGN;
20832 + dwc_memcpy(ep->bm_align, palignval, sizeof(ddma_align_buffer_setup_t));
20833 +
20834 + return 0;
20835 +}
20836 +
20837 +/**
20838 + * This function sets a new value for the Concatenation buffer setup.
20839 + */
20840 +static int cfi_ep_set_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
20841 +{
20842 + uint8_t addr;
20843 + cfi_ep_t *ep;
20844 + struct _ddma_concat_buffer_setup_hdr *pConcatValHdr;
20845 + uint16_t *pVals;
20846 + uint32_t desccount;
20847 + int i;
20848 + uint16_t mps;
20849 +
20850 + pConcatValHdr = (struct _ddma_concat_buffer_setup_hdr *)buf;
20851 + desccount = (uint32_t) pConcatValHdr->bDescCount;
20852 + pVals = (uint16_t *) (buf + BS_CONCAT_VAL_HDR_LEN);
20853 +
20854 + /* Check the DMA descriptor count */
20855 + if (desccount > MAX_DMA_DESCS_PER_EP) {
20856 + CFI_INFO("%s: Maximum DMA Descriptor count should be %d\n",
20857 + __func__, MAX_DMA_DESCS_PER_EP);
20858 + return -DWC_E_INVALID;
20859 + }
20860 +
20861 + addr = pConcatValHdr->bEndpointAddress;
20862 + ep = get_cfi_ep_by_addr(pcd->cfi, addr);
20863 + if (NULL == ep) {
20864 + CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
20865 + __func__, addr);
20866 + return -DWC_E_INVALID;
20867 + }
20868 +
20869 + mps = UGETW(ep->ep->desc->wMaxPacketSize);
20870 +
20871 +#if 0
20872 + for (i = 0; i < desccount; i++) {
20873 + CFI_INFO("%s: wTxSize[%d]=0x%04x\n", __func__, i, pVals[i]);
20874 + }
20875 + CFI_INFO("%s: epname=%s; mps=%d\n", __func__, ep->ep->ep.name, mps);
20876 +#endif
20877 +
20878 + /* Check the wTxSizes to be less than or equal to the mps */
20879 + for (i = 0; i < desccount; i++) {
20880 + if (pVals[i] > mps) {
20881 + CFI_INFO
20882 + ("%s: ERROR - the wTxSize[%d] should be <= MPS (wTxSize=%d)\n",
20883 + __func__, i, pVals[i]);
20884 + return -DWC_E_INVALID;
20885 + }
20886 + }
20887 +
20888 + ep->ep->dwc_ep.buff_mode = BM_CONCAT;
20889 + dwc_memcpy(ep->bm_concat, pConcatValHdr, BS_CONCAT_VAL_HDR_LEN);
20890 +
20891 + /* Free the previously allocated storage for the wTxBytes */
20892 + if (ep->bm_concat->wTxBytes) {
20893 + DWC_FREE(ep->bm_concat->wTxBytes);
20894 + }
20895 +
20896 + /* Allocate a new storage for the wTxBytes field */
20897 + ep->bm_concat->wTxBytes =
20898 + DWC_ALLOC(sizeof(uint16_t) * pConcatValHdr->bDescCount);
20899 + if (NULL == ep->bm_concat->wTxBytes) {
20900 + CFI_INFO("%s: Unable to allocate memory\n", __func__);
20901 + return -DWC_E_NO_MEMORY;
20902 + }
20903 +
20904 + /* Copy the new values into the wTxBytes filed */
20905 + dwc_memcpy(ep->bm_concat->wTxBytes, buf + BS_CONCAT_VAL_HDR_LEN,
20906 + sizeof(uint16_t) * pConcatValHdr->bDescCount);
20907 +
20908 + return 0;
20909 +}
20910 +
20911 +/**
20912 + * This function calculates the total of all FIFO sizes
20913 + *
20914 + * @param core_if Programming view of DWC_otg controller
20915 + *
20916 + * @return The total of data FIFO sizes.
20917 + *
20918 + */
20919 +static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if)
20920 +{
20921 + dwc_otg_core_params_t *params = core_if->core_params;
20922 + uint16_t dfifo_total = 0;
20923 + int i;
20924 +
20925 + /* The shared RxFIFO size */
20926 + dfifo_total =
20927 + params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;
20928 +
20929 + /* Add up each TxFIFO size to the total */
20930 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
20931 + dfifo_total += params->dev_tx_fifo_size[i];
20932 + }
20933 +
20934 + return dfifo_total;
20935 +}
20936 +
20937 +/**
20938 + * This function returns Rx FIFO size
20939 + *
20940 + * @param core_if Programming view of DWC_otg controller
20941 + *
20942 + * @return The total of data FIFO sizes.
20943 + *
20944 + */
20945 +static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue)
20946 +{
20947 + switch (wValue >> 8) {
20948 + case 0:
20949 + return (core_if->pwron_rxfsiz <
20950 + 32768) ? core_if->pwron_rxfsiz : 32768;
20951 + break;
20952 + case 1:
20953 + return core_if->core_params->dev_rx_fifo_size;
20954 + break;
20955 + default:
20956 + return -DWC_E_INVALID;
20957 + break;
20958 + }
20959 +}
20960 +
20961 +/**
20962 + * This function returns Tx FIFO size for IN EP
20963 + *
20964 + * @param core_if Programming view of DWC_otg controller
20965 + *
20966 + * @return The total of data FIFO sizes.
20967 + *
20968 + */
20969 +static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue)
20970 +{
20971 + dwc_otg_pcd_ep_t *ep;
20972 +
20973 + ep = get_ep_by_addr(pcd, wValue & 0xff);
20974 +
20975 + if (NULL == ep) {
20976 + CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
20977 + __func__, wValue & 0xff);
20978 + return -DWC_E_INVALID;
20979 + }
20980 +
20981 + if (!ep->dwc_ep.is_in) {
20982 + CFI_INFO
20983 + ("%s: No Tx FIFO assingned to the Out endpoint addr=0x%02x\n",
20984 + __func__, wValue & 0xff);
20985 + return -DWC_E_INVALID;
20986 + }
20987 +
20988 + switch (wValue >> 8) {
20989 + case 0:
20990 + return (GET_CORE_IF(pcd)->pwron_txfsiz
20991 + [ep->dwc_ep.tx_fifo_num - 1] <
20992 + 768) ? GET_CORE_IF(pcd)->pwron_txfsiz[ep->
20993 + dwc_ep.tx_fifo_num
20994 + - 1] : 32768;
20995 + break;
20996 + case 1:
20997 + return GET_CORE_IF(pcd)->core_params->
20998 + dev_tx_fifo_size[ep->dwc_ep.num - 1];
20999 + break;
21000 + default:
21001 + return -DWC_E_INVALID;
21002 + break;
21003 + }
21004 +}
21005 +
21006 +/**
21007 + * This function checks if the submitted combination of
21008 + * device mode FIFO sizes is possible or not.
21009 + *
21010 + * @param core_if Programming view of DWC_otg controller
21011 + *
21012 + * @return 1 if possible, 0 otherwise.
21013 + *
21014 + */
21015 +static uint8_t check_fifo_sizes(dwc_otg_core_if_t * core_if)
21016 +{
21017 + uint16_t dfifo_actual = 0;
21018 + dwc_otg_core_params_t *params = core_if->core_params;
21019 + uint16_t start_addr = 0;
21020 + int i;
21021 +
21022 + dfifo_actual =
21023 + params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;
21024 +
21025 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
21026 + dfifo_actual += params->dev_tx_fifo_size[i];
21027 + }
21028 +
21029 + if (dfifo_actual > core_if->total_fifo_size) {
21030 + return 0;
21031 + }
21032 +
21033 + if (params->dev_rx_fifo_size > 32768 || params->dev_rx_fifo_size < 16)
21034 + return 0;
21035 +
21036 + if (params->dev_nperio_tx_fifo_size > 32768
21037 + || params->dev_nperio_tx_fifo_size < 16)
21038 + return 0;
21039 +
21040 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
21041 +
21042 + if (params->dev_tx_fifo_size[i] > 768
21043 + || params->dev_tx_fifo_size[i] < 4)
21044 + return 0;
21045 + }
21046 +
21047 + if (params->dev_rx_fifo_size > core_if->pwron_rxfsiz)
21048 + return 0;
21049 + start_addr = params->dev_rx_fifo_size;
21050 +
21051 + if (params->dev_nperio_tx_fifo_size > core_if->pwron_gnptxfsiz)
21052 + return 0;
21053 + start_addr += params->dev_nperio_tx_fifo_size;
21054 +
21055 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
21056 +
21057 + if (params->dev_tx_fifo_size[i] > core_if->pwron_txfsiz[i])
21058 + return 0;
21059 + start_addr += params->dev_tx_fifo_size[i];
21060 + }
21061 +
21062 + return 1;
21063 +}
21064 +
21065 +/**
21066 + * This function resizes Device mode FIFOs
21067 + *
21068 + * @param core_if Programming view of DWC_otg controller
21069 + *
21070 + * @return 1 if successful, 0 otherwise
21071 + *
21072 + */
21073 +static uint8_t resize_fifos(dwc_otg_core_if_t * core_if)
21074 +{
21075 + int i = 0;
21076 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
21077 + dwc_otg_core_params_t *params = core_if->core_params;
21078 + uint32_t rx_fifo_size;
21079 + fifosize_data_t nptxfifosize;
21080 + fifosize_data_t txfifosize[15];
21081 +
21082 + uint32_t rx_fsz_bak;
21083 + uint32_t nptxfsz_bak;
21084 + uint32_t txfsz_bak[15];
21085 +
21086 + uint16_t start_address;
21087 + uint8_t retval = 1;
21088 +
21089 + if (!check_fifo_sizes(core_if)) {
21090 + return 0;
21091 + }
21092 +
21093 + /* Configure data FIFO sizes */
21094 + if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
21095 + rx_fsz_bak = DWC_READ_REG32(&global_regs->grxfsiz);
21096 + rx_fifo_size = params->dev_rx_fifo_size;
21097 + DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size);
21098 +
21099 + /*
21100 + * Tx FIFOs These FIFOs are numbered from 1 to 15.
21101 + * Indexes of the FIFO size module parameters in the
21102 + * dev_tx_fifo_size array and the FIFO size registers in
21103 + * the dtxfsiz array run from 0 to 14.
21104 + */
21105 +
21106 + /* Non-periodic Tx FIFO */
21107 + nptxfsz_bak = DWC_READ_REG32(&global_regs->gnptxfsiz);
21108 + nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
21109 + start_address = params->dev_rx_fifo_size;
21110 + nptxfifosize.b.startaddr = start_address;
21111 +
21112 + DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);
21113 +
21114 + start_address += nptxfifosize.b.depth;
21115 +
21116 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
21117 + txfsz_bak[i] = DWC_READ_REG32(&global_regs->dtxfsiz[i]);
21118 +
21119 + txfifosize[i].b.depth = params->dev_tx_fifo_size[i];
21120 + txfifosize[i].b.startaddr = start_address;
21121 + DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
21122 + txfifosize[i].d32);
21123 +
21124 + start_address += txfifosize[i].b.depth;
21125 + }
21126 +
21127 + /** Check if register values are set correctly */
21128 + if (rx_fifo_size != DWC_READ_REG32(&global_regs->grxfsiz)) {
21129 + retval = 0;
21130 + }
21131 +
21132 + if (nptxfifosize.d32 != DWC_READ_REG32(&global_regs->gnptxfsiz)) {
21133 + retval = 0;
21134 + }
21135 +
21136 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
21137 + if (txfifosize[i].d32 !=
21138 + DWC_READ_REG32(&global_regs->dtxfsiz[i])) {
21139 + retval = 0;
21140 + }
21141 + }
21142 +
21143 + /** If register values are not set correctly, reset old values */
21144 + if (retval == 0) {
21145 + DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fsz_bak);
21146 +
21147 + /* Non-periodic Tx FIFO */
21148 + DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfsz_bak);
21149 +
21150 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
21151 + DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
21152 + txfsz_bak[i]);
21153 + }
21154 + }
21155 + } else {
21156 + return 0;
21157 + }
21158 +
21159 + /* Flush the FIFOs */
21160 + dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */
21161 + dwc_otg_flush_rx_fifo(core_if);
21162 +
21163 + return retval;
21164 +}
21165 +
21166 +/**
21167 + * This function sets a new value for the buffer Alignment setup.
21168 + */
21169 +static int cfi_ep_set_tx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)
21170 +{
21171 + int retval;
21172 + uint32_t fsiz;
21173 + uint16_t size;
21174 + uint16_t ep_addr;
21175 + dwc_otg_pcd_ep_t *ep;
21176 + dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
21177 + tx_fifo_size_setup_t *ptxfifoval;
21178 +
21179 + ptxfifoval = (tx_fifo_size_setup_t *) buf;
21180 + ep_addr = ptxfifoval->bEndpointAddress;
21181 + size = ptxfifoval->wDepth;
21182 +
21183 + ep = get_ep_by_addr(pcd, ep_addr);
21184 +
21185 + CFI_INFO
21186 + ("%s: Set Tx FIFO size: endpoint addr=0x%02x, depth=%d, FIFO Num=%d\n",
21187 + __func__, ep_addr, size, ep->dwc_ep.tx_fifo_num);
21188 +
21189 + if (NULL == ep) {
21190 + CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
21191 + __func__, ep_addr);
21192 + return -DWC_E_INVALID;
21193 + }
21194 +
21195 + fsiz = params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1];
21196 + params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = size;
21197 +
21198 + if (resize_fifos(GET_CORE_IF(pcd))) {
21199 + retval = 0;
21200 + } else {
21201 + CFI_INFO
21202 + ("%s: Error setting the feature Tx FIFO Size for EP%d\n",
21203 + __func__, ep_addr);
21204 + params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = fsiz;
21205 + retval = -DWC_E_INVALID;
21206 + }
21207 +
21208 + return retval;
21209 +}
21210 +
21211 +/**
21212 + * This function sets a new value for the buffer Alignment setup.
21213 + */
21214 +static int cfi_set_rx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)
21215 +{
21216 + int retval;
21217 + uint32_t fsiz;
21218 + uint16_t size;
21219 + dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
21220 + rx_fifo_size_setup_t *prxfifoval;
21221 +
21222 + prxfifoval = (rx_fifo_size_setup_t *) buf;
21223 + size = prxfifoval->wDepth;
21224 +
21225 + fsiz = params->dev_rx_fifo_size;
21226 + params->dev_rx_fifo_size = size;
21227 +
21228 + if (resize_fifos(GET_CORE_IF(pcd))) {
21229 + retval = 0;
21230 + } else {
21231 + CFI_INFO("%s: Error setting the feature Rx FIFO Size\n",
21232 + __func__);
21233 + params->dev_rx_fifo_size = fsiz;
21234 + retval = -DWC_E_INVALID;
21235 + }
21236 +
21237 + return retval;
21238 +}
21239 +
21240 +/**
21241 + * This function reads the SG of an EP's buffer setup into the buffer buf
21242 + */
21243 +static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
21244 + struct cfi_usb_ctrlrequest *req)
21245 +{
21246 + int retval = -DWC_E_INVALID;
21247 + uint8_t addr;
21248 + cfi_ep_t *ep;
21249 +
21250 + /* The Low Byte of the wValue contains a non-zero address of the endpoint */
21251 + addr = req->wValue & 0xFF;
21252 + if (addr == 0) /* The address should be non-zero */
21253 + return retval;
21254 +
21255 + ep = get_cfi_ep_by_addr(pcd->cfi, addr);
21256 + if (NULL == ep) {
21257 + CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
21258 + __func__, addr);
21259 + return retval;
21260 + }
21261 +
21262 + dwc_memcpy(buf, ep->bm_sg, BS_SG_VAL_DESC_LEN);
21263 + retval = BS_SG_VAL_DESC_LEN;
21264 + return retval;
21265 +}
21266 +
21267 +/**
21268 + * This function reads the Concatenation value of an EP's buffer mode into
21269 + * the buffer buf
21270 + */
21271 +static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
21272 + struct cfi_usb_ctrlrequest *req)
21273 +{
21274 + int retval = -DWC_E_INVALID;
21275 + uint8_t addr;
21276 + cfi_ep_t *ep;
21277 + uint8_t desc_count;
21278 +
21279 + /* The Low Byte of the wValue contains a non-zero address of the endpoint */
21280 + addr = req->wValue & 0xFF;
21281 + if (addr == 0) /* The address should be non-zero */
21282 + return retval;
21283 +
21284 + ep = get_cfi_ep_by_addr(pcd->cfi, addr);
21285 + if (NULL == ep) {
21286 + CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
21287 + __func__, addr);
21288 + return retval;
21289 + }
21290 +
21291 + /* Copy the header to the buffer */
21292 + dwc_memcpy(buf, ep->bm_concat, BS_CONCAT_VAL_HDR_LEN);
21293 + /* Advance the buffer pointer by the header size */
21294 + buf += BS_CONCAT_VAL_HDR_LEN;
21295 +
21296 + desc_count = ep->bm_concat->hdr.bDescCount;
21297 + /* Copy alll the wTxBytes to the buffer */
21298 + dwc_memcpy(buf, ep->bm_concat->wTxBytes, sizeof(uid16_t) * desc_count);
21299 +
21300 + retval = BS_CONCAT_VAL_HDR_LEN + sizeof(uid16_t) * desc_count;
21301 + return retval;
21302 +}
21303 +
21304 +/**
21305 + * This function reads the buffer Alignment value of an EP's buffer mode into
21306 + * the buffer buf
21307 + *
21308 + * @return The total number of bytes copied to the buffer or negative error code.
21309 + */
21310 +static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
21311 + struct cfi_usb_ctrlrequest *req)
21312 +{
21313 + int retval = -DWC_E_INVALID;
21314 + uint8_t addr;
21315 + cfi_ep_t *ep;
21316 +
21317 + /* The Low Byte of the wValue contains a non-zero address of the endpoint */
21318 + addr = req->wValue & 0xFF;
21319 + if (addr == 0) /* The address should be non-zero */
21320 + return retval;
21321 +
21322 + ep = get_cfi_ep_by_addr(pcd->cfi, addr);
21323 + if (NULL == ep) {
21324 + CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
21325 + __func__, addr);
21326 + return retval;
21327 + }
21328 +
21329 + dwc_memcpy(buf, ep->bm_align, BS_ALIGN_VAL_HDR_LEN);
21330 + retval = BS_ALIGN_VAL_HDR_LEN;
21331 +
21332 + return retval;
21333 +}
21334 +
21335 +/**
21336 + * This function sets a new value for the specified feature
21337 + *
21338 + * @param pcd A pointer to the PCD object
21339 + *
21340 + * @return 0 if successful, negative error code otherwise to stall the DCE.
21341 + */
21342 +static int cfi_set_feature_value(struct dwc_otg_pcd *pcd)
21343 +{
21344 + int retval = -DWC_E_NOT_SUPPORTED;
21345 + uint16_t wIndex, wValue;
21346 + uint8_t bRequest;
21347 + struct dwc_otg_core_if *coreif;
21348 + cfiobject_t *cfi = pcd->cfi;
21349 + struct cfi_usb_ctrlrequest *ctrl_req;
21350 + uint8_t *buf;
21351 + ctrl_req = &cfi->ctrl_req;
21352 +
21353 + buf = pcd->cfi->ctrl_req.data;
21354 +
21355 + coreif = GET_CORE_IF(pcd);
21356 + bRequest = ctrl_req->bRequest;
21357 + wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);
21358 + wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);
21359 +
21360 + /* See which feature is to be modified */
21361 + switch (wIndex) {
21362 + case FT_ID_DMA_BUFFER_SETUP:
21363 + /* Modify the feature */
21364 + if ((retval = cfi_ep_set_sg_val(buf, pcd)) < 0)
21365 + return retval;
21366 +
21367 + /* And send this request to the gadget */
21368 + cfi->need_gadget_att = 1;
21369 + break;
21370 +
21371 + case FT_ID_DMA_BUFF_ALIGN:
21372 + if ((retval = cfi_ep_set_alignment_val(buf, pcd)) < 0)
21373 + return retval;
21374 + cfi->need_gadget_att = 1;
21375 + break;
21376 +
21377 + case FT_ID_DMA_CONCAT_SETUP:
21378 + /* Modify the feature */
21379 + if ((retval = cfi_ep_set_concat_val(buf, pcd)) < 0)
21380 + return retval;
21381 + cfi->need_gadget_att = 1;
21382 + break;
21383 +
21384 + case FT_ID_DMA_CIRCULAR:
21385 + CFI_INFO("FT_ID_DMA_CIRCULAR\n");
21386 + break;
21387 +
21388 + case FT_ID_THRESHOLD_SETUP:
21389 + CFI_INFO("FT_ID_THRESHOLD_SETUP\n");
21390 + break;
21391 +
21392 + case FT_ID_DFIFO_DEPTH:
21393 + CFI_INFO("FT_ID_DFIFO_DEPTH\n");
21394 + break;
21395 +
21396 + case FT_ID_TX_FIFO_DEPTH:
21397 + CFI_INFO("FT_ID_TX_FIFO_DEPTH\n");
21398 + if ((retval = cfi_ep_set_tx_fifo_val(buf, pcd)) < 0)
21399 + return retval;
21400 + cfi->need_gadget_att = 0;
21401 + break;
21402 +
21403 + case FT_ID_RX_FIFO_DEPTH:
21404 + CFI_INFO("FT_ID_RX_FIFO_DEPTH\n");
21405 + if ((retval = cfi_set_rx_fifo_val(buf, pcd)) < 0)
21406 + return retval;
21407 + cfi->need_gadget_att = 0;
21408 + break;
21409 + }
21410 +
21411 + return retval;
21412 +}
21413 +
21414 +#endif //DWC_UTE_CFI
21415 --- /dev/null
21416 +++ b/drivers/usb/host/dwc_otg/dwc_otg_cfi.h
21417 @@ -0,0 +1,320 @@
21418 +/* ==========================================================================
21419 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
21420 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
21421 + * otherwise expressly agreed to in writing between Synopsys and you.
21422 + *
21423 + * The Software IS NOT an item of Licensed Software or Licensed Product under
21424 + * any End User Software License Agreement or Agreement for Licensed Product
21425 + * with Synopsys or any supplement thereto. You are permitted to use and
21426 + * redistribute this Software in source and binary forms, with or without
21427 + * modification, provided that redistributions of source code must retain this
21428 + * notice. You may not view, use, disclose, copy or distribute this file or
21429 + * any information contained herein except pursuant to this license grant from
21430 + * Synopsys. If you do not agree with this notice, including the disclaimer
21431 + * below, then you are not authorized to use the Software.
21432 + *
21433 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
21434 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21435 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21436 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
21437 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21438 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21439 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
21440 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21441 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
21442 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
21443 + * DAMAGE.
21444 + * ========================================================================== */
21445 +
21446 +#if !defined(__DWC_OTG_CFI_H__)
21447 +#define __DWC_OTG_CFI_H__
21448 +
21449 +#include "dwc_otg_pcd.h"
21450 +#include "dwc_cfi_common.h"
21451 +
21452 +/**
21453 + * @file
21454 + * This file contains the CFI related OTG PCD specific common constants,
21455 + * interfaces(functions and macros) and data structures.The CFI Protocol is an
21456 + * optional interface for internal testing purposes that a DUT may implement to
21457 + * support testing of configurable features.
21458 + *
21459 + */
21460 +
21461 +struct dwc_otg_pcd;
21462 +struct dwc_otg_pcd_ep;
21463 +
21464 +/** OTG CFI Features (properties) ID constants */
21465 +/** This is a request for all Core Features */
21466 +#define FT_ID_DMA_MODE 0x0001
21467 +#define FT_ID_DMA_BUFFER_SETUP 0x0002
21468 +#define FT_ID_DMA_BUFF_ALIGN 0x0003
21469 +#define FT_ID_DMA_CONCAT_SETUP 0x0004
21470 +#define FT_ID_DMA_CIRCULAR 0x0005
21471 +#define FT_ID_THRESHOLD_SETUP 0x0006
21472 +#define FT_ID_DFIFO_DEPTH 0x0007
21473 +#define FT_ID_TX_FIFO_DEPTH 0x0008
21474 +#define FT_ID_RX_FIFO_DEPTH 0x0009
21475 +
21476 +/**********************************************************/
21477 +#define CFI_INFO_DEF
21478 +
21479 +#ifdef CFI_INFO_DEF
21480 +#define CFI_INFO(fmt...) DWC_PRINTF("CFI: " fmt);
21481 +#else
21482 +#define CFI_INFO(fmt...)
21483 +#endif
21484 +
21485 +#define min(x,y) ({ \
21486 + x < y ? x : y; })
21487 +
21488 +#define max(x,y) ({ \
21489 + x > y ? x : y; })
21490 +
21491 +/**
21492 + * Descriptor DMA SG Buffer setup structure (SG buffer). This structure is
21493 + * also used for setting up a buffer for Circular DDMA.
21494 + */
21495 +struct _ddma_sg_buffer_setup {
21496 +#define BS_SG_VAL_DESC_LEN 6
21497 + /* The OUT EP address */
21498 + uint8_t bOutEndpointAddress;
21499 + /* The IN EP address */
21500 + uint8_t bInEndpointAddress;
21501 + /* Number of bytes to put between transfer segments (must be DWORD boundaries) */
21502 + uint8_t bOffset;
21503 + /* The number of transfer segments (a DMA descriptors per each segment) */
21504 + uint8_t bCount;
21505 + /* Size (in byte) of each transfer segment */
21506 + uint16_t wSize;
21507 +} __attribute__ ((packed));
21508 +typedef struct _ddma_sg_buffer_setup ddma_sg_buffer_setup_t;
21509 +
21510 +/** Descriptor DMA Concatenation Buffer setup structure */
21511 +struct _ddma_concat_buffer_setup_hdr {
21512 +#define BS_CONCAT_VAL_HDR_LEN 4
21513 + /* The endpoint for which the buffer is to be set up */
21514 + uint8_t bEndpointAddress;
21515 + /* The count of descriptors to be used */
21516 + uint8_t bDescCount;
21517 + /* The total size of the transfer */
21518 + uint16_t wSize;
21519 +} __attribute__ ((packed));
21520 +typedef struct _ddma_concat_buffer_setup_hdr ddma_concat_buffer_setup_hdr_t;
21521 +
21522 +/** Descriptor DMA Concatenation Buffer setup structure */
21523 +struct _ddma_concat_buffer_setup {
21524 + /* The SG header */
21525 + ddma_concat_buffer_setup_hdr_t hdr;
21526 +
21527 + /* The XFER sizes pointer (allocated dynamically) */
21528 + uint16_t *wTxBytes;
21529 +} __attribute__ ((packed));
21530 +typedef struct _ddma_concat_buffer_setup ddma_concat_buffer_setup_t;
21531 +
21532 +/** Descriptor DMA Alignment Buffer setup structure */
21533 +struct _ddma_align_buffer_setup {
21534 +#define BS_ALIGN_VAL_HDR_LEN 2
21535 + uint8_t bEndpointAddress;
21536 + uint8_t bAlign;
21537 +} __attribute__ ((packed));
21538 +typedef struct _ddma_align_buffer_setup ddma_align_buffer_setup_t;
21539 +
21540 +/** Transmit FIFO Size setup structure */
21541 +struct _tx_fifo_size_setup {
21542 + uint8_t bEndpointAddress;
21543 + uint16_t wDepth;
21544 +} __attribute__ ((packed));
21545 +typedef struct _tx_fifo_size_setup tx_fifo_size_setup_t;
21546 +
21547 +/** Transmit FIFO Size setup structure */
21548 +struct _rx_fifo_size_setup {
21549 + uint16_t wDepth;
21550 +} __attribute__ ((packed));
21551 +typedef struct _rx_fifo_size_setup rx_fifo_size_setup_t;
21552 +
21553 +/**
21554 + * struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest
21555 + * This structure encapsulates the standard usb_ctrlrequest and adds a pointer
21556 + * to the data returned in the data stage of a 3-stage Control Write requests.
21557 + */
21558 +struct cfi_usb_ctrlrequest {
21559 + uint8_t bRequestType;
21560 + uint8_t bRequest;
21561 + uint16_t wValue;
21562 + uint16_t wIndex;
21563 + uint16_t wLength;
21564 + uint8_t *data;
21565 +} UPACKED;
21566 +
21567 +/*---------------------------------------------------------------------------*/
21568 +
21569 +/**
21570 + * The CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures.
21571 + * This structure is used to store the buffer setup data for any
21572 + * enabled endpoint in the PCD.
21573 + */
21574 +struct cfi_ep {
21575 + /* Entry for the list container */
21576 + dwc_list_link_t lh;
21577 + /* Pointer to the active PCD endpoint structure */
21578 + struct dwc_otg_pcd_ep *ep;
21579 + /* The last descriptor in the chain of DMA descriptors of the endpoint */
21580 + struct dwc_otg_dma_desc *dma_desc_last;
21581 + /* The SG feature value */
21582 + ddma_sg_buffer_setup_t *bm_sg;
21583 + /* The Circular feature value */
21584 + ddma_sg_buffer_setup_t *bm_circ;
21585 + /* The Concatenation feature value */
21586 + ddma_concat_buffer_setup_t *bm_concat;
21587 + /* The Alignment feature value */
21588 + ddma_align_buffer_setup_t *bm_align;
21589 + /* XFER length */
21590 + uint32_t xfer_len;
21591 + /*
21592 + * Count of DMA descriptors currently used.
21593 + * The total should not exceed the MAX_DMA_DESCS_PER_EP value
21594 + * defined in the dwc_otg_cil.h
21595 + */
21596 + uint32_t desc_count;
21597 +};
21598 +typedef struct cfi_ep cfi_ep_t;
21599 +
21600 +typedef struct cfi_dma_buff {
21601 +#define CFI_IN_BUF_LEN 1024
21602 +#define CFI_OUT_BUF_LEN 1024
21603 + dma_addr_t addr;
21604 + uint8_t *buf;
21605 +} cfi_dma_buff_t;
21606 +
21607 +struct cfiobject;
21608 +
21609 +/**
21610 + * This is the interface for the CFI operations.
21611 + *
21612 + * @param ep_enable Called when any endpoint is enabled and activated.
21613 + * @param release Called when the CFI object is released and it needs to correctly
21614 + * deallocate the dynamic memory
21615 + * @param ctrl_write_complete Called when the data stage of the request is complete
21616 + */
21617 +typedef struct cfi_ops {
21618 + int (*ep_enable) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,
21619 + struct dwc_otg_pcd_ep * ep);
21620 + void *(*ep_alloc_buf) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,
21621 + struct dwc_otg_pcd_ep * ep, dma_addr_t * dma,
21622 + unsigned size, gfp_t flags);
21623 + void (*release) (struct cfiobject * cfi);
21624 + int (*ctrl_write_complete) (struct cfiobject * cfi,
21625 + struct dwc_otg_pcd * pcd);
21626 + void (*build_descriptors) (struct cfiobject * cfi,
21627 + struct dwc_otg_pcd * pcd,
21628 + struct dwc_otg_pcd_ep * ep,
21629 + dwc_otg_pcd_request_t * req);
21630 +} cfi_ops_t;
21631 +
21632 +struct cfiobject {
21633 + cfi_ops_t ops;
21634 + struct dwc_otg_pcd *pcd;
21635 + struct usb_gadget *gadget;
21636 +
21637 + /* Buffers used to send/receive CFI-related request data */
21638 + cfi_dma_buff_t buf_in;
21639 + cfi_dma_buff_t buf_out;
21640 +
21641 + /* CFI specific Control request wrapper */
21642 + struct cfi_usb_ctrlrequest ctrl_req;
21643 +
21644 + /* The list of active EP's in the PCD of type cfi_ep_t */
21645 + dwc_list_link_t active_eps;
21646 +
21647 + /* This flag shall control the propagation of a specific request
21648 + * to the gadget's processing routines.
21649 + * 0 - no gadget handling
21650 + * 1 - the gadget needs to know about this request (w/o completing a status
21651 + * phase - just return a 0 to the _setup callback)
21652 + */
21653 + uint8_t need_gadget_att;
21654 +
21655 + /* Flag indicating whether the status IN phase needs to be
21656 + * completed by the PCD
21657 + */
21658 + uint8_t need_status_in_complete;
21659 +};
21660 +typedef struct cfiobject cfiobject_t;
21661 +
21662 +#define DUMP_MSG
21663 +
21664 +#if defined(DUMP_MSG)
21665 +static inline void dump_msg(const u8 * buf, unsigned int length)
21666 +{
21667 + unsigned int start, num, i;
21668 + char line[52], *p;
21669 +
21670 + if (length >= 512)
21671 + return;
21672 +
21673 + start = 0;
21674 + while (length > 0) {
21675 + num = min(length, 16u);
21676 + p = line;
21677 + for (i = 0; i < num; ++i) {
21678 + if (i == 8)
21679 + *p++ = ' ';
21680 + DWC_SPRINTF(p, " %02x", buf[i]);
21681 + p += 3;
21682 + }
21683 + *p = 0;
21684 + DWC_DEBUG("%6x: %s\n", start, line);
21685 + buf += num;
21686 + start += num;
21687 + length -= num;
21688 + }
21689 +}
21690 +#else
21691 +static inline void dump_msg(const u8 * buf, unsigned int length)
21692 +{
21693 +}
21694 +#endif
21695 +
21696 +/**
21697 + * This function returns a pointer to cfi_ep_t object with the addr address.
21698 + */
21699 +static inline struct cfi_ep *get_cfi_ep_by_addr(struct cfiobject *cfi,
21700 + uint8_t addr)
21701 +{
21702 + struct cfi_ep *pcfiep;
21703 + dwc_list_link_t *tmp;
21704 +
21705 + DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
21706 + pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
21707 +
21708 + if (pcfiep->ep->desc->bEndpointAddress == addr) {
21709 + return pcfiep;
21710 + }
21711 + }
21712 +
21713 + return NULL;
21714 +}
21715 +
21716 +/**
21717 + * This function returns a pointer to cfi_ep_t object that matches
21718 + * the dwc_otg_pcd_ep object.
21719 + */
21720 +static inline struct cfi_ep *get_cfi_ep_by_pcd_ep(struct cfiobject *cfi,
21721 + struct dwc_otg_pcd_ep *ep)
21722 +{
21723 + struct cfi_ep *pcfiep = NULL;
21724 + dwc_list_link_t *tmp;
21725 +
21726 + DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
21727 + pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
21728 + if (pcfiep->ep == ep) {
21729 + return pcfiep;
21730 + }
21731 + }
21732 + return NULL;
21733 +}
21734 +
21735 +int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl);
21736 +
21737 +#endif /* (__DWC_OTG_CFI_H__) */
21738 --- /dev/null
21739 +++ b/drivers/usb/host/dwc_otg/dwc_otg_cil.c
21740 @@ -0,0 +1,7141 @@
21741 +/* ==========================================================================
21742 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $
21743 + * $Revision: #191 $
21744 + * $Date: 2012/08/10 $
21745 + * $Change: 2047372 $
21746 + *
21747 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
21748 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
21749 + * otherwise expressly agreed to in writing between Synopsys and you.
21750 + *
21751 + * The Software IS NOT an item of Licensed Software or Licensed Product under
21752 + * any End User Software License Agreement or Agreement for Licensed Product
21753 + * with Synopsys or any supplement thereto. You are permitted to use and
21754 + * redistribute this Software in source and binary forms, with or without
21755 + * modification, provided that redistributions of source code must retain this
21756 + * notice. You may not view, use, disclose, copy or distribute this file or
21757 + * any information contained herein except pursuant to this license grant from
21758 + * Synopsys. If you do not agree with this notice, including the disclaimer
21759 + * below, then you are not authorized to use the Software.
21760 + *
21761 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
21762 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21763 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21764 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
21765 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21766 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21767 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
21768 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21769 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
21770 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
21771 + * DAMAGE.
21772 + * ========================================================================== */
21773 +
21774 +/** @file
21775 + *
21776 + * The Core Interface Layer provides basic services for accessing and
21777 + * managing the DWC_otg hardware. These services are used by both the
21778 + * Host Controller Driver and the Peripheral Controller Driver.
21779 + *
21780 + * The CIL manages the memory map for the core so that the HCD and PCD
21781 + * don't have to do this separately. It also handles basic tasks like
21782 + * reading/writing the registers and data FIFOs in the controller.
21783 + * Some of the data access functions provide encapsulation of several
21784 + * operations required to perform a task, such as writing multiple
21785 + * registers to start a transfer. Finally, the CIL performs basic
21786 + * services that are not specific to either the host or device modes
21787 + * of operation. These services include management of the OTG Host
21788 + * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A
21789 + * Diagnostic API is also provided to allow testing of the controller
21790 + * hardware.
21791 + *
21792 + * The Core Interface Layer has the following requirements:
21793 + * - Provides basic controller operations.
21794 + * - Minimal use of OS services.
21795 + * - The OS services used will be abstracted by using inline functions
21796 + * or macros.
21797 + *
21798 + */
21799 +
21800 +#include "dwc_os.h"
21801 +#include "dwc_otg_regs.h"
21802 +#include "dwc_otg_cil.h"
21803 +
21804 +static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if);
21805 +
21806 +/**
21807 + * This function is called to initialize the DWC_otg CSR data
21808 + * structures. The register addresses in the device and host
21809 + * structures are initialized from the base address supplied by the
21810 + * caller. The calling function must make the OS calls to get the
21811 + * base address of the DWC_otg controller registers. The core_params
21812 + * argument holds the parameters that specify how the core should be
21813 + * configured.
21814 + *
21815 + * @param reg_base_addr Base address of DWC_otg core registers
21816 + *
21817 + */
21818 +dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * reg_base_addr)
21819 +{
21820 + dwc_otg_core_if_t *core_if = 0;
21821 + dwc_otg_dev_if_t *dev_if = 0;
21822 + dwc_otg_host_if_t *host_if = 0;
21823 + uint8_t *reg_base = (uint8_t *) reg_base_addr;
21824 + int i = 0;
21825 +
21826 + DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, reg_base_addr);
21827 +
21828 + core_if = DWC_ALLOC(sizeof(dwc_otg_core_if_t));
21829 +
21830 + if (core_if == NULL) {
21831 + DWC_DEBUGPL(DBG_CIL,
21832 + "Allocation of dwc_otg_core_if_t failed\n");
21833 + return 0;
21834 + }
21835 + core_if->core_global_regs = (dwc_otg_core_global_regs_t *) reg_base;
21836 +
21837 + /*
21838 + * Allocate the Device Mode structures.
21839 + */
21840 + dev_if = DWC_ALLOC(sizeof(dwc_otg_dev_if_t));
21841 +
21842 + if (dev_if == NULL) {
21843 + DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n");
21844 + DWC_FREE(core_if);
21845 + return 0;
21846 + }
21847 +
21848 + dev_if->dev_global_regs =
21849 + (dwc_otg_device_global_regs_t *) (reg_base +
21850 + DWC_DEV_GLOBAL_REG_OFFSET);
21851 +
21852 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
21853 + dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *)
21854 + (reg_base + DWC_DEV_IN_EP_REG_OFFSET +
21855 + (i * DWC_EP_REG_OFFSET));
21856 +
21857 + dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *)
21858 + (reg_base + DWC_DEV_OUT_EP_REG_OFFSET +
21859 + (i * DWC_EP_REG_OFFSET));
21860 + DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n",
21861 + i, &dev_if->in_ep_regs[i]->diepctl);
21862 + DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n",
21863 + i, &dev_if->out_ep_regs[i]->doepctl);
21864 + }
21865 +
21866 + dev_if->speed = 0; // unknown
21867 +
21868 + core_if->dev_if = dev_if;
21869 +
21870 + /*
21871 + * Allocate the Host Mode structures.
21872 + */
21873 + host_if = DWC_ALLOC(sizeof(dwc_otg_host_if_t));
21874 +
21875 + if (host_if == NULL) {
21876 + DWC_DEBUGPL(DBG_CIL,
21877 + "Allocation of dwc_otg_host_if_t failed\n");
21878 + DWC_FREE(dev_if);
21879 + DWC_FREE(core_if);
21880 + return 0;
21881 + }
21882 +
21883 + host_if->host_global_regs = (dwc_otg_host_global_regs_t *)
21884 + (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET);
21885 +
21886 + host_if->hprt0 =
21887 + (uint32_t *) (reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);
21888 +
21889 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
21890 + host_if->hc_regs[i] = (dwc_otg_hc_regs_t *)
21891 + (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET +
21892 + (i * DWC_OTG_CHAN_REGS_OFFSET));
21893 + DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
21894 + i, &host_if->hc_regs[i]->hcchar);
21895 + }
21896 +
21897 + host_if->num_host_channels = MAX_EPS_CHANNELS;
21898 + core_if->host_if = host_if;
21899 +
21900 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
21901 + core_if->data_fifo[i] =
21902 + (uint32_t *) (reg_base + DWC_OTG_DATA_FIFO_OFFSET +
21903 + (i * DWC_OTG_DATA_FIFO_SIZE));
21904 + DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08lx\n",
21905 + i, (unsigned long)core_if->data_fifo[i]);
21906 + }
21907 +
21908 + core_if->pcgcctl = (uint32_t *) (reg_base + DWC_OTG_PCGCCTL_OFFSET);
21909 +
21910 + /* Initiate lx_state to L3 disconnected state */
21911 + core_if->lx_state = DWC_OTG_L3;
21912 + /*
21913 + * Store the contents of the hardware configuration registers here for
21914 + * easy access later.
21915 + */
21916 + core_if->hwcfg1.d32 =
21917 + DWC_READ_REG32(&core_if->core_global_regs->ghwcfg1);
21918 + core_if->hwcfg2.d32 =
21919 + DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
21920 + core_if->hwcfg3.d32 =
21921 + DWC_READ_REG32(&core_if->core_global_regs->ghwcfg3);
21922 + core_if->hwcfg4.d32 =
21923 + DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
21924 +
21925 + /* Force host mode to get HPTXFSIZ exact power on value */
21926 + {
21927 + gusbcfg_data_t gusbcfg = {.d32 = 0 };
21928 + gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
21929 + gusbcfg.b.force_host_mode = 1;
21930 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
21931 + dwc_mdelay(100);
21932 + core_if->hptxfsiz.d32 =
21933 + DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
21934 + gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
21935 + gusbcfg.b.force_host_mode = 0;
21936 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
21937 + dwc_mdelay(100);
21938 + }
21939 +
21940 + DWC_DEBUGPL(DBG_CILV, "hwcfg1=%08x\n", core_if->hwcfg1.d32);
21941 + DWC_DEBUGPL(DBG_CILV, "hwcfg2=%08x\n", core_if->hwcfg2.d32);
21942 + DWC_DEBUGPL(DBG_CILV, "hwcfg3=%08x\n", core_if->hwcfg3.d32);
21943 + DWC_DEBUGPL(DBG_CILV, "hwcfg4=%08x\n", core_if->hwcfg4.d32);
21944 +
21945 + core_if->hcfg.d32 =
21946 + DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
21947 + core_if->dcfg.d32 =
21948 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
21949 +
21950 + DWC_DEBUGPL(DBG_CILV, "hcfg=%08x\n", core_if->hcfg.d32);
21951 + DWC_DEBUGPL(DBG_CILV, "dcfg=%08x\n", core_if->dcfg.d32);
21952 +
21953 + DWC_DEBUGPL(DBG_CILV, "op_mode=%0x\n", core_if->hwcfg2.b.op_mode);
21954 + DWC_DEBUGPL(DBG_CILV, "arch=%0x\n", core_if->hwcfg2.b.architecture);
21955 + DWC_DEBUGPL(DBG_CILV, "num_dev_ep=%d\n", core_if->hwcfg2.b.num_dev_ep);
21956 + DWC_DEBUGPL(DBG_CILV, "num_host_chan=%d\n",
21957 + core_if->hwcfg2.b.num_host_chan);
21958 + DWC_DEBUGPL(DBG_CILV, "nonperio_tx_q_depth=0x%0x\n",
21959 + core_if->hwcfg2.b.nonperio_tx_q_depth);
21960 + DWC_DEBUGPL(DBG_CILV, "host_perio_tx_q_depth=0x%0x\n",
21961 + core_if->hwcfg2.b.host_perio_tx_q_depth);
21962 + DWC_DEBUGPL(DBG_CILV, "dev_token_q_depth=0x%0x\n",
21963 + core_if->hwcfg2.b.dev_token_q_depth);
21964 +
21965 + DWC_DEBUGPL(DBG_CILV, "Total FIFO SZ=%d\n",
21966 + core_if->hwcfg3.b.dfifo_depth);
21967 + DWC_DEBUGPL(DBG_CILV, "xfer_size_cntr_width=%0x\n",
21968 + core_if->hwcfg3.b.xfer_size_cntr_width);
21969 +
21970 + /*
21971 + * Set the SRP sucess bit for FS-I2c
21972 + */
21973 + core_if->srp_success = 0;
21974 + core_if->srp_timer_started = 0;
21975 +
21976 + /*
21977 + * Create new workqueue and init works
21978 + */
21979 + core_if->wq_otg = DWC_WORKQ_ALLOC("dwc_otg");
21980 + if (core_if->wq_otg == 0) {
21981 + DWC_WARN("DWC_WORKQ_ALLOC failed\n");
21982 + DWC_FREE(host_if);
21983 + DWC_FREE(dev_if);
21984 + DWC_FREE(core_if);
21985 + return 0;
21986 + }
21987 +
21988 + core_if->snpsid = DWC_READ_REG32(&core_if->core_global_regs->gsnpsid);
21989 +
21990 + DWC_PRINTF("Core Release: %x.%x%x%x\n",
21991 + (core_if->snpsid >> 12 & 0xF),
21992 + (core_if->snpsid >> 8 & 0xF),
21993 + (core_if->snpsid >> 4 & 0xF), (core_if->snpsid & 0xF));
21994 +
21995 + core_if->wkp_timer = DWC_TIMER_ALLOC("Wake Up Timer",
21996 + w_wakeup_detected, core_if);
21997 + if (core_if->wkp_timer == 0) {
21998 + DWC_WARN("DWC_TIMER_ALLOC failed\n");
21999 + DWC_FREE(host_if);
22000 + DWC_FREE(dev_if);
22001 + DWC_WORKQ_FREE(core_if->wq_otg);
22002 + DWC_FREE(core_if);
22003 + return 0;
22004 + }
22005 +
22006 + if (dwc_otg_setup_params(core_if)) {
22007 + DWC_WARN("Error while setting core params\n");
22008 + }
22009 +
22010 + core_if->hibernation_suspend = 0;
22011 +
22012 + /** ADP initialization */
22013 + dwc_otg_adp_init(core_if);
22014 +
22015 + return core_if;
22016 +}
22017 +
22018 +/**
22019 + * This function frees the structures allocated by dwc_otg_cil_init().
22020 + *
22021 + * @param core_if The core interface pointer returned from
22022 + * dwc_otg_cil_init().
22023 + *
22024 + */
22025 +void dwc_otg_cil_remove(dwc_otg_core_if_t * core_if)
22026 +{
22027 + dctl_data_t dctl = {.d32 = 0 };
22028 + DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
22029 +
22030 + /* Disable all interrupts */
22031 + DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 1, 0);
22032 + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);
22033 +
22034 + dctl.b.sftdiscon = 1;
22035 + if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
22036 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0,
22037 + dctl.d32);
22038 + }
22039 +
22040 + if (core_if->wq_otg) {
22041 + DWC_WORKQ_WAIT_WORK_DONE(core_if->wq_otg, 500);
22042 + DWC_WORKQ_FREE(core_if->wq_otg);
22043 + }
22044 + if (core_if->dev_if) {
22045 + DWC_FREE(core_if->dev_if);
22046 + }
22047 + if (core_if->host_if) {
22048 + DWC_FREE(core_if->host_if);
22049 + }
22050 +
22051 + /** Remove ADP Stuff */
22052 + dwc_otg_adp_remove(core_if);
22053 + if (core_if->core_params) {
22054 + DWC_FREE(core_if->core_params);
22055 + }
22056 + if (core_if->wkp_timer) {
22057 + DWC_TIMER_FREE(core_if->wkp_timer);
22058 + }
22059 + if (core_if->srp_timer) {
22060 + DWC_TIMER_FREE(core_if->srp_timer);
22061 + }
22062 + DWC_FREE(core_if);
22063 +}
22064 +
22065 +/**
22066 + * This function enables the controller's Global Interrupt in the AHB Config
22067 + * register.
22068 + *
22069 + * @param core_if Programming view of DWC_otg controller.
22070 + */
22071 +void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * core_if)
22072 +{
22073 + gahbcfg_data_t ahbcfg = {.d32 = 0 };
22074 + ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
22075 + DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
22076 +}
22077 +
22078 +/**
22079 + * This function disables the controller's Global Interrupt in the AHB Config
22080 + * register.
22081 + *
22082 + * @param core_if Programming view of DWC_otg controller.
22083 + */
22084 +void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * core_if)
22085 +{
22086 + gahbcfg_data_t ahbcfg = {.d32 = 0 };
22087 + ahbcfg.b.glblintrmsk = 1; /* Disable interrupts */
22088 + DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
22089 +}
22090 +
22091 +/**
22092 + * This function initializes the commmon interrupts, used in both
22093 + * device and host modes.
22094 + *
22095 + * @param core_if Programming view of the DWC_otg controller
22096 + *
22097 + */
22098 +static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t * core_if)
22099 +{
22100 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
22101 + gintmsk_data_t intr_mask = {.d32 = 0 };
22102 +
22103 + /* Clear any pending OTG Interrupts */
22104 + DWC_WRITE_REG32(&global_regs->gotgint, 0xFFFFFFFF);
22105 +
22106 + /* Clear any pending interrupts */
22107 + DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
22108 +
22109 + /*
22110 + * Enable the interrupts in the GINTMSK.
22111 + */
22112 + intr_mask.b.modemismatch = 1;
22113 + intr_mask.b.otgintr = 1;
22114 +
22115 + if (!core_if->dma_enable) {
22116 + intr_mask.b.rxstsqlvl = 1;
22117 + }
22118 +
22119 + intr_mask.b.conidstschng = 1;
22120 + intr_mask.b.wkupintr = 1;
22121 + intr_mask.b.disconnect = 0;
22122 + intr_mask.b.usbsuspend = 1;
22123 + intr_mask.b.sessreqintr = 1;
22124 +#ifdef CONFIG_USB_DWC_OTG_LPM
22125 + if (core_if->core_params->lpm_enable) {
22126 + intr_mask.b.lpmtranrcvd = 1;
22127 + }
22128 +#endif
22129 + DWC_WRITE_REG32(&global_regs->gintmsk, intr_mask.d32);
22130 +}
22131 +
22132 +/*
22133 + * The restore operation is modified to support Synopsys Emulated Powerdown and
22134 + * Hibernation. This function is for exiting from Device mode hibernation by
22135 + * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
22136 + * @param core_if Programming view of DWC_otg controller.
22137 + * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
22138 + * @param reset - indicates whether resume is initiated by Reset.
22139 + */
22140 +int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
22141 + int rem_wakeup, int reset)
22142 +{
22143 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
22144 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
22145 + dctl_data_t dctl = {.d32 = 0 };
22146 +
22147 + int timeout = 2000;
22148 +
22149 + if (!core_if->hibernation_suspend) {
22150 + DWC_PRINTF("Already exited from Hibernation\n");
22151 + return 1;
22152 + }
22153 +
22154 + DWC_DEBUGPL(DBG_PCD, "%s called\n", __FUNCTION__);
22155 + /* Switch-on voltage to the core */
22156 + gpwrdn.b.pwrdnswtch = 1;
22157 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22158 + dwc_udelay(10);
22159 +
22160 + /* Reset core */
22161 + gpwrdn.d32 = 0;
22162 + gpwrdn.b.pwrdnrstn = 1;
22163 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22164 + dwc_udelay(10);
22165 +
22166 + /* Assert Restore signal */
22167 + gpwrdn.d32 = 0;
22168 + gpwrdn.b.restore = 1;
22169 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
22170 + dwc_udelay(10);
22171 +
22172 + /* Disable power clamps */
22173 + gpwrdn.d32 = 0;
22174 + gpwrdn.b.pwrdnclmp = 1;
22175 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22176 +
22177 + if (rem_wakeup) {
22178 + dwc_udelay(70);
22179 + }
22180 +
22181 + /* Deassert Reset core */
22182 + gpwrdn.d32 = 0;
22183 + gpwrdn.b.pwrdnrstn = 1;
22184 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
22185 + dwc_udelay(10);
22186 +
22187 + /* Disable PMU interrupt */
22188 + gpwrdn.d32 = 0;
22189 + gpwrdn.b.pmuintsel = 1;
22190 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22191 +
22192 + /* Mask interrupts from gpwrdn */
22193 + gpwrdn.d32 = 0;
22194 + gpwrdn.b.connect_det_msk = 1;
22195 + gpwrdn.b.srp_det_msk = 1;
22196 + gpwrdn.b.disconn_det_msk = 1;
22197 + gpwrdn.b.rst_det_msk = 1;
22198 + gpwrdn.b.lnstchng_msk = 1;
22199 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22200 +
22201 + /* Indicates that we are going out from hibernation */
22202 + core_if->hibernation_suspend = 0;
22203 +
22204 + /*
22205 + * Set Restore Essential Regs bit in PCGCCTL register, restore_mode = 1
22206 + * indicates restore from remote_wakeup
22207 + */
22208 + restore_essential_regs(core_if, rem_wakeup, 0);
22209 +
22210 + /*
22211 + * Wait a little for seeing new value of variable hibernation_suspend if
22212 + * Restore done interrupt received before polling
22213 + */
22214 + dwc_udelay(10);
22215 +
22216 + if (core_if->hibernation_suspend == 0) {
22217 + /*
22218 + * Wait For Restore_done Interrupt. This mechanism of polling the
22219 + * interrupt is introduced to avoid any possible race conditions
22220 + */
22221 + do {
22222 + gintsts_data_t gintsts;
22223 + gintsts.d32 =
22224 + DWC_READ_REG32(&core_if->core_global_regs->gintsts);
22225 + if (gintsts.b.restoredone) {
22226 + gintsts.d32 = 0;
22227 + gintsts.b.restoredone = 1;
22228 + DWC_WRITE_REG32(&core_if->core_global_regs->
22229 + gintsts, gintsts.d32);
22230 + DWC_PRINTF("Restore Done Interrupt seen\n");
22231 + break;
22232 + }
22233 + dwc_udelay(10);
22234 + } while (--timeout);
22235 + if (!timeout) {
22236 + DWC_PRINTF("Restore Done interrupt wasn't generated here\n");
22237 + }
22238 + }
22239 + /* Clear all pending interupts */
22240 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
22241 +
22242 + /* De-assert Restore */
22243 + gpwrdn.d32 = 0;
22244 + gpwrdn.b.restore = 1;
22245 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22246 + dwc_udelay(10);
22247 +
22248 + if (!rem_wakeup) {
22249 + pcgcctl.d32 = 0;
22250 + pcgcctl.b.rstpdwnmodule = 1;
22251 + DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
22252 + }
22253 +
22254 + /* Restore GUSBCFG and DCFG */
22255 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
22256 + core_if->gr_backup->gusbcfg_local);
22257 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
22258 + core_if->dr_backup->dcfg);
22259 +
22260 + /* De-assert Wakeup Logic */
22261 + gpwrdn.d32 = 0;
22262 + gpwrdn.b.pmuactv = 1;
22263 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22264 + dwc_udelay(10);
22265 +
22266 + if (!rem_wakeup) {
22267 + /* Set Device programming done bit */
22268 + dctl.b.pwronprgdone = 1;
22269 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
22270 + } else {
22271 + /* Start Remote Wakeup Signaling */
22272 + dctl.d32 = core_if->dr_backup->dctl;
22273 + dctl.b.rmtwkupsig = 1;
22274 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
22275 + }
22276 +
22277 + dwc_mdelay(2);
22278 + /* Clear all pending interupts */
22279 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
22280 +
22281 + /* Restore global registers */
22282 + dwc_otg_restore_global_regs(core_if);
22283 + /* Restore device global registers */
22284 + dwc_otg_restore_dev_regs(core_if, rem_wakeup);
22285 +
22286 + if (rem_wakeup) {
22287 + dwc_mdelay(7);
22288 + dctl.d32 = 0;
22289 + dctl.b.rmtwkupsig = 1;
22290 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
22291 + }
22292 +
22293 + core_if->hibernation_suspend = 0;
22294 + /* The core will be in ON STATE */
22295 + core_if->lx_state = DWC_OTG_L0;
22296 + DWC_PRINTF("Hibernation recovery completes here\n");
22297 +
22298 + return 1;
22299 +}
22300 +
22301 +/*
22302 + * The restore operation is modified to support Synopsys Emulated Powerdown and
22303 + * Hibernation. This function is for exiting from Host mode hibernation by
22304 + * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
22305 + * @param core_if Programming view of DWC_otg controller.
22306 + * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
22307 + * @param reset - indicates whether resume is initiated by Reset.
22308 + */
22309 +int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,
22310 + int rem_wakeup, int reset)
22311 +{
22312 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
22313 + hprt0_data_t hprt0 = {.d32 = 0 };
22314 +
22315 + int timeout = 2000;
22316 +
22317 + DWC_DEBUGPL(DBG_HCD, "%s called\n", __FUNCTION__);
22318 + /* Switch-on voltage to the core */
22319 + gpwrdn.b.pwrdnswtch = 1;
22320 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22321 + dwc_udelay(10);
22322 +
22323 + /* Reset core */
22324 + gpwrdn.d32 = 0;
22325 + gpwrdn.b.pwrdnrstn = 1;
22326 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22327 + dwc_udelay(10);
22328 +
22329 + /* Assert Restore signal */
22330 + gpwrdn.d32 = 0;
22331 + gpwrdn.b.restore = 1;
22332 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
22333 + dwc_udelay(10);
22334 +
22335 + /* Disable power clamps */
22336 + gpwrdn.d32 = 0;
22337 + gpwrdn.b.pwrdnclmp = 1;
22338 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22339 +
22340 + if (!rem_wakeup) {
22341 + dwc_udelay(50);
22342 + }
22343 +
22344 + /* Deassert Reset core */
22345 + gpwrdn.d32 = 0;
22346 + gpwrdn.b.pwrdnrstn = 1;
22347 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
22348 + dwc_udelay(10);
22349 +
22350 + /* Disable PMU interrupt */
22351 + gpwrdn.d32 = 0;
22352 + gpwrdn.b.pmuintsel = 1;
22353 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22354 +
22355 + gpwrdn.d32 = 0;
22356 + gpwrdn.b.connect_det_msk = 1;
22357 + gpwrdn.b.srp_det_msk = 1;
22358 + gpwrdn.b.disconn_det_msk = 1;
22359 + gpwrdn.b.rst_det_msk = 1;
22360 + gpwrdn.b.lnstchng_msk = 1;
22361 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22362 +
22363 + /* Indicates that we are going out from hibernation */
22364 + core_if->hibernation_suspend = 0;
22365 +
22366 + /* Set Restore Essential Regs bit in PCGCCTL register */
22367 + restore_essential_regs(core_if, rem_wakeup, 1);
22368 +
22369 + /* Wait a little for seeing new value of variable hibernation_suspend if
22370 + * Restore done interrupt received before polling */
22371 + dwc_udelay(10);
22372 +
22373 + if (core_if->hibernation_suspend == 0) {
22374 + /* Wait For Restore_done Interrupt. This mechanism of polling the
22375 + * interrupt is introduced to avoid any possible race conditions
22376 + */
22377 + do {
22378 + gintsts_data_t gintsts;
22379 + gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
22380 + if (gintsts.b.restoredone) {
22381 + gintsts.d32 = 0;
22382 + gintsts.b.restoredone = 1;
22383 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
22384 + DWC_DEBUGPL(DBG_HCD,"Restore Done Interrupt seen\n");
22385 + break;
22386 + }
22387 + dwc_udelay(10);
22388 + } while (--timeout);
22389 + if (!timeout) {
22390 + DWC_WARN("Restore Done interrupt wasn't generated\n");
22391 + }
22392 + }
22393 +
22394 + /* Set the flag's value to 0 again after receiving restore done interrupt */
22395 + core_if->hibernation_suspend = 0;
22396 +
22397 + /* This step is not described in functional spec but if not wait for this
22398 + * delay, mismatch interrupts occurred because just after restore core is
22399 + * in Device mode(gintsts.curmode == 0) */
22400 + dwc_mdelay(100);
22401 +
22402 + /* Clear all pending interrupts */
22403 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
22404 +
22405 + /* De-assert Restore */
22406 + gpwrdn.d32 = 0;
22407 + gpwrdn.b.restore = 1;
22408 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22409 + dwc_udelay(10);
22410 +
22411 + /* Restore GUSBCFG and HCFG */
22412 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
22413 + core_if->gr_backup->gusbcfg_local);
22414 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
22415 + core_if->hr_backup->hcfg_local);
22416 +
22417 + /* De-assert Wakeup Logic */
22418 + gpwrdn.d32 = 0;
22419 + gpwrdn.b.pmuactv = 1;
22420 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22421 + dwc_udelay(10);
22422 +
22423 + /* Start the Resume operation by programming HPRT0 */
22424 + hprt0.d32 = core_if->hr_backup->hprt0_local;
22425 + hprt0.b.prtpwr = 1;
22426 + hprt0.b.prtena = 0;
22427 + hprt0.b.prtsusp = 0;
22428 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
22429 +
22430 + DWC_PRINTF("Resume Starts Now\n");
22431 + if (!reset) { // Indicates it is Resume Operation
22432 + hprt0.d32 = core_if->hr_backup->hprt0_local;
22433 + hprt0.b.prtres = 1;
22434 + hprt0.b.prtpwr = 1;
22435 + hprt0.b.prtena = 0;
22436 + hprt0.b.prtsusp = 0;
22437 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
22438 +
22439 + if (!rem_wakeup)
22440 + hprt0.b.prtres = 0;
22441 + /* Wait for Resume time and then program HPRT again */
22442 + dwc_mdelay(100);
22443 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
22444 +
22445 + } else { // Indicates it is Reset Operation
22446 + hprt0.d32 = core_if->hr_backup->hprt0_local;
22447 + hprt0.b.prtrst = 1;
22448 + hprt0.b.prtpwr = 1;
22449 + hprt0.b.prtena = 0;
22450 + hprt0.b.prtsusp = 0;
22451 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
22452 + /* Wait for Reset time and then program HPRT again */
22453 + dwc_mdelay(60);
22454 + hprt0.b.prtrst = 0;
22455 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
22456 + }
22457 + /* Clear all interrupt status */
22458 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
22459 + hprt0.b.prtconndet = 1;
22460 + hprt0.b.prtenchng = 1;
22461 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
22462 +
22463 + /* Clear all pending interupts */
22464 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
22465 +
22466 + /* Restore global registers */
22467 + dwc_otg_restore_global_regs(core_if);
22468 + /* Restore host global registers */
22469 + dwc_otg_restore_host_regs(core_if, reset);
22470 +
22471 + /* The core will be in ON STATE */
22472 + core_if->lx_state = DWC_OTG_L0;
22473 + DWC_PRINTF("Hibernation recovery is complete here\n");
22474 + return 0;
22475 +}
22476 +
22477 +/** Saves some register values into system memory. */
22478 +int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if)
22479 +{
22480 + struct dwc_otg_global_regs_backup *gr;
22481 + int i;
22482 +
22483 + gr = core_if->gr_backup;
22484 + if (!gr) {
22485 + gr = DWC_ALLOC(sizeof(*gr));
22486 + if (!gr) {
22487 + return -DWC_E_NO_MEMORY;
22488 + }
22489 + core_if->gr_backup = gr;
22490 + }
22491 +
22492 + gr->gotgctl_local = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
22493 + gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
22494 + gr->gahbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);
22495 + gr->gusbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
22496 + gr->grxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
22497 + gr->gnptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
22498 + gr->hptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
22499 +#ifdef CONFIG_USB_DWC_OTG_LPM
22500 + gr->glpmcfg_local = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
22501 +#endif
22502 + gr->gi2cctl_local = DWC_READ_REG32(&core_if->core_global_regs->gi2cctl);
22503 + gr->pcgcctl_local = DWC_READ_REG32(core_if->pcgcctl);
22504 + gr->gdfifocfg_local =
22505 + DWC_READ_REG32(&core_if->core_global_regs->gdfifocfg);
22506 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
22507 + gr->dtxfsiz_local[i] =
22508 + DWC_READ_REG32(&(core_if->core_global_regs->dtxfsiz[i]));
22509 + }
22510 +
22511 + DWC_DEBUGPL(DBG_ANY, "===========Backing Global registers==========\n");
22512 + DWC_DEBUGPL(DBG_ANY, "Backed up gotgctl = %08x\n", gr->gotgctl_local);
22513 + DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk = %08x\n", gr->gintmsk_local);
22514 + DWC_DEBUGPL(DBG_ANY, "Backed up gahbcfg = %08x\n", gr->gahbcfg_local);
22515 + DWC_DEBUGPL(DBG_ANY, "Backed up gusbcfg = %08x\n", gr->gusbcfg_local);
22516 + DWC_DEBUGPL(DBG_ANY, "Backed up grxfsiz = %08x\n", gr->grxfsiz_local);
22517 + DWC_DEBUGPL(DBG_ANY, "Backed up gnptxfsiz = %08x\n",
22518 + gr->gnptxfsiz_local);
22519 + DWC_DEBUGPL(DBG_ANY, "Backed up hptxfsiz = %08x\n",
22520 + gr->hptxfsiz_local);
22521 +#ifdef CONFIG_USB_DWC_OTG_LPM
22522 + DWC_DEBUGPL(DBG_ANY, "Backed up glpmcfg = %08x\n", gr->glpmcfg_local);
22523 +#endif
22524 + DWC_DEBUGPL(DBG_ANY, "Backed up gi2cctl = %08x\n", gr->gi2cctl_local);
22525 + DWC_DEBUGPL(DBG_ANY, "Backed up pcgcctl = %08x\n", gr->pcgcctl_local);
22526 + DWC_DEBUGPL(DBG_ANY,"Backed up gdfifocfg = %08x\n",gr->gdfifocfg_local);
22527 +
22528 + return 0;
22529 +}
22530 +
22531 +/** Saves GINTMSK register before setting the msk bits. */
22532 +int dwc_otg_save_gintmsk_reg(dwc_otg_core_if_t * core_if)
22533 +{
22534 + struct dwc_otg_global_regs_backup *gr;
22535 +
22536 + gr = core_if->gr_backup;
22537 + if (!gr) {
22538 + gr = DWC_ALLOC(sizeof(*gr));
22539 + if (!gr) {
22540 + return -DWC_E_NO_MEMORY;
22541 + }
22542 + core_if->gr_backup = gr;
22543 + }
22544 +
22545 + gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
22546 +
22547 + DWC_DEBUGPL(DBG_ANY,"=============Backing GINTMSK registers============\n");
22548 + DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk = %08x\n", gr->gintmsk_local);
22549 +
22550 + return 0;
22551 +}
22552 +
22553 +int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if)
22554 +{
22555 + struct dwc_otg_dev_regs_backup *dr;
22556 + int i;
22557 +
22558 + dr = core_if->dr_backup;
22559 + if (!dr) {
22560 + dr = DWC_ALLOC(sizeof(*dr));
22561 + if (!dr) {
22562 + return -DWC_E_NO_MEMORY;
22563 + }
22564 + core_if->dr_backup = dr;
22565 + }
22566 +
22567 + dr->dcfg = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
22568 + dr->dctl = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
22569 + dr->daintmsk =
22570 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
22571 + dr->diepmsk =
22572 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->diepmsk);
22573 + dr->doepmsk =
22574 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->doepmsk);
22575 +
22576 + for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
22577 + dr->diepctl[i] =
22578 + DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl);
22579 + dr->dieptsiz[i] =
22580 + DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz);
22581 + dr->diepdma[i] =
22582 + DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma);
22583 + }
22584 +
22585 + DWC_DEBUGPL(DBG_ANY,
22586 + "=============Backing Host registers==============\n");
22587 + DWC_DEBUGPL(DBG_ANY, "Backed up dcfg = %08x\n", dr->dcfg);
22588 + DWC_DEBUGPL(DBG_ANY, "Backed up dctl = %08x\n", dr->dctl);
22589 + DWC_DEBUGPL(DBG_ANY, "Backed up daintmsk = %08x\n",
22590 + dr->daintmsk);
22591 + DWC_DEBUGPL(DBG_ANY, "Backed up diepmsk = %08x\n", dr->diepmsk);
22592 + DWC_DEBUGPL(DBG_ANY, "Backed up doepmsk = %08x\n", dr->doepmsk);
22593 + for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
22594 + DWC_DEBUGPL(DBG_ANY, "Backed up diepctl[%d] = %08x\n", i,
22595 + dr->diepctl[i]);
22596 + DWC_DEBUGPL(DBG_ANY, "Backed up dieptsiz[%d] = %08x\n",
22597 + i, dr->dieptsiz[i]);
22598 + DWC_DEBUGPL(DBG_ANY, "Backed up diepdma[%d] = %08x\n", i,
22599 + dr->diepdma[i]);
22600 + }
22601 +
22602 + return 0;
22603 +}
22604 +
22605 +int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if)
22606 +{
22607 + struct dwc_otg_host_regs_backup *hr;
22608 + int i;
22609 +
22610 + hr = core_if->hr_backup;
22611 + if (!hr) {
22612 + hr = DWC_ALLOC(sizeof(*hr));
22613 + if (!hr) {
22614 + return -DWC_E_NO_MEMORY;
22615 + }
22616 + core_if->hr_backup = hr;
22617 + }
22618 +
22619 + hr->hcfg_local =
22620 + DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
22621 + hr->haintmsk_local =
22622 + DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk);
22623 + for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
22624 + hr->hcintmsk_local[i] =
22625 + DWC_READ_REG32(&core_if->host_if->hc_regs[i]->hcintmsk);
22626 + }
22627 + hr->hprt0_local = DWC_READ_REG32(core_if->host_if->hprt0);
22628 + hr->hfir_local =
22629 + DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
22630 +
22631 + DWC_DEBUGPL(DBG_ANY,
22632 + "=============Backing Host registers===============\n");
22633 + DWC_DEBUGPL(DBG_ANY, "Backed up hcfg = %08x\n",
22634 + hr->hcfg_local);
22635 + DWC_DEBUGPL(DBG_ANY, "Backed up haintmsk = %08x\n", hr->haintmsk_local);
22636 + for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
22637 + DWC_DEBUGPL(DBG_ANY, "Backed up hcintmsk[%02d]=%08x\n", i,
22638 + hr->hcintmsk_local[i]);
22639 + }
22640 + DWC_DEBUGPL(DBG_ANY, "Backed up hprt0 = %08x\n",
22641 + hr->hprt0_local);
22642 + DWC_DEBUGPL(DBG_ANY, "Backed up hfir = %08x\n",
22643 + hr->hfir_local);
22644 +
22645 + return 0;
22646 +}
22647 +
22648 +int dwc_otg_restore_global_regs(dwc_otg_core_if_t *core_if)
22649 +{
22650 + struct dwc_otg_global_regs_backup *gr;
22651 + int i;
22652 +
22653 + gr = core_if->gr_backup;
22654 + if (!gr) {
22655 + return -DWC_E_INVALID;
22656 + }
22657 +
22658 + DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, gr->gotgctl_local);
22659 + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gr->gintmsk_local);
22660 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gr->gusbcfg_local);
22661 + DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gr->gahbcfg_local);
22662 + DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, gr->grxfsiz_local);
22663 + DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz,
22664 + gr->gnptxfsiz_local);
22665 + DWC_WRITE_REG32(&core_if->core_global_regs->hptxfsiz,
22666 + gr->hptxfsiz_local);
22667 + DWC_WRITE_REG32(&core_if->core_global_regs->gdfifocfg,
22668 + gr->gdfifocfg_local);
22669 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
22670 + DWC_WRITE_REG32(&core_if->core_global_regs->dtxfsiz[i],
22671 + gr->dtxfsiz_local[i]);
22672 + }
22673 +
22674 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
22675 + DWC_WRITE_REG32(core_if->host_if->hprt0, 0x0000100A);
22676 + DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg,
22677 + (gr->gahbcfg_local));
22678 + return 0;
22679 +}
22680 +
22681 +int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if, int rem_wakeup)
22682 +{
22683 + struct dwc_otg_dev_regs_backup *dr;
22684 + int i;
22685 +
22686 + dr = core_if->dr_backup;
22687 +
22688 + if (!dr) {
22689 + return -DWC_E_INVALID;
22690 + }
22691 +
22692 + if (!rem_wakeup) {
22693 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
22694 + dr->dctl);
22695 + }
22696 +
22697 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, dr->daintmsk);
22698 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, dr->diepmsk);
22699 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, dr->doepmsk);
22700 +
22701 + for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
22702 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz, dr->dieptsiz[i]);
22703 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma, dr->diepdma[i]);
22704 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl, dr->diepctl[i]);
22705 + }
22706 +
22707 + return 0;
22708 +}
22709 +
22710 +int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset)
22711 +{
22712 + struct dwc_otg_host_regs_backup *hr;
22713 + int i;
22714 + hr = core_if->hr_backup;
22715 +
22716 + if (!hr) {
22717 + return -DWC_E_INVALID;
22718 + }
22719 +
22720 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hr->hcfg_local);
22721 + //if (!reset)
22722 + //{
22723 + // DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hr->hfir_local);
22724 + //}
22725 +
22726 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk,
22727 + hr->haintmsk_local);
22728 + for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
22729 + DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk,
22730 + hr->hcintmsk_local[i]);
22731 + }
22732 +
22733 + return 0;
22734 +}
22735 +
22736 +int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if)
22737 +{
22738 + struct dwc_otg_global_regs_backup *gr;
22739 +
22740 + gr = core_if->gr_backup;
22741 +
22742 + /* Restore values for LPM and I2C */
22743 +#ifdef CONFIG_USB_DWC_OTG_LPM
22744 + DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, gr->glpmcfg_local);
22745 +#endif
22746 + DWC_WRITE_REG32(&core_if->core_global_regs->gi2cctl, gr->gi2cctl_local);
22747 +
22748 + return 0;
22749 +}
22750 +
22751 +int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode, int is_host)
22752 +{
22753 + struct dwc_otg_global_regs_backup *gr;
22754 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
22755 + gahbcfg_data_t gahbcfg = {.d32 = 0 };
22756 + gusbcfg_data_t gusbcfg = {.d32 = 0 };
22757 + gintmsk_data_t gintmsk = {.d32 = 0 };
22758 +
22759 + /* Restore LPM and I2C registers */
22760 + restore_lpm_i2c_regs(core_if);
22761 +
22762 + /* Set PCGCCTL to 0 */
22763 + DWC_WRITE_REG32(core_if->pcgcctl, 0x00000000);
22764 +
22765 + gr = core_if->gr_backup;
22766 + /* Load restore values for [31:14] bits */
22767 + DWC_WRITE_REG32(core_if->pcgcctl,
22768 + ((gr->pcgcctl_local & 0xffffc000) | 0x00020000));
22769 +
22770 + /* Umnask global Interrupt in GAHBCFG and restore it */
22771 + gahbcfg.d32 = gr->gahbcfg_local;
22772 + gahbcfg.b.glblintrmsk = 1;
22773 + DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32);
22774 +
22775 + /* Clear all pending interupts */
22776 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
22777 +
22778 + /* Unmask restore done interrupt */
22779 + gintmsk.b.restoredone = 1;
22780 + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
22781 +
22782 + /* Restore GUSBCFG and HCFG/DCFG */
22783 + gusbcfg.d32 = core_if->gr_backup->gusbcfg_local;
22784 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
22785 +
22786 + if (is_host) {
22787 + hcfg_data_t hcfg = {.d32 = 0 };
22788 + hcfg.d32 = core_if->hr_backup->hcfg_local;
22789 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
22790 + hcfg.d32);
22791 +
22792 + /* Load restore values for [31:14] bits */
22793 + pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
22794 + pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
22795 +
22796 + if (rmode)
22797 + pcgcctl.b.restoremode = 1;
22798 + DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
22799 + dwc_udelay(10);
22800 +
22801 + /* Load restore values for [31:14] bits and set EssRegRestored bit */
22802 + pcgcctl.d32 = gr->pcgcctl_local | 0xffffc000;
22803 + pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
22804 + pcgcctl.b.ess_reg_restored = 1;
22805 + if (rmode)
22806 + pcgcctl.b.restoremode = 1;
22807 + DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
22808 + } else {
22809 + dcfg_data_t dcfg = {.d32 = 0 };
22810 + dcfg.d32 = core_if->dr_backup->dcfg;
22811 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
22812 +
22813 + /* Load restore values for [31:14] bits */
22814 + pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
22815 + pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
22816 + if (!rmode) {
22817 + pcgcctl.d32 |= 0x208;
22818 + }
22819 + DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
22820 + dwc_udelay(10);
22821 +
22822 + /* Load restore values for [31:14] bits */
22823 + pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
22824 + pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
22825 + pcgcctl.b.ess_reg_restored = 1;
22826 + if (!rmode)
22827 + pcgcctl.d32 |= 0x208;
22828 + DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
22829 + }
22830 +
22831 + return 0;
22832 +}
22833 +
22834 +/**
22835 + * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY
22836 + * type.
22837 + */
22838 +static void init_fslspclksel(dwc_otg_core_if_t * core_if)
22839 +{
22840 + uint32_t val;
22841 + hcfg_data_t hcfg;
22842 +
22843 + if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
22844 + (core_if->hwcfg2.b.fs_phy_type == 1) &&
22845 + (core_if->core_params->ulpi_fs_ls)) ||
22846 + (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
22847 + /* Full speed PHY */
22848 + val = DWC_HCFG_48_MHZ;
22849 + } else {
22850 + /* High speed PHY running at full speed or high speed */
22851 + val = DWC_HCFG_30_60_MHZ;
22852 + }
22853 +
22854 + DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val);
22855 + hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
22856 + hcfg.b.fslspclksel = val;
22857 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
22858 +}
22859 +
22860 +/**
22861 + * Initializes the DevSpd field of the DCFG register depending on the PHY type
22862 + * and the enumeration speed of the device.
22863 + */
22864 +static void init_devspd(dwc_otg_core_if_t * core_if)
22865 +{
22866 + uint32_t val;
22867 + dcfg_data_t dcfg;
22868 +
22869 + if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
22870 + (core_if->hwcfg2.b.fs_phy_type == 1) &&
22871 + (core_if->core_params->ulpi_fs_ls)) ||
22872 + (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
22873 + /* Full speed PHY */
22874 + val = 0x3;
22875 + } else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
22876 + /* High speed PHY running at full speed */
22877 + val = 0x1;
22878 + } else {
22879 + /* High speed PHY running at high speed */
22880 + val = 0x0;
22881 + }
22882 +
22883 + DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
22884 +
22885 + dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
22886 + dcfg.b.devspd = val;
22887 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
22888 +}
22889 +
22890 +/**
22891 + * This function calculates the number of IN EPS
22892 + * using GHWCFG1 and GHWCFG2 registers values
22893 + *
22894 + * @param core_if Programming view of the DWC_otg controller
22895 + */
22896 +static uint32_t calc_num_in_eps(dwc_otg_core_if_t * core_if)
22897 +{
22898 + uint32_t num_in_eps = 0;
22899 + uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
22900 + uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3;
22901 + uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps;
22902 + int i;
22903 +
22904 + for (i = 0; i < num_eps; ++i) {
22905 + if (!(hwcfg1 & 0x1))
22906 + num_in_eps++;
22907 +
22908 + hwcfg1 >>= 2;
22909 + }
22910 +
22911 + if (core_if->hwcfg4.b.ded_fifo_en) {
22912 + num_in_eps =
22913 + (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
22914 + }
22915 +
22916 + return num_in_eps;
22917 +}
22918 +
22919 +/**
22920 + * This function calculates the number of OUT EPS
22921 + * using GHWCFG1 and GHWCFG2 registers values
22922 + *
22923 + * @param core_if Programming view of the DWC_otg controller
22924 + */
22925 +static uint32_t calc_num_out_eps(dwc_otg_core_if_t * core_if)
22926 +{
22927 + uint32_t num_out_eps = 0;
22928 + uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
22929 + uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2;
22930 + int i;
22931 +
22932 + for (i = 0; i < num_eps; ++i) {
22933 + if (!(hwcfg1 & 0x1))
22934 + num_out_eps++;
22935 +
22936 + hwcfg1 >>= 2;
22937 + }
22938 + return num_out_eps;
22939 +}
22940 +
22941 +/**
22942 + * This function initializes the DWC_otg controller registers and
22943 + * prepares the core for device mode or host mode operation.
22944 + *
22945 + * @param core_if Programming view of the DWC_otg controller
22946 + *
22947 + */
22948 +void dwc_otg_core_init(dwc_otg_core_if_t * core_if)
22949 +{
22950 + int i = 0;
22951 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
22952 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
22953 + gahbcfg_data_t ahbcfg = {.d32 = 0 };
22954 + gusbcfg_data_t usbcfg = {.d32 = 0 };
22955 + gi2cctl_data_t i2cctl = {.d32 = 0 };
22956 +
22957 + DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p) regs at %p\n",
22958 + core_if, global_regs);
22959 +
22960 + /* Common Initialization */
22961 + usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
22962 +
22963 + /* Program the ULPI External VBUS bit if needed */
22964 + usbcfg.b.ulpi_ext_vbus_drv =
22965 + (core_if->core_params->phy_ulpi_ext_vbus ==
22966 + DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
22967 +
22968 + /* Set external TS Dline pulsing */
22969 + usbcfg.b.term_sel_dl_pulse =
22970 + (core_if->core_params->ts_dline == 1) ? 1 : 0;
22971 + DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
22972 +
22973 + /* Reset the Controller */
22974 + dwc_otg_core_reset(core_if);
22975 +
22976 + core_if->adp_enable = core_if->core_params->adp_supp_enable;
22977 + core_if->power_down = core_if->core_params->power_down;
22978 + core_if->otg_sts = 0;
22979 +
22980 + /* Initialize parameters from Hardware configuration registers. */
22981 + dev_if->num_in_eps = calc_num_in_eps(core_if);
22982 + dev_if->num_out_eps = calc_num_out_eps(core_if);
22983 +
22984 + DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",
22985 + core_if->hwcfg4.b.num_dev_perio_in_ep);
22986 +
22987 + for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
22988 + dev_if->perio_tx_fifo_size[i] =
22989 + DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
22990 + DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n",
22991 + i, dev_if->perio_tx_fifo_size[i]);
22992 + }
22993 +
22994 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
22995 + dev_if->tx_fifo_size[i] =
22996 + DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
22997 + DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n",
22998 + i, dev_if->tx_fifo_size[i]);
22999 + }
23000 +
23001 + core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth;
23002 + core_if->rx_fifo_size = DWC_READ_REG32(&global_regs->grxfsiz);
23003 + core_if->nperio_tx_fifo_size =
23004 + DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16;
23005 +
23006 + DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size);
23007 + DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size);
23008 + DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n",
23009 + core_if->nperio_tx_fifo_size);
23010 +
23011 + /* This programming sequence needs to happen in FS mode before any other
23012 + * programming occurs */
23013 + if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
23014 + (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
23015 + /* If FS mode with FS PHY */
23016 +
23017 + /* core_init() is now called on every switch so only call the
23018 + * following for the first time through. */
23019 + if (!core_if->phy_init_done) {
23020 + core_if->phy_init_done = 1;
23021 + DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
23022 + usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
23023 + usbcfg.b.physel = 1;
23024 + DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
23025 +
23026 + /* Reset after a PHY select */
23027 + dwc_otg_core_reset(core_if);
23028 + }
23029 +
23030 + /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
23031 + * do this on HNP Dev/Host mode switches (done in dev_init and
23032 + * host_init). */
23033 + if (dwc_otg_is_host_mode(core_if)) {
23034 + init_fslspclksel(core_if);
23035 + } else {
23036 + init_devspd(core_if);
23037 + }
23038 +
23039 + if (core_if->core_params->i2c_enable) {
23040 + DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
23041 + /* Program GUSBCFG.OtgUtmifsSel to I2C */
23042 + usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
23043 + usbcfg.b.otgutmifssel = 1;
23044 + DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
23045 +
23046 + /* Program GI2CCTL.I2CEn */
23047 + i2cctl.d32 = DWC_READ_REG32(&global_regs->gi2cctl);
23048 + i2cctl.b.i2cdevaddr = 1;
23049 + i2cctl.b.i2cen = 0;
23050 + DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
23051 + i2cctl.b.i2cen = 1;
23052 + DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
23053 + }
23054 +
23055 + } /* endif speed == DWC_SPEED_PARAM_FULL */
23056 + else {
23057 + /* High speed PHY. */
23058 + if (!core_if->phy_init_done) {
23059 + core_if->phy_init_done = 1;
23060 + /* HS PHY parameters. These parameters are preserved
23061 + * during soft reset so only program the first time. Do
23062 + * a soft reset immediately after setting phyif. */
23063 +
23064 + if (core_if->core_params->phy_type == 2) {
23065 + /* ULPI interface */
23066 + usbcfg.b.ulpi_utmi_sel = 1;
23067 + usbcfg.b.phyif = 0;
23068 + usbcfg.b.ddrsel =
23069 + core_if->core_params->phy_ulpi_ddr;
23070 + } else if (core_if->core_params->phy_type == 1) {
23071 + /* UTMI+ interface */
23072 + usbcfg.b.ulpi_utmi_sel = 0;
23073 + if (core_if->core_params->phy_utmi_width == 16) {
23074 + usbcfg.b.phyif = 1;
23075 +
23076 + } else {
23077 + usbcfg.b.phyif = 0;
23078 + }
23079 + } else {
23080 + DWC_ERROR("FS PHY TYPE\n");
23081 + }
23082 + DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
23083 + /* Reset after setting the PHY parameters */
23084 + dwc_otg_core_reset(core_if);
23085 + }
23086 + }
23087 +
23088 + if ((core_if->hwcfg2.b.hs_phy_type == 2) &&
23089 + (core_if->hwcfg2.b.fs_phy_type == 1) &&
23090 + (core_if->core_params->ulpi_fs_ls)) {
23091 + DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
23092 + usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
23093 + usbcfg.b.ulpi_fsls = 1;
23094 + usbcfg.b.ulpi_clk_sus_m = 1;
23095 + DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
23096 + } else {
23097 + usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
23098 + usbcfg.b.ulpi_fsls = 0;
23099 + usbcfg.b.ulpi_clk_sus_m = 0;
23100 + DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
23101 + }
23102 +
23103 + /* Program the GAHBCFG Register. */
23104 + switch (core_if->hwcfg2.b.architecture) {
23105 +
23106 + case DWC_SLAVE_ONLY_ARCH:
23107 + DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
23108 + ahbcfg.b.nptxfemplvl_txfemplvl =
23109 + DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
23110 + ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
23111 + core_if->dma_enable = 0;
23112 + core_if->dma_desc_enable = 0;
23113 + break;
23114 +
23115 + case DWC_EXT_DMA_ARCH:
23116 + DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
23117 + {
23118 + uint8_t brst_sz = core_if->core_params->dma_burst_size;
23119 + ahbcfg.b.hburstlen = 0;
23120 + while (brst_sz > 1) {
23121 + ahbcfg.b.hburstlen++;
23122 + brst_sz >>= 1;
23123 + }
23124 + }
23125 + core_if->dma_enable = (core_if->core_params->dma_enable != 0);
23126 + core_if->dma_desc_enable =
23127 + (core_if->core_params->dma_desc_enable != 0);
23128 + break;
23129 +
23130 + case DWC_INT_DMA_ARCH:
23131 + DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
23132 + /* Old value was DWC_GAHBCFG_INT_DMA_BURST_INCR - done for
23133 + Host mode ISOC in issue fix - vahrama */
23134 + /* Broadcom had altered to (1<<3)|(0<<0) - WRESP=1, max 4 beats */
23135 + ahbcfg.b.hburstlen = (1<<3)|(0<<0);//DWC_GAHBCFG_INT_DMA_BURST_INCR4;
23136 + core_if->dma_enable = (core_if->core_params->dma_enable != 0);
23137 + core_if->dma_desc_enable =
23138 + (core_if->core_params->dma_desc_enable != 0);
23139 + break;
23140 +
23141 + }
23142 + if (core_if->dma_enable) {
23143 + if (core_if->dma_desc_enable) {
23144 + DWC_PRINTF("Using Descriptor DMA mode\n");
23145 + } else {
23146 + DWC_PRINTF("Using Buffer DMA mode\n");
23147 +
23148 + }
23149 + } else {
23150 + DWC_PRINTF("Using Slave mode\n");
23151 + core_if->dma_desc_enable = 0;
23152 + }
23153 +
23154 + if (core_if->core_params->ahb_single) {
23155 + ahbcfg.b.ahbsingle = 1;
23156 + }
23157 +
23158 + ahbcfg.b.dmaenable = core_if->dma_enable;
23159 + DWC_WRITE_REG32(&global_regs->gahbcfg, ahbcfg.d32);
23160 +
23161 + core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en;
23162 +
23163 + core_if->pti_enh_enable = core_if->core_params->pti_enable != 0;
23164 + core_if->multiproc_int_enable = core_if->core_params->mpi_enable;
23165 + DWC_PRINTF("Periodic Transfer Interrupt Enhancement - %s\n",
23166 + ((core_if->pti_enh_enable) ? "enabled" : "disabled"));
23167 + DWC_PRINTF("Multiprocessor Interrupt Enhancement - %s\n",
23168 + ((core_if->multiproc_int_enable) ? "enabled" : "disabled"));
23169 +
23170 + /*
23171 + * Program the GUSBCFG register.
23172 + */
23173 + usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
23174 +
23175 + switch (core_if->hwcfg2.b.op_mode) {
23176 + case DWC_MODE_HNP_SRP_CAPABLE:
23177 + usbcfg.b.hnpcap = (core_if->core_params->otg_cap ==
23178 + DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
23179 + usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
23180 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
23181 + break;
23182 +
23183 + case DWC_MODE_SRP_ONLY_CAPABLE:
23184 + usbcfg.b.hnpcap = 0;
23185 + usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
23186 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
23187 + break;
23188 +
23189 + case DWC_MODE_NO_HNP_SRP_CAPABLE:
23190 + usbcfg.b.hnpcap = 0;
23191 + usbcfg.b.srpcap = 0;
23192 + break;
23193 +
23194 + case DWC_MODE_SRP_CAPABLE_DEVICE:
23195 + usbcfg.b.hnpcap = 0;
23196 + usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
23197 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
23198 + break;
23199 +
23200 + case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
23201 + usbcfg.b.hnpcap = 0;
23202 + usbcfg.b.srpcap = 0;
23203 + break;
23204 +
23205 + case DWC_MODE_SRP_CAPABLE_HOST:
23206 + usbcfg.b.hnpcap = 0;
23207 + usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
23208 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
23209 + break;
23210 +
23211 + case DWC_MODE_NO_SRP_CAPABLE_HOST:
23212 + usbcfg.b.hnpcap = 0;
23213 + usbcfg.b.srpcap = 0;
23214 + break;
23215 + }
23216 +
23217 + DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
23218 +
23219 +#ifdef CONFIG_USB_DWC_OTG_LPM
23220 + if (core_if->core_params->lpm_enable) {
23221 + glpmcfg_data_t lpmcfg = {.d32 = 0 };
23222 +
23223 + /* To enable LPM support set lpm_cap_en bit */
23224 + lpmcfg.b.lpm_cap_en = 1;
23225 +
23226 + /* Make AppL1Res ACK */
23227 + lpmcfg.b.appl_resp = 1;
23228 +
23229 + /* Retry 3 times */
23230 + lpmcfg.b.retry_count = 3;
23231 +
23232 + DWC_MODIFY_REG32(&core_if->core_global_regs->glpmcfg,
23233 + 0, lpmcfg.d32);
23234 +
23235 + }
23236 +#endif
23237 + if (core_if->core_params->ic_usb_cap) {
23238 + gusbcfg_data_t gusbcfg = {.d32 = 0 };
23239 + gusbcfg.b.ic_usb_cap = 1;
23240 + DWC_MODIFY_REG32(&core_if->core_global_regs->gusbcfg,
23241 + 0, gusbcfg.d32);
23242 + }
23243 + {
23244 + gotgctl_data_t gotgctl = {.d32 = 0 };
23245 + gotgctl.b.otgver = core_if->core_params->otg_ver;
23246 + DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, 0,
23247 + gotgctl.d32);
23248 + /* Set OTG version supported */
23249 + core_if->otg_ver = core_if->core_params->otg_ver;
23250 + DWC_PRINTF("OTG VER PARAM: %d, OTG VER FLAG: %d\n",
23251 + core_if->core_params->otg_ver, core_if->otg_ver);
23252 + }
23253 +
23254 +
23255 + /* Enable common interrupts */
23256 + dwc_otg_enable_common_interrupts(core_if);
23257 +
23258 + /* Do device or host intialization based on mode during PCD
23259 + * and HCD initialization */
23260 + if (dwc_otg_is_host_mode(core_if)) {
23261 + DWC_DEBUGPL(DBG_ANY, "Host Mode\n");
23262 + core_if->op_state = A_HOST;
23263 + } else {
23264 + DWC_DEBUGPL(DBG_ANY, "Device Mode\n");
23265 + core_if->op_state = B_PERIPHERAL;
23266 +#ifdef DWC_DEVICE_ONLY
23267 + dwc_otg_core_dev_init(core_if);
23268 +#endif
23269 + }
23270 +}
23271 +
23272 +/**
23273 + * This function enables the Device mode interrupts.
23274 + *
23275 + * @param core_if Programming view of DWC_otg controller
23276 + */
23277 +void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * core_if)
23278 +{
23279 + gintmsk_data_t intr_mask = {.d32 = 0 };
23280 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
23281 +
23282 + DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
23283 +
23284 + /* Disable all interrupts. */
23285 + DWC_WRITE_REG32(&global_regs->gintmsk, 0);
23286 +
23287 + /* Clear any pending interrupts */
23288 + DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
23289 +
23290 + /* Enable the common interrupts */
23291 + dwc_otg_enable_common_interrupts(core_if);
23292 +
23293 + /* Enable interrupts */
23294 + intr_mask.b.usbreset = 1;
23295 + intr_mask.b.enumdone = 1;
23296 + /* Disable Disconnect interrupt in Device mode */
23297 + intr_mask.b.disconnect = 0;
23298 +
23299 + if (!core_if->multiproc_int_enable) {
23300 + intr_mask.b.inepintr = 1;
23301 + intr_mask.b.outepintr = 1;
23302 + }
23303 +
23304 + intr_mask.b.erlysuspend = 1;
23305 +
23306 + if (core_if->en_multiple_tx_fifo == 0) {
23307 + intr_mask.b.epmismatch = 1;
23308 + }
23309 +
23310 + //intr_mask.b.incomplisoout = 1;
23311 + intr_mask.b.incomplisoin = 1;
23312 +
23313 +/* Enable the ignore frame number for ISOC xfers - MAS */
23314 +/* Disable to support high bandwith ISOC transfers - manukz */
23315 +#if 0
23316 +#ifdef DWC_UTE_PER_IO
23317 + if (core_if->dma_enable) {
23318 + if (core_if->dma_desc_enable) {
23319 + dctl_data_t dctl1 = {.d32 = 0 };
23320 + dctl1.b.ifrmnum = 1;
23321 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
23322 + dctl, 0, dctl1.d32);
23323 + DWC_DEBUG("----Enabled Ignore frame number (0x%08x)",
23324 + DWC_READ_REG32(&core_if->dev_if->
23325 + dev_global_regs->dctl));
23326 + }
23327 + }
23328 +#endif
23329 +#endif
23330 +#ifdef DWC_EN_ISOC
23331 + if (core_if->dma_enable) {
23332 + if (core_if->dma_desc_enable == 0) {
23333 + if (core_if->pti_enh_enable) {
23334 + dctl_data_t dctl = {.d32 = 0 };
23335 + dctl.b.ifrmnum = 1;
23336 + DWC_MODIFY_REG32(&core_if->
23337 + dev_if->dev_global_regs->dctl,
23338 + 0, dctl.d32);
23339 + } else {
23340 + intr_mask.b.incomplisoin = 1;
23341 + intr_mask.b.incomplisoout = 1;
23342 + }
23343 + }
23344 + } else {
23345 + intr_mask.b.incomplisoin = 1;
23346 + intr_mask.b.incomplisoout = 1;
23347 + }
23348 +#endif /* DWC_EN_ISOC */
23349 +
23350 + /** @todo NGS: Should this be a module parameter? */
23351 +#ifdef USE_PERIODIC_EP
23352 + intr_mask.b.isooutdrop = 1;
23353 + intr_mask.b.eopframe = 1;
23354 + intr_mask.b.incomplisoin = 1;
23355 + intr_mask.b.incomplisoout = 1;
23356 +#endif
23357 +
23358 + DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
23359 +
23360 + DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__,
23361 + DWC_READ_REG32(&global_regs->gintmsk));
23362 +}
23363 +
23364 +/**
23365 + * This function initializes the DWC_otg controller registers for
23366 + * device mode.
23367 + *
23368 + * @param core_if Programming view of DWC_otg controller
23369 + *
23370 + */
23371 +void dwc_otg_core_dev_init(dwc_otg_core_if_t * core_if)
23372 +{
23373 + int i;
23374 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
23375 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
23376 + dwc_otg_core_params_t *params = core_if->core_params;
23377 + dcfg_data_t dcfg = {.d32 = 0 };
23378 + depctl_data_t diepctl = {.d32 = 0 };
23379 + grstctl_t resetctl = {.d32 = 0 };
23380 + uint32_t rx_fifo_size;
23381 + fifosize_data_t nptxfifosize;
23382 + fifosize_data_t txfifosize;
23383 + dthrctl_data_t dthrctl;
23384 + fifosize_data_t ptxfifosize;
23385 + uint16_t rxfsiz, nptxfsiz;
23386 + gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
23387 + hwcfg3_data_t hwcfg3 = {.d32 = 0 };
23388 +
23389 + /* Restart the Phy Clock */
23390 + DWC_WRITE_REG32(core_if->pcgcctl, 0);
23391 +
23392 + /* Device configuration register */
23393 + init_devspd(core_if);
23394 + dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
23395 + dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0;
23396 + dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
23397 + /* Enable Device OUT NAK in case of DDMA mode*/
23398 + if (core_if->core_params->dev_out_nak) {
23399 + dcfg.b.endevoutnak = 1;
23400 + }
23401 +
23402 + if (core_if->core_params->cont_on_bna) {
23403 + dctl_data_t dctl = {.d32 = 0 };
23404 + dctl.b.encontonbna = 1;
23405 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
23406 + }
23407 +
23408 +
23409 + DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
23410 +
23411 + /* Configure data FIFO sizes */
23412 + if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
23413 + DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
23414 + core_if->total_fifo_size);
23415 + DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
23416 + params->dev_rx_fifo_size);
23417 + DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
23418 + params->dev_nperio_tx_fifo_size);
23419 +
23420 + /* Rx FIFO */
23421 + DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
23422 + DWC_READ_REG32(&global_regs->grxfsiz));
23423 +
23424 +#ifdef DWC_UTE_CFI
23425 + core_if->pwron_rxfsiz = DWC_READ_REG32(&global_regs->grxfsiz);
23426 + core_if->init_rxfsiz = params->dev_rx_fifo_size;
23427 +#endif
23428 + rx_fifo_size = params->dev_rx_fifo_size;
23429 + DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size);
23430 +
23431 + DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
23432 + DWC_READ_REG32(&global_regs->grxfsiz));
23433 +
23434 + /** Set Periodic Tx FIFO Mask all bits 0 */
23435 + core_if->p_tx_msk = 0;
23436 +
23437 + /** Set Tx FIFO Mask all bits 0 */
23438 + core_if->tx_msk = 0;
23439 +
23440 + if (core_if->en_multiple_tx_fifo == 0) {
23441 + /* Non-periodic Tx FIFO */
23442 + DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
23443 + DWC_READ_REG32(&global_regs->gnptxfsiz));
23444 +
23445 + nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
23446 + nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
23447 +
23448 + DWC_WRITE_REG32(&global_regs->gnptxfsiz,
23449 + nptxfifosize.d32);
23450 +
23451 + DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
23452 + DWC_READ_REG32(&global_regs->gnptxfsiz));
23453 +
23454 + /**@todo NGS: Fix Periodic FIFO Sizing! */
23455 + /*
23456 + * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.
23457 + * Indexes of the FIFO size module parameters in the
23458 + * dev_perio_tx_fifo_size array and the FIFO size registers in
23459 + * the dptxfsiz array run from 0 to 14.
23460 + */
23461 + /** @todo Finish debug of this */
23462 + ptxfifosize.b.startaddr =
23463 + nptxfifosize.b.startaddr + nptxfifosize.b.depth;
23464 + for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
23465 + ptxfifosize.b.depth =
23466 + params->dev_perio_tx_fifo_size[i];
23467 + DWC_DEBUGPL(DBG_CIL,
23468 + "initial dtxfsiz[%d]=%08x\n", i,
23469 + DWC_READ_REG32(&global_regs->dtxfsiz
23470 + [i]));
23471 + DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
23472 + ptxfifosize.d32);
23473 + DWC_DEBUGPL(DBG_CIL, "new dtxfsiz[%d]=%08x\n",
23474 + i,
23475 + DWC_READ_REG32(&global_regs->dtxfsiz
23476 + [i]));
23477 + ptxfifosize.b.startaddr += ptxfifosize.b.depth;
23478 + }
23479 + } else {
23480 + /*
23481 + * Tx FIFOs These FIFOs are numbered from 1 to 15.
23482 + * Indexes of the FIFO size module parameters in the
23483 + * dev_tx_fifo_size array and the FIFO size registers in
23484 + * the dtxfsiz array run from 0 to 14.
23485 + */
23486 +
23487 + /* Non-periodic Tx FIFO */
23488 + DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
23489 + DWC_READ_REG32(&global_regs->gnptxfsiz));
23490 +
23491 +#ifdef DWC_UTE_CFI
23492 + core_if->pwron_gnptxfsiz =
23493 + (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
23494 + core_if->init_gnptxfsiz =
23495 + params->dev_nperio_tx_fifo_size;
23496 +#endif
23497 + nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
23498 + nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
23499 +
23500 + DWC_WRITE_REG32(&global_regs->gnptxfsiz,
23501 + nptxfifosize.d32);
23502 +
23503 + DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
23504 + DWC_READ_REG32(&global_regs->gnptxfsiz));
23505 +
23506 + txfifosize.b.startaddr =
23507 + nptxfifosize.b.startaddr + nptxfifosize.b.depth;
23508 +
23509 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
23510 +
23511 + txfifosize.b.depth =
23512 + params->dev_tx_fifo_size[i];
23513 +
23514 + DWC_DEBUGPL(DBG_CIL,
23515 + "initial dtxfsiz[%d]=%08x\n",
23516 + i,
23517 + DWC_READ_REG32(&global_regs->dtxfsiz
23518 + [i]));
23519 +
23520 +#ifdef DWC_UTE_CFI
23521 + core_if->pwron_txfsiz[i] =
23522 + (DWC_READ_REG32
23523 + (&global_regs->dtxfsiz[i]) >> 16);
23524 + core_if->init_txfsiz[i] =
23525 + params->dev_tx_fifo_size[i];
23526 +#endif
23527 + DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
23528 + txfifosize.d32);
23529 +
23530 + DWC_DEBUGPL(DBG_CIL,
23531 + "new dtxfsiz[%d]=%08x\n",
23532 + i,
23533 + DWC_READ_REG32(&global_regs->dtxfsiz
23534 + [i]));
23535 +
23536 + txfifosize.b.startaddr += txfifosize.b.depth;
23537 + }
23538 + if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
23539 + /* Calculating DFIFOCFG for Device mode to include RxFIFO and NPTXFIFO */
23540 + gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
23541 + hwcfg3.d32 = DWC_READ_REG32(&global_regs->ghwcfg3);
23542 + gdfifocfg.b.gdfifocfg = (DWC_READ_REG32(&global_regs->ghwcfg3) >> 16);
23543 + DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
23544 + rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);
23545 + nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
23546 + gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz;
23547 + DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
23548 + }
23549 + }
23550 +
23551 + /* Flush the FIFOs */
23552 + dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */
23553 + dwc_otg_flush_rx_fifo(core_if);
23554 +
23555 + /* Flush the Learning Queue. */
23556 + resetctl.b.intknqflsh = 1;
23557 + DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
23558 +
23559 + if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
23560 + core_if->start_predict = 0;
23561 + for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) {
23562 + core_if->nextep_seq[i] = 0xff; // 0xff - EP not active
23563 + }
23564 + core_if->nextep_seq[0] = 0;
23565 + core_if->first_in_nextep_seq = 0;
23566 + diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
23567 + diepctl.b.nextep = 0;
23568 + DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
23569 +
23570 + /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */
23571 + dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
23572 + dcfg.b.epmscnt = 2;
23573 + DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
23574 +
23575 + DWC_DEBUGPL(DBG_CILV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
23576 + __func__, core_if->first_in_nextep_seq);
23577 + for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
23578 + DWC_DEBUGPL(DBG_CILV, "%2d ", core_if->nextep_seq[i]);
23579 + }
23580 + DWC_DEBUGPL(DBG_CILV,"\n");
23581 + }
23582 +
23583 + /* Clear all pending Device Interrupts */
23584 + /** @todo - if the condition needed to be checked
23585 + * or in any case all pending interrutps should be cleared?
23586 + */
23587 + if (core_if->multiproc_int_enable) {
23588 + for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
23589 + DWC_WRITE_REG32(&dev_if->
23590 + dev_global_regs->diepeachintmsk[i], 0);
23591 + }
23592 + }
23593 +
23594 + for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
23595 + DWC_WRITE_REG32(&dev_if->
23596 + dev_global_regs->doepeachintmsk[i], 0);
23597 + }
23598 +
23599 + DWC_WRITE_REG32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF);
23600 + DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk, 0);
23601 + } else {
23602 + DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, 0);
23603 + DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, 0);
23604 + DWC_WRITE_REG32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF);
23605 + DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk, 0);
23606 + }
23607 +
23608 + for (i = 0; i <= dev_if->num_in_eps; i++) {
23609 + depctl_data_t depctl;
23610 + depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
23611 + if (depctl.b.epena) {
23612 + depctl.d32 = 0;
23613 + depctl.b.epdis = 1;
23614 + depctl.b.snak = 1;
23615 + } else {
23616 + depctl.d32 = 0;
23617 + }
23618 +
23619 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
23620 +
23621 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, 0);
23622 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, 0);
23623 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepint, 0xFF);
23624 + }
23625 +
23626 + for (i = 0; i <= dev_if->num_out_eps; i++) {
23627 + depctl_data_t depctl;
23628 + depctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
23629 + if (depctl.b.epena) {
23630 + dctl_data_t dctl = {.d32 = 0 };
23631 + gintmsk_data_t gintsts = {.d32 = 0 };
23632 + doepint_data_t doepint = {.d32 = 0 };
23633 + dctl.b.sgoutnak = 1;
23634 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
23635 + do {
23636 + dwc_udelay(10);
23637 + gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
23638 + } while (!gintsts.b.goutnakeff);
23639 + gintsts.d32 = 0;
23640 + gintsts.b.goutnakeff = 1;
23641 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
23642 +
23643 + depctl.d32 = 0;
23644 + depctl.b.epdis = 1;
23645 + depctl.b.snak = 1;
23646 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepctl, depctl.d32);
23647 + do {
23648 + dwc_udelay(10);
23649 + doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
23650 + out_ep_regs[i]->doepint);
23651 + } while (!doepint.b.epdisabled);
23652 +
23653 + doepint.b.epdisabled = 1;
23654 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepint, doepint.d32);
23655 +
23656 + dctl.d32 = 0;
23657 + dctl.b.cgoutnak = 1;
23658 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
23659 + } else {
23660 + depctl.d32 = 0;
23661 + }
23662 +
23663 + DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32);
23664 +
23665 + DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doeptsiz, 0);
23666 + DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepdma, 0);
23667 + DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepint, 0xFF);
23668 + }
23669 +
23670 + if (core_if->en_multiple_tx_fifo && core_if->dma_enable) {
23671 + dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1;
23672 + dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1;
23673 + dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1;
23674 +
23675 + dev_if->rx_thr_length = params->rx_thr_length;
23676 + dev_if->tx_thr_length = params->tx_thr_length;
23677 +
23678 + dev_if->setup_desc_index = 0;
23679 +
23680 + dthrctl.d32 = 0;
23681 + dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en;
23682 + dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en;
23683 + dthrctl.b.tx_thr_len = dev_if->tx_thr_length;
23684 + dthrctl.b.rx_thr_en = dev_if->rx_thr_en;
23685 + dthrctl.b.rx_thr_len = dev_if->rx_thr_length;
23686 + dthrctl.b.ahb_thr_ratio = params->ahb_thr_ratio;
23687 +
23688 + DWC_WRITE_REG32(&dev_if->dev_global_regs->dtknqr3_dthrctl,
23689 + dthrctl.d32);
23690 +
23691 + DWC_DEBUGPL(DBG_CIL,
23692 + "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n",
23693 + dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en,
23694 + dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len,
23695 + dthrctl.b.rx_thr_len);
23696 +
23697 + }
23698 +
23699 + dwc_otg_enable_device_interrupts(core_if);
23700 +
23701 + {
23702 + diepmsk_data_t msk = {.d32 = 0 };
23703 + msk.b.txfifoundrn = 1;
23704 + if (core_if->multiproc_int_enable) {
23705 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->
23706 + diepeachintmsk[0], msk.d32, msk.d32);
23707 + } else {
23708 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk,
23709 + msk.d32, msk.d32);
23710 + }
23711 + }
23712 +
23713 + if (core_if->multiproc_int_enable) {
23714 + /* Set NAK on Babble */
23715 + dctl_data_t dctl = {.d32 = 0 };
23716 + dctl.b.nakonbble = 1;
23717 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
23718 + }
23719 +
23720 + if (core_if->snpsid >= OTG_CORE_REV_2_94a) {
23721 + dctl_data_t dctl = {.d32 = 0 };
23722 + dctl.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dctl);
23723 + dctl.b.sftdiscon = 0;
23724 + DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl, dctl.d32);
23725 + }
23726 +}
23727 +
23728 +/**
23729 + * This function enables the Host mode interrupts.
23730 + *
23731 + * @param core_if Programming view of DWC_otg controller
23732 + */
23733 +void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * core_if)
23734 +{
23735 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
23736 + gintmsk_data_t intr_mask = {.d32 = 0 };
23737 +
23738 + DWC_DEBUGPL(DBG_CIL, "%s(%p)\n", __func__, core_if);
23739 +
23740 + /* Disable all interrupts. */
23741 + DWC_WRITE_REG32(&global_regs->gintmsk, 0);
23742 +
23743 + /* Clear any pending interrupts. */
23744 + DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
23745 +
23746 + /* Enable the common interrupts */
23747 + dwc_otg_enable_common_interrupts(core_if);
23748 +
23749 + /*
23750 + * Enable host mode interrupts without disturbing common
23751 + * interrupts.
23752 + */
23753 +
23754 + intr_mask.b.disconnect = 1;
23755 + intr_mask.b.portintr = 1;
23756 + intr_mask.b.hcintr = 1;
23757 +
23758 + DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
23759 +}
23760 +
23761 +/**
23762 + * This function disables the Host Mode interrupts.
23763 + *
23764 + * @param core_if Programming view of DWC_otg controller
23765 + */
23766 +void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * core_if)
23767 +{
23768 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
23769 + gintmsk_data_t intr_mask = {.d32 = 0 };
23770 +
23771 + DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__);
23772 +
23773 + /*
23774 + * Disable host mode interrupts without disturbing common
23775 + * interrupts.
23776 + */
23777 + intr_mask.b.sofintr = 1;
23778 + intr_mask.b.portintr = 1;
23779 + intr_mask.b.hcintr = 1;
23780 + intr_mask.b.ptxfempty = 1;
23781 + intr_mask.b.nptxfempty = 1;
23782 +
23783 + DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, 0);
23784 +}
23785 +
23786 +/**
23787 + * This function initializes the DWC_otg controller registers for
23788 + * host mode.
23789 + *
23790 + * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
23791 + * request queues. Host channels are reset to ensure that they are ready for
23792 + * performing transfers.
23793 + *
23794 + * @param core_if Programming view of DWC_otg controller
23795 + *
23796 + */
23797 +void dwc_otg_core_host_init(dwc_otg_core_if_t * core_if)
23798 +{
23799 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
23800 + dwc_otg_host_if_t *host_if = core_if->host_if;
23801 + dwc_otg_core_params_t *params = core_if->core_params;
23802 + hprt0_data_t hprt0 = {.d32 = 0 };
23803 + fifosize_data_t nptxfifosize;
23804 + fifosize_data_t ptxfifosize;
23805 + uint16_t rxfsiz, nptxfsiz, hptxfsiz;
23806 + gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
23807 + int i;
23808 + hcchar_data_t hcchar;
23809 + hcfg_data_t hcfg;
23810 + hfir_data_t hfir;
23811 + dwc_otg_hc_regs_t *hc_regs;
23812 + int num_channels;
23813 + gotgctl_data_t gotgctl = {.d32 = 0 };
23814 +
23815 + DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
23816 +
23817 + /* Restart the Phy Clock */
23818 + DWC_WRITE_REG32(core_if->pcgcctl, 0);
23819 +
23820 + /* Initialize Host Configuration Register */
23821 + init_fslspclksel(core_if);
23822 + if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
23823 + hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
23824 + hcfg.b.fslssupp = 1;
23825 + DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
23826 +
23827 + }
23828 +
23829 + /* This bit allows dynamic reloading of the HFIR register
23830 + * during runtime. This bit needs to be programmed during
23831 + * initial configuration and its value must not be changed
23832 + * during runtime.*/
23833 + if (core_if->core_params->reload_ctl == 1) {
23834 + hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
23835 + hfir.b.hfirrldctrl = 1;
23836 + DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
23837 + }
23838 +
23839 + if (core_if->core_params->dma_desc_enable) {
23840 + uint8_t op_mode = core_if->hwcfg2.b.op_mode;
23841 + if (!
23842 + (core_if->hwcfg4.b.desc_dma
23843 + && (core_if->snpsid >= OTG_CORE_REV_2_90a)
23844 + && ((op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
23845 + || (op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
23846 + || (op_mode ==
23847 + DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG)
23848 + || (op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)
23849 + || (op_mode ==
23850 + DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST)))) {
23851 +
23852 + DWC_ERROR("Host can't operate in Descriptor DMA mode.\n"
23853 + "Either core version is below 2.90a or "
23854 + "GHWCFG2, GHWCFG4 registers' values do not allow Descriptor DMA in host mode.\n"
23855 + "To run the driver in Buffer DMA host mode set dma_desc_enable "
23856 + "module parameter to 0.\n");
23857 + return;
23858 + }
23859 + hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
23860 + hcfg.b.descdma = 1;
23861 + DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
23862 + }
23863 +
23864 + /* Configure data FIFO sizes */
23865 + if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
23866 + DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
23867 + core_if->total_fifo_size);
23868 + DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
23869 + params->host_rx_fifo_size);
23870 + DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
23871 + params->host_nperio_tx_fifo_size);
23872 + DWC_DEBUGPL(DBG_CIL, "P Tx FIFO Size=%d\n",
23873 + params->host_perio_tx_fifo_size);
23874 +
23875 + /* Rx FIFO */
23876 + DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
23877 + DWC_READ_REG32(&global_regs->grxfsiz));
23878 + DWC_WRITE_REG32(&global_regs->grxfsiz,
23879 + params->host_rx_fifo_size);
23880 + DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
23881 + DWC_READ_REG32(&global_regs->grxfsiz));
23882 +
23883 + /* Non-periodic Tx FIFO */
23884 + DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
23885 + DWC_READ_REG32(&global_regs->gnptxfsiz));
23886 + nptxfifosize.b.depth = params->host_nperio_tx_fifo_size;
23887 + nptxfifosize.b.startaddr = params->host_rx_fifo_size;
23888 + DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);
23889 + DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
23890 + DWC_READ_REG32(&global_regs->gnptxfsiz));
23891 +
23892 + /* Periodic Tx FIFO */
23893 + DWC_DEBUGPL(DBG_CIL, "initial hptxfsiz=%08x\n",
23894 + DWC_READ_REG32(&global_regs->hptxfsiz));
23895 + ptxfifosize.b.depth = params->host_perio_tx_fifo_size;
23896 + ptxfifosize.b.startaddr =
23897 + nptxfifosize.b.startaddr + nptxfifosize.b.depth;
23898 + DWC_WRITE_REG32(&global_regs->hptxfsiz, ptxfifosize.d32);
23899 + DWC_DEBUGPL(DBG_CIL, "new hptxfsiz=%08x\n",
23900 + DWC_READ_REG32(&global_regs->hptxfsiz));
23901 +
23902 + if (core_if->en_multiple_tx_fifo
23903 + && core_if->snpsid <= OTG_CORE_REV_2_94a) {
23904 + /* Global DFIFOCFG calculation for Host mode - include RxFIFO, NPTXFIFO and HPTXFIFO */
23905 + gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
23906 + rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);
23907 + nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
23908 + hptxfsiz = (DWC_READ_REG32(&global_regs->hptxfsiz) >> 16);
23909 + gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz + hptxfsiz;
23910 + DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
23911 + }
23912 + }
23913 +
23914 + /* TODO - check this */
23915 + /* Clear Host Set HNP Enable in the OTG Control Register */
23916 + gotgctl.b.hstsethnpen = 1;
23917 + DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
23918 + /* Make sure the FIFOs are flushed. */
23919 + dwc_otg_flush_tx_fifo(core_if, 0x10 /* all TX FIFOs */ );
23920 + dwc_otg_flush_rx_fifo(core_if);
23921 +
23922 + /* Clear Host Set HNP Enable in the OTG Control Register */
23923 + gotgctl.b.hstsethnpen = 1;
23924 + DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
23925 +
23926 + if (!core_if->core_params->dma_desc_enable) {
23927 + /* Flush out any leftover queued requests. */
23928 + num_channels = core_if->core_params->host_channels;
23929 +
23930 + for (i = 0; i < num_channels; i++) {
23931 + hc_regs = core_if->host_if->hc_regs[i];
23932 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
23933 + hcchar.b.chen = 0;
23934 + hcchar.b.chdis = 1;
23935 + hcchar.b.epdir = 0;
23936 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
23937 + }
23938 +
23939 + /* Halt all channels to put them into a known state. */
23940 + for (i = 0; i < num_channels; i++) {
23941 + int count = 0;
23942 + hc_regs = core_if->host_if->hc_regs[i];
23943 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
23944 + hcchar.b.chen = 1;
23945 + hcchar.b.chdis = 1;
23946 + hcchar.b.epdir = 0;
23947 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
23948 + DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d regs %p\n", __func__, i, hc_regs);
23949 + do {
23950 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
23951 + if (++count > 1000) {
23952 + DWC_ERROR
23953 + ("%s: Unable to clear halt on channel %d (timeout HCCHAR 0x%X @%p)\n",
23954 + __func__, i, hcchar.d32, &hc_regs->hcchar);
23955 + break;
23956 + }
23957 + dwc_udelay(1);
23958 + } while (hcchar.b.chen);
23959 + }
23960 + }
23961 +
23962 + /* Turn on the vbus power. */
23963 + DWC_PRINTF("Init: Port Power? op_state=%d\n", core_if->op_state);
23964 + if (core_if->op_state == A_HOST) {
23965 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
23966 + DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr);
23967 + if (hprt0.b.prtpwr == 0) {
23968 + hprt0.b.prtpwr = 1;
23969 + DWC_WRITE_REG32(host_if->hprt0, hprt0.d32);
23970 + }
23971 + }
23972 +
23973 + dwc_otg_enable_host_interrupts(core_if);
23974 +}
23975 +
23976 +/**
23977 + * Prepares a host channel for transferring packets to/from a specific
23978 + * endpoint. The HCCHARn register is set up with the characteristics specified
23979 + * in _hc. Host channel interrupts that may need to be serviced while this
23980 + * transfer is in progress are enabled.
23981 + *
23982 + * @param core_if Programming view of DWC_otg controller
23983 + * @param hc Information needed to initialize the host channel
23984 + */
23985 +void dwc_otg_hc_init(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
23986 +{
23987 + hcintmsk_data_t hc_intr_mask;
23988 + hcchar_data_t hcchar;
23989 + hcsplt_data_t hcsplt;
23990 +
23991 + uint8_t hc_num = hc->hc_num;
23992 + dwc_otg_host_if_t *host_if = core_if->host_if;
23993 + dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];
23994 +
23995 + /* Clear old interrupt conditions for this host channel. */
23996 + hc_intr_mask.d32 = 0xFFFFFFFF;
23997 + hc_intr_mask.b.reserved14_31 = 0;
23998 + DWC_WRITE_REG32(&hc_regs->hcint, hc_intr_mask.d32);
23999 +
24000 + /* Enable channel interrupts required for this transfer. */
24001 + hc_intr_mask.d32 = 0;
24002 + hc_intr_mask.b.chhltd = 1;
24003 + if (core_if->dma_enable) {
24004 + /* For Descriptor DMA mode core halts the channel on AHB error. Interrupt is not required */
24005 + if (!core_if->dma_desc_enable)
24006 + hc_intr_mask.b.ahberr = 1;
24007 + else {
24008 + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
24009 + hc_intr_mask.b.xfercompl = 1;
24010 + }
24011 +
24012 + if (hc->error_state && !hc->do_split &&
24013 + hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
24014 + hc_intr_mask.b.ack = 1;
24015 + if (hc->ep_is_in) {
24016 + hc_intr_mask.b.datatglerr = 1;
24017 + if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
24018 + hc_intr_mask.b.nak = 1;
24019 + }
24020 + }
24021 + }
24022 + } else {
24023 + switch (hc->ep_type) {
24024 + case DWC_OTG_EP_TYPE_CONTROL:
24025 + case DWC_OTG_EP_TYPE_BULK:
24026 + hc_intr_mask.b.xfercompl = 1;
24027 + hc_intr_mask.b.stall = 1;
24028 + hc_intr_mask.b.xacterr = 1;
24029 + hc_intr_mask.b.datatglerr = 1;
24030 + if (hc->ep_is_in) {
24031 + hc_intr_mask.b.bblerr = 1;
24032 + } else {
24033 + hc_intr_mask.b.nak = 1;
24034 + hc_intr_mask.b.nyet = 1;
24035 + if (hc->do_ping) {
24036 + hc_intr_mask.b.ack = 1;
24037 + }
24038 + }
24039 +
24040 + if (hc->do_split) {
24041 + hc_intr_mask.b.nak = 1;
24042 + if (hc->complete_split) {
24043 + hc_intr_mask.b.nyet = 1;
24044 + } else {
24045 + hc_intr_mask.b.ack = 1;
24046 + }
24047 + }
24048 +
24049 + if (hc->error_state) {
24050 + hc_intr_mask.b.ack = 1;
24051 + }
24052 + break;
24053 + case DWC_OTG_EP_TYPE_INTR:
24054 + hc_intr_mask.b.xfercompl = 1;
24055 + hc_intr_mask.b.nak = 1;
24056 + hc_intr_mask.b.stall = 1;
24057 + hc_intr_mask.b.xacterr = 1;
24058 + hc_intr_mask.b.datatglerr = 1;
24059 + hc_intr_mask.b.frmovrun = 1;
24060 +
24061 + if (hc->ep_is_in) {
24062 + hc_intr_mask.b.bblerr = 1;
24063 + }
24064 + if (hc->error_state) {
24065 + hc_intr_mask.b.ack = 1;
24066 + }
24067 + if (hc->do_split) {
24068 + if (hc->complete_split) {
24069 + hc_intr_mask.b.nyet = 1;
24070 + } else {
24071 + hc_intr_mask.b.ack = 1;
24072 + }
24073 + }
24074 + break;
24075 + case DWC_OTG_EP_TYPE_ISOC:
24076 + hc_intr_mask.b.xfercompl = 1;
24077 + hc_intr_mask.b.frmovrun = 1;
24078 + hc_intr_mask.b.ack = 1;
24079 +
24080 + if (hc->ep_is_in) {
24081 + hc_intr_mask.b.xacterr = 1;
24082 + hc_intr_mask.b.bblerr = 1;
24083 + }
24084 + break;
24085 + }
24086 + }
24087 + DWC_WRITE_REG32(&hc_regs->hcintmsk, hc_intr_mask.d32);
24088 +
24089 + /*
24090 + * Program the HCCHARn register with the endpoint characteristics for
24091 + * the current transfer.
24092 + */
24093 + hcchar.d32 = 0;
24094 + hcchar.b.devaddr = hc->dev_addr;
24095 + hcchar.b.epnum = hc->ep_num;
24096 + hcchar.b.epdir = hc->ep_is_in;
24097 + hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
24098 + hcchar.b.eptype = hc->ep_type;
24099 + hcchar.b.mps = hc->max_packet;
24100 +
24101 + DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);
24102 +
24103 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d, Dev Addr %d, EP #%d\n",
24104 + __func__, hc->hc_num, hcchar.b.devaddr, hcchar.b.epnum);
24105 + DWC_DEBUGPL(DBG_HCDV, " Is In %d, Is Low Speed %d, EP Type %d, "
24106 + "Max Pkt %d, Multi Cnt %d\n",
24107 + hcchar.b.epdir, hcchar.b.lspddev, hcchar.b.eptype,
24108 + hcchar.b.mps, hcchar.b.multicnt);
24109 +
24110 + /*
24111 + * Program the HCSPLIT register for SPLITs
24112 + */
24113 + hcsplt.d32 = 0;
24114 + if (hc->do_split) {
24115 + DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n",
24116 + hc->hc_num,
24117 + hc->complete_split ? "CSPLIT" : "SSPLIT");
24118 + hcsplt.b.compsplt = hc->complete_split;
24119 + hcsplt.b.xactpos = hc->xact_pos;
24120 + hcsplt.b.hubaddr = hc->hub_addr;
24121 + hcsplt.b.prtaddr = hc->port_addr;
24122 + DWC_DEBUGPL(DBG_HCDV, "\t comp split %d\n", hc->complete_split);
24123 + DWC_DEBUGPL(DBG_HCDV, "\t xact pos %d\n", hc->xact_pos);
24124 + DWC_DEBUGPL(DBG_HCDV, "\t hub addr %d\n", hc->hub_addr);
24125 + DWC_DEBUGPL(DBG_HCDV, "\t port addr %d\n", hc->port_addr);
24126 + DWC_DEBUGPL(DBG_HCDV, "\t is_in %d\n", hc->ep_is_in);
24127 + DWC_DEBUGPL(DBG_HCDV, "\t Max Pkt: %d\n", hcchar.b.mps);
24128 + DWC_DEBUGPL(DBG_HCDV, "\t xferlen: %d\n", hc->xfer_len);
24129 + }
24130 + DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);
24131 +
24132 +}
24133 +
24134 +/**
24135 + * Attempts to halt a host channel. This function should only be called in
24136 + * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under
24137 + * normal circumstances in DMA mode, the controller halts the channel when the
24138 + * transfer is complete or a condition occurs that requires application
24139 + * intervention.
24140 + *
24141 + * In slave mode, checks for a free request queue entry, then sets the Channel
24142 + * Enable and Channel Disable bits of the Host Channel Characteristics
24143 + * register of the specified channel to intiate the halt. If there is no free
24144 + * request queue entry, sets only the Channel Disable bit of the HCCHARn
24145 + * register to flush requests for this channel. In the latter case, sets a
24146 + * flag to indicate that the host channel needs to be halted when a request
24147 + * queue slot is open.
24148 + *
24149 + * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
24150 + * HCCHARn register. The controller ensures there is space in the request
24151 + * queue before submitting the halt request.
24152 + *
24153 + * Some time may elapse before the core flushes any posted requests for this
24154 + * host channel and halts. The Channel Halted interrupt handler completes the
24155 + * deactivation of the host channel.
24156 + *
24157 + * @param core_if Controller register interface.
24158 + * @param hc Host channel to halt.
24159 + * @param halt_status Reason for halting the channel.
24160 + */
24161 +void dwc_otg_hc_halt(dwc_otg_core_if_t * core_if,
24162 + dwc_hc_t * hc, dwc_otg_halt_status_e halt_status)
24163 +{
24164 + gnptxsts_data_t nptxsts;
24165 + hptxsts_data_t hptxsts;
24166 + hcchar_data_t hcchar;
24167 + dwc_otg_hc_regs_t *hc_regs;
24168 + dwc_otg_core_global_regs_t *global_regs;
24169 + dwc_otg_host_global_regs_t *host_global_regs;
24170 +
24171 + hc_regs = core_if->host_if->hc_regs[hc->hc_num];
24172 + global_regs = core_if->core_global_regs;
24173 + host_global_regs = core_if->host_if->host_global_regs;
24174 +
24175 + DWC_ASSERT(!(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS),
24176 + "halt_status = %d\n", halt_status);
24177 +
24178 + if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
24179 + halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
24180 + /*
24181 + * Disable all channel interrupts except Ch Halted. The QTD
24182 + * and QH state associated with this transfer has been cleared
24183 + * (in the case of URB_DEQUEUE), so the channel needs to be
24184 + * shut down carefully to prevent crashes.
24185 + */
24186 + hcintmsk_data_t hcintmsk;
24187 + hcintmsk.d32 = 0;
24188 + hcintmsk.b.chhltd = 1;
24189 + DWC_WRITE_REG32(&hc_regs->hcintmsk, hcintmsk.d32);
24190 +
24191 + /*
24192 + * Make sure no other interrupts besides halt are currently
24193 + * pending. Handling another interrupt could cause a crash due
24194 + * to the QTD and QH state.
24195 + */
24196 + DWC_WRITE_REG32(&hc_regs->hcint, ~hcintmsk.d32);
24197 +
24198 + /*
24199 + * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
24200 + * even if the channel was already halted for some other
24201 + * reason.
24202 + */
24203 + hc->halt_status = halt_status;
24204 +
24205 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
24206 + if (hcchar.b.chen == 0) {
24207 + /*
24208 + * The channel is either already halted or it hasn't
24209 + * started yet. In DMA mode, the transfer may halt if
24210 + * it finishes normally or a condition occurs that
24211 + * requires driver intervention. Don't want to halt
24212 + * the channel again. In either Slave or DMA mode,
24213 + * it's possible that the transfer has been assigned
24214 + * to a channel, but not started yet when an URB is
24215 + * dequeued. Don't want to halt a channel that hasn't
24216 + * started yet.
24217 + */
24218 + return;
24219 + }
24220 + }
24221 + if (hc->halt_pending) {
24222 + /*
24223 + * A halt has already been issued for this channel. This might
24224 + * happen when a transfer is aborted by a higher level in
24225 + * the stack.
24226 + */
24227 +#ifdef DEBUG
24228 + DWC_PRINTF
24229 + ("*** %s: Channel %d, _hc->halt_pending already set ***\n",
24230 + __func__, hc->hc_num);
24231 +
24232 +#endif
24233 + return;
24234 + }
24235 +
24236 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
24237 +
24238 + /* No need to set the bit in DDMA for disabling the channel */
24239 + //TODO check it everywhere channel is disabled
24240 + if (!core_if->core_params->dma_desc_enable)
24241 + hcchar.b.chen = 1;
24242 + hcchar.b.chdis = 1;
24243 +
24244 + if (!core_if->dma_enable) {
24245 + /* Check for space in the request queue to issue the halt. */
24246 + if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
24247 + hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
24248 + nptxsts.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
24249 + if (nptxsts.b.nptxqspcavail == 0) {
24250 + hcchar.b.chen = 0;
24251 + }
24252 + } else {
24253 + hptxsts.d32 =
24254 + DWC_READ_REG32(&host_global_regs->hptxsts);
24255 + if ((hptxsts.b.ptxqspcavail == 0)
24256 + || (core_if->queuing_high_bandwidth)) {
24257 + hcchar.b.chen = 0;
24258 + }
24259 + }
24260 + }
24261 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
24262 +
24263 + hc->halt_status = halt_status;
24264 +
24265 + if (hcchar.b.chen) {
24266 + hc->halt_pending = 1;
24267 + hc->halt_on_queue = 0;
24268 + } else {
24269 + hc->halt_on_queue = 1;
24270 + }
24271 +
24272 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
24273 + DWC_DEBUGPL(DBG_HCDV, " hcchar: 0x%08x\n", hcchar.d32);
24274 + DWC_DEBUGPL(DBG_HCDV, " halt_pending: %d\n", hc->halt_pending);
24275 + DWC_DEBUGPL(DBG_HCDV, " halt_on_queue: %d\n", hc->halt_on_queue);
24276 + DWC_DEBUGPL(DBG_HCDV, " halt_status: %d\n", hc->halt_status);
24277 +
24278 + return;
24279 +}
24280 +
24281 +/**
24282 + * Clears the transfer state for a host channel. This function is normally
24283 + * called after a transfer is done and the host channel is being released.
24284 + *
24285 + * @param core_if Programming view of DWC_otg controller.
24286 + * @param hc Identifies the host channel to clean up.
24287 + */
24288 +void dwc_otg_hc_cleanup(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
24289 +{
24290 + dwc_otg_hc_regs_t *hc_regs;
24291 +
24292 + hc->xfer_started = 0;
24293 +
24294 + /*
24295 + * Clear channel interrupt enables and any unhandled channel interrupt
24296 + * conditions.
24297 + */
24298 + hc_regs = core_if->host_if->hc_regs[hc->hc_num];
24299 + DWC_WRITE_REG32(&hc_regs->hcintmsk, 0);
24300 + DWC_WRITE_REG32(&hc_regs->hcint, 0xFFFFFFFF);
24301 +#ifdef DEBUG
24302 + DWC_TIMER_CANCEL(core_if->hc_xfer_timer[hc->hc_num]);
24303 +#endif
24304 +}
24305 +
24306 +/**
24307 + * Sets the channel property that indicates in which frame a periodic transfer
24308 + * should occur. This is always set to the _next_ frame. This function has no
24309 + * effect on non-periodic transfers.
24310 + *
24311 + * @param core_if Programming view of DWC_otg controller.
24312 + * @param hc Identifies the host channel to set up and its properties.
24313 + * @param hcchar Current value of the HCCHAR register for the specified host
24314 + * channel.
24315 + */
24316 +static inline void hc_set_even_odd_frame(dwc_otg_core_if_t * core_if,
24317 + dwc_hc_t * hc, hcchar_data_t * hcchar)
24318 +{
24319 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
24320 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
24321 + hfnum_data_t hfnum;
24322 + hfnum.d32 =
24323 + DWC_READ_REG32(&core_if->host_if->host_global_regs->hfnum);
24324 +
24325 + /* 1 if _next_ frame is odd, 0 if it's even */
24326 + hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
24327 +#ifdef DEBUG
24328 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split
24329 + && !hc->complete_split) {
24330 + switch (hfnum.b.frnum & 0x7) {
24331 + case 7:
24332 + core_if->hfnum_7_samples++;
24333 + core_if->hfnum_7_frrem_accum += hfnum.b.frrem;
24334 + break;
24335 + case 0:
24336 + core_if->hfnum_0_samples++;
24337 + core_if->hfnum_0_frrem_accum += hfnum.b.frrem;
24338 + break;
24339 + default:
24340 + core_if->hfnum_other_samples++;
24341 + core_if->hfnum_other_frrem_accum +=
24342 + hfnum.b.frrem;
24343 + break;
24344 + }
24345 + }
24346 +#endif
24347 + }
24348 +}
24349 +
24350 +#ifdef DEBUG
24351 +void hc_xfer_timeout(void *ptr)
24352 +{
24353 + hc_xfer_info_t *xfer_info = NULL;
24354 + int hc_num = 0;
24355 +
24356 + if (ptr)
24357 + xfer_info = (hc_xfer_info_t *) ptr;
24358 +
24359 + if (!xfer_info->hc) {
24360 + DWC_ERROR("xfer_info->hc = %p\n", xfer_info->hc);
24361 + return;
24362 + }
24363 +
24364 + hc_num = xfer_info->hc->hc_num;
24365 + DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num);
24366 + DWC_WARN(" start_hcchar_val 0x%08x\n",
24367 + xfer_info->core_if->start_hcchar_val[hc_num]);
24368 +}
24369 +#endif
24370 +
24371 +void ep_xfer_timeout(void *ptr)
24372 +{
24373 + ep_xfer_info_t *xfer_info = NULL;
24374 + int ep_num = 0;
24375 + dctl_data_t dctl = {.d32 = 0 };
24376 + gintsts_data_t gintsts = {.d32 = 0 };
24377 + gintmsk_data_t gintmsk = {.d32 = 0 };
24378 +
24379 + if (ptr)
24380 + xfer_info = (ep_xfer_info_t *) ptr;
24381 +
24382 + if (!xfer_info->ep) {
24383 + DWC_ERROR("xfer_info->ep = %p\n", xfer_info->ep);
24384 + return;
24385 + }
24386 +
24387 + ep_num = xfer_info->ep->num;
24388 + DWC_WARN("%s: timeout on endpoit %d\n", __func__, ep_num);
24389 + /* Put the sate to 2 as it was time outed */
24390 + xfer_info->state = 2;
24391 +
24392 + dctl.d32 =
24393 + DWC_READ_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl);
24394 + gintsts.d32 =
24395 + DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintsts);
24396 + gintmsk.d32 =
24397 + DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintmsk);
24398 +
24399 + if (!gintmsk.b.goutnakeff) {
24400 + /* Unmask it */
24401 + gintmsk.b.goutnakeff = 1;
24402 + DWC_WRITE_REG32(&xfer_info->core_if->core_global_regs->gintmsk,
24403 + gintmsk.d32);
24404 +
24405 + }
24406 +
24407 + if (!gintsts.b.goutnakeff) {
24408 + dctl.b.sgoutnak = 1;
24409 + }
24410 + DWC_WRITE_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl,
24411 + dctl.d32);
24412 +
24413 +}
24414 +
24415 +void set_pid_isoc(dwc_hc_t * hc)
24416 +{
24417 + /* Set up the initial PID for the transfer. */
24418 + if (hc->speed == DWC_OTG_EP_SPEED_HIGH) {
24419 + if (hc->ep_is_in) {
24420 + if (hc->multi_count == 1) {
24421 + hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
24422 + } else if (hc->multi_count == 2) {
24423 + hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
24424 + } else {
24425 + hc->data_pid_start = DWC_OTG_HC_PID_DATA2;
24426 + }
24427 + } else {
24428 + if (hc->multi_count == 1) {
24429 + hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
24430 + } else {
24431 + hc->data_pid_start = DWC_OTG_HC_PID_MDATA;
24432 + }
24433 + }
24434 + } else {
24435 + hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
24436 + }
24437 +}
24438 +
24439 +/**
24440 + * This function does the setup for a data transfer for a host channel and
24441 + * starts the transfer. May be called in either Slave mode or DMA mode. In
24442 + * Slave mode, the caller must ensure that there is sufficient space in the
24443 + * request queue and Tx Data FIFO.
24444 + *
24445 + * For an OUT transfer in Slave mode, it loads a data packet into the
24446 + * appropriate FIFO. If necessary, additional data packets will be loaded in
24447 + * the Host ISR.
24448 + *
24449 + * For an IN transfer in Slave mode, a data packet is requested. The data
24450 + * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
24451 + * additional data packets are requested in the Host ISR.
24452 + *
24453 + * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
24454 + * register along with a packet count of 1 and the channel is enabled. This
24455 + * causes a single PING transaction to occur. Other fields in HCTSIZ are
24456 + * simply set to 0 since no data transfer occurs in this case.
24457 + *
24458 + * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
24459 + * all the information required to perform the subsequent data transfer. In
24460 + * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
24461 + * controller performs the entire PING protocol, then starts the data
24462 + * transfer.
24463 + *
24464 + * @param core_if Programming view of DWC_otg controller.
24465 + * @param hc Information needed to initialize the host channel. The xfer_len
24466 + * value may be reduced to accommodate the max widths of the XferSize and
24467 + * PktCnt fields in the HCTSIZn register. The multi_count value may be changed
24468 + * to reflect the final xfer_len value.
24469 + */
24470 +void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
24471 +{
24472 + hcchar_data_t hcchar;
24473 + hctsiz_data_t hctsiz;
24474 + uint16_t num_packets;
24475 + uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size;
24476 + uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count;
24477 + dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
24478 +
24479 + hctsiz.d32 = 0;
24480 +
24481 + if (hc->do_ping) {
24482 + if (!core_if->dma_enable) {
24483 + dwc_otg_hc_do_ping(core_if, hc);
24484 + hc->xfer_started = 1;
24485 + return;
24486 + } else {
24487 + hctsiz.b.dopng = 1;
24488 + }
24489 + }
24490 +
24491 + if (hc->do_split) {
24492 + num_packets = 1;
24493 +
24494 + if (hc->complete_split && !hc->ep_is_in) {
24495 + /* For CSPLIT OUT Transfer, set the size to 0 so the
24496 + * core doesn't expect any data written to the FIFO */
24497 + hc->xfer_len = 0;
24498 + } else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
24499 + hc->xfer_len = hc->max_packet;
24500 + } else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
24501 + hc->xfer_len = 188;
24502 + }
24503 +
24504 + hctsiz.b.xfersize = hc->xfer_len;
24505 + } else {
24506 + /*
24507 + * Ensure that the transfer length and packet count will fit
24508 + * in the widths allocated for them in the HCTSIZn register.
24509 + */
24510 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
24511 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
24512 + /*
24513 + * Make sure the transfer size is no larger than one
24514 + * (micro)frame's worth of data. (A check was done
24515 + * when the periodic transfer was accepted to ensure
24516 + * that a (micro)frame's worth of data can be
24517 + * programmed into a channel.)
24518 + */
24519 + uint32_t max_periodic_len =
24520 + hc->multi_count * hc->max_packet;
24521 + if (hc->xfer_len > max_periodic_len) {
24522 + hc->xfer_len = max_periodic_len;
24523 + } else {
24524 + }
24525 + } else if (hc->xfer_len > max_hc_xfer_size) {
24526 + /* Make sure that xfer_len is a multiple of max packet size. */
24527 + hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1;
24528 + }
24529 +
24530 + if (hc->xfer_len > 0) {
24531 + num_packets =
24532 + (hc->xfer_len + hc->max_packet -
24533 + 1) / hc->max_packet;
24534 + if (num_packets > max_hc_pkt_count) {
24535 + num_packets = max_hc_pkt_count;
24536 + hc->xfer_len = num_packets * hc->max_packet;
24537 + }
24538 + } else {
24539 + /* Need 1 packet for transfer length of 0. */
24540 + num_packets = 1;
24541 + }
24542 +
24543 + if (hc->ep_is_in) {
24544 + /* Always program an integral # of max packets for IN transfers. */
24545 + hc->xfer_len = num_packets * hc->max_packet;
24546 + }
24547 +
24548 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
24549 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
24550 + /*
24551 + * Make sure that the multi_count field matches the
24552 + * actual transfer length.
24553 + */
24554 + hc->multi_count = num_packets;
24555 + }
24556 +
24557 + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
24558 + set_pid_isoc(hc);
24559 +
24560 + hctsiz.b.xfersize = hc->xfer_len;
24561 + }
24562 +
24563 + hc->start_pkt_count = num_packets;
24564 + hctsiz.b.pktcnt = num_packets;
24565 + hctsiz.b.pid = hc->data_pid_start;
24566 + DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
24567 +
24568 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
24569 + DWC_DEBUGPL(DBG_HCDV, " Xfer Size: %d\n", hctsiz.b.xfersize);
24570 + DWC_DEBUGPL(DBG_HCDV, " Num Pkts: %d\n", hctsiz.b.pktcnt);
24571 + DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid);
24572 +
24573 + if (core_if->dma_enable) {
24574 + dwc_dma_t dma_addr;
24575 + if (hc->align_buff) {
24576 + dma_addr = hc->align_buff;
24577 + } else {
24578 + dma_addr = ((unsigned long)hc->xfer_buff & 0xffffffff);
24579 + }
24580 + DWC_WRITE_REG32(&hc_regs->hcdma, dma_addr);
24581 + }
24582 +
24583 + /* Start the split */
24584 + if (hc->do_split) {
24585 + hcsplt_data_t hcsplt;
24586 + hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
24587 + hcsplt.b.spltena = 1;
24588 + DWC_WRITE_REG32(&hc_regs->hcsplt, hcsplt.d32);
24589 + }
24590 +
24591 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
24592 + hcchar.b.multicnt = hc->multi_count;
24593 + hc_set_even_odd_frame(core_if, hc, &hcchar);
24594 +#ifdef DEBUG
24595 + core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
24596 + if (hcchar.b.chdis) {
24597 + DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
24598 + __func__, hc->hc_num, hcchar.d32);
24599 + }
24600 +#endif
24601 +
24602 + /* Set host channel enable after all other setup is complete. */
24603 + hcchar.b.chen = 1;
24604 + hcchar.b.chdis = 0;
24605 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
24606 +
24607 + hc->xfer_started = 1;
24608 + hc->requests++;
24609 +
24610 + if (!core_if->dma_enable && !hc->ep_is_in && hc->xfer_len > 0) {
24611 + /* Load OUT packet into the appropriate Tx FIFO. */
24612 + dwc_otg_hc_write_packet(core_if, hc);
24613 + }
24614 +#ifdef DEBUG
24615 + if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
24616 + DWC_DEBUGPL(DBG_HCDV, "transfer %d from core_if %p\n",
24617 + hc->hc_num, core_if);//GRAYG
24618 + core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
24619 + core_if->hc_xfer_info[hc->hc_num].hc = hc;
24620 +
24621 + /* Start a timer for this transfer. */
24622 + DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
24623 + }
24624 +#endif
24625 +}
24626 +
24627 +/**
24628 + * This function does the setup for a data transfer for a host channel
24629 + * and starts the transfer in Descriptor DMA mode.
24630 + *
24631 + * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
24632 + * Sets PID and NTD values. For periodic transfers
24633 + * initializes SCHED_INFO field with micro-frame bitmap.
24634 + *
24635 + * Initializes HCDMA register with descriptor list address and CTD value
24636 + * then starts the transfer via enabling the channel.
24637 + *
24638 + * @param core_if Programming view of DWC_otg controller.
24639 + * @param hc Information needed to initialize the host channel.
24640 + */
24641 +void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
24642 +{
24643 + dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
24644 + hcchar_data_t hcchar;
24645 + hctsiz_data_t hctsiz;
24646 + hcdma_data_t hcdma;
24647 +
24648 + hctsiz.d32 = 0;
24649 +
24650 + if (hc->do_ping)
24651 + hctsiz.b_ddma.dopng = 1;
24652 +
24653 + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
24654 + set_pid_isoc(hc);
24655 +
24656 + /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
24657 + hctsiz.b_ddma.pid = hc->data_pid_start;
24658 + hctsiz.b_ddma.ntd = hc->ntd - 1; /* 0 - 1 descriptor, 1 - 2 descriptors, etc. */
24659 + hctsiz.b_ddma.schinfo = hc->schinfo; /* Non-zero only for high-speed interrupt endpoints */
24660 +
24661 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
24662 + DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid);
24663 + DWC_DEBUGPL(DBG_HCDV, " NTD: %d\n", hctsiz.b_ddma.ntd);
24664 +
24665 + DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
24666 +
24667 + hcdma.d32 = 0;
24668 + hcdma.b.dma_addr = ((uint32_t) hc->desc_list_addr) >> 11;
24669 +
24670 + /* Always start from first descriptor. */
24671 + hcdma.b.ctd = 0;
24672 + DWC_WRITE_REG32(&hc_regs->hcdma, hcdma.d32);
24673 +
24674 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
24675 + hcchar.b.multicnt = hc->multi_count;
24676 +
24677 +#ifdef DEBUG
24678 + core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
24679 + if (hcchar.b.chdis) {
24680 + DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
24681 + __func__, hc->hc_num, hcchar.d32);
24682 + }
24683 +#endif
24684 +
24685 + /* Set host channel enable after all other setup is complete. */
24686 + hcchar.b.chen = 1;
24687 + hcchar.b.chdis = 0;
24688 +
24689 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
24690 +
24691 + hc->xfer_started = 1;
24692 + hc->requests++;
24693 +
24694 +#ifdef DEBUG
24695 + if ((hc->ep_type != DWC_OTG_EP_TYPE_INTR)
24696 + && (hc->ep_type != DWC_OTG_EP_TYPE_ISOC)) {
24697 + DWC_DEBUGPL(DBG_HCDV, "DMA transfer %d from core_if %p\n",
24698 + hc->hc_num, core_if);//GRAYG
24699 + core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
24700 + core_if->hc_xfer_info[hc->hc_num].hc = hc;
24701 + /* Start a timer for this transfer. */
24702 + DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
24703 + }
24704 +#endif
24705 +
24706 +}
24707 +
24708 +/**
24709 + * This function continues a data transfer that was started by previous call
24710 + * to <code>dwc_otg_hc_start_transfer</code>. The caller must ensure there is
24711 + * sufficient space in the request queue and Tx Data FIFO. This function
24712 + * should only be called in Slave mode. In DMA mode, the controller acts
24713 + * autonomously to complete transfers programmed to a host channel.
24714 + *
24715 + * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
24716 + * if there is any data remaining to be queued. For an IN transfer, another
24717 + * data packet is always requested. For the SETUP phase of a control transfer,
24718 + * this function does nothing.
24719 + *
24720 + * @return 1 if a new request is queued, 0 if no more requests are required
24721 + * for this transfer.
24722 + */
24723 +int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
24724 +{
24725 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
24726 +
24727 + if (hc->do_split) {
24728 + /* SPLITs always queue just once per channel */
24729 + return 0;
24730 + } else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
24731 + /* SETUPs are queued only once since they can't be NAKed. */
24732 + return 0;
24733 + } else if (hc->ep_is_in) {
24734 + /*
24735 + * Always queue another request for other IN transfers. If
24736 + * back-to-back INs are issued and NAKs are received for both,
24737 + * the driver may still be processing the first NAK when the
24738 + * second NAK is received. When the interrupt handler clears
24739 + * the NAK interrupt for the first NAK, the second NAK will
24740 + * not be seen. So we can't depend on the NAK interrupt
24741 + * handler to requeue a NAKed request. Instead, IN requests
24742 + * are issued each time this function is called. When the
24743 + * transfer completes, the extra requests for the channel will
24744 + * be flushed.
24745 + */
24746 + hcchar_data_t hcchar;
24747 + dwc_otg_hc_regs_t *hc_regs =
24748 + core_if->host_if->hc_regs[hc->hc_num];
24749 +
24750 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
24751 + hc_set_even_odd_frame(core_if, hc, &hcchar);
24752 + hcchar.b.chen = 1;
24753 + hcchar.b.chdis = 0;
24754 + DWC_DEBUGPL(DBG_HCDV, " IN xfer: hcchar = 0x%08x\n",
24755 + hcchar.d32);
24756 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
24757 + hc->requests++;
24758 + return 1;
24759 + } else {
24760 + /* OUT transfers. */
24761 + if (hc->xfer_count < hc->xfer_len) {
24762 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
24763 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
24764 + hcchar_data_t hcchar;
24765 + dwc_otg_hc_regs_t *hc_regs;
24766 + hc_regs = core_if->host_if->hc_regs[hc->hc_num];
24767 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
24768 + hc_set_even_odd_frame(core_if, hc, &hcchar);
24769 + }
24770 +
24771 + /* Load OUT packet into the appropriate Tx FIFO. */
24772 + dwc_otg_hc_write_packet(core_if, hc);
24773 + hc->requests++;
24774 + return 1;
24775 + } else {
24776 + return 0;
24777 + }
24778 + }
24779 +}
24780 +
24781 +/**
24782 + * Starts a PING transfer. This function should only be called in Slave mode.
24783 + * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled.
24784 + */
24785 +void dwc_otg_hc_do_ping(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
24786 +{
24787 + hcchar_data_t hcchar;
24788 + hctsiz_data_t hctsiz;
24789 + dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
24790 +
24791 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
24792 +
24793 + hctsiz.d32 = 0;
24794 + hctsiz.b.dopng = 1;
24795 + hctsiz.b.pktcnt = 1;
24796 + DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
24797 +
24798 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
24799 + hcchar.b.chen = 1;
24800 + hcchar.b.chdis = 0;
24801 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
24802 +}
24803 +
24804 +/*
24805 + * This function writes a packet into the Tx FIFO associated with the Host
24806 + * Channel. For a channel associated with a non-periodic EP, the non-periodic
24807 + * Tx FIFO is written. For a channel associated with a periodic EP, the
24808 + * periodic Tx FIFO is written. This function should only be called in Slave
24809 + * mode.
24810 + *
24811 + * Upon return the xfer_buff and xfer_count fields in _hc are incremented by
24812 + * then number of bytes written to the Tx FIFO.
24813 + */
24814 +void dwc_otg_hc_write_packet(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
24815 +{
24816 + uint32_t i;
24817 + uint32_t remaining_count;
24818 + uint32_t byte_count;
24819 + uint32_t dword_count;
24820 +
24821 + uint32_t *data_buff = (uint32_t *) (hc->xfer_buff);
24822 + uint32_t *data_fifo = core_if->data_fifo[hc->hc_num];
24823 +
24824 + remaining_count = hc->xfer_len - hc->xfer_count;
24825 + if (remaining_count > hc->max_packet) {
24826 + byte_count = hc->max_packet;
24827 + } else {
24828 + byte_count = remaining_count;
24829 + }
24830 +
24831 + dword_count = (byte_count + 3) / 4;
24832 +
24833 + if ((((unsigned long)data_buff) & 0x3) == 0) {
24834 + /* xfer_buff is DWORD aligned. */
24835 + for (i = 0; i < dword_count; i++, data_buff++) {
24836 + DWC_WRITE_REG32(data_fifo, *data_buff);
24837 + }
24838 + } else {
24839 + /* xfer_buff is not DWORD aligned. */
24840 + for (i = 0; i < dword_count; i++, data_buff++) {
24841 + uint32_t data;
24842 + data =
24843 + (data_buff[0] | data_buff[1] << 8 | data_buff[2] <<
24844 + 16 | data_buff[3] << 24);
24845 + DWC_WRITE_REG32(data_fifo, data);
24846 + }
24847 + }
24848 +
24849 + hc->xfer_count += byte_count;
24850 + hc->xfer_buff += byte_count;
24851 +}
24852 +
24853 +/**
24854 + * Gets the current USB frame number. This is the frame number from the last
24855 + * SOF packet.
24856 + */
24857 +uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * core_if)
24858 +{
24859 + dsts_data_t dsts;
24860 + dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
24861 +
24862 + /* read current frame/microframe number from DSTS register */
24863 + return dsts.b.soffn;
24864 +}
24865 +
24866 +/**
24867 + * Calculates and gets the frame Interval value of HFIR register according PHY
24868 + * type and speed.The application can modify a value of HFIR register only after
24869 + * the Port Enable bit of the Host Port Control and Status register
24870 + * (HPRT.PrtEnaPort) has been set.
24871 +*/
24872 +
24873 +uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if)
24874 +{
24875 + gusbcfg_data_t usbcfg;
24876 + hwcfg2_data_t hwcfg2;
24877 + hprt0_data_t hprt0;
24878 + int clock = 60; // default value
24879 + usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
24880 + hwcfg2.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
24881 + hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
24882 + if (!usbcfg.b.physel && usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
24883 + clock = 60;
24884 + if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 3)
24885 + clock = 48;
24886 + if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
24887 + !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
24888 + clock = 30;
24889 + if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
24890 + !usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
24891 + clock = 60;
24892 + if (usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
24893 + !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
24894 + clock = 48;
24895 + if (usbcfg.b.physel && !usbcfg.b.phyif && hwcfg2.b.fs_phy_type == 2)
24896 + clock = 48;
24897 + if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 1)
24898 + clock = 48;
24899 + if (hprt0.b.prtspd == 0)
24900 + /* High speed case */
24901 + return 125 * clock;
24902 + else
24903 + /* FS/LS case */
24904 + return 1000 * clock;
24905 +}
24906 +
24907 +/**
24908 + * This function reads a setup packet from the Rx FIFO into the destination
24909 + * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl)
24910 + * Interrupt routine when a SETUP packet has been received in Slave mode.
24911 + *
24912 + * @param core_if Programming view of DWC_otg controller.
24913 + * @param dest Destination buffer for packet data.
24914 + */
24915 +void dwc_otg_read_setup_packet(dwc_otg_core_if_t * core_if, uint32_t * dest)
24916 +{
24917 + device_grxsts_data_t status;
24918 + /* Get the 8 bytes of a setup transaction data */
24919 +
24920 + /* Pop 2 DWORDS off the receive data FIFO into memory */
24921 + dest[0] = DWC_READ_REG32(core_if->data_fifo[0]);
24922 + dest[1] = DWC_READ_REG32(core_if->data_fifo[0]);
24923 + if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
24924 + status.d32 =
24925 + DWC_READ_REG32(&core_if->core_global_regs->grxstsp);
24926 + DWC_DEBUGPL(DBG_ANY,
24927 + "EP:%d BCnt:%d " "pktsts:%x Frame:%d(0x%0x)\n",
24928 + status.b.epnum, status.b.bcnt, status.b.pktsts,
24929 + status.b.fn, status.b.fn);
24930 + }
24931 +}
24932 +
24933 +/**
24934 + * This function enables EP0 OUT to receive SETUP packets and configures EP0
24935 + * IN for transmitting packets. It is normally called when the
24936 + * "Enumeration Done" interrupt occurs.
24937 + *
24938 + * @param core_if Programming view of DWC_otg controller.
24939 + * @param ep The EP0 data.
24940 + */
24941 +void dwc_otg_ep0_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
24942 +{
24943 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
24944 + dsts_data_t dsts;
24945 + depctl_data_t diepctl;
24946 + depctl_data_t doepctl;
24947 + dctl_data_t dctl = {.d32 = 0 };
24948 +
24949 + ep->stp_rollover = 0;
24950 + /* Read the Device Status and Endpoint 0 Control registers */
24951 + dsts.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dsts);
24952 + diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
24953 + doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl);
24954 +
24955 + /* Set the MPS of the IN EP based on the enumeration speed */
24956 + switch (dsts.b.enumspd) {
24957 + case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
24958 + case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
24959 + case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
24960 + diepctl.b.mps = DWC_DEP0CTL_MPS_64;
24961 + break;
24962 + case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
24963 + diepctl.b.mps = DWC_DEP0CTL_MPS_8;
24964 + break;
24965 + }
24966 +
24967 + DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
24968 +
24969 + /* Enable OUT EP for receive */
24970 + if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
24971 + doepctl.b.epena = 1;
24972 + DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
24973 + }
24974 +#ifdef VERBOSE
24975 + DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
24976 + DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
24977 + DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
24978 + DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));
24979 +#endif
24980 + dctl.b.cgnpinnak = 1;
24981 +
24982 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
24983 + DWC_DEBUGPL(DBG_PCDV, "dctl=%0x\n",
24984 + DWC_READ_REG32(&dev_if->dev_global_regs->dctl));
24985 +
24986 +}
24987 +
24988 +/**
24989 + * This function activates an EP. The Device EP control register for
24990 + * the EP is configured as defined in the ep structure. Note: This
24991 + * function is not used for EP0.
24992 + *
24993 + * @param core_if Programming view of DWC_otg controller.
24994 + * @param ep The EP to activate.
24995 + */
24996 +void dwc_otg_ep_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
24997 +{
24998 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
24999 + depctl_data_t depctl;
25000 + volatile uint32_t *addr;
25001 + daint_data_t daintmsk = {.d32 = 0 };
25002 + dcfg_data_t dcfg;
25003 + uint8_t i;
25004 +
25005 + DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num,
25006 + (ep->is_in ? "IN" : "OUT"));
25007 +
25008 +#ifdef DWC_UTE_PER_IO
25009 + ep->xiso_frame_num = 0xFFFFFFFF;
25010 + ep->xiso_active_xfers = 0;
25011 + ep->xiso_queued_xfers = 0;
25012 +#endif
25013 + /* Read DEPCTLn register */
25014 + if (ep->is_in == 1) {
25015 + addr = &dev_if->in_ep_regs[ep->num]->diepctl;
25016 + daintmsk.ep.in = 1 << ep->num;
25017 + } else {
25018 + addr = &dev_if->out_ep_regs[ep->num]->doepctl;
25019 + daintmsk.ep.out = 1 << ep->num;
25020 + }
25021 +
25022 + /* If the EP is already active don't change the EP Control
25023 + * register. */
25024 + depctl.d32 = DWC_READ_REG32(addr);
25025 + if (!depctl.b.usbactep) {
25026 + depctl.b.mps = ep->maxpacket;
25027 + depctl.b.eptype = ep->type;
25028 + depctl.b.txfnum = ep->tx_fifo_num;
25029 +
25030 + if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
25031 + depctl.b.setd0pid = 1; // ???
25032 + } else {
25033 + depctl.b.setd0pid = 1;
25034 + }
25035 + depctl.b.usbactep = 1;
25036 +
25037 + /* Update nextep_seq array and EPMSCNT in DCFG*/
25038 + if (!(depctl.b.eptype & 1) && (ep->is_in == 1)) { // NP IN EP
25039 + for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
25040 + if (core_if->nextep_seq[i] == core_if->first_in_nextep_seq)
25041 + break;
25042 + }
25043 + core_if->nextep_seq[i] = ep->num;
25044 + core_if->nextep_seq[ep->num] = core_if->first_in_nextep_seq;
25045 + depctl.b.nextep = core_if->nextep_seq[ep->num];
25046 + dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
25047 + dcfg.b.epmscnt++;
25048 + DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
25049 +
25050 + DWC_DEBUGPL(DBG_PCDV,
25051 + "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
25052 + __func__, core_if->first_in_nextep_seq);
25053 + for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
25054 + DWC_DEBUGPL(DBG_PCDV, "%2d\n",
25055 + core_if->nextep_seq[i]);
25056 + }
25057 +
25058 + }
25059 +
25060 +
25061 + DWC_WRITE_REG32(addr, depctl.d32);
25062 + DWC_DEBUGPL(DBG_PCDV, "DEPCTL=%08x\n", DWC_READ_REG32(addr));
25063 + }
25064 +
25065 + /* Enable the Interrupt for this EP */
25066 + if (core_if->multiproc_int_enable) {
25067 + if (ep->is_in == 1) {
25068 + diepmsk_data_t diepmsk = {.d32 = 0 };
25069 + diepmsk.b.xfercompl = 1;
25070 + diepmsk.b.timeout = 1;
25071 + diepmsk.b.epdisabled = 1;
25072 + diepmsk.b.ahberr = 1;
25073 + diepmsk.b.intknepmis = 1;
25074 + if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
25075 + diepmsk.b.intknepmis = 0;
25076 + diepmsk.b.txfifoundrn = 1; //?????
25077 + if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
25078 + diepmsk.b.nak = 1;
25079 + }
25080 +
25081 +
25082 +
25083 +/*
25084 + if (core_if->dma_desc_enable) {
25085 + diepmsk.b.bna = 1;
25086 + }
25087 +*/
25088 +/*
25089 + if (core_if->dma_enable) {
25090 + doepmsk.b.nak = 1;
25091 + }
25092 +*/
25093 + DWC_WRITE_REG32(&dev_if->dev_global_regs->
25094 + diepeachintmsk[ep->num], diepmsk.d32);
25095 +
25096 + } else {
25097 + doepmsk_data_t doepmsk = {.d32 = 0 };
25098 + doepmsk.b.xfercompl = 1;
25099 + doepmsk.b.ahberr = 1;
25100 + doepmsk.b.epdisabled = 1;
25101 + if (ep->type == DWC_OTG_EP_TYPE_ISOC)
25102 + doepmsk.b.outtknepdis = 1;
25103 +
25104 +/*
25105 +
25106 + if (core_if->dma_desc_enable) {
25107 + doepmsk.b.bna = 1;
25108 + }
25109 +*/
25110 +/*
25111 + doepmsk.b.babble = 1;
25112 + doepmsk.b.nyet = 1;
25113 + doepmsk.b.nak = 1;
25114 +*/
25115 + DWC_WRITE_REG32(&dev_if->dev_global_regs->
25116 + doepeachintmsk[ep->num], doepmsk.d32);
25117 + }
25118 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->deachintmsk,
25119 + 0, daintmsk.d32);
25120 + } else {
25121 + if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
25122 + if (ep->is_in) {
25123 + diepmsk_data_t diepmsk = {.d32 = 0 };
25124 + diepmsk.b.nak = 1;
25125 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk, 0, diepmsk.d32);
25126 + } else {
25127 + doepmsk_data_t doepmsk = {.d32 = 0 };
25128 + doepmsk.b.outtknepdis = 1;
25129 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->doepmsk, 0, doepmsk.d32);
25130 + }
25131 + }
25132 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->daintmsk,
25133 + 0, daintmsk.d32);
25134 + }
25135 +
25136 + DWC_DEBUGPL(DBG_PCDV, "DAINTMSK=%0x\n",
25137 + DWC_READ_REG32(&dev_if->dev_global_regs->daintmsk));
25138 +
25139 + ep->stall_clear_flag = 0;
25140 +
25141 + return;
25142 +}
25143 +
25144 +/**
25145 + * This function deactivates an EP. This is done by clearing the USB Active
25146 + * EP bit in the Device EP control register. Note: This function is not used
25147 + * for EP0. EP0 cannot be deactivated.
25148 + *
25149 + * @param core_if Programming view of DWC_otg controller.
25150 + * @param ep The EP to deactivate.
25151 + */
25152 +void dwc_otg_ep_deactivate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
25153 +{
25154 + depctl_data_t depctl = {.d32 = 0 };
25155 + volatile uint32_t *addr;
25156 + daint_data_t daintmsk = {.d32 = 0 };
25157 + dcfg_data_t dcfg;
25158 + uint8_t i = 0;
25159 +
25160 +#ifdef DWC_UTE_PER_IO
25161 + ep->xiso_frame_num = 0xFFFFFFFF;
25162 + ep->xiso_active_xfers = 0;
25163 + ep->xiso_queued_xfers = 0;
25164 +#endif
25165 +
25166 + /* Read DEPCTLn register */
25167 + if (ep->is_in == 1) {
25168 + addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
25169 + daintmsk.ep.in = 1 << ep->num;
25170 + } else {
25171 + addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
25172 + daintmsk.ep.out = 1 << ep->num;
25173 + }
25174 +
25175 + depctl.d32 = DWC_READ_REG32(addr);
25176 +
25177 + depctl.b.usbactep = 0;
25178 +
25179 + /* Update nextep_seq array and EPMSCNT in DCFG*/
25180 + if (!(depctl.b.eptype & 1) && ep->is_in == 1) { // NP EP IN
25181 + for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
25182 + if (core_if->nextep_seq[i] == ep->num)
25183 + break;
25184 + }
25185 + core_if->nextep_seq[i] = core_if->nextep_seq[ep->num];
25186 + if (core_if->first_in_nextep_seq == ep->num)
25187 + core_if->first_in_nextep_seq = i;
25188 + core_if->nextep_seq[ep->num] = 0xff;
25189 + depctl.b.nextep = 0;
25190 + dcfg.d32 =
25191 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
25192 + dcfg.b.epmscnt--;
25193 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
25194 + dcfg.d32);
25195 +
25196 + DWC_DEBUGPL(DBG_PCDV,
25197 + "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
25198 + __func__, core_if->first_in_nextep_seq);
25199 + for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
25200 + DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
25201 + }
25202 + }
25203 +
25204 + if (ep->is_in == 1)
25205 + depctl.b.txfnum = 0;
25206 +
25207 + if (core_if->dma_desc_enable)
25208 + depctl.b.epdis = 1;
25209 +
25210 + DWC_WRITE_REG32(addr, depctl.d32);
25211 + depctl.d32 = DWC_READ_REG32(addr);
25212 + if (core_if->dma_enable && ep->type == DWC_OTG_EP_TYPE_ISOC
25213 + && depctl.b.epena) {
25214 + depctl_data_t depctl = {.d32 = 0};
25215 + if (ep->is_in) {
25216 + diepint_data_t diepint = {.d32 = 0};
25217 +
25218 + depctl.b.snak = 1;
25219 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
25220 + diepctl, depctl.d32);
25221 + do {
25222 + dwc_udelay(10);
25223 + diepint.d32 =
25224 + DWC_READ_REG32(&core_if->
25225 + dev_if->in_ep_regs[ep->num]->
25226 + diepint);
25227 + } while (!diepint.b.inepnakeff);
25228 + diepint.b.inepnakeff = 1;
25229 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
25230 + diepint, diepint.d32);
25231 + depctl.d32 = 0;
25232 + depctl.b.epdis = 1;
25233 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
25234 + diepctl, depctl.d32);
25235 + do {
25236 + dwc_udelay(10);
25237 + diepint.d32 =
25238 + DWC_READ_REG32(&core_if->
25239 + dev_if->in_ep_regs[ep->num]->
25240 + diepint);
25241 + } while (!diepint.b.epdisabled);
25242 + diepint.b.epdisabled = 1;
25243 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
25244 + diepint, diepint.d32);
25245 + } else {
25246 + dctl_data_t dctl = {.d32 = 0};
25247 + gintmsk_data_t gintsts = {.d32 = 0};
25248 + doepint_data_t doepint = {.d32 = 0};
25249 + dctl.b.sgoutnak = 1;
25250 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
25251 + dctl, 0, dctl.d32);
25252 + do {
25253 + dwc_udelay(10);
25254 + gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
25255 + } while (!gintsts.b.goutnakeff);
25256 + gintsts.d32 = 0;
25257 + gintsts.b.goutnakeff = 1;
25258 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
25259 +
25260 + depctl.d32 = 0;
25261 + depctl.b.epdis = 1;
25262 + depctl.b.snak = 1;
25263 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepctl, depctl.d32);
25264 + do
25265 + {
25266 + dwc_udelay(10);
25267 + doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
25268 + out_ep_regs[ep->num]->doepint);
25269 + } while (!doepint.b.epdisabled);
25270 +
25271 + doepint.b.epdisabled = 1;
25272 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepint, doepint.d32);
25273 +
25274 + dctl.d32 = 0;
25275 + dctl.b.cgoutnak = 1;
25276 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
25277 + }
25278 + }
25279 +
25280 + /* Disable the Interrupt for this EP */
25281 + if (core_if->multiproc_int_enable) {
25282 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,
25283 + daintmsk.d32, 0);
25284 +
25285 + if (ep->is_in == 1) {
25286 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
25287 + diepeachintmsk[ep->num], 0);
25288 + } else {
25289 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
25290 + doepeachintmsk[ep->num], 0);
25291 + }
25292 + } else {
25293 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->daintmsk,
25294 + daintmsk.d32, 0);
25295 + }
25296 +
25297 +}
25298 +
25299 +/**
25300 + * This function initializes dma descriptor chain.
25301 + *
25302 + * @param core_if Programming view of DWC_otg controller.
25303 + * @param ep The EP to start the transfer on.
25304 + */
25305 +static void init_dma_desc_chain(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
25306 +{
25307 + dwc_otg_dev_dma_desc_t *dma_desc;
25308 + uint32_t offset;
25309 + uint32_t xfer_est;
25310 + int i;
25311 + unsigned maxxfer_local, total_len;
25312 +
25313 + if (!ep->is_in && ep->type == DWC_OTG_EP_TYPE_INTR &&
25314 + (ep->maxpacket%4)) {
25315 + maxxfer_local = ep->maxpacket;
25316 + total_len = ep->xfer_len;
25317 + } else {
25318 + maxxfer_local = ep->maxxfer;
25319 + total_len = ep->total_len;
25320 + }
25321 +
25322 + ep->desc_cnt = (total_len / maxxfer_local) +
25323 + ((total_len % maxxfer_local) ? 1 : 0);
25324 +
25325 + if (!ep->desc_cnt)
25326 + ep->desc_cnt = 1;
25327 +
25328 + if (ep->desc_cnt > MAX_DMA_DESC_CNT)
25329 + ep->desc_cnt = MAX_DMA_DESC_CNT;
25330 +
25331 + dma_desc = ep->desc_addr;
25332 + if (maxxfer_local == ep->maxpacket) {
25333 + if ((total_len % maxxfer_local) &&
25334 + (total_len/maxxfer_local < MAX_DMA_DESC_CNT)) {
25335 + xfer_est = (ep->desc_cnt - 1) * maxxfer_local +
25336 + (total_len % maxxfer_local);
25337 + } else
25338 + xfer_est = ep->desc_cnt * maxxfer_local;
25339 + } else
25340 + xfer_est = total_len;
25341 + offset = 0;
25342 + for (i = 0; i < ep->desc_cnt; ++i) {
25343 + /** DMA Descriptor Setup */
25344 + if (xfer_est > maxxfer_local) {
25345 + dma_desc->status.b.bs = BS_HOST_BUSY;
25346 + dma_desc->status.b.l = 0;
25347 + dma_desc->status.b.ioc = 0;
25348 + dma_desc->status.b.sp = 0;
25349 + dma_desc->status.b.bytes = maxxfer_local;
25350 + dma_desc->buf = ep->dma_addr + offset;
25351 + dma_desc->status.b.sts = 0;
25352 + dma_desc->status.b.bs = BS_HOST_READY;
25353 +
25354 + xfer_est -= maxxfer_local;
25355 + offset += maxxfer_local;
25356 + } else {
25357 + dma_desc->status.b.bs = BS_HOST_BUSY;
25358 + dma_desc->status.b.l = 1;
25359 + dma_desc->status.b.ioc = 1;
25360 + if (ep->is_in) {
25361 + dma_desc->status.b.sp =
25362 + (xfer_est %
25363 + ep->maxpacket) ? 1 : ((ep->
25364 + sent_zlp) ? 1 : 0);
25365 + dma_desc->status.b.bytes = xfer_est;
25366 + } else {
25367 + if (maxxfer_local == ep->maxpacket)
25368 + dma_desc->status.b.bytes = xfer_est;
25369 + else
25370 + dma_desc->status.b.bytes =
25371 + xfer_est + ((4 - (xfer_est & 0x3)) & 0x3);
25372 + }
25373 +
25374 + dma_desc->buf = ep->dma_addr + offset;
25375 + dma_desc->status.b.sts = 0;
25376 + dma_desc->status.b.bs = BS_HOST_READY;
25377 + }
25378 + dma_desc++;
25379 + }
25380 +}
25381 +/**
25382 + * This function is called when to write ISOC data into appropriate dedicated
25383 + * periodic FIFO.
25384 + */
25385 +static int32_t write_isoc_tx_fifo(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
25386 +{
25387 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
25388 + dwc_otg_dev_in_ep_regs_t *ep_regs;
25389 + dtxfsts_data_t txstatus = {.d32 = 0 };
25390 + uint32_t len = 0;
25391 + int epnum = dwc_ep->num;
25392 + int dwords;
25393 +
25394 + DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
25395 +
25396 + ep_regs = core_if->dev_if->in_ep_regs[epnum];
25397 +
25398 + len = dwc_ep->xfer_len - dwc_ep->xfer_count;
25399 +
25400 + if (len > dwc_ep->maxpacket) {
25401 + len = dwc_ep->maxpacket;
25402 + }
25403 +
25404 + dwords = (len + 3) / 4;
25405 +
25406 + /* While there is space in the queue and space in the FIFO and
25407 + * More data to tranfer, Write packets to the Tx FIFO */
25408 + txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
25409 + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
25410 +
25411 + while (txstatus.b.txfspcavail > dwords &&
25412 + dwc_ep->xfer_count < dwc_ep->xfer_len && dwc_ep->xfer_len != 0) {
25413 + /* Write the FIFO */
25414 + dwc_otg_ep_write_packet(core_if, dwc_ep, 0);
25415 +
25416 + len = dwc_ep->xfer_len - dwc_ep->xfer_count;
25417 + if (len > dwc_ep->maxpacket) {
25418 + len = dwc_ep->maxpacket;
25419 + }
25420 +
25421 + dwords = (len + 3) / 4;
25422 + txstatus.d32 =
25423 + DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
25424 + DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
25425 + txstatus.d32);
25426 + }
25427 +
25428 + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
25429 + DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));
25430 +
25431 + return 1;
25432 +}
25433 +/**
25434 + * This function does the setup for a data transfer for an EP and
25435 + * starts the transfer. For an IN transfer, the packets will be
25436 + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
25437 + * the packets are unloaded from the Rx FIFO in the ISR. the ISR.
25438 + *
25439 + * @param core_if Programming view of DWC_otg controller.
25440 + * @param ep The EP to start the transfer on.
25441 + */
25442 +
25443 +void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
25444 +{
25445 + depctl_data_t depctl;
25446 + deptsiz_data_t deptsiz;
25447 + gintmsk_data_t intr_mask = {.d32 = 0 };
25448 +
25449 + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
25450 + DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
25451 + "xfer_buff=%p start_xfer_buff=%p, total_len = %d\n",
25452 + ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
25453 + ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff,
25454 + ep->total_len);
25455 + /* IN endpoint */
25456 + if (ep->is_in == 1) {
25457 + dwc_otg_dev_in_ep_regs_t *in_regs =
25458 + core_if->dev_if->in_ep_regs[ep->num];
25459 +
25460 + gnptxsts_data_t gtxstatus;
25461 +
25462 + gtxstatus.d32 =
25463 + DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
25464 +
25465 + if (core_if->en_multiple_tx_fifo == 0
25466 + && gtxstatus.b.nptxqspcavail == 0 && !core_if->dma_enable) {
25467 +#ifdef DEBUG
25468 + DWC_PRINTF("TX Queue Full (0x%0x)\n", gtxstatus.d32);
25469 +#endif
25470 + return;
25471 + }
25472 +
25473 + depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
25474 + deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
25475 +
25476 + if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
25477 + ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
25478 + ep->maxxfer : (ep->total_len - ep->xfer_len);
25479 + else
25480 + ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len - ep->xfer_len)) ?
25481 + MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);
25482 +
25483 +
25484 + /* Zero Length Packet? */
25485 + if ((ep->xfer_len - ep->xfer_count) == 0) {
25486 + deptsiz.b.xfersize = 0;
25487 + deptsiz.b.pktcnt = 1;
25488 + } else {
25489 + /* Program the transfer size and packet count
25490 + * as follows: xfersize = N * maxpacket +
25491 + * short_packet pktcnt = N + (short_packet
25492 + * exist ? 1 : 0)
25493 + */
25494 + deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
25495 + deptsiz.b.pktcnt =
25496 + (ep->xfer_len - ep->xfer_count - 1 +
25497 + ep->maxpacket) / ep->maxpacket;
25498 + if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
25499 + deptsiz.b.pktcnt = MAX_PKT_CNT;
25500 + deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
25501 + }
25502 + if (ep->type == DWC_OTG_EP_TYPE_ISOC)
25503 + deptsiz.b.mc = deptsiz.b.pktcnt;
25504 + }
25505 +
25506 + /* Write the DMA register */
25507 + if (core_if->dma_enable) {
25508 + if (core_if->dma_desc_enable == 0) {
25509 + if (ep->type != DWC_OTG_EP_TYPE_ISOC)
25510 + deptsiz.b.mc = 1;
25511 + DWC_WRITE_REG32(&in_regs->dieptsiz,
25512 + deptsiz.d32);
25513 + DWC_WRITE_REG32(&(in_regs->diepdma),
25514 + (uint32_t) ep->dma_addr);
25515 + } else {
25516 +#ifdef DWC_UTE_CFI
25517 + /* The descriptor chain should be already initialized by now */
25518 + if (ep->buff_mode != BM_STANDARD) {
25519 + DWC_WRITE_REG32(&in_regs->diepdma,
25520 + ep->descs_dma_addr);
25521 + } else {
25522 +#endif
25523 + init_dma_desc_chain(core_if, ep);
25524 + /** DIEPDMAn Register write */
25525 + DWC_WRITE_REG32(&in_regs->diepdma,
25526 + ep->dma_desc_addr);
25527 +#ifdef DWC_UTE_CFI
25528 + }
25529 +#endif
25530 + }
25531 + } else {
25532 + DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
25533 + if (ep->type != DWC_OTG_EP_TYPE_ISOC) {
25534 + /**
25535 + * Enable the Non-Periodic Tx FIFO empty interrupt,
25536 + * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
25537 + * the data will be written into the fifo by the ISR.
25538 + */
25539 + if (core_if->en_multiple_tx_fifo == 0) {
25540 + intr_mask.b.nptxfempty = 1;
25541 + DWC_MODIFY_REG32
25542 + (&core_if->core_global_regs->gintmsk,
25543 + intr_mask.d32, intr_mask.d32);
25544 + } else {
25545 + /* Enable the Tx FIFO Empty Interrupt for this EP */
25546 + if (ep->xfer_len > 0) {
25547 + uint32_t fifoemptymsk = 0;
25548 + fifoemptymsk = 1 << ep->num;
25549 + DWC_MODIFY_REG32
25550 + (&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
25551 + 0, fifoemptymsk);
25552 +
25553 + }
25554 + }
25555 + } else {
25556 + write_isoc_tx_fifo(core_if, ep);
25557 + }
25558 + }
25559 + if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
25560 + depctl.b.nextep = core_if->nextep_seq[ep->num];
25561 +
25562 + if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
25563 + dsts_data_t dsts = {.d32 = 0};
25564 + if (ep->bInterval == 1) {
25565 + dsts.d32 =
25566 + DWC_READ_REG32(&core_if->dev_if->
25567 + dev_global_regs->dsts);
25568 + ep->frame_num = dsts.b.soffn + ep->bInterval;
25569 + if (ep->frame_num > 0x3FFF) {
25570 + ep->frm_overrun = 1;
25571 + ep->frame_num &= 0x3FFF;
25572 + } else
25573 + ep->frm_overrun = 0;
25574 + if (ep->frame_num & 0x1) {
25575 + depctl.b.setd1pid = 1;
25576 + } else {
25577 + depctl.b.setd0pid = 1;
25578 + }
25579 + }
25580 + }
25581 + /* EP enable, IN data in FIFO */
25582 + depctl.b.cnak = 1;
25583 + depctl.b.epena = 1;
25584 + DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
25585 +
25586 + } else {
25587 + /* OUT endpoint */
25588 + dwc_otg_dev_out_ep_regs_t *out_regs =
25589 + core_if->dev_if->out_ep_regs[ep->num];
25590 +
25591 + depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
25592 + deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
25593 +
25594 + if (!core_if->dma_desc_enable) {
25595 + if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
25596 + ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
25597 + ep->maxxfer : (ep->total_len - ep->xfer_len);
25598 + else
25599 + ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len
25600 + - ep->xfer_len)) ? MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);
25601 + }
25602 +
25603 + /* Program the transfer size and packet count as follows:
25604 + *
25605 + * pktcnt = N
25606 + * xfersize = N * maxpacket
25607 + */
25608 + if ((ep->xfer_len - ep->xfer_count) == 0) {
25609 + /* Zero Length Packet */
25610 + deptsiz.b.xfersize = ep->maxpacket;
25611 + deptsiz.b.pktcnt = 1;
25612 + } else {
25613 + deptsiz.b.pktcnt =
25614 + (ep->xfer_len - ep->xfer_count +
25615 + (ep->maxpacket - 1)) / ep->maxpacket;
25616 + if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
25617 + deptsiz.b.pktcnt = MAX_PKT_CNT;
25618 + }
25619 + if (!core_if->dma_desc_enable) {
25620 + ep->xfer_len =
25621 + deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count;
25622 + }
25623 + deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
25624 + }
25625 +
25626 + DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n",
25627 + ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt);
25628 +
25629 + if (core_if->dma_enable) {
25630 + if (!core_if->dma_desc_enable) {
25631 + DWC_WRITE_REG32(&out_regs->doeptsiz,
25632 + deptsiz.d32);
25633 +
25634 + DWC_WRITE_REG32(&(out_regs->doepdma),
25635 + (uint32_t) ep->dma_addr);
25636 + } else {
25637 +#ifdef DWC_UTE_CFI
25638 + /* The descriptor chain should be already initialized by now */
25639 + if (ep->buff_mode != BM_STANDARD) {
25640 + DWC_WRITE_REG32(&out_regs->doepdma,
25641 + ep->descs_dma_addr);
25642 + } else {
25643 +#endif
25644 + /** This is used for interrupt out transfers*/
25645 + if (!ep->xfer_len)
25646 + ep->xfer_len = ep->total_len;
25647 + init_dma_desc_chain(core_if, ep);
25648 +
25649 + if (core_if->core_params->dev_out_nak) {
25650 + if (ep->type == DWC_OTG_EP_TYPE_BULK) {
25651 + deptsiz.b.pktcnt = (ep->total_len +
25652 + (ep->maxpacket - 1)) / ep->maxpacket;
25653 + deptsiz.b.xfersize = ep->total_len;
25654 + /* Remember initial value of doeptsiz */
25655 + core_if->start_doeptsiz_val[ep->num] = deptsiz.d32;
25656 + DWC_WRITE_REG32(&out_regs->doeptsiz,
25657 + deptsiz.d32);
25658 + }
25659 + }
25660 + /** DOEPDMAn Register write */
25661 + DWC_WRITE_REG32(&out_regs->doepdma,
25662 + ep->dma_desc_addr);
25663 +#ifdef DWC_UTE_CFI
25664 + }
25665 +#endif
25666 + }
25667 + } else {
25668 + DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
25669 + }
25670 +
25671 + if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
25672 + dsts_data_t dsts = {.d32 = 0};
25673 + if (ep->bInterval == 1) {
25674 + dsts.d32 =
25675 + DWC_READ_REG32(&core_if->dev_if->
25676 + dev_global_regs->dsts);
25677 + ep->frame_num = dsts.b.soffn + ep->bInterval;
25678 + if (ep->frame_num > 0x3FFF) {
25679 + ep->frm_overrun = 1;
25680 + ep->frame_num &= 0x3FFF;
25681 + } else
25682 + ep->frm_overrun = 0;
25683 +
25684 + if (ep->frame_num & 0x1) {
25685 + depctl.b.setd1pid = 1;
25686 + } else {
25687 + depctl.b.setd0pid = 1;
25688 + }
25689 + }
25690 + }
25691 +
25692 + /* EP enable */
25693 + depctl.b.cnak = 1;
25694 + depctl.b.epena = 1;
25695 +
25696 + DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
25697 +
25698 + DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n",
25699 + DWC_READ_REG32(&out_regs->doepctl),
25700 + DWC_READ_REG32(&out_regs->doeptsiz));
25701 + DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
25702 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->
25703 + daintmsk),
25704 + DWC_READ_REG32(&core_if->core_global_regs->
25705 + gintmsk));
25706 +
25707 + /* Timer is scheduling only for out bulk transfers for
25708 + * "Device DDMA OUT NAK Enhancement" feature to inform user
25709 + * about received data payload in case of timeout
25710 + */
25711 + if (core_if->core_params->dev_out_nak) {
25712 + if (ep->type == DWC_OTG_EP_TYPE_BULK) {
25713 + core_if->ep_xfer_info[ep->num].core_if = core_if;
25714 + core_if->ep_xfer_info[ep->num].ep = ep;
25715 + core_if->ep_xfer_info[ep->num].state = 1;
25716 +
25717 + /* Start a timer for this transfer. */
25718 + DWC_TIMER_SCHEDULE(core_if->ep_xfer_timer[ep->num], 10000);
25719 + }
25720 + }
25721 + }
25722 +}
25723 +
25724 +/**
25725 + * This function setup a zero length transfer in Buffer DMA and
25726 + * Slave modes for usb requests with zero field set
25727 + *
25728 + * @param core_if Programming view of DWC_otg controller.
25729 + * @param ep The EP to start the transfer on.
25730 + *
25731 + */
25732 +void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
25733 +{
25734 +
25735 + depctl_data_t depctl;
25736 + deptsiz_data_t deptsiz;
25737 + gintmsk_data_t intr_mask = {.d32 = 0 };
25738 +
25739 + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
25740 + DWC_PRINTF("zero length transfer is called\n");
25741 +
25742 + /* IN endpoint */
25743 + if (ep->is_in == 1) {
25744 + dwc_otg_dev_in_ep_regs_t *in_regs =
25745 + core_if->dev_if->in_ep_regs[ep->num];
25746 +
25747 + depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
25748 + deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
25749 +
25750 + deptsiz.b.xfersize = 0;
25751 + deptsiz.b.pktcnt = 1;
25752 +
25753 + /* Write the DMA register */
25754 + if (core_if->dma_enable) {
25755 + if (core_if->dma_desc_enable == 0) {
25756 + deptsiz.b.mc = 1;
25757 + DWC_WRITE_REG32(&in_regs->dieptsiz,
25758 + deptsiz.d32);
25759 + DWC_WRITE_REG32(&(in_regs->diepdma),
25760 + (uint32_t) ep->dma_addr);
25761 + }
25762 + } else {
25763 + DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
25764 + /**
25765 + * Enable the Non-Periodic Tx FIFO empty interrupt,
25766 + * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
25767 + * the data will be written into the fifo by the ISR.
25768 + */
25769 + if (core_if->en_multiple_tx_fifo == 0) {
25770 + intr_mask.b.nptxfempty = 1;
25771 + DWC_MODIFY_REG32(&core_if->
25772 + core_global_regs->gintmsk,
25773 + intr_mask.d32, intr_mask.d32);
25774 + } else {
25775 + /* Enable the Tx FIFO Empty Interrupt for this EP */
25776 + if (ep->xfer_len > 0) {
25777 + uint32_t fifoemptymsk = 0;
25778 + fifoemptymsk = 1 << ep->num;
25779 + DWC_MODIFY_REG32(&core_if->
25780 + dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
25781 + 0, fifoemptymsk);
25782 + }
25783 + }
25784 + }
25785 +
25786 + if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
25787 + depctl.b.nextep = core_if->nextep_seq[ep->num];
25788 + /* EP enable, IN data in FIFO */
25789 + depctl.b.cnak = 1;
25790 + depctl.b.epena = 1;
25791 + DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
25792 +
25793 + } else {
25794 + /* OUT endpoint */
25795 + dwc_otg_dev_out_ep_regs_t *out_regs =
25796 + core_if->dev_if->out_ep_regs[ep->num];
25797 +
25798 + depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
25799 + deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
25800 +
25801 + /* Zero Length Packet */
25802 + deptsiz.b.xfersize = ep->maxpacket;
25803 + deptsiz.b.pktcnt = 1;
25804 +
25805 + if (core_if->dma_enable) {
25806 + if (!core_if->dma_desc_enable) {
25807 + DWC_WRITE_REG32(&out_regs->doeptsiz,
25808 + deptsiz.d32);
25809 +
25810 + DWC_WRITE_REG32(&(out_regs->doepdma),
25811 + (uint32_t) ep->dma_addr);
25812 + }
25813 + } else {
25814 + DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
25815 + }
25816 +
25817 + /* EP enable */
25818 + depctl.b.cnak = 1;
25819 + depctl.b.epena = 1;
25820 +
25821 + DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
25822 +
25823 + }
25824 +}
25825 +
25826 +/**
25827 + * This function does the setup for a data transfer for EP0 and starts
25828 + * the transfer. For an IN transfer, the packets will be loaded into
25829 + * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are
25830 + * unloaded from the Rx FIFO in the ISR.
25831 + *
25832 + * @param core_if Programming view of DWC_otg controller.
25833 + * @param ep The EP0 data.
25834 + */
25835 +void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
25836 +{
25837 + depctl_data_t depctl;
25838 + deptsiz0_data_t deptsiz;
25839 + gintmsk_data_t intr_mask = {.d32 = 0 };
25840 + dwc_otg_dev_dma_desc_t *dma_desc;
25841 +
25842 + DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
25843 + "xfer_buff=%p start_xfer_buff=%p \n",
25844 + ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
25845 + ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff);
25846 +
25847 + ep->total_len = ep->xfer_len;
25848 +
25849 + /* IN endpoint */
25850 + if (ep->is_in == 1) {
25851 + dwc_otg_dev_in_ep_regs_t *in_regs =
25852 + core_if->dev_if->in_ep_regs[0];
25853 +
25854 + gnptxsts_data_t gtxstatus;
25855 +
25856 + if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
25857 + depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
25858 + if (depctl.b.epena)
25859 + return;
25860 + }
25861 +
25862 + gtxstatus.d32 =
25863 + DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
25864 +
25865 + /* If dedicated FIFO every time flush fifo before enable ep*/
25866 + if (core_if->en_multiple_tx_fifo && core_if->snpsid >= OTG_CORE_REV_3_00a)
25867 + dwc_otg_flush_tx_fifo(core_if, ep->tx_fifo_num);
25868 +
25869 + if (core_if->en_multiple_tx_fifo == 0
25870 + && gtxstatus.b.nptxqspcavail == 0
25871 + && !core_if->dma_enable) {
25872 +#ifdef DEBUG
25873 + deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
25874 + DWC_DEBUGPL(DBG_PCD, "DIEPCTL0=%0x\n",
25875 + DWC_READ_REG32(&in_regs->diepctl));
25876 + DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n",
25877 + deptsiz.d32,
25878 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
25879 + DWC_PRINTF("TX Queue or FIFO Full (0x%0x)\n",
25880 + gtxstatus.d32);
25881 +#endif
25882 + return;
25883 + }
25884 +
25885 + depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
25886 + deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
25887 +
25888 + /* Zero Length Packet? */
25889 + if (ep->xfer_len == 0) {
25890 + deptsiz.b.xfersize = 0;
25891 + deptsiz.b.pktcnt = 1;
25892 + } else {
25893 + /* Program the transfer size and packet count
25894 + * as follows: xfersize = N * maxpacket +
25895 + * short_packet pktcnt = N + (short_packet
25896 + * exist ? 1 : 0)
25897 + */
25898 + if (ep->xfer_len > ep->maxpacket) {
25899 + ep->xfer_len = ep->maxpacket;
25900 + deptsiz.b.xfersize = ep->maxpacket;
25901 + } else {
25902 + deptsiz.b.xfersize = ep->xfer_len;
25903 + }
25904 + deptsiz.b.pktcnt = 1;
25905 +
25906 + }
25907 + DWC_DEBUGPL(DBG_PCDV,
25908 + "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
25909 + ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
25910 + deptsiz.d32);
25911 +
25912 + /* Write the DMA register */
25913 + if (core_if->dma_enable) {
25914 + if (core_if->dma_desc_enable == 0) {
25915 + DWC_WRITE_REG32(&in_regs->dieptsiz,
25916 + deptsiz.d32);
25917 +
25918 + DWC_WRITE_REG32(&(in_regs->diepdma),
25919 + (uint32_t) ep->dma_addr);
25920 + } else {
25921 + dma_desc = core_if->dev_if->in_desc_addr;
25922 +
25923 + /** DMA Descriptor Setup */
25924 + dma_desc->status.b.bs = BS_HOST_BUSY;
25925 + dma_desc->status.b.l = 1;
25926 + dma_desc->status.b.ioc = 1;
25927 + dma_desc->status.b.sp =
25928 + (ep->xfer_len == ep->maxpacket) ? 0 : 1;
25929 + dma_desc->status.b.bytes = ep->xfer_len;
25930 + dma_desc->buf = ep->dma_addr;
25931 + dma_desc->status.b.sts = 0;
25932 + dma_desc->status.b.bs = BS_HOST_READY;
25933 +
25934 + /** DIEPDMA0 Register write */
25935 + DWC_WRITE_REG32(&in_regs->diepdma,
25936 + core_if->
25937 + dev_if->dma_in_desc_addr);
25938 + }
25939 + } else {
25940 + DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
25941 + }
25942 +
25943 + if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
25944 + depctl.b.nextep = core_if->nextep_seq[ep->num];
25945 + /* EP enable, IN data in FIFO */
25946 + depctl.b.cnak = 1;
25947 + depctl.b.epena = 1;
25948 + DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
25949 +
25950 + /**
25951 + * Enable the Non-Periodic Tx FIFO empty interrupt, the
25952 + * data will be written into the fifo by the ISR.
25953 + */
25954 + if (!core_if->dma_enable) {
25955 + if (core_if->en_multiple_tx_fifo == 0) {
25956 + intr_mask.b.nptxfempty = 1;
25957 + DWC_MODIFY_REG32(&core_if->
25958 + core_global_regs->gintmsk,
25959 + intr_mask.d32, intr_mask.d32);
25960 + } else {
25961 + /* Enable the Tx FIFO Empty Interrupt for this EP */
25962 + if (ep->xfer_len > 0) {
25963 + uint32_t fifoemptymsk = 0;
25964 + fifoemptymsk |= 1 << ep->num;
25965 + DWC_MODIFY_REG32(&core_if->
25966 + dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
25967 + 0, fifoemptymsk);
25968 + }
25969 + }
25970 + }
25971 + } else {
25972 + /* OUT endpoint */
25973 + dwc_otg_dev_out_ep_regs_t *out_regs =
25974 + core_if->dev_if->out_ep_regs[0];
25975 +
25976 + depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
25977 + deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
25978 +
25979 + /* Program the transfer size and packet count as follows:
25980 + * xfersize = N * (maxpacket + 4 - (maxpacket % 4))
25981 + * pktcnt = N */
25982 + /* Zero Length Packet */
25983 + deptsiz.b.xfersize = ep->maxpacket;
25984 + deptsiz.b.pktcnt = 1;
25985 + if (core_if->snpsid >= OTG_CORE_REV_3_00a)
25986 + deptsiz.b.supcnt = 3;
25987 +
25988 + DWC_DEBUGPL(DBG_PCDV, "len=%d xfersize=%d pktcnt=%d\n",
25989 + ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt);
25990 +
25991 + if (core_if->dma_enable) {
25992 + if (!core_if->dma_desc_enable) {
25993 + DWC_WRITE_REG32(&out_regs->doeptsiz,
25994 + deptsiz.d32);
25995 +
25996 + DWC_WRITE_REG32(&(out_regs->doepdma),
25997 + (uint32_t) ep->dma_addr);
25998 + } else {
25999 + dma_desc = core_if->dev_if->out_desc_addr;
26000 +
26001 + /** DMA Descriptor Setup */
26002 + dma_desc->status.b.bs = BS_HOST_BUSY;
26003 + if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
26004 + dma_desc->status.b.mtrf = 0;
26005 + dma_desc->status.b.sr = 0;
26006 + }
26007 + dma_desc->status.b.l = 1;
26008 + dma_desc->status.b.ioc = 1;
26009 + dma_desc->status.b.bytes = ep->maxpacket;
26010 + dma_desc->buf = ep->dma_addr;
26011 + dma_desc->status.b.sts = 0;
26012 + dma_desc->status.b.bs = BS_HOST_READY;
26013 +
26014 + /** DOEPDMA0 Register write */
26015 + DWC_WRITE_REG32(&out_regs->doepdma,
26016 + core_if->dev_if->
26017 + dma_out_desc_addr);
26018 + }
26019 + } else {
26020 + DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
26021 + }
26022 +
26023 + /* EP enable */
26024 + depctl.b.cnak = 1;
26025 + depctl.b.epena = 1;
26026 + DWC_WRITE_REG32(&(out_regs->doepctl), depctl.d32);
26027 + }
26028 +}
26029 +
26030 +/**
26031 + * This function continues control IN transfers started by
26032 + * dwc_otg_ep0_start_transfer, when the transfer does not fit in a
26033 + * single packet. NOTE: The DIEPCTL0/DOEPCTL0 registers only have one
26034 + * bit for the packet count.
26035 + *
26036 + * @param core_if Programming view of DWC_otg controller.
26037 + * @param ep The EP0 data.
26038 + */
26039 +void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
26040 +{
26041 + depctl_data_t depctl;
26042 + deptsiz0_data_t deptsiz;
26043 + gintmsk_data_t intr_mask = {.d32 = 0 };
26044 + dwc_otg_dev_dma_desc_t *dma_desc;
26045 +
26046 + if (ep->is_in == 1) {
26047 + dwc_otg_dev_in_ep_regs_t *in_regs =
26048 + core_if->dev_if->in_ep_regs[0];
26049 + gnptxsts_data_t tx_status = {.d32 = 0 };
26050 +
26051 + tx_status.d32 =
26052 + DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
26053 + /** @todo Should there be check for room in the Tx
26054 + * Status Queue. If not remove the code above this comment. */
26055 +
26056 + depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
26057 + deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
26058 +
26059 + /* Program the transfer size and packet count
26060 + * as follows: xfersize = N * maxpacket +
26061 + * short_packet pktcnt = N + (short_packet
26062 + * exist ? 1 : 0)
26063 + */
26064 +
26065 + if (core_if->dma_desc_enable == 0) {
26066 + deptsiz.b.xfersize =
26067 + (ep->total_len - ep->xfer_count) >
26068 + ep->maxpacket ? ep->maxpacket : (ep->total_len -
26069 + ep->xfer_count);
26070 + deptsiz.b.pktcnt = 1;
26071 + if (core_if->dma_enable == 0) {
26072 + ep->xfer_len += deptsiz.b.xfersize;
26073 + } else {
26074 + ep->xfer_len = deptsiz.b.xfersize;
26075 + }
26076 + DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
26077 + } else {
26078 + ep->xfer_len =
26079 + (ep->total_len - ep->xfer_count) >
26080 + ep->maxpacket ? ep->maxpacket : (ep->total_len -
26081 + ep->xfer_count);
26082 +
26083 + dma_desc = core_if->dev_if->in_desc_addr;
26084 +
26085 + /** DMA Descriptor Setup */
26086 + dma_desc->status.b.bs = BS_HOST_BUSY;
26087 + dma_desc->status.b.l = 1;
26088 + dma_desc->status.b.ioc = 1;
26089 + dma_desc->status.b.sp =
26090 + (ep->xfer_len == ep->maxpacket) ? 0 : 1;
26091 + dma_desc->status.b.bytes = ep->xfer_len;
26092 + dma_desc->buf = ep->dma_addr;
26093 + dma_desc->status.b.sts = 0;
26094 + dma_desc->status.b.bs = BS_HOST_READY;
26095 +
26096 + /** DIEPDMA0 Register write */
26097 + DWC_WRITE_REG32(&in_regs->diepdma,
26098 + core_if->dev_if->dma_in_desc_addr);
26099 + }
26100 +
26101 + DWC_DEBUGPL(DBG_PCDV,
26102 + "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
26103 + ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
26104 + deptsiz.d32);
26105 +
26106 + /* Write the DMA register */
26107 + if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
26108 + if (core_if->dma_desc_enable == 0)
26109 + DWC_WRITE_REG32(&(in_regs->diepdma),
26110 + (uint32_t) ep->dma_addr);
26111 + }
26112 + if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
26113 + depctl.b.nextep = core_if->nextep_seq[ep->num];
26114 + /* EP enable, IN data in FIFO */
26115 + depctl.b.cnak = 1;
26116 + depctl.b.epena = 1;
26117 + DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
26118 +
26119 + /**
26120 + * Enable the Non-Periodic Tx FIFO empty interrupt, the
26121 + * data will be written into the fifo by the ISR.
26122 + */
26123 + if (!core_if->dma_enable) {
26124 + if (core_if->en_multiple_tx_fifo == 0) {
26125 + /* First clear it from GINTSTS */
26126 + intr_mask.b.nptxfempty = 1;
26127 + DWC_MODIFY_REG32(&core_if->
26128 + core_global_regs->gintmsk,
26129 + intr_mask.d32, intr_mask.d32);
26130 +
26131 + } else {
26132 + /* Enable the Tx FIFO Empty Interrupt for this EP */
26133 + if (ep->xfer_len > 0) {
26134 + uint32_t fifoemptymsk = 0;
26135 + fifoemptymsk |= 1 << ep->num;
26136 + DWC_MODIFY_REG32(&core_if->
26137 + dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
26138 + 0, fifoemptymsk);
26139 + }
26140 + }
26141 + }
26142 + } else {
26143 + dwc_otg_dev_out_ep_regs_t *out_regs =
26144 + core_if->dev_if->out_ep_regs[0];
26145 +
26146 + depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
26147 + deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
26148 +
26149 + /* Program the transfer size and packet count
26150 + * as follows: xfersize = N * maxpacket +
26151 + * short_packet pktcnt = N + (short_packet
26152 + * exist ? 1 : 0)
26153 + */
26154 + deptsiz.b.xfersize = ep->maxpacket;
26155 + deptsiz.b.pktcnt = 1;
26156 +
26157 + if (core_if->dma_desc_enable == 0) {
26158 + DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
26159 + } else {
26160 + dma_desc = core_if->dev_if->out_desc_addr;
26161 +
26162 + /** DMA Descriptor Setup */
26163 + dma_desc->status.b.bs = BS_HOST_BUSY;
26164 + dma_desc->status.b.l = 1;
26165 + dma_desc->status.b.ioc = 1;
26166 + dma_desc->status.b.bytes = ep->maxpacket;
26167 + dma_desc->buf = ep->dma_addr;
26168 + dma_desc->status.b.sts = 0;
26169 + dma_desc->status.b.bs = BS_HOST_READY;
26170 +
26171 + /** DOEPDMA0 Register write */
26172 + DWC_WRITE_REG32(&out_regs->doepdma,
26173 + core_if->dev_if->dma_out_desc_addr);
26174 + }
26175 +
26176 + DWC_DEBUGPL(DBG_PCDV,
26177 + "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
26178 + ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
26179 + deptsiz.d32);
26180 +
26181 + /* Write the DMA register */
26182 + if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
26183 + if (core_if->dma_desc_enable == 0)
26184 + DWC_WRITE_REG32(&(out_regs->doepdma),
26185 + (uint32_t) ep->dma_addr);
26186 +
26187 + }
26188 +
26189 + /* EP enable, IN data in FIFO */
26190 + depctl.b.cnak = 1;
26191 + depctl.b.epena = 1;
26192 + DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
26193 +
26194 + }
26195 +}
26196 +
26197 +#ifdef DEBUG
26198 +void dump_msg(const u8 * buf, unsigned int length)
26199 +{
26200 + unsigned int start, num, i;
26201 + char line[52], *p;
26202 +
26203 + if (length >= 512)
26204 + return;
26205 + start = 0;
26206 + while (length > 0) {
26207 + num = length < 16u ? length : 16u;
26208 + p = line;
26209 + for (i = 0; i < num; ++i) {
26210 + if (i == 8)
26211 + *p++ = ' ';
26212 + DWC_SPRINTF(p, " %02x", buf[i]);
26213 + p += 3;
26214 + }
26215 + *p = 0;
26216 + DWC_PRINTF("%6x: %s\n", start, line);
26217 + buf += num;
26218 + start += num;
26219 + length -= num;
26220 + }
26221 +}
26222 +#else
26223 +static inline void dump_msg(const u8 * buf, unsigned int length)
26224 +{
26225 +}
26226 +#endif
26227 +
26228 +/**
26229 + * This function writes a packet into the Tx FIFO associated with the
26230 + * EP. For non-periodic EPs the non-periodic Tx FIFO is written. For
26231 + * periodic EPs the periodic Tx FIFO associated with the EP is written
26232 + * with all packets for the next micro-frame.
26233 + *
26234 + * @param core_if Programming view of DWC_otg controller.
26235 + * @param ep The EP to write packet for.
26236 + * @param dma Indicates if DMA is being used.
26237 + */
26238 +void dwc_otg_ep_write_packet(dwc_otg_core_if_t * core_if, dwc_ep_t * ep,
26239 + int dma)
26240 +{
26241 + /**
26242 + * The buffer is padded to DWORD on a per packet basis in
26243 + * slave/dma mode if the MPS is not DWORD aligned. The last
26244 + * packet, if short, is also padded to a multiple of DWORD.
26245 + *
26246 + * ep->xfer_buff always starts DWORD aligned in memory and is a
26247 + * multiple of DWORD in length
26248 + *
26249 + * ep->xfer_len can be any number of bytes
26250 + *
26251 + * ep->xfer_count is a multiple of ep->maxpacket until the last
26252 + * packet
26253 + *
26254 + * FIFO access is DWORD */
26255 +
26256 + uint32_t i;
26257 + uint32_t byte_count;
26258 + uint32_t dword_count;
26259 + uint32_t *fifo;
26260 + uint32_t *data_buff = (uint32_t *) ep->xfer_buff;
26261 +
26262 + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if,
26263 + ep);
26264 + if (ep->xfer_count >= ep->xfer_len) {
26265 + DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num);
26266 + return;
26267 + }
26268 +
26269 + /* Find the byte length of the packet either short packet or MPS */
26270 + if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) {
26271 + byte_count = ep->xfer_len - ep->xfer_count;
26272 + } else {
26273 + byte_count = ep->maxpacket;
26274 + }
26275 +
26276 + /* Find the DWORD length, padded by extra bytes as neccessary if MPS
26277 + * is not a multiple of DWORD */
26278 + dword_count = (byte_count + 3) / 4;
26279 +
26280 +#ifdef VERBOSE
26281 + dump_msg(ep->xfer_buff, byte_count);
26282 +#endif
26283 +
26284 + /**@todo NGS Where are the Periodic Tx FIFO addresses
26285 + * intialized? What should this be? */
26286 +
26287 + fifo = core_if->data_fifo[ep->num];
26288 +
26289 + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n",
26290 + fifo, data_buff, *data_buff, byte_count);
26291 +
26292 + if (!dma) {
26293 + for (i = 0; i < dword_count; i++, data_buff++) {
26294 + DWC_WRITE_REG32(fifo, *data_buff);
26295 + }
26296 + }
26297 +
26298 + ep->xfer_count += byte_count;
26299 + ep->xfer_buff += byte_count;
26300 + ep->dma_addr += byte_count;
26301 +}
26302 +
26303 +/**
26304 + * Set the EP STALL.
26305 + *
26306 + * @param core_if Programming view of DWC_otg controller.
26307 + * @param ep The EP to set the stall on.
26308 + */
26309 +void dwc_otg_ep_set_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
26310 +{
26311 + depctl_data_t depctl;
26312 + volatile uint32_t *depctl_addr;
26313 +
26314 + DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
26315 + (ep->is_in ? "IN" : "OUT"));
26316 +
26317 + if (ep->is_in == 1) {
26318 + depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
26319 + depctl.d32 = DWC_READ_REG32(depctl_addr);
26320 +
26321 + /* set the disable and stall bits */
26322 + if (depctl.b.epena) {
26323 + depctl.b.epdis = 1;
26324 + }
26325 + depctl.b.stall = 1;
26326 + DWC_WRITE_REG32(depctl_addr, depctl.d32);
26327 + } else {
26328 + depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
26329 + depctl.d32 = DWC_READ_REG32(depctl_addr);
26330 +
26331 + /* set the stall bit */
26332 + depctl.b.stall = 1;
26333 + DWC_WRITE_REG32(depctl_addr, depctl.d32);
26334 + }
26335 +
26336 + DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
26337 +
26338 + return;
26339 +}
26340 +
26341 +/**
26342 + * Clear the EP STALL.
26343 + *
26344 + * @param core_if Programming view of DWC_otg controller.
26345 + * @param ep The EP to clear stall from.
26346 + */
26347 +void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
26348 +{
26349 + depctl_data_t depctl;
26350 + volatile uint32_t *depctl_addr;
26351 +
26352 + DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
26353 + (ep->is_in ? "IN" : "OUT"));
26354 +
26355 + if (ep->is_in == 1) {
26356 + depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
26357 + } else {
26358 + depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
26359 + }
26360 +
26361 + depctl.d32 = DWC_READ_REG32(depctl_addr);
26362 +
26363 + /* clear the stall bits */
26364 + depctl.b.stall = 0;
26365 +
26366 + /*
26367 + * USB Spec 9.4.5: For endpoints using data toggle, regardless
26368 + * of whether an endpoint has the Halt feature set, a
26369 + * ClearFeature(ENDPOINT_HALT) request always results in the
26370 + * data toggle being reinitialized to DATA0.
26371 + */
26372 + if (ep->type == DWC_OTG_EP_TYPE_INTR ||
26373 + ep->type == DWC_OTG_EP_TYPE_BULK) {
26374 + depctl.b.setd0pid = 1; /* DATA0 */
26375 + }
26376 +
26377 + DWC_WRITE_REG32(depctl_addr, depctl.d32);
26378 + DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
26379 + return;
26380 +}
26381 +
26382 +/**
26383 + * This function reads a packet from the Rx FIFO into the destination
26384 + * buffer. To read SETUP data use dwc_otg_read_setup_packet.
26385 + *
26386 + * @param core_if Programming view of DWC_otg controller.
26387 + * @param dest Destination buffer for the packet.
26388 + * @param bytes Number of bytes to copy to the destination.
26389 + */
26390 +void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
26391 + uint8_t * dest, uint16_t bytes)
26392 +{
26393 + int i;
26394 + int word_count = (bytes + 3) / 4;
26395 +
26396 + volatile uint32_t *fifo = core_if->data_fifo[0];
26397 + uint32_t *data_buff = (uint32_t *) dest;
26398 +
26399 + /**
26400 + * @todo Account for the case where _dest is not dword aligned. This
26401 + * requires reading data from the FIFO into a uint32_t temp buffer,
26402 + * then moving it into the data buffer.
26403 + */
26404 +
26405 + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__,
26406 + core_if, dest, bytes);
26407 +
26408 + for (i = 0; i < word_count; i++, data_buff++) {
26409 + *data_buff = DWC_READ_REG32(fifo);
26410 + }
26411 +
26412 + return;
26413 +}
26414 +
26415 +/**
26416 + * This functions reads the device registers and prints them
26417 + *
26418 + * @param core_if Programming view of DWC_otg controller.
26419 + */
26420 +void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * core_if)
26421 +{
26422 + int i;
26423 + volatile uint32_t *addr;
26424 +
26425 + DWC_PRINTF("Device Global Registers\n");
26426 + addr = &core_if->dev_if->dev_global_regs->dcfg;
26427 + DWC_PRINTF("DCFG @0x%08lX : 0x%08X\n",
26428 + (unsigned long)addr, DWC_READ_REG32(addr));
26429 + addr = &core_if->dev_if->dev_global_regs->dctl;
26430 + DWC_PRINTF("DCTL @0x%08lX : 0x%08X\n",
26431 + (unsigned long)addr, DWC_READ_REG32(addr));
26432 + addr = &core_if->dev_if->dev_global_regs->dsts;
26433 + DWC_PRINTF("DSTS @0x%08lX : 0x%08X\n",
26434 + (unsigned long)addr, DWC_READ_REG32(addr));
26435 + addr = &core_if->dev_if->dev_global_regs->diepmsk;
26436 + DWC_PRINTF("DIEPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
26437 + DWC_READ_REG32(addr));
26438 + addr = &core_if->dev_if->dev_global_regs->doepmsk;
26439 + DWC_PRINTF("DOEPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
26440 + DWC_READ_REG32(addr));
26441 + addr = &core_if->dev_if->dev_global_regs->daint;
26442 + DWC_PRINTF("DAINT @0x%08lX : 0x%08X\n", (unsigned long)addr,
26443 + DWC_READ_REG32(addr));
26444 + addr = &core_if->dev_if->dev_global_regs->daintmsk;
26445 + DWC_PRINTF("DAINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
26446 + DWC_READ_REG32(addr));
26447 + addr = &core_if->dev_if->dev_global_regs->dtknqr1;
26448 + DWC_PRINTF("DTKNQR1 @0x%08lX : 0x%08X\n", (unsigned long)addr,
26449 + DWC_READ_REG32(addr));
26450 + if (core_if->hwcfg2.b.dev_token_q_depth > 6) {
26451 + addr = &core_if->dev_if->dev_global_regs->dtknqr2;
26452 + DWC_PRINTF("DTKNQR2 @0x%08lX : 0x%08X\n",
26453 + (unsigned long)addr, DWC_READ_REG32(addr));
26454 + }
26455 +
26456 + addr = &core_if->dev_if->dev_global_regs->dvbusdis;
26457 + DWC_PRINTF("DVBUSID @0x%08lX : 0x%08X\n", (unsigned long)addr,
26458 + DWC_READ_REG32(addr));
26459 +
26460 + addr = &core_if->dev_if->dev_global_regs->dvbuspulse;
26461 + DWC_PRINTF("DVBUSPULSE @0x%08lX : 0x%08X\n",
26462 + (unsigned long)addr, DWC_READ_REG32(addr));
26463 +
26464 + addr = &core_if->dev_if->dev_global_regs->dtknqr3_dthrctl;
26465 + DWC_PRINTF("DTKNQR3_DTHRCTL @0x%08lX : 0x%08X\n",
26466 + (unsigned long)addr, DWC_READ_REG32(addr));
26467 +
26468 + if (core_if->hwcfg2.b.dev_token_q_depth > 22) {
26469 + addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
26470 + DWC_PRINTF("DTKNQR4 @0x%08lX : 0x%08X\n",
26471 + (unsigned long)addr, DWC_READ_REG32(addr));
26472 + }
26473 +
26474 + addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
26475 + DWC_PRINTF("FIFOEMPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
26476 + DWC_READ_REG32(addr));
26477 +
26478 + if (core_if->hwcfg2.b.multi_proc_int) {
26479 +
26480 + addr = &core_if->dev_if->dev_global_regs->deachint;
26481 + DWC_PRINTF("DEACHINT @0x%08lX : 0x%08X\n",
26482 + (unsigned long)addr, DWC_READ_REG32(addr));
26483 + addr = &core_if->dev_if->dev_global_regs->deachintmsk;
26484 + DWC_PRINTF("DEACHINTMSK @0x%08lX : 0x%08X\n",
26485 + (unsigned long)addr, DWC_READ_REG32(addr));
26486 +
26487 + for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
26488 + addr =
26489 + &core_if->dev_if->
26490 + dev_global_regs->diepeachintmsk[i];
26491 + DWC_PRINTF("DIEPEACHINTMSK[%d] @0x%08lX : 0x%08X\n",
26492 + i, (unsigned long)addr,
26493 + DWC_READ_REG32(addr));
26494 + }
26495 +
26496 + for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
26497 + addr =
26498 + &core_if->dev_if->
26499 + dev_global_regs->doepeachintmsk[i];
26500 + DWC_PRINTF("DOEPEACHINTMSK[%d] @0x%08lX : 0x%08X\n",
26501 + i, (unsigned long)addr,
26502 + DWC_READ_REG32(addr));
26503 + }
26504 + }
26505 +
26506 + for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
26507 + DWC_PRINTF("Device IN EP %d Registers\n", i);
26508 + addr = &core_if->dev_if->in_ep_regs[i]->diepctl;
26509 + DWC_PRINTF("DIEPCTL @0x%08lX : 0x%08X\n",
26510 + (unsigned long)addr, DWC_READ_REG32(addr));
26511 + addr = &core_if->dev_if->in_ep_regs[i]->diepint;
26512 + DWC_PRINTF("DIEPINT @0x%08lX : 0x%08X\n",
26513 + (unsigned long)addr, DWC_READ_REG32(addr));
26514 + addr = &core_if->dev_if->in_ep_regs[i]->dieptsiz;
26515 + DWC_PRINTF("DIETSIZ @0x%08lX : 0x%08X\n",
26516 + (unsigned long)addr, DWC_READ_REG32(addr));
26517 + addr = &core_if->dev_if->in_ep_regs[i]->diepdma;
26518 + DWC_PRINTF("DIEPDMA @0x%08lX : 0x%08X\n",
26519 + (unsigned long)addr, DWC_READ_REG32(addr));
26520 + addr = &core_if->dev_if->in_ep_regs[i]->dtxfsts;
26521 + DWC_PRINTF("DTXFSTS @0x%08lX : 0x%08X\n",
26522 + (unsigned long)addr, DWC_READ_REG32(addr));
26523 + addr = &core_if->dev_if->in_ep_regs[i]->diepdmab;
26524 + DWC_PRINTF("DIEPDMAB @0x%08lX : 0x%08X\n",
26525 + (unsigned long)addr, 0 /*DWC_READ_REG32(addr) */ );
26526 + }
26527 +
26528 + for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
26529 + DWC_PRINTF("Device OUT EP %d Registers\n", i);
26530 + addr = &core_if->dev_if->out_ep_regs[i]->doepctl;
26531 + DWC_PRINTF("DOEPCTL @0x%08lX : 0x%08X\n",
26532 + (unsigned long)addr, DWC_READ_REG32(addr));
26533 + addr = &core_if->dev_if->out_ep_regs[i]->doepint;
26534 + DWC_PRINTF("DOEPINT @0x%08lX : 0x%08X\n",
26535 + (unsigned long)addr, DWC_READ_REG32(addr));
26536 + addr = &core_if->dev_if->out_ep_regs[i]->doeptsiz;
26537 + DWC_PRINTF("DOETSIZ @0x%08lX : 0x%08X\n",
26538 + (unsigned long)addr, DWC_READ_REG32(addr));
26539 + addr = &core_if->dev_if->out_ep_regs[i]->doepdma;
26540 + DWC_PRINTF("DOEPDMA @0x%08lX : 0x%08X\n",
26541 + (unsigned long)addr, DWC_READ_REG32(addr));
26542 + if (core_if->dma_enable) { /* Don't access this register in SLAVE mode */
26543 + addr = &core_if->dev_if->out_ep_regs[i]->doepdmab;
26544 + DWC_PRINTF("DOEPDMAB @0x%08lX : 0x%08X\n",
26545 + (unsigned long)addr, DWC_READ_REG32(addr));
26546 + }
26547 +
26548 + }
26549 +}
26550 +
26551 +/**
26552 + * This functions reads the SPRAM and prints its content
26553 + *
26554 + * @param core_if Programming view of DWC_otg controller.
26555 + */
26556 +void dwc_otg_dump_spram(dwc_otg_core_if_t * core_if)
26557 +{
26558 + volatile uint8_t *addr, *start_addr, *end_addr;
26559 +
26560 + DWC_PRINTF("SPRAM Data:\n");
26561 + start_addr = (void *)core_if->core_global_regs;
26562 + DWC_PRINTF("Base Address: 0x%8lX\n", (unsigned long)start_addr);
26563 + start_addr += 0x00028000;
26564 + end_addr = (void *)core_if->core_global_regs;
26565 + end_addr += 0x000280e0;
26566 +
26567 + for (addr = start_addr; addr < end_addr; addr += 16) {
26568 + DWC_PRINTF
26569 + ("0x%8lX:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n",
26570 + (unsigned long)addr, addr[0], addr[1], addr[2], addr[3],
26571 + addr[4], addr[5], addr[6], addr[7], addr[8], addr[9],
26572 + addr[10], addr[11], addr[12], addr[13], addr[14], addr[15]
26573 + );
26574 + }
26575 +
26576 + return;
26577 +}
26578 +
26579 +/**
26580 + * This function reads the host registers and prints them
26581 + *
26582 + * @param core_if Programming view of DWC_otg controller.
26583 + */
26584 +void dwc_otg_dump_host_registers(dwc_otg_core_if_t * core_if)
26585 +{
26586 + int i;
26587 + volatile uint32_t *addr;
26588 +
26589 + DWC_PRINTF("Host Global Registers\n");
26590 + addr = &core_if->host_if->host_global_regs->hcfg;
26591 + DWC_PRINTF("HCFG @0x%08lX : 0x%08X\n",
26592 + (unsigned long)addr, DWC_READ_REG32(addr));
26593 + addr = &core_if->host_if->host_global_regs->hfir;
26594 + DWC_PRINTF("HFIR @0x%08lX : 0x%08X\n",
26595 + (unsigned long)addr, DWC_READ_REG32(addr));
26596 + addr = &core_if->host_if->host_global_regs->hfnum;
26597 + DWC_PRINTF("HFNUM @0x%08lX : 0x%08X\n", (unsigned long)addr,
26598 + DWC_READ_REG32(addr));
26599 + addr = &core_if->host_if->host_global_regs->hptxsts;
26600 + DWC_PRINTF("HPTXSTS @0x%08lX : 0x%08X\n", (unsigned long)addr,
26601 + DWC_READ_REG32(addr));
26602 + addr = &core_if->host_if->host_global_regs->haint;
26603 + DWC_PRINTF("HAINT @0x%08lX : 0x%08X\n", (unsigned long)addr,
26604 + DWC_READ_REG32(addr));
26605 + addr = &core_if->host_if->host_global_regs->haintmsk;
26606 + DWC_PRINTF("HAINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
26607 + DWC_READ_REG32(addr));
26608 + if (core_if->dma_desc_enable) {
26609 + addr = &core_if->host_if->host_global_regs->hflbaddr;
26610 + DWC_PRINTF("HFLBADDR @0x%08lX : 0x%08X\n",
26611 + (unsigned long)addr, DWC_READ_REG32(addr));
26612 + }
26613 +
26614 + addr = core_if->host_if->hprt0;
26615 + DWC_PRINTF("HPRT0 @0x%08lX : 0x%08X\n", (unsigned long)addr,
26616 + DWC_READ_REG32(addr));
26617 +
26618 + for (i = 0; i < core_if->core_params->host_channels; i++) {
26619 + DWC_PRINTF("Host Channel %d Specific Registers\n", i);
26620 + addr = &core_if->host_if->hc_regs[i]->hcchar;
26621 + DWC_PRINTF("HCCHAR @0x%08lX : 0x%08X\n",
26622 + (unsigned long)addr, DWC_READ_REG32(addr));
26623 + addr = &core_if->host_if->hc_regs[i]->hcsplt;
26624 + DWC_PRINTF("HCSPLT @0x%08lX : 0x%08X\n",
26625 + (unsigned long)addr, DWC_READ_REG32(addr));
26626 + addr = &core_if->host_if->hc_regs[i]->hcint;
26627 + DWC_PRINTF("HCINT @0x%08lX : 0x%08X\n",
26628 + (unsigned long)addr, DWC_READ_REG32(addr));
26629 + addr = &core_if->host_if->hc_regs[i]->hcintmsk;
26630 + DWC_PRINTF("HCINTMSK @0x%08lX : 0x%08X\n",
26631 + (unsigned long)addr, DWC_READ_REG32(addr));
26632 + addr = &core_if->host_if->hc_regs[i]->hctsiz;
26633 + DWC_PRINTF("HCTSIZ @0x%08lX : 0x%08X\n",
26634 + (unsigned long)addr, DWC_READ_REG32(addr));
26635 + addr = &core_if->host_if->hc_regs[i]->hcdma;
26636 + DWC_PRINTF("HCDMA @0x%08lX : 0x%08X\n",
26637 + (unsigned long)addr, DWC_READ_REG32(addr));
26638 + if (core_if->dma_desc_enable) {
26639 + addr = &core_if->host_if->hc_regs[i]->hcdmab;
26640 + DWC_PRINTF("HCDMAB @0x%08lX : 0x%08X\n",
26641 + (unsigned long)addr, DWC_READ_REG32(addr));
26642 + }
26643 +
26644 + }
26645 + return;
26646 +}
26647 +
26648 +/**
26649 + * This function reads the core global registers and prints them
26650 + *
26651 + * @param core_if Programming view of DWC_otg controller.
26652 + */
26653 +void dwc_otg_dump_global_registers(dwc_otg_core_if_t * core_if)
26654 +{
26655 + int i, ep_num;
26656 + volatile uint32_t *addr;
26657 + char *txfsiz;
26658 +
26659 + DWC_PRINTF("Core Global Registers\n");
26660 + addr = &core_if->core_global_regs->gotgctl;
26661 + DWC_PRINTF("GOTGCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
26662 + DWC_READ_REG32(addr));
26663 + addr = &core_if->core_global_regs->gotgint;
26664 + DWC_PRINTF("GOTGINT @0x%08lX : 0x%08X\n", (unsigned long)addr,
26665 + DWC_READ_REG32(addr));
26666 + addr = &core_if->core_global_regs->gahbcfg;
26667 + DWC_PRINTF("GAHBCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
26668 + DWC_READ_REG32(addr));
26669 + addr = &core_if->core_global_regs->gusbcfg;
26670 + DWC_PRINTF("GUSBCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
26671 + DWC_READ_REG32(addr));
26672 + addr = &core_if->core_global_regs->grstctl;
26673 + DWC_PRINTF("GRSTCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
26674 + DWC_READ_REG32(addr));
26675 + addr = &core_if->core_global_regs->gintsts;
26676 + DWC_PRINTF("GINTSTS @0x%08lX : 0x%08X\n", (unsigned long)addr,
26677 + DWC_READ_REG32(addr));
26678 + addr = &core_if->core_global_regs->gintmsk;
26679 + DWC_PRINTF("GINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
26680 + DWC_READ_REG32(addr));
26681 + addr = &core_if->core_global_regs->grxstsr;
26682 + DWC_PRINTF("GRXSTSR @0x%08lX : 0x%08X\n", (unsigned long)addr,
26683 + DWC_READ_REG32(addr));
26684 + addr = &core_if->core_global_regs->grxfsiz;
26685 + DWC_PRINTF("GRXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
26686 + DWC_READ_REG32(addr));
26687 + addr = &core_if->core_global_regs->gnptxfsiz;
26688 + DWC_PRINTF("GNPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
26689 + DWC_READ_REG32(addr));
26690 + addr = &core_if->core_global_regs->gnptxsts;
26691 + DWC_PRINTF("GNPTXSTS @0x%08lX : 0x%08X\n", (unsigned long)addr,
26692 + DWC_READ_REG32(addr));
26693 + addr = &core_if->core_global_regs->gi2cctl;
26694 + DWC_PRINTF("GI2CCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
26695 + DWC_READ_REG32(addr));
26696 + addr = &core_if->core_global_regs->gpvndctl;
26697 + DWC_PRINTF("GPVNDCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
26698 + DWC_READ_REG32(addr));
26699 + addr = &core_if->core_global_regs->ggpio;
26700 + DWC_PRINTF("GGPIO @0x%08lX : 0x%08X\n", (unsigned long)addr,
26701 + DWC_READ_REG32(addr));
26702 + addr = &core_if->core_global_regs->guid;
26703 + DWC_PRINTF("GUID @0x%08lX : 0x%08X\n",
26704 + (unsigned long)addr, DWC_READ_REG32(addr));
26705 + addr = &core_if->core_global_regs->gsnpsid;
26706 + DWC_PRINTF("GSNPSID @0x%08lX : 0x%08X\n", (unsigned long)addr,
26707 + DWC_READ_REG32(addr));
26708 + addr = &core_if->core_global_regs->ghwcfg1;
26709 + DWC_PRINTF("GHWCFG1 @0x%08lX : 0x%08X\n", (unsigned long)addr,
26710 + DWC_READ_REG32(addr));
26711 + addr = &core_if->core_global_regs->ghwcfg2;
26712 + DWC_PRINTF("GHWCFG2 @0x%08lX : 0x%08X\n", (unsigned long)addr,
26713 + DWC_READ_REG32(addr));
26714 + addr = &core_if->core_global_regs->ghwcfg3;
26715 + DWC_PRINTF("GHWCFG3 @0x%08lX : 0x%08X\n", (unsigned long)addr,
26716 + DWC_READ_REG32(addr));
26717 + addr = &core_if->core_global_regs->ghwcfg4;
26718 + DWC_PRINTF("GHWCFG4 @0x%08lX : 0x%08X\n", (unsigned long)addr,
26719 + DWC_READ_REG32(addr));
26720 + addr = &core_if->core_global_regs->glpmcfg;
26721 + DWC_PRINTF("GLPMCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
26722 + DWC_READ_REG32(addr));
26723 + addr = &core_if->core_global_regs->gpwrdn;
26724 + DWC_PRINTF("GPWRDN @0x%08lX : 0x%08X\n", (unsigned long)addr,
26725 + DWC_READ_REG32(addr));
26726 + addr = &core_if->core_global_regs->gdfifocfg;
26727 + DWC_PRINTF("GDFIFOCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
26728 + DWC_READ_REG32(addr));
26729 + addr = &core_if->core_global_regs->adpctl;
26730 + DWC_PRINTF("ADPCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
26731 + dwc_otg_adp_read_reg(core_if));
26732 + addr = &core_if->core_global_regs->hptxfsiz;
26733 + DWC_PRINTF("HPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
26734 + DWC_READ_REG32(addr));
26735 +
26736 + if (core_if->en_multiple_tx_fifo == 0) {
26737 + ep_num = core_if->hwcfg4.b.num_dev_perio_in_ep;
26738 + txfsiz = "DPTXFSIZ";
26739 + } else {
26740 + ep_num = core_if->hwcfg4.b.num_in_eps;
26741 + txfsiz = "DIENPTXF";
26742 + }
26743 + for (i = 0; i < ep_num; i++) {
26744 + addr = &core_if->core_global_regs->dtxfsiz[i];
26745 + DWC_PRINTF("%s[%d] @0x%08lX : 0x%08X\n", txfsiz, i + 1,
26746 + (unsigned long)addr, DWC_READ_REG32(addr));
26747 + }
26748 + addr = core_if->pcgcctl;
26749 + DWC_PRINTF("PCGCCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
26750 + DWC_READ_REG32(addr));
26751 +}
26752 +
26753 +/**
26754 + * Flush a Tx FIFO.
26755 + *
26756 + * @param core_if Programming view of DWC_otg controller.
26757 + * @param num Tx FIFO to flush.
26758 + */
26759 +void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * core_if, const int num)
26760 +{
26761 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
26762 + volatile grstctl_t greset = {.d32 = 0 };
26763 + int count = 0;
26764 +
26765 + DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "Flush Tx FIFO %d\n", num);
26766 +
26767 + greset.b.txfflsh = 1;
26768 + greset.b.txfnum = num;
26769 + DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
26770 +
26771 + do {
26772 + greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
26773 + if (++count > 10000) {
26774 + DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
26775 + __func__, greset.d32,
26776 + DWC_READ_REG32(&global_regs->gnptxsts));
26777 + break;
26778 + }
26779 + dwc_udelay(1);
26780 + } while (greset.b.txfflsh == 1);
26781 +
26782 + /* Wait for 3 PHY Clocks */
26783 + dwc_udelay(1);
26784 +}
26785 +
26786 +/**
26787 + * Flush Rx FIFO.
26788 + *
26789 + * @param core_if Programming view of DWC_otg controller.
26790 + */
26791 +void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * core_if)
26792 +{
26793 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
26794 + volatile grstctl_t greset = {.d32 = 0 };
26795 + int count = 0;
26796 +
26797 + DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "%s\n", __func__);
26798 + /*
26799 + *
26800 + */
26801 + greset.b.rxfflsh = 1;
26802 + DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
26803 +
26804 + do {
26805 + greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
26806 + if (++count > 10000) {
26807 + DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__,
26808 + greset.d32);
26809 + break;
26810 + }
26811 + dwc_udelay(1);
26812 + } while (greset.b.rxfflsh == 1);
26813 +
26814 + /* Wait for 3 PHY Clocks */
26815 + dwc_udelay(1);
26816 +}
26817 +
26818 +/**
26819 + * Do core a soft reset of the core. Be careful with this because it
26820 + * resets all the internal state machines of the core.
26821 + */
26822 +void dwc_otg_core_reset(dwc_otg_core_if_t * core_if)
26823 +{
26824 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
26825 + volatile grstctl_t greset = {.d32 = 0 };
26826 + int count = 0;
26827 +
26828 + DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
26829 + /* Wait for AHB master IDLE state. */
26830 + do {
26831 + dwc_udelay(10);
26832 + greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
26833 + if (++count > 100000) {
26834 + DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__,
26835 + greset.d32);
26836 + return;
26837 + }
26838 + }
26839 + while (greset.b.ahbidle == 0);
26840 +
26841 + /* Core Soft Reset */
26842 + count = 0;
26843 + greset.b.csftrst = 1;
26844 + DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
26845 + do {
26846 + greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
26847 + if (++count > 10000) {
26848 + DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n",
26849 + __func__, greset.d32);
26850 + break;
26851 + }
26852 + dwc_udelay(1);
26853 + }
26854 + while (greset.b.csftrst == 1);
26855 +
26856 + /* Wait for 3 PHY Clocks */
26857 + dwc_mdelay(100);
26858 +}
26859 +
26860 +uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if)
26861 +{
26862 + return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
26863 +}
26864 +
26865 +uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if)
26866 +{
26867 + return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
26868 +}
26869 +
26870 +/**
26871 + * Register HCD callbacks. The callbacks are used to start and stop
26872 + * the HCD for interrupt processing.
26873 + *
26874 + * @param core_if Programming view of DWC_otg controller.
26875 + * @param cb the HCD callback structure.
26876 + * @param p pointer to be passed to callback function (usb_hcd*).
26877 + */
26878 +void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * core_if,
26879 + dwc_otg_cil_callbacks_t * cb, void *p)
26880 +{
26881 + core_if->hcd_cb = cb;
26882 + cb->p = p;
26883 +}
26884 +
26885 +/**
26886 + * Register PCD callbacks. The callbacks are used to start and stop
26887 + * the PCD for interrupt processing.
26888 + *
26889 + * @param core_if Programming view of DWC_otg controller.
26890 + * @param cb the PCD callback structure.
26891 + * @param p pointer to be passed to callback function (pcd*).
26892 + */
26893 +void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * core_if,
26894 + dwc_otg_cil_callbacks_t * cb, void *p)
26895 +{
26896 + core_if->pcd_cb = cb;
26897 + cb->p = p;
26898 +}
26899 +
26900 +#ifdef DWC_EN_ISOC
26901 +
26902 +/**
26903 + * This function writes isoc data per 1 (micro)frame into tx fifo
26904 + *
26905 + * @param core_if Programming view of DWC_otg controller.
26906 + * @param ep The EP to start the transfer on.
26907 + *
26908 + */
26909 +void write_isoc_frame_data(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
26910 +{
26911 + dwc_otg_dev_in_ep_regs_t *ep_regs;
26912 + dtxfsts_data_t txstatus = {.d32 = 0 };
26913 + uint32_t len = 0;
26914 + uint32_t dwords;
26915 +
26916 + ep->xfer_len = ep->data_per_frame;
26917 + ep->xfer_count = 0;
26918 +
26919 + ep_regs = core_if->dev_if->in_ep_regs[ep->num];
26920 +
26921 + len = ep->xfer_len - ep->xfer_count;
26922 +
26923 + if (len > ep->maxpacket) {
26924 + len = ep->maxpacket;
26925 + }
26926 +
26927 + dwords = (len + 3) / 4;
26928 +
26929 + /* While there is space in the queue and space in the FIFO and
26930 + * More data to tranfer, Write packets to the Tx FIFO */
26931 + txstatus.d32 =
26932 + DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
26933 + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32);
26934 +
26935 + while (txstatus.b.txfspcavail > dwords &&
26936 + ep->xfer_count < ep->xfer_len && ep->xfer_len != 0) {
26937 + /* Write the FIFO */
26938 + dwc_otg_ep_write_packet(core_if, ep, 0);
26939 +
26940 + len = ep->xfer_len - ep->xfer_count;
26941 + if (len > ep->maxpacket) {
26942 + len = ep->maxpacket;
26943 + }
26944 +
26945 + dwords = (len + 3) / 4;
26946 + txstatus.d32 =
26947 + DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
26948 + dtxfsts);
26949 + DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", ep->num,
26950 + txstatus.d32);
26951 + }
26952 +}
26953 +
26954 +/**
26955 + * This function initializes a descriptor chain for Isochronous transfer
26956 + *
26957 + * @param core_if Programming view of DWC_otg controller.
26958 + * @param ep The EP to start the transfer on.
26959 + *
26960 + */
26961 +void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
26962 + dwc_ep_t * ep)
26963 +{
26964 + deptsiz_data_t deptsiz = {.d32 = 0 };
26965 + depctl_data_t depctl = {.d32 = 0 };
26966 + dsts_data_t dsts = {.d32 = 0 };
26967 + volatile uint32_t *addr;
26968 +
26969 + if (ep->is_in) {
26970 + addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
26971 + } else {
26972 + addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
26973 + }
26974 +
26975 + ep->xfer_len = ep->data_per_frame;
26976 + ep->xfer_count = 0;
26977 + ep->xfer_buff = ep->cur_pkt_addr;
26978 + ep->dma_addr = ep->cur_pkt_dma_addr;
26979 +
26980 + if (ep->is_in) {
26981 + /* Program the transfer size and packet count
26982 + * as follows: xfersize = N * maxpacket +
26983 + * short_packet pktcnt = N + (short_packet
26984 + * exist ? 1 : 0)
26985 + */
26986 + deptsiz.b.xfersize = ep->xfer_len;
26987 + deptsiz.b.pktcnt =
26988 + (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
26989 + deptsiz.b.mc = deptsiz.b.pktcnt;
26990 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz,
26991 + deptsiz.d32);
26992 +
26993 + /* Write the DMA register */
26994 + if (core_if->dma_enable) {
26995 + DWC_WRITE_REG32(&
26996 + (core_if->dev_if->in_ep_regs[ep->num]->
26997 + diepdma), (uint32_t) ep->dma_addr);
26998 + }
26999 + } else {
27000 + deptsiz.b.pktcnt =
27001 + (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket;
27002 + deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
27003 +
27004 + DWC_WRITE_REG32(&core_if->dev_if->
27005 + out_ep_regs[ep->num]->doeptsiz, deptsiz.d32);
27006 +
27007 + if (core_if->dma_enable) {
27008 + DWC_WRITE_REG32(&
27009 + (core_if->dev_if->
27010 + out_ep_regs[ep->num]->doepdma),
27011 + (uint32_t) ep->dma_addr);
27012 + }
27013 + }
27014 +
27015 + /** Enable endpoint, clear nak */
27016 +
27017 + depctl.d32 = 0;
27018 + if (ep->bInterval == 1) {
27019 + dsts.d32 =
27020 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
27021 + ep->next_frame = dsts.b.soffn + ep->bInterval;
27022 +
27023 + if (ep->next_frame & 0x1) {
27024 + depctl.b.setd1pid = 1;
27025 + } else {
27026 + depctl.b.setd0pid = 1;
27027 + }
27028 + } else {
27029 + ep->next_frame += ep->bInterval;
27030 +
27031 + if (ep->next_frame & 0x1) {
27032 + depctl.b.setd1pid = 1;
27033 + } else {
27034 + depctl.b.setd0pid = 1;
27035 + }
27036 + }
27037 + depctl.b.epena = 1;
27038 + depctl.b.cnak = 1;
27039 +
27040 + DWC_MODIFY_REG32(addr, 0, depctl.d32);
27041 + depctl.d32 = DWC_READ_REG32(addr);
27042 +
27043 + if (ep->is_in && core_if->dma_enable == 0) {
27044 + write_isoc_frame_data(core_if, ep);
27045 + }
27046 +
27047 +}
27048 +#endif /* DWC_EN_ISOC */
27049 +
27050 +static void dwc_otg_set_uninitialized(int32_t * p, int size)
27051 +{
27052 + int i;
27053 + for (i = 0; i < size; i++) {
27054 + p[i] = -1;
27055 + }
27056 +}
27057 +
27058 +static int dwc_otg_param_initialized(int32_t val)
27059 +{
27060 + return val != -1;
27061 +}
27062 +
27063 +static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if)
27064 +{
27065 + int i;
27066 + core_if->core_params = DWC_ALLOC(sizeof(*core_if->core_params));
27067 + if (!core_if->core_params) {
27068 + return -DWC_E_NO_MEMORY;
27069 + }
27070 + dwc_otg_set_uninitialized((int32_t *) core_if->core_params,
27071 + sizeof(*core_if->core_params) /
27072 + sizeof(int32_t));
27073 + DWC_PRINTF("Setting default values for core params\n");
27074 + dwc_otg_set_param_otg_cap(core_if, dwc_param_otg_cap_default);
27075 + dwc_otg_set_param_dma_enable(core_if, dwc_param_dma_enable_default);
27076 + dwc_otg_set_param_dma_desc_enable(core_if,
27077 + dwc_param_dma_desc_enable_default);
27078 + dwc_otg_set_param_opt(core_if, dwc_param_opt_default);
27079 + dwc_otg_set_param_dma_burst_size(core_if,
27080 + dwc_param_dma_burst_size_default);
27081 + dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
27082 + dwc_param_host_support_fs_ls_low_power_default);
27083 + dwc_otg_set_param_enable_dynamic_fifo(core_if,
27084 + dwc_param_enable_dynamic_fifo_default);
27085 + dwc_otg_set_param_data_fifo_size(core_if,
27086 + dwc_param_data_fifo_size_default);
27087 + dwc_otg_set_param_dev_rx_fifo_size(core_if,
27088 + dwc_param_dev_rx_fifo_size_default);
27089 + dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
27090 + dwc_param_dev_nperio_tx_fifo_size_default);
27091 + dwc_otg_set_param_host_rx_fifo_size(core_if,
27092 + dwc_param_host_rx_fifo_size_default);
27093 + dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
27094 + dwc_param_host_nperio_tx_fifo_size_default);
27095 + dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
27096 + dwc_param_host_perio_tx_fifo_size_default);
27097 + dwc_otg_set_param_max_transfer_size(core_if,
27098 + dwc_param_max_transfer_size_default);
27099 + dwc_otg_set_param_max_packet_count(core_if,
27100 + dwc_param_max_packet_count_default);
27101 + dwc_otg_set_param_host_channels(core_if,
27102 + dwc_param_host_channels_default);
27103 + dwc_otg_set_param_dev_endpoints(core_if,
27104 + dwc_param_dev_endpoints_default);
27105 + dwc_otg_set_param_phy_type(core_if, dwc_param_phy_type_default);
27106 + dwc_otg_set_param_speed(core_if, dwc_param_speed_default);
27107 + dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
27108 + dwc_param_host_ls_low_power_phy_clk_default);
27109 + dwc_otg_set_param_phy_ulpi_ddr(core_if, dwc_param_phy_ulpi_ddr_default);
27110 + dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
27111 + dwc_param_phy_ulpi_ext_vbus_default);
27112 + dwc_otg_set_param_phy_utmi_width(core_if,
27113 + dwc_param_phy_utmi_width_default);
27114 + dwc_otg_set_param_ts_dline(core_if, dwc_param_ts_dline_default);
27115 + dwc_otg_set_param_i2c_enable(core_if, dwc_param_i2c_enable_default);
27116 + dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_param_ulpi_fs_ls_default);
27117 + dwc_otg_set_param_en_multiple_tx_fifo(core_if,
27118 + dwc_param_en_multiple_tx_fifo_default);
27119 + for (i = 0; i < 15; i++) {
27120 + dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
27121 + dwc_param_dev_perio_tx_fifo_size_default,
27122 + i);
27123 + }
27124 +
27125 + for (i = 0; i < 15; i++) {
27126 + dwc_otg_set_param_dev_tx_fifo_size(core_if,
27127 + dwc_param_dev_tx_fifo_size_default,
27128 + i);
27129 + }
27130 + dwc_otg_set_param_thr_ctl(core_if, dwc_param_thr_ctl_default);
27131 + dwc_otg_set_param_mpi_enable(core_if, dwc_param_mpi_enable_default);
27132 + dwc_otg_set_param_pti_enable(core_if, dwc_param_pti_enable_default);
27133 + dwc_otg_set_param_lpm_enable(core_if, dwc_param_lpm_enable_default);
27134 + dwc_otg_set_param_ic_usb_cap(core_if, dwc_param_ic_usb_cap_default);
27135 + dwc_otg_set_param_tx_thr_length(core_if,
27136 + dwc_param_tx_thr_length_default);
27137 + dwc_otg_set_param_rx_thr_length(core_if,
27138 + dwc_param_rx_thr_length_default);
27139 + dwc_otg_set_param_ahb_thr_ratio(core_if,
27140 + dwc_param_ahb_thr_ratio_default);
27141 + dwc_otg_set_param_power_down(core_if, dwc_param_power_down_default);
27142 + dwc_otg_set_param_reload_ctl(core_if, dwc_param_reload_ctl_default);
27143 + dwc_otg_set_param_dev_out_nak(core_if, dwc_param_dev_out_nak_default);
27144 + dwc_otg_set_param_cont_on_bna(core_if, dwc_param_cont_on_bna_default);
27145 + dwc_otg_set_param_ahb_single(core_if, dwc_param_ahb_single_default);
27146 + dwc_otg_set_param_otg_ver(core_if, dwc_param_otg_ver_default);
27147 + dwc_otg_set_param_adp_enable(core_if, dwc_param_adp_enable_default);
27148 + DWC_PRINTF("Finished setting default values for core params\n");
27149 +
27150 + return 0;
27151 +}
27152 +
27153 +uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if)
27154 +{
27155 + return core_if->dma_enable;
27156 +}
27157 +
27158 +/* Checks if the parameter is outside of its valid range of values */
27159 +#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
27160 + (((_param_) < (_low_)) || \
27161 + ((_param_) > (_high_)))
27162 +
27163 +/* Parameter access functions */
27164 +int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val)
27165 +{
27166 + int valid;
27167 + int retval = 0;
27168 + if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
27169 + DWC_WARN("Wrong value for otg_cap parameter\n");
27170 + DWC_WARN("otg_cap parameter must be 0,1 or 2\n");
27171 + retval = -DWC_E_INVALID;
27172 + goto out;
27173 + }
27174 +
27175 + valid = 1;
27176 + switch (val) {
27177 + case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
27178 + if (core_if->hwcfg2.b.op_mode !=
27179 + DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
27180 + valid = 0;
27181 + break;
27182 + case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
27183 + if ((core_if->hwcfg2.b.op_mode !=
27184 + DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
27185 + && (core_if->hwcfg2.b.op_mode !=
27186 + DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
27187 + && (core_if->hwcfg2.b.op_mode !=
27188 + DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
27189 + && (core_if->hwcfg2.b.op_mode !=
27190 + DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
27191 + valid = 0;
27192 + }
27193 + break;
27194 + case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
27195 + /* always valid */
27196 + break;
27197 + }
27198 + if (!valid) {
27199 + if (dwc_otg_param_initialized(core_if->core_params->otg_cap)) {
27200 + DWC_ERROR
27201 + ("%d invalid for otg_cap paremter. Check HW configuration.\n",
27202 + val);
27203 + }
27204 + val =
27205 + (((core_if->hwcfg2.b.op_mode ==
27206 + DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
27207 + || (core_if->hwcfg2.b.op_mode ==
27208 + DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
27209 + || (core_if->hwcfg2.b.op_mode ==
27210 + DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
27211 + || (core_if->hwcfg2.b.op_mode ==
27212 + DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
27213 + DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
27214 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
27215 + retval = -DWC_E_INVALID;
27216 + }
27217 +
27218 + core_if->core_params->otg_cap = val;
27219 +out:
27220 + return retval;
27221 +}
27222 +
27223 +int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if)
27224 +{
27225 + return core_if->core_params->otg_cap;
27226 +}
27227 +
27228 +int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val)
27229 +{
27230 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27231 + DWC_WARN("Wrong value for opt parameter\n");
27232 + return -DWC_E_INVALID;
27233 + }
27234 + core_if->core_params->opt = val;
27235 + return 0;
27236 +}
27237 +
27238 +int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if)
27239 +{
27240 + return core_if->core_params->opt;
27241 +}
27242 +
27243 +int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if, int32_t val)
27244 +{
27245 + int retval = 0;
27246 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27247 + DWC_WARN("Wrong value for dma enable\n");
27248 + return -DWC_E_INVALID;
27249 + }
27250 +
27251 + if ((val == 1) && (core_if->hwcfg2.b.architecture == 0)) {
27252 + if (dwc_otg_param_initialized(core_if->core_params->dma_enable)) {
27253 + DWC_ERROR
27254 + ("%d invalid for dma_enable paremter. Check HW configuration.\n",
27255 + val);
27256 + }
27257 + val = 0;
27258 + retval = -DWC_E_INVALID;
27259 + }
27260 +
27261 + core_if->core_params->dma_enable = val;
27262 + if (val == 0) {
27263 + dwc_otg_set_param_dma_desc_enable(core_if, 0);
27264 + }
27265 + return retval;
27266 +}
27267 +
27268 +int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if)
27269 +{
27270 + return core_if->core_params->dma_enable;
27271 +}
27272 +
27273 +int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if, int32_t val)
27274 +{
27275 + int retval = 0;
27276 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27277 + DWC_WARN("Wrong value for dma_enable\n");
27278 + DWC_WARN("dma_desc_enable must be 0 or 1\n");
27279 + return -DWC_E_INVALID;
27280 + }
27281 +
27282 + if ((val == 1)
27283 + && ((dwc_otg_get_param_dma_enable(core_if) == 0)
27284 + || (core_if->hwcfg4.b.desc_dma == 0))) {
27285 + if (dwc_otg_param_initialized
27286 + (core_if->core_params->dma_desc_enable)) {
27287 + DWC_ERROR
27288 + ("%d invalid for dma_desc_enable paremter. Check HW configuration.\n",
27289 + val);
27290 + }
27291 + val = 0;
27292 + retval = -DWC_E_INVALID;
27293 + }
27294 + core_if->core_params->dma_desc_enable = val;
27295 + return retval;
27296 +}
27297 +
27298 +int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if)
27299 +{
27300 + return core_if->core_params->dma_desc_enable;
27301 +}
27302 +
27303 +int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * core_if,
27304 + int32_t val)
27305 +{
27306 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27307 + DWC_WARN("Wrong value for host_support_fs_low_power\n");
27308 + DWC_WARN("host_support_fs_low_power must be 0 or 1\n");
27309 + return -DWC_E_INVALID;
27310 + }
27311 + core_if->core_params->host_support_fs_ls_low_power = val;
27312 + return 0;
27313 +}
27314 +
27315 +int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
27316 + core_if)
27317 +{
27318 + return core_if->core_params->host_support_fs_ls_low_power;
27319 +}
27320 +
27321 +int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
27322 + int32_t val)
27323 +{
27324 + int retval = 0;
27325 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27326 + DWC_WARN("Wrong value for enable_dynamic_fifo\n");
27327 + DWC_WARN("enable_dynamic_fifo must be 0 or 1\n");
27328 + return -DWC_E_INVALID;
27329 + }
27330 +
27331 + if ((val == 1) && (core_if->hwcfg2.b.dynamic_fifo == 0)) {
27332 + if (dwc_otg_param_initialized
27333 + (core_if->core_params->enable_dynamic_fifo)) {
27334 + DWC_ERROR
27335 + ("%d invalid for enable_dynamic_fifo paremter. Check HW configuration.\n",
27336 + val);
27337 + }
27338 + val = 0;
27339 + retval = -DWC_E_INVALID;
27340 + }
27341 + core_if->core_params->enable_dynamic_fifo = val;
27342 + return retval;
27343 +}
27344 +
27345 +int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if)
27346 +{
27347 + return core_if->core_params->enable_dynamic_fifo;
27348 +}
27349 +
27350 +int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
27351 +{
27352 + int retval = 0;
27353 + if (DWC_OTG_PARAM_TEST(val, 32, 32768)) {
27354 + DWC_WARN("Wrong value for data_fifo_size\n");
27355 + DWC_WARN("data_fifo_size must be 32-32768\n");
27356 + return -DWC_E_INVALID;
27357 + }
27358 +
27359 + if (val > core_if->hwcfg3.b.dfifo_depth) {
27360 + if (dwc_otg_param_initialized
27361 + (core_if->core_params->data_fifo_size)) {
27362 + DWC_ERROR
27363 + ("%d invalid for data_fifo_size parameter. Check HW configuration.\n",
27364 + val);
27365 + }
27366 + val = core_if->hwcfg3.b.dfifo_depth;
27367 + retval = -DWC_E_INVALID;
27368 + }
27369 +
27370 + core_if->core_params->data_fifo_size = val;
27371 + return retval;
27372 +}
27373 +
27374 +int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if)
27375 +{
27376 + return core_if->core_params->data_fifo_size;
27377 +}
27378 +
27379 +int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
27380 +{
27381 + int retval = 0;
27382 + if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
27383 + DWC_WARN("Wrong value for dev_rx_fifo_size\n");
27384 + DWC_WARN("dev_rx_fifo_size must be 16-32768\n");
27385 + return -DWC_E_INVALID;
27386 + }
27387 +
27388 + if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
27389 + if (dwc_otg_param_initialized(core_if->core_params->dev_rx_fifo_size)) {
27390 + DWC_WARN("%d invalid for dev_rx_fifo_size parameter\n", val);
27391 + }
27392 + val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
27393 + retval = -DWC_E_INVALID;
27394 + }
27395 +
27396 + core_if->core_params->dev_rx_fifo_size = val;
27397 + return retval;
27398 +}
27399 +
27400 +int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if)
27401 +{
27402 + return core_if->core_params->dev_rx_fifo_size;
27403 +}
27404 +
27405 +int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
27406 + int32_t val)
27407 +{
27408 + int retval = 0;
27409 +
27410 + if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
27411 + DWC_WARN("Wrong value for dev_nperio_tx_fifo\n");
27412 + DWC_WARN("dev_nperio_tx_fifo must be 16-32768\n");
27413 + return -DWC_E_INVALID;
27414 + }
27415 +
27416 + if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
27417 + if (dwc_otg_param_initialized
27418 + (core_if->core_params->dev_nperio_tx_fifo_size)) {
27419 + DWC_ERROR
27420 + ("%d invalid for dev_nperio_tx_fifo_size. Check HW configuration.\n",
27421 + val);
27422 + }
27423 + val =
27424 + (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
27425 + 16);
27426 + retval = -DWC_E_INVALID;
27427 + }
27428 +
27429 + core_if->core_params->dev_nperio_tx_fifo_size = val;
27430 + return retval;
27431 +}
27432 +
27433 +int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
27434 +{
27435 + return core_if->core_params->dev_nperio_tx_fifo_size;
27436 +}
27437 +
27438 +int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
27439 + int32_t val)
27440 +{
27441 + int retval = 0;
27442 +
27443 + if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
27444 + DWC_WARN("Wrong value for host_rx_fifo_size\n");
27445 + DWC_WARN("host_rx_fifo_size must be 16-32768\n");
27446 + return -DWC_E_INVALID;
27447 + }
27448 +
27449 + if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
27450 + if (dwc_otg_param_initialized
27451 + (core_if->core_params->host_rx_fifo_size)) {
27452 + DWC_ERROR
27453 + ("%d invalid for host_rx_fifo_size. Check HW configuration.\n",
27454 + val);
27455 + }
27456 + val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
27457 + retval = -DWC_E_INVALID;
27458 + }
27459 +
27460 + core_if->core_params->host_rx_fifo_size = val;
27461 + return retval;
27462 +
27463 +}
27464 +
27465 +int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if)
27466 +{
27467 + return core_if->core_params->host_rx_fifo_size;
27468 +}
27469 +
27470 +int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
27471 + int32_t val)
27472 +{
27473 + int retval = 0;
27474 +
27475 + if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
27476 + DWC_WARN("Wrong value for host_nperio_tx_fifo_size\n");
27477 + DWC_WARN("host_nperio_tx_fifo_size must be 16-32768\n");
27478 + return -DWC_E_INVALID;
27479 + }
27480 +
27481 + if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
27482 + if (dwc_otg_param_initialized
27483 + (core_if->core_params->host_nperio_tx_fifo_size)) {
27484 + DWC_ERROR
27485 + ("%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
27486 + val);
27487 + }
27488 + val =
27489 + (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
27490 + 16);
27491 + retval = -DWC_E_INVALID;
27492 + }
27493 +
27494 + core_if->core_params->host_nperio_tx_fifo_size = val;
27495 + return retval;
27496 +}
27497 +
27498 +int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
27499 +{
27500 + return core_if->core_params->host_nperio_tx_fifo_size;
27501 +}
27502 +
27503 +int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
27504 + int32_t val)
27505 +{
27506 + int retval = 0;
27507 + if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
27508 + DWC_WARN("Wrong value for host_perio_tx_fifo_size\n");
27509 + DWC_WARN("host_perio_tx_fifo_size must be 16-32768\n");
27510 + return -DWC_E_INVALID;
27511 + }
27512 +
27513 + if (val > ((core_if->hptxfsiz.d32) >> 16)) {
27514 + if (dwc_otg_param_initialized
27515 + (core_if->core_params->host_perio_tx_fifo_size)) {
27516 + DWC_ERROR
27517 + ("%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
27518 + val);
27519 + }
27520 + val = (core_if->hptxfsiz.d32) >> 16;
27521 + retval = -DWC_E_INVALID;
27522 + }
27523 +
27524 + core_if->core_params->host_perio_tx_fifo_size = val;
27525 + return retval;
27526 +}
27527 +
27528 +int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if)
27529 +{
27530 + return core_if->core_params->host_perio_tx_fifo_size;
27531 +}
27532 +
27533 +int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
27534 + int32_t val)
27535 +{
27536 + int retval = 0;
27537 +
27538 + if (DWC_OTG_PARAM_TEST(val, 2047, 524288)) {
27539 + DWC_WARN("Wrong value for max_transfer_size\n");
27540 + DWC_WARN("max_transfer_size must be 2047-524288\n");
27541 + return -DWC_E_INVALID;
27542 + }
27543 +
27544 + if (val >= (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))) {
27545 + if (dwc_otg_param_initialized
27546 + (core_if->core_params->max_transfer_size)) {
27547 + DWC_ERROR
27548 + ("%d invalid for max_transfer_size. Check HW configuration.\n",
27549 + val);
27550 + }
27551 + val =
27552 + ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 11)) -
27553 + 1);
27554 + retval = -DWC_E_INVALID;
27555 + }
27556 +
27557 + core_if->core_params->max_transfer_size = val;
27558 + return retval;
27559 +}
27560 +
27561 +int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if)
27562 +{
27563 + return core_if->core_params->max_transfer_size;
27564 +}
27565 +
27566 +int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if, int32_t val)
27567 +{
27568 + int retval = 0;
27569 +
27570 + if (DWC_OTG_PARAM_TEST(val, 15, 511)) {
27571 + DWC_WARN("Wrong value for max_packet_count\n");
27572 + DWC_WARN("max_packet_count must be 15-511\n");
27573 + return -DWC_E_INVALID;
27574 + }
27575 +
27576 + if (val > (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))) {
27577 + if (dwc_otg_param_initialized
27578 + (core_if->core_params->max_packet_count)) {
27579 + DWC_ERROR
27580 + ("%d invalid for max_packet_count. Check HW configuration.\n",
27581 + val);
27582 + }
27583 + val =
27584 + ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1);
27585 + retval = -DWC_E_INVALID;
27586 + }
27587 +
27588 + core_if->core_params->max_packet_count = val;
27589 + return retval;
27590 +}
27591 +
27592 +int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if)
27593 +{
27594 + return core_if->core_params->max_packet_count;
27595 +}
27596 +
27597 +int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, int32_t val)
27598 +{
27599 + int retval = 0;
27600 +
27601 + if (DWC_OTG_PARAM_TEST(val, 1, 16)) {
27602 + DWC_WARN("Wrong value for host_channels\n");
27603 + DWC_WARN("host_channels must be 1-16\n");
27604 + return -DWC_E_INVALID;
27605 + }
27606 +
27607 + if (val > (core_if->hwcfg2.b.num_host_chan + 1)) {
27608 + if (dwc_otg_param_initialized
27609 + (core_if->core_params->host_channels)) {
27610 + DWC_ERROR
27611 + ("%d invalid for host_channels. Check HW configurations.\n",
27612 + val);
27613 + }
27614 + val = (core_if->hwcfg2.b.num_host_chan + 1);
27615 + retval = -DWC_E_INVALID;
27616 + }
27617 +
27618 + core_if->core_params->host_channels = val;
27619 + return retval;
27620 +}
27621 +
27622 +int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if)
27623 +{
27624 + return core_if->core_params->host_channels;
27625 +}
27626 +
27627 +int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if, int32_t val)
27628 +{
27629 + int retval = 0;
27630 +
27631 + if (DWC_OTG_PARAM_TEST(val, 1, 15)) {
27632 + DWC_WARN("Wrong value for dev_endpoints\n");
27633 + DWC_WARN("dev_endpoints must be 1-15\n");
27634 + return -DWC_E_INVALID;
27635 + }
27636 +
27637 + if (val > (core_if->hwcfg2.b.num_dev_ep)) {
27638 + if (dwc_otg_param_initialized
27639 + (core_if->core_params->dev_endpoints)) {
27640 + DWC_ERROR
27641 + ("%d invalid for dev_endpoints. Check HW configurations.\n",
27642 + val);
27643 + }
27644 + val = core_if->hwcfg2.b.num_dev_ep;
27645 + retval = -DWC_E_INVALID;
27646 + }
27647 +
27648 + core_if->core_params->dev_endpoints = val;
27649 + return retval;
27650 +}
27651 +
27652 +int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if)
27653 +{
27654 + return core_if->core_params->dev_endpoints;
27655 +}
27656 +
27657 +int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val)
27658 +{
27659 + int retval = 0;
27660 + int valid = 0;
27661 +
27662 + if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
27663 + DWC_WARN("Wrong value for phy_type\n");
27664 + DWC_WARN("phy_type must be 0,1 or 2\n");
27665 + return -DWC_E_INVALID;
27666 + }
27667 +#ifndef NO_FS_PHY_HW_CHECKS
27668 + if ((val == DWC_PHY_TYPE_PARAM_UTMI) &&
27669 + ((core_if->hwcfg2.b.hs_phy_type == 1) ||
27670 + (core_if->hwcfg2.b.hs_phy_type == 3))) {
27671 + valid = 1;
27672 + } else if ((val == DWC_PHY_TYPE_PARAM_ULPI) &&
27673 + ((core_if->hwcfg2.b.hs_phy_type == 2) ||
27674 + (core_if->hwcfg2.b.hs_phy_type == 3))) {
27675 + valid = 1;
27676 + } else if ((val == DWC_PHY_TYPE_PARAM_FS) &&
27677 + (core_if->hwcfg2.b.fs_phy_type == 1)) {
27678 + valid = 1;
27679 + }
27680 + if (!valid) {
27681 + if (dwc_otg_param_initialized(core_if->core_params->phy_type)) {
27682 + DWC_ERROR
27683 + ("%d invalid for phy_type. Check HW configurations.\n",
27684 + val);
27685 + }
27686 + if (core_if->hwcfg2.b.hs_phy_type) {
27687 + if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
27688 + (core_if->hwcfg2.b.hs_phy_type == 1)) {
27689 + val = DWC_PHY_TYPE_PARAM_UTMI;
27690 + } else {
27691 + val = DWC_PHY_TYPE_PARAM_ULPI;
27692 + }
27693 + }
27694 + retval = -DWC_E_INVALID;
27695 + }
27696 +#endif
27697 + core_if->core_params->phy_type = val;
27698 + return retval;
27699 +}
27700 +
27701 +int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if)
27702 +{
27703 + return core_if->core_params->phy_type;
27704 +}
27705 +
27706 +int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val)
27707 +{
27708 + int retval = 0;
27709 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27710 + DWC_WARN("Wrong value for speed parameter\n");
27711 + DWC_WARN("max_speed parameter must be 0 or 1\n");
27712 + return -DWC_E_INVALID;
27713 + }
27714 + if ((val == 0)
27715 + && dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS) {
27716 + if (dwc_otg_param_initialized(core_if->core_params->speed)) {
27717 + DWC_ERROR
27718 + ("%d invalid for speed paremter. Check HW configuration.\n",
27719 + val);
27720 + }
27721 + val =
27722 + (dwc_otg_get_param_phy_type(core_if) ==
27723 + DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
27724 + retval = -DWC_E_INVALID;
27725 + }
27726 + core_if->core_params->speed = val;
27727 + return retval;
27728 +}
27729 +
27730 +int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if)
27731 +{
27732 + return core_if->core_params->speed;
27733 +}
27734 +
27735 +int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if,
27736 + int32_t val)
27737 +{
27738 + int retval = 0;
27739 +
27740 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27741 + DWC_WARN
27742 + ("Wrong value for host_ls_low_power_phy_clk parameter\n");
27743 + DWC_WARN("host_ls_low_power_phy_clk must be 0 or 1\n");
27744 + return -DWC_E_INVALID;
27745 + }
27746 +
27747 + if ((val == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ)
27748 + && (dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS)) {
27749 + if (dwc_otg_param_initialized
27750 + (core_if->core_params->host_ls_low_power_phy_clk)) {
27751 + DWC_ERROR
27752 + ("%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
27753 + val);
27754 + }
27755 + val =
27756 + (dwc_otg_get_param_phy_type(core_if) ==
27757 + DWC_PHY_TYPE_PARAM_FS) ?
27758 + DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ :
27759 + DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
27760 + retval = -DWC_E_INVALID;
27761 + }
27762 +
27763 + core_if->core_params->host_ls_low_power_phy_clk = val;
27764 + return retval;
27765 +}
27766 +
27767 +int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if)
27768 +{
27769 + return core_if->core_params->host_ls_low_power_phy_clk;
27770 +}
27771 +
27772 +int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if, int32_t val)
27773 +{
27774 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27775 + DWC_WARN("Wrong value for phy_ulpi_ddr\n");
27776 + DWC_WARN("phy_upli_ddr must be 0 or 1\n");
27777 + return -DWC_E_INVALID;
27778 + }
27779 +
27780 + core_if->core_params->phy_ulpi_ddr = val;
27781 + return 0;
27782 +}
27783 +
27784 +int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if)
27785 +{
27786 + return core_if->core_params->phy_ulpi_ddr;
27787 +}
27788 +
27789 +int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
27790 + int32_t val)
27791 +{
27792 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27793 + DWC_WARN("Wrong valaue for phy_ulpi_ext_vbus\n");
27794 + DWC_WARN("phy_ulpi_ext_vbus must be 0 or 1\n");
27795 + return -DWC_E_INVALID;
27796 + }
27797 +
27798 + core_if->core_params->phy_ulpi_ext_vbus = val;
27799 + return 0;
27800 +}
27801 +
27802 +int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if)
27803 +{
27804 + return core_if->core_params->phy_ulpi_ext_vbus;
27805 +}
27806 +
27807 +int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if, int32_t val)
27808 +{
27809 + if (DWC_OTG_PARAM_TEST(val, 8, 8) && DWC_OTG_PARAM_TEST(val, 16, 16)) {
27810 + DWC_WARN("Wrong valaue for phy_utmi_width\n");
27811 + DWC_WARN("phy_utmi_width must be 8 or 16\n");
27812 + return -DWC_E_INVALID;
27813 + }
27814 +
27815 + core_if->core_params->phy_utmi_width = val;
27816 + return 0;
27817 +}
27818 +
27819 +int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if)
27820 +{
27821 + return core_if->core_params->phy_utmi_width;
27822 +}
27823 +
27824 +int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if, int32_t val)
27825 +{
27826 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27827 + DWC_WARN("Wrong valaue for ulpi_fs_ls\n");
27828 + DWC_WARN("ulpi_fs_ls must be 0 or 1\n");
27829 + return -DWC_E_INVALID;
27830 + }
27831 +
27832 + core_if->core_params->ulpi_fs_ls = val;
27833 + return 0;
27834 +}
27835 +
27836 +int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if)
27837 +{
27838 + return core_if->core_params->ulpi_fs_ls;
27839 +}
27840 +
27841 +int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val)
27842 +{
27843 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27844 + DWC_WARN("Wrong valaue for ts_dline\n");
27845 + DWC_WARN("ts_dline must be 0 or 1\n");
27846 + return -DWC_E_INVALID;
27847 + }
27848 +
27849 + core_if->core_params->ts_dline = val;
27850 + return 0;
27851 +}
27852 +
27853 +int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if)
27854 +{
27855 + return core_if->core_params->ts_dline;
27856 +}
27857 +
27858 +int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if, int32_t val)
27859 +{
27860 + int retval = 0;
27861 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27862 + DWC_WARN("Wrong valaue for i2c_enable\n");
27863 + DWC_WARN("i2c_enable must be 0 or 1\n");
27864 + return -DWC_E_INVALID;
27865 + }
27866 +#ifndef NO_FS_PHY_HW_CHECK
27867 + if (val == 1 && core_if->hwcfg3.b.i2c == 0) {
27868 + if (dwc_otg_param_initialized(core_if->core_params->i2c_enable)) {
27869 + DWC_ERROR
27870 + ("%d invalid for i2c_enable. Check HW configuration.\n",
27871 + val);
27872 + }
27873 + val = 0;
27874 + retval = -DWC_E_INVALID;
27875 + }
27876 +#endif
27877 +
27878 + core_if->core_params->i2c_enable = val;
27879 + return retval;
27880 +}
27881 +
27882 +int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if)
27883 +{
27884 + return core_if->core_params->i2c_enable;
27885 +}
27886 +
27887 +int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
27888 + int32_t val, int fifo_num)
27889 +{
27890 + int retval = 0;
27891 +
27892 + if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
27893 + DWC_WARN("Wrong value for dev_perio_tx_fifo_size\n");
27894 + DWC_WARN("dev_perio_tx_fifo_size must be 4-768\n");
27895 + return -DWC_E_INVALID;
27896 + }
27897 +
27898 + if (val >
27899 + (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) {
27900 + if (dwc_otg_param_initialized
27901 + (core_if->core_params->dev_perio_tx_fifo_size[fifo_num])) {
27902 + DWC_ERROR
27903 + ("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n",
27904 + val, fifo_num);
27905 + }
27906 + val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]));
27907 + retval = -DWC_E_INVALID;
27908 + }
27909 +
27910 + core_if->core_params->dev_perio_tx_fifo_size[fifo_num] = val;
27911 + return retval;
27912 +}
27913 +
27914 +int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
27915 + int fifo_num)
27916 +{
27917 + return core_if->core_params->dev_perio_tx_fifo_size[fifo_num];
27918 +}
27919 +
27920 +int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
27921 + int32_t val)
27922 +{
27923 + int retval = 0;
27924 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27925 + DWC_WARN("Wrong valaue for en_multiple_tx_fifo,\n");
27926 + DWC_WARN("en_multiple_tx_fifo must be 0 or 1\n");
27927 + return -DWC_E_INVALID;
27928 + }
27929 +
27930 + if (val == 1 && core_if->hwcfg4.b.ded_fifo_en == 0) {
27931 + if (dwc_otg_param_initialized
27932 + (core_if->core_params->en_multiple_tx_fifo)) {
27933 + DWC_ERROR
27934 + ("%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
27935 + val);
27936 + }
27937 + val = 0;
27938 + retval = -DWC_E_INVALID;
27939 + }
27940 +
27941 + core_if->core_params->en_multiple_tx_fifo = val;
27942 + return retval;
27943 +}
27944 +
27945 +int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if)
27946 +{
27947 + return core_if->core_params->en_multiple_tx_fifo;
27948 +}
27949 +
27950 +int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val,
27951 + int fifo_num)
27952 +{
27953 + int retval = 0;
27954 +
27955 + if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
27956 + DWC_WARN("Wrong value for dev_tx_fifo_size\n");
27957 + DWC_WARN("dev_tx_fifo_size must be 4-768\n");
27958 + return -DWC_E_INVALID;
27959 + }
27960 +
27961 + if (val >
27962 + (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) {
27963 + if (dwc_otg_param_initialized
27964 + (core_if->core_params->dev_tx_fifo_size[fifo_num])) {
27965 + DWC_ERROR
27966 + ("`%d' invalid for parameter `dev_tx_fifo_size_%d'. Check HW configuration.\n",
27967 + val, fifo_num);
27968 + }
27969 + val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]));
27970 + retval = -DWC_E_INVALID;
27971 + }
27972 +
27973 + core_if->core_params->dev_tx_fifo_size[fifo_num] = val;
27974 + return retval;
27975 +}
27976 +
27977 +int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
27978 + int fifo_num)
27979 +{
27980 + return core_if->core_params->dev_tx_fifo_size[fifo_num];
27981 +}
27982 +
27983 +int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val)
27984 +{
27985 + int retval = 0;
27986 +
27987 + if (DWC_OTG_PARAM_TEST(val, 0, 7)) {
27988 + DWC_WARN("Wrong value for thr_ctl\n");
27989 + DWC_WARN("thr_ctl must be 0-7\n");
27990 + return -DWC_E_INVALID;
27991 + }
27992 +
27993 + if ((val != 0) &&
27994 + (!dwc_otg_get_param_dma_enable(core_if) ||
27995 + !core_if->hwcfg4.b.ded_fifo_en)) {
27996 + if (dwc_otg_param_initialized(core_if->core_params->thr_ctl)) {
27997 + DWC_ERROR
27998 + ("%d invalid for parameter thr_ctl. Check HW configuration.\n",
27999 + val);
28000 + }
28001 + val = 0;
28002 + retval = -DWC_E_INVALID;
28003 + }
28004 +
28005 + core_if->core_params->thr_ctl = val;
28006 + return retval;
28007 +}
28008 +
28009 +int32_t dwc_otg_get_param_thr_ctl(dwc_otg_core_if_t * core_if)
28010 +{
28011 + return core_if->core_params->thr_ctl;
28012 +}
28013 +
28014 +int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if, int32_t val)
28015 +{
28016 + int retval = 0;
28017 +
28018 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
28019 + DWC_WARN("Wrong value for lpm_enable\n");
28020 + DWC_WARN("lpm_enable must be 0 or 1\n");
28021 + return -DWC_E_INVALID;
28022 + }
28023 +
28024 + if (val && !core_if->hwcfg3.b.otg_lpm_en) {
28025 + if (dwc_otg_param_initialized(core_if->core_params->lpm_enable)) {
28026 + DWC_ERROR
28027 + ("%d invalid for parameter lpm_enable. Check HW configuration.\n",
28028 + val);
28029 + }
28030 + val = 0;
28031 + retval = -DWC_E_INVALID;
28032 + }
28033 +
28034 + core_if->core_params->lpm_enable = val;
28035 + return retval;
28036 +}
28037 +
28038 +int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if)
28039 +{
28040 + return core_if->core_params->lpm_enable;
28041 +}
28042 +
28043 +int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
28044 +{
28045 + if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
28046 + DWC_WARN("Wrong valaue for tx_thr_length\n");
28047 + DWC_WARN("tx_thr_length must be 8 - 128\n");
28048 + return -DWC_E_INVALID;
28049 + }
28050 +
28051 + core_if->core_params->tx_thr_length = val;
28052 + return 0;
28053 +}
28054 +
28055 +int32_t dwc_otg_get_param_tx_thr_length(dwc_otg_core_if_t * core_if)
28056 +{
28057 + return core_if->core_params->tx_thr_length;
28058 +}
28059 +
28060 +int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
28061 +{
28062 + if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
28063 + DWC_WARN("Wrong valaue for rx_thr_length\n");
28064 + DWC_WARN("rx_thr_length must be 8 - 128\n");
28065 + return -DWC_E_INVALID;
28066 + }
28067 +
28068 + core_if->core_params->rx_thr_length = val;
28069 + return 0;
28070 +}
28071 +
28072 +int32_t dwc_otg_get_param_rx_thr_length(dwc_otg_core_if_t * core_if)
28073 +{
28074 + return core_if->core_params->rx_thr_length;
28075 +}
28076 +
28077 +int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if, int32_t val)
28078 +{
28079 + if (DWC_OTG_PARAM_TEST(val, 1, 1) &&
28080 + DWC_OTG_PARAM_TEST(val, 4, 4) &&
28081 + DWC_OTG_PARAM_TEST(val, 8, 8) &&
28082 + DWC_OTG_PARAM_TEST(val, 16, 16) &&
28083 + DWC_OTG_PARAM_TEST(val, 32, 32) &&
28084 + DWC_OTG_PARAM_TEST(val, 64, 64) &&
28085 + DWC_OTG_PARAM_TEST(val, 128, 128) &&
28086 + DWC_OTG_PARAM_TEST(val, 256, 256)) {
28087 + DWC_WARN("`%d' invalid for parameter `dma_burst_size'\n", val);
28088 + return -DWC_E_INVALID;
28089 + }
28090 + core_if->core_params->dma_burst_size = val;
28091 + return 0;
28092 +}
28093 +
28094 +int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if)
28095 +{
28096 + return core_if->core_params->dma_burst_size;
28097 +}
28098 +
28099 +int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if, int32_t val)
28100 +{
28101 + int retval = 0;
28102 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
28103 + DWC_WARN("`%d' invalid for parameter `pti_enable'\n", val);
28104 + return -DWC_E_INVALID;
28105 + }
28106 + if (val && (core_if->snpsid < OTG_CORE_REV_2_72a)) {
28107 + if (dwc_otg_param_initialized(core_if->core_params->pti_enable)) {
28108 + DWC_ERROR
28109 + ("%d invalid for parameter pti_enable. Check HW configuration.\n",
28110 + val);
28111 + }
28112 + retval = -DWC_E_INVALID;
28113 + val = 0;
28114 + }
28115 + core_if->core_params->pti_enable = val;
28116 + return retval;
28117 +}
28118 +
28119 +int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if)
28120 +{
28121 + return core_if->core_params->pti_enable;
28122 +}
28123 +
28124 +int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if, int32_t val)
28125 +{
28126 + int retval = 0;
28127 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
28128 + DWC_WARN("`%d' invalid for parameter `mpi_enable'\n", val);
28129 + return -DWC_E_INVALID;
28130 + }
28131 + if (val && (core_if->hwcfg2.b.multi_proc_int == 0)) {
28132 + if (dwc_otg_param_initialized(core_if->core_params->mpi_enable)) {
28133 + DWC_ERROR
28134 + ("%d invalid for parameter mpi_enable. Check HW configuration.\n",
28135 + val);
28136 + }
28137 + retval = -DWC_E_INVALID;
28138 + val = 0;
28139 + }
28140 + core_if->core_params->mpi_enable = val;
28141 + return retval;
28142 +}
28143 +
28144 +int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if)
28145 +{
28146 + return core_if->core_params->mpi_enable;
28147 +}
28148 +
28149 +int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if, int32_t val)
28150 +{
28151 + int retval = 0;
28152 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
28153 + DWC_WARN("`%d' invalid for parameter `adp_enable'\n", val);
28154 + return -DWC_E_INVALID;
28155 + }
28156 + if (val && (core_if->hwcfg3.b.adp_supp == 0)) {
28157 + if (dwc_otg_param_initialized
28158 + (core_if->core_params->adp_supp_enable)) {
28159 + DWC_ERROR
28160 + ("%d invalid for parameter adp_enable. Check HW configuration.\n",
28161 + val);
28162 + }
28163 + retval = -DWC_E_INVALID;
28164 + val = 0;
28165 + }
28166 + core_if->core_params->adp_supp_enable = val;
28167 + /*Set OTG version 2.0 in case of enabling ADP*/
28168 + if (val)
28169 + dwc_otg_set_param_otg_ver(core_if, 1);
28170 +
28171 + return retval;
28172 +}
28173 +
28174 +int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if)
28175 +{
28176 + return core_if->core_params->adp_supp_enable;
28177 +}
28178 +
28179 +int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if, int32_t val)
28180 +{
28181 + int retval = 0;
28182 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
28183 + DWC_WARN("`%d' invalid for parameter `ic_usb_cap'\n", val);
28184 + DWC_WARN("ic_usb_cap must be 0 or 1\n");
28185 + return -DWC_E_INVALID;
28186 + }
28187 +
28188 + if (val && (core_if->hwcfg2.b.otg_enable_ic_usb == 0)) {
28189 + if (dwc_otg_param_initialized(core_if->core_params->ic_usb_cap)) {
28190 + DWC_ERROR
28191 + ("%d invalid for parameter ic_usb_cap. Check HW configuration.\n",
28192 + val);
28193 + }
28194 + retval = -DWC_E_INVALID;
28195 + val = 0;
28196 + }
28197 + core_if->core_params->ic_usb_cap = val;
28198 + return retval;
28199 +}
28200 +
28201 +int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if)
28202 +{
28203 + return core_if->core_params->ic_usb_cap;
28204 +}
28205 +
28206 +int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, int32_t val)
28207 +{
28208 + int retval = 0;
28209 + int valid = 1;
28210 +
28211 + if (DWC_OTG_PARAM_TEST(val, 0, 3)) {
28212 + DWC_WARN("`%d' invalid for parameter `ahb_thr_ratio'\n", val);
28213 + DWC_WARN("ahb_thr_ratio must be 0 - 3\n");
28214 + return -DWC_E_INVALID;
28215 + }
28216 +
28217 + if (val
28218 + && (core_if->snpsid < OTG_CORE_REV_2_81a
28219 + || !dwc_otg_get_param_thr_ctl(core_if))) {
28220 + valid = 0;
28221 + } else if (val
28222 + && ((dwc_otg_get_param_tx_thr_length(core_if) / (1 << val)) <
28223 + 4)) {
28224 + valid = 0;
28225 + }
28226 + if (valid == 0) {
28227 + if (dwc_otg_param_initialized
28228 + (core_if->core_params->ahb_thr_ratio)) {
28229 + DWC_ERROR
28230 + ("%d invalid for parameter ahb_thr_ratio. Check HW configuration.\n",
28231 + val);
28232 + }
28233 + retval = -DWC_E_INVALID;
28234 + val = 0;
28235 + }
28236 +
28237 + core_if->core_params->ahb_thr_ratio = val;
28238 + return retval;
28239 +}
28240 +
28241 +int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if)
28242 +{
28243 + return core_if->core_params->ahb_thr_ratio;
28244 +}
28245 +
28246 +int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if, int32_t val)
28247 +{
28248 + int retval = 0;
28249 + int valid = 1;
28250 + hwcfg4_data_t hwcfg4 = {.d32 = 0 };
28251 + hwcfg4.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
28252 +
28253 + if (DWC_OTG_PARAM_TEST(val, 0, 3)) {
28254 + DWC_WARN("`%d' invalid for parameter `power_down'\n", val);
28255 + DWC_WARN("power_down must be 0 - 2\n");
28256 + return -DWC_E_INVALID;
28257 + }
28258 +
28259 + if ((val == 2) && (core_if->snpsid < OTG_CORE_REV_2_91a)) {
28260 + valid = 0;
28261 + }
28262 + if ((val == 3)
28263 + && ((core_if->snpsid < OTG_CORE_REV_3_00a)
28264 + || (hwcfg4.b.xhiber == 0))) {
28265 + valid = 0;
28266 + }
28267 + if (valid == 0) {
28268 + if (dwc_otg_param_initialized(core_if->core_params->power_down)) {
28269 + DWC_ERROR
28270 + ("%d invalid for parameter power_down. Check HW configuration.\n",
28271 + val);
28272 + }
28273 + retval = -DWC_E_INVALID;
28274 + val = 0;
28275 + }
28276 + core_if->core_params->power_down = val;
28277 + return retval;
28278 +}
28279 +
28280 +int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if)
28281 +{
28282 + return core_if->core_params->power_down;
28283 +}
28284 +
28285 +int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if, int32_t val)
28286 +{
28287 + int retval = 0;
28288 + int valid = 1;
28289 +
28290 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
28291 + DWC_WARN("`%d' invalid for parameter `reload_ctl'\n", val);
28292 + DWC_WARN("reload_ctl must be 0 or 1\n");
28293 + return -DWC_E_INVALID;
28294 + }
28295 +
28296 + if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_92a)) {
28297 + valid = 0;
28298 + }
28299 + if (valid == 0) {
28300 + if (dwc_otg_param_initialized(core_if->core_params->reload_ctl)) {
28301 + DWC_ERROR("%d invalid for parameter reload_ctl."
28302 + "Check HW configuration.\n", val);
28303 + }
28304 + retval = -DWC_E_INVALID;
28305 + val = 0;
28306 + }
28307 + core_if->core_params->reload_ctl = val;
28308 + return retval;
28309 +}
28310 +
28311 +int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if)
28312 +{
28313 + return core_if->core_params->reload_ctl;
28314 +}
28315 +
28316 +int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if, int32_t val)
28317 +{
28318 + int retval = 0;
28319 + int valid = 1;
28320 +
28321 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
28322 + DWC_WARN("`%d' invalid for parameter `dev_out_nak'\n", val);
28323 + DWC_WARN("dev_out_nak must be 0 or 1\n");
28324 + return -DWC_E_INVALID;
28325 + }
28326 +
28327 + if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_93a) ||
28328 + !(core_if->core_params->dma_desc_enable))) {
28329 + valid = 0;
28330 + }
28331 + if (valid == 0) {
28332 + if (dwc_otg_param_initialized(core_if->core_params->dev_out_nak)) {
28333 + DWC_ERROR("%d invalid for parameter dev_out_nak."
28334 + "Check HW configuration.\n", val);
28335 + }
28336 + retval = -DWC_E_INVALID;
28337 + val = 0;
28338 + }
28339 + core_if->core_params->dev_out_nak = val;
28340 + return retval;
28341 +}
28342 +
28343 +int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if)
28344 +{
28345 + return core_if->core_params->dev_out_nak;
28346 +}
28347 +
28348 +int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if, int32_t val)
28349 +{
28350 + int retval = 0;
28351 + int valid = 1;
28352 +
28353 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
28354 + DWC_WARN("`%d' invalid for parameter `cont_on_bna'\n", val);
28355 + DWC_WARN("cont_on_bna must be 0 or 1\n");
28356 + return -DWC_E_INVALID;
28357 + }
28358 +
28359 + if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_94a) ||
28360 + !(core_if->core_params->dma_desc_enable))) {
28361 + valid = 0;
28362 + }
28363 + if (valid == 0) {
28364 + if (dwc_otg_param_initialized(core_if->core_params->cont_on_bna)) {
28365 + DWC_ERROR("%d invalid for parameter cont_on_bna."
28366 + "Check HW configuration.\n", val);
28367 + }
28368 + retval = -DWC_E_INVALID;
28369 + val = 0;
28370 + }
28371 + core_if->core_params->cont_on_bna = val;
28372 + return retval;
28373 +}
28374 +
28375 +int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if)
28376 +{
28377 + return core_if->core_params->cont_on_bna;
28378 +}
28379 +
28380 +int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if, int32_t val)
28381 +{
28382 + int retval = 0;
28383 + int valid = 1;
28384 +
28385 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
28386 + DWC_WARN("`%d' invalid for parameter `ahb_single'\n", val);
28387 + DWC_WARN("ahb_single must be 0 or 1\n");
28388 + return -DWC_E_INVALID;
28389 + }
28390 +
28391 + if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_94a)) {
28392 + valid = 0;
28393 + }
28394 + if (valid == 0) {
28395 + if (dwc_otg_param_initialized(core_if->core_params->ahb_single)) {
28396 + DWC_ERROR("%d invalid for parameter ahb_single."
28397 + "Check HW configuration.\n", val);
28398 + }
28399 + retval = -DWC_E_INVALID;
28400 + val = 0;
28401 + }
28402 + core_if->core_params->ahb_single = val;
28403 + return retval;
28404 +}
28405 +
28406 +int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if)
28407 +{
28408 + return core_if->core_params->ahb_single;
28409 +}
28410 +
28411 +int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val)
28412 +{
28413 + int retval = 0;
28414 +
28415 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
28416 + DWC_WARN("`%d' invalid for parameter `otg_ver'\n", val);
28417 + DWC_WARN
28418 + ("otg_ver must be 0(for OTG 1.3 support) or 1(for OTG 2.0 support)\n");
28419 + return -DWC_E_INVALID;
28420 + }
28421 +
28422 + core_if->core_params->otg_ver = val;
28423 + return retval;
28424 +}
28425 +
28426 +int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if)
28427 +{
28428 + return core_if->core_params->otg_ver;
28429 +}
28430 +
28431 +uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if)
28432 +{
28433 + gotgctl_data_t otgctl;
28434 + otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
28435 + return otgctl.b.hstnegscs;
28436 +}
28437 +
28438 +uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if)
28439 +{
28440 + gotgctl_data_t otgctl;
28441 + otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
28442 + return otgctl.b.sesreqscs;
28443 +}
28444 +
28445 +void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val)
28446 +{
28447 + if(core_if->otg_ver == 0) {
28448 + gotgctl_data_t otgctl;
28449 + otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
28450 + otgctl.b.hnpreq = val;
28451 + DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, otgctl.d32);
28452 + } else {
28453 + core_if->otg_sts = val;
28454 + }
28455 +}
28456 +
28457 +uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if)
28458 +{
28459 + return core_if->snpsid;
28460 +}
28461 +
28462 +uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if)
28463 +{
28464 + gintsts_data_t gintsts;
28465 + gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
28466 + return gintsts.b.curmode;
28467 +}
28468 +
28469 +uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if)
28470 +{
28471 + gusbcfg_data_t usbcfg;
28472 + usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
28473 + return usbcfg.b.hnpcap;
28474 +}
28475 +
28476 +void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
28477 +{
28478 + gusbcfg_data_t usbcfg;
28479 + usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
28480 + usbcfg.b.hnpcap = val;
28481 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
28482 +}
28483 +
28484 +uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if)
28485 +{
28486 + gusbcfg_data_t usbcfg;
28487 + usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
28488 + return usbcfg.b.srpcap;
28489 +}
28490 +
28491 +void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
28492 +{
28493 + gusbcfg_data_t usbcfg;
28494 + usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
28495 + usbcfg.b.srpcap = val;
28496 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
28497 +}
28498 +
28499 +uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if)
28500 +{
28501 + dcfg_data_t dcfg;
28502 + /* originally: dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); */
28503 +
28504 + dcfg.d32 = -1; //GRAYG
28505 + DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)\n", __func__, core_if);
28506 + if (NULL == core_if)
28507 + DWC_ERROR("reg request with NULL core_if\n");
28508 + DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)->dev_if(%p)\n", __func__,
28509 + core_if, core_if->dev_if);
28510 + if (NULL == core_if->dev_if)
28511 + DWC_ERROR("reg request with NULL dev_if\n");
28512 + DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)->dev_if(%p)->"
28513 + "dev_global_regs(%p)\n", __func__,
28514 + core_if, core_if->dev_if,
28515 + core_if->dev_if->dev_global_regs);
28516 + if (NULL == core_if->dev_if->dev_global_regs)
28517 + DWC_ERROR("reg request with NULL dev_global_regs\n");
28518 + else {
28519 + DWC_DEBUGPL(DBG_CILV, "%s - &core_if(%p)->dev_if(%p)->"
28520 + "dev_global_regs(%p)->dcfg = %p\n", __func__,
28521 + core_if, core_if->dev_if,
28522 + core_if->dev_if->dev_global_regs,
28523 + &core_if->dev_if->dev_global_regs->dcfg);
28524 + dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
28525 + }
28526 + return dcfg.b.devspd;
28527 +}
28528 +
28529 +void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val)
28530 +{
28531 + dcfg_data_t dcfg;
28532 + dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
28533 + dcfg.b.devspd = val;
28534 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
28535 +}
28536 +
28537 +uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if)
28538 +{
28539 + hprt0_data_t hprt0;
28540 + hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
28541 + return hprt0.b.prtconnsts;
28542 +}
28543 +
28544 +uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if)
28545 +{
28546 + dsts_data_t dsts;
28547 + dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
28548 + return dsts.b.enumspd;
28549 +}
28550 +
28551 +uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if)
28552 +{
28553 + hprt0_data_t hprt0;
28554 + hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
28555 + return hprt0.b.prtpwr;
28556 +
28557 +}
28558 +
28559 +uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if)
28560 +{
28561 + return core_if->hibernation_suspend;
28562 +}
28563 +
28564 +void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val)
28565 +{
28566 + hprt0_data_t hprt0;
28567 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
28568 + hprt0.b.prtpwr = val;
28569 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
28570 +}
28571 +
28572 +uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if)
28573 +{
28574 + hprt0_data_t hprt0;
28575 + hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
28576 + return hprt0.b.prtsusp;
28577 +
28578 +}
28579 +
28580 +void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val)
28581 +{
28582 + hprt0_data_t hprt0;
28583 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
28584 + hprt0.b.prtsusp = val;
28585 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
28586 +}
28587 +
28588 +uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if)
28589 +{
28590 + hfir_data_t hfir;
28591 + hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
28592 + return hfir.b.frint;
28593 +
28594 +}
28595 +
28596 +void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val)
28597 +{
28598 + hfir_data_t hfir;
28599 + uint32_t fram_int;
28600 + fram_int = calc_frame_interval(core_if);
28601 + hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
28602 + if (!core_if->core_params->reload_ctl) {
28603 + DWC_WARN("\nCannot reload HFIR register.HFIR.HFIRRldCtrl bit is"
28604 + "not set to 1.\nShould load driver with reload_ctl=1"
28605 + " module parameter\n");
28606 + return;
28607 + }
28608 + switch (fram_int) {
28609 + case 3750:
28610 + if ((val < 3350) || (val > 4150)) {
28611 + DWC_WARN("HFIR interval for HS core and 30 MHz"
28612 + "clock freq should be from 3350 to 4150\n");
28613 + return;
28614 + }
28615 + break;
28616 + case 30000:
28617 + if ((val < 26820) || (val > 33180)) {
28618 + DWC_WARN("HFIR interval for FS/LS core and 30 MHz"
28619 + "clock freq should be from 26820 to 33180\n");
28620 + return;
28621 + }
28622 + break;
28623 + case 6000:
28624 + if ((val < 5360) || (val > 6640)) {
28625 + DWC_WARN("HFIR interval for HS core and 48 MHz"
28626 + "clock freq should be from 5360 to 6640\n");
28627 + return;
28628 + }
28629 + break;
28630 + case 48000:
28631 + if ((val < 42912) || (val > 53088)) {
28632 + DWC_WARN("HFIR interval for FS/LS core and 48 MHz"
28633 + "clock freq should be from 42912 to 53088\n");
28634 + return;
28635 + }
28636 + break;
28637 + case 7500:
28638 + if ((val < 6700) || (val > 8300)) {
28639 + DWC_WARN("HFIR interval for HS core and 60 MHz"
28640 + "clock freq should be from 6700 to 8300\n");
28641 + return;
28642 + }
28643 + break;
28644 + case 60000:
28645 + if ((val < 53640) || (val > 65536)) {
28646 + DWC_WARN("HFIR interval for FS/LS core and 60 MHz"
28647 + "clock freq should be from 53640 to 65536\n");
28648 + return;
28649 + }
28650 + break;
28651 + default:
28652 + DWC_WARN("Unknown frame interval\n");
28653 + return;
28654 + break;
28655 +
28656 + }
28657 + hfir.b.frint = val;
28658 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hfir.d32);
28659 +}
28660 +
28661 +uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if)
28662 +{
28663 + hcfg_data_t hcfg;
28664 + hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
28665 + return hcfg.b.modechtimen;
28666 +
28667 +}
28668 +
28669 +void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val)
28670 +{
28671 + hcfg_data_t hcfg;
28672 + hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
28673 + hcfg.b.modechtimen = val;
28674 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
28675 +}
28676 +
28677 +void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val)
28678 +{
28679 + hprt0_data_t hprt0;
28680 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
28681 + hprt0.b.prtres = val;
28682 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
28683 +}
28684 +
28685 +uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if)
28686 +{
28687 + dctl_data_t dctl;
28688 + dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
28689 + return dctl.b.rmtwkupsig;
28690 +}
28691 +
28692 +uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if)
28693 +{
28694 + glpmcfg_data_t lpmcfg;
28695 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28696 +
28697 + DWC_ASSERT(!
28698 + ((core_if->lx_state == DWC_OTG_L1) ^ lpmcfg.b.prt_sleep_sts),
28699 + "lx_state = %d, lmpcfg.prt_sleep_sts = %d\n",
28700 + core_if->lx_state, lpmcfg.b.prt_sleep_sts);
28701 +
28702 + return lpmcfg.b.prt_sleep_sts;
28703 +}
28704 +
28705 +uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if)
28706 +{
28707 + glpmcfg_data_t lpmcfg;
28708 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28709 + return lpmcfg.b.rem_wkup_en;
28710 +}
28711 +
28712 +uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if)
28713 +{
28714 + glpmcfg_data_t lpmcfg;
28715 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28716 + return lpmcfg.b.appl_resp;
28717 +}
28718 +
28719 +void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val)
28720 +{
28721 + glpmcfg_data_t lpmcfg;
28722 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28723 + lpmcfg.b.appl_resp = val;
28724 + DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
28725 +}
28726 +
28727 +uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if)
28728 +{
28729 + glpmcfg_data_t lpmcfg;
28730 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28731 + return lpmcfg.b.hsic_connect;
28732 +}
28733 +
28734 +void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val)
28735 +{
28736 + glpmcfg_data_t lpmcfg;
28737 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28738 + lpmcfg.b.hsic_connect = val;
28739 + DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
28740 +}
28741 +
28742 +uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if)
28743 +{
28744 + glpmcfg_data_t lpmcfg;
28745 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28746 + return lpmcfg.b.inv_sel_hsic;
28747 +
28748 +}
28749 +
28750 +void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val)
28751 +{
28752 + glpmcfg_data_t lpmcfg;
28753 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28754 + lpmcfg.b.inv_sel_hsic = val;
28755 + DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
28756 +}
28757 +
28758 +uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if)
28759 +{
28760 + return DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
28761 +}
28762 +
28763 +void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val)
28764 +{
28765 + DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, val);
28766 +}
28767 +
28768 +uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if)
28769 +{
28770 + return DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
28771 +}
28772 +
28773 +void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val)
28774 +{
28775 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, val);
28776 +}
28777 +
28778 +uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if)
28779 +{
28780 + return DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
28781 +}
28782 +
28783 +void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
28784 +{
28785 + DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, val);
28786 +}
28787 +
28788 +uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if)
28789 +{
28790 + return DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
28791 +}
28792 +
28793 +void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
28794 +{
28795 + DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz, val);
28796 +}
28797 +
28798 +uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if)
28799 +{
28800 + return DWC_READ_REG32(&core_if->core_global_regs->gpvndctl);
28801 +}
28802 +
28803 +void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val)
28804 +{
28805 + DWC_WRITE_REG32(&core_if->core_global_regs->gpvndctl, val);
28806 +}
28807 +
28808 +uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if)
28809 +{
28810 + return DWC_READ_REG32(&core_if->core_global_regs->ggpio);
28811 +}
28812 +
28813 +void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val)
28814 +{
28815 + DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, val);
28816 +}
28817 +
28818 +uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if)
28819 +{
28820 + return DWC_READ_REG32(core_if->host_if->hprt0);
28821 +
28822 +}
28823 +
28824 +void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val)
28825 +{
28826 + DWC_WRITE_REG32(core_if->host_if->hprt0, val);
28827 +}
28828 +
28829 +uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if)
28830 +{
28831 + return DWC_READ_REG32(&core_if->core_global_regs->guid);
28832 +}
28833 +
28834 +void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val)
28835 +{
28836 + DWC_WRITE_REG32(&core_if->core_global_regs->guid, val);
28837 +}
28838 +
28839 +uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if)
28840 +{
28841 + return DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
28842 +}
28843 +
28844 +uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if)
28845 +{
28846 + return ((core_if->otg_ver == 1) ? (uint16_t)0x0200 : (uint16_t)0x0103);
28847 +}
28848 +
28849 +/**
28850 + * Start the SRP timer to detect when the SRP does not complete within
28851 + * 6 seconds.
28852 + *
28853 + * @param core_if the pointer to core_if strucure.
28854 + */
28855 +void dwc_otg_pcd_start_srp_timer(dwc_otg_core_if_t * core_if)
28856 +{
28857 + core_if->srp_timer_started = 1;
28858 + DWC_TIMER_SCHEDULE(core_if->srp_timer, 6000 /* 6 secs */ );
28859 +}
28860 +
28861 +void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if)
28862 +{
28863 + uint32_t *addr = (uint32_t *) & (core_if->core_global_regs->gotgctl);
28864 + gotgctl_data_t mem;
28865 + gotgctl_data_t val;
28866 +
28867 + val.d32 = DWC_READ_REG32(addr);
28868 + if (val.b.sesreq) {
28869 + DWC_ERROR("Session Request Already active!\n");
28870 + return;
28871 + }
28872 +
28873 + DWC_INFO("Session Request Initated\n"); //NOTICE
28874 + mem.d32 = DWC_READ_REG32(addr);
28875 + mem.b.sesreq = 1;
28876 + DWC_WRITE_REG32(addr, mem.d32);
28877 +
28878 + /* Start the SRP timer */
28879 + dwc_otg_pcd_start_srp_timer(core_if);
28880 + return;
28881 +}
28882 --- /dev/null
28883 +++ b/drivers/usb/host/dwc_otg/dwc_otg_cil.h
28884 @@ -0,0 +1,1464 @@
28885 +/* ==========================================================================
28886 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $
28887 + * $Revision: #123 $
28888 + * $Date: 2012/08/10 $
28889 + * $Change: 2047372 $
28890 + *
28891 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
28892 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
28893 + * otherwise expressly agreed to in writing between Synopsys and you.
28894 + *
28895 + * The Software IS NOT an item of Licensed Software or Licensed Product under
28896 + * any End User Software License Agreement or Agreement for Licensed Product
28897 + * with Synopsys or any supplement thereto. You are permitted to use and
28898 + * redistribute this Software in source and binary forms, with or without
28899 + * modification, provided that redistributions of source code must retain this
28900 + * notice. You may not view, use, disclose, copy or distribute this file or
28901 + * any information contained herein except pursuant to this license grant from
28902 + * Synopsys. If you do not agree with this notice, including the disclaimer
28903 + * below, then you are not authorized to use the Software.
28904 + *
28905 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
28906 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28907 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28908 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
28909 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28910 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28911 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28912 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28913 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28914 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
28915 + * DAMAGE.
28916 + * ========================================================================== */
28917 +
28918 +#if !defined(__DWC_CIL_H__)
28919 +#define __DWC_CIL_H__
28920 +
28921 +#include "dwc_list.h"
28922 +#include "dwc_otg_dbg.h"
28923 +#include "dwc_otg_regs.h"
28924 +
28925 +#include "dwc_otg_core_if.h"
28926 +#include "dwc_otg_adp.h"
28927 +
28928 +/**
28929 + * @file
28930 + * This file contains the interface to the Core Interface Layer.
28931 + */
28932 +
28933 +#ifdef DWC_UTE_CFI
28934 +
28935 +#define MAX_DMA_DESCS_PER_EP 256
28936 +
28937 +/**
28938 + * Enumeration for the data buffer mode
28939 + */
28940 +typedef enum _data_buffer_mode {
28941 + BM_STANDARD = 0, /* data buffer is in normal mode */
28942 + BM_SG = 1, /* data buffer uses the scatter/gather mode */
28943 + BM_CONCAT = 2, /* data buffer uses the concatenation mode */
28944 + BM_CIRCULAR = 3, /* data buffer uses the circular DMA mode */
28945 + BM_ALIGN = 4 /* data buffer is in buffer alignment mode */
28946 +} data_buffer_mode_e;
28947 +#endif //DWC_UTE_CFI
28948 +
28949 +/** Macros defined for DWC OTG HW Release version */
28950 +
28951 +#define OTG_CORE_REV_2_60a 0x4F54260A
28952 +#define OTG_CORE_REV_2_71a 0x4F54271A
28953 +#define OTG_CORE_REV_2_72a 0x4F54272A
28954 +#define OTG_CORE_REV_2_80a 0x4F54280A
28955 +#define OTG_CORE_REV_2_81a 0x4F54281A
28956 +#define OTG_CORE_REV_2_90a 0x4F54290A
28957 +#define OTG_CORE_REV_2_91a 0x4F54291A
28958 +#define OTG_CORE_REV_2_92a 0x4F54292A
28959 +#define OTG_CORE_REV_2_93a 0x4F54293A
28960 +#define OTG_CORE_REV_2_94a 0x4F54294A
28961 +#define OTG_CORE_REV_3_00a 0x4F54300A
28962 +
28963 +/**
28964 + * Information for each ISOC packet.
28965 + */
28966 +typedef struct iso_pkt_info {
28967 + uint32_t offset;
28968 + uint32_t length;
28969 + int32_t status;
28970 +} iso_pkt_info_t;
28971 +
28972 +/**
28973 + * The <code>dwc_ep</code> structure represents the state of a single
28974 + * endpoint when acting in device mode. It contains the data items
28975 + * needed for an endpoint to be activated and transfer packets.
28976 + */
28977 +typedef struct dwc_ep {
28978 + /** EP number used for register address lookup */
28979 + uint8_t num;
28980 + /** EP direction 0 = OUT */
28981 + unsigned is_in:1;
28982 + /** EP active. */
28983 + unsigned active:1;
28984 +
28985 + /**
28986 + * Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic
28987 + * Tx FIFO. If dedicated Tx FIFOs are enabled Tx FIFO # FOR IN EPs*/
28988 + unsigned tx_fifo_num:4;
28989 + /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */
28990 + unsigned type:2;
28991 +#define DWC_OTG_EP_TYPE_CONTROL 0
28992 +#define DWC_OTG_EP_TYPE_ISOC 1
28993 +#define DWC_OTG_EP_TYPE_BULK 2
28994 +#define DWC_OTG_EP_TYPE_INTR 3
28995 +
28996 + /** DATA start PID for INTR and BULK EP */
28997 + unsigned data_pid_start:1;
28998 + /** Frame (even/odd) for ISOC EP */
28999 + unsigned even_odd_frame:1;
29000 + /** Max Packet bytes */
29001 + unsigned maxpacket:11;
29002 +
29003 + /** Max Transfer size */
29004 + uint32_t maxxfer;
29005 +
29006 + /** @name Transfer state */
29007 + /** @{ */
29008 +
29009 + /**
29010 + * Pointer to the beginning of the transfer buffer -- do not modify
29011 + * during transfer.
29012 + */
29013 +
29014 + dwc_dma_t dma_addr;
29015 +
29016 + dwc_dma_t dma_desc_addr;
29017 + dwc_otg_dev_dma_desc_t *desc_addr;
29018 +
29019 + uint8_t *start_xfer_buff;
29020 + /** pointer to the transfer buffer */
29021 + uint8_t *xfer_buff;
29022 + /** Number of bytes to transfer */
29023 + unsigned xfer_len:19;
29024 + /** Number of bytes transferred. */
29025 + unsigned xfer_count:19;
29026 + /** Sent ZLP */
29027 + unsigned sent_zlp:1;
29028 + /** Total len for control transfer */
29029 + unsigned total_len:19;
29030 +
29031 + /** stall clear flag */
29032 + unsigned stall_clear_flag:1;
29033 +
29034 + /** SETUP pkt cnt rollover flag for EP0 out*/
29035 + unsigned stp_rollover;
29036 +
29037 +#ifdef DWC_UTE_CFI
29038 + /* The buffer mode */
29039 + data_buffer_mode_e buff_mode;
29040 +
29041 + /* The chain of DMA descriptors.
29042 + * MAX_DMA_DESCS_PER_EP will be allocated for each active EP.
29043 + */
29044 + dwc_otg_dma_desc_t *descs;
29045 +
29046 + /* The DMA address of the descriptors chain start */
29047 + dma_addr_t descs_dma_addr;
29048 + /** This variable stores the length of the last enqueued request */
29049 + uint32_t cfi_req_len;
29050 +#endif //DWC_UTE_CFI
29051 +
29052 +/** Max DMA Descriptor count for any EP */
29053 +#define MAX_DMA_DESC_CNT 256
29054 + /** Allocated DMA Desc count */
29055 + uint32_t desc_cnt;
29056 +
29057 + /** bInterval */
29058 + uint32_t bInterval;
29059 + /** Next frame num to setup next ISOC transfer */
29060 + uint32_t frame_num;
29061 + /** Indicates SOF number overrun in DSTS */
29062 + uint8_t frm_overrun;
29063 +
29064 +#ifdef DWC_UTE_PER_IO
29065 + /** Next frame num for which will be setup DMA Desc */
29066 + uint32_t xiso_frame_num;
29067 + /** bInterval */
29068 + uint32_t xiso_bInterval;
29069 + /** Count of currently active transfers - shall be either 0 or 1 */
29070 + int xiso_active_xfers;
29071 + int xiso_queued_xfers;
29072 +#endif
29073 +#ifdef DWC_EN_ISOC
29074 + /**
29075 + * Variables specific for ISOC EPs
29076 + *
29077 + */
29078 + /** DMA addresses of ISOC buffers */
29079 + dwc_dma_t dma_addr0;
29080 + dwc_dma_t dma_addr1;
29081 +
29082 + dwc_dma_t iso_dma_desc_addr;
29083 + dwc_otg_dev_dma_desc_t *iso_desc_addr;
29084 +
29085 + /** pointer to the transfer buffers */
29086 + uint8_t *xfer_buff0;
29087 + uint8_t *xfer_buff1;
29088 +
29089 + /** number of ISOC Buffer is processing */
29090 + uint32_t proc_buf_num;
29091 + /** Interval of ISOC Buffer processing */
29092 + uint32_t buf_proc_intrvl;
29093 + /** Data size for regular frame */
29094 + uint32_t data_per_frame;
29095 +
29096 + /* todo - pattern data support is to be implemented in the future */
29097 + /** Data size for pattern frame */
29098 + uint32_t data_pattern_frame;
29099 + /** Frame number of pattern data */
29100 + uint32_t sync_frame;
29101 +
29102 + /** bInterval */
29103 + uint32_t bInterval;
29104 + /** ISO Packet number per frame */
29105 + uint32_t pkt_per_frm;
29106 + /** Next frame num for which will be setup DMA Desc */
29107 + uint32_t next_frame;
29108 + /** Number of packets per buffer processing */
29109 + uint32_t pkt_cnt;
29110 + /** Info for all isoc packets */
29111 + iso_pkt_info_t *pkt_info;
29112 + /** current pkt number */
29113 + uint32_t cur_pkt;
29114 + /** current pkt number */
29115 + uint8_t *cur_pkt_addr;
29116 + /** current pkt number */
29117 + uint32_t cur_pkt_dma_addr;
29118 +#endif /* DWC_EN_ISOC */
29119 +
29120 +/** @} */
29121 +} dwc_ep_t;
29122 +
29123 +/*
29124 + * Reasons for halting a host channel.
29125 + */
29126 +typedef enum dwc_otg_halt_status {
29127 + DWC_OTG_HC_XFER_NO_HALT_STATUS,
29128 + DWC_OTG_HC_XFER_COMPLETE,
29129 + DWC_OTG_HC_XFER_URB_COMPLETE,
29130 + DWC_OTG_HC_XFER_ACK,
29131 + DWC_OTG_HC_XFER_NAK,
29132 + DWC_OTG_HC_XFER_NYET,
29133 + DWC_OTG_HC_XFER_STALL,
29134 + DWC_OTG_HC_XFER_XACT_ERR,
29135 + DWC_OTG_HC_XFER_FRAME_OVERRUN,
29136 + DWC_OTG_HC_XFER_BABBLE_ERR,
29137 + DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
29138 + DWC_OTG_HC_XFER_AHB_ERR,
29139 + DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
29140 + DWC_OTG_HC_XFER_URB_DEQUEUE
29141 +} dwc_otg_halt_status_e;
29142 +
29143 +/**
29144 + * Host channel descriptor. This structure represents the state of a single
29145 + * host channel when acting in host mode. It contains the data items needed to
29146 + * transfer packets to an endpoint via a host channel.
29147 + */
29148 +typedef struct dwc_hc {
29149 + /** Host channel number used for register address lookup */
29150 + uint8_t hc_num;
29151 +
29152 + /** Device to access */
29153 + unsigned dev_addr:7;
29154 +
29155 + /** EP to access */
29156 + unsigned ep_num:4;
29157 +
29158 + /** EP direction. 0: OUT, 1: IN */
29159 + unsigned ep_is_in:1;
29160 +
29161 + /**
29162 + * EP speed.
29163 + * One of the following values:
29164 + * - DWC_OTG_EP_SPEED_LOW
29165 + * - DWC_OTG_EP_SPEED_FULL
29166 + * - DWC_OTG_EP_SPEED_HIGH
29167 + */
29168 + unsigned speed:2;
29169 +#define DWC_OTG_EP_SPEED_LOW 0
29170 +#define DWC_OTG_EP_SPEED_FULL 1
29171 +#define DWC_OTG_EP_SPEED_HIGH 2
29172 +
29173 + /**
29174 + * Endpoint type.
29175 + * One of the following values:
29176 + * - DWC_OTG_EP_TYPE_CONTROL: 0
29177 + * - DWC_OTG_EP_TYPE_ISOC: 1
29178 + * - DWC_OTG_EP_TYPE_BULK: 2
29179 + * - DWC_OTG_EP_TYPE_INTR: 3
29180 + */
29181 + unsigned ep_type:2;
29182 +
29183 + /** Max packet size in bytes */
29184 + unsigned max_packet:11;
29185 +
29186 + /**
29187 + * PID for initial transaction.
29188 + * 0: DATA0,<br>
29189 + * 1: DATA2,<br>
29190 + * 2: DATA1,<br>
29191 + * 3: MDATA (non-Control EP),
29192 + * SETUP (Control EP)
29193 + */
29194 + unsigned data_pid_start:2;
29195 +#define DWC_OTG_HC_PID_DATA0 0
29196 +#define DWC_OTG_HC_PID_DATA2 1
29197 +#define DWC_OTG_HC_PID_DATA1 2
29198 +#define DWC_OTG_HC_PID_MDATA 3
29199 +#define DWC_OTG_HC_PID_SETUP 3
29200 +
29201 + /** Number of periodic transactions per (micro)frame */
29202 + unsigned multi_count:2;
29203 +
29204 + /** @name Transfer State */
29205 + /** @{ */
29206 +
29207 + /** Pointer to the current transfer buffer position. */
29208 + uint8_t *xfer_buff;
29209 + /**
29210 + * In Buffer DMA mode this buffer will be used
29211 + * if xfer_buff is not DWORD aligned.
29212 + */
29213 + dwc_dma_t align_buff;
29214 + /** Total number of bytes to transfer. */
29215 + uint32_t xfer_len;
29216 + /** Number of bytes transferred so far. */
29217 + uint32_t xfer_count;
29218 + /** Packet count at start of transfer.*/
29219 + uint16_t start_pkt_count;
29220 +
29221 + /**
29222 + * Flag to indicate whether the transfer has been started. Set to 1 if
29223 + * it has been started, 0 otherwise.
29224 + */
29225 + uint8_t xfer_started;
29226 +
29227 + /**
29228 + * Set to 1 to indicate that a PING request should be issued on this
29229 + * channel. If 0, process normally.
29230 + */
29231 + uint8_t do_ping;
29232 +
29233 + /**
29234 + * Set to 1 to indicate that the error count for this transaction is
29235 + * non-zero. Set to 0 if the error count is 0.
29236 + */
29237 + uint8_t error_state;
29238 +
29239 + /**
29240 + * Set to 1 to indicate that this channel should be halted the next
29241 + * time a request is queued for the channel. This is necessary in
29242 + * slave mode if no request queue space is available when an attempt
29243 + * is made to halt the channel.
29244 + */
29245 + uint8_t halt_on_queue;
29246 +
29247 + /**
29248 + * Set to 1 if the host channel has been halted, but the core is not
29249 + * finished flushing queued requests. Otherwise 0.
29250 + */
29251 + uint8_t halt_pending;
29252 +
29253 + /**
29254 + * Reason for halting the host channel.
29255 + */
29256 + dwc_otg_halt_status_e halt_status;
29257 +
29258 + /*
29259 + * Split settings for the host channel
29260 + */
29261 + uint8_t do_split; /**< Enable split for the channel */
29262 + uint8_t complete_split; /**< Enable complete split */
29263 + uint8_t hub_addr; /**< Address of high speed hub */
29264 +
29265 + uint8_t port_addr; /**< Port of the low/full speed device */
29266 + /** Split transaction position
29267 + * One of the following values:
29268 + * - DWC_HCSPLIT_XACTPOS_MID
29269 + * - DWC_HCSPLIT_XACTPOS_BEGIN
29270 + * - DWC_HCSPLIT_XACTPOS_END
29271 + * - DWC_HCSPLIT_XACTPOS_ALL */
29272 + uint8_t xact_pos;
29273 +
29274 + /** Set when the host channel does a short read. */
29275 + uint8_t short_read;
29276 +
29277 + /**
29278 + * Number of requests issued for this channel since it was assigned to
29279 + * the current transfer (not counting PINGs).
29280 + */
29281 + uint8_t requests;
29282 +
29283 + /**
29284 + * Queue Head for the transfer being processed by this channel.
29285 + */
29286 + struct dwc_otg_qh *qh;
29287 +
29288 + /** @} */
29289 +
29290 + /** Entry in list of host channels. */
29291 + DWC_CIRCLEQ_ENTRY(dwc_hc) hc_list_entry;
29292 +
29293 + /** @name Descriptor DMA support */
29294 + /** @{ */
29295 +
29296 + /** Number of Transfer Descriptors */
29297 + uint16_t ntd;
29298 +
29299 + /** Descriptor List DMA address */
29300 + dwc_dma_t desc_list_addr;
29301 +
29302 + /** Scheduling micro-frame bitmap. */
29303 + uint8_t schinfo;
29304 +
29305 + /** @} */
29306 +} dwc_hc_t;
29307 +
29308 +/**
29309 + * The following parameters may be specified when starting the module. These
29310 + * parameters define how the DWC_otg controller should be configured.
29311 + */
29312 +typedef struct dwc_otg_core_params {
29313 + int32_t opt;
29314 +
29315 + /**
29316 + * Specifies the OTG capabilities. The driver will automatically
29317 + * detect the value for this parameter if none is specified.
29318 + * 0 - HNP and SRP capable (default)
29319 + * 1 - SRP Only capable
29320 + * 2 - No HNP/SRP capable
29321 + */
29322 + int32_t otg_cap;
29323 +
29324 + /**
29325 + * Specifies whether to use slave or DMA mode for accessing the data
29326 + * FIFOs. The driver will automatically detect the value for this
29327 + * parameter if none is specified.
29328 + * 0 - Slave
29329 + * 1 - DMA (default, if available)
29330 + */
29331 + int32_t dma_enable;
29332 +
29333 + /**
29334 + * When DMA mode is enabled specifies whether to use address DMA or DMA
29335 + * Descriptor mode for accessing the data FIFOs in device mode. The driver
29336 + * will automatically detect the value for this if none is specified.
29337 + * 0 - address DMA
29338 + * 1 - DMA Descriptor(default, if available)
29339 + */
29340 + int32_t dma_desc_enable;
29341 + /** The DMA Burst size (applicable only for External DMA
29342 + * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
29343 + */
29344 + int32_t dma_burst_size; /* Translate this to GAHBCFG values */
29345 +
29346 + /**
29347 + * Specifies the maximum speed of operation in host and device mode.
29348 + * The actual speed depends on the speed of the attached device and
29349 + * the value of phy_type. The actual speed depends on the speed of the
29350 + * attached device.
29351 + * 0 - High Speed (default)
29352 + * 1 - Full Speed
29353 + */
29354 + int32_t speed;
29355 + /** Specifies whether low power mode is supported when attached
29356 + * to a Full Speed or Low Speed device in host mode.
29357 + * 0 - Don't support low power mode (default)
29358 + * 1 - Support low power mode
29359 + */
29360 + int32_t host_support_fs_ls_low_power;
29361 +
29362 + /** Specifies the PHY clock rate in low power mode when connected to a
29363 + * Low Speed device in host mode. This parameter is applicable only if
29364 + * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
29365 + * then defaults to 6 MHZ otherwise 48 MHZ.
29366 + *
29367 + * 0 - 48 MHz
29368 + * 1 - 6 MHz
29369 + */
29370 + int32_t host_ls_low_power_phy_clk;
29371 +
29372 + /**
29373 + * 0 - Use cC FIFO size parameters
29374 + * 1 - Allow dynamic FIFO sizing (default)
29375 + */
29376 + int32_t enable_dynamic_fifo;
29377 +
29378 + /** Total number of 4-byte words in the data FIFO memory. This
29379 + * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
29380 + * Tx FIFOs.
29381 + * 32 to 32768 (default 8192)
29382 + * Note: The total FIFO memory depth in the FPGA configuration is 8192.
29383 + */
29384 + int32_t data_fifo_size;
29385 +
29386 + /** Number of 4-byte words in the Rx FIFO in device mode when dynamic
29387 + * FIFO sizing is enabled.
29388 + * 16 to 32768 (default 1064)
29389 + */
29390 + int32_t dev_rx_fifo_size;
29391 +
29392 + /** Number of 4-byte words in the non-periodic Tx FIFO in device mode
29393 + * when dynamic FIFO sizing is enabled.
29394 + * 16 to 32768 (default 1024)
29395 + */
29396 + int32_t dev_nperio_tx_fifo_size;
29397 +
29398 + /** Number of 4-byte words in each of the periodic Tx FIFOs in device
29399 + * mode when dynamic FIFO sizing is enabled.
29400 + * 4 to 768 (default 256)
29401 + */
29402 + uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
29403 +
29404 + /** Number of 4-byte words in the Rx FIFO in host mode when dynamic
29405 + * FIFO sizing is enabled.
29406 + * 16 to 32768 (default 1024)
29407 + */
29408 + int32_t host_rx_fifo_size;
29409 +
29410 + /** Number of 4-byte words in the non-periodic Tx FIFO in host mode
29411 + * when Dynamic FIFO sizing is enabled in the core.
29412 + * 16 to 32768 (default 1024)
29413 + */
29414 + int32_t host_nperio_tx_fifo_size;
29415 +
29416 + /** Number of 4-byte words in the host periodic Tx FIFO when dynamic
29417 + * FIFO sizing is enabled.
29418 + * 16 to 32768 (default 1024)
29419 + */
29420 + int32_t host_perio_tx_fifo_size;
29421 +
29422 + /** The maximum transfer size supported in bytes.
29423 + * 2047 to 65,535 (default 65,535)
29424 + */
29425 + int32_t max_transfer_size;
29426 +
29427 + /** The maximum number of packets in a transfer.
29428 + * 15 to 511 (default 511)
29429 + */
29430 + int32_t max_packet_count;
29431 +
29432 + /** The number of host channel registers to use.
29433 + * 1 to 16 (default 12)
29434 + * Note: The FPGA configuration supports a maximum of 12 host channels.
29435 + */
29436 + int32_t host_channels;
29437 +
29438 + /** The number of endpoints in addition to EP0 available for device
29439 + * mode operations.
29440 + * 1 to 15 (default 6 IN and OUT)
29441 + * Note: The FPGA configuration supports a maximum of 6 IN and OUT
29442 + * endpoints in addition to EP0.
29443 + */
29444 + int32_t dev_endpoints;
29445 +
29446 + /**
29447 + * Specifies the type of PHY interface to use. By default, the driver
29448 + * will automatically detect the phy_type.
29449 + *
29450 + * 0 - Full Speed PHY
29451 + * 1 - UTMI+ (default)
29452 + * 2 - ULPI
29453 + */
29454 + int32_t phy_type;
29455 +
29456 + /**
29457 + * Specifies the UTMI+ Data Width. This parameter is
29458 + * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
29459 + * PHY_TYPE, this parameter indicates the data width between
29460 + * the MAC and the ULPI Wrapper.) Also, this parameter is
29461 + * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
29462 + * to "8 and 16 bits", meaning that the core has been
29463 + * configured to work at either data path width.
29464 + *
29465 + * 8 or 16 bits (default 16)
29466 + */
29467 + int32_t phy_utmi_width;
29468 +
29469 + /**
29470 + * Specifies whether the ULPI operates at double or single
29471 + * data rate. This parameter is only applicable if PHY_TYPE is
29472 + * ULPI.
29473 + *
29474 + * 0 - single data rate ULPI interface with 8 bit wide data
29475 + * bus (default)
29476 + * 1 - double data rate ULPI interface with 4 bit wide data
29477 + * bus
29478 + */
29479 + int32_t phy_ulpi_ddr;
29480 +
29481 + /**
29482 + * Specifies whether to use the internal or external supply to
29483 + * drive the vbus with a ULPI phy.
29484 + */
29485 + int32_t phy_ulpi_ext_vbus;
29486 +
29487 + /**
29488 + * Specifies whether to use the I2Cinterface for full speed PHY. This
29489 + * parameter is only applicable if PHY_TYPE is FS.
29490 + * 0 - No (default)
29491 + * 1 - Yes
29492 + */
29493 + int32_t i2c_enable;
29494 +
29495 + int32_t ulpi_fs_ls;
29496 +
29497 + int32_t ts_dline;
29498 +
29499 + /**
29500 + * Specifies whether dedicated transmit FIFOs are
29501 + * enabled for non periodic IN endpoints in device mode
29502 + * 0 - No
29503 + * 1 - Yes
29504 + */
29505 + int32_t en_multiple_tx_fifo;
29506 +
29507 + /** Number of 4-byte words in each of the Tx FIFOs in device
29508 + * mode when dynamic FIFO sizing is enabled.
29509 + * 4 to 768 (default 256)
29510 + */
29511 + uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
29512 +
29513 + /** Thresholding enable flag-
29514 + * bit 0 - enable non-ISO Tx thresholding
29515 + * bit 1 - enable ISO Tx thresholding
29516 + * bit 2 - enable Rx thresholding
29517 + */
29518 + uint32_t thr_ctl;
29519 +
29520 + /** Thresholding length for Tx
29521 + * FIFOs in 32 bit DWORDs
29522 + */
29523 + uint32_t tx_thr_length;
29524 +
29525 + /** Thresholding length for Rx
29526 + * FIFOs in 32 bit DWORDs
29527 + */
29528 + uint32_t rx_thr_length;
29529 +
29530 + /**
29531 + * Specifies whether LPM (Link Power Management) support is enabled
29532 + */
29533 + int32_t lpm_enable;
29534 +
29535 + /** Per Transfer Interrupt
29536 + * mode enable flag
29537 + * 1 - Enabled
29538 + * 0 - Disabled
29539 + */
29540 + int32_t pti_enable;
29541 +
29542 + /** Multi Processor Interrupt
29543 + * mode enable flag
29544 + * 1 - Enabled
29545 + * 0 - Disabled
29546 + */
29547 + int32_t mpi_enable;
29548 +
29549 + /** IS_USB Capability
29550 + * 1 - Enabled
29551 + * 0 - Disabled
29552 + */
29553 + int32_t ic_usb_cap;
29554 +
29555 + /** AHB Threshold Ratio
29556 + * 2'b00 AHB Threshold = MAC Threshold
29557 + * 2'b01 AHB Threshold = 1/2 MAC Threshold
29558 + * 2'b10 AHB Threshold = 1/4 MAC Threshold
29559 + * 2'b11 AHB Threshold = 1/8 MAC Threshold
29560 + */
29561 + int32_t ahb_thr_ratio;
29562 +
29563 + /** ADP Support
29564 + * 1 - Enabled
29565 + * 0 - Disabled
29566 + */
29567 + int32_t adp_supp_enable;
29568 +
29569 + /** HFIR Reload Control
29570 + * 0 - The HFIR cannot be reloaded dynamically.
29571 + * 1 - Allow dynamic reloading of the HFIR register during runtime.
29572 + */
29573 + int32_t reload_ctl;
29574 +
29575 + /** DCFG: Enable device Out NAK
29576 + * 0 - The core does not set NAK after Bulk Out transfer complete.
29577 + * 1 - The core sets NAK after Bulk OUT transfer complete.
29578 + */
29579 + int32_t dev_out_nak;
29580 +
29581 + /** DCFG: Enable Continue on BNA
29582 + * After receiving BNA interrupt the core disables the endpoint,when the
29583 + * endpoint is re-enabled by the application the core starts processing
29584 + * 0 - from the DOEPDMA descriptor
29585 + * 1 - from the descriptor which received the BNA.
29586 + */
29587 + int32_t cont_on_bna;
29588 +
29589 + /** GAHBCFG: AHB Single Support
29590 + * This bit when programmed supports SINGLE transfers for remainder
29591 + * data in a transfer for DMA mode of operation.
29592 + * 0 - in this case the remainder data will be sent using INCR burst size.
29593 + * 1 - in this case the remainder data will be sent using SINGLE burst size.
29594 + */
29595 + int32_t ahb_single;
29596 +
29597 + /** Core Power down mode
29598 + * 0 - No Power Down is enabled
29599 + * 1 - Reserved
29600 + * 2 - Complete Power Down (Hibernation)
29601 + */
29602 + int32_t power_down;
29603 +
29604 + /** OTG revision supported
29605 + * 0 - OTG 1.3 revision
29606 + * 1 - OTG 2.0 revision
29607 + */
29608 + int32_t otg_ver;
29609 +
29610 +} dwc_otg_core_params_t;
29611 +
29612 +#ifdef DEBUG
29613 +struct dwc_otg_core_if;
29614 +typedef struct hc_xfer_info {
29615 + struct dwc_otg_core_if *core_if;
29616 + dwc_hc_t *hc;
29617 +} hc_xfer_info_t;
29618 +#endif
29619 +
29620 +typedef struct ep_xfer_info {
29621 + struct dwc_otg_core_if *core_if;
29622 + dwc_ep_t *ep;
29623 + uint8_t state;
29624 +} ep_xfer_info_t;
29625 +/*
29626 + * Device States
29627 + */
29628 +typedef enum dwc_otg_lx_state {
29629 + /** On state */
29630 + DWC_OTG_L0,
29631 + /** LPM sleep state*/
29632 + DWC_OTG_L1,
29633 + /** USB suspend state*/
29634 + DWC_OTG_L2,
29635 + /** Off state*/
29636 + DWC_OTG_L3
29637 +} dwc_otg_lx_state_e;
29638 +
29639 +struct dwc_otg_global_regs_backup {
29640 + uint32_t gotgctl_local;
29641 + uint32_t gintmsk_local;
29642 + uint32_t gahbcfg_local;
29643 + uint32_t gusbcfg_local;
29644 + uint32_t grxfsiz_local;
29645 + uint32_t gnptxfsiz_local;
29646 +#ifdef CONFIG_USB_DWC_OTG_LPM
29647 + uint32_t glpmcfg_local;
29648 +#endif
29649 + uint32_t gi2cctl_local;
29650 + uint32_t hptxfsiz_local;
29651 + uint32_t pcgcctl_local;
29652 + uint32_t gdfifocfg_local;
29653 + uint32_t dtxfsiz_local[MAX_EPS_CHANNELS];
29654 + uint32_t gpwrdn_local;
29655 + uint32_t xhib_pcgcctl;
29656 + uint32_t xhib_gpwrdn;
29657 +};
29658 +
29659 +struct dwc_otg_host_regs_backup {
29660 + uint32_t hcfg_local;
29661 + uint32_t haintmsk_local;
29662 + uint32_t hcintmsk_local[MAX_EPS_CHANNELS];
29663 + uint32_t hprt0_local;
29664 + uint32_t hfir_local;
29665 +};
29666 +
29667 +struct dwc_otg_dev_regs_backup {
29668 + uint32_t dcfg;
29669 + uint32_t dctl;
29670 + uint32_t daintmsk;
29671 + uint32_t diepmsk;
29672 + uint32_t doepmsk;
29673 + uint32_t diepctl[MAX_EPS_CHANNELS];
29674 + uint32_t dieptsiz[MAX_EPS_CHANNELS];
29675 + uint32_t diepdma[MAX_EPS_CHANNELS];
29676 +};
29677 +/**
29678 + * The <code>dwc_otg_core_if</code> structure contains information needed to manage
29679 + * the DWC_otg controller acting in either host or device mode. It
29680 + * represents the programming view of the controller as a whole.
29681 + */
29682 +struct dwc_otg_core_if {
29683 + /** Parameters that define how the core should be configured.*/
29684 + dwc_otg_core_params_t *core_params;
29685 +
29686 + /** Core Global registers starting at offset 000h. */
29687 + dwc_otg_core_global_regs_t *core_global_regs;
29688 +
29689 + /** Device-specific information */
29690 + dwc_otg_dev_if_t *dev_if;
29691 + /** Host-specific information */
29692 + dwc_otg_host_if_t *host_if;
29693 +
29694 + /** Value from SNPSID register */
29695 + uint32_t snpsid;
29696 +
29697 + /*
29698 + * Set to 1 if the core PHY interface bits in USBCFG have been
29699 + * initialized.
29700 + */
29701 + uint8_t phy_init_done;
29702 +
29703 + /*
29704 + * SRP Success flag, set by srp success interrupt in FS I2C mode
29705 + */
29706 + uint8_t srp_success;
29707 + uint8_t srp_timer_started;
29708 + /** Timer for SRP. If it expires before SRP is successful
29709 + * clear the SRP. */
29710 + dwc_timer_t *srp_timer;
29711 +
29712 +#ifdef DWC_DEV_SRPCAP
29713 + /* This timer is needed to power on the hibernated host core if SRP is not
29714 + * initiated on connected SRP capable device for limited period of time
29715 + */
29716 + uint8_t pwron_timer_started;
29717 + dwc_timer_t *pwron_timer;
29718 +#endif
29719 + /* Common configuration information */
29720 + /** Power and Clock Gating Control Register */
29721 + volatile uint32_t *pcgcctl;
29722 +#define DWC_OTG_PCGCCTL_OFFSET 0xE00
29723 +
29724 + /** Push/pop addresses for endpoints or host channels.*/
29725 + uint32_t *data_fifo[MAX_EPS_CHANNELS];
29726 +#define DWC_OTG_DATA_FIFO_OFFSET 0x1000
29727 +#define DWC_OTG_DATA_FIFO_SIZE 0x1000
29728 +
29729 + /** Total RAM for FIFOs (Bytes) */
29730 + uint16_t total_fifo_size;
29731 + /** Size of Rx FIFO (Bytes) */
29732 + uint16_t rx_fifo_size;
29733 + /** Size of Non-periodic Tx FIFO (Bytes) */
29734 + uint16_t nperio_tx_fifo_size;
29735 +
29736 + /** 1 if DMA is enabled, 0 otherwise. */
29737 + uint8_t dma_enable;
29738 +
29739 + /** 1 if DMA descriptor is enabled, 0 otherwise. */
29740 + uint8_t dma_desc_enable;
29741 +
29742 + /** 1 if PTI Enhancement mode is enabled, 0 otherwise. */
29743 + uint8_t pti_enh_enable;
29744 +
29745 + /** 1 if MPI Enhancement mode is enabled, 0 otherwise. */
29746 + uint8_t multiproc_int_enable;
29747 +
29748 + /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
29749 + uint8_t en_multiple_tx_fifo;
29750 +
29751 + /** Set to 1 if multiple packets of a high-bandwidth transfer is in
29752 + * process of being queued */
29753 + uint8_t queuing_high_bandwidth;
29754 +
29755 + /** Hardware Configuration -- stored here for convenience.*/
29756 + hwcfg1_data_t hwcfg1;
29757 + hwcfg2_data_t hwcfg2;
29758 + hwcfg3_data_t hwcfg3;
29759 + hwcfg4_data_t hwcfg4;
29760 + fifosize_data_t hptxfsiz;
29761 +
29762 + /** Host and Device Configuration -- stored here for convenience.*/
29763 + hcfg_data_t hcfg;
29764 + dcfg_data_t dcfg;
29765 +
29766 + /** The operational State, during transations
29767 + * (a_host>>a_peripherial and b_device=>b_host) this may not
29768 + * match the core but allows the software to determine
29769 + * transitions.
29770 + */
29771 + uint8_t op_state;
29772 +
29773 + /**
29774 + * Set to 1 if the HCD needs to be restarted on a session request
29775 + * interrupt. This is required if no connector ID status change has
29776 + * occurred since the HCD was last disconnected.
29777 + */
29778 + uint8_t restart_hcd_on_session_req;
29779 +
29780 + /** HCD callbacks */
29781 + /** A-Device is a_host */
29782 +#define A_HOST (1)
29783 + /** A-Device is a_suspend */
29784 +#define A_SUSPEND (2)
29785 + /** A-Device is a_peripherial */
29786 +#define A_PERIPHERAL (3)
29787 + /** B-Device is operating as a Peripheral. */
29788 +#define B_PERIPHERAL (4)
29789 + /** B-Device is operating as a Host. */
29790 +#define B_HOST (5)
29791 +
29792 + /** HCD callbacks */
29793 + struct dwc_otg_cil_callbacks *hcd_cb;
29794 + /** PCD callbacks */
29795 + struct dwc_otg_cil_callbacks *pcd_cb;
29796 +
29797 + /** Device mode Periodic Tx FIFO Mask */
29798 + uint32_t p_tx_msk;
29799 + /** Device mode Periodic Tx FIFO Mask */
29800 + uint32_t tx_msk;
29801 +
29802 + /** Workqueue object used for handling several interrupts */
29803 + dwc_workq_t *wq_otg;
29804 +
29805 + /** Timer object used for handling "Wakeup Detected" Interrupt */
29806 + dwc_timer_t *wkp_timer;
29807 + /** This arrays used for debug purposes for DEV OUT NAK enhancement */
29808 + uint32_t start_doeptsiz_val[MAX_EPS_CHANNELS];
29809 + ep_xfer_info_t ep_xfer_info[MAX_EPS_CHANNELS];
29810 + dwc_timer_t *ep_xfer_timer[MAX_EPS_CHANNELS];
29811 +#ifdef DEBUG
29812 + uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
29813 +
29814 + hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
29815 + dwc_timer_t *hc_xfer_timer[MAX_EPS_CHANNELS];
29816 +
29817 + uint32_t hfnum_7_samples;
29818 + uint64_t hfnum_7_frrem_accum;
29819 + uint32_t hfnum_0_samples;
29820 + uint64_t hfnum_0_frrem_accum;
29821 + uint32_t hfnum_other_samples;
29822 + uint64_t hfnum_other_frrem_accum;
29823 +#endif
29824 +
29825 +#ifdef DWC_UTE_CFI
29826 + uint16_t pwron_rxfsiz;
29827 + uint16_t pwron_gnptxfsiz;
29828 + uint16_t pwron_txfsiz[15];
29829 +
29830 + uint16_t init_rxfsiz;
29831 + uint16_t init_gnptxfsiz;
29832 + uint16_t init_txfsiz[15];
29833 +#endif
29834 +
29835 + /** Lx state of device */
29836 + dwc_otg_lx_state_e lx_state;
29837 +
29838 + /** Saved Core Global registers */
29839 + struct dwc_otg_global_regs_backup *gr_backup;
29840 + /** Saved Host registers */
29841 + struct dwc_otg_host_regs_backup *hr_backup;
29842 + /** Saved Device registers */
29843 + struct dwc_otg_dev_regs_backup *dr_backup;
29844 +
29845 + /** Power Down Enable */
29846 + uint32_t power_down;
29847 +
29848 + /** ADP support Enable */
29849 + uint32_t adp_enable;
29850 +
29851 + /** ADP structure object */
29852 + dwc_otg_adp_t adp;
29853 +
29854 + /** hibernation/suspend flag */
29855 + int hibernation_suspend;
29856 +
29857 + /** Device mode extended hibernation flag */
29858 + int xhib;
29859 +
29860 + /** OTG revision supported */
29861 + uint32_t otg_ver;
29862 +
29863 + /** OTG status flag used for HNP polling */
29864 + uint8_t otg_sts;
29865 +
29866 + /** Pointer to either hcd->lock or pcd->lock */
29867 + dwc_spinlock_t *lock;
29868 +
29869 + /** Start predict NextEP based on Learning Queue if equal 1,
29870 + * also used as counter of disabled NP IN EP's */
29871 + uint8_t start_predict;
29872 +
29873 + /** NextEp sequence, including EP0: nextep_seq[] = EP if non-periodic and
29874 + * active, 0xff otherwise */
29875 + uint8_t nextep_seq[MAX_EPS_CHANNELS];
29876 +
29877 + /** Index of fisrt EP in nextep_seq array which should be re-enabled **/
29878 + uint8_t first_in_nextep_seq;
29879 +
29880 + /** Frame number while entering to ISR - needed for ISOCs **/
29881 + uint32_t frame_num;
29882 +
29883 +};
29884 +
29885 +#ifdef DEBUG
29886 +/*
29887 + * This function is called when transfer is timed out.
29888 + */
29889 +extern void hc_xfer_timeout(void *ptr);
29890 +#endif
29891 +
29892 +/*
29893 + * This function is called when transfer is timed out on endpoint.
29894 + */
29895 +extern void ep_xfer_timeout(void *ptr);
29896 +
29897 +/*
29898 + * The following functions are functions for works
29899 + * using during handling some interrupts
29900 + */
29901 +extern void w_conn_id_status_change(void *p);
29902 +
29903 +extern void w_wakeup_detected(void *p);
29904 +
29905 +/** Saves global register values into system memory. */
29906 +extern int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if);
29907 +/** Saves device register values into system memory. */
29908 +extern int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if);
29909 +/** Saves host register values into system memory. */
29910 +extern int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if);
29911 +/** Restore global register values. */
29912 +extern int dwc_otg_restore_global_regs(dwc_otg_core_if_t * core_if);
29913 +/** Restore host register values. */
29914 +extern int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset);
29915 +/** Restore device register values. */
29916 +extern int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if,
29917 + int rem_wakeup);
29918 +extern int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if);
29919 +extern int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode,
29920 + int is_host);
29921 +
29922 +extern int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,
29923 + int restore_mode, int reset);
29924 +extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
29925 + int rem_wakeup, int reset);
29926 +
29927 +/*
29928 + * The following functions support initialization of the CIL driver component
29929 + * and the DWC_otg controller.
29930 + */
29931 +extern void dwc_otg_core_host_init(dwc_otg_core_if_t * _core_if);
29932 +extern void dwc_otg_core_dev_init(dwc_otg_core_if_t * _core_if);
29933 +
29934 +/** @name Device CIL Functions
29935 + * The following functions support managing the DWC_otg controller in device
29936 + * mode.
29937 + */
29938 +/**@{*/
29939 +extern void dwc_otg_wakeup(dwc_otg_core_if_t * _core_if);
29940 +extern void dwc_otg_read_setup_packet(dwc_otg_core_if_t * _core_if,
29941 + uint32_t * _dest);
29942 +extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * _core_if);
29943 +extern void dwc_otg_ep0_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
29944 +extern void dwc_otg_ep_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
29945 +extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
29946 +extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * _core_if,
29947 + dwc_ep_t * _ep);
29948 +extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * _core_if,
29949 + dwc_ep_t * _ep);
29950 +extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * _core_if,
29951 + dwc_ep_t * _ep);
29952 +extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * _core_if,
29953 + dwc_ep_t * _ep);
29954 +extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t * _core_if,
29955 + dwc_ep_t * _ep, int _dma);
29956 +extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
29957 +extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * _core_if,
29958 + dwc_ep_t * _ep);
29959 +extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * _core_if);
29960 +
29961 +#ifdef DWC_EN_ISOC
29962 +extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
29963 + dwc_ep_t * ep);
29964 +extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
29965 + dwc_ep_t * ep);
29966 +#endif /* DWC_EN_ISOC */
29967 +/**@}*/
29968 +
29969 +/** @name Host CIL Functions
29970 + * The following functions support managing the DWC_otg controller in host
29971 + * mode.
29972 + */
29973 +/**@{*/
29974 +extern void dwc_otg_hc_init(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
29975 +extern void dwc_otg_hc_halt(dwc_otg_core_if_t * _core_if,
29976 + dwc_hc_t * _hc, dwc_otg_halt_status_e _halt_status);
29977 +extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
29978 +extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * _core_if,
29979 + dwc_hc_t * _hc);
29980 +extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * _core_if,
29981 + dwc_hc_t * _hc);
29982 +extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
29983 +extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t * _core_if,
29984 + dwc_hc_t * _hc);
29985 +extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * _core_if);
29986 +extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * _core_if);
29987 +
29988 +extern void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if,
29989 + dwc_hc_t * hc);
29990 +
29991 +extern uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if);
29992 +
29993 +/* Macro used to clear one channel interrupt */
29994 +#define clear_hc_int(_hc_regs_, _intr_) \
29995 +do { \
29996 + hcint_data_t hcint_clear = {.d32 = 0}; \
29997 + hcint_clear.b._intr_ = 1; \
29998 + DWC_WRITE_REG32(&(_hc_regs_)->hcint, hcint_clear.d32); \
29999 +} while (0)
30000 +
30001 +/*
30002 + * Macro used to disable one channel interrupt. Channel interrupts are
30003 + * disabled when the channel is halted or released by the interrupt handler.
30004 + * There is no need to handle further interrupts of that type until the
30005 + * channel is re-assigned. In fact, subsequent handling may cause crashes
30006 + * because the channel structures are cleaned up when the channel is released.
30007 + */
30008 +#define disable_hc_int(_hc_regs_, _intr_) \
30009 +do { \
30010 + hcintmsk_data_t hcintmsk = {.d32 = 0}; \
30011 + hcintmsk.b._intr_ = 1; \
30012 + DWC_MODIFY_REG32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
30013 +} while (0)
30014 +
30015 +/**
30016 + * This function Reads HPRT0 in preparation to modify. It keeps the
30017 + * WC bits 0 so that if they are read as 1, they won't clear when you
30018 + * write it back
30019 + */
30020 +static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t * _core_if)
30021 +{
30022 + hprt0_data_t hprt0;
30023 + hprt0.d32 = DWC_READ_REG32(_core_if->host_if->hprt0);
30024 + hprt0.b.prtena = 0;
30025 + hprt0.b.prtconndet = 0;
30026 + hprt0.b.prtenchng = 0;
30027 + hprt0.b.prtovrcurrchng = 0;
30028 + return hprt0.d32;
30029 +}
30030 +
30031 +/**@}*/
30032 +
30033 +/** @name Common CIL Functions
30034 + * The following functions support managing the DWC_otg controller in either
30035 + * device or host mode.
30036 + */
30037 +/**@{*/
30038 +
30039 +extern void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
30040 + uint8_t * dest, uint16_t bytes);
30041 +
30042 +extern void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * _core_if, const int _num);
30043 +extern void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * _core_if);
30044 +extern void dwc_otg_core_reset(dwc_otg_core_if_t * _core_if);
30045 +
30046 +/**
30047 + * This function returns the Core Interrupt register.
30048 + */
30049 +static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t * core_if)
30050 +{
30051 + return (DWC_READ_REG32(&core_if->core_global_regs->gintsts) &
30052 + DWC_READ_REG32(&core_if->core_global_regs->gintmsk));
30053 +}
30054 +
30055 +/**
30056 + * This function returns the OTG Interrupt register.
30057 + */
30058 +static inline uint32_t dwc_otg_read_otg_intr(dwc_otg_core_if_t * core_if)
30059 +{
30060 + return (DWC_READ_REG32(&core_if->core_global_regs->gotgint));
30061 +}
30062 +
30063 +/**
30064 + * This function reads the Device All Endpoints Interrupt register and
30065 + * returns the IN endpoint interrupt bits.
30066 + */
30067 +static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *
30068 + core_if)
30069 +{
30070 +
30071 + uint32_t v;
30072 +
30073 + if (core_if->multiproc_int_enable) {
30074 + v = DWC_READ_REG32(&core_if->dev_if->
30075 + dev_global_regs->deachint) &
30076 + DWC_READ_REG32(&core_if->
30077 + dev_if->dev_global_regs->deachintmsk);
30078 + } else {
30079 + v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &
30080 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
30081 + }
30082 + return (v & 0xffff);
30083 +}
30084 +
30085 +/**
30086 + * This function reads the Device All Endpoints Interrupt register and
30087 + * returns the OUT endpoint interrupt bits.
30088 + */
30089 +static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *
30090 + core_if)
30091 +{
30092 + uint32_t v;
30093 +
30094 + if (core_if->multiproc_int_enable) {
30095 + v = DWC_READ_REG32(&core_if->dev_if->
30096 + dev_global_regs->deachint) &
30097 + DWC_READ_REG32(&core_if->
30098 + dev_if->dev_global_regs->deachintmsk);
30099 + } else {
30100 + v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &
30101 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
30102 + }
30103 +
30104 + return ((v & 0xffff0000) >> 16);
30105 +}
30106 +
30107 +/**
30108 + * This function returns the Device IN EP Interrupt register
30109 + */
30110 +static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t * core_if,
30111 + dwc_ep_t * ep)
30112 +{
30113 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
30114 + uint32_t v, msk, emp;
30115 +
30116 + if (core_if->multiproc_int_enable) {
30117 + msk =
30118 + DWC_READ_REG32(&dev_if->
30119 + dev_global_regs->diepeachintmsk[ep->num]);
30120 + emp =
30121 + DWC_READ_REG32(&dev_if->
30122 + dev_global_regs->dtknqr4_fifoemptymsk);
30123 + msk |= ((emp >> ep->num) & 0x1) << 7;
30124 + v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
30125 + } else {
30126 + msk = DWC_READ_REG32(&dev_if->dev_global_regs->diepmsk);
30127 + emp =
30128 + DWC_READ_REG32(&dev_if->
30129 + dev_global_regs->dtknqr4_fifoemptymsk);
30130 + msk |= ((emp >> ep->num) & 0x1) << 7;
30131 + v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
30132 + }
30133 +
30134 + return v;
30135 +}
30136 +
30137 +/**
30138 + * This function returns the Device OUT EP Interrupt register
30139 + */
30140 +static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *
30141 + _core_if, dwc_ep_t * _ep)
30142 +{
30143 + dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
30144 + uint32_t v;
30145 + doepmsk_data_t msk = {.d32 = 0 };
30146 +
30147 + if (_core_if->multiproc_int_enable) {
30148 + msk.d32 =
30149 + DWC_READ_REG32(&dev_if->
30150 + dev_global_regs->doepeachintmsk[_ep->num]);
30151 + if (_core_if->pti_enh_enable) {
30152 + msk.b.pktdrpsts = 1;
30153 + }
30154 + v = DWC_READ_REG32(&dev_if->
30155 + out_ep_regs[_ep->num]->doepint) & msk.d32;
30156 + } else {
30157 + msk.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->doepmsk);
30158 + if (_core_if->pti_enh_enable) {
30159 + msk.b.pktdrpsts = 1;
30160 + }
30161 + v = DWC_READ_REG32(&dev_if->
30162 + out_ep_regs[_ep->num]->doepint) & msk.d32;
30163 + }
30164 + return v;
30165 +}
30166 +
30167 +/**
30168 + * This function returns the Host All Channel Interrupt register
30169 + */
30170 +static inline uint32_t dwc_otg_read_host_all_channels_intr(dwc_otg_core_if_t *
30171 + _core_if)
30172 +{
30173 + return (DWC_READ_REG32(&_core_if->host_if->host_global_regs->haint));
30174 +}
30175 +
30176 +static inline uint32_t dwc_otg_read_host_channel_intr(dwc_otg_core_if_t *
30177 + _core_if, dwc_hc_t * _hc)
30178 +{
30179 + return (DWC_READ_REG32
30180 + (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
30181 +}
30182 +
30183 +/**
30184 + * This function returns the mode of the operation, host or device.
30185 + *
30186 + * @return 0 - Device Mode, 1 - Host Mode
30187 + */
30188 +static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t * _core_if)
30189 +{
30190 + return (DWC_READ_REG32(&_core_if->core_global_regs->gintsts) & 0x1);
30191 +}
30192 +
30193 +/**@}*/
30194 +
30195 +/**
30196 + * DWC_otg CIL callback structure. This structure allows the HCD and
30197 + * PCD to register functions used for starting and stopping the PCD
30198 + * and HCD for role change on for a DRD.
30199 + */
30200 +typedef struct dwc_otg_cil_callbacks {
30201 + /** Start function for role change */
30202 + int (*start) (void *_p);
30203 + /** Stop Function for role change */
30204 + int (*stop) (void *_p);
30205 + /** Disconnect Function for role change */
30206 + int (*disconnect) (void *_p);
30207 + /** Resume/Remote wakeup Function */
30208 + int (*resume_wakeup) (void *_p);
30209 + /** Suspend function */
30210 + int (*suspend) (void *_p);
30211 + /** Session Start (SRP) */
30212 + int (*session_start) (void *_p);
30213 +#ifdef CONFIG_USB_DWC_OTG_LPM
30214 + /** Sleep (switch to L0 state) */
30215 + int (*sleep) (void *_p);
30216 +#endif
30217 + /** Pointer passed to start() and stop() */
30218 + void *p;
30219 +} dwc_otg_cil_callbacks_t;
30220 +
30221 +extern void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * _core_if,
30222 + dwc_otg_cil_callbacks_t * _cb,
30223 + void *_p);
30224 +extern void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * _core_if,
30225 + dwc_otg_cil_callbacks_t * _cb,
30226 + void *_p);
30227 +
30228 +void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if);
30229 +
30230 +//////////////////////////////////////////////////////////////////////
30231 +/** Start the HCD. Helper function for using the HCD callbacks.
30232 + *
30233 + * @param core_if Programming view of DWC_otg controller.
30234 + */
30235 +static inline void cil_hcd_start(dwc_otg_core_if_t * core_if)
30236 +{
30237 + if (core_if->hcd_cb && core_if->hcd_cb->start) {
30238 + core_if->hcd_cb->start(core_if->hcd_cb->p);
30239 + }
30240 +}
30241 +
30242 +/** Stop the HCD. Helper function for using the HCD callbacks.
30243 + *
30244 + * @param core_if Programming view of DWC_otg controller.
30245 + */
30246 +static inline void cil_hcd_stop(dwc_otg_core_if_t * core_if)
30247 +{
30248 + if (core_if->hcd_cb && core_if->hcd_cb->stop) {
30249 + core_if->hcd_cb->stop(core_if->hcd_cb->p);
30250 + }
30251 +}
30252 +
30253 +/** Disconnect the HCD. Helper function for using the HCD callbacks.
30254 + *
30255 + * @param core_if Programming view of DWC_otg controller.
30256 + */
30257 +static inline void cil_hcd_disconnect(dwc_otg_core_if_t * core_if)
30258 +{
30259 + if (core_if->hcd_cb && core_if->hcd_cb->disconnect) {
30260 + core_if->hcd_cb->disconnect(core_if->hcd_cb->p);
30261 + }
30262 +}
30263 +
30264 +/** Inform the HCD the a New Session has begun. Helper function for
30265 + * using the HCD callbacks.
30266 + *
30267 + * @param core_if Programming view of DWC_otg controller.
30268 + */
30269 +static inline void cil_hcd_session_start(dwc_otg_core_if_t * core_if)
30270 +{
30271 + if (core_if->hcd_cb && core_if->hcd_cb->session_start) {
30272 + core_if->hcd_cb->session_start(core_if->hcd_cb->p);
30273 + }
30274 +}
30275 +
30276 +#ifdef CONFIG_USB_DWC_OTG_LPM
30277 +/**
30278 + * Inform the HCD about LPM sleep.
30279 + * Helper function for using the HCD callbacks.
30280 + *
30281 + * @param core_if Programming view of DWC_otg controller.
30282 + */
30283 +static inline void cil_hcd_sleep(dwc_otg_core_if_t * core_if)
30284 +{
30285 + if (core_if->hcd_cb && core_if->hcd_cb->sleep) {
30286 + core_if->hcd_cb->sleep(core_if->hcd_cb->p);
30287 + }
30288 +}
30289 +#endif
30290 +
30291 +/** Resume the HCD. Helper function for using the HCD callbacks.
30292 + *
30293 + * @param core_if Programming view of DWC_otg controller.
30294 + */
30295 +static inline void cil_hcd_resume(dwc_otg_core_if_t * core_if)
30296 +{
30297 + if (core_if->hcd_cb && core_if->hcd_cb->resume_wakeup) {
30298 + core_if->hcd_cb->resume_wakeup(core_if->hcd_cb->p);
30299 + }
30300 +}
30301 +
30302 +/** Start the PCD. Helper function for using the PCD callbacks.
30303 + *
30304 + * @param core_if Programming view of DWC_otg controller.
30305 + */
30306 +static inline void cil_pcd_start(dwc_otg_core_if_t * core_if)
30307 +{
30308 + if (core_if->pcd_cb && core_if->pcd_cb->start) {
30309 + core_if->pcd_cb->start(core_if->pcd_cb->p);
30310 + }
30311 +}
30312 +
30313 +/** Stop the PCD. Helper function for using the PCD callbacks.
30314 + *
30315 + * @param core_if Programming view of DWC_otg controller.
30316 + */
30317 +static inline void cil_pcd_stop(dwc_otg_core_if_t * core_if)
30318 +{
30319 + if (core_if->pcd_cb && core_if->pcd_cb->stop) {
30320 + core_if->pcd_cb->stop(core_if->pcd_cb->p);
30321 + }
30322 +}
30323 +
30324 +/** Suspend the PCD. Helper function for using the PCD callbacks.
30325 + *
30326 + * @param core_if Programming view of DWC_otg controller.
30327 + */
30328 +static inline void cil_pcd_suspend(dwc_otg_core_if_t * core_if)
30329 +{
30330 + if (core_if->pcd_cb && core_if->pcd_cb->suspend) {
30331 + core_if->pcd_cb->suspend(core_if->pcd_cb->p);
30332 + }
30333 +}
30334 +
30335 +/** Resume the PCD. Helper function for using the PCD callbacks.
30336 + *
30337 + * @param core_if Programming view of DWC_otg controller.
30338 + */
30339 +static inline void cil_pcd_resume(dwc_otg_core_if_t * core_if)
30340 +{
30341 + if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
30342 + core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
30343 + }
30344 +}
30345 +
30346 +//////////////////////////////////////////////////////////////////////
30347 +
30348 +#endif
30349 --- /dev/null
30350 +++ b/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c
30351 @@ -0,0 +1,1594 @@
30352 +/* ==========================================================================
30353 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $
30354 + * $Revision: #32 $
30355 + * $Date: 2012/08/10 $
30356 + * $Change: 2047372 $
30357 + *
30358 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
30359 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
30360 + * otherwise expressly agreed to in writing between Synopsys and you.
30361 + *
30362 + * The Software IS NOT an item of Licensed Software or Licensed Product under
30363 + * any End User Software License Agreement or Agreement for Licensed Product
30364 + * with Synopsys or any supplement thereto. You are permitted to use and
30365 + * redistribute this Software in source and binary forms, with or without
30366 + * modification, provided that redistributions of source code must retain this
30367 + * notice. You may not view, use, disclose, copy or distribute this file or
30368 + * any information contained herein except pursuant to this license grant from
30369 + * Synopsys. If you do not agree with this notice, including the disclaimer
30370 + * below, then you are not authorized to use the Software.
30371 + *
30372 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
30373 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30374 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30375 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
30376 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30377 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30378 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
30379 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30380 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30381 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
30382 + * DAMAGE.
30383 + * ========================================================================== */
30384 +
30385 +/** @file
30386 + *
30387 + * The Core Interface Layer provides basic services for accessing and
30388 + * managing the DWC_otg hardware. These services are used by both the
30389 + * Host Controller Driver and the Peripheral Controller Driver.
30390 + *
30391 + * This file contains the Common Interrupt handlers.
30392 + */
30393 +#include "dwc_os.h"
30394 +#include "dwc_otg_regs.h"
30395 +#include "dwc_otg_cil.h"
30396 +#include "dwc_otg_driver.h"
30397 +#include "dwc_otg_pcd.h"
30398 +#include "dwc_otg_hcd.h"
30399 +
30400 +#ifdef DEBUG
30401 +inline const char *op_state_str(dwc_otg_core_if_t * core_if)
30402 +{
30403 + return (core_if->op_state == A_HOST ? "a_host" :
30404 + (core_if->op_state == A_SUSPEND ? "a_suspend" :
30405 + (core_if->op_state == A_PERIPHERAL ? "a_peripheral" :
30406 + (core_if->op_state == B_PERIPHERAL ? "b_peripheral" :
30407 + (core_if->op_state == B_HOST ? "b_host" : "unknown")))));
30408 +}
30409 +#endif
30410 +
30411 +/** This function will log a debug message
30412 + *
30413 + * @param core_if Programming view of DWC_otg controller.
30414 + */
30415 +int32_t dwc_otg_handle_mode_mismatch_intr(dwc_otg_core_if_t * core_if)
30416 +{
30417 + gintsts_data_t gintsts;
30418 + DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
30419 + dwc_otg_mode(core_if) ? "Host" : "Device");
30420 +
30421 + /* Clear interrupt */
30422 + gintsts.d32 = 0;
30423 + gintsts.b.modemismatch = 1;
30424 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
30425 + return 1;
30426 +}
30427 +
30428 +/**
30429 + * This function handles the OTG Interrupts. It reads the OTG
30430 + * Interrupt Register (GOTGINT) to determine what interrupt has
30431 + * occurred.
30432 + *
30433 + * @param core_if Programming view of DWC_otg controller.
30434 + */
30435 +int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t * core_if)
30436 +{
30437 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
30438 + gotgint_data_t gotgint;
30439 + gotgctl_data_t gotgctl;
30440 + gintmsk_data_t gintmsk;
30441 + gpwrdn_data_t gpwrdn;
30442 +
30443 + gotgint.d32 = DWC_READ_REG32(&global_regs->gotgint);
30444 + gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
30445 + DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32,
30446 + op_state_str(core_if));
30447 +
30448 + if (gotgint.b.sesenddet) {
30449 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
30450 + "Session End Detected++ (%s)\n",
30451 + op_state_str(core_if));
30452 + gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
30453 +
30454 + if (core_if->op_state == B_HOST) {
30455 + cil_pcd_start(core_if);
30456 + core_if->op_state = B_PERIPHERAL;
30457 + } else {
30458 + /* If not B_HOST and Device HNP still set. HNP
30459 + * Did not succeed!*/
30460 + if (gotgctl.b.devhnpen) {
30461 + DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
30462 + __DWC_ERROR("Device Not Connected/Responding!\n");
30463 + }
30464 +
30465 + /* If Session End Detected the B-Cable has
30466 + * been disconnected. */
30467 + /* Reset PCD and Gadget driver to a
30468 + * clean state. */
30469 + core_if->lx_state = DWC_OTG_L0;
30470 + DWC_SPINUNLOCK(core_if->lock);
30471 + cil_pcd_stop(core_if);
30472 + DWC_SPINLOCK(core_if->lock);
30473 +
30474 + if (core_if->adp_enable) {
30475 + if (core_if->power_down == 2) {
30476 + gpwrdn.d32 = 0;
30477 + gpwrdn.b.pwrdnswtch = 1;
30478 + DWC_MODIFY_REG32(&core_if->
30479 + core_global_regs->
30480 + gpwrdn, gpwrdn.d32, 0);
30481 + }
30482 +
30483 + gpwrdn.d32 = 0;
30484 + gpwrdn.b.pmuintsel = 1;
30485 + gpwrdn.b.pmuactv = 1;
30486 + DWC_MODIFY_REG32(&core_if->core_global_regs->
30487 + gpwrdn, 0, gpwrdn.d32);
30488 +
30489 + dwc_otg_adp_sense_start(core_if);
30490 + }
30491 + }
30492 +
30493 + gotgctl.d32 = 0;
30494 + gotgctl.b.devhnpen = 1;
30495 + DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
30496 + }
30497 + if (gotgint.b.sesreqsucstschng) {
30498 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
30499 + "Session Reqeust Success Status Change++\n");
30500 + gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
30501 + if (gotgctl.b.sesreqscs) {
30502 +
30503 + if ((core_if->core_params->phy_type ==
30504 + DWC_PHY_TYPE_PARAM_FS) && (core_if->core_params->i2c_enable)) {
30505 + core_if->srp_success = 1;
30506 + } else {
30507 + DWC_SPINUNLOCK(core_if->lock);
30508 + cil_pcd_resume(core_if);
30509 + DWC_SPINLOCK(core_if->lock);
30510 + /* Clear Session Request */
30511 + gotgctl.d32 = 0;
30512 + gotgctl.b.sesreq = 1;
30513 + DWC_MODIFY_REG32(&global_regs->gotgctl,
30514 + gotgctl.d32, 0);
30515 + }
30516 + }
30517 + }
30518 + if (gotgint.b.hstnegsucstschng) {
30519 + /* Print statements during the HNP interrupt handling
30520 + * can cause it to fail.*/
30521 + gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
30522 + /* WA for 3.00a- HW is not setting cur_mode, even sometimes
30523 + * this does not help*/
30524 + if (core_if->snpsid >= OTG_CORE_REV_3_00a)
30525 + dwc_udelay(100);
30526 + if (gotgctl.b.hstnegscs) {
30527 + if (dwc_otg_is_host_mode(core_if)) {
30528 + core_if->op_state = B_HOST;
30529 + /*
30530 + * Need to disable SOF interrupt immediately.
30531 + * When switching from device to host, the PCD
30532 + * interrupt handler won't handle the
30533 + * interrupt if host mode is already set. The
30534 + * HCD interrupt handler won't get called if
30535 + * the HCD state is HALT. This means that the
30536 + * interrupt does not get handled and Linux
30537 + * complains loudly.
30538 + */
30539 + gintmsk.d32 = 0;
30540 + gintmsk.b.sofintr = 1;
30541 + DWC_MODIFY_REG32(&global_regs->gintmsk,
30542 + gintmsk.d32, 0);
30543 + /* Call callback function with spin lock released */
30544 + DWC_SPINUNLOCK(core_if->lock);
30545 + cil_pcd_stop(core_if);
30546 + /*
30547 + * Initialize the Core for Host mode.
30548 + */
30549 + cil_hcd_start(core_if);
30550 + DWC_SPINLOCK(core_if->lock);
30551 + core_if->op_state = B_HOST;
30552 + }
30553 + } else {
30554 + gotgctl.d32 = 0;
30555 + gotgctl.b.hnpreq = 1;
30556 + gotgctl.b.devhnpen = 1;
30557 + DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
30558 + DWC_DEBUGPL(DBG_ANY, "HNP Failed\n");
30559 + __DWC_ERROR("Device Not Connected/Responding\n");
30560 + }
30561 + }
30562 + if (gotgint.b.hstnegdet) {
30563 + /* The disconnect interrupt is set at the same time as
30564 + * Host Negotiation Detected. During the mode
30565 + * switch all interrupts are cleared so the disconnect
30566 + * interrupt handler will not get executed.
30567 + */
30568 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
30569 + "Host Negotiation Detected++ (%s)\n",
30570 + (dwc_otg_is_host_mode(core_if) ? "Host" :
30571 + "Device"));
30572 + if (dwc_otg_is_device_mode(core_if)) {
30573 + DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n",
30574 + core_if->op_state);
30575 + DWC_SPINUNLOCK(core_if->lock);
30576 + cil_hcd_disconnect(core_if);
30577 + cil_pcd_start(core_if);
30578 + DWC_SPINLOCK(core_if->lock);
30579 + core_if->op_state = A_PERIPHERAL;
30580 + } else {
30581 + /*
30582 + * Need to disable SOF interrupt immediately. When
30583 + * switching from device to host, the PCD interrupt
30584 + * handler won't handle the interrupt if host mode is
30585 + * already set. The HCD interrupt handler won't get
30586 + * called if the HCD state is HALT. This means that
30587 + * the interrupt does not get handled and Linux
30588 + * complains loudly.
30589 + */
30590 + gintmsk.d32 = 0;
30591 + gintmsk.b.sofintr = 1;
30592 + DWC_MODIFY_REG32(&global_regs->gintmsk, gintmsk.d32, 0);
30593 + DWC_SPINUNLOCK(core_if->lock);
30594 + cil_pcd_stop(core_if);
30595 + cil_hcd_start(core_if);
30596 + DWC_SPINLOCK(core_if->lock);
30597 + core_if->op_state = A_HOST;
30598 + }
30599 + }
30600 + if (gotgint.b.adevtoutchng) {
30601 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
30602 + "A-Device Timeout Change++\n");
30603 + }
30604 + if (gotgint.b.debdone) {
30605 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " "Debounce Done++\n");
30606 + }
30607 +
30608 + /* Clear GOTGINT */
30609 + DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, gotgint.d32);
30610 +
30611 + return 1;
30612 +}
30613 +
30614 +void w_conn_id_status_change(void *p)
30615 +{
30616 + dwc_otg_core_if_t *core_if = p;
30617 + uint32_t count = 0;
30618 + gotgctl_data_t gotgctl = {.d32 = 0 };
30619 +
30620 + gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
30621 + DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
30622 + DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
30623 +
30624 + /* B-Device connector (Device Mode) */
30625 + if (gotgctl.b.conidsts) {
30626 + /* Wait for switch to device mode. */
30627 + while (!dwc_otg_is_device_mode(core_if)) {
30628 + DWC_PRINTF("Waiting for Peripheral Mode, Mode=%s\n",
30629 + (dwc_otg_is_host_mode(core_if) ? "Host" :
30630 + "Peripheral"));
30631 + dwc_mdelay(100);
30632 + if (++count > 10000)
30633 + break;
30634 + }
30635 + DWC_ASSERT(++count < 10000,
30636 + "Connection id status change timed out");
30637 + core_if->op_state = B_PERIPHERAL;
30638 + dwc_otg_core_init(core_if);
30639 + dwc_otg_enable_global_interrupts(core_if);
30640 + cil_pcd_start(core_if);
30641 + } else {
30642 + /* A-Device connector (Host Mode) */
30643 + while (!dwc_otg_is_host_mode(core_if)) {
30644 + DWC_PRINTF("Waiting for Host Mode, Mode=%s\n",
30645 + (dwc_otg_is_host_mode(core_if) ? "Host" :
30646 + "Peripheral"));
30647 + dwc_mdelay(100);
30648 + if (++count > 10000)
30649 + break;
30650 + }
30651 + DWC_ASSERT(++count < 10000,
30652 + "Connection id status change timed out");
30653 + core_if->op_state = A_HOST;
30654 + /*
30655 + * Initialize the Core for Host mode.
30656 + */
30657 + dwc_otg_core_init(core_if);
30658 + dwc_otg_enable_global_interrupts(core_if);
30659 + cil_hcd_start(core_if);
30660 + }
30661 +}
30662 +
30663 +/**
30664 + * This function handles the Connector ID Status Change Interrupt. It
30665 + * reads the OTG Interrupt Register (GOTCTL) to determine whether this
30666 + * is a Device to Host Mode transition or a Host Mode to Device
30667 + * Transition.
30668 + *
30669 + * This only occurs when the cable is connected/removed from the PHY
30670 + * connector.
30671 + *
30672 + * @param core_if Programming view of DWC_otg controller.
30673 + */
30674 +int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t * core_if)
30675 +{
30676 +
30677 + /*
30678 + * Need to disable SOF interrupt immediately. If switching from device
30679 + * to host, the PCD interrupt handler won't handle the interrupt if
30680 + * host mode is already set. The HCD interrupt handler won't get
30681 + * called if the HCD state is HALT. This means that the interrupt does
30682 + * not get handled and Linux complains loudly.
30683 + */
30684 + gintmsk_data_t gintmsk = {.d32 = 0 };
30685 + gintsts_data_t gintsts = {.d32 = 0 };
30686 +
30687 + gintmsk.b.sofintr = 1;
30688 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
30689 +
30690 + DWC_DEBUGPL(DBG_CIL,
30691 + " ++Connector ID Status Change Interrupt++ (%s)\n",
30692 + (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"));
30693 +
30694 + DWC_SPINUNLOCK(core_if->lock);
30695 +
30696 + /*
30697 + * Need to schedule a work, as there are possible DELAY function calls
30698 + * Release lock before scheduling workq as it holds spinlock during scheduling
30699 + */
30700 +
30701 + DWC_WORKQ_SCHEDULE(core_if->wq_otg, w_conn_id_status_change,
30702 + core_if, "connection id status change");
30703 + DWC_SPINLOCK(core_if->lock);
30704 +
30705 + /* Set flag and clear interrupt */
30706 + gintsts.b.conidstschng = 1;
30707 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
30708 +
30709 + return 1;
30710 +}
30711 +
30712 +/**
30713 + * This interrupt indicates that a device is initiating the Session
30714 + * Request Protocol to request the host to turn on bus power so a new
30715 + * session can begin. The handler responds by turning on bus power. If
30716 + * the DWC_otg controller is in low power mode, the handler brings the
30717 + * controller out of low power mode before turning on bus power.
30718 + *
30719 + * @param core_if Programming view of DWC_otg controller.
30720 + */
30721 +int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t * core_if)
30722 +{
30723 + gintsts_data_t gintsts;
30724 +
30725 +#ifndef DWC_HOST_ONLY
30726 + DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
30727 +
30728 + if (dwc_otg_is_device_mode(core_if)) {
30729 + DWC_PRINTF("SRP: Device mode\n");
30730 + } else {
30731 + hprt0_data_t hprt0;
30732 + DWC_PRINTF("SRP: Host mode\n");
30733 +
30734 + /* Turn on the port power bit. */
30735 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
30736 + hprt0.b.prtpwr = 1;
30737 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
30738 +
30739 + /* Start the Connection timer. So a message can be displayed
30740 + * if connect does not occur within 10 seconds. */
30741 + cil_hcd_session_start(core_if);
30742 + }
30743 +#endif
30744 +
30745 + /* Clear interrupt */
30746 + gintsts.d32 = 0;
30747 + gintsts.b.sessreqintr = 1;
30748 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
30749 +
30750 + return 1;
30751 +}
30752 +
30753 +void w_wakeup_detected(void *p)
30754 +{
30755 + dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) p;
30756 + /*
30757 + * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
30758 + * so that OPT tests pass with all PHYs).
30759 + */
30760 + hprt0_data_t hprt0 = {.d32 = 0 };
30761 +#if 0
30762 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
30763 + /* Restart the Phy Clock */
30764 + pcgcctl.b.stoppclk = 1;
30765 + DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
30766 + dwc_udelay(10);
30767 +#endif //0
30768 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
30769 + DWC_DEBUGPL(DBG_ANY, "Resume: HPRT0=%0x\n", hprt0.d32);
30770 +// dwc_mdelay(70);
30771 + hprt0.b.prtres = 0; /* Resume */
30772 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
30773 + DWC_DEBUGPL(DBG_ANY, "Clear Resume: HPRT0=%0x\n",
30774 + DWC_READ_REG32(core_if->host_if->hprt0));
30775 +
30776 + cil_hcd_resume(core_if);
30777 +
30778 + /** Change to L0 state*/
30779 + core_if->lx_state = DWC_OTG_L0;
30780 +}
30781 +
30782 +/**
30783 + * This interrupt indicates that the DWC_otg controller has detected a
30784 + * resume or remote wakeup sequence. If the DWC_otg controller is in
30785 + * low power mode, the handler must brings the controller out of low
30786 + * power mode. The controller automatically begins resume
30787 + * signaling. The handler schedules a time to stop resume signaling.
30788 + */
30789 +int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
30790 +{
30791 + gintsts_data_t gintsts;
30792 +
30793 + DWC_DEBUGPL(DBG_ANY,
30794 + "++Resume and Remote Wakeup Detected Interrupt++\n");
30795 +
30796 + DWC_PRINTF("%s lxstate = %d\n", __func__, core_if->lx_state);
30797 +
30798 + if (dwc_otg_is_device_mode(core_if)) {
30799 + dctl_data_t dctl = {.d32 = 0 };
30800 + DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
30801 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->
30802 + dsts));
30803 + if (core_if->lx_state == DWC_OTG_L2) {
30804 +#ifdef PARTIAL_POWER_DOWN
30805 + if (core_if->hwcfg4.b.power_optimiz) {
30806 + pcgcctl_data_t power = {.d32 = 0 };
30807 +
30808 + power.d32 = DWC_READ_REG32(core_if->pcgcctl);
30809 + DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n",
30810 + power.d32);
30811 +
30812 + power.b.stoppclk = 0;
30813 + DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
30814 +
30815 + power.b.pwrclmp = 0;
30816 + DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
30817 +
30818 + power.b.rstpdwnmodule = 0;
30819 + DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
30820 + }
30821 +#endif
30822 + /* Clear the Remote Wakeup Signaling */
30823 + dctl.b.rmtwkupsig = 1;
30824 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
30825 + dctl, dctl.d32, 0);
30826 +
30827 + DWC_SPINUNLOCK(core_if->lock);
30828 + if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
30829 + core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
30830 + }
30831 + DWC_SPINLOCK(core_if->lock);
30832 + } else {
30833 + glpmcfg_data_t lpmcfg;
30834 + lpmcfg.d32 =
30835 + DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
30836 + lpmcfg.b.hird_thres &= (~(1 << 4));
30837 + DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg,
30838 + lpmcfg.d32);
30839 + }
30840 + /** Change to L0 state*/
30841 + core_if->lx_state = DWC_OTG_L0;
30842 + } else {
30843 + if (core_if->lx_state != DWC_OTG_L1) {
30844 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
30845 +
30846 + /* Restart the Phy Clock */
30847 + pcgcctl.b.stoppclk = 1;
30848 + DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
30849 + DWC_TIMER_SCHEDULE(core_if->wkp_timer, 71);
30850 + } else {
30851 + /** Change to L0 state*/
30852 + core_if->lx_state = DWC_OTG_L0;
30853 + }
30854 + }
30855 +
30856 + /* Clear interrupt */
30857 + gintsts.d32 = 0;
30858 + gintsts.b.wkupintr = 1;
30859 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
30860 +
30861 + return 1;
30862 +}
30863 +
30864 +/**
30865 + * This interrupt indicates that the Wakeup Logic has detected a
30866 + * Device disconnect.
30867 + */
30868 +static int32_t dwc_otg_handle_pwrdn_disconnect_intr(dwc_otg_core_if_t *core_if)
30869 +{
30870 + gpwrdn_data_t gpwrdn = { .d32 = 0 };
30871 + gpwrdn_data_t gpwrdn_temp = { .d32 = 0 };
30872 + gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
30873 +
30874 + DWC_PRINTF("%s called\n", __FUNCTION__);
30875 +
30876 + if (!core_if->hibernation_suspend) {
30877 + DWC_PRINTF("Already exited from Hibernation\n");
30878 + return 1;
30879 + }
30880 +
30881 + /* Switch on the voltage to the core */
30882 + gpwrdn.b.pwrdnswtch = 1;
30883 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30884 + dwc_udelay(10);
30885 +
30886 + /* Reset the core */
30887 + gpwrdn.d32 = 0;
30888 + gpwrdn.b.pwrdnrstn = 1;
30889 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30890 + dwc_udelay(10);
30891 +
30892 + /* Disable power clamps*/
30893 + gpwrdn.d32 = 0;
30894 + gpwrdn.b.pwrdnclmp = 1;
30895 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30896 +
30897 + /* Remove reset the core signal */
30898 + gpwrdn.d32 = 0;
30899 + gpwrdn.b.pwrdnrstn = 1;
30900 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
30901 + dwc_udelay(10);
30902 +
30903 + /* Disable PMU interrupt */
30904 + gpwrdn.d32 = 0;
30905 + gpwrdn.b.pmuintsel = 1;
30906 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30907 +
30908 + core_if->hibernation_suspend = 0;
30909 +
30910 + /* Disable PMU */
30911 + gpwrdn.d32 = 0;
30912 + gpwrdn.b.pmuactv = 1;
30913 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30914 + dwc_udelay(10);
30915 +
30916 + if (gpwrdn_temp.b.idsts) {
30917 + core_if->op_state = B_PERIPHERAL;
30918 + dwc_otg_core_init(core_if);
30919 + dwc_otg_enable_global_interrupts(core_if);
30920 + cil_pcd_start(core_if);
30921 + } else {
30922 + core_if->op_state = A_HOST;
30923 + dwc_otg_core_init(core_if);
30924 + dwc_otg_enable_global_interrupts(core_if);
30925 + cil_hcd_start(core_if);
30926 + }
30927 +
30928 + return 1;
30929 +}
30930 +
30931 +/**
30932 + * This interrupt indicates that the Wakeup Logic has detected a
30933 + * remote wakeup sequence.
30934 + */
30935 +static int32_t dwc_otg_handle_pwrdn_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
30936 +{
30937 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
30938 + DWC_DEBUGPL(DBG_ANY,
30939 + "++Powerdown Remote Wakeup Detected Interrupt++\n");
30940 +
30941 + if (!core_if->hibernation_suspend) {
30942 + DWC_PRINTF("Already exited from Hibernation\n");
30943 + return 1;
30944 + }
30945 +
30946 + gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
30947 + if (gpwrdn.b.idsts) { // Device Mode
30948 + if ((core_if->power_down == 2)
30949 + && (core_if->hibernation_suspend == 1)) {
30950 + dwc_otg_device_hibernation_restore(core_if, 0, 0);
30951 + }
30952 + } else {
30953 + if ((core_if->power_down == 2)
30954 + && (core_if->hibernation_suspend == 1)) {
30955 + dwc_otg_host_hibernation_restore(core_if, 1, 0);
30956 + }
30957 + }
30958 + return 1;
30959 +}
30960 +
30961 +static int32_t dwc_otg_handle_pwrdn_idsts_change(dwc_otg_device_t *otg_dev)
30962 +{
30963 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
30964 + gpwrdn_data_t gpwrdn_temp = {.d32 = 0 };
30965 + dwc_otg_core_if_t *core_if = otg_dev->core_if;
30966 +
30967 + DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
30968 + gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
30969 + if (core_if->power_down == 2) {
30970 + if (!core_if->hibernation_suspend) {
30971 + DWC_PRINTF("Already exited from Hibernation\n");
30972 + return 1;
30973 + }
30974 + DWC_DEBUGPL(DBG_ANY, "Exit from hibernation on ID sts change\n");
30975 + /* Switch on the voltage to the core */
30976 + gpwrdn.b.pwrdnswtch = 1;
30977 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30978 + dwc_udelay(10);
30979 +
30980 + /* Reset the core */
30981 + gpwrdn.d32 = 0;
30982 + gpwrdn.b.pwrdnrstn = 1;
30983 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30984 + dwc_udelay(10);
30985 +
30986 + /* Disable power clamps */
30987 + gpwrdn.d32 = 0;
30988 + gpwrdn.b.pwrdnclmp = 1;
30989 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30990 +
30991 + /* Remove reset the core signal */
30992 + gpwrdn.d32 = 0;
30993 + gpwrdn.b.pwrdnrstn = 1;
30994 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
30995 + dwc_udelay(10);
30996 +
30997 + /* Disable PMU interrupt */
30998 + gpwrdn.d32 = 0;
30999 + gpwrdn.b.pmuintsel = 1;
31000 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31001 +
31002 + /*Indicates that we are exiting from hibernation */
31003 + core_if->hibernation_suspend = 0;
31004 +
31005 + /* Disable PMU */
31006 + gpwrdn.d32 = 0;
31007 + gpwrdn.b.pmuactv = 1;
31008 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31009 + dwc_udelay(10);
31010 +
31011 + gpwrdn.d32 = core_if->gr_backup->gpwrdn_local;
31012 + if (gpwrdn.b.dis_vbus == 1) {
31013 + gpwrdn.d32 = 0;
31014 + gpwrdn.b.dis_vbus = 1;
31015 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31016 + }
31017 +
31018 + if (gpwrdn_temp.b.idsts) {
31019 + core_if->op_state = B_PERIPHERAL;
31020 + dwc_otg_core_init(core_if);
31021 + dwc_otg_enable_global_interrupts(core_if);
31022 + cil_pcd_start(core_if);
31023 + } else {
31024 + core_if->op_state = A_HOST;
31025 + dwc_otg_core_init(core_if);
31026 + dwc_otg_enable_global_interrupts(core_if);
31027 + cil_hcd_start(core_if);
31028 + }
31029 + }
31030 +
31031 + if (core_if->adp_enable) {
31032 + uint8_t is_host = 0;
31033 + DWC_SPINUNLOCK(core_if->lock);
31034 + /* Change the core_if's lock to hcd/pcd lock depend on mode? */
31035 +#ifndef DWC_HOST_ONLY
31036 + if (gpwrdn_temp.b.idsts)
31037 + core_if->lock = otg_dev->pcd->lock;
31038 +#endif
31039 +#ifndef DWC_DEVICE_ONLY
31040 + if (!gpwrdn_temp.b.idsts) {
31041 + core_if->lock = otg_dev->hcd->lock;
31042 + is_host = 1;
31043 + }
31044 +#endif
31045 + DWC_PRINTF("RESTART ADP\n");
31046 + if (core_if->adp.probe_enabled)
31047 + dwc_otg_adp_probe_stop(core_if);
31048 + if (core_if->adp.sense_enabled)
31049 + dwc_otg_adp_sense_stop(core_if);
31050 + if (core_if->adp.sense_timer_started)
31051 + DWC_TIMER_CANCEL(core_if->adp.sense_timer);
31052 + if (core_if->adp.vbuson_timer_started)
31053 + DWC_TIMER_CANCEL(core_if->adp.vbuson_timer);
31054 + core_if->adp.probe_timer_values[0] = -1;
31055 + core_if->adp.probe_timer_values[1] = -1;
31056 + core_if->adp.sense_timer_started = 0;
31057 + core_if->adp.vbuson_timer_started = 0;
31058 + core_if->adp.probe_counter = 0;
31059 + core_if->adp.gpwrdn = 0;
31060 +
31061 + /* Disable PMU and restart ADP */
31062 + gpwrdn_temp.d32 = 0;
31063 + gpwrdn_temp.b.pmuactv = 1;
31064 + gpwrdn_temp.b.pmuintsel = 1;
31065 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31066 + DWC_PRINTF("Check point 1\n");
31067 + dwc_mdelay(110);
31068 + dwc_otg_adp_start(core_if, is_host);
31069 + DWC_SPINLOCK(core_if->lock);
31070 + }
31071 +
31072 +
31073 + return 1;
31074 +}
31075 +
31076 +static int32_t dwc_otg_handle_pwrdn_session_change(dwc_otg_core_if_t * core_if)
31077 +{
31078 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
31079 + int32_t otg_cap_param = core_if->core_params->otg_cap;
31080 + DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
31081 +
31082 + gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
31083 + if (core_if->power_down == 2) {
31084 + if (!core_if->hibernation_suspend) {
31085 + DWC_PRINTF("Already exited from Hibernation\n");
31086 + return 1;
31087 + }
31088 +
31089 + if ((otg_cap_param != DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ||
31090 + otg_cap_param != DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) &&
31091 + gpwrdn.b.bsessvld == 0) {
31092 + /* Save gpwrdn register for further usage if stschng interrupt */
31093 + core_if->gr_backup->gpwrdn_local =
31094 + DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
31095 + /*Exit from ISR and wait for stschng interrupt with bsessvld = 1 */
31096 + return 1;
31097 + }
31098 +
31099 + /* Switch on the voltage to the core */
31100 + gpwrdn.d32 = 0;
31101 + gpwrdn.b.pwrdnswtch = 1;
31102 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31103 + dwc_udelay(10);
31104 +
31105 + /* Reset the core */
31106 + gpwrdn.d32 = 0;
31107 + gpwrdn.b.pwrdnrstn = 1;
31108 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31109 + dwc_udelay(10);
31110 +
31111 + /* Disable power clamps */
31112 + gpwrdn.d32 = 0;
31113 + gpwrdn.b.pwrdnclmp = 1;
31114 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31115 +
31116 + /* Remove reset the core signal */
31117 + gpwrdn.d32 = 0;
31118 + gpwrdn.b.pwrdnrstn = 1;
31119 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
31120 + dwc_udelay(10);
31121 +
31122 + /* Disable PMU interrupt */
31123 + gpwrdn.d32 = 0;
31124 + gpwrdn.b.pmuintsel = 1;
31125 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31126 + dwc_udelay(10);
31127 +
31128 + /*Indicates that we are exiting from hibernation */
31129 + core_if->hibernation_suspend = 0;
31130 +
31131 + /* Disable PMU */
31132 + gpwrdn.d32 = 0;
31133 + gpwrdn.b.pmuactv = 1;
31134 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31135 + dwc_udelay(10);
31136 +
31137 + core_if->op_state = B_PERIPHERAL;
31138 + dwc_otg_core_init(core_if);
31139 + dwc_otg_enable_global_interrupts(core_if);
31140 + cil_pcd_start(core_if);
31141 +
31142 + if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ||
31143 + otg_cap_param == DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) {
31144 + /*
31145 + * Initiate SRP after initial ADP probe.
31146 + */
31147 + dwc_otg_initiate_srp(core_if);
31148 + }
31149 + }
31150 +
31151 + return 1;
31152 +}
31153 +/**
31154 + * This interrupt indicates that the Wakeup Logic has detected a
31155 + * status change either on IDDIG or BSessVld.
31156 + */
31157 +static uint32_t dwc_otg_handle_pwrdn_stschng_intr(dwc_otg_device_t *otg_dev)
31158 +{
31159 + int retval;
31160 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
31161 + gpwrdn_data_t gpwrdn_temp = {.d32 = 0 };
31162 + dwc_otg_core_if_t *core_if = otg_dev->core_if;
31163 +
31164 + DWC_PRINTF("%s called\n", __FUNCTION__);
31165 +
31166 + if (core_if->power_down == 2) {
31167 + if (core_if->hibernation_suspend <= 0) {
31168 + DWC_PRINTF("Already exited from Hibernation\n");
31169 + return 1;
31170 + } else
31171 + gpwrdn_temp.d32 = core_if->gr_backup->gpwrdn_local;
31172 +
31173 + } else {
31174 + gpwrdn_temp.d32 = core_if->adp.gpwrdn;
31175 + }
31176 +
31177 + gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
31178 +
31179 + if (gpwrdn.b.idsts ^ gpwrdn_temp.b.idsts) {
31180 + retval = dwc_otg_handle_pwrdn_idsts_change(otg_dev);
31181 + } else if (gpwrdn.b.bsessvld ^ gpwrdn_temp.b.bsessvld) {
31182 + retval = dwc_otg_handle_pwrdn_session_change(core_if);
31183 + }
31184 +
31185 + return retval;
31186 +}
31187 +
31188 +/**
31189 + * This interrupt indicates that the Wakeup Logic has detected a
31190 + * SRP.
31191 + */
31192 +static int32_t dwc_otg_handle_pwrdn_srp_intr(dwc_otg_core_if_t * core_if)
31193 +{
31194 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
31195 +
31196 + DWC_PRINTF("%s called\n", __FUNCTION__);
31197 +
31198 + if (!core_if->hibernation_suspend) {
31199 + DWC_PRINTF("Already exited from Hibernation\n");
31200 + return 1;
31201 + }
31202 +#ifdef DWC_DEV_SRPCAP
31203 + if (core_if->pwron_timer_started) {
31204 + core_if->pwron_timer_started = 0;
31205 + DWC_TIMER_CANCEL(core_if->pwron_timer);
31206 + }
31207 +#endif
31208 +
31209 + /* Switch on the voltage to the core */
31210 + gpwrdn.b.pwrdnswtch = 1;
31211 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31212 + dwc_udelay(10);
31213 +
31214 + /* Reset the core */
31215 + gpwrdn.d32 = 0;
31216 + gpwrdn.b.pwrdnrstn = 1;
31217 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31218 + dwc_udelay(10);
31219 +
31220 + /* Disable power clamps */
31221 + gpwrdn.d32 = 0;
31222 + gpwrdn.b.pwrdnclmp = 1;
31223 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31224 +
31225 + /* Remove reset the core signal */
31226 + gpwrdn.d32 = 0;
31227 + gpwrdn.b.pwrdnrstn = 1;
31228 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
31229 + dwc_udelay(10);
31230 +
31231 + /* Disable PMU interrupt */
31232 + gpwrdn.d32 = 0;
31233 + gpwrdn.b.pmuintsel = 1;
31234 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31235 +
31236 + /* Indicates that we are exiting from hibernation */
31237 + core_if->hibernation_suspend = 0;
31238 +
31239 + /* Disable PMU */
31240 + gpwrdn.d32 = 0;
31241 + gpwrdn.b.pmuactv = 1;
31242 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31243 + dwc_udelay(10);
31244 +
31245 + /* Programm Disable VBUS to 0 */
31246 + gpwrdn.d32 = 0;
31247 + gpwrdn.b.dis_vbus = 1;
31248 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31249 +
31250 + /*Initialize the core as Host */
31251 + core_if->op_state = A_HOST;
31252 + dwc_otg_core_init(core_if);
31253 + dwc_otg_enable_global_interrupts(core_if);
31254 + cil_hcd_start(core_if);
31255 +
31256 + return 1;
31257 +}
31258 +
31259 +/** This interrupt indicates that restore command after Hibernation
31260 + * was completed by the core. */
31261 +int32_t dwc_otg_handle_restore_done_intr(dwc_otg_core_if_t * core_if)
31262 +{
31263 + pcgcctl_data_t pcgcctl;
31264 + DWC_DEBUGPL(DBG_ANY, "++Restore Done Interrupt++\n");
31265 +
31266 + //TODO De-assert restore signal. 8.a
31267 + pcgcctl.d32 = DWC_READ_REG32(core_if->pcgcctl);
31268 + if (pcgcctl.b.restoremode == 1) {
31269 + gintmsk_data_t gintmsk = {.d32 = 0 };
31270 + /*
31271 + * If restore mode is Remote Wakeup,
31272 + * unmask Remote Wakeup interrupt.
31273 + */
31274 + gintmsk.b.wkupintr = 1;
31275 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
31276 + 0, gintmsk.d32);
31277 + }
31278 +
31279 + return 1;
31280 +}
31281 +
31282 +/**
31283 + * This interrupt indicates that a device has been disconnected from
31284 + * the root port.
31285 + */
31286 +int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t * core_if)
31287 +{
31288 + gintsts_data_t gintsts;
31289 +
31290 + DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
31291 + (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"),
31292 + op_state_str(core_if));
31293 +
31294 +/** @todo Consolidate this if statement. */
31295 +#ifndef DWC_HOST_ONLY
31296 + if (core_if->op_state == B_HOST) {
31297 + /* If in device mode Disconnect and stop the HCD, then
31298 + * start the PCD. */
31299 + DWC_SPINUNLOCK(core_if->lock);
31300 + cil_hcd_disconnect(core_if);
31301 + cil_pcd_start(core_if);
31302 + DWC_SPINLOCK(core_if->lock);
31303 + core_if->op_state = B_PERIPHERAL;
31304 + } else if (dwc_otg_is_device_mode(core_if)) {
31305 + gotgctl_data_t gotgctl = {.d32 = 0 };
31306 + gotgctl.d32 =
31307 + DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
31308 + if (gotgctl.b.hstsethnpen == 1) {
31309 + /* Do nothing, if HNP in process the OTG
31310 + * interrupt "Host Negotiation Detected"
31311 + * interrupt will do the mode switch.
31312 + */
31313 + } else if (gotgctl.b.devhnpen == 0) {
31314 + /* If in device mode Disconnect and stop the HCD, then
31315 + * start the PCD. */
31316 + DWC_SPINUNLOCK(core_if->lock);
31317 + cil_hcd_disconnect(core_if);
31318 + cil_pcd_start(core_if);
31319 + DWC_SPINLOCK(core_if->lock);
31320 + core_if->op_state = B_PERIPHERAL;
31321 + } else {
31322 + DWC_DEBUGPL(DBG_ANY, "!a_peripheral && !devhnpen\n");
31323 + }
31324 + } else {
31325 + if (core_if->op_state == A_HOST) {
31326 + /* A-Cable still connected but device disconnected. */
31327 + cil_hcd_disconnect(core_if);
31328 + if (core_if->adp_enable) {
31329 + gpwrdn_data_t gpwrdn = { .d32 = 0 };
31330 + cil_hcd_stop(core_if);
31331 + /* Enable Power Down Logic */
31332 + gpwrdn.b.pmuintsel = 1;
31333 + gpwrdn.b.pmuactv = 1;
31334 + DWC_MODIFY_REG32(&core_if->core_global_regs->
31335 + gpwrdn, 0, gpwrdn.d32);
31336 + dwc_otg_adp_probe_start(core_if);
31337 +
31338 + /* Power off the core */
31339 + if (core_if->power_down == 2) {
31340 + gpwrdn.d32 = 0;
31341 + gpwrdn.b.pwrdnswtch = 1;
31342 + DWC_MODIFY_REG32
31343 + (&core_if->core_global_regs->gpwrdn,
31344 + gpwrdn.d32, 0);
31345 + }
31346 + }
31347 + }
31348 + }
31349 +#endif
31350 + /* Change to L3(OFF) state */
31351 + core_if->lx_state = DWC_OTG_L3;
31352 +
31353 + gintsts.d32 = 0;
31354 + gintsts.b.disconnect = 1;
31355 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
31356 + return 1;
31357 +}
31358 +
31359 +/**
31360 + * This interrupt indicates that SUSPEND state has been detected on
31361 + * the USB.
31362 + *
31363 + * For HNP the USB Suspend interrupt signals the change from
31364 + * "a_peripheral" to "a_host".
31365 + *
31366 + * When power management is enabled the core will be put in low power
31367 + * mode.
31368 + */
31369 +int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t * core_if)
31370 +{
31371 + dsts_data_t dsts;
31372 + gintsts_data_t gintsts;
31373 + dcfg_data_t dcfg;
31374 +
31375 + DWC_DEBUGPL(DBG_ANY, "USB SUSPEND\n");
31376 +
31377 + if (dwc_otg_is_device_mode(core_if)) {
31378 + /* Check the Device status register to determine if the Suspend
31379 + * state is active. */
31380 + dsts.d32 =
31381 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
31382 + DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
31383 + DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
31384 + "HWCFG4.power Optimize=%d\n",
31385 + dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz);
31386 +
31387 +#ifdef PARTIAL_POWER_DOWN
31388 +/** @todo Add a module parameter for power management. */
31389 +
31390 + if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) {
31391 + pcgcctl_data_t power = {.d32 = 0 };
31392 + DWC_DEBUGPL(DBG_CIL, "suspend\n");
31393 +
31394 + power.b.pwrclmp = 1;
31395 + DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
31396 +
31397 + power.b.rstpdwnmodule = 1;
31398 + DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32);
31399 +
31400 + power.b.stoppclk = 1;
31401 + DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32);
31402 +
31403 + } else {
31404 + DWC_DEBUGPL(DBG_ANY, "disconnect?\n");
31405 + }
31406 +#endif
31407 + /* PCD callback for suspend. Release the lock inside of callback function */
31408 + cil_pcd_suspend(core_if);
31409 + if (core_if->power_down == 2)
31410 + {
31411 + dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
31412 + DWC_DEBUGPL(DBG_ANY,"lx_state = %08x\n",core_if->lx_state);
31413 + DWC_DEBUGPL(DBG_ANY," device address = %08d\n",dcfg.b.devaddr);
31414 +
31415 + if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) {
31416 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
31417 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
31418 + gusbcfg_data_t gusbcfg = {.d32 = 0 };
31419 +
31420 + /* Change to L2(suspend) state */
31421 + core_if->lx_state = DWC_OTG_L2;
31422 +
31423 + /* Clear interrupt in gintsts */
31424 + gintsts.d32 = 0;
31425 + gintsts.b.usbsuspend = 1;
31426 + DWC_WRITE_REG32(&core_if->core_global_regs->
31427 + gintsts, gintsts.d32);
31428 + DWC_PRINTF("Start of hibernation completed\n");
31429 + dwc_otg_save_global_regs(core_if);
31430 + dwc_otg_save_dev_regs(core_if);
31431 +
31432 + gusbcfg.d32 =
31433 + DWC_READ_REG32(&core_if->core_global_regs->
31434 + gusbcfg);
31435 + if (gusbcfg.b.ulpi_utmi_sel == 1) {
31436 + /* ULPI interface */
31437 + /* Suspend the Phy Clock */
31438 + pcgcctl.d32 = 0;
31439 + pcgcctl.b.stoppclk = 1;
31440 + DWC_MODIFY_REG32(core_if->pcgcctl, 0,
31441 + pcgcctl.d32);
31442 + dwc_udelay(10);
31443 + gpwrdn.b.pmuactv = 1;
31444 + DWC_MODIFY_REG32(&core_if->
31445 + core_global_regs->
31446 + gpwrdn, 0, gpwrdn.d32);
31447 + } else {
31448 + /* UTMI+ Interface */
31449 + gpwrdn.b.pmuactv = 1;
31450 + DWC_MODIFY_REG32(&core_if->
31451 + core_global_regs->
31452 + gpwrdn, 0, gpwrdn.d32);
31453 + dwc_udelay(10);
31454 + pcgcctl.b.stoppclk = 1;
31455 + DWC_MODIFY_REG32(core_if->pcgcctl, 0,
31456 + pcgcctl.d32);
31457 + dwc_udelay(10);
31458 + }
31459 +
31460 + /* Set flag to indicate that we are in hibernation */
31461 + core_if->hibernation_suspend = 1;
31462 + /* Enable interrupts from wake up logic */
31463 + gpwrdn.d32 = 0;
31464 + gpwrdn.b.pmuintsel = 1;
31465 + DWC_MODIFY_REG32(&core_if->core_global_regs->
31466 + gpwrdn, 0, gpwrdn.d32);
31467 + dwc_udelay(10);
31468 +
31469 + /* Unmask device mode interrupts in GPWRDN */
31470 + gpwrdn.d32 = 0;
31471 + gpwrdn.b.rst_det_msk = 1;
31472 + gpwrdn.b.lnstchng_msk = 1;
31473 + gpwrdn.b.sts_chngint_msk = 1;
31474 + DWC_MODIFY_REG32(&core_if->core_global_regs->
31475 + gpwrdn, 0, gpwrdn.d32);
31476 + dwc_udelay(10);
31477 +
31478 + /* Enable Power Down Clamp */
31479 + gpwrdn.d32 = 0;
31480 + gpwrdn.b.pwrdnclmp = 1;
31481 + DWC_MODIFY_REG32(&core_if->core_global_regs->
31482 + gpwrdn, 0, gpwrdn.d32);
31483 + dwc_udelay(10);
31484 +
31485 + /* Switch off VDD */
31486 + gpwrdn.d32 = 0;
31487 + gpwrdn.b.pwrdnswtch = 1;
31488 + DWC_MODIFY_REG32(&core_if->core_global_regs->
31489 + gpwrdn, 0, gpwrdn.d32);
31490 +
31491 + /* Save gpwrdn register for further usage if stschng interrupt */
31492 + core_if->gr_backup->gpwrdn_local =
31493 + DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
31494 + DWC_PRINTF("Hibernation completed\n");
31495 +
31496 + return 1;
31497 + }
31498 + } else if (core_if->power_down == 3) {
31499 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
31500 + dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
31501 + DWC_DEBUGPL(DBG_ANY, "lx_state = %08x\n",core_if->lx_state);
31502 + DWC_DEBUGPL(DBG_ANY, " device address = %08d\n",dcfg.b.devaddr);
31503 +
31504 + if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) {
31505 + DWC_DEBUGPL(DBG_ANY, "Start entering to extended hibernation\n");
31506 + core_if->xhib = 1;
31507 +
31508 + /* Clear interrupt in gintsts */
31509 + gintsts.d32 = 0;
31510 + gintsts.b.usbsuspend = 1;
31511 + DWC_WRITE_REG32(&core_if->core_global_regs->
31512 + gintsts, gintsts.d32);
31513 +
31514 + dwc_otg_save_global_regs(core_if);
31515 + dwc_otg_save_dev_regs(core_if);
31516 +
31517 + /* Wait for 10 PHY clocks */
31518 + dwc_udelay(10);
31519 +
31520 + /* Program GPIO register while entering to xHib */
31521 + DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x1);
31522 +
31523 + pcgcctl.b.enbl_extnd_hiber = 1;
31524 + DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
31525 + DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
31526 +
31527 + pcgcctl.d32 = 0;
31528 + pcgcctl.b.extnd_hiber_pwrclmp = 1;
31529 + DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
31530 +
31531 + pcgcctl.d32 = 0;
31532 + pcgcctl.b.extnd_hiber_switch = 1;
31533 + core_if->gr_backup->xhib_gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
31534 + core_if->gr_backup->xhib_pcgcctl = DWC_READ_REG32(core_if->pcgcctl) | pcgcctl.d32;
31535 + DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
31536 +
31537 + DWC_DEBUGPL(DBG_ANY, "Finished entering to extended hibernation\n");
31538 +
31539 + return 1;
31540 + }
31541 + }
31542 + } else {
31543 + if (core_if->op_state == A_PERIPHERAL) {
31544 + DWC_DEBUGPL(DBG_ANY, "a_peripheral->a_host\n");
31545 + /* Clear the a_peripheral flag, back to a_host. */
31546 + DWC_SPINUNLOCK(core_if->lock);
31547 + cil_pcd_stop(core_if);
31548 + cil_hcd_start(core_if);
31549 + DWC_SPINLOCK(core_if->lock);
31550 + core_if->op_state = A_HOST;
31551 + }
31552 + }
31553 +
31554 + /* Change to L2(suspend) state */
31555 + core_if->lx_state = DWC_OTG_L2;
31556 +
31557 + /* Clear interrupt */
31558 + gintsts.d32 = 0;
31559 + gintsts.b.usbsuspend = 1;
31560 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
31561 +
31562 + return 1;
31563 +}
31564 +
31565 +static int32_t dwc_otg_handle_xhib_exit_intr(dwc_otg_core_if_t * core_if)
31566 +{
31567 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
31568 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
31569 + gahbcfg_data_t gahbcfg = {.d32 = 0 };
31570 +
31571 + dwc_udelay(10);
31572 +
31573 + /* Program GPIO register while entering to xHib */
31574 + DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x0);
31575 +
31576 + pcgcctl.d32 = core_if->gr_backup->xhib_pcgcctl;
31577 + pcgcctl.b.extnd_hiber_pwrclmp = 0;
31578 + DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
31579 + dwc_udelay(10);
31580 +
31581 + gpwrdn.d32 = core_if->gr_backup->xhib_gpwrdn;
31582 + gpwrdn.b.restore = 1;
31583 + DWC_WRITE_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32);
31584 + dwc_udelay(10);
31585 +
31586 + restore_lpm_i2c_regs(core_if);
31587 +
31588 + pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
31589 + pcgcctl.b.max_xcvrselect = 1;
31590 + pcgcctl.b.ess_reg_restored = 0;
31591 + pcgcctl.b.extnd_hiber_switch = 0;
31592 + pcgcctl.b.extnd_hiber_pwrclmp = 0;
31593 + pcgcctl.b.enbl_extnd_hiber = 1;
31594 + DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
31595 +
31596 + gahbcfg.d32 = core_if->gr_backup->gahbcfg_local;
31597 + gahbcfg.b.glblintrmsk = 1;
31598 + DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32);
31599 +
31600 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
31601 + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0x1 << 16);
31602 +
31603 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
31604 + core_if->gr_backup->gusbcfg_local);
31605 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
31606 + core_if->dr_backup->dcfg);
31607 +
31608 + pcgcctl.d32 = 0;
31609 + pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
31610 + pcgcctl.b.max_xcvrselect = 1;
31611 + pcgcctl.d32 |= 0x608;
31612 + DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
31613 + dwc_udelay(10);
31614 +
31615 + pcgcctl.d32 = 0;
31616 + pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
31617 + pcgcctl.b.max_xcvrselect = 1;
31618 + pcgcctl.b.ess_reg_restored = 1;
31619 + pcgcctl.b.enbl_extnd_hiber = 1;
31620 + pcgcctl.b.rstpdwnmodule = 1;
31621 + pcgcctl.b.restoremode = 1;
31622 + DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
31623 +
31624 + DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
31625 +
31626 + return 1;
31627 +}
31628 +
31629 +#ifdef CONFIG_USB_DWC_OTG_LPM
31630 +/**
31631 + * This function hadles LPM transaction received interrupt.
31632 + */
31633 +static int32_t dwc_otg_handle_lpm_intr(dwc_otg_core_if_t * core_if)
31634 +{
31635 + glpmcfg_data_t lpmcfg;
31636 + gintsts_data_t gintsts;
31637 +
31638 + if (!core_if->core_params->lpm_enable) {
31639 + DWC_PRINTF("Unexpected LPM interrupt\n");
31640 + }
31641 +
31642 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
31643 + DWC_PRINTF("LPM config register = 0x%08x\n", lpmcfg.d32);
31644 +
31645 + if (dwc_otg_is_host_mode(core_if)) {
31646 + cil_hcd_sleep(core_if);
31647 + } else {
31648 + lpmcfg.b.hird_thres |= (1 << 4);
31649 + DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg,
31650 + lpmcfg.d32);
31651 + }
31652 +
31653 + /* Examine prt_sleep_sts after TL1TokenTetry period max (10 us) */
31654 + dwc_udelay(10);
31655 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
31656 + if (lpmcfg.b.prt_sleep_sts) {
31657 + /* Save the current state */
31658 + core_if->lx_state = DWC_OTG_L1;
31659 + }
31660 +
31661 + /* Clear interrupt */
31662 + gintsts.d32 = 0;
31663 + gintsts.b.lpmtranrcvd = 1;
31664 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
31665 + return 1;
31666 +}
31667 +#endif /* CONFIG_USB_DWC_OTG_LPM */
31668 +
31669 +/**
31670 + * This function returns the Core Interrupt register.
31671 + */
31672 +static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if, gintmsk_data_t *reenable_gintmsk, dwc_otg_hcd_t *hcd)
31673 +{
31674 + gahbcfg_data_t gahbcfg = {.d32 = 0 };
31675 + gintsts_data_t gintsts;
31676 + gintmsk_data_t gintmsk;
31677 + gintmsk_data_t gintmsk_common = {.d32 = 0 };
31678 + gintmsk_common.b.wkupintr = 1;
31679 + gintmsk_common.b.sessreqintr = 1;
31680 + gintmsk_common.b.conidstschng = 1;
31681 + gintmsk_common.b.otgintr = 1;
31682 + gintmsk_common.b.modemismatch = 1;
31683 + gintmsk_common.b.disconnect = 1;
31684 + gintmsk_common.b.usbsuspend = 1;
31685 +#ifdef CONFIG_USB_DWC_OTG_LPM
31686 + gintmsk_common.b.lpmtranrcvd = 1;
31687 +#endif
31688 + gintmsk_common.b.restoredone = 1;
31689 + if(dwc_otg_is_device_mode(core_if))
31690 + {
31691 + /** @todo: The port interrupt occurs while in device
31692 + * mode. Added code to CIL to clear the interrupt for now!
31693 + */
31694 + gintmsk_common.b.portintr = 1;
31695 + }
31696 + gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
31697 + gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
31698 + if(fiq_enable) {
31699 + local_fiq_disable();
31700 + /* Pull in the interrupts that the FIQ has masked */
31701 + gintmsk.d32 |= ~(hcd->fiq_state->gintmsk_saved.d32);
31702 + gintmsk.d32 |= gintmsk_common.d32;
31703 + /* for the upstairs function to reenable - have to read it here in case FIQ triggers again */
31704 + reenable_gintmsk->d32 = gintmsk.d32;
31705 + local_fiq_enable();
31706 + }
31707 +
31708 + gahbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);
31709 +
31710 +#ifdef DEBUG
31711 + /* if any common interrupts set */
31712 + if (gintsts.d32 & gintmsk_common.d32) {
31713 + DWC_DEBUGPL(DBG_ANY, "common_intr: gintsts=%08x gintmsk=%08x\n",
31714 + gintsts.d32, gintmsk.d32);
31715 + }
31716 +#endif
31717 + if (!fiq_enable){
31718 + if (gahbcfg.b.glblintrmsk)
31719 + return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
31720 + else
31721 + return 0;
31722 + } else {
31723 + /* Our IRQ kicker is no longer the USB hardware, it's the MPHI interface.
31724 + * Can't trust the global interrupt mask bit in this case.
31725 + */
31726 + return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
31727 + }
31728 +
31729 +}
31730 +
31731 +/* MACRO for clearing interupt bits in GPWRDN register */
31732 +#define CLEAR_GPWRDN_INTR(__core_if,__intr) \
31733 +do { \
31734 + gpwrdn_data_t gpwrdn = {.d32=0}; \
31735 + gpwrdn.b.__intr = 1; \
31736 + DWC_MODIFY_REG32(&__core_if->core_global_regs->gpwrdn, \
31737 + 0, gpwrdn.d32); \
31738 +} while (0)
31739 +
31740 +/**
31741 + * Common interrupt handler.
31742 + *
31743 + * The common interrupts are those that occur in both Host and Device mode.
31744 + * This handler handles the following interrupts:
31745 + * - Mode Mismatch Interrupt
31746 + * - Disconnect Interrupt
31747 + * - OTG Interrupt
31748 + * - Connector ID Status Change Interrupt
31749 + * - Session Request Interrupt.
31750 + * - Resume / Remote Wakeup Detected Interrupt.
31751 + * - LPM Transaction Received Interrupt
31752 + * - ADP Transaction Received Interrupt
31753 + *
31754 + */
31755 +int32_t dwc_otg_handle_common_intr(void *dev)
31756 +{
31757 + int retval = 0;
31758 + gintsts_data_t gintsts;
31759 + gintmsk_data_t gintmsk_reenable = { .d32 = 0 };
31760 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
31761 + dwc_otg_device_t *otg_dev = dev;
31762 + dwc_otg_core_if_t *core_if = otg_dev->core_if;
31763 + gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
31764 + if (dwc_otg_is_device_mode(core_if))
31765 + core_if->frame_num = dwc_otg_get_frame_number(core_if);
31766 +
31767 + if (core_if->lock)
31768 + DWC_SPINLOCK(core_if->lock);
31769 +
31770 + if (core_if->power_down == 3 && core_if->xhib == 1) {
31771 + DWC_DEBUGPL(DBG_ANY, "Exiting from xHIB state\n");
31772 + retval |= dwc_otg_handle_xhib_exit_intr(core_if);
31773 + core_if->xhib = 2;
31774 + if (core_if->lock)
31775 + DWC_SPINUNLOCK(core_if->lock);
31776 +
31777 + return retval;
31778 + }
31779 +
31780 + if (core_if->hibernation_suspend <= 0) {
31781 + /* read_common will have to poke the FIQ's saved mask. We must then clear this mask at the end
31782 + * of this handler - god only knows why it's done like this
31783 + */
31784 + gintsts.d32 = dwc_otg_read_common_intr(core_if, &gintmsk_reenable, otg_dev->hcd);
31785 +
31786 + if (gintsts.b.modemismatch) {
31787 + retval |= dwc_otg_handle_mode_mismatch_intr(core_if);
31788 + }
31789 + if (gintsts.b.otgintr) {
31790 + retval |= dwc_otg_handle_otg_intr(core_if);
31791 + }
31792 + if (gintsts.b.conidstschng) {
31793 + retval |=
31794 + dwc_otg_handle_conn_id_status_change_intr(core_if);
31795 + }
31796 + if (gintsts.b.disconnect) {
31797 + retval |= dwc_otg_handle_disconnect_intr(core_if);
31798 + }
31799 + if (gintsts.b.sessreqintr) {
31800 + retval |= dwc_otg_handle_session_req_intr(core_if);
31801 + }
31802 + if (gintsts.b.wkupintr) {
31803 + retval |= dwc_otg_handle_wakeup_detected_intr(core_if);
31804 + }
31805 + if (gintsts.b.usbsuspend) {
31806 + retval |= dwc_otg_handle_usb_suspend_intr(core_if);
31807 + }
31808 +#ifdef CONFIG_USB_DWC_OTG_LPM
31809 + if (gintsts.b.lpmtranrcvd) {
31810 + retval |= dwc_otg_handle_lpm_intr(core_if);
31811 + }
31812 +#endif
31813 + if (gintsts.b.restoredone) {
31814 + gintsts.d32 = 0;
31815 + if (core_if->power_down == 2)
31816 + core_if->hibernation_suspend = -1;
31817 + else if (core_if->power_down == 3 && core_if->xhib == 2) {
31818 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
31819 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
31820 + dctl_data_t dctl = {.d32 = 0 };
31821 +
31822 + DWC_WRITE_REG32(&core_if->core_global_regs->
31823 + gintsts, 0xFFFFFFFF);
31824 +
31825 + DWC_DEBUGPL(DBG_ANY,
31826 + "RESTORE DONE generated\n");
31827 +
31828 + gpwrdn.b.restore = 1;
31829 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31830 + dwc_udelay(10);
31831 +
31832 + pcgcctl.b.rstpdwnmodule = 1;
31833 + DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
31834 +
31835 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, core_if->gr_backup->gusbcfg_local);
31836 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, core_if->dr_backup->dcfg);
31837 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, core_if->dr_backup->dctl);
31838 + dwc_udelay(50);
31839 +
31840 + dctl.b.pwronprgdone = 1;
31841 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
31842 + dwc_udelay(10);
31843 +
31844 + dwc_otg_restore_global_regs(core_if);
31845 + dwc_otg_restore_dev_regs(core_if, 0);
31846 +
31847 + dctl.d32 = 0;
31848 + dctl.b.pwronprgdone = 1;
31849 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
31850 + dwc_udelay(10);
31851 +
31852 + pcgcctl.d32 = 0;
31853 + pcgcctl.b.enbl_extnd_hiber = 1;
31854 + DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
31855 +
31856 + /* The core will be in ON STATE */
31857 + core_if->lx_state = DWC_OTG_L0;
31858 + core_if->xhib = 0;
31859 +
31860 + DWC_SPINUNLOCK(core_if->lock);
31861 + if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
31862 + core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
31863 + }
31864 + DWC_SPINLOCK(core_if->lock);
31865 +
31866 + }
31867 +
31868 + gintsts.b.restoredone = 1;
31869 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32);
31870 + DWC_PRINTF(" --Restore done interrupt received-- \n");
31871 + retval |= 1;
31872 + }
31873 + if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) {
31874 + /* The port interrupt occurs while in device mode with HPRT0
31875 + * Port Enable/Disable.
31876 + */
31877 + gintsts.d32 = 0;
31878 + gintsts.b.portintr = 1;
31879 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32);
31880 + retval |= 1;
31881 + gintmsk_reenable.b.portintr = 1;
31882 +
31883 + }
31884 + /* Did we actually handle anything? if so, unmask the interrupt */
31885 +// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "CILOUT %1d", retval);
31886 +// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "%08x", gintsts.d32);
31887 +// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "%08x", gintmsk_reenable.d32);
31888 + if (retval && fiq_enable) {
31889 + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_reenable.d32);
31890 + }
31891 +
31892 + } else {
31893 + DWC_DEBUGPL(DBG_ANY, "gpwrdn=%08x\n", gpwrdn.d32);
31894 +
31895 + if (gpwrdn.b.disconn_det && gpwrdn.b.disconn_det_msk) {
31896 + CLEAR_GPWRDN_INTR(core_if, disconn_det);
31897 + if (gpwrdn.b.linestate == 0) {
31898 + dwc_otg_handle_pwrdn_disconnect_intr(core_if);
31899 + } else {
31900 + DWC_PRINTF("Disconnect detected while linestate is not 0\n");
31901 + }
31902 +
31903 + retval |= 1;
31904 + }
31905 + if (gpwrdn.b.lnstschng && gpwrdn.b.lnstchng_msk) {
31906 + CLEAR_GPWRDN_INTR(core_if, lnstschng);
31907 + /* remote wakeup from hibernation */
31908 + if (gpwrdn.b.linestate == 2 || gpwrdn.b.linestate == 1) {
31909 + dwc_otg_handle_pwrdn_wakeup_detected_intr(core_if);
31910 + } else {
31911 + DWC_PRINTF("gpwrdn.linestate = %d\n", gpwrdn.b.linestate);
31912 + }
31913 + retval |= 1;
31914 + }
31915 + if (gpwrdn.b.rst_det && gpwrdn.b.rst_det_msk) {
31916 + CLEAR_GPWRDN_INTR(core_if, rst_det);
31917 + if (gpwrdn.b.linestate == 0) {
31918 + DWC_PRINTF("Reset detected\n");
31919 + retval |= dwc_otg_device_hibernation_restore(core_if, 0, 1);
31920 + }
31921 + }
31922 + if (gpwrdn.b.srp_det && gpwrdn.b.srp_det_msk) {
31923 + CLEAR_GPWRDN_INTR(core_if, srp_det);
31924 + dwc_otg_handle_pwrdn_srp_intr(core_if);
31925 + retval |= 1;
31926 + }
31927 + }
31928 + /* Handle ADP interrupt here */
31929 + if (gpwrdn.b.adp_int) {
31930 + DWC_PRINTF("ADP interrupt\n");
31931 + CLEAR_GPWRDN_INTR(core_if, adp_int);
31932 + dwc_otg_adp_handle_intr(core_if);
31933 + retval |= 1;
31934 + }
31935 + if (gpwrdn.b.sts_chngint && gpwrdn.b.sts_chngint_msk) {
31936 + DWC_PRINTF("STS CHNG interrupt asserted\n");
31937 + CLEAR_GPWRDN_INTR(core_if, sts_chngint);
31938 + dwc_otg_handle_pwrdn_stschng_intr(otg_dev);
31939 +
31940 + retval |= 1;
31941 + }
31942 + if (core_if->lock)
31943 + DWC_SPINUNLOCK(core_if->lock);
31944 + return retval;
31945 +}
31946 --- /dev/null
31947 +++ b/drivers/usb/host/dwc_otg/dwc_otg_core_if.h
31948 @@ -0,0 +1,705 @@
31949 +/* ==========================================================================
31950 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $
31951 + * $Revision: #13 $
31952 + * $Date: 2012/08/10 $
31953 + * $Change: 2047372 $
31954 + *
31955 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
31956 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
31957 + * otherwise expressly agreed to in writing between Synopsys and you.
31958 + *
31959 + * The Software IS NOT an item of Licensed Software or Licensed Product under
31960 + * any End User Software License Agreement or Agreement for Licensed Product
31961 + * with Synopsys or any supplement thereto. You are permitted to use and
31962 + * redistribute this Software in source and binary forms, with or without
31963 + * modification, provided that redistributions of source code must retain this
31964 + * notice. You may not view, use, disclose, copy or distribute this file or
31965 + * any information contained herein except pursuant to this license grant from
31966 + * Synopsys. If you do not agree with this notice, including the disclaimer
31967 + * below, then you are not authorized to use the Software.
31968 + *
31969 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
31970 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31971 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31972 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
31973 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31974 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31975 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31976 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31977 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31978 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
31979 + * DAMAGE.
31980 + * ========================================================================== */
31981 +#if !defined(__DWC_CORE_IF_H__)
31982 +#define __DWC_CORE_IF_H__
31983 +
31984 +#include "dwc_os.h"
31985 +
31986 +/** @file
31987 + * This file defines DWC_OTG Core API
31988 + */
31989 +
31990 +struct dwc_otg_core_if;
31991 +typedef struct dwc_otg_core_if dwc_otg_core_if_t;
31992 +
31993 +/** Maximum number of Periodic FIFOs */
31994 +#define MAX_PERIO_FIFOS 15
31995 +/** Maximum number of Periodic FIFOs */
31996 +#define MAX_TX_FIFOS 15
31997 +
31998 +/** Maximum number of Endpoints/HostChannels */
31999 +#define MAX_EPS_CHANNELS 16
32000 +
32001 +extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * _reg_base_addr);
32002 +extern void dwc_otg_core_init(dwc_otg_core_if_t * _core_if);
32003 +extern void dwc_otg_cil_remove(dwc_otg_core_if_t * _core_if);
32004 +
32005 +extern void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * _core_if);
32006 +extern void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * _core_if);
32007 +
32008 +extern uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if);
32009 +extern uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if);
32010 +
32011 +extern uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if);
32012 +
32013 +/** This function should be called on every hardware interrupt. */
32014 +extern int32_t dwc_otg_handle_common_intr(void *otg_dev);
32015 +
32016 +/** @name OTG Core Parameters */
32017 +/** @{ */
32018 +
32019 +/**
32020 + * Specifies the OTG capabilities. The driver will automatically
32021 + * detect the value for this parameter if none is specified.
32022 + * 0 - HNP and SRP capable (default)
32023 + * 1 - SRP Only capable
32024 + * 2 - No HNP/SRP capable
32025 + */
32026 +extern int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val);
32027 +extern int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if);
32028 +#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
32029 +#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
32030 +#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
32031 +#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
32032 +
32033 +extern int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val);
32034 +extern int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if);
32035 +#define dwc_param_opt_default 1
32036 +
32037 +/**
32038 + * Specifies whether to use slave or DMA mode for accessing the data
32039 + * FIFOs. The driver will automatically detect the value for this
32040 + * parameter if none is specified.
32041 + * 0 - Slave
32042 + * 1 - DMA (default, if available)
32043 + */
32044 +extern int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if,
32045 + int32_t val);
32046 +extern int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if);
32047 +#define dwc_param_dma_enable_default 1
32048 +
32049 +/**
32050 + * When DMA mode is enabled specifies whether to use
32051 + * address DMA or DMA Descritor mode for accessing the data
32052 + * FIFOs in device mode. The driver will automatically detect
32053 + * the value for this parameter if none is specified.
32054 + * 0 - address DMA
32055 + * 1 - DMA Descriptor(default, if available)
32056 + */
32057 +extern int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if,
32058 + int32_t val);
32059 +extern int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if);
32060 +//#define dwc_param_dma_desc_enable_default 1
32061 +#define dwc_param_dma_desc_enable_default 0 // Broadcom BCM2708
32062 +
32063 +/** The DMA Burst size (applicable only for External DMA
32064 + * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
32065 + */
32066 +extern int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if,
32067 + int32_t val);
32068 +extern int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if);
32069 +#define dwc_param_dma_burst_size_default 32
32070 +
32071 +/**
32072 + * Specifies the maximum speed of operation in host and device mode.
32073 + * The actual speed depends on the speed of the attached device and
32074 + * the value of phy_type. The actual speed depends on the speed of the
32075 + * attached device.
32076 + * 0 - High Speed (default)
32077 + * 1 - Full Speed
32078 + */
32079 +extern int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val);
32080 +extern int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if);
32081 +#define dwc_param_speed_default 0
32082 +#define DWC_SPEED_PARAM_HIGH 0
32083 +#define DWC_SPEED_PARAM_FULL 1
32084 +
32085 +/** Specifies whether low power mode is supported when attached
32086 + * to a Full Speed or Low Speed device in host mode.
32087 + * 0 - Don't support low power mode (default)
32088 + * 1 - Support low power mode
32089 + */
32090 +extern int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
32091 + core_if, int32_t val);
32092 +extern int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t
32093 + * core_if);
32094 +#define dwc_param_host_support_fs_ls_low_power_default 0
32095 +
32096 +/** Specifies the PHY clock rate in low power mode when connected to a
32097 + * Low Speed device in host mode. This parameter is applicable only if
32098 + * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
32099 + * then defaults to 6 MHZ otherwise 48 MHZ.
32100 + *
32101 + * 0 - 48 MHz
32102 + * 1 - 6 MHz
32103 + */
32104 +extern int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
32105 + core_if, int32_t val);
32106 +extern int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
32107 + core_if);
32108 +#define dwc_param_host_ls_low_power_phy_clk_default 0
32109 +#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
32110 +#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
32111 +
32112 +/**
32113 + * 0 - Use cC FIFO size parameters
32114 + * 1 - Allow dynamic FIFO sizing (default)
32115 + */
32116 +extern int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
32117 + int32_t val);
32118 +extern int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t *
32119 + core_if);
32120 +#define dwc_param_enable_dynamic_fifo_default 1
32121 +
32122 +/** Total number of 4-byte words in the data FIFO memory. This
32123 + * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
32124 + * Tx FIFOs.
32125 + * 32 to 32768 (default 8192)
32126 + * Note: The total FIFO memory depth in the FPGA configuration is 8192.
32127 + */
32128 +extern int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if,
32129 + int32_t val);
32130 +extern int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if);
32131 +//#define dwc_param_data_fifo_size_default 8192
32132 +#define dwc_param_data_fifo_size_default 0xFF0 // Broadcom BCM2708
32133 +
32134 +/** Number of 4-byte words in the Rx FIFO in device mode when dynamic
32135 + * FIFO sizing is enabled.
32136 + * 16 to 32768 (default 1064)
32137 + */
32138 +extern int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if,
32139 + int32_t val);
32140 +extern int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if);
32141 +#define dwc_param_dev_rx_fifo_size_default 1064
32142 +
32143 +/** Number of 4-byte words in the non-periodic Tx FIFO in device mode
32144 + * when dynamic FIFO sizing is enabled.
32145 + * 16 to 32768 (default 1024)
32146 + */
32147 +extern int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
32148 + core_if, int32_t val);
32149 +extern int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
32150 + core_if);
32151 +#define dwc_param_dev_nperio_tx_fifo_size_default 1024
32152 +
32153 +/** Number of 4-byte words in each of the periodic Tx FIFOs in device
32154 + * mode when dynamic FIFO sizing is enabled.
32155 + * 4 to 768 (default 256)
32156 + */
32157 +extern int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
32158 + int32_t val, int fifo_num);
32159 +extern int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t *
32160 + core_if, int fifo_num);
32161 +#define dwc_param_dev_perio_tx_fifo_size_default 256
32162 +
32163 +/** Number of 4-byte words in the Rx FIFO in host mode when dynamic
32164 + * FIFO sizing is enabled.
32165 + * 16 to 32768 (default 1024)
32166 + */
32167 +extern int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
32168 + int32_t val);
32169 +extern int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if);
32170 +//#define dwc_param_host_rx_fifo_size_default 1024
32171 +#define dwc_param_host_rx_fifo_size_default 774 // Broadcom BCM2708
32172 +
32173 +/** Number of 4-byte words in the non-periodic Tx FIFO in host mode
32174 + * when Dynamic FIFO sizing is enabled in the core.
32175 + * 16 to 32768 (default 1024)
32176 + */
32177 +extern int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
32178 + core_if, int32_t val);
32179 +extern int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
32180 + core_if);
32181 +//#define dwc_param_host_nperio_tx_fifo_size_default 1024
32182 +#define dwc_param_host_nperio_tx_fifo_size_default 0x100 // Broadcom BCM2708
32183 +
32184 +/** Number of 4-byte words in the host periodic Tx FIFO when dynamic
32185 + * FIFO sizing is enabled.
32186 + * 16 to 32768 (default 1024)
32187 + */
32188 +extern int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
32189 + core_if, int32_t val);
32190 +extern int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
32191 + core_if);
32192 +//#define dwc_param_host_perio_tx_fifo_size_default 1024
32193 +#define dwc_param_host_perio_tx_fifo_size_default 0x200 // Broadcom BCM2708
32194 +
32195 +/** The maximum transfer size supported in bytes.
32196 + * 2047 to 65,535 (default 65,535)
32197 + */
32198 +extern int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
32199 + int32_t val);
32200 +extern int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if);
32201 +#define dwc_param_max_transfer_size_default 65535
32202 +
32203 +/** The maximum number of packets in a transfer.
32204 + * 15 to 511 (default 511)
32205 + */
32206 +extern int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if,
32207 + int32_t val);
32208 +extern int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if);
32209 +#define dwc_param_max_packet_count_default 511
32210 +
32211 +/** The number of host channel registers to use.
32212 + * 1 to 16 (default 12)
32213 + * Note: The FPGA configuration supports a maximum of 12 host channels.
32214 + */
32215 +extern int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if,
32216 + int32_t val);
32217 +extern int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if);
32218 +//#define dwc_param_host_channels_default 12
32219 +#define dwc_param_host_channels_default 8 // Broadcom BCM2708
32220 +
32221 +/** The number of endpoints in addition to EP0 available for device
32222 + * mode operations.
32223 + * 1 to 15 (default 6 IN and OUT)
32224 + * Note: The FPGA configuration supports a maximum of 6 IN and OUT
32225 + * endpoints in addition to EP0.
32226 + */
32227 +extern int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if,
32228 + int32_t val);
32229 +extern int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if);
32230 +#define dwc_param_dev_endpoints_default 6
32231 +
32232 +/**
32233 + * Specifies the type of PHY interface to use. By default, the driver
32234 + * will automatically detect the phy_type.
32235 + *
32236 + * 0 - Full Speed PHY
32237 + * 1 - UTMI+ (default)
32238 + * 2 - ULPI
32239 + */
32240 +extern int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val);
32241 +extern int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if);
32242 +#define DWC_PHY_TYPE_PARAM_FS 0
32243 +#define DWC_PHY_TYPE_PARAM_UTMI 1
32244 +#define DWC_PHY_TYPE_PARAM_ULPI 2
32245 +#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
32246 +
32247 +/**
32248 + * Specifies the UTMI+ Data Width. This parameter is
32249 + * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
32250 + * PHY_TYPE, this parameter indicates the data width between
32251 + * the MAC and the ULPI Wrapper.) Also, this parameter is
32252 + * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
32253 + * to "8 and 16 bits", meaning that the core has been
32254 + * configured to work at either data path width.
32255 + *
32256 + * 8 or 16 bits (default 16)
32257 + */
32258 +extern int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if,
32259 + int32_t val);
32260 +extern int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if);
32261 +//#define dwc_param_phy_utmi_width_default 16
32262 +#define dwc_param_phy_utmi_width_default 8 // Broadcom BCM2708
32263 +
32264 +/**
32265 + * Specifies whether the ULPI operates at double or single
32266 + * data rate. This parameter is only applicable if PHY_TYPE is
32267 + * ULPI.
32268 + *
32269 + * 0 - single data rate ULPI interface with 8 bit wide data
32270 + * bus (default)
32271 + * 1 - double data rate ULPI interface with 4 bit wide data
32272 + * bus
32273 + */
32274 +extern int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if,
32275 + int32_t val);
32276 +extern int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if);
32277 +#define dwc_param_phy_ulpi_ddr_default 0
32278 +
32279 +/**
32280 + * Specifies whether to use the internal or external supply to
32281 + * drive the vbus with a ULPI phy.
32282 + */
32283 +extern int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
32284 + int32_t val);
32285 +extern int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if);
32286 +#define DWC_PHY_ULPI_INTERNAL_VBUS 0
32287 +#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
32288 +#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
32289 +
32290 +/**
32291 + * Specifies whether to use the I2Cinterface for full speed PHY. This
32292 + * parameter is only applicable if PHY_TYPE is FS.
32293 + * 0 - No (default)
32294 + * 1 - Yes
32295 + */
32296 +extern int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if,
32297 + int32_t val);
32298 +extern int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if);
32299 +#define dwc_param_i2c_enable_default 0
32300 +
32301 +extern int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if,
32302 + int32_t val);
32303 +extern int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if);
32304 +#define dwc_param_ulpi_fs_ls_default 0
32305 +
32306 +extern int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val);
32307 +extern int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if);
32308 +#define dwc_param_ts_dline_default 0
32309 +
32310 +/**
32311 + * Specifies whether dedicated transmit FIFOs are
32312 + * enabled for non periodic IN endpoints in device mode
32313 + * 0 - No
32314 + * 1 - Yes
32315 + */
32316 +extern int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
32317 + int32_t val);
32318 +extern int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t *
32319 + core_if);
32320 +#define dwc_param_en_multiple_tx_fifo_default 1
32321 +
32322 +/** Number of 4-byte words in each of the Tx FIFOs in device
32323 + * mode when dynamic FIFO sizing is enabled.
32324 + * 4 to 768 (default 256)
32325 + */
32326 +extern int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
32327 + int fifo_num, int32_t val);
32328 +extern int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
32329 + int fifo_num);
32330 +#define dwc_param_dev_tx_fifo_size_default 768
32331 +
32332 +/** Thresholding enable flag-
32333 + * bit 0 - enable non-ISO Tx thresholding
32334 + * bit 1 - enable ISO Tx thresholding
32335 + * bit 2 - enable Rx thresholding
32336 + */
32337 +extern int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val);
32338 +extern int32_t dwc_otg_get_thr_ctl(dwc_otg_core_if_t * core_if, int fifo_num);
32339 +#define dwc_param_thr_ctl_default 0
32340 +
32341 +/** Thresholding length for Tx
32342 + * FIFOs in 32 bit DWORDs
32343 + */
32344 +extern int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if,
32345 + int32_t val);
32346 +extern int32_t dwc_otg_get_tx_thr_length(dwc_otg_core_if_t * core_if);
32347 +#define dwc_param_tx_thr_length_default 64
32348 +
32349 +/** Thresholding length for Rx
32350 + * FIFOs in 32 bit DWORDs
32351 + */
32352 +extern int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if,
32353 + int32_t val);
32354 +extern int32_t dwc_otg_get_rx_thr_length(dwc_otg_core_if_t * core_if);
32355 +#define dwc_param_rx_thr_length_default 64
32356 +
32357 +/**
32358 + * Specifies whether LPM (Link Power Management) support is enabled
32359 + */
32360 +extern int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if,
32361 + int32_t val);
32362 +extern int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if);
32363 +#define dwc_param_lpm_enable_default 1
32364 +
32365 +/**
32366 + * Specifies whether PTI enhancement is enabled
32367 + */
32368 +extern int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if,
32369 + int32_t val);
32370 +extern int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if);
32371 +#define dwc_param_pti_enable_default 0
32372 +
32373 +/**
32374 + * Specifies whether MPI enhancement is enabled
32375 + */
32376 +extern int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if,
32377 + int32_t val);
32378 +extern int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if);
32379 +#define dwc_param_mpi_enable_default 0
32380 +
32381 +/**
32382 + * Specifies whether ADP capability is enabled
32383 + */
32384 +extern int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if,
32385 + int32_t val);
32386 +extern int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if);
32387 +#define dwc_param_adp_enable_default 0
32388 +
32389 +/**
32390 + * Specifies whether IC_USB capability is enabled
32391 + */
32392 +
32393 +extern int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if,
32394 + int32_t val);
32395 +extern int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if);
32396 +#define dwc_param_ic_usb_cap_default 0
32397 +
32398 +extern int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if,
32399 + int32_t val);
32400 +extern int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if);
32401 +#define dwc_param_ahb_thr_ratio_default 0
32402 +
32403 +extern int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if,
32404 + int32_t val);
32405 +extern int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if);
32406 +#define dwc_param_power_down_default 0
32407 +
32408 +extern int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if,
32409 + int32_t val);
32410 +extern int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if);
32411 +#define dwc_param_reload_ctl_default 0
32412 +
32413 +extern int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if,
32414 + int32_t val);
32415 +extern int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if);
32416 +#define dwc_param_dev_out_nak_default 0
32417 +
32418 +extern int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if,
32419 + int32_t val);
32420 +extern int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if);
32421 +#define dwc_param_cont_on_bna_default 0
32422 +
32423 +extern int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if,
32424 + int32_t val);
32425 +extern int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if);
32426 +#define dwc_param_ahb_single_default 0
32427 +
32428 +extern int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val);
32429 +extern int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if);
32430 +#define dwc_param_otg_ver_default 0
32431 +
32432 +/** @} */
32433 +
32434 +/** @name Access to registers and bit-fields */
32435 +
32436 +/**
32437 + * Dump core registers and SPRAM
32438 + */
32439 +extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * _core_if);
32440 +extern void dwc_otg_dump_spram(dwc_otg_core_if_t * _core_if);
32441 +extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t * _core_if);
32442 +extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t * _core_if);
32443 +
32444 +/**
32445 + * Get host negotiation status.
32446 + */
32447 +extern uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if);
32448 +
32449 +/**
32450 + * Get srp status
32451 + */
32452 +extern uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if);
32453 +
32454 +/**
32455 + * Set hnpreq bit in the GOTGCTL register.
32456 + */
32457 +extern void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val);
32458 +
32459 +/**
32460 + * Get Content of SNPSID register.
32461 + */
32462 +extern uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if);
32463 +
32464 +/**
32465 + * Get current mode.
32466 + * Returns 0 if in device mode, and 1 if in host mode.
32467 + */
32468 +extern uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if);
32469 +
32470 +/**
32471 + * Get value of hnpcapable field in the GUSBCFG register
32472 + */
32473 +extern uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if);
32474 +/**
32475 + * Set value of hnpcapable field in the GUSBCFG register
32476 + */
32477 +extern void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
32478 +
32479 +/**
32480 + * Get value of srpcapable field in the GUSBCFG register
32481 + */
32482 +extern uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if);
32483 +/**
32484 + * Set value of srpcapable field in the GUSBCFG register
32485 + */
32486 +extern void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
32487 +
32488 +/**
32489 + * Get value of devspeed field in the DCFG register
32490 + */
32491 +extern uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if);
32492 +/**
32493 + * Set value of devspeed field in the DCFG register
32494 + */
32495 +extern void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val);
32496 +
32497 +/**
32498 + * Get the value of busconnected field from the HPRT0 register
32499 + */
32500 +extern uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if);
32501 +
32502 +/**
32503 + * Gets the device enumeration Speed.
32504 + */
32505 +extern uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if);
32506 +
32507 +/**
32508 + * Get value of prtpwr field from the HPRT0 register
32509 + */
32510 +extern uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if);
32511 +
32512 +/**
32513 + * Get value of flag indicating core state - hibernated or not
32514 + */
32515 +extern uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if);
32516 +
32517 +/**
32518 + * Set value of prtpwr field from the HPRT0 register
32519 + */
32520 +extern void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val);
32521 +
32522 +/**
32523 + * Get value of prtsusp field from the HPRT0 regsiter
32524 + */
32525 +extern uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if);
32526 +/**
32527 + * Set value of prtpwr field from the HPRT0 register
32528 + */
32529 +extern void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val);
32530 +
32531 +/**
32532 + * Get value of ModeChTimEn field from the HCFG regsiter
32533 + */
32534 +extern uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if);
32535 +/**
32536 + * Set value of ModeChTimEn field from the HCFG regsiter
32537 + */
32538 +extern void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val);
32539 +
32540 +/**
32541 + * Get value of Fram Interval field from the HFIR regsiter
32542 + */
32543 +extern uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if);
32544 +/**
32545 + * Set value of Frame Interval field from the HFIR regsiter
32546 + */
32547 +extern void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val);
32548 +
32549 +/**
32550 + * Set value of prtres field from the HPRT0 register
32551 + *FIXME Remove?
32552 + */
32553 +extern void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val);
32554 +
32555 +/**
32556 + * Get value of rmtwkupsig bit in DCTL register
32557 + */
32558 +extern uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if);
32559 +
32560 +/**
32561 + * Get value of prt_sleep_sts field from the GLPMCFG register
32562 + */
32563 +extern uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if);
32564 +
32565 +/**
32566 + * Get value of rem_wkup_en field from the GLPMCFG register
32567 + */
32568 +extern uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if);
32569 +
32570 +/**
32571 + * Get value of appl_resp field from the GLPMCFG register
32572 + */
32573 +extern uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if);
32574 +/**
32575 + * Set value of appl_resp field from the GLPMCFG register
32576 + */
32577 +extern void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val);
32578 +
32579 +/**
32580 + * Get value of hsic_connect field from the GLPMCFG register
32581 + */
32582 +extern uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if);
32583 +/**
32584 + * Set value of hsic_connect field from the GLPMCFG register
32585 + */
32586 +extern void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val);
32587 +
32588 +/**
32589 + * Get value of inv_sel_hsic field from the GLPMCFG register.
32590 + */
32591 +extern uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if);
32592 +/**
32593 + * Set value of inv_sel_hsic field from the GLPMFG register.
32594 + */
32595 +extern void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val);
32596 +
32597 +/*
32598 + * Some functions for accessing registers
32599 + */
32600 +
32601 +/**
32602 + * GOTGCTL register
32603 + */
32604 +extern uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if);
32605 +extern void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val);
32606 +
32607 +/**
32608 + * GUSBCFG register
32609 + */
32610 +extern uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if);
32611 +extern void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val);
32612 +
32613 +/**
32614 + * GRXFSIZ register
32615 + */
32616 +extern uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if);
32617 +extern void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
32618 +
32619 +/**
32620 + * GNPTXFSIZ register
32621 + */
32622 +extern uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if);
32623 +extern void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
32624 +
32625 +extern uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if);
32626 +extern void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val);
32627 +
32628 +/**
32629 + * GGPIO register
32630 + */
32631 +extern uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if);
32632 +extern void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val);
32633 +
32634 +/**
32635 + * GUID register
32636 + */
32637 +extern uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if);
32638 +extern void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val);
32639 +
32640 +/**
32641 + * HPRT0 register
32642 + */
32643 +extern uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if);
32644 +extern void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val);
32645 +
32646 +/**
32647 + * GHPTXFSIZE
32648 + */
32649 +extern uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if);
32650 +
32651 +/** @} */
32652 +
32653 +#endif /* __DWC_CORE_IF_H__ */
32654 --- /dev/null
32655 +++ b/drivers/usb/host/dwc_otg/dwc_otg_dbg.h
32656 @@ -0,0 +1,117 @@
32657 +/* ==========================================================================
32658 + *
32659 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
32660 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
32661 + * otherwise expressly agreed to in writing between Synopsys and you.
32662 + *
32663 + * The Software IS NOT an item of Licensed Software or Licensed Product under
32664 + * any End User Software License Agreement or Agreement for Licensed Product
32665 + * with Synopsys or any supplement thereto. You are permitted to use and
32666 + * redistribute this Software in source and binary forms, with or without
32667 + * modification, provided that redistributions of source code must retain this
32668 + * notice. You may not view, use, disclose, copy or distribute this file or
32669 + * any information contained herein except pursuant to this license grant from
32670 + * Synopsys. If you do not agree with this notice, including the disclaimer
32671 + * below, then you are not authorized to use the Software.
32672 + *
32673 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
32674 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32675 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32676 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
32677 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
32678 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32679 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
32680 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32681 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32682 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32683 + * DAMAGE.
32684 + * ========================================================================== */
32685 +
32686 +#ifndef __DWC_OTG_DBG_H__
32687 +#define __DWC_OTG_DBG_H__
32688 +
32689 +/** @file
32690 + * This file defines debug levels.
32691 + * Debugging support vanishes in non-debug builds.
32692 + */
32693 +
32694 +/**
32695 + * The Debug Level bit-mask variable.
32696 + */
32697 +extern uint32_t g_dbg_lvl;
32698 +/**
32699 + * Set the Debug Level variable.
32700 + */
32701 +static inline uint32_t SET_DEBUG_LEVEL(const uint32_t new)
32702 +{
32703 + uint32_t old = g_dbg_lvl;
32704 + g_dbg_lvl = new;
32705 + return old;
32706 +}
32707 +
32708 +#define DBG_USER (0x1)
32709 +/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */
32710 +#define DBG_CIL (0x2)
32711 +/** When debug level has the DBG_CILV bit set, display CIL Verbose debug
32712 + * messages */
32713 +#define DBG_CILV (0x20)
32714 +/** When debug level has the DBG_PCD bit set, display PCD (Device) debug
32715 + * messages */
32716 +#define DBG_PCD (0x4)
32717 +/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug
32718 + * messages */
32719 +#define DBG_PCDV (0x40)
32720 +/** When debug level has the DBG_HCD bit set, display Host debug messages */
32721 +#define DBG_HCD (0x8)
32722 +/** When debug level has the DBG_HCDV bit set, display Verbose Host debug
32723 + * messages */
32724 +#define DBG_HCDV (0x80)
32725 +/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host
32726 + * mode. */
32727 +#define DBG_HCD_URB (0x800)
32728 +/** When debug level has the DBG_HCDI bit set, display host interrupt
32729 + * messages. */
32730 +#define DBG_HCDI (0x1000)
32731 +
32732 +/** When debug level has any bit set, display debug messages */
32733 +#define DBG_ANY (0xFF)
32734 +
32735 +/** All debug messages off */
32736 +#define DBG_OFF 0
32737 +
32738 +/** Prefix string for DWC_DEBUG print macros. */
32739 +#define USB_DWC "DWC_otg: "
32740 +
32741 +/**
32742 + * Print a debug message when the Global debug level variable contains
32743 + * the bit defined in <code>lvl</code>.
32744 + *
32745 + * @param[in] lvl - Debug level, use one of the DBG_ constants above.
32746 + * @param[in] x - like printf
32747 + *
32748 + * Example:<p>
32749 + * <code>
32750 + * DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr);
32751 + * </code>
32752 + * <br>
32753 + * results in:<br>
32754 + * <code>
32755 + * usb-DWC_otg: dwc_otg_cil_init(ca867000)
32756 + * </code>
32757 + */
32758 +#ifdef DEBUG
32759 +
32760 +# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)__DWC_DEBUG(USB_DWC x ); }while(0)
32761 +# define DWC_DEBUGP(x...) DWC_DEBUGPL(DBG_ANY, x )
32762 +
32763 +# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl)
32764 +
32765 +#else
32766 +
32767 +# define DWC_DEBUGPL(lvl, x...) do{}while(0)
32768 +# define DWC_DEBUGP(x...)
32769 +
32770 +# define CHK_DEBUG_LEVEL(level) (0)
32771 +
32772 +#endif /*DEBUG*/
32773 +#endif
32774 --- /dev/null
32775 +++ b/drivers/usb/host/dwc_otg/dwc_otg_driver.c
32776 @@ -0,0 +1,1756 @@
32777 +/* ==========================================================================
32778 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
32779 + * $Revision: #92 $
32780 + * $Date: 2012/08/10 $
32781 + * $Change: 2047372 $
32782 + *
32783 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
32784 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
32785 + * otherwise expressly agreed to in writing between Synopsys and you.
32786 + *
32787 + * The Software IS NOT an item of Licensed Software or Licensed Product under
32788 + * any End User Software License Agreement or Agreement for Licensed Product
32789 + * with Synopsys or any supplement thereto. You are permitted to use and
32790 + * redistribute this Software in source and binary forms, with or without
32791 + * modification, provided that redistributions of source code must retain this
32792 + * notice. You may not view, use, disclose, copy or distribute this file or
32793 + * any information contained herein except pursuant to this license grant from
32794 + * Synopsys. If you do not agree with this notice, including the disclaimer
32795 + * below, then you are not authorized to use the Software.
32796 + *
32797 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
32798 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32799 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32800 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
32801 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
32802 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32803 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
32804 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32805 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32806 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32807 + * DAMAGE.
32808 + * ========================================================================== */
32809 +
32810 +/** @file
32811 + * The dwc_otg_driver module provides the initialization and cleanup entry
32812 + * points for the DWC_otg driver. This module will be dynamically installed
32813 + * after Linux is booted using the insmod command. When the module is
32814 + * installed, the dwc_otg_driver_init function is called. When the module is
32815 + * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
32816 + *
32817 + * This module also defines a data structure for the dwc_otg_driver, which is
32818 + * used in conjunction with the standard ARM lm_device structure. These
32819 + * structures allow the OTG driver to comply with the standard Linux driver
32820 + * model in which devices and drivers are registered with a bus driver. This
32821 + * has the benefit that Linux can expose attributes of the driver and device
32822 + * in its special sysfs file system. Users can then read or write files in
32823 + * this file system to perform diagnostics on the driver components or the
32824 + * device.
32825 + */
32826 +
32827 +#include "dwc_otg_os_dep.h"
32828 +#include "dwc_os.h"
32829 +#include "dwc_otg_dbg.h"
32830 +#include "dwc_otg_driver.h"
32831 +#include "dwc_otg_attr.h"
32832 +#include "dwc_otg_core_if.h"
32833 +#include "dwc_otg_pcd_if.h"
32834 +#include "dwc_otg_hcd_if.h"
32835 +#include "dwc_otg_fiq_fsm.h"
32836 +
32837 +#define DWC_DRIVER_VERSION "3.00a 10-AUG-2012"
32838 +#define DWC_DRIVER_DESC "HS OTG USB Controller driver"
32839 +
32840 +bool microframe_schedule=true;
32841 +
32842 +static const char dwc_driver_name[] = "dwc_otg";
32843 +
32844 +
32845 +extern int pcd_init(
32846 +#ifdef LM_INTERFACE
32847 + struct lm_device *_dev
32848 +#elif defined(PCI_INTERFACE)
32849 + struct pci_dev *_dev
32850 +#elif defined(PLATFORM_INTERFACE)
32851 + struct platform_device *dev
32852 +#endif
32853 + );
32854 +extern int hcd_init(
32855 +#ifdef LM_INTERFACE
32856 + struct lm_device *_dev
32857 +#elif defined(PCI_INTERFACE)
32858 + struct pci_dev *_dev
32859 +#elif defined(PLATFORM_INTERFACE)
32860 + struct platform_device *dev
32861 +#endif
32862 + );
32863 +
32864 +extern int pcd_remove(
32865 +#ifdef LM_INTERFACE
32866 + struct lm_device *_dev
32867 +#elif defined(PCI_INTERFACE)
32868 + struct pci_dev *_dev
32869 +#elif defined(PLATFORM_INTERFACE)
32870 + struct platform_device *_dev
32871 +#endif
32872 + );
32873 +
32874 +extern void hcd_remove(
32875 +#ifdef LM_INTERFACE
32876 + struct lm_device *_dev
32877 +#elif defined(PCI_INTERFACE)
32878 + struct pci_dev *_dev
32879 +#elif defined(PLATFORM_INTERFACE)
32880 + struct platform_device *_dev
32881 +#endif
32882 + );
32883 +
32884 +extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
32885 +
32886 +/*-------------------------------------------------------------------------*/
32887 +/* Encapsulate the module parameter settings */
32888 +
32889 +struct dwc_otg_driver_module_params {
32890 + int32_t opt;
32891 + int32_t otg_cap;
32892 + int32_t dma_enable;
32893 + int32_t dma_desc_enable;
32894 + int32_t dma_burst_size;
32895 + int32_t speed;
32896 + int32_t host_support_fs_ls_low_power;
32897 + int32_t host_ls_low_power_phy_clk;
32898 + int32_t enable_dynamic_fifo;
32899 + int32_t data_fifo_size;
32900 + int32_t dev_rx_fifo_size;
32901 + int32_t dev_nperio_tx_fifo_size;
32902 + uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
32903 + int32_t host_rx_fifo_size;
32904 + int32_t host_nperio_tx_fifo_size;
32905 + int32_t host_perio_tx_fifo_size;
32906 + int32_t max_transfer_size;
32907 + int32_t max_packet_count;
32908 + int32_t host_channels;
32909 + int32_t dev_endpoints;
32910 + int32_t phy_type;
32911 + int32_t phy_utmi_width;
32912 + int32_t phy_ulpi_ddr;
32913 + int32_t phy_ulpi_ext_vbus;
32914 + int32_t i2c_enable;
32915 + int32_t ulpi_fs_ls;
32916 + int32_t ts_dline;
32917 + int32_t en_multiple_tx_fifo;
32918 + uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
32919 + uint32_t thr_ctl;
32920 + uint32_t tx_thr_length;
32921 + uint32_t rx_thr_length;
32922 + int32_t pti_enable;
32923 + int32_t mpi_enable;
32924 + int32_t lpm_enable;
32925 + int32_t ic_usb_cap;
32926 + int32_t ahb_thr_ratio;
32927 + int32_t power_down;
32928 + int32_t reload_ctl;
32929 + int32_t dev_out_nak;
32930 + int32_t cont_on_bna;
32931 + int32_t ahb_single;
32932 + int32_t otg_ver;
32933 + int32_t adp_enable;
32934 +};
32935 +
32936 +static struct dwc_otg_driver_module_params dwc_otg_module_params = {
32937 + .opt = -1,
32938 + .otg_cap = -1,
32939 + .dma_enable = -1,
32940 + .dma_desc_enable = -1,
32941 + .dma_burst_size = -1,
32942 + .speed = -1,
32943 + .host_support_fs_ls_low_power = -1,
32944 + .host_ls_low_power_phy_clk = -1,
32945 + .enable_dynamic_fifo = -1,
32946 + .data_fifo_size = -1,
32947 + .dev_rx_fifo_size = -1,
32948 + .dev_nperio_tx_fifo_size = -1,
32949 + .dev_perio_tx_fifo_size = {
32950 + /* dev_perio_tx_fifo_size_1 */
32951 + -1,
32952 + -1,
32953 + -1,
32954 + -1,
32955 + -1,
32956 + -1,
32957 + -1,
32958 + -1,
32959 + -1,
32960 + -1,
32961 + -1,
32962 + -1,
32963 + -1,
32964 + -1,
32965 + -1
32966 + /* 15 */
32967 + },
32968 + .host_rx_fifo_size = -1,
32969 + .host_nperio_tx_fifo_size = -1,
32970 + .host_perio_tx_fifo_size = -1,
32971 + .max_transfer_size = -1,
32972 + .max_packet_count = -1,
32973 + .host_channels = -1,
32974 + .dev_endpoints = -1,
32975 + .phy_type = -1,
32976 + .phy_utmi_width = -1,
32977 + .phy_ulpi_ddr = -1,
32978 + .phy_ulpi_ext_vbus = -1,
32979 + .i2c_enable = -1,
32980 + .ulpi_fs_ls = -1,
32981 + .ts_dline = -1,
32982 + .en_multiple_tx_fifo = -1,
32983 + .dev_tx_fifo_size = {
32984 + /* dev_tx_fifo_size */
32985 + -1,
32986 + -1,
32987 + -1,
32988 + -1,
32989 + -1,
32990 + -1,
32991 + -1,
32992 + -1,
32993 + -1,
32994 + -1,
32995 + -1,
32996 + -1,
32997 + -1,
32998 + -1,
32999 + -1
33000 + /* 15 */
33001 + },
33002 + .thr_ctl = -1,
33003 + .tx_thr_length = -1,
33004 + .rx_thr_length = -1,
33005 + .pti_enable = -1,
33006 + .mpi_enable = -1,
33007 + .lpm_enable = 0,
33008 + .ic_usb_cap = -1,
33009 + .ahb_thr_ratio = -1,
33010 + .power_down = -1,
33011 + .reload_ctl = -1,
33012 + .dev_out_nak = -1,
33013 + .cont_on_bna = -1,
33014 + .ahb_single = -1,
33015 + .otg_ver = -1,
33016 + .adp_enable = -1,
33017 +};
33018 +
33019 +//Global variable to switch the fiq fix on or off
33020 +bool fiq_enable = 1;
33021 +// Global variable to enable the split transaction fix
33022 +bool fiq_fsm_enable = true;
33023 +//Bulk split-transaction NAK holdoff in microframes
33024 +uint16_t nak_holdoff = 8;
33025 +
33026 +unsigned short fiq_fsm_mask = 0x07;
33027 +
33028 +/**
33029 + * This function shows the Driver Version.
33030 + */
33031 +static ssize_t version_show(struct device_driver *dev, char *buf)
33032 +{
33033 + return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
33034 + DWC_DRIVER_VERSION);
33035 +}
33036 +
33037 +static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
33038 +
33039 +/**
33040 + * Global Debug Level Mask.
33041 + */
33042 +uint32_t g_dbg_lvl = 0; /* OFF */
33043 +
33044 +/**
33045 + * This function shows the driver Debug Level.
33046 + */
33047 +static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
33048 +{
33049 + return sprintf(buf, "0x%0x\n", g_dbg_lvl);
33050 +}
33051 +
33052 +/**
33053 + * This function stores the driver Debug Level.
33054 + */
33055 +static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
33056 + size_t count)
33057 +{
33058 + g_dbg_lvl = simple_strtoul(buf, NULL, 16);
33059 + return count;
33060 +}
33061 +
33062 +static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
33063 + dbg_level_store);
33064 +
33065 +/**
33066 + * This function is called during module intialization
33067 + * to pass module parameters to the DWC_OTG CORE.
33068 + */
33069 +static int set_parameters(dwc_otg_core_if_t * core_if)
33070 +{
33071 + int retval = 0;
33072 + int i;
33073 +
33074 + if (dwc_otg_module_params.otg_cap != -1) {
33075 + retval +=
33076 + dwc_otg_set_param_otg_cap(core_if,
33077 + dwc_otg_module_params.otg_cap);
33078 + }
33079 + if (dwc_otg_module_params.dma_enable != -1) {
33080 + retval +=
33081 + dwc_otg_set_param_dma_enable(core_if,
33082 + dwc_otg_module_params.
33083 + dma_enable);
33084 + }
33085 + if (dwc_otg_module_params.dma_desc_enable != -1) {
33086 + retval +=
33087 + dwc_otg_set_param_dma_desc_enable(core_if,
33088 + dwc_otg_module_params.
33089 + dma_desc_enable);
33090 + }
33091 + if (dwc_otg_module_params.opt != -1) {
33092 + retval +=
33093 + dwc_otg_set_param_opt(core_if, dwc_otg_module_params.opt);
33094 + }
33095 + if (dwc_otg_module_params.dma_burst_size != -1) {
33096 + retval +=
33097 + dwc_otg_set_param_dma_burst_size(core_if,
33098 + dwc_otg_module_params.
33099 + dma_burst_size);
33100 + }
33101 + if (dwc_otg_module_params.host_support_fs_ls_low_power != -1) {
33102 + retval +=
33103 + dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
33104 + dwc_otg_module_params.
33105 + host_support_fs_ls_low_power);
33106 + }
33107 + if (dwc_otg_module_params.enable_dynamic_fifo != -1) {
33108 + retval +=
33109 + dwc_otg_set_param_enable_dynamic_fifo(core_if,
33110 + dwc_otg_module_params.
33111 + enable_dynamic_fifo);
33112 + }
33113 + if (dwc_otg_module_params.data_fifo_size != -1) {
33114 + retval +=
33115 + dwc_otg_set_param_data_fifo_size(core_if,
33116 + dwc_otg_module_params.
33117 + data_fifo_size);
33118 + }
33119 + if (dwc_otg_module_params.dev_rx_fifo_size != -1) {
33120 + retval +=
33121 + dwc_otg_set_param_dev_rx_fifo_size(core_if,
33122 + dwc_otg_module_params.
33123 + dev_rx_fifo_size);
33124 + }
33125 + if (dwc_otg_module_params.dev_nperio_tx_fifo_size != -1) {
33126 + retval +=
33127 + dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
33128 + dwc_otg_module_params.
33129 + dev_nperio_tx_fifo_size);
33130 + }
33131 + if (dwc_otg_module_params.host_rx_fifo_size != -1) {
33132 + retval +=
33133 + dwc_otg_set_param_host_rx_fifo_size(core_if,
33134 + dwc_otg_module_params.host_rx_fifo_size);
33135 + }
33136 + if (dwc_otg_module_params.host_nperio_tx_fifo_size != -1) {
33137 + retval +=
33138 + dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
33139 + dwc_otg_module_params.
33140 + host_nperio_tx_fifo_size);
33141 + }
33142 + if (dwc_otg_module_params.host_perio_tx_fifo_size != -1) {
33143 + retval +=
33144 + dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
33145 + dwc_otg_module_params.
33146 + host_perio_tx_fifo_size);
33147 + }
33148 + if (dwc_otg_module_params.max_transfer_size != -1) {
33149 + retval +=
33150 + dwc_otg_set_param_max_transfer_size(core_if,
33151 + dwc_otg_module_params.
33152 + max_transfer_size);
33153 + }
33154 + if (dwc_otg_module_params.max_packet_count != -1) {
33155 + retval +=
33156 + dwc_otg_set_param_max_packet_count(core_if,
33157 + dwc_otg_module_params.
33158 + max_packet_count);
33159 + }
33160 + if (dwc_otg_module_params.host_channels != -1) {
33161 + retval +=
33162 + dwc_otg_set_param_host_channels(core_if,
33163 + dwc_otg_module_params.
33164 + host_channels);
33165 + }
33166 + if (dwc_otg_module_params.dev_endpoints != -1) {
33167 + retval +=
33168 + dwc_otg_set_param_dev_endpoints(core_if,
33169 + dwc_otg_module_params.
33170 + dev_endpoints);
33171 + }
33172 + if (dwc_otg_module_params.phy_type != -1) {
33173 + retval +=
33174 + dwc_otg_set_param_phy_type(core_if,
33175 + dwc_otg_module_params.phy_type);
33176 + }
33177 + if (dwc_otg_module_params.speed != -1) {
33178 + retval +=
33179 + dwc_otg_set_param_speed(core_if,
33180 + dwc_otg_module_params.speed);
33181 + }
33182 + if (dwc_otg_module_params.host_ls_low_power_phy_clk != -1) {
33183 + retval +=
33184 + dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
33185 + dwc_otg_module_params.
33186 + host_ls_low_power_phy_clk);
33187 + }
33188 + if (dwc_otg_module_params.phy_ulpi_ddr != -1) {
33189 + retval +=
33190 + dwc_otg_set_param_phy_ulpi_ddr(core_if,
33191 + dwc_otg_module_params.
33192 + phy_ulpi_ddr);
33193 + }
33194 + if (dwc_otg_module_params.phy_ulpi_ext_vbus != -1) {
33195 + retval +=
33196 + dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
33197 + dwc_otg_module_params.
33198 + phy_ulpi_ext_vbus);
33199 + }
33200 + if (dwc_otg_module_params.phy_utmi_width != -1) {
33201 + retval +=
33202 + dwc_otg_set_param_phy_utmi_width(core_if,
33203 + dwc_otg_module_params.
33204 + phy_utmi_width);
33205 + }
33206 + if (dwc_otg_module_params.ulpi_fs_ls != -1) {
33207 + retval +=
33208 + dwc_otg_set_param_ulpi_fs_ls(core_if,
33209 + dwc_otg_module_params.ulpi_fs_ls);
33210 + }
33211 + if (dwc_otg_module_params.ts_dline != -1) {
33212 + retval +=
33213 + dwc_otg_set_param_ts_dline(core_if,
33214 + dwc_otg_module_params.ts_dline);
33215 + }
33216 + if (dwc_otg_module_params.i2c_enable != -1) {
33217 + retval +=
33218 + dwc_otg_set_param_i2c_enable(core_if,
33219 + dwc_otg_module_params.
33220 + i2c_enable);
33221 + }
33222 + if (dwc_otg_module_params.en_multiple_tx_fifo != -1) {
33223 + retval +=
33224 + dwc_otg_set_param_en_multiple_tx_fifo(core_if,
33225 + dwc_otg_module_params.
33226 + en_multiple_tx_fifo);
33227 + }
33228 + for (i = 0; i < 15; i++) {
33229 + if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
33230 + retval +=
33231 + dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
33232 + dwc_otg_module_params.
33233 + dev_perio_tx_fifo_size
33234 + [i], i);
33235 + }
33236 + }
33237 +
33238 + for (i = 0; i < 15; i++) {
33239 + if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
33240 + retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
33241 + dwc_otg_module_params.
33242 + dev_tx_fifo_size
33243 + [i], i);
33244 + }
33245 + }
33246 + if (dwc_otg_module_params.thr_ctl != -1) {
33247 + retval +=
33248 + dwc_otg_set_param_thr_ctl(core_if,
33249 + dwc_otg_module_params.thr_ctl);
33250 + }
33251 + if (dwc_otg_module_params.mpi_enable != -1) {
33252 + retval +=
33253 + dwc_otg_set_param_mpi_enable(core_if,
33254 + dwc_otg_module_params.
33255 + mpi_enable);
33256 + }
33257 + if (dwc_otg_module_params.pti_enable != -1) {
33258 + retval +=
33259 + dwc_otg_set_param_pti_enable(core_if,
33260 + dwc_otg_module_params.
33261 + pti_enable);
33262 + }
33263 + if (dwc_otg_module_params.lpm_enable != -1) {
33264 + retval +=
33265 + dwc_otg_set_param_lpm_enable(core_if,
33266 + dwc_otg_module_params.
33267 + lpm_enable);
33268 + }
33269 + if (dwc_otg_module_params.ic_usb_cap != -1) {
33270 + retval +=
33271 + dwc_otg_set_param_ic_usb_cap(core_if,
33272 + dwc_otg_module_params.
33273 + ic_usb_cap);
33274 + }
33275 + if (dwc_otg_module_params.tx_thr_length != -1) {
33276 + retval +=
33277 + dwc_otg_set_param_tx_thr_length(core_if,
33278 + dwc_otg_module_params.tx_thr_length);
33279 + }
33280 + if (dwc_otg_module_params.rx_thr_length != -1) {
33281 + retval +=
33282 + dwc_otg_set_param_rx_thr_length(core_if,
33283 + dwc_otg_module_params.
33284 + rx_thr_length);
33285 + }
33286 + if (dwc_otg_module_params.ahb_thr_ratio != -1) {
33287 + retval +=
33288 + dwc_otg_set_param_ahb_thr_ratio(core_if,
33289 + dwc_otg_module_params.ahb_thr_ratio);
33290 + }
33291 + if (dwc_otg_module_params.power_down != -1) {
33292 + retval +=
33293 + dwc_otg_set_param_power_down(core_if,
33294 + dwc_otg_module_params.power_down);
33295 + }
33296 + if (dwc_otg_module_params.reload_ctl != -1) {
33297 + retval +=
33298 + dwc_otg_set_param_reload_ctl(core_if,
33299 + dwc_otg_module_params.reload_ctl);
33300 + }
33301 +
33302 + if (dwc_otg_module_params.dev_out_nak != -1) {
33303 + retval +=
33304 + dwc_otg_set_param_dev_out_nak(core_if,
33305 + dwc_otg_module_params.dev_out_nak);
33306 + }
33307 +
33308 + if (dwc_otg_module_params.cont_on_bna != -1) {
33309 + retval +=
33310 + dwc_otg_set_param_cont_on_bna(core_if,
33311 + dwc_otg_module_params.cont_on_bna);
33312 + }
33313 +
33314 + if (dwc_otg_module_params.ahb_single != -1) {
33315 + retval +=
33316 + dwc_otg_set_param_ahb_single(core_if,
33317 + dwc_otg_module_params.ahb_single);
33318 + }
33319 +
33320 + if (dwc_otg_module_params.otg_ver != -1) {
33321 + retval +=
33322 + dwc_otg_set_param_otg_ver(core_if,
33323 + dwc_otg_module_params.otg_ver);
33324 + }
33325 + if (dwc_otg_module_params.adp_enable != -1) {
33326 + retval +=
33327 + dwc_otg_set_param_adp_enable(core_if,
33328 + dwc_otg_module_params.
33329 + adp_enable);
33330 + }
33331 + return retval;
33332 +}
33333 +
33334 +/**
33335 + * This function is the top level interrupt handler for the Common
33336 + * (Device and host modes) interrupts.
33337 + */
33338 +static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
33339 +{
33340 + int32_t retval = IRQ_NONE;
33341 +
33342 + retval = dwc_otg_handle_common_intr(dev);
33343 + if (retval != 0) {
33344 + S3C2410X_CLEAR_EINTPEND();
33345 + }
33346 + return IRQ_RETVAL(retval);
33347 +}
33348 +
33349 +/**
33350 + * This function is called when a lm_device is unregistered with the
33351 + * dwc_otg_driver. This happens, for example, when the rmmod command is
33352 + * executed. The device may or may not be electrically present. If it is
33353 + * present, the driver stops device processing. Any resources used on behalf
33354 + * of this device are freed.
33355 + *
33356 + * @param _dev
33357 + */
33358 +#ifdef LM_INTERFACE
33359 +#define REM_RETVAL(n)
33360 +static void dwc_otg_driver_remove( struct lm_device *_dev )
33361 +{ dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
33362 +#elif defined(PCI_INTERFACE)
33363 +#define REM_RETVAL(n)
33364 +static void dwc_otg_driver_remove( struct pci_dev *_dev )
33365 +{ dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
33366 +#elif defined(PLATFORM_INTERFACE)
33367 +#define REM_RETVAL(n) n
33368 +static int dwc_otg_driver_remove( struct platform_device *_dev )
33369 +{ dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev);
33370 +#endif
33371 +
33372 + DWC_DEBUGPL(DBG_ANY, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev);
33373 +
33374 + if (!otg_dev) {
33375 + /* Memory allocation for the dwc_otg_device failed. */
33376 + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
33377 + return REM_RETVAL(-ENOMEM);
33378 + }
33379 +#ifndef DWC_DEVICE_ONLY
33380 + if (otg_dev->hcd) {
33381 + hcd_remove(_dev);
33382 + } else {
33383 + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
33384 + return REM_RETVAL(-EINVAL);
33385 + }
33386 +#endif
33387 +
33388 +#ifndef DWC_HOST_ONLY
33389 + if (otg_dev->pcd) {
33390 + pcd_remove(_dev);
33391 + } else {
33392 + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
33393 + return REM_RETVAL(-EINVAL);
33394 + }
33395 +#endif
33396 + /*
33397 + * Free the IRQ
33398 + */
33399 + if (otg_dev->common_irq_installed) {
33400 +#ifdef PLATFORM_INTERFACE
33401 + free_irq(platform_get_irq(_dev, 0), otg_dev);
33402 +#else
33403 + free_irq(_dev->irq, otg_dev);
33404 +#endif
33405 + } else {
33406 + DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n", __func__);
33407 + return REM_RETVAL(-ENXIO);
33408 + }
33409 +
33410 + if (otg_dev->core_if) {
33411 + dwc_otg_cil_remove(otg_dev->core_if);
33412 + } else {
33413 + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
33414 + return REM_RETVAL(-ENXIO);
33415 + }
33416 +
33417 + /*
33418 + * Remove the device attributes
33419 + */
33420 + dwc_otg_attr_remove(_dev);
33421 +
33422 + /*
33423 + * Return the memory.
33424 + */
33425 + if (otg_dev->os_dep.base) {
33426 + iounmap(otg_dev->os_dep.base);
33427 + }
33428 + DWC_FREE(otg_dev);
33429 +
33430 + /*
33431 + * Clear the drvdata pointer.
33432 + */
33433 +#ifdef LM_INTERFACE
33434 + lm_set_drvdata(_dev, 0);
33435 +#elif defined(PCI_INTERFACE)
33436 + release_mem_region(otg_dev->os_dep.rsrc_start,
33437 + otg_dev->os_dep.rsrc_len);
33438 + pci_set_drvdata(_dev, 0);
33439 +#elif defined(PLATFORM_INTERFACE)
33440 + platform_set_drvdata(_dev, 0);
33441 +#endif
33442 + return REM_RETVAL(0);
33443 +}
33444 +
33445 +/**
33446 + * This function is called when an lm_device is bound to a
33447 + * dwc_otg_driver. It creates the driver components required to
33448 + * control the device (CIL, HCD, and PCD) and it initializes the
33449 + * device. The driver components are stored in a dwc_otg_device
33450 + * structure. A reference to the dwc_otg_device is saved in the
33451 + * lm_device. This allows the driver to access the dwc_otg_device
33452 + * structure on subsequent calls to driver methods for this device.
33453 + *
33454 + * @param _dev Bus device
33455 + */
33456 +static int dwc_otg_driver_probe(
33457 +#ifdef LM_INTERFACE
33458 + struct lm_device *_dev
33459 +#elif defined(PCI_INTERFACE)
33460 + struct pci_dev *_dev,
33461 + const struct pci_device_id *id
33462 +#elif defined(PLATFORM_INTERFACE)
33463 + struct platform_device *_dev
33464 +#endif
33465 + )
33466 +{
33467 + int retval = 0;
33468 + dwc_otg_device_t *dwc_otg_device;
33469 + int devirq;
33470 +
33471 + dev_dbg(&_dev->dev, "dwc_otg_driver_probe(%p)\n", _dev);
33472 +#ifdef LM_INTERFACE
33473 + dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)_dev->resource.start);
33474 +#elif defined(PCI_INTERFACE)
33475 + if (!id) {
33476 + DWC_ERROR("Invalid pci_device_id %p", id);
33477 + return -EINVAL;
33478 + }
33479 +
33480 + if (!_dev || (pci_enable_device(_dev) < 0)) {
33481 + DWC_ERROR("Invalid pci_device %p", _dev);
33482 + return -ENODEV;
33483 + }
33484 + dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)pci_resource_start(_dev,0));
33485 + /* other stuff needed as well? */
33486 +
33487 +#elif defined(PLATFORM_INTERFACE)
33488 + dev_dbg(&_dev->dev, "start=0x%08x (len 0x%x)\n",
33489 + (unsigned)_dev->resource->start,
33490 + (unsigned)(_dev->resource->end - _dev->resource->start));
33491 +#endif
33492 +
33493 + dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
33494 +
33495 + if (!dwc_otg_device) {
33496 + dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
33497 + return -ENOMEM;
33498 + }
33499 +
33500 + memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
33501 + dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
33502 +
33503 + /*
33504 + * Map the DWC_otg Core memory into virtual address space.
33505 + */
33506 +#ifdef LM_INTERFACE
33507 + dwc_otg_device->os_dep.base = ioremap(_dev->resource.start, SZ_256K);
33508 +
33509 + if (!dwc_otg_device->os_dep.base) {
33510 + dev_err(&_dev->dev, "ioremap() failed\n");
33511 + DWC_FREE(dwc_otg_device);
33512 + return -ENOMEM;
33513 + }
33514 + dev_dbg(&_dev->dev, "base=0x%08x\n",
33515 + (unsigned)dwc_otg_device->os_dep.base);
33516 +#elif defined(PCI_INTERFACE)
33517 + _dev->current_state = PCI_D0;
33518 + _dev->dev.power.power_state = PMSG_ON;
33519 +
33520 + if (!_dev->irq) {
33521 + DWC_ERROR("Found HC with no IRQ. Check BIOS/PCI %s setup!",
33522 + pci_name(_dev));
33523 + iounmap(dwc_otg_device->os_dep.base);
33524 + DWC_FREE(dwc_otg_device);
33525 + return -ENODEV;
33526 + }
33527 +
33528 + dwc_otg_device->os_dep.rsrc_start = pci_resource_start(_dev, 0);
33529 + dwc_otg_device->os_dep.rsrc_len = pci_resource_len(_dev, 0);
33530 + DWC_DEBUGPL(DBG_ANY, "PCI resource: start=%08x, len=%08x\n",
33531 + (unsigned)dwc_otg_device->os_dep.rsrc_start,
33532 + (unsigned)dwc_otg_device->os_dep.rsrc_len);
33533 + if (!request_mem_region
33534 + (dwc_otg_device->os_dep.rsrc_start, dwc_otg_device->os_dep.rsrc_len,
33535 + "dwc_otg")) {
33536 + dev_dbg(&_dev->dev, "error requesting memory\n");
33537 + iounmap(dwc_otg_device->os_dep.base);
33538 + DWC_FREE(dwc_otg_device);
33539 + return -EFAULT;
33540 + }
33541 +
33542 + dwc_otg_device->os_dep.base =
33543 + ioremap_nocache(dwc_otg_device->os_dep.rsrc_start,
33544 + dwc_otg_device->os_dep.rsrc_len);
33545 + if (dwc_otg_device->os_dep.base == NULL) {
33546 + dev_dbg(&_dev->dev, "error mapping memory\n");
33547 + release_mem_region(dwc_otg_device->os_dep.rsrc_start,
33548 + dwc_otg_device->os_dep.rsrc_len);
33549 + iounmap(dwc_otg_device->os_dep.base);
33550 + DWC_FREE(dwc_otg_device);
33551 + return -EFAULT;
33552 + }
33553 + dev_dbg(&_dev->dev, "base=0x%p (before adjust) \n",
33554 + dwc_otg_device->os_dep.base);
33555 + dwc_otg_device->os_dep.base = (char *)dwc_otg_device->os_dep.base;
33556 + dev_dbg(&_dev->dev, "base=0x%p (after adjust) \n",
33557 + dwc_otg_device->os_dep.base);
33558 + dev_dbg(&_dev->dev, "%s: mapped PA 0x%x to VA 0x%p\n", __func__,
33559 + (unsigned)dwc_otg_device->os_dep.rsrc_start,
33560 + dwc_otg_device->os_dep.base);
33561 +
33562 + pci_set_master(_dev);
33563 + pci_set_drvdata(_dev, dwc_otg_device);
33564 +#elif defined(PLATFORM_INTERFACE)
33565 + DWC_DEBUGPL(DBG_ANY,"Platform resource: start=%08x, len=%08x\n",
33566 + _dev->resource->start,
33567 + _dev->resource->end - _dev->resource->start + 1);
33568 +#if 1
33569 + if (!request_mem_region(_dev->resource[0].start,
33570 + _dev->resource[0].end - _dev->resource[0].start + 1,
33571 + "dwc_otg")) {
33572 + dev_dbg(&_dev->dev, "error reserving mapped memory\n");
33573 + retval = -EFAULT;
33574 + goto fail;
33575 + }
33576 +
33577 + dwc_otg_device->os_dep.base = ioremap_nocache(_dev->resource[0].start,
33578 + _dev->resource[0].end -
33579 + _dev->resource[0].start+1);
33580 + if (fiq_enable)
33581 + {
33582 + if (!request_mem_region(_dev->resource[1].start,
33583 + _dev->resource[1].end - _dev->resource[1].start + 1,
33584 + "dwc_otg")) {
33585 + dev_dbg(&_dev->dev, "error reserving mapped memory\n");
33586 + retval = -EFAULT;
33587 + goto fail;
33588 + }
33589 +
33590 + dwc_otg_device->os_dep.mphi_base = ioremap_nocache(_dev->resource[1].start,
33591 + _dev->resource[1].end -
33592 + _dev->resource[1].start + 1);
33593 + }
33594 +
33595 +#else
33596 + {
33597 + struct map_desc desc = {
33598 + .virtual = IO_ADDRESS((unsigned)_dev->resource->start),
33599 + .pfn = __phys_to_pfn((unsigned)_dev->resource->start),
33600 + .length = SZ_128K,
33601 + .type = MT_DEVICE
33602 + };
33603 + iotable_init(&desc, 1);
33604 + dwc_otg_device->os_dep.base = (void *)desc.virtual;
33605 + }
33606 +#endif
33607 + if (!dwc_otg_device->os_dep.base) {
33608 + dev_err(&_dev->dev, "ioremap() failed\n");
33609 + retval = -ENOMEM;
33610 + goto fail;
33611 + }
33612 + dev_dbg(&_dev->dev, "base=0x%08x\n",
33613 + (unsigned)dwc_otg_device->os_dep.base);
33614 +#endif
33615 +
33616 + /*
33617 + * Initialize driver data to point to the global DWC_otg
33618 + * Device structure.
33619 + */
33620 +#ifdef LM_INTERFACE
33621 + lm_set_drvdata(_dev, dwc_otg_device);
33622 +#elif defined(PLATFORM_INTERFACE)
33623 + platform_set_drvdata(_dev, dwc_otg_device);
33624 +#endif
33625 + dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
33626 +
33627 + dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
33628 + DWC_DEBUGPL(DBG_HCDV, "probe of device %p given core_if %p\n",
33629 + dwc_otg_device, dwc_otg_device->core_if);//GRAYG
33630 +
33631 + if (!dwc_otg_device->core_if) {
33632 + dev_err(&_dev->dev, "CIL initialization failed!\n");
33633 + retval = -ENOMEM;
33634 + goto fail;
33635 + }
33636 +
33637 + dev_dbg(&_dev->dev, "Calling get_gsnpsid\n");
33638 + /*
33639 + * Attempt to ensure this device is really a DWC_otg Controller.
33640 + * Read and verify the SNPSID register contents. The value should be
33641 + * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
33642 + * as in "OTG version 2.XX" or "OTG version 3.XX".
33643 + */
33644 +
33645 + if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F542000) &&
33646 + ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F543000)) {
33647 + dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
33648 + dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
33649 + retval = -EINVAL;
33650 + goto fail;
33651 + }
33652 +
33653 + /*
33654 + * Validate parameter values.
33655 + */
33656 + dev_dbg(&_dev->dev, "Calling set_parameters\n");
33657 + if (set_parameters(dwc_otg_device->core_if)) {
33658 + retval = -EINVAL;
33659 + goto fail;
33660 + }
33661 +
33662 + /*
33663 + * Create Device Attributes in sysfs
33664 + */
33665 + dev_dbg(&_dev->dev, "Calling attr_create\n");
33666 + dwc_otg_attr_create(_dev);
33667 +
33668 + /*
33669 + * Disable the global interrupt until all the interrupt
33670 + * handlers are installed.
33671 + */
33672 + dev_dbg(&_dev->dev, "Calling disable_global_interrupts\n");
33673 + dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
33674 +
33675 + /*
33676 + * Install the interrupt handler for the common interrupts before
33677 + * enabling common interrupts in core_init below.
33678 + */
33679 +
33680 +#if defined(PLATFORM_INTERFACE)
33681 + devirq = platform_get_irq(_dev, fiq_enable ? 0 : 1);
33682 +#else
33683 + devirq = _dev->irq;
33684 +#endif
33685 + DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
33686 + devirq);
33687 + dev_dbg(&_dev->dev, "Calling request_irq(%d)\n", devirq);
33688 + retval = request_irq(devirq, dwc_otg_common_irq,
33689 + IRQF_SHARED,
33690 + "dwc_otg", dwc_otg_device);
33691 + if (retval) {
33692 + DWC_ERROR("request of irq%d failed\n", devirq);
33693 + retval = -EBUSY;
33694 + goto fail;
33695 + } else {
33696 + dwc_otg_device->common_irq_installed = 1;
33697 + }
33698 +
33699 +#ifndef IRQF_TRIGGER_LOW
33700 +#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
33701 + dev_dbg(&_dev->dev, "Calling set_irq_type\n");
33702 + set_irq_type(devirq,
33703 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
33704 + IRQT_LOW
33705 +#else
33706 + IRQ_TYPE_LEVEL_LOW
33707 +#endif
33708 + );
33709 +#endif
33710 +#endif /*IRQF_TRIGGER_LOW*/
33711 +
33712 + /*
33713 + * Initialize the DWC_otg core.
33714 + */
33715 + dev_dbg(&_dev->dev, "Calling dwc_otg_core_init\n");
33716 + dwc_otg_core_init(dwc_otg_device->core_if);
33717 +
33718 +#ifndef DWC_HOST_ONLY
33719 + /*
33720 + * Initialize the PCD
33721 + */
33722 + dev_dbg(&_dev->dev, "Calling pcd_init\n");
33723 + retval = pcd_init(_dev);
33724 + if (retval != 0) {
33725 + DWC_ERROR("pcd_init failed\n");
33726 + dwc_otg_device->pcd = NULL;
33727 + goto fail;
33728 + }
33729 +#endif
33730 +#ifndef DWC_DEVICE_ONLY
33731 + /*
33732 + * Initialize the HCD
33733 + */
33734 + dev_dbg(&_dev->dev, "Calling hcd_init\n");
33735 + retval = hcd_init(_dev);
33736 + if (retval != 0) {
33737 + DWC_ERROR("hcd_init failed\n");
33738 + dwc_otg_device->hcd = NULL;
33739 + goto fail;
33740 + }
33741 +#endif
33742 + /* Recover from drvdata having been overwritten by hcd_init() */
33743 +#ifdef LM_INTERFACE
33744 + lm_set_drvdata(_dev, dwc_otg_device);
33745 +#elif defined(PLATFORM_INTERFACE)
33746 + platform_set_drvdata(_dev, dwc_otg_device);
33747 +#elif defined(PCI_INTERFACE)
33748 + pci_set_drvdata(_dev, dwc_otg_device);
33749 + dwc_otg_device->os_dep.pcidev = _dev;
33750 +#endif
33751 +
33752 + /*
33753 + * Enable the global interrupt after all the interrupt
33754 + * handlers are installed if there is no ADP support else
33755 + * perform initial actions required for Internal ADP logic.
33756 + */
33757 + if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
33758 + dev_dbg(&_dev->dev, "Calling enable_global_interrupts\n");
33759 + dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
33760 + dev_dbg(&_dev->dev, "Done\n");
33761 + } else
33762 + dwc_otg_adp_start(dwc_otg_device->core_if,
33763 + dwc_otg_is_host_mode(dwc_otg_device->core_if));
33764 +
33765 + return 0;
33766 +
33767 +fail:
33768 + dwc_otg_driver_remove(_dev);
33769 + return retval;
33770 +}
33771 +
33772 +/**
33773 + * This structure defines the methods to be called by a bus driver
33774 + * during the lifecycle of a device on that bus. Both drivers and
33775 + * devices are registered with a bus driver. The bus driver matches
33776 + * devices to drivers based on information in the device and driver
33777 + * structures.
33778 + *
33779 + * The probe function is called when the bus driver matches a device
33780 + * to this driver. The remove function is called when a device is
33781 + * unregistered with the bus driver.
33782 + */
33783 +#ifdef LM_INTERFACE
33784 +static struct lm_driver dwc_otg_driver = {
33785 + .drv = {.name = (char *)dwc_driver_name,},
33786 + .probe = dwc_otg_driver_probe,
33787 + .remove = dwc_otg_driver_remove,
33788 + // 'suspend' and 'resume' absent
33789 +};
33790 +#elif defined(PCI_INTERFACE)
33791 +static const struct pci_device_id pci_ids[] = { {
33792 + PCI_DEVICE(0x16c3, 0xabcd),
33793 + .driver_data =
33794 + (unsigned long)0xdeadbeef,
33795 + }, { /* end: all zeroes */ }
33796 +};
33797 +
33798 +MODULE_DEVICE_TABLE(pci, pci_ids);
33799 +
33800 +/* pci driver glue; this is a "new style" PCI driver module */
33801 +static struct pci_driver dwc_otg_driver = {
33802 + .name = "dwc_otg",
33803 + .id_table = pci_ids,
33804 +
33805 + .probe = dwc_otg_driver_probe,
33806 + .remove = dwc_otg_driver_remove,
33807 +
33808 + .driver = {
33809 + .name = (char *)dwc_driver_name,
33810 + },
33811 +};
33812 +#elif defined(PLATFORM_INTERFACE)
33813 +static struct platform_device_id platform_ids[] = {
33814 + {
33815 + .name = "bcm2708_usb",
33816 + .driver_data = (kernel_ulong_t) 0xdeadbeef,
33817 + },
33818 + { /* end: all zeroes */ }
33819 +};
33820 +MODULE_DEVICE_TABLE(platform, platform_ids);
33821 +
33822 +static const struct of_device_id dwc_otg_of_match_table[] = {
33823 + { .compatible = "brcm,bcm2708-usb", },
33824 + {},
33825 +};
33826 +MODULE_DEVICE_TABLE(of, dwc_otg_of_match_table);
33827 +
33828 +static struct platform_driver dwc_otg_driver = {
33829 + .driver = {
33830 + .name = (char *)dwc_driver_name,
33831 + .of_match_table = dwc_otg_of_match_table,
33832 + },
33833 + .id_table = platform_ids,
33834 +
33835 + .probe = dwc_otg_driver_probe,
33836 + .remove = dwc_otg_driver_remove,
33837 + // no 'shutdown', 'suspend', 'resume', 'suspend_late' or 'resume_early'
33838 +};
33839 +#endif
33840 +
33841 +/**
33842 + * This function is called when the dwc_otg_driver is installed with the
33843 + * insmod command. It registers the dwc_otg_driver structure with the
33844 + * appropriate bus driver. This will cause the dwc_otg_driver_probe function
33845 + * to be called. In addition, the bus driver will automatically expose
33846 + * attributes defined for the device and driver in the special sysfs file
33847 + * system.
33848 + *
33849 + * @return
33850 + */
33851 +static int __init dwc_otg_driver_init(void)
33852 +{
33853 + int retval = 0;
33854 + int error;
33855 + struct device_driver *drv;
33856 +
33857 + if(fiq_fsm_enable && !fiq_enable) {
33858 + printk(KERN_WARNING "dwc_otg: fiq_fsm_enable was set without fiq_enable! Correcting.\n");
33859 + fiq_enable = 1;
33860 + }
33861 +
33862 + printk(KERN_INFO "%s: version %s (%s bus)\n", dwc_driver_name,
33863 + DWC_DRIVER_VERSION,
33864 +#ifdef LM_INTERFACE
33865 + "logicmodule");
33866 + retval = lm_driver_register(&dwc_otg_driver);
33867 + drv = &dwc_otg_driver.drv;
33868 +#elif defined(PCI_INTERFACE)
33869 + "pci");
33870 + retval = pci_register_driver(&dwc_otg_driver);
33871 + drv = &dwc_otg_driver.driver;
33872 +#elif defined(PLATFORM_INTERFACE)
33873 + "platform");
33874 + retval = platform_driver_register(&dwc_otg_driver);
33875 + drv = &dwc_otg_driver.driver;
33876 +#endif
33877 + if (retval < 0) {
33878 + printk(KERN_ERR "%s retval=%d\n", __func__, retval);
33879 + return retval;
33880 + }
33881 + printk(KERN_DEBUG "dwc_otg: FIQ %s\n", fiq_enable ? "enabled":"disabled");
33882 + printk(KERN_DEBUG "dwc_otg: NAK holdoff %s\n", nak_holdoff ? "enabled":"disabled");
33883 + printk(KERN_DEBUG "dwc_otg: FIQ split-transaction FSM %s\n", fiq_fsm_enable ? "enabled":"disabled");
33884 +
33885 + error = driver_create_file(drv, &driver_attr_version);
33886 +#ifdef DEBUG
33887 + error = driver_create_file(drv, &driver_attr_debuglevel);
33888 +#endif
33889 + return retval;
33890 +}
33891 +
33892 +module_init(dwc_otg_driver_init);
33893 +
33894 +/**
33895 + * This function is called when the driver is removed from the kernel
33896 + * with the rmmod command. The driver unregisters itself with its bus
33897 + * driver.
33898 + *
33899 + */
33900 +static void __exit dwc_otg_driver_cleanup(void)
33901 +{
33902 + printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
33903 +
33904 +#ifdef LM_INTERFACE
33905 + driver_remove_file(&dwc_otg_driver.drv, &driver_attr_debuglevel);
33906 + driver_remove_file(&dwc_otg_driver.drv, &driver_attr_version);
33907 + lm_driver_unregister(&dwc_otg_driver);
33908 +#elif defined(PCI_INTERFACE)
33909 + driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
33910 + driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
33911 + pci_unregister_driver(&dwc_otg_driver);
33912 +#elif defined(PLATFORM_INTERFACE)
33913 + driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
33914 + driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
33915 + platform_driver_unregister(&dwc_otg_driver);
33916 +#endif
33917 +
33918 + printk(KERN_INFO "%s module removed\n", dwc_driver_name);
33919 +}
33920 +
33921 +module_exit(dwc_otg_driver_cleanup);
33922 +
33923 +MODULE_DESCRIPTION(DWC_DRIVER_DESC);
33924 +MODULE_AUTHOR("Synopsys Inc.");
33925 +MODULE_LICENSE("GPL");
33926 +
33927 +module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
33928 +MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
33929 +module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
33930 +MODULE_PARM_DESC(opt, "OPT Mode");
33931 +module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
33932 +MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
33933 +
33934 +module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
33935 + 0444);
33936 +MODULE_PARM_DESC(dma_desc_enable,
33937 + "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
33938 +
33939 +module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
33940 + 0444);
33941 +MODULE_PARM_DESC(dma_burst_size,
33942 + "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
33943 +module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
33944 +MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
33945 +module_param_named(host_support_fs_ls_low_power,
33946 + dwc_otg_module_params.host_support_fs_ls_low_power, int,
33947 + 0444);
33948 +MODULE_PARM_DESC(host_support_fs_ls_low_power,
33949 + "Support Low Power w/FS or LS 0=Support 1=Don't Support");
33950 +module_param_named(host_ls_low_power_phy_clk,
33951 + dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
33952 +MODULE_PARM_DESC(host_ls_low_power_phy_clk,
33953 + "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
33954 +module_param_named(enable_dynamic_fifo,
33955 + dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
33956 +MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
33957 +module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
33958 + 0444);
33959 +MODULE_PARM_DESC(data_fifo_size,
33960 + "Total number of words in the data FIFO memory 32-32768");
33961 +module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
33962 + int, 0444);
33963 +MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
33964 +module_param_named(dev_nperio_tx_fifo_size,
33965 + dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
33966 +MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
33967 + "Number of words in the non-periodic Tx FIFO 16-32768");
33968 +module_param_named(dev_perio_tx_fifo_size_1,
33969 + dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
33970 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
33971 + "Number of words in the periodic Tx FIFO 4-768");
33972 +module_param_named(dev_perio_tx_fifo_size_2,
33973 + dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
33974 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
33975 + "Number of words in the periodic Tx FIFO 4-768");
33976 +module_param_named(dev_perio_tx_fifo_size_3,
33977 + dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
33978 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
33979 + "Number of words in the periodic Tx FIFO 4-768");
33980 +module_param_named(dev_perio_tx_fifo_size_4,
33981 + dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
33982 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
33983 + "Number of words in the periodic Tx FIFO 4-768");
33984 +module_param_named(dev_perio_tx_fifo_size_5,
33985 + dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
33986 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
33987 + "Number of words in the periodic Tx FIFO 4-768");
33988 +module_param_named(dev_perio_tx_fifo_size_6,
33989 + dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
33990 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
33991 + "Number of words in the periodic Tx FIFO 4-768");
33992 +module_param_named(dev_perio_tx_fifo_size_7,
33993 + dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
33994 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
33995 + "Number of words in the periodic Tx FIFO 4-768");
33996 +module_param_named(dev_perio_tx_fifo_size_8,
33997 + dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
33998 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
33999 + "Number of words in the periodic Tx FIFO 4-768");
34000 +module_param_named(dev_perio_tx_fifo_size_9,
34001 + dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
34002 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
34003 + "Number of words in the periodic Tx FIFO 4-768");
34004 +module_param_named(dev_perio_tx_fifo_size_10,
34005 + dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
34006 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
34007 + "Number of words in the periodic Tx FIFO 4-768");
34008 +module_param_named(dev_perio_tx_fifo_size_11,
34009 + dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
34010 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
34011 + "Number of words in the periodic Tx FIFO 4-768");
34012 +module_param_named(dev_perio_tx_fifo_size_12,
34013 + dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
34014 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
34015 + "Number of words in the periodic Tx FIFO 4-768");
34016 +module_param_named(dev_perio_tx_fifo_size_13,
34017 + dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
34018 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
34019 + "Number of words in the periodic Tx FIFO 4-768");
34020 +module_param_named(dev_perio_tx_fifo_size_14,
34021 + dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
34022 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
34023 + "Number of words in the periodic Tx FIFO 4-768");
34024 +module_param_named(dev_perio_tx_fifo_size_15,
34025 + dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
34026 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
34027 + "Number of words in the periodic Tx FIFO 4-768");
34028 +module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
34029 + int, 0444);
34030 +MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
34031 +module_param_named(host_nperio_tx_fifo_size,
34032 + dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
34033 +MODULE_PARM_DESC(host_nperio_tx_fifo_size,
34034 + "Number of words in the non-periodic Tx FIFO 16-32768");
34035 +module_param_named(host_perio_tx_fifo_size,
34036 + dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
34037 +MODULE_PARM_DESC(host_perio_tx_fifo_size,
34038 + "Number of words in the host periodic Tx FIFO 16-32768");
34039 +module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
34040 + int, 0444);
34041 +/** @todo Set the max to 512K, modify checks */
34042 +MODULE_PARM_DESC(max_transfer_size,
34043 + "The maximum transfer size supported in bytes 2047-65535");
34044 +module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
34045 + int, 0444);
34046 +MODULE_PARM_DESC(max_packet_count,
34047 + "The maximum number of packets in a transfer 15-511");
34048 +module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
34049 + 0444);
34050 +MODULE_PARM_DESC(host_channels,
34051 + "The number of host channel registers to use 1-16");
34052 +module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
34053 + 0444);
34054 +MODULE_PARM_DESC(dev_endpoints,
34055 + "The number of endpoints in addition to EP0 available for device mode 1-15");
34056 +module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
34057 +MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
34058 +module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
34059 + 0444);
34060 +MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
34061 +module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
34062 +MODULE_PARM_DESC(phy_ulpi_ddr,
34063 + "ULPI at double or single data rate 0=Single 1=Double");
34064 +module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
34065 + int, 0444);
34066 +MODULE_PARM_DESC(phy_ulpi_ext_vbus,
34067 + "ULPI PHY using internal or external vbus 0=Internal");
34068 +module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
34069 +MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
34070 +module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
34071 +MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
34072 +module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
34073 +MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
34074 +module_param_named(debug, g_dbg_lvl, int, 0444);
34075 +MODULE_PARM_DESC(debug, "");
34076 +
34077 +module_param_named(en_multiple_tx_fifo,
34078 + dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
34079 +MODULE_PARM_DESC(en_multiple_tx_fifo,
34080 + "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
34081 +module_param_named(dev_tx_fifo_size_1,
34082 + dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
34083 +MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
34084 +module_param_named(dev_tx_fifo_size_2,
34085 + dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
34086 +MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
34087 +module_param_named(dev_tx_fifo_size_3,
34088 + dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
34089 +MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
34090 +module_param_named(dev_tx_fifo_size_4,
34091 + dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
34092 +MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
34093 +module_param_named(dev_tx_fifo_size_5,
34094 + dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
34095 +MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
34096 +module_param_named(dev_tx_fifo_size_6,
34097 + dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
34098 +MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
34099 +module_param_named(dev_tx_fifo_size_7,
34100 + dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
34101 +MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
34102 +module_param_named(dev_tx_fifo_size_8,
34103 + dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
34104 +MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
34105 +module_param_named(dev_tx_fifo_size_9,
34106 + dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
34107 +MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
34108 +module_param_named(dev_tx_fifo_size_10,
34109 + dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
34110 +MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
34111 +module_param_named(dev_tx_fifo_size_11,
34112 + dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
34113 +MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
34114 +module_param_named(dev_tx_fifo_size_12,
34115 + dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
34116 +MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
34117 +module_param_named(dev_tx_fifo_size_13,
34118 + dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
34119 +MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
34120 +module_param_named(dev_tx_fifo_size_14,
34121 + dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
34122 +MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
34123 +module_param_named(dev_tx_fifo_size_15,
34124 + dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
34125 +MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
34126 +
34127 +module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
34128 +MODULE_PARM_DESC(thr_ctl,
34129 + "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
34130 +module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
34131 + 0444);
34132 +MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
34133 +module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
34134 + 0444);
34135 +MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
34136 +
34137 +module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
34138 +module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
34139 +module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
34140 +MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
34141 +module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
34142 +MODULE_PARM_DESC(ic_usb_cap,
34143 + "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
34144 +module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
34145 + 0444);
34146 +MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
34147 +module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
34148 +MODULE_PARM_DESC(power_down, "Power Down Mode");
34149 +module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
34150 +MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
34151 +module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
34152 +MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
34153 +module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
34154 +MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
34155 +module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
34156 +MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
34157 +module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
34158 +MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
34159 +module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
34160 +MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
34161 +module_param(microframe_schedule, bool, 0444);
34162 +MODULE_PARM_DESC(microframe_schedule, "Enable the microframe scheduler");
34163 +
34164 +module_param(fiq_enable, bool, 0444);
34165 +MODULE_PARM_DESC(fiq_enable, "Enable the FIQ");
34166 +module_param(nak_holdoff, ushort, 0644);
34167 +MODULE_PARM_DESC(nak_holdoff, "Throttle duration for bulk split-transaction endpoints on a NAK. Default 8");
34168 +module_param(fiq_fsm_enable, bool, 0444);
34169 +MODULE_PARM_DESC(fiq_fsm_enable, "Enable the FIQ to perform split transactions as defined by fiq_fsm_mask");
34170 +module_param(fiq_fsm_mask, ushort, 0444);
34171 +MODULE_PARM_DESC(fiq_fsm_mask, "Bitmask of transactions to perform in the FIQ.\n"
34172 + "Bit 0 : Non-periodic split transactions\n"
34173 + "Bit 1 : Periodic split transactions\n"
34174 + "Bit 2 : High-speed multi-transfer isochronous\n"
34175 + "All other bits should be set 0.");
34176 +
34177 +
34178 +/** @page "Module Parameters"
34179 + *
34180 + * The following parameters may be specified when starting the module.
34181 + * These parameters define how the DWC_otg controller should be
34182 + * configured. Parameter values are passed to the CIL initialization
34183 + * function dwc_otg_cil_init
34184 + *
34185 + * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
34186 + *
34187 +
34188 + <table>
34189 + <tr><td>Parameter Name</td><td>Meaning</td></tr>
34190 +
34191 + <tr>
34192 + <td>otg_cap</td>
34193 + <td>Specifies the OTG capabilities. The driver will automatically detect the
34194 + value for this parameter if none is specified.
34195 + - 0: HNP and SRP capable (default, if available)
34196 + - 1: SRP Only capable
34197 + - 2: No HNP/SRP capable
34198 + </td></tr>
34199 +
34200 + <tr>
34201 + <td>dma_enable</td>
34202 + <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
34203 + The driver will automatically detect the value for this parameter if none is
34204 + specified.
34205 + - 0: Slave
34206 + - 1: DMA (default, if available)
34207 + </td></tr>
34208 +
34209 + <tr>
34210 + <td>dma_burst_size</td>
34211 + <td>The DMA Burst size (applicable only for External DMA Mode).
34212 + - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
34213 + </td></tr>
34214 +
34215 + <tr>
34216 + <td>speed</td>
34217 + <td>Specifies the maximum speed of operation in host and device mode. The
34218 + actual speed depends on the speed of the attached device and the value of
34219 + phy_type.
34220 + - 0: High Speed (default)
34221 + - 1: Full Speed
34222 + </td></tr>
34223 +
34224 + <tr>
34225 + <td>host_support_fs_ls_low_power</td>
34226 + <td>Specifies whether low power mode is supported when attached to a Full
34227 + Speed or Low Speed device in host mode.
34228 + - 0: Don't support low power mode (default)
34229 + - 1: Support low power mode
34230 + </td></tr>
34231 +
34232 + <tr>
34233 + <td>host_ls_low_power_phy_clk</td>
34234 + <td>Specifies the PHY clock rate in low power mode when connected to a Low
34235 + Speed device in host mode. This parameter is applicable only if
34236 + HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
34237 + - 0: 48 MHz (default)
34238 + - 1: 6 MHz
34239 + </td></tr>
34240 +
34241 + <tr>
34242 + <td>enable_dynamic_fifo</td>
34243 + <td> Specifies whether FIFOs may be resized by the driver software.
34244 + - 0: Use cC FIFO size parameters
34245 + - 1: Allow dynamic FIFO sizing (default)
34246 + </td></tr>
34247 +
34248 + <tr>
34249 + <td>data_fifo_size</td>
34250 + <td>Total number of 4-byte words in the data FIFO memory. This memory
34251 + includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
34252 + - Values: 32 to 32768 (default 8192)
34253 +
34254 + Note: The total FIFO memory depth in the FPGA configuration is 8192.
34255 + </td></tr>
34256 +
34257 + <tr>
34258 + <td>dev_rx_fifo_size</td>
34259 + <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
34260 + FIFO sizing is enabled.
34261 + - Values: 16 to 32768 (default 1064)
34262 + </td></tr>
34263 +
34264 + <tr>
34265 + <td>dev_nperio_tx_fifo_size</td>
34266 + <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
34267 + dynamic FIFO sizing is enabled.
34268 + - Values: 16 to 32768 (default 1024)
34269 + </td></tr>
34270 +
34271 + <tr>
34272 + <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
34273 + <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
34274 + when dynamic FIFO sizing is enabled.
34275 + - Values: 4 to 768 (default 256)
34276 + </td></tr>
34277 +
34278 + <tr>
34279 + <td>host_rx_fifo_size</td>
34280 + <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
34281 + sizing is enabled.
34282 + - Values: 16 to 32768 (default 1024)
34283 + </td></tr>
34284 +
34285 + <tr>
34286 + <td>host_nperio_tx_fifo_size</td>
34287 + <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
34288 + dynamic FIFO sizing is enabled in the core.
34289 + - Values: 16 to 32768 (default 1024)
34290 + </td></tr>
34291 +
34292 + <tr>
34293 + <td>host_perio_tx_fifo_size</td>
34294 + <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
34295 + sizing is enabled.
34296 + - Values: 16 to 32768 (default 1024)
34297 + </td></tr>
34298 +
34299 + <tr>
34300 + <td>max_transfer_size</td>
34301 + <td>The maximum transfer size supported in bytes.
34302 + - Values: 2047 to 65,535 (default 65,535)
34303 + </td></tr>
34304 +
34305 + <tr>
34306 + <td>max_packet_count</td>
34307 + <td>The maximum number of packets in a transfer.
34308 + - Values: 15 to 511 (default 511)
34309 + </td></tr>
34310 +
34311 + <tr>
34312 + <td>host_channels</td>
34313 + <td>The number of host channel registers to use.
34314 + - Values: 1 to 16 (default 12)
34315 +
34316 + Note: The FPGA configuration supports a maximum of 12 host channels.
34317 + </td></tr>
34318 +
34319 + <tr>
34320 + <td>dev_endpoints</td>
34321 + <td>The number of endpoints in addition to EP0 available for device mode
34322 + operations.
34323 + - Values: 1 to 15 (default 6 IN and OUT)
34324 +
34325 + Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
34326 + addition to EP0.
34327 + </td></tr>
34328 +
34329 + <tr>
34330 + <td>phy_type</td>
34331 + <td>Specifies the type of PHY interface to use. By default, the driver will
34332 + automatically detect the phy_type.
34333 + - 0: Full Speed
34334 + - 1: UTMI+ (default, if available)
34335 + - 2: ULPI
34336 + </td></tr>
34337 +
34338 + <tr>
34339 + <td>phy_utmi_width</td>
34340 + <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
34341 + phy_type of UTMI+. Also, this parameter is applicable only if the
34342 + OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
34343 + core has been configured to work at either data path width.
34344 + - Values: 8 or 16 bits (default 16)
34345 + </td></tr>
34346 +
34347 + <tr>
34348 + <td>phy_ulpi_ddr</td>
34349 + <td>Specifies whether the ULPI operates at double or single data rate. This
34350 + parameter is only applicable if phy_type is ULPI.
34351 + - 0: single data rate ULPI interface with 8 bit wide data bus (default)
34352 + - 1: double data rate ULPI interface with 4 bit wide data bus
34353 + </td></tr>
34354 +
34355 + <tr>
34356 + <td>i2c_enable</td>
34357 + <td>Specifies whether to use the I2C interface for full speed PHY. This
34358 + parameter is only applicable if PHY_TYPE is FS.
34359 + - 0: Disabled (default)
34360 + - 1: Enabled
34361 + </td></tr>
34362 +
34363 + <tr>
34364 + <td>ulpi_fs_ls</td>
34365 + <td>Specifies whether to use ULPI FS/LS mode only.
34366 + - 0: Disabled (default)
34367 + - 1: Enabled
34368 + </td></tr>
34369 +
34370 + <tr>
34371 + <td>ts_dline</td>
34372 + <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
34373 + - 0: Disabled (default)
34374 + - 1: Enabled
34375 + </td></tr>
34376 +
34377 + <tr>
34378 + <td>en_multiple_tx_fifo</td>
34379 + <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
34380 + The driver will automatically detect the value for this parameter if none is
34381 + specified.
34382 + - 0: Disabled
34383 + - 1: Enabled (default, if available)
34384 + </td></tr>
34385 +
34386 + <tr>
34387 + <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
34388 + <td>Number of 4-byte words in each of the Tx FIFOs in device mode
34389 + when dynamic FIFO sizing is enabled.
34390 + - Values: 4 to 768 (default 256)
34391 + </td></tr>
34392 +
34393 + <tr>
34394 + <td>tx_thr_length</td>
34395 + <td>Transmit Threshold length in 32 bit double words
34396 + - Values: 8 to 128 (default 64)
34397 + </td></tr>
34398 +
34399 + <tr>
34400 + <td>rx_thr_length</td>
34401 + <td>Receive Threshold length in 32 bit double words
34402 + - Values: 8 to 128 (default 64)
34403 + </td></tr>
34404 +
34405 +<tr>
34406 + <td>thr_ctl</td>
34407 + <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
34408 + this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
34409 + Rx transfers accordingly.
34410 + The driver will automatically detect the value for this parameter if none is
34411 + specified.
34412 + - Values: 0 to 7 (default 0)
34413 + Bit values indicate:
34414 + - 0: Thresholding disabled
34415 + - 1: Thresholding enabled
34416 + </td></tr>
34417 +
34418 +<tr>
34419 + <td>dma_desc_enable</td>
34420 + <td>Specifies whether to enable Descriptor DMA mode.
34421 + The driver will automatically detect the value for this parameter if none is
34422 + specified.
34423 + - 0: Descriptor DMA disabled
34424 + - 1: Descriptor DMA (default, if available)
34425 + </td></tr>
34426 +
34427 +<tr>
34428 + <td>mpi_enable</td>
34429 + <td>Specifies whether to enable MPI enhancement mode.
34430 + The driver will automatically detect the value for this parameter if none is
34431 + specified.
34432 + - 0: MPI disabled (default)
34433 + - 1: MPI enable
34434 + </td></tr>
34435 +
34436 +<tr>
34437 + <td>pti_enable</td>
34438 + <td>Specifies whether to enable PTI enhancement support.
34439 + The driver will automatically detect the value for this parameter if none is
34440 + specified.
34441 + - 0: PTI disabled (default)
34442 + - 1: PTI enable
34443 + </td></tr>
34444 +
34445 +<tr>
34446 + <td>lpm_enable</td>
34447 + <td>Specifies whether to enable LPM support.
34448 + The driver will automatically detect the value for this parameter if none is
34449 + specified.
34450 + - 0: LPM disabled
34451 + - 1: LPM enable (default, if available)
34452 + </td></tr>
34453 +
34454 +<tr>
34455 + <td>ic_usb_cap</td>
34456 + <td>Specifies whether to enable IC_USB capability.
34457 + The driver will automatically detect the value for this parameter if none is
34458 + specified.
34459 + - 0: IC_USB disabled (default, if available)
34460 + - 1: IC_USB enable
34461 + </td></tr>
34462 +
34463 +<tr>
34464 + <td>ahb_thr_ratio</td>
34465 + <td>Specifies AHB Threshold ratio.
34466 + - Values: 0 to 3 (default 0)
34467 + </td></tr>
34468 +
34469 +<tr>
34470 + <td>power_down</td>
34471 + <td>Specifies Power Down(Hibernation) Mode.
34472 + The driver will automatically detect the value for this parameter if none is
34473 + specified.
34474 + - 0: Power Down disabled (default)
34475 + - 2: Power Down enabled
34476 + </td></tr>
34477 +
34478 + <tr>
34479 + <td>reload_ctl</td>
34480 + <td>Specifies whether dynamic reloading of the HFIR register is allowed during
34481 + run time. The driver will automatically detect the value for this parameter if
34482 + none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
34483 + the core might misbehave.
34484 + - 0: Reload Control disabled (default)
34485 + - 1: Reload Control enabled
34486 + </td></tr>
34487 +
34488 + <tr>
34489 + <td>dev_out_nak</td>
34490 + <td>Specifies whether Device OUT NAK enhancement enabled or no.
34491 + The driver will automatically detect the value for this parameter if
34492 + none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1b1.
34493 + - 0: The core does not set NAK after Bulk OUT transfer complete (default)
34494 + - 1: The core sets NAK after Bulk OUT transfer complete
34495 + </td></tr>
34496 +
34497 + <tr>
34498 + <td>cont_on_bna</td>
34499 + <td>Specifies whether Enable Continue on BNA enabled or no.
34500 + After receiving BNA interrupt the core disables the endpoint,when the
34501 + endpoint is re-enabled by the application the
34502 + - 0: Core starts processing from the DOEPDMA descriptor (default)
34503 + - 1: Core starts processing from the descriptor which received the BNA.
34504 + This parameter is valid only when OTG_EN_DESC_DMA == 1b1.
34505 + </td></tr>
34506 +
34507 + <tr>
34508 + <td>ahb_single</td>
34509 + <td>This bit when programmed supports SINGLE transfers for remainder data
34510 + in a transfer for DMA mode of operation.
34511 + - 0: The remainder data will be sent using INCR burst size (default)
34512 + - 1: The remainder data will be sent using SINGLE burst size.
34513 + </td></tr>
34514 +
34515 +<tr>
34516 + <td>adp_enable</td>
34517 + <td>Specifies whether ADP feature is enabled.
34518 + The driver will automatically detect the value for this parameter if none is
34519 + specified.
34520 + - 0: ADP feature disabled (default)
34521 + - 1: ADP feature enabled
34522 + </td></tr>
34523 +
34524 + <tr>
34525 + <td>otg_ver</td>
34526 + <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
34527 + USB OTG device.
34528 + - 0: OTG 2.0 support disabled (default)
34529 + - 1: OTG 2.0 support enabled
34530 + </td></tr>
34531 +
34532 +*/
34533 --- /dev/null
34534 +++ b/drivers/usb/host/dwc_otg/dwc_otg_driver.h
34535 @@ -0,0 +1,86 @@
34536 +/* ==========================================================================
34537 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $
34538 + * $Revision: #19 $
34539 + * $Date: 2010/11/15 $
34540 + * $Change: 1627671 $
34541 + *
34542 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
34543 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
34544 + * otherwise expressly agreed to in writing between Synopsys and you.
34545 + *
34546 + * The Software IS NOT an item of Licensed Software or Licensed Product under
34547 + * any End User Software License Agreement or Agreement for Licensed Product
34548 + * with Synopsys or any supplement thereto. You are permitted to use and
34549 + * redistribute this Software in source and binary forms, with or without
34550 + * modification, provided that redistributions of source code must retain this
34551 + * notice. You may not view, use, disclose, copy or distribute this file or
34552 + * any information contained herein except pursuant to this license grant from
34553 + * Synopsys. If you do not agree with this notice, including the disclaimer
34554 + * below, then you are not authorized to use the Software.
34555 + *
34556 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
34557 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34558 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34559 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
34560 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
34561 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34562 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
34563 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34564 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34565 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
34566 + * DAMAGE.
34567 + * ========================================================================== */
34568 +
34569 +#ifndef __DWC_OTG_DRIVER_H__
34570 +#define __DWC_OTG_DRIVER_H__
34571 +
34572 +/** @file
34573 + * This file contains the interface to the Linux driver.
34574 + */
34575 +#include "dwc_otg_os_dep.h"
34576 +#include "dwc_otg_core_if.h"
34577 +
34578 +/* Type declarations */
34579 +struct dwc_otg_pcd;
34580 +struct dwc_otg_hcd;
34581 +
34582 +/**
34583 + * This structure is a wrapper that encapsulates the driver components used to
34584 + * manage a single DWC_otg controller.
34585 + */
34586 +typedef struct dwc_otg_device {
34587 + /** Structure containing OS-dependent stuff. KEEP THIS STRUCT AT THE
34588 + * VERY BEGINNING OF THE DEVICE STRUCT. OSes such as FreeBSD and NetBSD
34589 + * require this. */
34590 + struct os_dependent os_dep;
34591 +
34592 + /** Pointer to the core interface structure. */
34593 + dwc_otg_core_if_t *core_if;
34594 +
34595 + /** Pointer to the PCD structure. */
34596 + struct dwc_otg_pcd *pcd;
34597 +
34598 + /** Pointer to the HCD structure. */
34599 + struct dwc_otg_hcd *hcd;
34600 +
34601 + /** Flag to indicate whether the common IRQ handler is installed. */
34602 + uint8_t common_irq_installed;
34603 +
34604 +} dwc_otg_device_t;
34605 +
34606 +/*We must clear S3C24XX_EINTPEND external interrupt register
34607 + * because after clearing in this register trigerred IRQ from
34608 + * H/W core in kernel interrupt can be occured again before OTG
34609 + * handlers clear all IRQ sources of Core registers because of
34610 + * timing latencies and Low Level IRQ Type.
34611 + */
34612 +#ifdef CONFIG_MACH_IPMATE
34613 +#define S3C2410X_CLEAR_EINTPEND() \
34614 +do { \
34615 + __raw_writel(1UL << 11,S3C24XX_EINTPEND); \
34616 +} while (0)
34617 +#else
34618 +#define S3C2410X_CLEAR_EINTPEND() do { } while (0)
34619 +#endif
34620 +
34621 +#endif
34622 --- /dev/null
34623 +++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
34624 @@ -0,0 +1,1346 @@
34625 +/*
34626 + * dwc_otg_fiq_fsm.c - The finite state machine FIQ
34627 + *
34628 + * Copyright (c) 2013 Raspberry Pi Foundation
34629 + *
34630 + * Author: Jonathan Bell <jonathan@raspberrypi.org>
34631 + * All rights reserved.
34632 + *
34633 + * Redistribution and use in source and binary forms, with or without
34634 + * modification, are permitted provided that the following conditions are met:
34635 + * * Redistributions of source code must retain the above copyright
34636 + * notice, this list of conditions and the following disclaimer.
34637 + * * Redistributions in binary form must reproduce the above copyright
34638 + * notice, this list of conditions and the following disclaimer in the
34639 + * documentation and/or other materials provided with the distribution.
34640 + * * Neither the name of Raspberry Pi nor the
34641 + * names of its contributors may be used to endorse or promote products
34642 + * derived from this software without specific prior written permission.
34643 + *
34644 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
34645 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34646 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34647 + * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
34648 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
34649 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34650 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
34651 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34652 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34653 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34654 + *
34655 + * This FIQ implements functionality that performs split transactions on
34656 + * the dwc_otg hardware without any outside intervention. A split transaction
34657 + * is "queued" by nominating a specific host channel to perform the entirety
34658 + * of a split transaction. This FIQ will then perform the microframe-precise
34659 + * scheduling required in each phase of the transaction until completion.
34660 + *
34661 + * The FIQ functionality is glued into the Synopsys driver via the entry point
34662 + * in the FSM enqueue function, and at the exit point in handling a HC interrupt
34663 + * for a FSM-enabled channel.
34664 + *
34665 + * NB: Large parts of this implementation have architecture-specific code.
34666 + * For porting this functionality to other ARM machines, the minimum is required:
34667 + * - An interrupt controller allowing the top-level dwc USB interrupt to be routed
34668 + * to the FIQ
34669 + * - A method of forcing a software generated interrupt from FIQ mode that then
34670 + * triggers an IRQ entry (with the dwc USB handler called by this IRQ number)
34671 + * - Guaranteed interrupt routing such that both the FIQ and SGI occur on the same
34672 + * processor core - there is no locking between the FIQ and IRQ (aside from
34673 + * local_fiq_disable)
34674 + *
34675 + */
34676 +
34677 +#include "dwc_otg_fiq_fsm.h"
34678 +
34679 +
34680 +char buffer[1000*16];
34681 +int wptr;
34682 +void notrace _fiq_print(enum fiq_debug_level dbg_lvl, volatile struct fiq_state *state, char *fmt, ...)
34683 +{
34684 + enum fiq_debug_level dbg_lvl_req = FIQDBG_ERR;
34685 + va_list args;
34686 + char text[17];
34687 + hfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + 0x408) };
34688 +
34689 + if((dbg_lvl & dbg_lvl_req) || dbg_lvl == FIQDBG_ERR)
34690 + {
34691 + snprintf(text, 9, " %4d:%1u ", hfnum.b.frnum/8, hfnum.b.frnum & 7);
34692 + va_start(args, fmt);
34693 + vsnprintf(text+8, 9, fmt, args);
34694 + va_end(args);
34695 +
34696 + memcpy(buffer + wptr, text, 16);
34697 + wptr = (wptr + 16) % sizeof(buffer);
34698 + }
34699 +}
34700 +
34701 +/**
34702 + * fiq_fsm_spin_lock() - ARMv6+ bare bones spinlock
34703 + * Must be called with local interrupts and FIQ disabled.
34704 + */
34705 +#if defined(CONFIG_ARCH_BCM2709) && defined(CONFIG_SMP)
34706 +inline void fiq_fsm_spin_lock(fiq_lock_t *lock)
34707 +{
34708 + unsigned long tmp;
34709 + uint32_t newval;
34710 + fiq_lock_t lockval;
34711 + smp_mb__before_spinlock();
34712 + /* Nested locking, yay. If we are on the same CPU as the fiq, then the disable
34713 + * will be sufficient. If we are on a different CPU, then the lock protects us. */
34714 + prefetchw(&lock->slock);
34715 + asm volatile (
34716 + "1: ldrex %0, [%3]\n"
34717 + " add %1, %0, %4\n"
34718 + " strex %2, %1, [%3]\n"
34719 + " teq %2, #0\n"
34720 + " bne 1b"
34721 + : "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
34722 + : "r" (&lock->slock), "I" (1 << 16)
34723 + : "cc");
34724 +
34725 + while (lockval.tickets.next != lockval.tickets.owner) {
34726 + wfe();
34727 + lockval.tickets.owner = ACCESS_ONCE(lock->tickets.owner);
34728 + }
34729 + smp_mb();
34730 +}
34731 +#else
34732 +inline void fiq_fsm_spin_lock(fiq_lock_t *lock) { }
34733 +#endif
34734 +
34735 +/**
34736 + * fiq_fsm_spin_unlock() - ARMv6+ bare bones spinunlock
34737 + */
34738 +#if defined(CONFIG_ARCH_BCM2709) && defined(CONFIG_SMP)
34739 +inline void fiq_fsm_spin_unlock(fiq_lock_t *lock)
34740 +{
34741 + smp_mb();
34742 + lock->tickets.owner++;
34743 + dsb_sev();
34744 +}
34745 +#else
34746 +inline void fiq_fsm_spin_unlock(fiq_lock_t *lock) { }
34747 +#endif
34748 +
34749 +/**
34750 + * fiq_fsm_restart_channel() - Poke channel enable bit for a split transaction
34751 + * @channel: channel to re-enable
34752 + */
34753 +static void fiq_fsm_restart_channel(struct fiq_state *st, int n, int force)
34754 +{
34755 + hcchar_data_t hcchar = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR) };
34756 +
34757 + hcchar.b.chen = 0;
34758 + if (st->channel[n].hcchar_copy.b.eptype & 0x1) {
34759 + hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) };
34760 + /* Hardware bug workaround: update the ssplit index */
34761 + if (st->channel[n].hcsplt_copy.b.spltena)
34762 + st->channel[n].expected_uframe = (hfnum.b.frnum + 1) & 0x3FFF;
34763 +
34764 + hcchar.b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
34765 + }
34766 +
34767 + FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, hcchar.d32);
34768 + hcchar.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
34769 + hcchar.b.chen = 1;
34770 +
34771 + FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, hcchar.d32);
34772 + fiq_print(FIQDBG_INT, st, "HCGO %01d %01d", n, force);
34773 +}
34774 +
34775 +/**
34776 + * fiq_fsm_setup_csplit() - Prepare a host channel for a CSplit transaction stage
34777 + * @st: Pointer to the channel's state
34778 + * @n : channel number
34779 + *
34780 + * Change host channel registers to perform a complete-split transaction. Being mindful of the
34781 + * endpoint direction, set control regs up correctly.
34782 + */
34783 +static void notrace fiq_fsm_setup_csplit(struct fiq_state *st, int n)
34784 +{
34785 + hcsplt_data_t hcsplt = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT) };
34786 + hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) };
34787 +
34788 + hcsplt.b.compsplt = 1;
34789 + if (st->channel[n].hcchar_copy.b.epdir == 1) {
34790 + // If IN, the CSPLIT result contains the data or a hub handshake. hctsiz = maxpacket.
34791 + hctsiz.b.xfersize = st->channel[n].hctsiz_copy.b.xfersize;
34792 + } else {
34793 + // If OUT, the CSPLIT result contains handshake only.
34794 + hctsiz.b.xfersize = 0;
34795 + }
34796 + FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32);
34797 + FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);
34798 + mb();
34799 +}
34800 +
34801 +static inline int notrace fiq_get_xfer_len(struct fiq_state *st, int n)
34802 +{
34803 + /* The xfersize register is a bit wonky. For IN transfers, it decrements by the packet size. */
34804 + hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) };
34805 +
34806 + if (st->channel[n].hcchar_copy.b.epdir == 0) {
34807 + return st->channel[n].hctsiz_copy.b.xfersize;
34808 + } else {
34809 + return st->channel[n].hctsiz_copy.b.xfersize - hctsiz.b.xfersize;
34810 + }
34811 +
34812 +}
34813 +
34814 +
34815 +/**
34816 + * fiq_increment_dma_buf() - update DMA address for bounce buffers after a CSPLIT
34817 + *
34818 + * Of use only for IN periodic transfers.
34819 + */
34820 +static int notrace fiq_increment_dma_buf(struct fiq_state *st, int num_channels, int n)
34821 +{
34822 + hcdma_data_t hcdma;
34823 + int i = st->channel[n].dma_info.index;
34824 + int len;
34825 + struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base;
34826 +
34827 + len = fiq_get_xfer_len(st, n);
34828 + fiq_print(FIQDBG_INT, st, "LEN: %03d", len);
34829 + st->channel[n].dma_info.slot_len[i] = len;
34830 + i++;
34831 + if (i > 6)
34832 + BUG();
34833 +
34834 + hcdma.d32 = (dma_addr_t) &blob->channel[n].index[i].buf[0];
34835 + FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
34836 + st->channel[n].dma_info.index = i;
34837 + return 0;
34838 +}
34839 +
34840 +/**
34841 + * fiq_reload_hctsiz() - for IN transactions, reset HCTSIZ
34842 + */
34843 +static void notrace fiq_fsm_reload_hctsiz(struct fiq_state *st, int n)
34844 +{
34845 + hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) };
34846 + hctsiz.b.xfersize = st->channel[n].hctsiz_copy.b.xfersize;
34847 + hctsiz.b.pktcnt = 1;
34848 + FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);
34849 +}
34850 +
34851 +/**
34852 + * fiq_iso_out_advance() - update DMA address and split position bits
34853 + * for isochronous OUT transactions.
34854 + *
34855 + * Returns 1 if this is the last packet queued, 0 otherwise. Split-ALL and
34856 + * Split-BEGIN states are not handled - this is done when the transaction was queued.
34857 + *
34858 + * This function must only be called from the FIQ_ISO_OUT_ACTIVE state.
34859 + */
34860 +static int notrace fiq_iso_out_advance(struct fiq_state *st, int num_channels, int n)
34861 +{
34862 + hcsplt_data_t hcsplt;
34863 + hctsiz_data_t hctsiz;
34864 + hcdma_data_t hcdma;
34865 + struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base;
34866 + int last = 0;
34867 + int i = st->channel[n].dma_info.index;
34868 +
34869 + fiq_print(FIQDBG_INT, st, "ADV %01d %01d ", n, i);
34870 + i++;
34871 + if (i == 4)
34872 + last = 1;
34873 + if (st->channel[n].dma_info.slot_len[i+1] == 255)
34874 + last = 1;
34875 +
34876 + /* New DMA address - address of bounce buffer referred to in index */
34877 + hcdma.d32 = (uint32_t) &blob->channel[n].index[i].buf[0];
34878 + //hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n));
34879 + //hcdma.d32 += st->channel[n].dma_info.slot_len[i];
34880 + fiq_print(FIQDBG_INT, st, "LAST: %01d ", last);
34881 + fiq_print(FIQDBG_INT, st, "LEN: %03d", st->channel[n].dma_info.slot_len[i]);
34882 + hcsplt.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT);
34883 + hctsiz.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ);
34884 + hcsplt.b.xactpos = (last) ? ISOC_XACTPOS_END : ISOC_XACTPOS_MID;
34885 + /* Set up new packet length */
34886 + hctsiz.b.pktcnt = 1;
34887 + hctsiz.b.xfersize = st->channel[n].dma_info.slot_len[i];
34888 + fiq_print(FIQDBG_INT, st, "%08x", hctsiz.d32);
34889 +
34890 + st->channel[n].dma_info.index++;
34891 + FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32);
34892 + FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);
34893 + FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
34894 + return last;
34895 +}
34896 +
34897 +/**
34898 + * fiq_fsm_tt_next_isoc() - queue next pending isochronous out start-split on a TT
34899 + *
34900 + * Despite the limitations of the DWC core, we can force a microframe pipeline of
34901 + * isochronous OUT start-split transactions while waiting for a corresponding other-type
34902 + * of endpoint to finish its CSPLITs. TTs have big periodic buffers therefore it
34903 + * is very unlikely that filling the start-split FIFO will cause data loss.
34904 + * This allows much better interleaving of transactions in an order-independent way-
34905 + * there is no requirement to prioritise isochronous, just a state-space search has
34906 + * to be performed on each periodic start-split complete interrupt.
34907 + */
34908 +static int notrace fiq_fsm_tt_next_isoc(struct fiq_state *st, int num_channels, int n)
34909 +{
34910 + int hub_addr = st->channel[n].hub_addr;
34911 + int port_addr = st->channel[n].port_addr;
34912 + int i, poked = 0;
34913 + for (i = 0; i < num_channels; i++) {
34914 + if (i == n || st->channel[i].fsm == FIQ_PASSTHROUGH)
34915 + continue;
34916 + if (st->channel[i].hub_addr == hub_addr &&
34917 + st->channel[i].port_addr == port_addr) {
34918 + switch (st->channel[i].fsm) {
34919 + case FIQ_PER_ISO_OUT_PENDING:
34920 + if (st->channel[i].nrpackets == 1) {
34921 + st->channel[i].fsm = FIQ_PER_ISO_OUT_LAST;
34922 + } else {
34923 + st->channel[i].fsm = FIQ_PER_ISO_OUT_ACTIVE;
34924 + }
34925 + fiq_fsm_restart_channel(st, i, 0);
34926 + poked = 1;
34927 + break;
34928 +
34929 + default:
34930 + break;
34931 + }
34932 + }
34933 + if (poked)
34934 + break;
34935 + }
34936 + return poked;
34937 +}
34938 +
34939 +/**
34940 + * fiq_fsm_tt_in_use() - search for host channels using this TT
34941 + * @n: Channel to use as reference
34942 + *
34943 + */
34944 +int notrace noinline fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n)
34945 +{
34946 + int hub_addr = st->channel[n].hub_addr;
34947 + int port_addr = st->channel[n].port_addr;
34948 + int i, in_use = 0;
34949 + for (i = 0; i < num_channels; i++) {
34950 + if (i == n || st->channel[i].fsm == FIQ_PASSTHROUGH)
34951 + continue;
34952 + switch (st->channel[i].fsm) {
34953 + /* TT is reserved for channels that are in the middle of a periodic
34954 + * split transaction.
34955 + */
34956 + case FIQ_PER_SSPLIT_STARTED:
34957 + case FIQ_PER_CSPLIT_WAIT:
34958 + case FIQ_PER_CSPLIT_NYET1:
34959 + //case FIQ_PER_CSPLIT_POLL:
34960 + case FIQ_PER_ISO_OUT_ACTIVE:
34961 + case FIQ_PER_ISO_OUT_LAST:
34962 + if (st->channel[i].hub_addr == hub_addr &&
34963 + st->channel[i].port_addr == port_addr) {
34964 + in_use = 1;
34965 + }
34966 + break;
34967 + default:
34968 + break;
34969 + }
34970 + if (in_use)
34971 + break;
34972 + }
34973 + return in_use;
34974 +}
34975 +
34976 +/**
34977 + * fiq_fsm_more_csplits() - determine whether additional CSPLITs need
34978 + * to be issued for this IN transaction.
34979 + *
34980 + * We cannot tell the inbound PID of a data packet due to hardware limitations.
34981 + * we need to make an educated guess as to whether we need to queue another CSPLIT
34982 + * or not. A no-brainer is when we have received enough data to fill the endpoint
34983 + * size, but for endpoints that give variable-length data then we have to resort
34984 + * to heuristics.
34985 + *
34986 + * We also return whether this is the last CSPLIT to be queued, again based on
34987 + * heuristics. This is to allow a 1-uframe overlap of periodic split transactions.
34988 + * Note: requires at least 1 CSPLIT to have been performed prior to being called.
34989 + */
34990 +
34991 +/*
34992 + * We need some way of guaranteeing if a returned periodic packet of size X
34993 + * has a DATA0 PID.
34994 + * The heuristic value of 144 bytes assumes that the received data has maximal
34995 + * bit-stuffing and the clock frequency of the transmitting device is at the lowest
34996 + * permissible limit. If the transfer length results in a final packet size
34997 + * 144 < p <= 188, then an erroneous CSPLIT will be issued.
34998 + * Also used to ensure that an endpoint will nominally only return a single
34999 + * complete-split worth of data.
35000 + */
35001 +#define DATA0_PID_HEURISTIC 144
35002 +
35003 +static int notrace noinline fiq_fsm_more_csplits(struct fiq_state *state, int n, int *probably_last)
35004 +{
35005 +
35006 + int i;
35007 + int total_len = 0;
35008 + int more_needed = 1;
35009 + struct fiq_channel_state *st = &state->channel[n];
35010 +
35011 + for (i = 0; i < st->dma_info.index; i++) {
35012 + total_len += st->dma_info.slot_len[i];
35013 + }
35014 +
35015 + *probably_last = 0;
35016 +
35017 + if (st->hcchar_copy.b.eptype == 0x3) {
35018 + /*
35019 + * An interrupt endpoint will take max 2 CSPLITs. if we are receiving data
35020 + * then this is definitely the last CSPLIT.
35021 + */
35022 + *probably_last = 1;
35023 + } else {
35024 + /* Isoc IN. This is a bit risky if we are the first transaction:
35025 + * we may have been held off slightly. */
35026 + if (i > 1 && st->dma_info.slot_len[st->dma_info.index-1] <= DATA0_PID_HEURISTIC) {
35027 + more_needed = 0;
35028 + }
35029 + /* If in the next uframe we will receive enough data to fill the endpoint,
35030 + * then only issue 1 more csplit.
35031 + */
35032 + if (st->hctsiz_copy.b.xfersize - total_len <= DATA0_PID_HEURISTIC)
35033 + *probably_last = 1;
35034 + }
35035 +
35036 + if (total_len >= st->hctsiz_copy.b.xfersize ||
35037 + i == 6 || total_len == 0)
35038 + /* Note: due to bit stuffing it is possible to have > 6 CSPLITs for
35039 + * a single endpoint. Accepting more would completely break our scheduling mechanism though
35040 + * - in these extreme cases we will pass through a truncated packet.
35041 + */
35042 + more_needed = 0;
35043 +
35044 + return more_needed;
35045 +}
35046 +
35047 +/**
35048 + * fiq_fsm_too_late() - Test transaction for lateness
35049 + *
35050 + * If a SSPLIT for a large IN transaction is issued too late in a frame,
35051 + * the hub will disable the port to the device and respond with ERR handshakes.
35052 + * The hub status endpoint will not reflect this change.
35053 + * Returns 1 if we will issue a SSPLIT that will result in a device babble.
35054 + */
35055 +int notrace fiq_fsm_too_late(struct fiq_state *st, int n)
35056 +{
35057 + int uframe;
35058 + hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) };
35059 + uframe = hfnum.b.frnum & 0x7;
35060 + if ((uframe < 6) && (st->channel[n].nrpackets + 1 + uframe > 7)) {
35061 + return 1;
35062 + } else {
35063 + return 0;
35064 + }
35065 +}
35066 +
35067 +
35068 +/**
35069 + * fiq_fsm_start_next_periodic() - A half-arsed attempt at a microframe pipeline
35070 + *
35071 + * Search pending transactions in the start-split pending state and queue them.
35072 + * Don't queue packets in uframe .5 (comes out in .6) (USB2.0 11.18.4).
35073 + * Note: we specifically don't do isochronous OUT transactions first because better
35074 + * use of the TT's start-split fifo can be achieved by pipelining an IN before an OUT.
35075 + */
35076 +static void notrace noinline fiq_fsm_start_next_periodic(struct fiq_state *st, int num_channels)
35077 +{
35078 + int n;
35079 + hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) };
35080 + if ((hfnum.b.frnum & 0x7) == 5)
35081 + return;
35082 + for (n = 0; n < num_channels; n++) {
35083 + if (st->channel[n].fsm == FIQ_PER_SSPLIT_QUEUED) {
35084 + /* Check to see if any other transactions are using this TT */
35085 + if(!fiq_fsm_tt_in_use(st, num_channels, n)) {
35086 + if (!fiq_fsm_too_late(st, n)) {
35087 + st->channel[n].fsm = FIQ_PER_SSPLIT_STARTED;
35088 + fiq_print(FIQDBG_INT, st, "NEXTPER ");
35089 + fiq_fsm_restart_channel(st, n, 0);
35090 + } else {
35091 + st->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT;
35092 + }
35093 + break;
35094 + }
35095 + }
35096 + }
35097 + for (n = 0; n < num_channels; n++) {
35098 + if (st->channel[n].fsm == FIQ_PER_ISO_OUT_PENDING) {
35099 + if (!fiq_fsm_tt_in_use(st, num_channels, n)) {
35100 + fiq_print(FIQDBG_INT, st, "NEXTISO ");
35101 + st->channel[n].fsm = FIQ_PER_ISO_OUT_ACTIVE;
35102 + fiq_fsm_restart_channel(st, n, 0);
35103 + break;
35104 + }
35105 + }
35106 + }
35107 +}
35108 +
35109 +/**
35110 + * fiq_fsm_update_hs_isoc() - update isochronous frame and transfer data
35111 + * @state: Pointer to fiq_state
35112 + * @n: Channel transaction is active on
35113 + * @hcint: Copy of host channel interrupt register
35114 + *
35115 + * Returns 0 if there are no more transactions for this HC to do, 1
35116 + * otherwise.
35117 + */
35118 +static int notrace noinline fiq_fsm_update_hs_isoc(struct fiq_state *state, int n, hcint_data_t hcint)
35119 +{
35120 + struct fiq_channel_state *st = &state->channel[n];
35121 + int xfer_len = 0, nrpackets = 0;
35122 + hcdma_data_t hcdma;
35123 + fiq_print(FIQDBG_INT, state, "HSISO %02d", n);
35124 +
35125 + xfer_len = fiq_get_xfer_len(state, n);
35126 + st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].actual_length = xfer_len;
35127 +
35128 + st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].status = hcint.d32;
35129 +
35130 + st->hs_isoc_info.index++;
35131 + if (st->hs_isoc_info.index == st->hs_isoc_info.nrframes) {
35132 + return 0;
35133 + }
35134 +
35135 + /* grab the next DMA address offset from the array */
35136 + hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].offset;
35137 + FIQ_WRITE(state->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
35138 +
35139 + /* We need to set multi_count. This is a bit tricky - has to be set per-transaction as
35140 + * the core needs to be told to send the correct number. Caution: for IN transfers,
35141 + * this is always set to the maximum size of the endpoint. */
35142 + xfer_len = st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].length;
35143 + /* Integer divide in a FIQ: fun. FIXME: make this not suck */
35144 + nrpackets = (xfer_len + st->hcchar_copy.b.mps - 1) / st->hcchar_copy.b.mps;
35145 + if (nrpackets == 0)
35146 + nrpackets = 1;
35147 + st->hcchar_copy.b.multicnt = nrpackets;
35148 + st->hctsiz_copy.b.pktcnt = nrpackets;
35149 +
35150 + /* Initial PID also needs to be set */
35151 + if (st->hcchar_copy.b.epdir == 0) {
35152 + st->hctsiz_copy.b.xfersize = xfer_len;
35153 + switch (st->hcchar_copy.b.multicnt) {
35154 + case 1:
35155 + st->hctsiz_copy.b.pid = DWC_PID_DATA0;
35156 + break;
35157 + case 2:
35158 + case 3:
35159 + st->hctsiz_copy.b.pid = DWC_PID_MDATA;
35160 + break;
35161 + }
35162 +
35163 + } else {
35164 + switch (st->hcchar_copy.b.multicnt) {
35165 + st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps;
35166 + case 1:
35167 + st->hctsiz_copy.b.pid = DWC_PID_DATA0;
35168 + break;
35169 + case 2:
35170 + st->hctsiz_copy.b.pid = DWC_PID_DATA1;
35171 + break;
35172 + case 3:
35173 + st->hctsiz_copy.b.pid = DWC_PID_DATA2;
35174 + break;
35175 + }
35176 + }
35177 + FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, st->hctsiz_copy.d32);
35178 + FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, st->hcchar_copy.d32);
35179 + /* Channel is enabled on hcint handler exit */
35180 + fiq_print(FIQDBG_INT, state, "HSISOOUT");
35181 + return 1;
35182 +}
35183 +
35184 +
35185 +/**
35186 + * fiq_fsm_do_sof() - FSM start-of-frame interrupt handler
35187 + * @state: Pointer to the state struct passed from banked FIQ mode registers.
35188 + * @num_channels: set according to the DWC hardware configuration
35189 + *
35190 + * The SOF handler in FSM mode has two functions
35191 + * 1. Hold off SOF from causing schedule advancement in IRQ context if there's
35192 + * nothing to do
35193 + * 2. Advance certain FSM states that require either a microframe delay, or a microframe
35194 + * of holdoff.
35195 + *
35196 + * The second part is architecture-specific to mach-bcm2835 -
35197 + * a sane interrupt controller would have a mask register for ARM interrupt sources
35198 + * to be promoted to the nFIQ line, but it doesn't. Instead a single interrupt
35199 + * number (USB) can be enabled. This means that certain parts of the USB specification
35200 + * that require "wait a little while, then issue another packet" cannot be fulfilled with
35201 + * the timing granularity required to achieve optimal throughout. The workaround is to use
35202 + * the SOF "timer" (125uS) to perform this task.
35203 + */
35204 +static int notrace noinline fiq_fsm_do_sof(struct fiq_state *state, int num_channels)
35205 +{
35206 + hfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + HFNUM) };
35207 + int n;
35208 + int kick_irq = 0;
35209 +
35210 + if ((hfnum.b.frnum & 0x7) == 1) {
35211 + /* We cannot issue csplits for transactions in the last frame past (n+1).1
35212 + * Check to see if there are any transactions that are stale.
35213 + * Boot them out.
35214 + */
35215 + for (n = 0; n < num_channels; n++) {
35216 + switch (state->channel[n].fsm) {
35217 + case FIQ_PER_CSPLIT_WAIT:
35218 + case FIQ_PER_CSPLIT_NYET1:
35219 + case FIQ_PER_CSPLIT_POLL:
35220 + case FIQ_PER_CSPLIT_LAST:
35221 + /* Check if we are no longer in the same full-speed frame. */
35222 + if (((state->channel[n].expected_uframe & 0x3FFF) & ~0x7) <
35223 + (hfnum.b.frnum & ~0x7))
35224 + state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT;
35225 + break;
35226 + default:
35227 + break;
35228 + }
35229 + }
35230 + }
35231 +
35232 + for (n = 0; n < num_channels; n++) {
35233 + switch (state->channel[n].fsm) {
35234 +
35235 + case FIQ_NP_SSPLIT_RETRY:
35236 + case FIQ_NP_IN_CSPLIT_RETRY:
35237 + case FIQ_NP_OUT_CSPLIT_RETRY:
35238 + fiq_fsm_restart_channel(state, n, 0);
35239 + break;
35240 +
35241 + case FIQ_HS_ISOC_SLEEPING:
35242 + state->channel[n].fsm = FIQ_HS_ISOC_TURBO;
35243 + fiq_fsm_restart_channel(state, n, 0);
35244 + break;
35245 +
35246 + case FIQ_PER_SSPLIT_QUEUED:
35247 + if ((hfnum.b.frnum & 0x7) == 5)
35248 + break;
35249 + if(!fiq_fsm_tt_in_use(state, num_channels, n)) {
35250 + if (!fiq_fsm_too_late(state, n)) {
35251 + fiq_print(FIQDBG_INT, st, "SOF GO %01d", n);
35252 + fiq_fsm_restart_channel(state, n, 0);
35253 + state->channel[n].fsm = FIQ_PER_SSPLIT_STARTED;
35254 + } else {
35255 + /* Transaction cannot be started without risking a device babble error */
35256 + state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT;
35257 + state->haintmsk_saved.b2.chint &= ~(1 << n);
35258 + FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, 0);
35259 + kick_irq |= 1;
35260 + }
35261 + }
35262 + break;
35263 +
35264 + case FIQ_PER_ISO_OUT_PENDING:
35265 + /* Ordinarily, this should be poked after the SSPLIT
35266 + * complete interrupt for a competing transfer on the same
35267 + * TT. Doesn't happen for aborted transactions though.
35268 + */
35269 + if ((hfnum.b.frnum & 0x7) >= 5)
35270 + break;
35271 + if (!fiq_fsm_tt_in_use(state, num_channels, n)) {
35272 + /* Hardware bug. SOF can sometimes occur after the channel halt interrupt
35273 + * that caused this.
35274 + */
35275 + fiq_fsm_restart_channel(state, n, 0);
35276 + fiq_print(FIQDBG_INT, state, "SOF ISOC");
35277 + if (state->channel[n].nrpackets == 1) {
35278 + state->channel[n].fsm = FIQ_PER_ISO_OUT_LAST;
35279 + } else {
35280 + state->channel[n].fsm = FIQ_PER_ISO_OUT_ACTIVE;
35281 + }
35282 + }
35283 + break;
35284 +
35285 + case FIQ_PER_CSPLIT_WAIT:
35286 + /* we are guaranteed to be in this state if and only if the SSPLIT interrupt
35287 + * occurred when the bus transaction occurred. The SOF interrupt reversal bug
35288 + * will utterly bugger this up though.
35289 + */
35290 + if (hfnum.b.frnum != state->channel[n].expected_uframe) {
35291 + fiq_print(FIQDBG_INT, state, "SOFCS %d ", n);
35292 + state->channel[n].fsm = FIQ_PER_CSPLIT_POLL;
35293 + fiq_fsm_restart_channel(state, n, 0);
35294 + fiq_fsm_start_next_periodic(state, num_channels);
35295 +
35296 + }
35297 + break;
35298 +
35299 + case FIQ_PER_SPLIT_TIMEOUT:
35300 + case FIQ_DEQUEUE_ISSUED:
35301 + /* Ugly: we have to force a HCD interrupt.
35302 + * Poke the mask for the channel in question.
35303 + * We will take a fake SOF because of this, but
35304 + * that's OK.
35305 + */
35306 + state->haintmsk_saved.b2.chint &= ~(1 << n);
35307 + FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, 0);
35308 + kick_irq |= 1;
35309 + break;
35310 +
35311 + default:
35312 + break;
35313 + }
35314 + }
35315 +
35316 + if (state->kick_np_queues ||
35317 + dwc_frame_num_le(state->next_sched_frame, hfnum.b.frnum))
35318 + kick_irq |= 1;
35319 +
35320 + return !kick_irq;
35321 +}
35322 +
35323 +
35324 +/**
35325 + * fiq_fsm_do_hcintr() - FSM host channel interrupt handler
35326 + * @state: Pointer to the FIQ state struct
35327 + * @num_channels: Number of channels as per hardware config
35328 + * @n: channel for which HAINT(i) was raised
35329 + *
35330 + * An important property is that only the CHHLT interrupt is unmasked. Unfortunately, AHBerr is as well.
35331 + */
35332 +static int notrace noinline fiq_fsm_do_hcintr(struct fiq_state *state, int num_channels, int n)
35333 +{
35334 + hcint_data_t hcint;
35335 + hcintmsk_data_t hcintmsk;
35336 + hcint_data_t hcint_probe;
35337 + hcchar_data_t hcchar;
35338 + int handled = 0;
35339 + int restart = 0;
35340 + int last_csplit = 0;
35341 + int start_next_periodic = 0;
35342 + struct fiq_channel_state *st = &state->channel[n];
35343 + hfnum_data_t hfnum;
35344 +
35345 + hcint.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT);
35346 + hcintmsk.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK);
35347 + hcint_probe.d32 = hcint.d32 & hcintmsk.d32;
35348 +
35349 + if (st->fsm != FIQ_PASSTHROUGH) {
35350 + fiq_print(FIQDBG_INT, state, "HC%01d ST%02d", n, st->fsm);
35351 + fiq_print(FIQDBG_INT, state, "%08x", hcint.d32);
35352 + }
35353 +
35354 + switch (st->fsm) {
35355 +
35356 + case FIQ_PASSTHROUGH:
35357 + case FIQ_DEQUEUE_ISSUED:
35358 + /* doesn't belong to us, kick it upstairs */
35359 + break;
35360 +
35361 + case FIQ_PASSTHROUGH_ERRORSTATE:
35362 + /* We are here to emulate the error recovery mechanism of the dwc HCD.
35363 + * Several interrupts are unmasked if a previous transaction failed - it's
35364 + * death for the FIQ to attempt to handle them as the channel isn't halted.
35365 + * Emulate what the HCD does in this situation: mask and continue.
35366 + * The FSM has no other state setup so this has to be handled out-of-band.
35367 + */
35368 + fiq_print(FIQDBG_ERR, state, "ERRST %02d", n);
35369 + if (hcint_probe.b.nak || hcint_probe.b.ack || hcint_probe.b.datatglerr) {
35370 + fiq_print(FIQDBG_ERR, state, "RESET %02d", n);
35371 + /* In some random cases we can get a NAK interrupt coincident with a Xacterr
35372 + * interrupt, after the device has disappeared.
35373 + */
35374 + if (!hcint.b.xacterr)
35375 + st->nr_errors = 0;
35376 + hcintmsk.b.nak = 0;
35377 + hcintmsk.b.ack = 0;
35378 + hcintmsk.b.datatglerr = 0;
35379 + FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, hcintmsk.d32);
35380 + return 1;
35381 + }
35382 + if (hcint_probe.b.chhltd) {
35383 + fiq_print(FIQDBG_ERR, state, "CHHLT %02d", n);
35384 + fiq_print(FIQDBG_ERR, state, "%08x", hcint.d32);
35385 + return 0;
35386 + }
35387 + break;
35388 +
35389 + /* Non-periodic state groups */
35390 + case FIQ_NP_SSPLIT_STARTED:
35391 + case FIQ_NP_SSPLIT_RETRY:
35392 + /* Got a HCINT for a NP SSPLIT. Expected ACK / NAK / fail */
35393 + if (hcint.b.ack) {
35394 + /* SSPLIT complete. For OUT, the data has been sent. For IN, the LS transaction
35395 + * will start shortly. SOF needs to kick the transaction to prevent a NYET flood.
35396 + */
35397 + if(st->hcchar_copy.b.epdir == 1)
35398 + st->fsm = FIQ_NP_IN_CSPLIT_RETRY;
35399 + else
35400 + st->fsm = FIQ_NP_OUT_CSPLIT_RETRY;
35401 + st->nr_errors = 0;
35402 + handled = 1;
35403 + fiq_fsm_setup_csplit(state, n);
35404 + } else if (hcint.b.nak) {
35405 + // No buffer space in TT. Retry on a uframe boundary.
35406 + st->fsm = FIQ_NP_SSPLIT_RETRY;
35407 + handled = 1;
35408 + } else if (hcint.b.xacterr) {
35409 + // The only other one we care about is xacterr. This implies HS bus error - retry.
35410 + st->nr_errors++;
35411 + st->fsm = FIQ_NP_SSPLIT_RETRY;
35412 + if (st->nr_errors >= 3) {
35413 + st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
35414 + } else {
35415 + handled = 1;
35416 + restart = 1;
35417 + }
35418 + } else {
35419 + st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
35420 + handled = 0;
35421 + restart = 0;
35422 + }
35423 + break;
35424 +
35425 + case FIQ_NP_IN_CSPLIT_RETRY:
35426 + /* Received a CSPLIT done interrupt.
35427 + * Expected Data/NAK/STALL/NYET for IN.
35428 + */
35429 + if (hcint.b.xfercomp) {
35430 + /* For IN, data is present. */
35431 + st->fsm = FIQ_NP_SPLIT_DONE;
35432 + } else if (hcint.b.nak) {
35433 + /* no endpoint data. Punt it upstairs */
35434 + st->fsm = FIQ_NP_SPLIT_DONE;
35435 + } else if (hcint.b.nyet) {
35436 + /* CSPLIT NYET - retry on a uframe boundary. */
35437 + handled = 1;
35438 + st->nr_errors = 0;
35439 + } else if (hcint.b.datatglerr) {
35440 + /* data toggle errors do not set the xfercomp bit. */
35441 + st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
35442 + } else if (hcint.b.xacterr) {
35443 + /* HS error. Retry immediate */
35444 + st->fsm = FIQ_NP_IN_CSPLIT_RETRY;
35445 + st->nr_errors++;
35446 + if (st->nr_errors >= 3) {
35447 + st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
35448 + } else {
35449 + handled = 1;
35450 + restart = 1;
35451 + }
35452 + } else if (hcint.b.stall || hcint.b.bblerr) {
35453 + /* A STALL implies either a LS bus error or a genuine STALL. */
35454 + st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
35455 + } else {
35456 + /* Hardware bug. It's possible in some cases to
35457 + * get a channel halt with nothing else set when
35458 + * the response was a NYET. Treat as local 3-strikes retry.
35459 + */
35460 + hcint_data_t hcint_test = hcint;
35461 + hcint_test.b.chhltd = 0;
35462 + if (!hcint_test.d32) {
35463 + st->nr_errors++;
35464 + if (st->nr_errors >= 3) {
35465 + st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
35466 + } else {
35467 + handled = 1;
35468 + }
35469 + } else {
35470 + /* Bail out if something unexpected happened */
35471 + st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
35472 + }
35473 + }
35474 + break;
35475 +
35476 + case FIQ_NP_OUT_CSPLIT_RETRY:
35477 + /* Received a CSPLIT done interrupt.
35478 + * Expected ACK/NAK/STALL/NYET/XFERCOMP for OUT.*/
35479 + if (hcint.b.xfercomp) {
35480 + st->fsm = FIQ_NP_SPLIT_DONE;
35481 + } else if (hcint.b.nak) {
35482 + // The HCD will implement the holdoff on frame boundaries.
35483 + st->fsm = FIQ_NP_SPLIT_DONE;
35484 + } else if (hcint.b.nyet) {
35485 + // Hub still processing.
35486 + st->fsm = FIQ_NP_OUT_CSPLIT_RETRY;
35487 + handled = 1;
35488 + st->nr_errors = 0;
35489 + //restart = 1;
35490 + } else if (hcint.b.xacterr) {
35491 + /* HS error. retry immediate */
35492 + st->fsm = FIQ_NP_OUT_CSPLIT_RETRY;
35493 + st->nr_errors++;
35494 + if (st->nr_errors >= 3) {
35495 + st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
35496 + } else {
35497 + handled = 1;
35498 + restart = 1;
35499 + }
35500 + } else if (hcint.b.stall) {
35501 + /* LS bus error or genuine stall */
35502 + st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
35503 + } else {
35504 + /*
35505 + * Hardware bug. It's possible in some cases to get a
35506 + * channel halt with nothing else set when the response was a NYET.
35507 + * Treat as local 3-strikes retry.
35508 + */
35509 + hcint_data_t hcint_test = hcint;
35510 + hcint_test.b.chhltd = 0;
35511 + if (!hcint_test.d32) {
35512 + st->nr_errors++;
35513 + if (st->nr_errors >= 3) {
35514 + st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
35515 + } else {
35516 + handled = 1;
35517 + }
35518 + } else {
35519 + // Something unexpected happened. AHBerror or babble perhaps. Let the IRQ deal with it.
35520 + st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
35521 + }
35522 + }
35523 + break;
35524 +
35525 + /* Periodic split states (except isoc out) */
35526 + case FIQ_PER_SSPLIT_STARTED:
35527 + /* Expect an ACK or failure for SSPLIT */
35528 + if (hcint.b.ack) {
35529 + /*
35530 + * SSPLIT transfer complete interrupt - the generation of this interrupt is fraught with bugs.
35531 + * For a packet queued in microframe n-3 to appear in n-2, if the channel is enabled near the EOF1
35532 + * point for microframe n-3, the packet will not appear on the bus until microframe n.
35533 + * Additionally, the generation of the actual interrupt is dodgy. For a packet appearing on the bus
35534 + * in microframe n, sometimes the interrupt is generated immediately. Sometimes, it appears in n+1
35535 + * coincident with SOF for n+1.
35536 + * SOF is also buggy. It can sometimes be raised AFTER the first bus transaction has taken place.
35537 + * These appear to be caused by timing/clock crossing bugs within the core itself.
35538 + * State machine workaround.
35539 + */
35540 + hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
35541 + hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
35542 + fiq_fsm_setup_csplit(state, n);
35543 + /* Poke the oddfrm bit. If we are equivalent, we received the interrupt at the correct
35544 + * time. If not, then we're in the next SOF.
35545 + */
35546 + if ((hfnum.b.frnum & 0x1) == hcchar.b.oddfrm) {
35547 + fiq_print(FIQDBG_INT, state, "CSWAIT %01d", n);
35548 + st->expected_uframe = hfnum.b.frnum;
35549 + st->fsm = FIQ_PER_CSPLIT_WAIT;
35550 + } else {
35551 + fiq_print(FIQDBG_INT, state, "CSPOL %01d", n);
35552 + /* For isochronous IN endpoints,
35553 + * we need to hold off if we are expecting a lot of data */
35554 + if (st->hcchar_copy.b.mps < DATA0_PID_HEURISTIC) {
35555 + start_next_periodic = 1;
35556 + }
35557 + /* Danger will robinson: we are in a broken state. If our first interrupt after
35558 + * this is a NYET, it will be delayed by 1 uframe and result in an unrecoverable
35559 + * lag. Unmask the NYET interrupt.
35560 + */
35561 + st->expected_uframe = (hfnum.b.frnum + 1) & 0x3FFF;
35562 + st->fsm = FIQ_PER_CSPLIT_BROKEN_NYET1;
35563 + restart = 1;
35564 + }
35565 + handled = 1;
35566 + } else if (hcint.b.xacterr) {
35567 + /* 3-strikes retry is enabled, we have hit our max nr_errors */
35568 + st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
35569 + start_next_periodic = 1;
35570 + } else {
35571 + st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
35572 + start_next_periodic = 1;
35573 + }
35574 + /* We can now queue the next isochronous OUT transaction, if one is pending. */
35575 + if(fiq_fsm_tt_next_isoc(state, num_channels, n)) {
35576 + fiq_print(FIQDBG_INT, state, "NEXTISO ");
35577 + }
35578 + break;
35579 +
35580 + case FIQ_PER_CSPLIT_NYET1:
35581 + /* First CSPLIT attempt was a NYET. If we get a subsequent NYET,
35582 + * we are too late and the TT has dropped its CSPLIT fifo.
35583 + */
35584 + hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
35585 + hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
35586 + start_next_periodic = 1;
35587 + if (hcint.b.nak) {
35588 + st->fsm = FIQ_PER_SPLIT_DONE;
35589 + } else if (hcint.b.xfercomp) {
35590 + fiq_increment_dma_buf(state, num_channels, n);
35591 + st->fsm = FIQ_PER_CSPLIT_POLL;
35592 + st->nr_errors = 0;
35593 + if (fiq_fsm_more_csplits(state, n, &last_csplit)) {
35594 + handled = 1;
35595 + restart = 1;
35596 + if (!last_csplit)
35597 + start_next_periodic = 0;
35598 + } else {
35599 + st->fsm = FIQ_PER_SPLIT_DONE;
35600 + }
35601 + } else if (hcint.b.nyet) {
35602 + /* Doh. Data lost. */
35603 + st->fsm = FIQ_PER_SPLIT_NYET_ABORTED;
35604 + } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) {
35605 + st->fsm = FIQ_PER_SPLIT_LS_ABORTED;
35606 + } else {
35607 + st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
35608 + }
35609 + break;
35610 +
35611 + case FIQ_PER_CSPLIT_BROKEN_NYET1:
35612 + /*
35613 + * we got here because our host channel is in the delayed-interrupt
35614 + * state and we cannot take a NYET interrupt any later than when it
35615 + * occurred. Disable then re-enable the channel if this happens to force
35616 + * CSPLITs to occur at the right time.
35617 + */
35618 + hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
35619 + hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
35620 + fiq_print(FIQDBG_INT, state, "BROK: %01d ", n);
35621 + if (hcint.b.nak) {
35622 + st->fsm = FIQ_PER_SPLIT_DONE;
35623 + start_next_periodic = 1;
35624 + } else if (hcint.b.xfercomp) {
35625 + fiq_increment_dma_buf(state, num_channels, n);
35626 + if (fiq_fsm_more_csplits(state, n, &last_csplit)) {
35627 + st->fsm = FIQ_PER_CSPLIT_POLL;
35628 + handled = 1;
35629 + restart = 1;
35630 + start_next_periodic = 1;
35631 + /* Reload HCTSIZ for the next transfer */
35632 + fiq_fsm_reload_hctsiz(state, n);
35633 + if (!last_csplit)
35634 + start_next_periodic = 0;
35635 + } else {
35636 + st->fsm = FIQ_PER_SPLIT_DONE;
35637 + }
35638 + } else if (hcint.b.nyet) {
35639 + st->fsm = FIQ_PER_SPLIT_NYET_ABORTED;
35640 + start_next_periodic = 1;
35641 + } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) {
35642 + /* Local 3-strikes retry is handled by the core. This is a ERR response.*/
35643 + st->fsm = FIQ_PER_SPLIT_LS_ABORTED;
35644 + } else {
35645 + st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
35646 + }
35647 + break;
35648 +
35649 + case FIQ_PER_CSPLIT_POLL:
35650 + hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
35651 + hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
35652 + start_next_periodic = 1;
35653 + if (hcint.b.nak) {
35654 + st->fsm = FIQ_PER_SPLIT_DONE;
35655 + } else if (hcint.b.xfercomp) {
35656 + fiq_increment_dma_buf(state, num_channels, n);
35657 + if (fiq_fsm_more_csplits(state, n, &last_csplit)) {
35658 + handled = 1;
35659 + restart = 1;
35660 + /* Reload HCTSIZ for the next transfer */
35661 + fiq_fsm_reload_hctsiz(state, n);
35662 + if (!last_csplit)
35663 + start_next_periodic = 0;
35664 + } else {
35665 + st->fsm = FIQ_PER_SPLIT_DONE;
35666 + }
35667 + } else if (hcint.b.nyet) {
35668 + /* Are we a NYET after the first data packet? */
35669 + if (st->nrpackets == 0) {
35670 + st->fsm = FIQ_PER_CSPLIT_NYET1;
35671 + handled = 1;
35672 + restart = 1;
35673 + } else {
35674 + /* We got a NYET when polling CSPLITs. Can happen
35675 + * if our heuristic fails, or if someone disables us
35676 + * for any significant length of time.
35677 + */
35678 + if (st->nr_errors >= 3) {
35679 + st->fsm = FIQ_PER_SPLIT_NYET_ABORTED;
35680 + } else {
35681 + st->fsm = FIQ_PER_SPLIT_DONE;
35682 + }
35683 + }
35684 + } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) {
35685 + /* For xacterr, Local 3-strikes retry is handled by the core. This is a ERR response.*/
35686 + st->fsm = FIQ_PER_SPLIT_LS_ABORTED;
35687 + } else {
35688 + st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
35689 + }
35690 + break;
35691 +
35692 + case FIQ_HS_ISOC_TURBO:
35693 + if (fiq_fsm_update_hs_isoc(state, n, hcint)) {
35694 + /* more transactions to come */
35695 + handled = 1;
35696 + restart = 1;
35697 + fiq_print(FIQDBG_INT, state, "HSISO M ");
35698 + } else {
35699 + st->fsm = FIQ_HS_ISOC_DONE;
35700 + fiq_print(FIQDBG_INT, state, "HSISO F ");
35701 + }
35702 + break;
35703 +
35704 + case FIQ_HS_ISOC_ABORTED:
35705 + /* This abort is called by the driver rewriting the state mid-transaction
35706 + * which allows the dequeue mechanism to work more effectively.
35707 + */
35708 + break;
35709 +
35710 + case FIQ_PER_ISO_OUT_ACTIVE:
35711 + if (hcint.b.ack) {
35712 + if(fiq_iso_out_advance(state, num_channels, n)) {
35713 + /* last OUT transfer */
35714 + st->fsm = FIQ_PER_ISO_OUT_LAST;
35715 + /*
35716 + * Assuming the periodic FIFO in the dwc core
35717 + * actually does its job properly, we can queue
35718 + * the next ssplit now and in theory, the wire
35719 + * transactions will be in-order.
35720 + */
35721 + // No it doesn't. It appears to process requests in host channel order.
35722 + //start_next_periodic = 1;
35723 + }
35724 + handled = 1;
35725 + restart = 1;
35726 + } else {
35727 + /*
35728 + * Isochronous transactions carry on regardless. Log the error
35729 + * and continue.
35730 + */
35731 + //explode += 1;
35732 + st->nr_errors++;
35733 + if(fiq_iso_out_advance(state, num_channels, n)) {
35734 + st->fsm = FIQ_PER_ISO_OUT_LAST;
35735 + //start_next_periodic = 1;
35736 + }
35737 + handled = 1;
35738 + restart = 1;
35739 + }
35740 + break;
35741 +
35742 + case FIQ_PER_ISO_OUT_LAST:
35743 + if (hcint.b.ack) {
35744 + /* All done here */
35745 + st->fsm = FIQ_PER_ISO_OUT_DONE;
35746 + } else {
35747 + st->fsm = FIQ_PER_ISO_OUT_DONE;
35748 + st->nr_errors++;
35749 + }
35750 + start_next_periodic = 1;
35751 + break;
35752 +
35753 + case FIQ_PER_SPLIT_TIMEOUT:
35754 + /* SOF kicked us because we overran. */
35755 + start_next_periodic = 1;
35756 + break;
35757 +
35758 + default:
35759 + break;
35760 + }
35761 +
35762 + if (handled) {
35763 + FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT, hcint.d32);
35764 + } else {
35765 + /* Copy the regs into the state so the IRQ knows what to do */
35766 + st->hcint_copy.d32 = hcint.d32;
35767 + }
35768 +
35769 + if (restart) {
35770 + /* Restart always implies handled. */
35771 + if (restart == 2) {
35772 + /* For complete-split INs, the show must go on.
35773 + * Force a channel restart */
35774 + fiq_fsm_restart_channel(state, n, 1);
35775 + } else {
35776 + fiq_fsm_restart_channel(state, n, 0);
35777 + }
35778 + }
35779 + if (start_next_periodic) {
35780 + fiq_fsm_start_next_periodic(state, num_channels);
35781 + }
35782 + if (st->fsm != FIQ_PASSTHROUGH)
35783 + fiq_print(FIQDBG_INT, state, "FSMOUT%02d", st->fsm);
35784 +
35785 + return handled;
35786 +}
35787 +
35788 +
35789 +/**
35790 + * dwc_otg_fiq_fsm() - Flying State Machine (monster) FIQ
35791 + * @state: pointer to state struct passed from the banked FIQ mode registers.
35792 + * @num_channels: set according to the DWC hardware configuration
35793 + * @dma: pointer to DMA bounce buffers for split transaction slots
35794 + *
35795 + * The FSM FIQ performs the low-level tasks that normally would be performed by the microcode
35796 + * inside an EHCI or similar host controller regarding split transactions. The DWC core
35797 + * interrupts each and every time a split transaction packet is received or sent successfully.
35798 + * This results in either an interrupt storm when everything is working "properly", or
35799 + * the interrupt latency of the system in general breaks time-sensitive periodic split
35800 + * transactions. Pushing the low-level, but relatively easy state machine work into the FIQ
35801 + * solves these problems.
35802 + *
35803 + * Return: void
35804 + */
35805 +void notrace dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels)
35806 +{
35807 + gintsts_data_t gintsts, gintsts_handled;
35808 + gintmsk_data_t gintmsk;
35809 + //hfnum_data_t hfnum;
35810 + haint_data_t haint, haint_handled;
35811 + haintmsk_data_t haintmsk;
35812 + int kick_irq = 0;
35813 +
35814 + gintsts_handled.d32 = 0;
35815 + haint_handled.d32 = 0;
35816 +
35817 + fiq_fsm_spin_lock(&state->lock);
35818 + gintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS);
35819 + gintmsk.d32 = FIQ_READ(state->dwc_regs_base + GINTMSK);
35820 + gintsts.d32 &= gintmsk.d32;
35821 +
35822 + if (gintsts.b.sofintr) {
35823 + /* For FSM mode, SOF is required to keep the state machine advance for
35824 + * certain stages of the periodic pipeline. It's death to mask this
35825 + * interrupt in that case.
35826 + */
35827 +
35828 + if (!fiq_fsm_do_sof(state, num_channels)) {
35829 + /* Kick IRQ once. Queue advancement means that all pending transactions
35830 + * will get serviced when the IRQ finally executes.
35831 + */
35832 + if (state->gintmsk_saved.b.sofintr == 1)
35833 + kick_irq |= 1;
35834 + state->gintmsk_saved.b.sofintr = 0;
35835 + }
35836 + gintsts_handled.b.sofintr = 1;
35837 + }
35838 +
35839 + if (gintsts.b.hcintr) {
35840 + int i;
35841 + haint.d32 = FIQ_READ(state->dwc_regs_base + HAINT);
35842 + haintmsk.d32 = FIQ_READ(state->dwc_regs_base + HAINTMSK);
35843 + haint.d32 &= haintmsk.d32;
35844 + haint_handled.d32 = 0;
35845 + for (i=0; i<num_channels; i++) {
35846 + if (haint.b2.chint & (1 << i)) {
35847 + if(!fiq_fsm_do_hcintr(state, num_channels, i)) {
35848 + /* HCINT was not handled in FIQ
35849 + * HAINT is level-sensitive, leading to level-sensitive ginststs.b.hcint bit.
35850 + * Mask HAINT(i) but keep top-level hcint unmasked.
35851 + */
35852 + state->haintmsk_saved.b2.chint &= ~(1 << i);
35853 + } else {
35854 + /* do_hcintr cleaned up after itself, but clear haint */
35855 + haint_handled.b2.chint |= (1 << i);
35856 + }
35857 + }
35858 + }
35859 +
35860 + if (haint_handled.b2.chint) {
35861 + FIQ_WRITE(state->dwc_regs_base + HAINT, haint_handled.d32);
35862 + }
35863 +
35864 + if (haintmsk.d32 != (haintmsk.d32 & state->haintmsk_saved.d32)) {
35865 + /*
35866 + * This is necessary to avoid multiple retriggers of the MPHI in the case
35867 + * where interrupts are held off and HCINTs start to pile up.
35868 + * Only wake up the IRQ if a new interrupt came in, was not handled and was
35869 + * masked.
35870 + */
35871 + haintmsk.d32 &= state->haintmsk_saved.d32;
35872 + FIQ_WRITE(state->dwc_regs_base + HAINTMSK, haintmsk.d32);
35873 + kick_irq |= 1;
35874 + }
35875 + /* Top-Level interrupt - always handled because it's level-sensitive */
35876 + gintsts_handled.b.hcintr = 1;
35877 + }
35878 +
35879 +
35880 + /* Clear the bits in the saved register that were not handled but were triggered. */
35881 + state->gintmsk_saved.d32 &= ~(gintsts.d32 & ~gintsts_handled.d32);
35882 +
35883 + /* FIQ didn't handle something - mask has changed - write new mask */
35884 + if (gintmsk.d32 != (gintmsk.d32 & state->gintmsk_saved.d32)) {
35885 + gintmsk.d32 &= state->gintmsk_saved.d32;
35886 + gintmsk.b.sofintr = 1;
35887 + FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32);
35888 +// fiq_print(FIQDBG_INT, state, "KICKGINT");
35889 +// fiq_print(FIQDBG_INT, state, "%08x", gintmsk.d32);
35890 +// fiq_print(FIQDBG_INT, state, "%08x", state->gintmsk_saved.d32);
35891 + kick_irq |= 1;
35892 + }
35893 +
35894 + if (gintsts_handled.d32) {
35895 + /* Only applies to edge-sensitive bits in GINTSTS */
35896 + FIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32);
35897 + }
35898 +
35899 + /* We got an interrupt, didn't handle it. */
35900 + if (kick_irq) {
35901 + state->mphi_int_count++;
35902 + FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send);
35903 + FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
35904 +
35905 + }
35906 + state->fiq_done++;
35907 + mb();
35908 + fiq_fsm_spin_unlock(&state->lock);
35909 +}
35910 +
35911 +
35912 +/**
35913 + * dwc_otg_fiq_nop() - FIQ "lite"
35914 + * @state: pointer to state struct passed from the banked FIQ mode registers.
35915 + *
35916 + * The "nop" handler does not intervene on any interrupts other than SOF.
35917 + * It is limited in scope to deciding at each SOF if the IRQ SOF handler (which deals
35918 + * with non-periodic/periodic queues) needs to be kicked.
35919 + *
35920 + * This is done to hold off the SOF interrupt, which occurs at a rate of 8000 per second.
35921 + *
35922 + * Return: void
35923 + */
35924 +void notrace dwc_otg_fiq_nop(struct fiq_state *state)
35925 +{
35926 + gintsts_data_t gintsts, gintsts_handled;
35927 + gintmsk_data_t gintmsk;
35928 + hfnum_data_t hfnum;
35929 +
35930 + fiq_fsm_spin_lock(&state->lock);
35931 + hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
35932 + gintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS);
35933 + gintmsk.d32 = FIQ_READ(state->dwc_regs_base + GINTMSK);
35934 + gintsts.d32 &= gintmsk.d32;
35935 + gintsts_handled.d32 = 0;
35936 +
35937 + if (gintsts.b.sofintr) {
35938 + if (!state->kick_np_queues &&
35939 + dwc_frame_num_gt(state->next_sched_frame, hfnum.b.frnum)) {
35940 + /* SOF handled, no work to do, just ACK interrupt */
35941 + gintsts_handled.b.sofintr = 1;
35942 + } else {
35943 + /* Kick IRQ */
35944 + state->gintmsk_saved.b.sofintr = 0;
35945 + }
35946 + }
35947 +
35948 + /* Reset handled interrupts */
35949 + if(gintsts_handled.d32) {
35950 + FIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32);
35951 + }
35952 +
35953 + /* Clear the bits in the saved register that were not handled but were triggered. */
35954 + state->gintmsk_saved.d32 &= ~(gintsts.d32 & ~gintsts_handled.d32);
35955 +
35956 + /* We got an interrupt, didn't handle it and want to mask it */
35957 + if (~(state->gintmsk_saved.d32)) {
35958 + state->mphi_int_count++;
35959 + gintmsk.d32 &= state->gintmsk_saved.d32;
35960 + FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32);
35961 + /* Force a clear before another dummy send */
35962 + FIQ_WRITE(state->mphi_regs.intstat, (1<<29));
35963 + FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send);
35964 + FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
35965 +
35966 + }
35967 + state->fiq_done++;
35968 + mb();
35969 + fiq_fsm_spin_unlock(&state->lock);
35970 +}
35971 --- /dev/null
35972 +++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h
35973 @@ -0,0 +1,367 @@
35974 +/*
35975 + * dwc_otg_fiq_fsm.h - Finite state machine FIQ header definitions
35976 + *
35977 + * Copyright (c) 2013 Raspberry Pi Foundation
35978 + *
35979 + * Author: Jonathan Bell <jonathan@raspberrypi.org>
35980 + * All rights reserved.
35981 + *
35982 + * Redistribution and use in source and binary forms, with or without
35983 + * modification, are permitted provided that the following conditions are met:
35984 + * * Redistributions of source code must retain the above copyright
35985 + * notice, this list of conditions and the following disclaimer.
35986 + * * Redistributions in binary form must reproduce the above copyright
35987 + * notice, this list of conditions and the following disclaimer in the
35988 + * documentation and/or other materials provided with the distribution.
35989 + * * Neither the name of Raspberry Pi nor the
35990 + * names of its contributors may be used to endorse or promote products
35991 + * derived from this software without specific prior written permission.
35992 + *
35993 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
35994 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
35995 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35996 + * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
35997 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
35998 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
35999 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
36000 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36001 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36002 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36003 + *
36004 + * This FIQ implements functionality that performs split transactions on
36005 + * the dwc_otg hardware without any outside intervention. A split transaction
36006 + * is "queued" by nominating a specific host channel to perform the entirety
36007 + * of a split transaction. This FIQ will then perform the microframe-precise
36008 + * scheduling required in each phase of the transaction until completion.
36009 + *
36010 + * The FIQ functionality has been surgically implanted into the Synopsys
36011 + * vendor-provided driver.
36012 + *
36013 + */
36014 +
36015 +#ifndef DWC_OTG_FIQ_FSM_H_
36016 +#define DWC_OTG_FIQ_FSM_H_
36017 +
36018 +#include "dwc_otg_regs.h"
36019 +#include "dwc_otg_cil.h"
36020 +#include "dwc_otg_hcd.h"
36021 +#include <linux/kernel.h>
36022 +#include <linux/irqflags.h>
36023 +#include <linux/string.h>
36024 +#include <asm/barrier.h>
36025 +
36026 +#if 0
36027 +#define FLAME_ON(x) \
36028 +do { \
36029 + int gpioreg; \
36030 + \
36031 + gpioreg = readl(__io_address(0x20200000+0x8)); \
36032 + gpioreg &= ~(7 << (x-20)*3); \
36033 + gpioreg |= 0x1 << (x-20)*3; \
36034 + writel(gpioreg, __io_address(0x20200000+0x8)); \
36035 + \
36036 + writel(1<<x, __io_address(0x20200000+(0x1C))); \
36037 +} while (0)
36038 +
36039 +#define FLAME_OFF(x) \
36040 +do { \
36041 + writel(1<<x, __io_address(0x20200000+(0x28))); \
36042 +} while (0)
36043 +#else
36044 +#define FLAME_ON(x) do { } while (0)
36045 +#define FLAME_OFF(X) do { } while (0)
36046 +#endif
36047 +
36048 +/* This is a quick-and-dirty arch-specific register read/write. We know that
36049 + * writes to a peripheral on BCM2835 will always arrive in-order, also that
36050 + * reads and writes are executed in-order therefore the need for memory barriers
36051 + * is obviated if we're only talking to USB.
36052 + */
36053 +#define FIQ_WRITE(_addr_,_data_) (*(volatile unsigned int *) (_addr_) = (_data_))
36054 +#define FIQ_READ(_addr_) (*(volatile unsigned int *) (_addr_))
36055 +
36056 +/* FIQ-ified register definitions. Offsets are from dwc_regs_base. */
36057 +#define GINTSTS 0x014
36058 +#define GINTMSK 0x018
36059 +/* Debug register. Poll the top of the received packets FIFO. */
36060 +#define GRXSTSR 0x01C
36061 +#define HFNUM 0x408
36062 +#define HAINT 0x414
36063 +#define HAINTMSK 0x418
36064 +#define HPRT0 0x440
36065 +
36066 +/* HC_regs start from an offset of 0x500 */
36067 +#define HC_START 0x500
36068 +#define HC_OFFSET 0x020
36069 +
36070 +#define HC_DMA 0x514
36071 +
36072 +#define HCCHAR 0x00
36073 +#define HCSPLT 0x04
36074 +#define HCINT 0x08
36075 +#define HCINTMSK 0x0C
36076 +#define HCTSIZ 0x10
36077 +
36078 +#define ISOC_XACTPOS_ALL 0b11
36079 +#define ISOC_XACTPOS_BEGIN 0b10
36080 +#define ISOC_XACTPOS_MID 0b00
36081 +#define ISOC_XACTPOS_END 0b01
36082 +
36083 +#define DWC_PID_DATA2 0b01
36084 +#define DWC_PID_MDATA 0b11
36085 +#define DWC_PID_DATA1 0b10
36086 +#define DWC_PID_DATA0 0b00
36087 +
36088 +typedef struct {
36089 + volatile void* base;
36090 + volatile void* ctrl;
36091 + volatile void* outdda;
36092 + volatile void* outddb;
36093 + volatile void* intstat;
36094 +} mphi_regs_t;
36095 +
36096 +enum fiq_debug_level {
36097 + FIQDBG_SCHED = (1 << 0),
36098 + FIQDBG_INT = (1 << 1),
36099 + FIQDBG_ERR = (1 << 2),
36100 + FIQDBG_PORTHUB = (1 << 3),
36101 +};
36102 +
36103 +typedef struct {
36104 + union {
36105 + uint32_t slock;
36106 + struct _tickets {
36107 + uint16_t owner;
36108 + uint16_t next;
36109 + } tickets;
36110 + };
36111 +} fiq_lock_t;
36112 +
36113 +struct fiq_state;
36114 +
36115 +extern void _fiq_print (enum fiq_debug_level dbg_lvl, volatile struct fiq_state *state, char *fmt, ...);
36116 +#if 0
36117 +#define fiq_print _fiq_print
36118 +#else
36119 +#define fiq_print(x, y, ...)
36120 +#endif
36121 +
36122 +extern bool fiq_enable, fiq_fsm_enable;
36123 +extern ushort nak_holdoff;
36124 +
36125 +/**
36126 + * enum fiq_fsm_state - The FIQ FSM states.
36127 + *
36128 + * This is the "core" of the FIQ FSM. Broadly, the FSM states follow the
36129 + * USB2.0 specification for host responses to various transaction states.
36130 + * There are modifications to this host state machine because of a variety of
36131 + * quirks and limitations in the dwc_otg hardware.
36132 + *
36133 + * The fsm state is also used to communicate back to the driver on completion of
36134 + * a split transaction. The end states are used in conjunction with the interrupts
36135 + * raised by the final transaction.
36136 + */
36137 +enum fiq_fsm_state {
36138 + /* FIQ isn't enabled for this host channel */
36139 + FIQ_PASSTHROUGH = 0,
36140 + /* For the first interrupt received for this channel,
36141 + * the FIQ has to ack any interrupts indicating success. */
36142 + FIQ_PASSTHROUGH_ERRORSTATE = 31,
36143 + /* Nonperiodic state groups */
36144 + FIQ_NP_SSPLIT_STARTED = 1,
36145 + FIQ_NP_SSPLIT_RETRY = 2,
36146 + FIQ_NP_OUT_CSPLIT_RETRY = 3,
36147 + FIQ_NP_IN_CSPLIT_RETRY = 4,
36148 + FIQ_NP_SPLIT_DONE = 5,
36149 + FIQ_NP_SPLIT_LS_ABORTED = 6,
36150 + /* This differentiates a HS transaction error from a LS one
36151 + * (handling the hub state is different) */
36152 + FIQ_NP_SPLIT_HS_ABORTED = 7,
36153 +
36154 + /* Periodic state groups */
36155 + /* Periodic transactions are either started directly by the IRQ handler
36156 + * or deferred if the TT is already in use.
36157 + */
36158 + FIQ_PER_SSPLIT_QUEUED = 8,
36159 + FIQ_PER_SSPLIT_STARTED = 9,
36160 + FIQ_PER_SSPLIT_LAST = 10,
36161 +
36162 +
36163 + FIQ_PER_ISO_OUT_PENDING = 11,
36164 + FIQ_PER_ISO_OUT_ACTIVE = 12,
36165 + FIQ_PER_ISO_OUT_LAST = 13,
36166 + FIQ_PER_ISO_OUT_DONE = 27,
36167 +
36168 + FIQ_PER_CSPLIT_WAIT = 14,
36169 + FIQ_PER_CSPLIT_NYET1 = 15,
36170 + FIQ_PER_CSPLIT_BROKEN_NYET1 = 28,
36171 + FIQ_PER_CSPLIT_NYET_FAFF = 29,
36172 + /* For multiple CSPLITs (large isoc IN, or delayed interrupt) */
36173 + FIQ_PER_CSPLIT_POLL = 16,
36174 + /* The last CSPLIT for a transaction has been issued, differentiates
36175 + * for the state machine to queue the next packet.
36176 + */
36177 + FIQ_PER_CSPLIT_LAST = 17,
36178 +
36179 + FIQ_PER_SPLIT_DONE = 18,
36180 + FIQ_PER_SPLIT_LS_ABORTED = 19,
36181 + FIQ_PER_SPLIT_HS_ABORTED = 20,
36182 + FIQ_PER_SPLIT_NYET_ABORTED = 21,
36183 + /* Frame rollover has occurred without the transaction finishing. */
36184 + FIQ_PER_SPLIT_TIMEOUT = 22,
36185 +
36186 + /* FIQ-accelerated HS Isochronous state groups */
36187 + FIQ_HS_ISOC_TURBO = 23,
36188 + /* For interval > 1, SOF wakes up the isochronous FSM */
36189 + FIQ_HS_ISOC_SLEEPING = 24,
36190 + FIQ_HS_ISOC_DONE = 25,
36191 + FIQ_HS_ISOC_ABORTED = 26,
36192 + FIQ_DEQUEUE_ISSUED = 30,
36193 + FIQ_TEST = 32,
36194 +};
36195 +
36196 +struct fiq_stack {
36197 + int magic1;
36198 + uint8_t stack[2048];
36199 + int magic2;
36200 +};
36201 +
36202 +
36203 +/**
36204 + * struct fiq_dma_info - DMA bounce buffer utilisation information (per-channel)
36205 + * @index: Number of slots reported used for IN transactions / number of slots
36206 + * transmitted for an OUT transaction
36207 + * @slot_len[6]: Number of actual transfer bytes in each slot (255 if unused)
36208 + *
36209 + * Split transaction transfers can have variable length depending on other bus
36210 + * traffic. The OTG core DMA engine requires 4-byte aligned addresses therefore
36211 + * each transaction needs a guaranteed aligned address. A maximum of 6 split transfers
36212 + * can happen per-frame.
36213 + */
36214 +struct fiq_dma_info {
36215 + u8 index;
36216 + u8 slot_len[6];
36217 +};
36218 +
36219 +struct __attribute__((packed)) fiq_split_dma_slot {
36220 + u8 buf[188];
36221 +};
36222 +
36223 +struct fiq_dma_channel {
36224 + struct __attribute__((packed)) fiq_split_dma_slot index[6];
36225 +};
36226 +
36227 +struct fiq_dma_blob {
36228 + struct __attribute__((packed)) fiq_dma_channel channel[0];
36229 +};
36230 +
36231 +/**
36232 + * struct fiq_hs_isoc_info - USB2.0 isochronous data
36233 + * @iso_frame: Pointer to the array of OTG URB iso_frame_descs.
36234 + * @nrframes: Total length of iso_frame_desc array
36235 + * @index: Current index (FIQ-maintained)
36236 + *
36237 + */
36238 +struct fiq_hs_isoc_info {
36239 + struct dwc_otg_hcd_iso_packet_desc *iso_desc;
36240 + unsigned int nrframes;
36241 + unsigned int index;
36242 +};
36243 +
36244 +/**
36245 + * struct fiq_channel_state - FIQ state machine storage
36246 + * @fsm: Current state of the channel as understood by the FIQ
36247 + * @nr_errors: Number of transaction errors on this split-transaction
36248 + * @hub_addr: SSPLIT/CSPLIT destination hub
36249 + * @port_addr: SSPLIT/CSPLIT destination port - always 1 if single TT hub
36250 + * @nrpackets: For isoc OUT, the number of split-OUT packets to transmit. For
36251 + * split-IN, number of CSPLIT data packets that were received.
36252 + * @hcchar_copy:
36253 + * @hcsplt_copy:
36254 + * @hcintmsk_copy:
36255 + * @hctsiz_copy: Copies of the host channel registers.
36256 + * For use as scratch, or for returning state.
36257 + *
36258 + * The fiq_channel_state is state storage between interrupts for a host channel. The
36259 + * FSM state is stored here. Members of this structure must only be set up by the
36260 + * driver prior to enabling the FIQ for this host channel, and not touched until the FIQ
36261 + * has updated the state to either a COMPLETE state group or ABORT state group.
36262 + */
36263 +
36264 +struct fiq_channel_state {
36265 + enum fiq_fsm_state fsm;
36266 + unsigned int nr_errors;
36267 + unsigned int hub_addr;
36268 + unsigned int port_addr;
36269 + /* Hardware bug workaround: sometimes channel halt interrupts are
36270 + * delayed until the next SOF. Keep track of when we expected to get interrupted. */
36271 + unsigned int expected_uframe;
36272 + /* in/out for communicating number of dma buffers used, or number of ISOC to do */
36273 + unsigned int nrpackets;
36274 + struct fiq_dma_info dma_info;
36275 + struct fiq_hs_isoc_info hs_isoc_info;
36276 + /* Copies of HC registers - in/out communication from/to IRQ handler
36277 + * and for ease of channel setup. A bit of mungeing is performed - for
36278 + * example the hctsiz.b.maxp is _always_ the max packet size of the endpoint.
36279 + */
36280 + hcchar_data_t hcchar_copy;
36281 + hcsplt_data_t hcsplt_copy;
36282 + hcint_data_t hcint_copy;
36283 + hcintmsk_data_t hcintmsk_copy;
36284 + hctsiz_data_t hctsiz_copy;
36285 + hcdma_data_t hcdma_copy;
36286 +};
36287 +
36288 +/**
36289 + * struct fiq_state - top-level FIQ state machine storage
36290 + * @mphi_regs: virtual address of the MPHI peripheral register file
36291 + * @dwc_regs_base: virtual address of the base of the DWC core register file
36292 + * @dma_base: physical address for the base of the DMA bounce buffers
36293 + * @dummy_send: Scratch area for sending a fake message to the MPHI peripheral
36294 + * @gintmsk_saved: Top-level mask of interrupts that the FIQ has not handled.
36295 + * Used for determining which interrupts fired to set off the IRQ handler.
36296 + * @haintmsk_saved: Mask of interrupts from host channels that the FIQ did not handle internally.
36297 + * @np_count: Non-periodic transactions in the active queue
36298 + * @np_sent: Count of non-periodic transactions that have completed
36299 + * @next_sched_frame: For periodic transactions handled by the driver's SOF-driven queuing mechanism,
36300 + * this is the next frame on which a SOF interrupt is required. Used to hold off
36301 + * passing SOF through to the driver until necessary.
36302 + * @channel[n]: Per-channel FIQ state. Allocated during init depending on the number of host
36303 + * channels configured into the core logic.
36304 + *
36305 + * This is passed as the first argument to the dwc_otg_fiq_fsm top-level FIQ handler from the asm stub.
36306 + * It contains top-level state information.
36307 + */
36308 +struct fiq_state {
36309 + fiq_lock_t lock;
36310 + mphi_regs_t mphi_regs;
36311 + void *dwc_regs_base;
36312 + dma_addr_t dma_base;
36313 + struct fiq_dma_blob *fiq_dmab;
36314 + void *dummy_send;
36315 + gintmsk_data_t gintmsk_saved;
36316 + haintmsk_data_t haintmsk_saved;
36317 + int mphi_int_count;
36318 + unsigned int fiq_done;
36319 + unsigned int kick_np_queues;
36320 + unsigned int next_sched_frame;
36321 +#ifdef FIQ_DEBUG
36322 + char * buffer;
36323 + unsigned int bufsiz;
36324 +#endif
36325 + struct fiq_channel_state channel[0];
36326 +};
36327 +
36328 +extern void fiq_fsm_spin_lock(fiq_lock_t *lock);
36329 +
36330 +extern void fiq_fsm_spin_unlock(fiq_lock_t *lock);
36331 +
36332 +extern int fiq_fsm_too_late(struct fiq_state *st, int n);
36333 +
36334 +extern int fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n);
36335 +
36336 +extern void dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels);
36337 +
36338 +extern void dwc_otg_fiq_nop(struct fiq_state *state);
36339 +
36340 +#endif /* DWC_OTG_FIQ_FSM_H_ */
36341 --- /dev/null
36342 +++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S
36343 @@ -0,0 +1,80 @@
36344 +/*
36345 + * dwc_otg_fiq_fsm.S - assembly stub for the FSM FIQ
36346 + *
36347 + * Copyright (c) 2013 Raspberry Pi Foundation
36348 + *
36349 + * Author: Jonathan Bell <jonathan@raspberrypi.org>
36350 + * All rights reserved.
36351 + *
36352 + * Redistribution and use in source and binary forms, with or without
36353 + * modification, are permitted provided that the following conditions are met:
36354 + * * Redistributions of source code must retain the above copyright
36355 + * notice, this list of conditions and the following disclaimer.
36356 + * * Redistributions in binary form must reproduce the above copyright
36357 + * notice, this list of conditions and the following disclaimer in the
36358 + * documentation and/or other materials provided with the distribution.
36359 + * * Neither the name of Raspberry Pi nor the
36360 + * names of its contributors may be used to endorse or promote products
36361 + * derived from this software without specific prior written permission.
36362 + *
36363 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
36364 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
36365 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36366 + * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
36367 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36368 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
36369 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
36370 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36371 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36372 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36373 + */
36374 +
36375 +
36376 +#include <asm/assembler.h>
36377 +#include <linux/linkage.h>
36378 +
36379 +
36380 +.text
36381 +
36382 +.global _dwc_otg_fiq_stub_end;
36383 +
36384 +/**
36385 + * _dwc_otg_fiq_stub() - entry copied to the FIQ vector page to allow
36386 + * a C-style function call with arguments from the FIQ banked registers.
36387 + * r0 = &hcd->fiq_state
36388 + * r1 = &hcd->num_channels
36389 + * r2 = &hcd->dma_buffers
36390 + * Tramples: r0, r1, r2, r4, fp, ip
36391 + */
36392 +
36393 +ENTRY(_dwc_otg_fiq_stub)
36394 + /* Stash unbanked regs - SP will have been set up for us */
36395 + mov ip, sp;
36396 + stmdb sp!, {r0-r12, lr};
36397 +#ifdef FIQ_DEBUG
36398 + // Cycle profiling - read cycle counter at start
36399 + mrc p15, 0, r5, c15, c12, 1;
36400 +#endif
36401 + /* r11 = fp, don't trample it */
36402 + mov r4, fp;
36403 + /* set EABI frame size */
36404 + sub fp, ip, #512;
36405 +
36406 + /* for fiq NOP mode - just need state */
36407 + mov r0, r8;
36408 + /* r9 = num_channels */
36409 + mov r1, r9;
36410 + /* r10 = struct *dma_bufs */
36411 +// mov r2, r10;
36412 +
36413 + /* r4 = &fiq_c_function */
36414 + blx r4;
36415 +#ifdef FIQ_DEBUG
36416 + mrc p15, 0, r4, c15, c12, 1;
36417 + subs r5, r5, r4;
36418 + // r5 is now the cycle count time for executing the FIQ. Store it somewhere?
36419 +#endif
36420 + ldmia sp!, {r0-r12, lr};
36421 + subs pc, lr, #4;
36422 +_dwc_otg_fiq_stub_end:
36423 +END(_dwc_otg_fiq_stub)
36424 --- /dev/null
36425 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
36426 @@ -0,0 +1,4252 @@
36427 +
36428 +/* ==========================================================================
36429 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
36430 + * $Revision: #104 $
36431 + * $Date: 2011/10/24 $
36432 + * $Change: 1871159 $
36433 + *
36434 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
36435 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
36436 + * otherwise expressly agreed to in writing between Synopsys and you.
36437 + *
36438 + * The Software IS NOT an item of Licensed Software or Licensed Product under
36439 + * any End User Software License Agreement or Agreement for Licensed Product
36440 + * with Synopsys or any supplement thereto. You are permitted to use and
36441 + * redistribute this Software in source and binary forms, with or without
36442 + * modification, provided that redistributions of source code must retain this
36443 + * notice. You may not view, use, disclose, copy or distribute this file or
36444 + * any information contained herein except pursuant to this license grant from
36445 + * Synopsys. If you do not agree with this notice, including the disclaimer
36446 + * below, then you are not authorized to use the Software.
36447 + *
36448 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
36449 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
36450 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36451 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
36452 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36453 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36454 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
36455 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36456 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36457 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
36458 + * DAMAGE.
36459 + * ========================================================================== */
36460 +#ifndef DWC_DEVICE_ONLY
36461 +
36462 +/** @file
36463 + * This file implements HCD Core. All code in this file is portable and doesn't
36464 + * use any OS specific functions.
36465 + * Interface provided by HCD Core is defined in <code><hcd_if.h></code>
36466 + * header file.
36467 + */
36468 +
36469 +#include <linux/usb.h>
36470 +#include <linux/usb/hcd.h>
36471 +
36472 +#include "dwc_otg_hcd.h"
36473 +#include "dwc_otg_regs.h"
36474 +#include "dwc_otg_fiq_fsm.h"
36475 +
36476 +extern bool microframe_schedule;
36477 +extern uint16_t fiq_fsm_mask, nak_holdoff;
36478 +
36479 +//#define DEBUG_HOST_CHANNELS
36480 +#ifdef DEBUG_HOST_CHANNELS
36481 +static int last_sel_trans_num_per_scheduled = 0;
36482 +static int last_sel_trans_num_nonper_scheduled = 0;
36483 +static int last_sel_trans_num_avail_hc_at_start = 0;
36484 +static int last_sel_trans_num_avail_hc_at_end = 0;
36485 +#endif /* DEBUG_HOST_CHANNELS */
36486 +
36487 +
36488 +dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)
36489 +{
36490 + return DWC_ALLOC(sizeof(dwc_otg_hcd_t));
36491 +}
36492 +
36493 +/**
36494 + * Connection timeout function. An OTG host is required to display a
36495 + * message if the device does not connect within 10 seconds.
36496 + */
36497 +void dwc_otg_hcd_connect_timeout(void *ptr)
36498 +{
36499 + DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr);
36500 + DWC_PRINTF("Connect Timeout\n");
36501 + __DWC_ERROR("Device Not Connected/Responding\n");
36502 +}
36503 +
36504 +#if defined(DEBUG)
36505 +static void dump_channel_info(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
36506 +{
36507 + if (qh->channel != NULL) {
36508 + dwc_hc_t *hc = qh->channel;
36509 + dwc_list_link_t *item;
36510 + dwc_otg_qh_t *qh_item;
36511 + int num_channels = hcd->core_if->core_params->host_channels;
36512 + int i;
36513 +
36514 + dwc_otg_hc_regs_t *hc_regs;
36515 + hcchar_data_t hcchar;
36516 + hcsplt_data_t hcsplt;
36517 + hctsiz_data_t hctsiz;
36518 + uint32_t hcdma;
36519 +
36520 + hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
36521 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
36522 + hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
36523 + hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
36524 + hcdma = DWC_READ_REG32(&hc_regs->hcdma);
36525 +
36526 + DWC_PRINTF(" Assigned to channel %p:\n", hc);
36527 + DWC_PRINTF(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32,
36528 + hcsplt.d32);
36529 + DWC_PRINTF(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32,
36530 + hcdma);
36531 + DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
36532 + hc->dev_addr, hc->ep_num, hc->ep_is_in);
36533 + DWC_PRINTF(" ep_type: %d\n", hc->ep_type);
36534 + DWC_PRINTF(" max_packet: %d\n", hc->max_packet);
36535 + DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start);
36536 + DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started);
36537 + DWC_PRINTF(" halt_status: %d\n", hc->halt_status);
36538 + DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff);
36539 + DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len);
36540 + DWC_PRINTF(" qh: %p\n", hc->qh);
36541 + DWC_PRINTF(" NP inactive sched:\n");
36542 + DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) {
36543 + qh_item =
36544 + DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
36545 + DWC_PRINTF(" %p\n", qh_item);
36546 + }
36547 + DWC_PRINTF(" NP active sched:\n");
36548 + DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) {
36549 + qh_item =
36550 + DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
36551 + DWC_PRINTF(" %p\n", qh_item);
36552 + }
36553 + DWC_PRINTF(" Channels: \n");
36554 + for (i = 0; i < num_channels; i++) {
36555 + dwc_hc_t *hc = hcd->hc_ptr_array[i];
36556 + DWC_PRINTF(" %2d: %p\n", i, hc);
36557 + }
36558 + }
36559 +}
36560 +#else
36561 +#define dump_channel_info(hcd, qh)
36562 +#endif /* DEBUG */
36563 +
36564 +/**
36565 + * Work queue function for starting the HCD when A-Cable is connected.
36566 + * The hcd_start() must be called in a process context.
36567 + */
36568 +static void hcd_start_func(void *_vp)
36569 +{
36570 + dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp;
36571 +
36572 + DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd);
36573 + if (hcd) {
36574 + hcd->fops->start(hcd);
36575 + }
36576 +}
36577 +
36578 +static void del_xfer_timers(dwc_otg_hcd_t * hcd)
36579 +{
36580 +#ifdef DEBUG
36581 + int i;
36582 + int num_channels = hcd->core_if->core_params->host_channels;
36583 + for (i = 0; i < num_channels; i++) {
36584 + DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]);
36585 + }
36586 +#endif
36587 +}
36588 +
36589 +static void del_timers(dwc_otg_hcd_t * hcd)
36590 +{
36591 + del_xfer_timers(hcd);
36592 + DWC_TIMER_CANCEL(hcd->conn_timer);
36593 +}
36594 +
36595 +/**
36596 + * Processes all the URBs in a single list of QHs. Completes them with
36597 + * -ESHUTDOWN and frees the QTD.
36598 + */
36599 +static void kill_urbs_in_qh_list(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
36600 +{
36601 + dwc_list_link_t *qh_item, *qh_tmp;
36602 + dwc_otg_qh_t *qh;
36603 + dwc_otg_qtd_t *qtd, *qtd_tmp;
36604 +
36605 + DWC_LIST_FOREACH_SAFE(qh_item, qh_tmp, qh_list) {
36606 + qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry);
36607 + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,
36608 + &qh->qtd_list, qtd_list_entry) {
36609 + qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
36610 + if (qtd->urb != NULL) {
36611 + hcd->fops->complete(hcd, qtd->urb->priv,
36612 + qtd->urb, -DWC_E_SHUTDOWN);
36613 + dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
36614 + }
36615 +
36616 + }
36617 + if(qh->channel) {
36618 + /* Using hcchar.chen == 1 is not a reliable test.
36619 + * It is possible that the channel has already halted
36620 + * but not yet been through the IRQ handler.
36621 + */
36622 + dwc_otg_hc_halt(hcd->core_if, qh->channel,
36623 + DWC_OTG_HC_XFER_URB_DEQUEUE);
36624 + if(microframe_schedule)
36625 + hcd->available_host_channels++;
36626 + qh->channel = NULL;
36627 + }
36628 + dwc_otg_hcd_qh_remove(hcd, qh);
36629 + }
36630 +}
36631 +
36632 +/**
36633 + * Responds with an error status of ESHUTDOWN to all URBs in the non-periodic
36634 + * and periodic schedules. The QTD associated with each URB is removed from
36635 + * the schedule and freed. This function may be called when a disconnect is
36636 + * detected or when the HCD is being stopped.
36637 + */
36638 +static void kill_all_urbs(dwc_otg_hcd_t * hcd)
36639 +{
36640 + kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
36641 + kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
36642 + kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
36643 + kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
36644 + kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
36645 + kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
36646 +}
36647 +
36648 +/**
36649 + * Start the connection timer. An OTG host is required to display a
36650 + * message if the device does not connect within 10 seconds. The
36651 + * timer is deleted if a port connect interrupt occurs before the
36652 + * timer expires.
36653 + */
36654 +static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t * hcd)
36655 +{
36656 + DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */ );
36657 +}
36658 +
36659 +/**
36660 + * HCD Callback function for disconnect of the HCD.
36661 + *
36662 + * @param p void pointer to the <code>struct usb_hcd</code>
36663 + */
36664 +static int32_t dwc_otg_hcd_session_start_cb(void *p)
36665 +{
36666 + dwc_otg_hcd_t *dwc_otg_hcd;
36667 + DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
36668 + dwc_otg_hcd = p;
36669 + dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
36670 + return 1;
36671 +}
36672 +
36673 +/**
36674 + * HCD Callback function for starting the HCD when A-Cable is
36675 + * connected.
36676 + *
36677 + * @param p void pointer to the <code>struct usb_hcd</code>
36678 + */
36679 +static int32_t dwc_otg_hcd_start_cb(void *p)
36680 +{
36681 + dwc_otg_hcd_t *dwc_otg_hcd = p;
36682 + dwc_otg_core_if_t *core_if;
36683 + hprt0_data_t hprt0;
36684 +
36685 + core_if = dwc_otg_hcd->core_if;
36686 +
36687 + if (core_if->op_state == B_HOST) {
36688 + /*
36689 + * Reset the port. During a HNP mode switch the reset
36690 + * needs to occur within 1ms and have a duration of at
36691 + * least 50ms.
36692 + */
36693 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
36694 + hprt0.b.prtrst = 1;
36695 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
36696 + }
36697 + DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,
36698 + hcd_start_func, dwc_otg_hcd, 50,
36699 + "start hcd");
36700 +
36701 + return 1;
36702 +}
36703 +
36704 +/**
36705 + * HCD Callback function for disconnect of the HCD.
36706 + *
36707 + * @param p void pointer to the <code>struct usb_hcd</code>
36708 + */
36709 +static int32_t dwc_otg_hcd_disconnect_cb(void *p)
36710 +{
36711 + gintsts_data_t intr;
36712 + dwc_otg_hcd_t *dwc_otg_hcd = p;
36713 +
36714 + /*
36715 + * Set status flags for the hub driver.
36716 + */
36717 + dwc_otg_hcd->flags.b.port_connect_status_change = 1;
36718 + dwc_otg_hcd->flags.b.port_connect_status = 0;
36719 + if(fiq_enable)
36720 + local_fiq_disable();
36721 + /*
36722 + * Shutdown any transfers in process by clearing the Tx FIFO Empty
36723 + * interrupt mask and status bits and disabling subsequent host
36724 + * channel interrupts.
36725 + */
36726 + intr.d32 = 0;
36727 + intr.b.nptxfempty = 1;
36728 + intr.b.ptxfempty = 1;
36729 + intr.b.hcintr = 1;
36730 + DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk,
36731 + intr.d32, 0);
36732 + DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts,
36733 + intr.d32, 0);
36734 +
36735 + del_timers(dwc_otg_hcd);
36736 +
36737 + /*
36738 + * Turn off the vbus power only if the core has transitioned to device
36739 + * mode. If still in host mode, need to keep power on to detect a
36740 + * reconnection.
36741 + */
36742 + if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
36743 + if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
36744 + hprt0_data_t hprt0 = {.d32 = 0 };
36745 + DWC_PRINTF("Disconnect: PortPower off\n");
36746 + hprt0.b.prtpwr = 0;
36747 + DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,
36748 + hprt0.d32);
36749 + }
36750 +
36751 + dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
36752 + }
36753 +
36754 + /* Respond with an error status to all URBs in the schedule. */
36755 + kill_all_urbs(dwc_otg_hcd);
36756 +
36757 + if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
36758 + /* Clean up any host channels that were in use. */
36759 + int num_channels;
36760 + int i;
36761 + dwc_hc_t *channel;
36762 + dwc_otg_hc_regs_t *hc_regs;
36763 + hcchar_data_t hcchar;
36764 +
36765 + num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
36766 +
36767 + if (!dwc_otg_hcd->core_if->dma_enable) {
36768 + /* Flush out any channel requests in slave mode. */
36769 + for (i = 0; i < num_channels; i++) {
36770 + channel = dwc_otg_hcd->hc_ptr_array[i];
36771 + if (DWC_CIRCLEQ_EMPTY_ENTRY
36772 + (channel, hc_list_entry)) {
36773 + hc_regs =
36774 + dwc_otg_hcd->core_if->
36775 + host_if->hc_regs[i];
36776 + hcchar.d32 =
36777 + DWC_READ_REG32(&hc_regs->hcchar);
36778 + if (hcchar.b.chen) {
36779 + hcchar.b.chen = 0;
36780 + hcchar.b.chdis = 1;
36781 + hcchar.b.epdir = 0;
36782 + DWC_WRITE_REG32
36783 + (&hc_regs->hcchar,
36784 + hcchar.d32);
36785 + }
36786 + }
36787 + }
36788 + }
36789 +
36790 + for (i = 0; i < num_channels; i++) {
36791 + channel = dwc_otg_hcd->hc_ptr_array[i];
36792 + if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) {
36793 + hc_regs =
36794 + dwc_otg_hcd->core_if->host_if->hc_regs[i];
36795 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
36796 + if (hcchar.b.chen) {
36797 + /* Halt the channel. */
36798 + hcchar.b.chdis = 1;
36799 + DWC_WRITE_REG32(&hc_regs->hcchar,
36800 + hcchar.d32);
36801 + }
36802 +
36803 + dwc_otg_hc_cleanup(dwc_otg_hcd->core_if,
36804 + channel);
36805 + DWC_CIRCLEQ_INSERT_TAIL
36806 + (&dwc_otg_hcd->free_hc_list, channel,
36807 + hc_list_entry);
36808 + /*
36809 + * Added for Descriptor DMA to prevent channel double cleanup
36810 + * in release_channel_ddma(). Which called from ep_disable
36811 + * when device disconnect.
36812 + */
36813 + channel->qh = NULL;
36814 + }
36815 + }
36816 + if(fiq_fsm_enable) {
36817 + for(i=0; i < 128; i++) {
36818 + dwc_otg_hcd->hub_port[i] = 0;
36819 + }
36820 + }
36821 +
36822 + }
36823 +
36824 + if(fiq_enable)
36825 + local_fiq_enable();
36826 +
36827 + if (dwc_otg_hcd->fops->disconnect) {
36828 + dwc_otg_hcd->fops->disconnect(dwc_otg_hcd);
36829 + }
36830 +
36831 + return 1;
36832 +}
36833 +
36834 +/**
36835 + * HCD Callback function for stopping the HCD.
36836 + *
36837 + * @param p void pointer to the <code>struct usb_hcd</code>
36838 + */
36839 +static int32_t dwc_otg_hcd_stop_cb(void *p)
36840 +{
36841 + dwc_otg_hcd_t *dwc_otg_hcd = p;
36842 +
36843 + DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
36844 + dwc_otg_hcd_stop(dwc_otg_hcd);
36845 + return 1;
36846 +}
36847 +
36848 +#ifdef CONFIG_USB_DWC_OTG_LPM
36849 +/**
36850 + * HCD Callback function for sleep of HCD.
36851 + *
36852 + * @param p void pointer to the <code>struct usb_hcd</code>
36853 + */
36854 +static int dwc_otg_hcd_sleep_cb(void *p)
36855 +{
36856 + dwc_otg_hcd_t *hcd = p;
36857 +
36858 + dwc_otg_hcd_free_hc_from_lpm(hcd);
36859 +
36860 + return 0;
36861 +}
36862 +#endif
36863 +
36864 +
36865 +/**
36866 + * HCD Callback function for Remote Wakeup.
36867 + *
36868 + * @param p void pointer to the <code>struct usb_hcd</code>
36869 + */
36870 +static int dwc_otg_hcd_rem_wakeup_cb(void *p)
36871 +{
36872 + dwc_otg_hcd_t *hcd = p;
36873 +
36874 + if (hcd->core_if->lx_state == DWC_OTG_L2) {
36875 + hcd->flags.b.port_suspend_change = 1;
36876 + }
36877 +#ifdef CONFIG_USB_DWC_OTG_LPM
36878 + else {
36879 + hcd->flags.b.port_l1_change = 1;
36880 + }
36881 +#endif
36882 + return 0;
36883 +}
36884 +
36885 +/**
36886 + * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
36887 + * stopped.
36888 + */
36889 +void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd)
36890 +{
36891 + hprt0_data_t hprt0 = {.d32 = 0 };
36892 +
36893 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
36894 +
36895 + /*
36896 + * The root hub should be disconnected before this function is called.
36897 + * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
36898 + * and the QH lists (via ..._hcd_endpoint_disable).
36899 + */
36900 +
36901 + /* Turn off all host-specific interrupts. */
36902 + dwc_otg_disable_host_interrupts(hcd->core_if);
36903 +
36904 + /* Turn off the vbus power */
36905 + DWC_PRINTF("PortPower off\n");
36906 + hprt0.b.prtpwr = 0;
36907 + DWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32);
36908 + dwc_mdelay(1);
36909 +}
36910 +
36911 +int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * hcd,
36912 + dwc_otg_hcd_urb_t * dwc_otg_urb, void **ep_handle,
36913 + int atomic_alloc)
36914 +{
36915 + int retval = 0;
36916 + uint8_t needs_scheduling = 0;
36917 + dwc_otg_transaction_type_e tr_type;
36918 + dwc_otg_qtd_t *qtd;
36919 + gintmsk_data_t intr_mask = {.d32 = 0 };
36920 + hprt0_data_t hprt0 = { .d32 = 0 };
36921 +
36922 +#ifdef DEBUG /* integrity checks (Broadcom) */
36923 + if (NULL == hcd->core_if) {
36924 + DWC_ERROR("**** DWC OTG HCD URB Enqueue - HCD has NULL core_if\n");
36925 + /* No longer connected. */
36926 + return -DWC_E_INVALID;
36927 + }
36928 +#endif
36929 + if (!hcd->flags.b.port_connect_status) {
36930 + /* No longer connected. */
36931 + DWC_ERROR("Not connected\n");
36932 + return -DWC_E_NO_DEVICE;
36933 + }
36934 +
36935 + /* Some core configurations cannot support LS traffic on a FS root port */
36936 + if ((hcd->fops->speed(hcd, dwc_otg_urb->priv) == USB_SPEED_LOW) &&
36937 + (hcd->core_if->hwcfg2.b.fs_phy_type == 1) &&
36938 + (hcd->core_if->hwcfg2.b.hs_phy_type == 1)) {
36939 + hprt0.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0);
36940 + if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_FULL_SPEED) {
36941 + return -DWC_E_NO_DEVICE;
36942 + }
36943 + }
36944 +
36945 + qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc);
36946 + if (qtd == NULL) {
36947 + DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
36948 + return -DWC_E_NO_MEMORY;
36949 + }
36950 +#ifdef DEBUG /* integrity checks (Broadcom) */
36951 + if (qtd->urb == NULL) {
36952 + DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD with no URBs\n");
36953 + return -DWC_E_NO_MEMORY;
36954 + }
36955 + if (qtd->urb->priv == NULL) {
36956 + DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD URB with no URB handle\n");
36957 + return -DWC_E_NO_MEMORY;
36958 + }
36959 +#endif
36960 + intr_mask.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk);
36961 + if(!intr_mask.b.sofintr || fiq_enable) needs_scheduling = 1;
36962 + if((((dwc_otg_qh_t *)ep_handle)->ep_type == UE_BULK) && !(qtd->urb->flags & URB_GIVEBACK_ASAP))
36963 + /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */
36964 + needs_scheduling = 0;
36965 +
36966 + retval = dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle, atomic_alloc);
36967 + // creates a new queue in ep_handle if it doesn't exist already
36968 + if (retval < 0) {
36969 + DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
36970 + "Error status %d\n", retval);
36971 + dwc_otg_hcd_qtd_free(qtd);
36972 + return retval;
36973 + }
36974 +
36975 + if(needs_scheduling) {
36976 + tr_type = dwc_otg_hcd_select_transactions(hcd);
36977 + if (tr_type != DWC_OTG_TRANSACTION_NONE) {
36978 + dwc_otg_hcd_queue_transactions(hcd, tr_type);
36979 + }
36980 + }
36981 + return retval;
36982 +}
36983 +
36984 +int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * hcd,
36985 + dwc_otg_hcd_urb_t * dwc_otg_urb)
36986 +{
36987 + dwc_otg_qh_t *qh;
36988 + dwc_otg_qtd_t *urb_qtd;
36989 + BUG_ON(!hcd);
36990 + BUG_ON(!dwc_otg_urb);
36991 +
36992 +#ifdef DEBUG /* integrity checks (Broadcom) */
36993 +
36994 + if (hcd == NULL) {
36995 + DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL HCD\n");
36996 + return -DWC_E_INVALID;
36997 + }
36998 + if (dwc_otg_urb == NULL) {
36999 + DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL URB\n");
37000 + return -DWC_E_INVALID;
37001 + }
37002 + if (dwc_otg_urb->qtd == NULL) {
37003 + DWC_ERROR("**** DWC OTG HCD URB Dequeue with NULL QTD\n");
37004 + return -DWC_E_INVALID;
37005 + }
37006 + urb_qtd = dwc_otg_urb->qtd;
37007 + BUG_ON(!urb_qtd);
37008 + if (urb_qtd->qh == NULL) {
37009 + DWC_ERROR("**** DWC OTG HCD URB Dequeue with QTD with NULL Q handler\n");
37010 + return -DWC_E_INVALID;
37011 + }
37012 +#else
37013 + urb_qtd = dwc_otg_urb->qtd;
37014 + BUG_ON(!urb_qtd);
37015 +#endif
37016 + qh = urb_qtd->qh;
37017 + BUG_ON(!qh);
37018 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
37019 + if (urb_qtd->in_process) {
37020 + dump_channel_info(hcd, qh);
37021 + }
37022 + }
37023 +#ifdef DEBUG /* integrity checks (Broadcom) */
37024 + if (hcd->core_if == NULL) {
37025 + DWC_ERROR("**** DWC OTG HCD URB Dequeue HCD has NULL core_if\n");
37026 + return -DWC_E_INVALID;
37027 + }
37028 +#endif
37029 + if (urb_qtd->in_process && qh->channel) {
37030 + /* The QTD is in process (it has been assigned to a channel). */
37031 + if (hcd->flags.b.port_connect_status) {
37032 + int n = qh->channel->hc_num;
37033 + /*
37034 + * If still connected (i.e. in host mode), halt the
37035 + * channel so it can be used for other transfers. If
37036 + * no longer connected, the host registers can't be
37037 + * written to halt the channel since the core is in
37038 + * device mode.
37039 + */
37040 + /* In FIQ FSM mode, we need to shut down carefully.
37041 + * The FIQ may attempt to restart a disabled channel */
37042 + if (fiq_fsm_enable && (hcd->fiq_state->channel[n].fsm != FIQ_PASSTHROUGH)) {
37043 + qh->channel->halt_status = DWC_OTG_HC_XFER_URB_DEQUEUE;
37044 + qh->channel->halt_pending = 1;
37045 + hcd->fiq_state->channel[n].fsm = FIQ_DEQUEUE_ISSUED;
37046 + } else {
37047 + dwc_otg_hc_halt(hcd->core_if, qh->channel,
37048 + DWC_OTG_HC_XFER_URB_DEQUEUE);
37049 + }
37050 + }
37051 + }
37052 +
37053 + /*
37054 + * Free the QTD and clean up the associated QH. Leave the QH in the
37055 + * schedule if it has any remaining QTDs.
37056 + */
37057 +
37058 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue - "
37059 + "delete %sQueue handler\n",
37060 + hcd->core_if->dma_desc_enable?"DMA ":"");
37061 + if (!hcd->core_if->dma_desc_enable) {
37062 + uint8_t b = urb_qtd->in_process;
37063 + dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
37064 + if (b) {
37065 + dwc_otg_hcd_qh_deactivate(hcd, qh, 0);
37066 + qh->channel = NULL;
37067 + } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
37068 + dwc_otg_hcd_qh_remove(hcd, qh);
37069 + }
37070 + } else {
37071 + dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
37072 + }
37073 + return 0;
37074 +}
37075 +
37076 +int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
37077 + int retry)
37078 +{
37079 + dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
37080 + int retval = 0;
37081 + dwc_irqflags_t flags;
37082 +
37083 + if (retry < 0) {
37084 + retval = -DWC_E_INVALID;
37085 + goto done;
37086 + }
37087 +
37088 + if (!qh) {
37089 + retval = -DWC_E_INVALID;
37090 + goto done;
37091 + }
37092 +
37093 + DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
37094 +
37095 + while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) {
37096 + DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
37097 + retry--;
37098 + dwc_msleep(5);
37099 + DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
37100 + }
37101 +
37102 + dwc_otg_hcd_qh_remove(hcd, qh);
37103 +
37104 + DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
37105 + /*
37106 + * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove
37107 + * and qh_free to prevent stack dump on DWC_DMA_FREE() with
37108 + * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free()
37109 + * and dwc_otg_hcd_frame_list_alloc().
37110 + */
37111 + dwc_otg_hcd_qh_free(hcd, qh);
37112 +
37113 +done:
37114 + return retval;
37115 +}
37116 +
37117 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
37118 +int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle)
37119 +{
37120 + int retval = 0;
37121 + dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
37122 + if (!qh)
37123 + return -DWC_E_INVALID;
37124 +
37125 + qh->data_toggle = DWC_OTG_HC_PID_DATA0;
37126 + return retval;
37127 +}
37128 +#endif
37129 +
37130 +/**
37131 + * HCD Callback structure for handling mode switching.
37132 + */
37133 +static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
37134 + .start = dwc_otg_hcd_start_cb,
37135 + .stop = dwc_otg_hcd_stop_cb,
37136 + .disconnect = dwc_otg_hcd_disconnect_cb,
37137 + .session_start = dwc_otg_hcd_session_start_cb,
37138 + .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
37139 +#ifdef CONFIG_USB_DWC_OTG_LPM
37140 + .sleep = dwc_otg_hcd_sleep_cb,
37141 +#endif
37142 + .p = 0,
37143 +};
37144 +
37145 +/**
37146 + * Reset tasklet function
37147 + */
37148 +static void reset_tasklet_func(void *data)
37149 +{
37150 + dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data;
37151 + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
37152 + hprt0_data_t hprt0;
37153 +
37154 + DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
37155 +
37156 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
37157 + hprt0.b.prtrst = 1;
37158 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
37159 + dwc_mdelay(60);
37160 +
37161 + hprt0.b.prtrst = 0;
37162 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
37163 + dwc_otg_hcd->flags.b.port_reset_change = 1;
37164 +}
37165 +
37166 +static void completion_tasklet_func(void *ptr)
37167 +{
37168 + dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) ptr;
37169 + struct urb *urb;
37170 + urb_tq_entry_t *item;
37171 + dwc_irqflags_t flags;
37172 +
37173 + /* This could just be spin_lock_irq */
37174 + DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
37175 + while (!DWC_TAILQ_EMPTY(&hcd->completed_urb_list)) {
37176 + item = DWC_TAILQ_FIRST(&hcd->completed_urb_list);
37177 + urb = item->urb;
37178 + DWC_TAILQ_REMOVE(&hcd->completed_urb_list, item,
37179 + urb_tq_entries);
37180 + DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
37181 + DWC_FREE(item);
37182 +
37183 + usb_hcd_giveback_urb(hcd->priv, urb, urb->status);
37184 +
37185 +
37186 + DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
37187 + }
37188 + DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
37189 + return;
37190 +}
37191 +
37192 +static void qh_list_free(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
37193 +{
37194 + dwc_list_link_t *item;
37195 + dwc_otg_qh_t *qh;
37196 + dwc_irqflags_t flags;
37197 +
37198 + if (!qh_list->next) {
37199 + /* The list hasn't been initialized yet. */
37200 + return;
37201 + }
37202 + /*
37203 + * Hold spinlock here. Not needed in that case if bellow
37204 + * function is being called from ISR
37205 + */
37206 + DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
37207 + /* Ensure there are no QTDs or URBs left. */
37208 + kill_urbs_in_qh_list(hcd, qh_list);
37209 + DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
37210 +
37211 + DWC_LIST_FOREACH(item, qh_list) {
37212 + qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
37213 + dwc_otg_hcd_qh_remove_and_free(hcd, qh);
37214 + }
37215 +}
37216 +
37217 +/**
37218 + * Exit from Hibernation if Host did not detect SRP from connected SRP capable
37219 + * Device during SRP time by host power up.
37220 + */
37221 +void dwc_otg_hcd_power_up(void *ptr)
37222 +{
37223 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
37224 + dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
37225 +
37226 + DWC_PRINTF("%s called\n", __FUNCTION__);
37227 +
37228 + if (!core_if->hibernation_suspend) {
37229 + DWC_PRINTF("Already exited from Hibernation\n");
37230 + return;
37231 + }
37232 +
37233 + /* Switch on the voltage to the core */
37234 + gpwrdn.b.pwrdnswtch = 1;
37235 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
37236 + dwc_udelay(10);
37237 +
37238 + /* Reset the core */
37239 + gpwrdn.d32 = 0;
37240 + gpwrdn.b.pwrdnrstn = 1;
37241 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
37242 + dwc_udelay(10);
37243 +
37244 + /* Disable power clamps */
37245 + gpwrdn.d32 = 0;
37246 + gpwrdn.b.pwrdnclmp = 1;
37247 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
37248 +
37249 + /* Remove reset the core signal */
37250 + gpwrdn.d32 = 0;
37251 + gpwrdn.b.pwrdnrstn = 1;
37252 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
37253 + dwc_udelay(10);
37254 +
37255 + /* Disable PMU interrupt */
37256 + gpwrdn.d32 = 0;
37257 + gpwrdn.b.pmuintsel = 1;
37258 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
37259 +
37260 + core_if->hibernation_suspend = 0;
37261 +
37262 + /* Disable PMU */
37263 + gpwrdn.d32 = 0;
37264 + gpwrdn.b.pmuactv = 1;
37265 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
37266 + dwc_udelay(10);
37267 +
37268 + /* Enable VBUS */
37269 + gpwrdn.d32 = 0;
37270 + gpwrdn.b.dis_vbus = 1;
37271 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
37272 +
37273 + core_if->op_state = A_HOST;
37274 + dwc_otg_core_init(core_if);
37275 + dwc_otg_enable_global_interrupts(core_if);
37276 + cil_hcd_start(core_if);
37277 +}
37278 +
37279 +void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num)
37280 +{
37281 + struct fiq_channel_state *st = &hcd->fiq_state->channel[num];
37282 + struct fiq_dma_blob *blob = hcd->fiq_dmab;
37283 + int i;
37284 +
37285 + st->fsm = FIQ_PASSTHROUGH;
37286 + st->hcchar_copy.d32 = 0;
37287 + st->hcsplt_copy.d32 = 0;
37288 + st->hcint_copy.d32 = 0;
37289 + st->hcintmsk_copy.d32 = 0;
37290 + st->hctsiz_copy.d32 = 0;
37291 + st->hcdma_copy.d32 = 0;
37292 + st->nr_errors = 0;
37293 + st->hub_addr = 0;
37294 + st->port_addr = 0;
37295 + st->expected_uframe = 0;
37296 + st->nrpackets = 0;
37297 + st->dma_info.index = 0;
37298 + for (i = 0; i < 6; i++)
37299 + st->dma_info.slot_len[i] = 255;
37300 + st->hs_isoc_info.index = 0;
37301 + st->hs_isoc_info.iso_desc = NULL;
37302 + st->hs_isoc_info.nrframes = 0;
37303 +
37304 + DWC_MEMSET(&blob->channel[num].index[0], 0x6b, 1128);
37305 +}
37306 +
37307 +/**
37308 + * Frees secondary storage associated with the dwc_otg_hcd structure contained
37309 + * in the struct usb_hcd field.
37310 + */
37311 +static void dwc_otg_hcd_free(dwc_otg_hcd_t * dwc_otg_hcd)
37312 +{
37313 + int i;
37314 +
37315 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
37316 +
37317 + del_timers(dwc_otg_hcd);
37318 +
37319 + /* Free memory for QH/QTD lists */
37320 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
37321 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
37322 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
37323 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
37324 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
37325 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
37326 +
37327 + /* Free memory for the host channels. */
37328 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
37329 + dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
37330 +
37331 +#ifdef DEBUG
37332 + if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) {
37333 + DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]);
37334 + }
37335 +#endif
37336 + if (hc != NULL) {
37337 + DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n",
37338 + i, hc);
37339 + DWC_FREE(hc);
37340 + }
37341 + }
37342 +
37343 + if (dwc_otg_hcd->core_if->dma_enable) {
37344 + if (dwc_otg_hcd->status_buf_dma) {
37345 + DWC_DMA_FREE(DWC_OTG_HCD_STATUS_BUF_SIZE,
37346 + dwc_otg_hcd->status_buf,
37347 + dwc_otg_hcd->status_buf_dma);
37348 + }
37349 + } else if (dwc_otg_hcd->status_buf != NULL) {
37350 + DWC_FREE(dwc_otg_hcd->status_buf);
37351 + }
37352 + DWC_SPINLOCK_FREE(dwc_otg_hcd->channel_lock);
37353 + DWC_SPINLOCK_FREE(dwc_otg_hcd->lock);
37354 + /* Set core_if's lock pointer to NULL */
37355 + dwc_otg_hcd->core_if->lock = NULL;
37356 +
37357 + DWC_TIMER_FREE(dwc_otg_hcd->conn_timer);
37358 + DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);
37359 + DWC_TASK_FREE(dwc_otg_hcd->completion_tasklet);
37360 + DWC_FREE(dwc_otg_hcd->fiq_state);
37361 +
37362 +#ifdef DWC_DEV_SRPCAP
37363 + if (dwc_otg_hcd->core_if->power_down == 2 &&
37364 + dwc_otg_hcd->core_if->pwron_timer) {
37365 + DWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer);
37366 + }
37367 +#endif
37368 + DWC_FREE(dwc_otg_hcd);
37369 +}
37370 +
37371 +int init_hcd_usecs(dwc_otg_hcd_t *_hcd);
37372 +
37373 +int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if)
37374 +{
37375 + int retval = 0;
37376 + int num_channels;
37377 + int i;
37378 + dwc_hc_t *channel;
37379 +
37380 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))
37381 + DWC_SPINLOCK_ALLOC_LINUX_DEBUG(hcd->lock);
37382 + DWC_SPINLOCK_ALLOC_LINUX_DEBUG(hcd->channel_lock);
37383 +#else
37384 + hcd->lock = DWC_SPINLOCK_ALLOC();
37385 + hcd->channel_lock = DWC_SPINLOCK_ALLOC();
37386 +#endif
37387 + DWC_DEBUGPL(DBG_HCDV, "init of HCD %p given core_if %p\n",
37388 + hcd, core_if);
37389 + if (!hcd->lock) {
37390 + DWC_ERROR("Could not allocate lock for pcd");
37391 + DWC_FREE(hcd);
37392 + retval = -DWC_E_NO_MEMORY;
37393 + goto out;
37394 + }
37395 + hcd->core_if = core_if;
37396 +
37397 + /* Register the HCD CIL Callbacks */
37398 + dwc_otg_cil_register_hcd_callbacks(hcd->core_if,
37399 + &hcd_cil_callbacks, hcd);
37400 +
37401 + /* Initialize the non-periodic schedule. */
37402 + DWC_LIST_INIT(&hcd->non_periodic_sched_inactive);
37403 + DWC_LIST_INIT(&hcd->non_periodic_sched_active);
37404 +
37405 + /* Initialize the periodic schedule. */
37406 + DWC_LIST_INIT(&hcd->periodic_sched_inactive);
37407 + DWC_LIST_INIT(&hcd->periodic_sched_ready);
37408 + DWC_LIST_INIT(&hcd->periodic_sched_assigned);
37409 + DWC_LIST_INIT(&hcd->periodic_sched_queued);
37410 + DWC_TAILQ_INIT(&hcd->completed_urb_list);
37411 + /*
37412 + * Create a host channel descriptor for each host channel implemented
37413 + * in the controller. Initialize the channel descriptor array.
37414 + */
37415 + DWC_CIRCLEQ_INIT(&hcd->free_hc_list);
37416 + num_channels = hcd->core_if->core_params->host_channels;
37417 + DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array));
37418 + for (i = 0; i < num_channels; i++) {
37419 + channel = DWC_ALLOC(sizeof(dwc_hc_t));
37420 + if (channel == NULL) {
37421 + retval = -DWC_E_NO_MEMORY;
37422 + DWC_ERROR("%s: host channel allocation failed\n",
37423 + __func__);
37424 + dwc_otg_hcd_free(hcd);
37425 + goto out;
37426 + }
37427 + channel->hc_num = i;
37428 + hcd->hc_ptr_array[i] = channel;
37429 +#ifdef DEBUG
37430 + hcd->core_if->hc_xfer_timer[i] =
37431 + DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout,
37432 + &hcd->core_if->hc_xfer_info[i]);
37433 +#endif
37434 + DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i,
37435 + channel);
37436 + }
37437 +
37438 + if (fiq_enable) {
37439 + hcd->fiq_state = DWC_ALLOC(sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels));
37440 + if (!hcd->fiq_state) {
37441 + retval = -DWC_E_NO_MEMORY;
37442 + DWC_ERROR("%s: cannot allocate fiq_state structure\n", __func__);
37443 + dwc_otg_hcd_free(hcd);
37444 + goto out;
37445 + }
37446 + DWC_MEMSET(hcd->fiq_state, 0, (sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels)));
37447 +
37448 + for (i = 0; i < num_channels; i++) {
37449 + hcd->fiq_state->channel[i].fsm = FIQ_PASSTHROUGH;
37450 + }
37451 + hcd->fiq_state->dummy_send = DWC_ALLOC_ATOMIC(16);
37452 +
37453 + hcd->fiq_stack = DWC_ALLOC(sizeof(struct fiq_stack));
37454 + if (!hcd->fiq_stack) {
37455 + retval = -DWC_E_NO_MEMORY;
37456 + DWC_ERROR("%s: cannot allocate fiq_stack structure\n", __func__);
37457 + dwc_otg_hcd_free(hcd);
37458 + goto out;
37459 + }
37460 + hcd->fiq_stack->magic1 = 0xDEADBEEF;
37461 + hcd->fiq_stack->magic2 = 0xD00DFEED;
37462 + hcd->fiq_state->gintmsk_saved.d32 = ~0;
37463 + hcd->fiq_state->haintmsk_saved.b2.chint = ~0;
37464 +
37465 + /* This bit is terrible and uses no API, but necessary. The FIQ has no concept of DMA pools
37466 + * (and if it did, would be a lot slower). This allocates a chunk of memory (~9kiB for 8 host channels)
37467 + * for use as transaction bounce buffers in a 2-D array. Our access into this chunk is done by some
37468 + * moderately readable array casts.
37469 + */
37470 + hcd->fiq_dmab = DWC_DMA_ALLOC((sizeof(struct fiq_dma_channel) * num_channels), &hcd->fiq_state->dma_base);
37471 + DWC_WARN("FIQ DMA bounce buffers: virt = 0x%08x dma = 0x%08x len=%d",
37472 + (unsigned int)hcd->fiq_dmab, (unsigned int)hcd->fiq_state->dma_base,
37473 + sizeof(struct fiq_dma_channel) * num_channels);
37474 +
37475 + DWC_MEMSET(hcd->fiq_dmab, 0x6b, 9024);
37476 +
37477 + /* pointer for debug in fiq_print */
37478 + hcd->fiq_state->fiq_dmab = hcd->fiq_dmab;
37479 + if (fiq_fsm_enable) {
37480 + int i;
37481 + for (i=0; i < hcd->core_if->core_params->host_channels; i++) {
37482 + dwc_otg_cleanup_fiq_channel(hcd, i);
37483 + }
37484 + DWC_PRINTF("FIQ FSM acceleration enabled for :\n%s%s%s%s",
37485 + (fiq_fsm_mask & 0x1) ? "Non-periodic Split Transactions\n" : "",
37486 + (fiq_fsm_mask & 0x2) ? "Periodic Split Transactions\n" : "",
37487 + (fiq_fsm_mask & 0x4) ? "High-Speed Isochronous Endpoints\n" : "",
37488 + (fiq_fsm_mask & 0x8) ? "Interrupt/Control Split Transaction hack enabled\n" : "");
37489 + }
37490 + }
37491 +
37492 + /* Initialize the Connection timeout timer. */
37493 + hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer",
37494 + dwc_otg_hcd_connect_timeout, 0);
37495 +
37496 + printk(KERN_DEBUG "dwc_otg: Microframe scheduler %s\n", microframe_schedule ? "enabled":"disabled");
37497 + if (microframe_schedule)
37498 + init_hcd_usecs(hcd);
37499 +
37500 + /* Initialize reset tasklet. */
37501 + hcd->reset_tasklet = DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd);
37502 +
37503 + hcd->completion_tasklet = DWC_TASK_ALLOC("completion_tasklet",
37504 + completion_tasklet_func, hcd);
37505 +#ifdef DWC_DEV_SRPCAP
37506 + if (hcd->core_if->power_down == 2) {
37507 + /* Initialize Power on timer for Host power up in case hibernation */
37508 + hcd->core_if->pwron_timer = DWC_TIMER_ALLOC("PWRON TIMER",
37509 + dwc_otg_hcd_power_up, core_if);
37510 + }
37511 +#endif
37512 +
37513 + /*
37514 + * Allocate space for storing data on status transactions. Normally no
37515 + * data is sent, but this space acts as a bit bucket. This must be
37516 + * done after usb_add_hcd since that function allocates the DMA buffer
37517 + * pool.
37518 + */
37519 + if (hcd->core_if->dma_enable) {
37520 + hcd->status_buf =
37521 + DWC_DMA_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE,
37522 + &hcd->status_buf_dma);
37523 + } else {
37524 + hcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE);
37525 + }
37526 + if (!hcd->status_buf) {
37527 + retval = -DWC_E_NO_MEMORY;
37528 + DWC_ERROR("%s: status_buf allocation failed\n", __func__);
37529 + dwc_otg_hcd_free(hcd);
37530 + goto out;
37531 + }
37532 +
37533 + hcd->otg_port = 1;
37534 + hcd->frame_list = NULL;
37535 + hcd->frame_list_dma = 0;
37536 + hcd->periodic_qh_count = 0;
37537 +
37538 + DWC_MEMSET(hcd->hub_port, 0, sizeof(hcd->hub_port));
37539 +#ifdef FIQ_DEBUG
37540 + DWC_MEMSET(hcd->hub_port_alloc, -1, sizeof(hcd->hub_port_alloc));
37541 +#endif
37542 +
37543 +out:
37544 + return retval;
37545 +}
37546 +
37547 +void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd)
37548 +{
37549 + /* Turn off all host-specific interrupts. */
37550 + dwc_otg_disable_host_interrupts(hcd->core_if);
37551 +
37552 + dwc_otg_hcd_free(hcd);
37553 +}
37554 +
37555 +/**
37556 + * Initializes dynamic portions of the DWC_otg HCD state.
37557 + */
37558 +static void dwc_otg_hcd_reinit(dwc_otg_hcd_t * hcd)
37559 +{
37560 + int num_channels;
37561 + int i;
37562 + dwc_hc_t *channel;
37563 + dwc_hc_t *channel_tmp;
37564 +
37565 + hcd->flags.d32 = 0;
37566 +
37567 + hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
37568 + if (!microframe_schedule) {
37569 + hcd->non_periodic_channels = 0;
37570 + hcd->periodic_channels = 0;
37571 + } else {
37572 + hcd->available_host_channels = hcd->core_if->core_params->host_channels;
37573 + }
37574 + /*
37575 + * Put all channels in the free channel list and clean up channel
37576 + * states.
37577 + */
37578 + DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,
37579 + &hcd->free_hc_list, hc_list_entry) {
37580 + DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry);
37581 + }
37582 +
37583 + num_channels = hcd->core_if->core_params->host_channels;
37584 + for (i = 0; i < num_channels; i++) {
37585 + channel = hcd->hc_ptr_array[i];
37586 + DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel,
37587 + hc_list_entry);
37588 + dwc_otg_hc_cleanup(hcd->core_if, channel);
37589 + }
37590 +
37591 + /* Initialize the DWC core for host mode operation. */
37592 + dwc_otg_core_host_init(hcd->core_if);
37593 +
37594 + /* Set core_if's lock pointer to the hcd->lock */
37595 + hcd->core_if->lock = hcd->lock;
37596 +}
37597 +
37598 +/**
37599 + * Assigns transactions from a QTD to a free host channel and initializes the
37600 + * host channel to perform the transactions. The host channel is removed from
37601 + * the free list.
37602 + *
37603 + * @param hcd The HCD state structure.
37604 + * @param qh Transactions from the first QTD for this QH are selected and
37605 + * assigned to a free host channel.
37606 + */
37607 +static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
37608 +{
37609 + dwc_hc_t *hc;
37610 + dwc_otg_qtd_t *qtd;
37611 + dwc_otg_hcd_urb_t *urb;
37612 + void* ptr = NULL;
37613 + uint32_t intr_enable;
37614 + unsigned long flags;
37615 + gintmsk_data_t gintmsk = { .d32 = 0, };
37616 +
37617 + qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
37618 +
37619 + urb = qtd->urb;
37620 +
37621 + DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p) - urb %x, actual_length %d\n", __func__, hcd, qh, (unsigned int)urb, urb->actual_length);
37622 +
37623 + if (((urb->actual_length < 0) || (urb->actual_length > urb->length)) && !dwc_otg_hcd_is_pipe_in(&urb->pipe_info))
37624 + urb->actual_length = urb->length;
37625 +
37626 +
37627 + hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
37628 +
37629 + /* Remove the host channel from the free list. */
37630 + DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
37631 +
37632 + qh->channel = hc;
37633 +
37634 + qtd->in_process = 1;
37635 +
37636 + /*
37637 + * Use usb_pipedevice to determine device address. This address is
37638 + * 0 before the SET_ADDRESS command and the correct address afterward.
37639 + */
37640 + hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info);
37641 + hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info);
37642 + hc->speed = qh->dev_speed;
37643 + hc->max_packet = dwc_max_packet(qh->maxp);
37644 +
37645 + hc->xfer_started = 0;
37646 + hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
37647 + hc->error_state = (qtd->error_count > 0);
37648 + hc->halt_on_queue = 0;
37649 + hc->halt_pending = 0;
37650 + hc->requests = 0;
37651 +
37652 + /*
37653 + * The following values may be modified in the transfer type section
37654 + * below. The xfer_len value may be reduced when the transfer is
37655 + * started to accommodate the max widths of the XferSize and PktCnt
37656 + * fields in the HCTSIZn register.
37657 + */
37658 +
37659 + hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);
37660 + if (hc->ep_is_in) {
37661 + hc->do_ping = 0;
37662 + } else {
37663 + hc->do_ping = qh->ping_state;
37664 + }
37665 +
37666 + hc->data_pid_start = qh->data_toggle;
37667 + hc->multi_count = 1;
37668 +
37669 + if (hcd->core_if->dma_enable) {
37670 + hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
37671 +
37672 + /* For non-dword aligned case */
37673 + if (((unsigned long)hc->xfer_buff & 0x3)
37674 + && !hcd->core_if->dma_desc_enable) {
37675 + ptr = (uint8_t *) urb->buf + urb->actual_length;
37676 + }
37677 + } else {
37678 + hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length;
37679 + }
37680 + hc->xfer_len = urb->length - urb->actual_length;
37681 + hc->xfer_count = 0;
37682 +
37683 + /*
37684 + * Set the split attributes
37685 + */
37686 + hc->do_split = 0;
37687 + if (qh->do_split) {
37688 + uint32_t hub_addr, port_addr;
37689 + hc->do_split = 1;
37690 + hc->xact_pos = qtd->isoc_split_pos;
37691 + /* We don't need to do complete splits anymore */
37692 +// if(fiq_fsm_enable)
37693 + if (0)
37694 + hc->complete_split = qtd->complete_split = 0;
37695 + else
37696 + hc->complete_split = qtd->complete_split;
37697 +
37698 + hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr);
37699 + hc->hub_addr = (uint8_t) hub_addr;
37700 + hc->port_addr = (uint8_t) port_addr;
37701 + }
37702 +
37703 + switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
37704 + case UE_CONTROL:
37705 + hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
37706 + switch (qtd->control_phase) {
37707 + case DWC_OTG_CONTROL_SETUP:
37708 + DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n");
37709 + hc->do_ping = 0;
37710 + hc->ep_is_in = 0;
37711 + hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
37712 + if (hcd->core_if->dma_enable) {
37713 + hc->xfer_buff = (uint8_t *) urb->setup_dma;
37714 + } else {
37715 + hc->xfer_buff = (uint8_t *) urb->setup_packet;
37716 + }
37717 + hc->xfer_len = 8;
37718 + ptr = NULL;
37719 + break;
37720 + case DWC_OTG_CONTROL_DATA:
37721 + DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n");
37722 + hc->data_pid_start = qtd->data_toggle;
37723 + break;
37724 + case DWC_OTG_CONTROL_STATUS:
37725 + /*
37726 + * Direction is opposite of data direction or IN if no
37727 + * data.
37728 + */
37729 + DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n");
37730 + if (urb->length == 0) {
37731 + hc->ep_is_in = 1;
37732 + } else {
37733 + hc->ep_is_in =
37734 + dwc_otg_hcd_is_pipe_out(&urb->pipe_info);
37735 + }
37736 + if (hc->ep_is_in) {
37737 + hc->do_ping = 0;
37738 + }
37739 +
37740 + hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
37741 +
37742 + hc->xfer_len = 0;
37743 + if (hcd->core_if->dma_enable) {
37744 + hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
37745 + } else {
37746 + hc->xfer_buff = (uint8_t *) hcd->status_buf;
37747 + }
37748 + ptr = NULL;
37749 + break;
37750 + }
37751 + break;
37752 + case UE_BULK:
37753 + hc->ep_type = DWC_OTG_EP_TYPE_BULK;
37754 + break;
37755 + case UE_INTERRUPT:
37756 + hc->ep_type = DWC_OTG_EP_TYPE_INTR;
37757 + break;
37758 + case UE_ISOCHRONOUS:
37759 + {
37760 + struct dwc_otg_hcd_iso_packet_desc *frame_desc;
37761 +
37762 + hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
37763 +
37764 + if (hcd->core_if->dma_desc_enable)
37765 + break;
37766 +
37767 + frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
37768 +
37769 + frame_desc->status = 0;
37770 +
37771 + if (hcd->core_if->dma_enable) {
37772 + hc->xfer_buff = (uint8_t *) urb->dma;
37773 + } else {
37774 + hc->xfer_buff = (uint8_t *) urb->buf;
37775 + }
37776 + hc->xfer_buff +=
37777 + frame_desc->offset + qtd->isoc_split_offset;
37778 + hc->xfer_len =
37779 + frame_desc->length - qtd->isoc_split_offset;
37780 +
37781 + /* For non-dword aligned buffers */
37782 + if (((unsigned long)hc->xfer_buff & 0x3)
37783 + && hcd->core_if->dma_enable) {
37784 + ptr =
37785 + (uint8_t *) urb->buf + frame_desc->offset +
37786 + qtd->isoc_split_offset;
37787 + } else
37788 + ptr = NULL;
37789 +
37790 + if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
37791 + if (hc->xfer_len <= 188) {
37792 + hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
37793 + } else {
37794 + hc->xact_pos =
37795 + DWC_HCSPLIT_XACTPOS_BEGIN;
37796 + }
37797 + }
37798 + }
37799 + break;
37800 + }
37801 + /* non DWORD-aligned buffer case */
37802 + if (ptr) {
37803 + uint32_t buf_size;
37804 + if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
37805 + buf_size = hcd->core_if->core_params->max_transfer_size;
37806 + } else {
37807 + buf_size = 4096;
37808 + }
37809 + if (!qh->dw_align_buf) {
37810 + qh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(buf_size,
37811 + &qh->dw_align_buf_dma);
37812 + if (!qh->dw_align_buf) {
37813 + DWC_ERROR
37814 + ("%s: Failed to allocate memory to handle "
37815 + "non-dword aligned buffer case\n",
37816 + __func__);
37817 + return;
37818 + }
37819 + }
37820 + if (!hc->ep_is_in) {
37821 + dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len);
37822 + }
37823 + hc->align_buff = qh->dw_align_buf_dma;
37824 + } else {
37825 + hc->align_buff = 0;
37826 + }
37827 +
37828 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
37829 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
37830 + /*
37831 + * This value may be modified when the transfer is started to
37832 + * reflect the actual transfer length.
37833 + */
37834 + hc->multi_count = dwc_hb_mult(qh->maxp);
37835 + }
37836 +
37837 + if (hcd->core_if->dma_desc_enable)
37838 + hc->desc_list_addr = qh->desc_list_dma;
37839 +
37840 + dwc_otg_hc_init(hcd->core_if, hc);
37841 +
37842 + local_irq_save(flags);
37843 +
37844 + if (fiq_enable) {
37845 + local_fiq_disable();
37846 + fiq_fsm_spin_lock(&hcd->fiq_state->lock);
37847 + }
37848 +
37849 + /* Enable the top level host channel interrupt. */
37850 + intr_enable = (1 << hc->hc_num);
37851 + DWC_MODIFY_REG32(&hcd->core_if->host_if->host_global_regs->haintmsk, 0, intr_enable);
37852 +
37853 + /* Make sure host channel interrupts are enabled. */
37854 + gintmsk.b.hcintr = 1;
37855 + DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
37856 +
37857 + if (fiq_enable) {
37858 + fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
37859 + local_fiq_enable();
37860 + }
37861 +
37862 + local_irq_restore(flags);
37863 + hc->qh = qh;
37864 +}
37865 +
37866 +
37867 +/**
37868 + * fiq_fsm_transaction_suitable() - Test a QH for compatibility with the FIQ
37869 + * @qh: pointer to the endpoint's queue head
37870 + *
37871 + * Transaction start/end control flow is grafted onto the existing dwc_otg
37872 + * mechanisms, to avoid spaghettifying the functions more than they already are.
37873 + * This function's eligibility check is altered by debug parameter.
37874 + *
37875 + * Returns: 0 for unsuitable, 1 implies the FIQ can be enabled for this transaction.
37876 + */
37877 +
37878 +int fiq_fsm_transaction_suitable(dwc_otg_qh_t *qh)
37879 +{
37880 + if (qh->do_split) {
37881 + switch (qh->ep_type) {
37882 + case UE_CONTROL:
37883 + case UE_BULK:
37884 + if (fiq_fsm_mask & (1 << 0))
37885 + return 1;
37886 + break;
37887 + case UE_INTERRUPT:
37888 + case UE_ISOCHRONOUS:
37889 + if (fiq_fsm_mask & (1 << 1))
37890 + return 1;
37891 + break;
37892 + default:
37893 + break;
37894 + }
37895 + } else if (qh->ep_type == UE_ISOCHRONOUS) {
37896 + if (fiq_fsm_mask & (1 << 2)) {
37897 + /* HS ISOCH support. We test for compatibility:
37898 + * - DWORD aligned buffers
37899 + * - Must be at least 2 transfers (otherwise pointless to use the FIQ)
37900 + * If yes, then the fsm enqueue function will handle the state machine setup.
37901 + */
37902 + dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
37903 + dwc_otg_hcd_urb_t *urb = qtd->urb;
37904 + struct dwc_otg_hcd_iso_packet_desc (*iso_descs)[0] = &urb->iso_descs;
37905 + int nr_iso_frames = urb->packet_count;
37906 + int i;
37907 + uint32_t ptr;
37908 +
37909 + if (nr_iso_frames < 2)
37910 + return 0;
37911 + for (i = 0; i < nr_iso_frames; i++) {
37912 + ptr = urb->dma + iso_descs[i]->offset;
37913 + if (ptr & 0x3) {
37914 + printk_ratelimited("%s: Non-Dword aligned isochronous frame offset."
37915 + " Cannot queue FIQ-accelerated transfer to device %d endpoint %d\n",
37916 + __FUNCTION__, qh->channel->dev_addr, qh->channel->ep_num);
37917 + return 0;
37918 + }
37919 + }
37920 + return 1;
37921 + }
37922 + }
37923 + return 0;
37924 +}
37925 +
37926 +/**
37927 + * fiq_fsm_setup_periodic_dma() - Set up DMA bounce buffers
37928 + * @hcd: Pointer to the dwc_otg_hcd struct
37929 + * @qh: Pointer to the endpoint's queue head
37930 + *
37931 + * Periodic split transactions are transmitted modulo 188 bytes.
37932 + * This necessitates slicing data up into buckets for isochronous out
37933 + * and fixing up the DMA address for all IN transfers.
37934 + *
37935 + * Returns 1 if the DMA bounce buffers have been used, 0 if the default
37936 + * HC buffer has been used.
37937 + */
37938 +int fiq_fsm_setup_periodic_dma(dwc_otg_hcd_t *hcd, struct fiq_channel_state *st, dwc_otg_qh_t *qh)
37939 + {
37940 + int frame_length, i = 0;
37941 + uint8_t *ptr = NULL;
37942 + dwc_hc_t *hc = qh->channel;
37943 + struct fiq_dma_blob *blob;
37944 + struct dwc_otg_hcd_iso_packet_desc *frame_desc;
37945 +
37946 + for (i = 0; i < 6; i++) {
37947 + st->dma_info.slot_len[i] = 255;
37948 + }
37949 + st->dma_info.index = 0;
37950 + i = 0;
37951 + if (hc->ep_is_in) {
37952 + /*
37953 + * Set dma_regs to bounce buffer. FIQ will update the
37954 + * state depending on transaction progress.
37955 + */
37956 + blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;
37957 + st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0];
37958 + /* Calculate the max number of CSPLITS such that the FIQ can time out
37959 + * a transaction if it fails.
37960 + */
37961 + frame_length = st->hcchar_copy.b.mps;
37962 + do {
37963 + i++;
37964 + frame_length -= 188;
37965 + } while (frame_length >= 0);
37966 + st->nrpackets = i;
37967 + return 1;
37968 + } else {
37969 + if (qh->ep_type == UE_ISOCHRONOUS) {
37970 +
37971 + dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
37972 +
37973 + frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
37974 + frame_length = frame_desc->length;
37975 +
37976 + /* Virtual address for bounce buffers */
37977 + blob = hcd->fiq_dmab;
37978 +
37979 + ptr = qtd->urb->buf + frame_desc->offset;
37980 + if (frame_length == 0) {
37981 + /*
37982 + * for isochronous transactions, we must still transmit a packet
37983 + * even if the length is zero.
37984 + */
37985 + st->dma_info.slot_len[0] = 0;
37986 + st->nrpackets = 1;
37987 + } else {
37988 + do {
37989 + if (frame_length <= 188) {
37990 + dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, frame_length);
37991 + st->dma_info.slot_len[i] = frame_length;
37992 + ptr += frame_length;
37993 + } else {
37994 + dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, 188);
37995 + st->dma_info.slot_len[i] = 188;
37996 + ptr += 188;
37997 + }
37998 + i++;
37999 + frame_length -= 188;
38000 + } while (frame_length > 0);
38001 + st->nrpackets = i;
38002 + }
38003 + ptr = qtd->urb->buf + frame_desc->offset;
38004 + /* Point the HC at the DMA address of the bounce buffers */
38005 + blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;
38006 + st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0];
38007 +
38008 + /* fixup xfersize to the actual packet size */
38009 + st->hctsiz_copy.b.pid = 0;
38010 + st->hctsiz_copy.b.xfersize = st->dma_info.slot_len[0];
38011 + return 1;
38012 + } else {
38013 + /* For interrupt, single OUT packet required, goes in the SSPLIT from hc_buff. */
38014 + return 0;
38015 + }
38016 + }
38017 +}
38018 +
38019 +/*
38020 + * Pushing a periodic request into the queue near the EOF1 point
38021 + * in a microframe causes erroneous behaviour (frmovrun) interrupt.
38022 + * Usually, the request goes out on the bus causing a transfer but
38023 + * the core does not transfer the data to memory.
38024 + * This guard interval (in number of 60MHz clocks) is required which
38025 + * must cater for CPU latency between reading the value and enabling
38026 + * the channel.
38027 + */
38028 +#define PERIODIC_FRREM_BACKOFF 1000
38029 +
38030 +int fiq_fsm_queue_isoc_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
38031 +{
38032 + dwc_hc_t *hc = qh->channel;
38033 + dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
38034 + dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
38035 + int frame;
38036 + struct fiq_channel_state *st = &hcd->fiq_state->channel[hc->hc_num];
38037 + int xfer_len, nrpackets;
38038 + hcdma_data_t hcdma;
38039 + hfnum_data_t hfnum;
38040 +
38041 + if (st->fsm != FIQ_PASSTHROUGH)
38042 + return 0;
38043 +
38044 + st->nr_errors = 0;
38045 +
38046 + st->hcchar_copy.d32 = 0;
38047 + st->hcchar_copy.b.mps = hc->max_packet;
38048 + st->hcchar_copy.b.epdir = hc->ep_is_in;
38049 + st->hcchar_copy.b.devaddr = hc->dev_addr;
38050 + st->hcchar_copy.b.epnum = hc->ep_num;
38051 + st->hcchar_copy.b.eptype = hc->ep_type;
38052 +
38053 + st->hcintmsk_copy.b.chhltd = 1;
38054 +
38055 + frame = dwc_otg_hcd_get_frame_number(hcd);
38056 + st->hcchar_copy.b.oddfrm = (frame & 0x1) ? 0 : 1;
38057 +
38058 + st->hcchar_copy.b.lspddev = 0;
38059 + /* Enable the channel later as a final register write. */
38060 +
38061 + st->hcsplt_copy.d32 = 0;
38062 +
38063 + st->hs_isoc_info.iso_desc = (struct dwc_otg_hcd_iso_packet_desc *) &qtd->urb->iso_descs;
38064 + st->hs_isoc_info.nrframes = qtd->urb->packet_count;
38065 + /* grab the next DMA address offset from the array */
38066 + st->hcdma_copy.d32 = qtd->urb->dma;
38067 + hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[0].offset;
38068 +
38069 + /* We need to set multi_count. This is a bit tricky - has to be set per-transaction as
38070 + * the core needs to be told to send the correct number. Caution: for IN transfers,
38071 + * this is always set to the maximum size of the endpoint. */
38072 + xfer_len = st->hs_isoc_info.iso_desc[0].length;
38073 + nrpackets = (xfer_len + st->hcchar_copy.b.mps - 1) / st->hcchar_copy.b.mps;
38074 + if (nrpackets == 0)
38075 + nrpackets = 1;
38076 + st->hcchar_copy.b.multicnt = nrpackets;
38077 + st->hctsiz_copy.b.pktcnt = nrpackets;
38078 +
38079 + /* Initial PID also needs to be set */
38080 + if (st->hcchar_copy.b.epdir == 0) {
38081 + st->hctsiz_copy.b.xfersize = xfer_len;
38082 + switch (st->hcchar_copy.b.multicnt) {
38083 + case 1:
38084 + st->hctsiz_copy.b.pid = DWC_PID_DATA0;
38085 + break;
38086 + case 2:
38087 + case 3:
38088 + st->hctsiz_copy.b.pid = DWC_PID_MDATA;
38089 + break;
38090 + }
38091 +
38092 + } else {
38093 + st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps;
38094 + switch (st->hcchar_copy.b.multicnt) {
38095 + case 1:
38096 + st->hctsiz_copy.b.pid = DWC_PID_DATA0;
38097 + break;
38098 + case 2:
38099 + st->hctsiz_copy.b.pid = DWC_PID_DATA1;
38100 + break;
38101 + case 3:
38102 + st->hctsiz_copy.b.pid = DWC_PID_DATA2;
38103 + break;
38104 + }
38105 + }
38106 +
38107 + fiq_print(FIQDBG_INT, hcd->fiq_state, "FSMQ %01d ", hc->hc_num);
38108 + fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcchar_copy.d32);
38109 + fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hctsiz_copy.d32);
38110 + fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcdma_copy.d32);
38111 + hfnum.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
38112 + local_fiq_disable();
38113 + fiq_fsm_spin_lock(&hcd->fiq_state->lock);
38114 + DWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32);
38115 + DWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32);
38116 + DWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32);
38117 + DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
38118 + DWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32);
38119 + if (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) {
38120 + /* Prevent queueing near EOF1. Bad things happen if a periodic
38121 + * split transaction is queued very close to EOF.
38122 + */
38123 + st->fsm = FIQ_HS_ISOC_SLEEPING;
38124 + } else {
38125 + st->fsm = FIQ_HS_ISOC_TURBO;
38126 + st->hcchar_copy.b.chen = 1;
38127 + DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
38128 + }
38129 + mb();
38130 + st->hcchar_copy.b.chen = 0;
38131 + fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
38132 + local_fiq_enable();
38133 + return 0;
38134 +}
38135 +
38136 +
38137 +/**
38138 + * fiq_fsm_queue_split_transaction() - Set up a host channel and FIQ state
38139 + * @hcd: Pointer to the dwc_otg_hcd struct
38140 + * @qh: Pointer to the endpoint's queue head
38141 + *
38142 + * This overrides the dwc_otg driver's normal method of queueing a transaction.
38143 + * Called from dwc_otg_hcd_queue_transactions(), this performs specific setup
38144 + * for the nominated host channel.
38145 + *
38146 + * For periodic transfers, it also peeks at the FIQ state to see if an immediate
38147 + * start is possible. If not, then the FIQ is left to start the transfer.
38148 + */
38149 +int fiq_fsm_queue_split_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
38150 +{
38151 + int start_immediate = 1, i;
38152 + hfnum_data_t hfnum;
38153 + dwc_hc_t *hc = qh->channel;
38154 + dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
38155 + /* Program HC registers, setup FIQ_state, examine FIQ if periodic, start transfer (not if uframe 5) */
38156 + int hub_addr, port_addr, frame, uframe;
38157 + struct fiq_channel_state *st = &hcd->fiq_state->channel[hc->hc_num];
38158 +
38159 + if (st->fsm != FIQ_PASSTHROUGH)
38160 + return 0;
38161 + st->nr_errors = 0;
38162 +
38163 + st->hcchar_copy.d32 = 0;
38164 + st->hcchar_copy.b.mps = hc->max_packet;
38165 + st->hcchar_copy.b.epdir = hc->ep_is_in;
38166 + st->hcchar_copy.b.devaddr = hc->dev_addr;
38167 + st->hcchar_copy.b.epnum = hc->ep_num;
38168 + st->hcchar_copy.b.eptype = hc->ep_type;
38169 + if (hc->ep_type & 0x1) {
38170 + if (hc->ep_is_in)
38171 + st->hcchar_copy.b.multicnt = 3;
38172 + else
38173 + /* Docs say set this to 1, but driver sets to 0! */
38174 + st->hcchar_copy.b.multicnt = 0;
38175 + } else {
38176 + st->hcchar_copy.b.multicnt = 1;
38177 + st->hcchar_copy.b.oddfrm = 0;
38178 + }
38179 + st->hcchar_copy.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW) ? 1 : 0;
38180 + /* Enable the channel later as a final register write. */
38181 +
38182 + st->hcsplt_copy.d32 = 0;
38183 + if(qh->do_split) {
38184 + hcd->fops->hub_info(hcd, DWC_CIRCLEQ_FIRST(&qh->qtd_list)->urb->priv, &hub_addr, &port_addr);
38185 + st->hcsplt_copy.b.compsplt = 0;
38186 + st->hcsplt_copy.b.spltena = 1;
38187 + // XACTPOS is for isoc-out only but needs initialising anyway.
38188 + st->hcsplt_copy.b.xactpos = ISOC_XACTPOS_ALL;
38189 + if((qh->ep_type == DWC_OTG_EP_TYPE_ISOC) && (!qh->ep_is_in)) {
38190 + /* For packetsize 0 < L < 188, ISOC_XACTPOS_ALL.
38191 + * for longer than this, ISOC_XACTPOS_BEGIN and the FIQ
38192 + * will update as necessary.
38193 + */
38194 + if (hc->xfer_len > 188) {
38195 + st->hcsplt_copy.b.xactpos = ISOC_XACTPOS_BEGIN;
38196 + }
38197 + }
38198 + st->hcsplt_copy.b.hubaddr = (uint8_t) hub_addr;
38199 + st->hcsplt_copy.b.prtaddr = (uint8_t) port_addr;
38200 + st->hub_addr = hub_addr;
38201 + st->port_addr = port_addr;
38202 + }
38203 +
38204 + st->hctsiz_copy.d32 = 0;
38205 + st->hctsiz_copy.b.dopng = 0;
38206 + st->hctsiz_copy.b.pid = hc->data_pid_start;
38207 +
38208 + if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
38209 + hc->xfer_len = hc->max_packet;
38210 + } else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
38211 + hc->xfer_len = 188;
38212 + }
38213 + st->hctsiz_copy.b.xfersize = hc->xfer_len;
38214 +
38215 + st->hctsiz_copy.b.pktcnt = 1;
38216 +
38217 + if (hc->ep_type & 0x1) {
38218 + /*
38219 + * For potentially multi-packet transfers, must use the DMA bounce buffers. For IN transfers,
38220 + * the DMA address is the address of the first 188byte slot buffer in the bounce buffer array.
38221 + * For multi-packet OUT transfers, we need to copy the data into the bounce buffer array so the FIQ can punt
38222 + * the right address out as necessary. hc->xfer_buff and hc->xfer_len have already been set
38223 + * in assign_and_init_hc(), but this is for the eventual transaction completion only. The FIQ
38224 + * must not touch internal driver state.
38225 + */
38226 + if(!fiq_fsm_setup_periodic_dma(hcd, st, qh)) {
38227 + if (hc->align_buff) {
38228 + st->hcdma_copy.d32 = hc->align_buff;
38229 + } else {
38230 + st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);
38231 + }
38232 + }
38233 + } else {
38234 + if (hc->align_buff) {
38235 + st->hcdma_copy.d32 = hc->align_buff;
38236 + } else {
38237 + st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);
38238 + }
38239 + }
38240 + /* The FIQ depends upon no other interrupts being enabled except channel halt.
38241 + * Fixup channel interrupt mask. */
38242 + st->hcintmsk_copy.d32 = 0;
38243 + st->hcintmsk_copy.b.chhltd = 1;
38244 + st->hcintmsk_copy.b.ahberr = 1;
38245 +
38246 + /* Hack courtesy of FreeBSD: apparently forcing Interrupt Split transactions
38247 + * as Control puts the transfer into the non-periodic request queue and the
38248 + * non-periodic handler in the hub. Makes things lots easier.
38249 + */
38250 + if ((fiq_fsm_mask & 0x8) && hc->ep_type == UE_INTERRUPT) {
38251 + st->hcchar_copy.b.multicnt = 0;
38252 + st->hcchar_copy.b.oddfrm = 0;
38253 + st->hcchar_copy.b.eptype = UE_CONTROL;
38254 + if (hc->align_buff) {
38255 + st->hcdma_copy.d32 = hc->align_buff;
38256 + } else {
38257 + st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);
38258 + }
38259 + }
38260 + DWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32);
38261 + DWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32);
38262 + DWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32);
38263 + DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
38264 + DWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32);
38265 +
38266 + local_fiq_disable();
38267 + fiq_fsm_spin_lock(&hcd->fiq_state->lock);
38268 +
38269 + if (hc->ep_type & 0x1) {
38270 + hfnum.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
38271 + frame = (hfnum.b.frnum & ~0x7) >> 3;
38272 + uframe = hfnum.b.frnum & 0x7;
38273 + if (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) {
38274 + /* Prevent queueing near EOF1. Bad things happen if a periodic
38275 + * split transaction is queued very close to EOF.
38276 + */
38277 + start_immediate = 0;
38278 + } else if (uframe == 5) {
38279 + start_immediate = 0;
38280 + } else if (hc->ep_type == UE_ISOCHRONOUS && !hc->ep_is_in) {
38281 + start_immediate = 0;
38282 + } else if (hc->ep_is_in && fiq_fsm_too_late(hcd->fiq_state, hc->hc_num)) {
38283 + start_immediate = 0;
38284 + } else {
38285 + /* Search through all host channels to determine if a transaction
38286 + * is currently in progress */
38287 + for (i = 0; i < hcd->core_if->core_params->host_channels; i++) {
38288 + if (i == hc->hc_num || hcd->fiq_state->channel[i].fsm == FIQ_PASSTHROUGH)
38289 + continue;
38290 + switch (hcd->fiq_state->channel[i].fsm) {
38291 + /* TT is reserved for channels that are in the middle of a periodic
38292 + * split transaction.
38293 + */
38294 + case FIQ_PER_SSPLIT_STARTED:
38295 + case FIQ_PER_CSPLIT_WAIT:
38296 + case FIQ_PER_CSPLIT_NYET1:
38297 + case FIQ_PER_CSPLIT_POLL:
38298 + case FIQ_PER_ISO_OUT_ACTIVE:
38299 + case FIQ_PER_ISO_OUT_LAST:
38300 + if (hcd->fiq_state->channel[i].hub_addr == hub_addr &&
38301 + hcd->fiq_state->channel[i].port_addr == port_addr) {
38302 + start_immediate = 0;
38303 + }
38304 + break;
38305 + default:
38306 + break;
38307 + }
38308 + if (!start_immediate)
38309 + break;
38310 + }
38311 + }
38312 + }
38313 + if ((fiq_fsm_mask & 0x8) && hc->ep_type == UE_INTERRUPT)
38314 + start_immediate = 1;
38315 +
38316 + fiq_print(FIQDBG_INT, hcd->fiq_state, "FSMQ %01d %01d", hc->hc_num, start_immediate);
38317 + fiq_print(FIQDBG_INT, hcd->fiq_state, "%08d", hfnum.b.frrem);
38318 + //fiq_print(FIQDBG_INT, hcd->fiq_state, "H:%02dP:%02d", hub_addr, port_addr);
38319 + //fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hctsiz_copy.d32);
38320 + //fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcdma_copy.d32);
38321 + switch (hc->ep_type) {
38322 + case UE_CONTROL:
38323 + case UE_BULK:
38324 + st->fsm = FIQ_NP_SSPLIT_STARTED;
38325 + break;
38326 + case UE_ISOCHRONOUS:
38327 + if (hc->ep_is_in) {
38328 + if (start_immediate) {
38329 + st->fsm = FIQ_PER_SSPLIT_STARTED;
38330 + } else {
38331 + st->fsm = FIQ_PER_SSPLIT_QUEUED;
38332 + }
38333 + } else {
38334 + if (start_immediate) {
38335 + /* Single-isoc OUT packets don't require FIQ involvement */
38336 + if (st->nrpackets == 1) {
38337 + st->fsm = FIQ_PER_ISO_OUT_LAST;
38338 + } else {
38339 + st->fsm = FIQ_PER_ISO_OUT_ACTIVE;
38340 + }
38341 + } else {
38342 + st->fsm = FIQ_PER_ISO_OUT_PENDING;
38343 + }
38344 + }
38345 + break;
38346 + case UE_INTERRUPT:
38347 + if (fiq_fsm_mask & 0x8) {
38348 + st->fsm = FIQ_NP_SSPLIT_STARTED;
38349 + } else if (start_immediate) {
38350 + st->fsm = FIQ_PER_SSPLIT_STARTED;
38351 + } else {
38352 + st->fsm = FIQ_PER_SSPLIT_QUEUED;
38353 + }
38354 + default:
38355 + break;
38356 + }
38357 + if (start_immediate) {
38358 + /* Set the oddfrm bit as close as possible to actual queueing */
38359 + frame = dwc_otg_hcd_get_frame_number(hcd);
38360 + st->expected_uframe = (frame + 1) & 0x3FFF;
38361 + st->hcchar_copy.b.oddfrm = (frame & 0x1) ? 0 : 1;
38362 + st->hcchar_copy.b.chen = 1;
38363 + DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
38364 + }
38365 + mb();
38366 + fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
38367 + local_fiq_enable();
38368 + return 0;
38369 +}
38370 +
38371 +
38372 +/**
38373 + * This function selects transactions from the HCD transfer schedule and
38374 + * assigns them to available host channels. It is called from HCD interrupt
38375 + * handler functions.
38376 + *
38377 + * @param hcd The HCD state structure.
38378 + *
38379 + * @return The types of new transactions that were assigned to host channels.
38380 + */
38381 +dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd)
38382 +{
38383 + dwc_list_link_t *qh_ptr;
38384 + dwc_otg_qh_t *qh;
38385 + int num_channels;
38386 + dwc_irqflags_t flags;
38387 + dwc_spinlock_t *channel_lock = hcd->channel_lock;
38388 + dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
38389 +
38390 +#ifdef DEBUG_HOST_CHANNELS
38391 + last_sel_trans_num_per_scheduled = 0;
38392 + last_sel_trans_num_nonper_scheduled = 0;
38393 + last_sel_trans_num_avail_hc_at_start = hcd->available_host_channels;
38394 +#endif /* DEBUG_HOST_CHANNELS */
38395 +
38396 + /* Process entries in the periodic ready list. */
38397 + qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);
38398 +
38399 + while (qh_ptr != &hcd->periodic_sched_ready &&
38400 + !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
38401 +
38402 + qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
38403 +
38404 + if (microframe_schedule) {
38405 + // Make sure we leave one channel for non periodic transactions.
38406 + DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
38407 + if (hcd->available_host_channels <= 1) {
38408 + DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
38409 + break;
38410 + }
38411 + hcd->available_host_channels--;
38412 + DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
38413 +#ifdef DEBUG_HOST_CHANNELS
38414 + last_sel_trans_num_per_scheduled++;
38415 +#endif /* DEBUG_HOST_CHANNELS */
38416 + }
38417 + qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
38418 + assign_and_init_hc(hcd, qh);
38419 +
38420 + /*
38421 + * Move the QH from the periodic ready schedule to the
38422 + * periodic assigned schedule.
38423 + */
38424 + qh_ptr = DWC_LIST_NEXT(qh_ptr);
38425 + DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
38426 + DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
38427 + &qh->qh_list_entry);
38428 + DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
38429 + }
38430 +
38431 + /*
38432 + * Process entries in the inactive portion of the non-periodic
38433 + * schedule. Some free host channels may not be used if they are
38434 + * reserved for periodic transfers.
38435 + */
38436 + qh_ptr = hcd->non_periodic_sched_inactive.next;
38437 + num_channels = hcd->core_if->core_params->host_channels;
38438 + while (qh_ptr != &hcd->non_periodic_sched_inactive &&
38439 + (microframe_schedule || hcd->non_periodic_channels <
38440 + num_channels - hcd->periodic_channels) &&
38441 + !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
38442 +
38443 + qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
38444 + /*
38445 + * Check to see if this is a NAK'd retransmit, in which case ignore for retransmission
38446 + * we hold off on bulk retransmissions to reduce NAK interrupt overhead for full-speed
38447 + * cheeky devices that just hold off using NAKs
38448 + */
38449 + if (fiq_enable && nak_holdoff && qh->do_split) {
38450 + if (qh->nak_frame != 0xffff) {
38451 + uint16_t next_frame = dwc_frame_num_inc(qh->nak_frame, (qh->ep_type == UE_BULK) ? nak_holdoff : 8);
38452 + uint16_t frame = dwc_otg_hcd_get_frame_number(hcd);
38453 + if (dwc_frame_num_le(frame, next_frame)) {
38454 + if(dwc_frame_num_le(next_frame, hcd->fiq_state->next_sched_frame)) {
38455 + hcd->fiq_state->next_sched_frame = next_frame;
38456 + }
38457 + qh_ptr = DWC_LIST_NEXT(qh_ptr);
38458 + continue;
38459 + } else {
38460 + qh->nak_frame = 0xFFFF;
38461 + }
38462 + }
38463 + }
38464 +
38465 + if (microframe_schedule) {
38466 + DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
38467 + if (hcd->available_host_channels < 1) {
38468 + DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
38469 + break;
38470 + }
38471 + hcd->available_host_channels--;
38472 + DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
38473 +#ifdef DEBUG_HOST_CHANNELS
38474 + last_sel_trans_num_nonper_scheduled++;
38475 +#endif /* DEBUG_HOST_CHANNELS */
38476 + }
38477 +
38478 + assign_and_init_hc(hcd, qh);
38479 +
38480 + /*
38481 + * Move the QH from the non-periodic inactive schedule to the
38482 + * non-periodic active schedule.
38483 + */
38484 + qh_ptr = DWC_LIST_NEXT(qh_ptr);
38485 + DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
38486 + DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active,
38487 + &qh->qh_list_entry);
38488 + DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
38489 +
38490 +
38491 + if (!microframe_schedule)
38492 + hcd->non_periodic_channels++;
38493 + }
38494 + /* we moved a non-periodic QH to the active schedule. If the inactive queue is empty,
38495 + * stop the FIQ from kicking us. We could potentially still have elements here if we
38496 + * ran out of host channels.
38497 + */
38498 + if (fiq_enable) {
38499 + if (DWC_LIST_EMPTY(&hcd->non_periodic_sched_inactive)) {
38500 + hcd->fiq_state->kick_np_queues = 0;
38501 + } else {
38502 + /* For each entry remaining in the NP inactive queue,
38503 + * if this a NAK'd retransmit then don't set the kick flag.
38504 + */
38505 + if(nak_holdoff) {
38506 + DWC_LIST_FOREACH(qh_ptr, &hcd->non_periodic_sched_inactive) {
38507 + qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
38508 + if (qh->nak_frame == 0xFFFF) {
38509 + hcd->fiq_state->kick_np_queues = 1;
38510 + }
38511 + }
38512 + }
38513 + }
38514 + }
38515 + if(!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned))
38516 + ret_val |= DWC_OTG_TRANSACTION_PERIODIC;
38517 +
38518 + if(!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active))
38519 + ret_val |= DWC_OTG_TRANSACTION_NON_PERIODIC;
38520 +
38521 +
38522 +#ifdef DEBUG_HOST_CHANNELS
38523 + last_sel_trans_num_avail_hc_at_end = hcd->available_host_channels;
38524 +#endif /* DEBUG_HOST_CHANNELS */
38525 + return ret_val;
38526 +}
38527 +
38528 +/**
38529 + * Attempts to queue a single transaction request for a host channel
38530 + * associated with either a periodic or non-periodic transfer. This function
38531 + * assumes that there is space available in the appropriate request queue. For
38532 + * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
38533 + * is available in the appropriate Tx FIFO.
38534 + *
38535 + * @param hcd The HCD state structure.
38536 + * @param hc Host channel descriptor associated with either a periodic or
38537 + * non-periodic transfer.
38538 + * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx
38539 + * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
38540 + * transfers.
38541 + *
38542 + * @return 1 if a request is queued and more requests may be needed to
38543 + * complete the transfer, 0 if no more requests are required for this
38544 + * transfer, -1 if there is insufficient space in the Tx FIFO.
38545 + */
38546 +static int queue_transaction(dwc_otg_hcd_t * hcd,
38547 + dwc_hc_t * hc, uint16_t fifo_dwords_avail)
38548 +{
38549 + int retval;
38550 +
38551 + if (hcd->core_if->dma_enable) {
38552 + if (hcd->core_if->dma_desc_enable) {
38553 + if (!hc->xfer_started
38554 + || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {
38555 + dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh);
38556 + hc->qh->ping_state = 0;
38557 + }
38558 + } else if (!hc->xfer_started) {
38559 + if (fiq_fsm_enable && hc->error_state) {
38560 + hcd->fiq_state->channel[hc->hc_num].nr_errors =
38561 + DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list)->error_count;
38562 + hcd->fiq_state->channel[hc->hc_num].fsm =
38563 + FIQ_PASSTHROUGH_ERRORSTATE;
38564 + }
38565 + dwc_otg_hc_start_transfer(hcd->core_if, hc);
38566 + hc->qh->ping_state = 0;
38567 + }
38568 + retval = 0;
38569 + } else if (hc->halt_pending) {
38570 + /* Don't queue a request if the channel has been halted. */
38571 + retval = 0;
38572 + } else if (hc->halt_on_queue) {
38573 + dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
38574 + retval = 0;
38575 + } else if (hc->do_ping) {
38576 + if (!hc->xfer_started) {
38577 + dwc_otg_hc_start_transfer(hcd->core_if, hc);
38578 + }
38579 + retval = 0;
38580 + } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
38581 + if ((fifo_dwords_avail * 4) >= hc->max_packet) {
38582 + if (!hc->xfer_started) {
38583 + dwc_otg_hc_start_transfer(hcd->core_if, hc);
38584 + retval = 1;
38585 + } else {
38586 + retval =
38587 + dwc_otg_hc_continue_transfer(hcd->core_if,
38588 + hc);
38589 + }
38590 + } else {
38591 + retval = -1;
38592 + }
38593 + } else {
38594 + if (!hc->xfer_started) {
38595 + dwc_otg_hc_start_transfer(hcd->core_if, hc);
38596 + retval = 1;
38597 + } else {
38598 + retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
38599 + }
38600 + }
38601 +
38602 + return retval;
38603 +}
38604 +
38605 +/**
38606 + * Processes periodic channels for the next frame and queues transactions for
38607 + * these channels to the DWC_otg controller. After queueing transactions, the
38608 + * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
38609 + * to queue as Periodic Tx FIFO or request queue space becomes available.
38610 + * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
38611 + */
38612 +static void process_periodic_channels(dwc_otg_hcd_t * hcd)
38613 +{
38614 + hptxsts_data_t tx_status;
38615 + dwc_list_link_t *qh_ptr;
38616 + dwc_otg_qh_t *qh;
38617 + int status = 0;
38618 + int no_queue_space = 0;
38619 + int no_fifo_space = 0;
38620 +
38621 + dwc_otg_host_global_regs_t *host_regs;
38622 + host_regs = hcd->core_if->host_if->host_global_regs;
38623 +
38624 + DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
38625 +#ifdef DEBUG
38626 + tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
38627 + DWC_DEBUGPL(DBG_HCDV,
38628 + " P Tx Req Queue Space Avail (before queue): %d\n",
38629 + tx_status.b.ptxqspcavail);
38630 + DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n",
38631 + tx_status.b.ptxfspcavail);
38632 +#endif
38633 +
38634 + qh_ptr = hcd->periodic_sched_assigned.next;
38635 + while (qh_ptr != &hcd->periodic_sched_assigned) {
38636 + tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
38637 + if (tx_status.b.ptxqspcavail == 0) {
38638 + no_queue_space = 1;
38639 + break;
38640 + }
38641 +
38642 + qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
38643 +
38644 + // Do not send a split start transaction any later than frame .6
38645 + // Note, we have to schedule a periodic in .5 to make it go in .6
38646 + if(fiq_fsm_enable && qh->do_split && ((dwc_otg_hcd_get_frame_number(hcd) + 1) & 7) > 6)
38647 + {
38648 + qh_ptr = qh_ptr->next;
38649 + hcd->fiq_state->next_sched_frame = dwc_otg_hcd_get_frame_number(hcd) | 7;
38650 + continue;
38651 + }
38652 +
38653 + if (fiq_fsm_enable && fiq_fsm_transaction_suitable(qh)) {
38654 + if (qh->do_split)
38655 + fiq_fsm_queue_split_transaction(hcd, qh);
38656 + else
38657 + fiq_fsm_queue_isoc_transaction(hcd, qh);
38658 + } else {
38659 +
38660 + /*
38661 + * Set a flag if we're queueing high-bandwidth in slave mode.
38662 + * The flag prevents any halts to get into the request queue in
38663 + * the middle of multiple high-bandwidth packets getting queued.
38664 + */
38665 + if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) {
38666 + hcd->core_if->queuing_high_bandwidth = 1;
38667 + }
38668 + status = queue_transaction(hcd, qh->channel,
38669 + tx_status.b.ptxfspcavail);
38670 + if (status < 0) {
38671 + no_fifo_space = 1;
38672 + break;
38673 + }
38674 + }
38675 +
38676 + /*
38677 + * In Slave mode, stay on the current transfer until there is
38678 + * nothing more to do or the high-bandwidth request count is
38679 + * reached. In DMA mode, only need to queue one request. The
38680 + * controller automatically handles multiple packets for
38681 + * high-bandwidth transfers.
38682 + */
38683 + if (hcd->core_if->dma_enable || status == 0 ||
38684 + qh->channel->requests == qh->channel->multi_count) {
38685 + qh_ptr = qh_ptr->next;
38686 + /*
38687 + * Move the QH from the periodic assigned schedule to
38688 + * the periodic queued schedule.
38689 + */
38690 + DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued,
38691 + &qh->qh_list_entry);
38692 +
38693 + /* done queuing high bandwidth */
38694 + hcd->core_if->queuing_high_bandwidth = 0;
38695 + }
38696 + }
38697 +
38698 + if (!hcd->core_if->dma_enable) {
38699 + dwc_otg_core_global_regs_t *global_regs;
38700 + gintmsk_data_t intr_mask = {.d32 = 0 };
38701 +
38702 + global_regs = hcd->core_if->core_global_regs;
38703 + intr_mask.b.ptxfempty = 1;
38704 +#ifdef DEBUG
38705 + tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
38706 + DWC_DEBUGPL(DBG_HCDV,
38707 + " P Tx Req Queue Space Avail (after queue): %d\n",
38708 + tx_status.b.ptxqspcavail);
38709 + DWC_DEBUGPL(DBG_HCDV,
38710 + " P Tx FIFO Space Avail (after queue): %d\n",
38711 + tx_status.b.ptxfspcavail);
38712 +#endif
38713 + if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) ||
38714 + no_queue_space || no_fifo_space) {
38715 + /*
38716 + * May need to queue more transactions as the request
38717 + * queue or Tx FIFO empties. Enable the periodic Tx
38718 + * FIFO empty interrupt. (Always use the half-empty
38719 + * level to ensure that new requests are loaded as
38720 + * soon as possible.)
38721 + */
38722 + DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
38723 + intr_mask.d32);
38724 + } else {
38725 + /*
38726 + * Disable the Tx FIFO empty interrupt since there are
38727 + * no more transactions that need to be queued right
38728 + * now. This function is called from interrupt
38729 + * handlers to queue more transactions as transfer
38730 + * states change.
38731 + */
38732 + DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
38733 + 0);
38734 + }
38735 + }
38736 +}
38737 +
38738 +/**
38739 + * Processes active non-periodic channels and queues transactions for these
38740 + * channels to the DWC_otg controller. After queueing transactions, the NP Tx
38741 + * FIFO Empty interrupt is enabled if there are more transactions to queue as
38742 + * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
38743 + * FIFO Empty interrupt is disabled.
38744 + */
38745 +static void process_non_periodic_channels(dwc_otg_hcd_t * hcd)
38746 +{
38747 + gnptxsts_data_t tx_status;
38748 + dwc_list_link_t *orig_qh_ptr;
38749 + dwc_otg_qh_t *qh;
38750 + int status;
38751 + int no_queue_space = 0;
38752 + int no_fifo_space = 0;
38753 + int more_to_do = 0;
38754 +
38755 + dwc_otg_core_global_regs_t *global_regs =
38756 + hcd->core_if->core_global_regs;
38757 +
38758 + DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
38759 +#ifdef DEBUG
38760 + tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
38761 + DWC_DEBUGPL(DBG_HCDV,
38762 + " NP Tx Req Queue Space Avail (before queue): %d\n",
38763 + tx_status.b.nptxqspcavail);
38764 + DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n",
38765 + tx_status.b.nptxfspcavail);
38766 +#endif
38767 + /*
38768 + * Keep track of the starting point. Skip over the start-of-list
38769 + * entry.
38770 + */
38771 + if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
38772 + hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
38773 + }
38774 + orig_qh_ptr = hcd->non_periodic_qh_ptr;
38775 +
38776 + /*
38777 + * Process once through the active list or until no more space is
38778 + * available in the request queue or the Tx FIFO.
38779 + */
38780 + do {
38781 + tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
38782 + if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
38783 + no_queue_space = 1;
38784 + break;
38785 + }
38786 +
38787 + qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t,
38788 + qh_list_entry);
38789 +
38790 + if(fiq_fsm_enable && fiq_fsm_transaction_suitable(qh)) {
38791 + fiq_fsm_queue_split_transaction(hcd, qh);
38792 + } else {
38793 + status = queue_transaction(hcd, qh->channel,
38794 + tx_status.b.nptxfspcavail);
38795 +
38796 + if (status > 0) {
38797 + more_to_do = 1;
38798 + } else if (status < 0) {
38799 + no_fifo_space = 1;
38800 + break;
38801 + }
38802 + }
38803 + /* Advance to next QH, skipping start-of-list entry. */
38804 + hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
38805 + if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
38806 + hcd->non_periodic_qh_ptr =
38807 + hcd->non_periodic_qh_ptr->next;
38808 + }
38809 +
38810 + } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
38811 +
38812 + if (!hcd->core_if->dma_enable) {
38813 + gintmsk_data_t intr_mask = {.d32 = 0 };
38814 + intr_mask.b.nptxfempty = 1;
38815 +
38816 +#ifdef DEBUG
38817 + tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
38818 + DWC_DEBUGPL(DBG_HCDV,
38819 + " NP Tx Req Queue Space Avail (after queue): %d\n",
38820 + tx_status.b.nptxqspcavail);
38821 + DWC_DEBUGPL(DBG_HCDV,
38822 + " NP Tx FIFO Space Avail (after queue): %d\n",
38823 + tx_status.b.nptxfspcavail);
38824 +#endif
38825 + if (more_to_do || no_queue_space || no_fifo_space) {
38826 + /*
38827 + * May need to queue more transactions as the request
38828 + * queue or Tx FIFO empties. Enable the non-periodic
38829 + * Tx FIFO empty interrupt. (Always use the half-empty
38830 + * level to ensure that new requests are loaded as
38831 + * soon as possible.)
38832 + */
38833 + DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
38834 + intr_mask.d32);
38835 + } else {
38836 + /*
38837 + * Disable the Tx FIFO empty interrupt since there are
38838 + * no more transactions that need to be queued right
38839 + * now. This function is called from interrupt
38840 + * handlers to queue more transactions as transfer
38841 + * states change.
38842 + */
38843 + DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
38844 + 0);
38845 + }
38846 + }
38847 +}
38848 +
38849 +/**
38850 + * This function processes the currently active host channels and queues
38851 + * transactions for these channels to the DWC_otg controller. It is called
38852 + * from HCD interrupt handler functions.
38853 + *
38854 + * @param hcd The HCD state structure.
38855 + * @param tr_type The type(s) of transactions to queue (non-periodic,
38856 + * periodic, or both).
38857 + */
38858 +void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
38859 + dwc_otg_transaction_type_e tr_type)
38860 +{
38861 +#ifdef DEBUG_SOF
38862 + DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
38863 +#endif
38864 + /* Process host channels associated with periodic transfers. */
38865 + if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
38866 + tr_type == DWC_OTG_TRANSACTION_ALL) &&
38867 + !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) {
38868 +
38869 + process_periodic_channels(hcd);
38870 + }
38871 +
38872 + /* Process host channels associated with non-periodic transfers. */
38873 + if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
38874 + tr_type == DWC_OTG_TRANSACTION_ALL) {
38875 + if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) {
38876 + process_non_periodic_channels(hcd);
38877 + } else {
38878 + /*
38879 + * Ensure NP Tx FIFO empty interrupt is disabled when
38880 + * there are no non-periodic transfers to process.
38881 + */
38882 + gintmsk_data_t gintmsk = {.d32 = 0 };
38883 + gintmsk.b.nptxfempty = 1;
38884 +
38885 + if (fiq_enable) {
38886 + local_fiq_disable();
38887 + fiq_fsm_spin_lock(&hcd->fiq_state->lock);
38888 + DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
38889 + fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
38890 + local_fiq_enable();
38891 + } else {
38892 + DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
38893 + }
38894 + }
38895 + }
38896 +}
38897 +
38898 +#ifdef DWC_HS_ELECT_TST
38899 +/*
38900 + * Quick and dirty hack to implement the HS Electrical Test
38901 + * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
38902 + *
38903 + * This code was copied from our userspace app "hset". It sends a
38904 + * Get Device Descriptor control sequence in two parts, first the
38905 + * Setup packet by itself, followed some time later by the In and
38906 + * Ack packets. Rather than trying to figure out how to add this
38907 + * functionality to the normal driver code, we just hijack the
38908 + * hardware, using these two function to drive the hardware
38909 + * directly.
38910 + */
38911 +
38912 +static dwc_otg_core_global_regs_t *global_regs;
38913 +static dwc_otg_host_global_regs_t *hc_global_regs;
38914 +static dwc_otg_hc_regs_t *hc_regs;
38915 +static uint32_t *data_fifo;
38916 +
38917 +static void do_setup(void)
38918 +{
38919 + gintsts_data_t gintsts;
38920 + hctsiz_data_t hctsiz;
38921 + hcchar_data_t hcchar;
38922 + haint_data_t haint;
38923 + hcint_data_t hcint;
38924 +
38925 + /* Enable HAINTs */
38926 + DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
38927 +
38928 + /* Enable HCINTs */
38929 + DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
38930 +
38931 + /* Read GINTSTS */
38932 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
38933 +
38934 + /* Read HAINT */
38935 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
38936 +
38937 + /* Read HCINT */
38938 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
38939 +
38940 + /* Read HCCHAR */
38941 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
38942 +
38943 + /* Clear HCINT */
38944 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
38945 +
38946 + /* Clear HAINT */
38947 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
38948 +
38949 + /* Clear GINTSTS */
38950 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
38951 +
38952 + /* Read GINTSTS */
38953 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
38954 +
38955 + /*
38956 + * Send Setup packet (Get Device Descriptor)
38957 + */
38958 +
38959 + /* Make sure channel is disabled */
38960 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
38961 + if (hcchar.b.chen) {
38962 + hcchar.b.chdis = 1;
38963 +// hcchar.b.chen = 1;
38964 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
38965 + //sleep(1);
38966 + dwc_mdelay(1000);
38967 +
38968 + /* Read GINTSTS */
38969 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
38970 +
38971 + /* Read HAINT */
38972 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
38973 +
38974 + /* Read HCINT */
38975 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
38976 +
38977 + /* Read HCCHAR */
38978 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
38979 +
38980 + /* Clear HCINT */
38981 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
38982 +
38983 + /* Clear HAINT */
38984 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
38985 +
38986 + /* Clear GINTSTS */
38987 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
38988 +
38989 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
38990 + }
38991 +
38992 + /* Set HCTSIZ */
38993 + hctsiz.d32 = 0;
38994 + hctsiz.b.xfersize = 8;
38995 + hctsiz.b.pktcnt = 1;
38996 + hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
38997 + DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
38998 +
38999 + /* Set HCCHAR */
39000 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39001 + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
39002 + hcchar.b.epdir = 0;
39003 + hcchar.b.epnum = 0;
39004 + hcchar.b.mps = 8;
39005 + hcchar.b.chen = 1;
39006 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
39007 +
39008 + /* Fill FIFO with Setup data for Get Device Descriptor */
39009 + data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
39010 + DWC_WRITE_REG32(data_fifo++, 0x01000680);
39011 + DWC_WRITE_REG32(data_fifo++, 0x00080000);
39012 +
39013 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39014 +
39015 + /* Wait for host channel interrupt */
39016 + do {
39017 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39018 + } while (gintsts.b.hcintr == 0);
39019 +
39020 + /* Disable HCINTs */
39021 + DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
39022 +
39023 + /* Disable HAINTs */
39024 + DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
39025 +
39026 + /* Read HAINT */
39027 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
39028 +
39029 + /* Read HCINT */
39030 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
39031 +
39032 + /* Read HCCHAR */
39033 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39034 +
39035 + /* Clear HCINT */
39036 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
39037 +
39038 + /* Clear HAINT */
39039 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
39040 +
39041 + /* Clear GINTSTS */
39042 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
39043 +
39044 + /* Read GINTSTS */
39045 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39046 +}
39047 +
39048 +static void do_in_ack(void)
39049 +{
39050 + gintsts_data_t gintsts;
39051 + hctsiz_data_t hctsiz;
39052 + hcchar_data_t hcchar;
39053 + haint_data_t haint;
39054 + hcint_data_t hcint;
39055 + host_grxsts_data_t grxsts;
39056 +
39057 + /* Enable HAINTs */
39058 + DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
39059 +
39060 + /* Enable HCINTs */
39061 + DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
39062 +
39063 + /* Read GINTSTS */
39064 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39065 +
39066 + /* Read HAINT */
39067 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
39068 +
39069 + /* Read HCINT */
39070 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
39071 +
39072 + /* Read HCCHAR */
39073 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39074 +
39075 + /* Clear HCINT */
39076 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
39077 +
39078 + /* Clear HAINT */
39079 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
39080 +
39081 + /* Clear GINTSTS */
39082 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
39083 +
39084 + /* Read GINTSTS */
39085 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39086 +
39087 + /*
39088 + * Receive Control In packet
39089 + */
39090 +
39091 + /* Make sure channel is disabled */
39092 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39093 + if (hcchar.b.chen) {
39094 + hcchar.b.chdis = 1;
39095 + hcchar.b.chen = 1;
39096 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
39097 + //sleep(1);
39098 + dwc_mdelay(1000);
39099 +
39100 + /* Read GINTSTS */
39101 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39102 +
39103 + /* Read HAINT */
39104 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
39105 +
39106 + /* Read HCINT */
39107 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
39108 +
39109 + /* Read HCCHAR */
39110 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39111 +
39112 + /* Clear HCINT */
39113 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
39114 +
39115 + /* Clear HAINT */
39116 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
39117 +
39118 + /* Clear GINTSTS */
39119 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
39120 +
39121 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39122 + }
39123 +
39124 + /* Set HCTSIZ */
39125 + hctsiz.d32 = 0;
39126 + hctsiz.b.xfersize = 8;
39127 + hctsiz.b.pktcnt = 1;
39128 + hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
39129 + DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
39130 +
39131 + /* Set HCCHAR */
39132 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39133 + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
39134 + hcchar.b.epdir = 1;
39135 + hcchar.b.epnum = 0;
39136 + hcchar.b.mps = 8;
39137 + hcchar.b.chen = 1;
39138 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
39139 +
39140 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39141 +
39142 + /* Wait for receive status queue interrupt */
39143 + do {
39144 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39145 + } while (gintsts.b.rxstsqlvl == 0);
39146 +
39147 + /* Read RXSTS */
39148 + grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
39149 +
39150 + /* Clear RXSTSQLVL in GINTSTS */
39151 + gintsts.d32 = 0;
39152 + gintsts.b.rxstsqlvl = 1;
39153 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
39154 +
39155 + switch (grxsts.b.pktsts) {
39156 + case DWC_GRXSTS_PKTSTS_IN:
39157 + /* Read the data into the host buffer */
39158 + if (grxsts.b.bcnt > 0) {
39159 + int i;
39160 + int word_count = (grxsts.b.bcnt + 3) / 4;
39161 +
39162 + data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
39163 +
39164 + for (i = 0; i < word_count; i++) {
39165 + (void)DWC_READ_REG32(data_fifo++);
39166 + }
39167 + }
39168 + break;
39169 +
39170 + default:
39171 + break;
39172 + }
39173 +
39174 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39175 +
39176 + /* Wait for receive status queue interrupt */
39177 + do {
39178 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39179 + } while (gintsts.b.rxstsqlvl == 0);
39180 +
39181 + /* Read RXSTS */
39182 + grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
39183 +
39184 + /* Clear RXSTSQLVL in GINTSTS */
39185 + gintsts.d32 = 0;
39186 + gintsts.b.rxstsqlvl = 1;
39187 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
39188 +
39189 + switch (grxsts.b.pktsts) {
39190 + case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
39191 + break;
39192 +
39193 + default:
39194 + break;
39195 + }
39196 +
39197 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39198 +
39199 + /* Wait for host channel interrupt */
39200 + do {
39201 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39202 + } while (gintsts.b.hcintr == 0);
39203 +
39204 + /* Read HAINT */
39205 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
39206 +
39207 + /* Read HCINT */
39208 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
39209 +
39210 + /* Read HCCHAR */
39211 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39212 +
39213 + /* Clear HCINT */
39214 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
39215 +
39216 + /* Clear HAINT */
39217 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
39218 +
39219 + /* Clear GINTSTS */
39220 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
39221 +
39222 + /* Read GINTSTS */
39223 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39224 +
39225 +// usleep(100000);
39226 +// mdelay(100);
39227 + dwc_mdelay(1);
39228 +
39229 + /*
39230 + * Send handshake packet
39231 + */
39232 +
39233 + /* Read HAINT */
39234 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
39235 +
39236 + /* Read HCINT */
39237 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
39238 +
39239 + /* Read HCCHAR */
39240 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39241 +
39242 + /* Clear HCINT */
39243 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
39244 +
39245 + /* Clear HAINT */
39246 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
39247 +
39248 + /* Clear GINTSTS */
39249 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
39250 +
39251 + /* Read GINTSTS */
39252 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39253 +
39254 + /* Make sure channel is disabled */
39255 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39256 + if (hcchar.b.chen) {
39257 + hcchar.b.chdis = 1;
39258 + hcchar.b.chen = 1;
39259 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
39260 + //sleep(1);
39261 + dwc_mdelay(1000);
39262 +
39263 + /* Read GINTSTS */
39264 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39265 +
39266 + /* Read HAINT */
39267 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
39268 +
39269 + /* Read HCINT */
39270 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
39271 +
39272 + /* Read HCCHAR */
39273 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39274 +
39275 + /* Clear HCINT */
39276 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
39277 +
39278 + /* Clear HAINT */
39279 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
39280 +
39281 + /* Clear GINTSTS */
39282 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
39283 +
39284 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39285 + }
39286 +
39287 + /* Set HCTSIZ */
39288 + hctsiz.d32 = 0;
39289 + hctsiz.b.xfersize = 0;
39290 + hctsiz.b.pktcnt = 1;
39291 + hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
39292 + DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
39293 +
39294 + /* Set HCCHAR */
39295 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39296 + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
39297 + hcchar.b.epdir = 0;
39298 + hcchar.b.epnum = 0;
39299 + hcchar.b.mps = 8;
39300 + hcchar.b.chen = 1;
39301 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
39302 +
39303 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39304 +
39305 + /* Wait for host channel interrupt */
39306 + do {
39307 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39308 + } while (gintsts.b.hcintr == 0);
39309 +
39310 + /* Disable HCINTs */
39311 + DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
39312 +
39313 + /* Disable HAINTs */
39314 + DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
39315 +
39316 + /* Read HAINT */
39317 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
39318 +
39319 + /* Read HCINT */
39320 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
39321 +
39322 + /* Read HCCHAR */
39323 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39324 +
39325 + /* Clear HCINT */
39326 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
39327 +
39328 + /* Clear HAINT */
39329 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
39330 +
39331 + /* Clear GINTSTS */
39332 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
39333 +
39334 + /* Read GINTSTS */
39335 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39336 +}
39337 +#endif
39338 +
39339 +/** Handles hub class-specific requests. */
39340 +int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
39341 + uint16_t typeReq,
39342 + uint16_t wValue,
39343 + uint16_t wIndex, uint8_t * buf, uint16_t wLength)
39344 +{
39345 + int retval = 0;
39346 +
39347 + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
39348 + usb_hub_descriptor_t *hub_desc;
39349 + hprt0_data_t hprt0 = {.d32 = 0 };
39350 +
39351 + uint32_t port_status;
39352 +
39353 + switch (typeReq) {
39354 + case UCR_CLEAR_HUB_FEATURE:
39355 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39356 + "ClearHubFeature 0x%x\n", wValue);
39357 + switch (wValue) {
39358 + case UHF_C_HUB_LOCAL_POWER:
39359 + case UHF_C_HUB_OVER_CURRENT:
39360 + /* Nothing required here */
39361 + break;
39362 + default:
39363 + retval = -DWC_E_INVALID;
39364 + DWC_ERROR("DWC OTG HCD - "
39365 + "ClearHubFeature request %xh unknown\n",
39366 + wValue);
39367 + }
39368 + break;
39369 + case UCR_CLEAR_PORT_FEATURE:
39370 +#ifdef CONFIG_USB_DWC_OTG_LPM
39371 + if (wValue != UHF_PORT_L1)
39372 +#endif
39373 + if (!wIndex || wIndex > 1)
39374 + goto error;
39375 +
39376 + switch (wValue) {
39377 + case UHF_PORT_ENABLE:
39378 + DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
39379 + "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
39380 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
39381 + hprt0.b.prtena = 1;
39382 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39383 + break;
39384 + case UHF_PORT_SUSPEND:
39385 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39386 + "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
39387 +
39388 + if (core_if->power_down == 2) {
39389 + dwc_otg_host_hibernation_restore(core_if, 0, 0);
39390 + } else {
39391 + DWC_WRITE_REG32(core_if->pcgcctl, 0);
39392 + dwc_mdelay(5);
39393 +
39394 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
39395 + hprt0.b.prtres = 1;
39396 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39397 + hprt0.b.prtsusp = 0;
39398 + /* Clear Resume bit */
39399 + dwc_mdelay(100);
39400 + hprt0.b.prtres = 0;
39401 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39402 + }
39403 + break;
39404 +#ifdef CONFIG_USB_DWC_OTG_LPM
39405 + case UHF_PORT_L1:
39406 + {
39407 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
39408 + glpmcfg_data_t lpmcfg = {.d32 = 0 };
39409 +
39410 + lpmcfg.d32 =
39411 + DWC_READ_REG32(&core_if->
39412 + core_global_regs->glpmcfg);
39413 + lpmcfg.b.en_utmi_sleep = 0;
39414 + lpmcfg.b.hird_thres &= (~(1 << 4));
39415 + lpmcfg.b.prt_sleep_sts = 1;
39416 + DWC_WRITE_REG32(&core_if->
39417 + core_global_regs->glpmcfg,
39418 + lpmcfg.d32);
39419 +
39420 + /* Clear Enbl_L1Gating bit. */
39421 + pcgcctl.b.enbl_sleep_gating = 1;
39422 + DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
39423 + 0);
39424 +
39425 + dwc_mdelay(5);
39426 +
39427 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
39428 + hprt0.b.prtres = 1;
39429 + DWC_WRITE_REG32(core_if->host_if->hprt0,
39430 + hprt0.d32);
39431 + /* This bit will be cleared in wakeup interrupt handle */
39432 + break;
39433 + }
39434 +#endif
39435 + case UHF_PORT_POWER:
39436 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39437 + "ClearPortFeature USB_PORT_FEAT_POWER\n");
39438 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
39439 + hprt0.b.prtpwr = 0;
39440 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39441 + break;
39442 + case UHF_PORT_INDICATOR:
39443 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39444 + "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
39445 + /* Port inidicator not supported */
39446 + break;
39447 + case UHF_C_PORT_CONNECTION:
39448 + /* Clears drivers internal connect status change
39449 + * flag */
39450 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39451 + "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
39452 + dwc_otg_hcd->flags.b.port_connect_status_change = 0;
39453 + break;
39454 + case UHF_C_PORT_RESET:
39455 + /* Clears the driver's internal Port Reset Change
39456 + * flag */
39457 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39458 + "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
39459 + dwc_otg_hcd->flags.b.port_reset_change = 0;
39460 + break;
39461 + case UHF_C_PORT_ENABLE:
39462 + /* Clears the driver's internal Port
39463 + * Enable/Disable Change flag */
39464 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39465 + "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
39466 + dwc_otg_hcd->flags.b.port_enable_change = 0;
39467 + break;
39468 + case UHF_C_PORT_SUSPEND:
39469 + /* Clears the driver's internal Port Suspend
39470 + * Change flag, which is set when resume signaling on
39471 + * the host port is complete */
39472 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39473 + "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
39474 + dwc_otg_hcd->flags.b.port_suspend_change = 0;
39475 + break;
39476 +#ifdef CONFIG_USB_DWC_OTG_LPM
39477 + case UHF_C_PORT_L1:
39478 + dwc_otg_hcd->flags.b.port_l1_change = 0;
39479 + break;
39480 +#endif
39481 + case UHF_C_PORT_OVER_CURRENT:
39482 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39483 + "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
39484 + dwc_otg_hcd->flags.b.port_over_current_change = 0;
39485 + break;
39486 + default:
39487 + retval = -DWC_E_INVALID;
39488 + DWC_ERROR("DWC OTG HCD - "
39489 + "ClearPortFeature request %xh "
39490 + "unknown or unsupported\n", wValue);
39491 + }
39492 + break;
39493 + case UCR_GET_HUB_DESCRIPTOR:
39494 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39495 + "GetHubDescriptor\n");
39496 + hub_desc = (usb_hub_descriptor_t *) buf;
39497 + hub_desc->bDescLength = 9;
39498 + hub_desc->bDescriptorType = 0x29;
39499 + hub_desc->bNbrPorts = 1;
39500 + USETW(hub_desc->wHubCharacteristics, 0x08);
39501 + hub_desc->bPwrOn2PwrGood = 1;
39502 + hub_desc->bHubContrCurrent = 0;
39503 + hub_desc->DeviceRemovable[0] = 0;
39504 + hub_desc->DeviceRemovable[1] = 0xff;
39505 + break;
39506 + case UCR_GET_HUB_STATUS:
39507 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39508 + "GetHubStatus\n");
39509 + DWC_MEMSET(buf, 0, 4);
39510 + break;
39511 + case UCR_GET_PORT_STATUS:
39512 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39513 + "GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\n",
39514 + wIndex, dwc_otg_hcd->flags.d32);
39515 + if (!wIndex || wIndex > 1)
39516 + goto error;
39517 +
39518 + port_status = 0;
39519 +
39520 + if (dwc_otg_hcd->flags.b.port_connect_status_change)
39521 + port_status |= (1 << UHF_C_PORT_CONNECTION);
39522 +
39523 + if (dwc_otg_hcd->flags.b.port_enable_change)
39524 + port_status |= (1 << UHF_C_PORT_ENABLE);
39525 +
39526 + if (dwc_otg_hcd->flags.b.port_suspend_change)
39527 + port_status |= (1 << UHF_C_PORT_SUSPEND);
39528 +
39529 + if (dwc_otg_hcd->flags.b.port_l1_change)
39530 + port_status |= (1 << UHF_C_PORT_L1);
39531 +
39532 + if (dwc_otg_hcd->flags.b.port_reset_change) {
39533 + port_status |= (1 << UHF_C_PORT_RESET);
39534 + }
39535 +
39536 + if (dwc_otg_hcd->flags.b.port_over_current_change) {
39537 + DWC_WARN("Overcurrent change detected\n");
39538 + port_status |= (1 << UHF_C_PORT_OVER_CURRENT);
39539 + }
39540 +
39541 + if (!dwc_otg_hcd->flags.b.port_connect_status) {
39542 + /*
39543 + * The port is disconnected, which means the core is
39544 + * either in device mode or it soon will be. Just
39545 + * return 0's for the remainder of the port status
39546 + * since the port register can't be read if the core
39547 + * is in device mode.
39548 + */
39549 + *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
39550 + break;
39551 + }
39552 +
39553 + hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
39554 + DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32);
39555 +
39556 + if (hprt0.b.prtconnsts)
39557 + port_status |= (1 << UHF_PORT_CONNECTION);
39558 +
39559 + if (hprt0.b.prtena)
39560 + port_status |= (1 << UHF_PORT_ENABLE);
39561 +
39562 + if (hprt0.b.prtsusp)
39563 + port_status |= (1 << UHF_PORT_SUSPEND);
39564 +
39565 + if (hprt0.b.prtovrcurract)
39566 + port_status |= (1 << UHF_PORT_OVER_CURRENT);
39567 +
39568 + if (hprt0.b.prtrst)
39569 + port_status |= (1 << UHF_PORT_RESET);
39570 +
39571 + if (hprt0.b.prtpwr)
39572 + port_status |= (1 << UHF_PORT_POWER);
39573 +
39574 + if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
39575 + port_status |= (1 << UHF_PORT_HIGH_SPEED);
39576 + else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
39577 + port_status |= (1 << UHF_PORT_LOW_SPEED);
39578 +
39579 + if (hprt0.b.prttstctl)
39580 + port_status |= (1 << UHF_PORT_TEST);
39581 + if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) {
39582 + port_status |= (1 << UHF_PORT_L1);
39583 + }
39584 + /*
39585 + For Synopsys HW emulation of Power down wkup_control asserts the
39586 + hreset_n and prst_n on suspned. This causes the HPRT0 to be zero.
39587 + We intentionally tell the software that port is in L2Suspend state.
39588 + Only for STE.
39589 + */
39590 + if ((core_if->power_down == 2)
39591 + && (core_if->hibernation_suspend == 1)) {
39592 + port_status |= (1 << UHF_PORT_SUSPEND);
39593 + }
39594 + /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
39595 +
39596 + *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
39597 +
39598 + break;
39599 + case UCR_SET_HUB_FEATURE:
39600 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39601 + "SetHubFeature\n");
39602 + /* No HUB features supported */
39603 + break;
39604 + case UCR_SET_PORT_FEATURE:
39605 + if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1))
39606 + goto error;
39607 +
39608 + if (!dwc_otg_hcd->flags.b.port_connect_status) {
39609 + /*
39610 + * The port is disconnected, which means the core is
39611 + * either in device mode or it soon will be. Just
39612 + * return without doing anything since the port
39613 + * register can't be written if the core is in device
39614 + * mode.
39615 + */
39616 + break;
39617 + }
39618 +
39619 + switch (wValue) {
39620 + case UHF_PORT_SUSPEND:
39621 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39622 + "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
39623 + if (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) {
39624 + goto error;
39625 + }
39626 + if (core_if->power_down == 2) {
39627 + int timeout = 300;
39628 + dwc_irqflags_t flags;
39629 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
39630 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
39631 + gusbcfg_data_t gusbcfg = {.d32 = 0 };
39632 +#ifdef DWC_DEV_SRPCAP
39633 + int32_t otg_cap_param = core_if->core_params->otg_cap;
39634 +#endif
39635 + DWC_PRINTF("Preparing for complete power-off\n");
39636 +
39637 + /* Save registers before hibernation */
39638 + dwc_otg_save_global_regs(core_if);
39639 + dwc_otg_save_host_regs(core_if);
39640 +
39641 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
39642 + hprt0.b.prtsusp = 1;
39643 + hprt0.b.prtena = 0;
39644 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39645 + /* Spin hprt0.b.prtsusp to became 1 */
39646 + do {
39647 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
39648 + if (hprt0.b.prtsusp) {
39649 + break;
39650 + }
39651 + dwc_mdelay(1);
39652 + } while (--timeout);
39653 + if (!timeout) {
39654 + DWC_WARN("Suspend wasn't genereted\n");
39655 + }
39656 + dwc_udelay(10);
39657 +
39658 + /*
39659 + * We need to disable interrupts to prevent servicing of any IRQ
39660 + * during going to hibernation
39661 + */
39662 + DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
39663 + core_if->lx_state = DWC_OTG_L2;
39664 +#ifdef DWC_DEV_SRPCAP
39665 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
39666 + hprt0.b.prtpwr = 0;
39667 + hprt0.b.prtena = 0;
39668 + DWC_WRITE_REG32(core_if->host_if->hprt0,
39669 + hprt0.d32);
39670 +#endif
39671 + gusbcfg.d32 =
39672 + DWC_READ_REG32(&core_if->core_global_regs->
39673 + gusbcfg);
39674 + if (gusbcfg.b.ulpi_utmi_sel == 1) {
39675 + /* ULPI interface */
39676 + /* Suspend the Phy Clock */
39677 + pcgcctl.d32 = 0;
39678 + pcgcctl.b.stoppclk = 1;
39679 + DWC_MODIFY_REG32(core_if->pcgcctl, 0,
39680 + pcgcctl.d32);
39681 + dwc_udelay(10);
39682 + gpwrdn.b.pmuactv = 1;
39683 + DWC_MODIFY_REG32(&core_if->
39684 + core_global_regs->
39685 + gpwrdn, 0, gpwrdn.d32);
39686 + } else {
39687 + /* UTMI+ Interface */
39688 + gpwrdn.b.pmuactv = 1;
39689 + DWC_MODIFY_REG32(&core_if->
39690 + core_global_regs->
39691 + gpwrdn, 0, gpwrdn.d32);
39692 + dwc_udelay(10);
39693 + pcgcctl.b.stoppclk = 1;
39694 + DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
39695 + dwc_udelay(10);
39696 + }
39697 +#ifdef DWC_DEV_SRPCAP
39698 + gpwrdn.d32 = 0;
39699 + gpwrdn.b.dis_vbus = 1;
39700 + DWC_MODIFY_REG32(&core_if->core_global_regs->
39701 + gpwrdn, 0, gpwrdn.d32);
39702 +#endif
39703 + gpwrdn.d32 = 0;
39704 + gpwrdn.b.pmuintsel = 1;
39705 + DWC_MODIFY_REG32(&core_if->core_global_regs->
39706 + gpwrdn, 0, gpwrdn.d32);
39707 + dwc_udelay(10);
39708 +
39709 + gpwrdn.d32 = 0;
39710 +#ifdef DWC_DEV_SRPCAP
39711 + gpwrdn.b.srp_det_msk = 1;
39712 +#endif
39713 + gpwrdn.b.disconn_det_msk = 1;
39714 + gpwrdn.b.lnstchng_msk = 1;
39715 + gpwrdn.b.sts_chngint_msk = 1;
39716 + DWC_MODIFY_REG32(&core_if->core_global_regs->
39717 + gpwrdn, 0, gpwrdn.d32);
39718 + dwc_udelay(10);
39719 +
39720 + /* Enable Power Down Clamp and all interrupts in GPWRDN */
39721 + gpwrdn.d32 = 0;
39722 + gpwrdn.b.pwrdnclmp = 1;
39723 + DWC_MODIFY_REG32(&core_if->core_global_regs->
39724 + gpwrdn, 0, gpwrdn.d32);
39725 + dwc_udelay(10);
39726 +
39727 + /* Switch off VDD */
39728 + gpwrdn.d32 = 0;
39729 + gpwrdn.b.pwrdnswtch = 1;
39730 + DWC_MODIFY_REG32(&core_if->core_global_regs->
39731 + gpwrdn, 0, gpwrdn.d32);
39732 +
39733 +#ifdef DWC_DEV_SRPCAP
39734 + if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE)
39735 + {
39736 + core_if->pwron_timer_started = 1;
39737 + DWC_TIMER_SCHEDULE(core_if->pwron_timer, 6000 /* 6 secs */ );
39738 + }
39739 +#endif
39740 + /* Save gpwrdn register for further usage if stschng interrupt */
39741 + core_if->gr_backup->gpwrdn_local =
39742 + DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
39743 +
39744 + /* Set flag to indicate that we are in hibernation */
39745 + core_if->hibernation_suspend = 1;
39746 + DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,flags);
39747 +
39748 + DWC_PRINTF("Host hibernation completed\n");
39749 + // Exit from case statement
39750 + break;
39751 +
39752 + }
39753 + if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex &&
39754 + dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
39755 + gotgctl_data_t gotgctl = {.d32 = 0 };
39756 + gotgctl.b.hstsethnpen = 1;
39757 + DWC_MODIFY_REG32(&core_if->core_global_regs->
39758 + gotgctl, 0, gotgctl.d32);
39759 + core_if->op_state = A_SUSPEND;
39760 + }
39761 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
39762 + hprt0.b.prtsusp = 1;
39763 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39764 + {
39765 + dwc_irqflags_t flags;
39766 + /* Update lx_state */
39767 + DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
39768 + core_if->lx_state = DWC_OTG_L2;
39769 + DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
39770 + }
39771 + /* Suspend the Phy Clock */
39772 + {
39773 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
39774 + pcgcctl.b.stoppclk = 1;
39775 + DWC_MODIFY_REG32(core_if->pcgcctl, 0,
39776 + pcgcctl.d32);
39777 + dwc_udelay(10);
39778 + }
39779 +
39780 + /* For HNP the bus must be suspended for at least 200ms. */
39781 + if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
39782 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
39783 + pcgcctl.b.stoppclk = 1;
39784 + DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
39785 + dwc_mdelay(200);
39786 + }
39787 +
39788 + /** @todo - check how sw can wait for 1 sec to check asesvld??? */
39789 +#if 0 //vahrama !!!!!!!!!!!!!!!!!!
39790 + if (core_if->adp_enable) {
39791 + gotgctl_data_t gotgctl = {.d32 = 0 };
39792 + gpwrdn_data_t gpwrdn;
39793 +
39794 + while (gotgctl.b.asesvld == 1) {
39795 + gotgctl.d32 =
39796 + DWC_READ_REG32(&core_if->
39797 + core_global_regs->
39798 + gotgctl);
39799 + dwc_mdelay(100);
39800 + }
39801 +
39802 + /* Enable Power Down Logic */
39803 + gpwrdn.d32 = 0;
39804 + gpwrdn.b.pmuactv = 1;
39805 + DWC_MODIFY_REG32(&core_if->core_global_regs->
39806 + gpwrdn, 0, gpwrdn.d32);
39807 +
39808 + /* Unmask SRP detected interrupt from Power Down Logic */
39809 + gpwrdn.d32 = 0;
39810 + gpwrdn.b.srp_det_msk = 1;
39811 + DWC_MODIFY_REG32(&core_if->core_global_regs->
39812 + gpwrdn, 0, gpwrdn.d32);
39813 +
39814 + dwc_otg_adp_probe_start(core_if);
39815 + }
39816 +#endif
39817 + break;
39818 + case UHF_PORT_POWER:
39819 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39820 + "SetPortFeature - USB_PORT_FEAT_POWER\n");
39821 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
39822 + hprt0.b.prtpwr = 1;
39823 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39824 + break;
39825 + case UHF_PORT_RESET:
39826 + if ((core_if->power_down == 2)
39827 + && (core_if->hibernation_suspend == 1)) {
39828 + /* If we are going to exit from Hibernated
39829 + * state via USB RESET.
39830 + */
39831 + dwc_otg_host_hibernation_restore(core_if, 0, 1);
39832 + } else {
39833 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
39834 +
39835 + DWC_DEBUGPL(DBG_HCD,
39836 + "DWC OTG HCD HUB CONTROL - "
39837 + "SetPortFeature - USB_PORT_FEAT_RESET\n");
39838 + {
39839 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
39840 + pcgcctl.b.enbl_sleep_gating = 1;
39841 + pcgcctl.b.stoppclk = 1;
39842 + DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
39843 + DWC_WRITE_REG32(core_if->pcgcctl, 0);
39844 + }
39845 +#ifdef CONFIG_USB_DWC_OTG_LPM
39846 + {
39847 + glpmcfg_data_t lpmcfg;
39848 + lpmcfg.d32 =
39849 + DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
39850 + if (lpmcfg.b.prt_sleep_sts) {
39851 + lpmcfg.b.en_utmi_sleep = 0;
39852 + lpmcfg.b.hird_thres &= (~(1 << 4));
39853 + DWC_WRITE_REG32
39854 + (&core_if->core_global_regs->glpmcfg,
39855 + lpmcfg.d32);
39856 + dwc_mdelay(1);
39857 + }
39858 + }
39859 +#endif
39860 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
39861 + /* Clear suspend bit if resetting from suspended state. */
39862 + hprt0.b.prtsusp = 0;
39863 + /* When B-Host the Port reset bit is set in
39864 + * the Start HCD Callback function, so that
39865 + * the reset is started within 1ms of the HNP
39866 + * success interrupt. */
39867 + if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) {
39868 + hprt0.b.prtpwr = 1;
39869 + hprt0.b.prtrst = 1;
39870 + DWC_PRINTF("Indeed it is in host mode hprt0 = %08x\n",hprt0.d32);
39871 + DWC_WRITE_REG32(core_if->host_if->hprt0,
39872 + hprt0.d32);
39873 + }
39874 + /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
39875 + dwc_mdelay(60);
39876 + hprt0.b.prtrst = 0;
39877 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39878 + core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */
39879 + }
39880 + break;
39881 +#ifdef DWC_HS_ELECT_TST
39882 + case UHF_PORT_TEST:
39883 + {
39884 + uint32_t t;
39885 + gintmsk_data_t gintmsk;
39886 +
39887 + t = (wIndex >> 8); /* MSB wIndex USB */
39888 + DWC_DEBUGPL(DBG_HCD,
39889 + "DWC OTG HCD HUB CONTROL - "
39890 + "SetPortFeature - USB_PORT_FEAT_TEST %d\n",
39891 + t);
39892 + DWC_WARN("USB_PORT_FEAT_TEST %d\n", t);
39893 + if (t < 6) {
39894 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
39895 + hprt0.b.prttstctl = t;
39896 + DWC_WRITE_REG32(core_if->host_if->hprt0,
39897 + hprt0.d32);
39898 + } else {
39899 + /* Setup global vars with reg addresses (quick and
39900 + * dirty hack, should be cleaned up)
39901 + */
39902 + global_regs = core_if->core_global_regs;
39903 + hc_global_regs =
39904 + core_if->host_if->host_global_regs;
39905 + hc_regs =
39906 + (dwc_otg_hc_regs_t *) ((char *)
39907 + global_regs +
39908 + 0x500);
39909 + data_fifo =
39910 + (uint32_t *) ((char *)global_regs +
39911 + 0x1000);
39912 +
39913 + if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
39914 + /* Save current interrupt mask */
39915 + gintmsk.d32 =
39916 + DWC_READ_REG32
39917 + (&global_regs->gintmsk);
39918 +
39919 + /* Disable all interrupts while we muck with
39920 + * the hardware directly
39921 + */
39922 + DWC_WRITE_REG32(&global_regs->gintmsk, 0);
39923 +
39924 + /* 15 second delay per the test spec */
39925 + dwc_mdelay(15000);
39926 +
39927 + /* Drive suspend on the root port */
39928 + hprt0.d32 =
39929 + dwc_otg_read_hprt0(core_if);
39930 + hprt0.b.prtsusp = 1;
39931 + hprt0.b.prtres = 0;
39932 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39933 +
39934 + /* 15 second delay per the test spec */
39935 + dwc_mdelay(15000);
39936 +
39937 + /* Drive resume on the root port */
39938 + hprt0.d32 =
39939 + dwc_otg_read_hprt0(core_if);
39940 + hprt0.b.prtsusp = 0;
39941 + hprt0.b.prtres = 1;
39942 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39943 + dwc_mdelay(100);
39944 +
39945 + /* Clear the resume bit */
39946 + hprt0.b.prtres = 0;
39947 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39948 +
39949 + /* Restore interrupts */
39950 + DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
39951 + } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
39952 + /* Save current interrupt mask */
39953 + gintmsk.d32 =
39954 + DWC_READ_REG32
39955 + (&global_regs->gintmsk);
39956 +
39957 + /* Disable all interrupts while we muck with
39958 + * the hardware directly
39959 + */
39960 + DWC_WRITE_REG32(&global_regs->gintmsk, 0);
39961 +
39962 + /* 15 second delay per the test spec */
39963 + dwc_mdelay(15000);
39964 +
39965 + /* Send the Setup packet */
39966 + do_setup();
39967 +
39968 + /* 15 second delay so nothing else happens for awhile */
39969 + dwc_mdelay(15000);
39970 +
39971 + /* Restore interrupts */
39972 + DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
39973 + } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
39974 + /* Save current interrupt mask */
39975 + gintmsk.d32 =
39976 + DWC_READ_REG32
39977 + (&global_regs->gintmsk);
39978 +
39979 + /* Disable all interrupts while we muck with
39980 + * the hardware directly
39981 + */
39982 + DWC_WRITE_REG32(&global_regs->gintmsk, 0);
39983 +
39984 + /* Send the Setup packet */
39985 + do_setup();
39986 +
39987 + /* 15 second delay so nothing else happens for awhile */
39988 + dwc_mdelay(15000);
39989 +
39990 + /* Send the In and Ack packets */
39991 + do_in_ack();
39992 +
39993 + /* 15 second delay so nothing else happens for awhile */
39994 + dwc_mdelay(15000);
39995 +
39996 + /* Restore interrupts */
39997 + DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
39998 + }
39999 + }
40000 + break;
40001 + }
40002 +#endif /* DWC_HS_ELECT_TST */
40003 +
40004 + case UHF_PORT_INDICATOR:
40005 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
40006 + "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
40007 + /* Not supported */
40008 + break;
40009 + default:
40010 + retval = -DWC_E_INVALID;
40011 + DWC_ERROR("DWC OTG HCD - "
40012 + "SetPortFeature request %xh "
40013 + "unknown or unsupported\n", wValue);
40014 + break;
40015 + }
40016 + break;
40017 +#ifdef CONFIG_USB_DWC_OTG_LPM
40018 + case UCR_SET_AND_TEST_PORT_FEATURE:
40019 + if (wValue != UHF_PORT_L1) {
40020 + goto error;
40021 + }
40022 + {
40023 + int portnum, hird, devaddr, remwake;
40024 + glpmcfg_data_t lpmcfg;
40025 + uint32_t time_usecs;
40026 + gintsts_data_t gintsts;
40027 + gintmsk_data_t gintmsk;
40028 +
40029 + if (!dwc_otg_get_param_lpm_enable(core_if)) {
40030 + goto error;
40031 + }
40032 + if (wValue != UHF_PORT_L1 || wLength != 1) {
40033 + goto error;
40034 + }
40035 + /* Check if the port currently is in SLEEP state */
40036 + lpmcfg.d32 =
40037 + DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
40038 + if (lpmcfg.b.prt_sleep_sts) {
40039 + DWC_INFO("Port is already in sleep mode\n");
40040 + buf[0] = 0; /* Return success */
40041 + break;
40042 + }
40043 +
40044 + portnum = wIndex & 0xf;
40045 + hird = (wIndex >> 4) & 0xf;
40046 + devaddr = (wIndex >> 8) & 0x7f;
40047 + remwake = (wIndex >> 15);
40048 +
40049 + if (portnum != 1) {
40050 + retval = -DWC_E_INVALID;
40051 + DWC_WARN
40052 + ("Wrong port number(%d) in SetandTestPortFeature request\n",
40053 + portnum);
40054 + break;
40055 + }
40056 +
40057 + DWC_PRINTF
40058 + ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n",
40059 + portnum, hird, devaddr, remwake);
40060 + /* Disable LPM interrupt */
40061 + gintmsk.d32 = 0;
40062 + gintmsk.b.lpmtranrcvd = 1;
40063 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
40064 + gintmsk.d32, 0);
40065 +
40066 + if (dwc_otg_hcd_send_lpm
40067 + (dwc_otg_hcd, devaddr, hird, remwake)) {
40068 + retval = -DWC_E_INVALID;
40069 + break;
40070 + }
40071 +
40072 + time_usecs = 10 * (lpmcfg.b.retry_count + 1);
40073 + /* We will consider timeout if time_usecs microseconds pass,
40074 + * and we don't receive LPM transaction status.
40075 + * After receiving non-error responce(ACK/NYET/STALL) from device,
40076 + * core will set lpmtranrcvd bit.
40077 + */
40078 + do {
40079 + gintsts.d32 =
40080 + DWC_READ_REG32(&core_if->core_global_regs->gintsts);
40081 + if (gintsts.b.lpmtranrcvd) {
40082 + break;
40083 + }
40084 + dwc_udelay(1);
40085 + } while (--time_usecs);
40086 + /* lpm_int bit will be cleared in LPM interrupt handler */
40087 +
40088 + /* Now fill status
40089 + * 0x00 - Success
40090 + * 0x10 - NYET
40091 + * 0x11 - Timeout
40092 + */
40093 + if (!gintsts.b.lpmtranrcvd) {
40094 + buf[0] = 0x3; /* Completion code is Timeout */
40095 + dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);
40096 + } else {
40097 + lpmcfg.d32 =
40098 + DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
40099 + if (lpmcfg.b.lpm_resp == 0x3) {
40100 + /* ACK responce from the device */
40101 + buf[0] = 0x00; /* Success */
40102 + } else if (lpmcfg.b.lpm_resp == 0x2) {
40103 + /* NYET responce from the device */
40104 + buf[0] = 0x2;
40105 + } else {
40106 + /* Otherwise responce with Timeout */
40107 + buf[0] = 0x3;
40108 + }
40109 + }
40110 + DWC_PRINTF("Device responce to LPM trans is %x\n",
40111 + lpmcfg.b.lpm_resp);
40112 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,
40113 + gintmsk.d32);
40114 +
40115 + break;
40116 + }
40117 +#endif /* CONFIG_USB_DWC_OTG_LPM */
40118 + default:
40119 +error:
40120 + retval = -DWC_E_INVALID;
40121 + DWC_WARN("DWC OTG HCD - "
40122 + "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
40123 + typeReq, wIndex, wValue);
40124 + break;
40125 + }
40126 +
40127 + return retval;
40128 +}
40129 +
40130 +#ifdef CONFIG_USB_DWC_OTG_LPM
40131 +/** Returns index of host channel to perform LPM transaction. */
40132 +int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd, uint8_t devaddr)
40133 +{
40134 + dwc_otg_core_if_t *core_if = hcd->core_if;
40135 + dwc_hc_t *hc;
40136 + hcchar_data_t hcchar;
40137 + gintmsk_data_t gintmsk = {.d32 = 0 };
40138 +
40139 + if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
40140 + DWC_PRINTF("No free channel to select for LPM transaction\n");
40141 + return -1;
40142 + }
40143 +
40144 + hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
40145 +
40146 + /* Mask host channel interrupts. */
40147 + gintmsk.b.hcintr = 1;
40148 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
40149 +
40150 + /* Fill fields that core needs for LPM transaction */
40151 + hcchar.b.devaddr = devaddr;
40152 + hcchar.b.epnum = 0;
40153 + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
40154 + hcchar.b.mps = 64;
40155 + hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
40156 + hcchar.b.epdir = 0; /* OUT */
40157 + DWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar,
40158 + hcchar.d32);
40159 +
40160 + /* Remove the host channel from the free list. */
40161 + DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
40162 +
40163 + DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr);
40164 +
40165 + return hc->hc_num;
40166 +}
40167 +
40168 +/** Release hc after performing LPM transaction */
40169 +void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd)
40170 +{
40171 + dwc_hc_t *hc;
40172 + glpmcfg_data_t lpmcfg;
40173 + uint8_t hc_num;
40174 +
40175 + lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
40176 + hc_num = lpmcfg.b.lpm_chan_index;
40177 +
40178 + hc = hcd->hc_ptr_array[hc_num];
40179 +
40180 + DWC_PRINTF("Freeing channel %d after LPM\n", hc_num);
40181 + /* Return host channel to free list */
40182 + DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
40183 +}
40184 +
40185 +int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr, uint8_t hird,
40186 + uint8_t bRemoteWake)
40187 +{
40188 + glpmcfg_data_t lpmcfg;
40189 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
40190 + int channel;
40191 +
40192 + channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);
40193 + if (channel < 0) {
40194 + return channel;
40195 + }
40196 +
40197 + pcgcctl.b.enbl_sleep_gating = 1;
40198 + DWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32);
40199 +
40200 + /* Read LPM config register */
40201 + lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
40202 +
40203 + /* Program LPM transaction fields */
40204 + lpmcfg.b.rem_wkup_en = bRemoteWake;
40205 + lpmcfg.b.hird = hird;
40206 + lpmcfg.b.hird_thres = 0x1c;
40207 + lpmcfg.b.lpm_chan_index = channel;
40208 + lpmcfg.b.en_utmi_sleep = 1;
40209 + /* Program LPM config register */
40210 + DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
40211 +
40212 + /* Send LPM transaction */
40213 + lpmcfg.b.send_lpm = 1;
40214 + DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
40215 +
40216 + return 0;
40217 +}
40218 +
40219 +#endif /* CONFIG_USB_DWC_OTG_LPM */
40220 +
40221 +int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port)
40222 +{
40223 + int retval;
40224 +
40225 + if (port != 1) {
40226 + return -DWC_E_INVALID;
40227 + }
40228 +
40229 + retval = (hcd->flags.b.port_connect_status_change ||
40230 + hcd->flags.b.port_reset_change ||
40231 + hcd->flags.b.port_enable_change ||
40232 + hcd->flags.b.port_suspend_change ||
40233 + hcd->flags.b.port_over_current_change);
40234 +#ifdef DEBUG
40235 + if (retval) {
40236 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
40237 + " Root port status changed\n");
40238 + DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n",
40239 + hcd->flags.b.port_connect_status_change);
40240 + DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n",
40241 + hcd->flags.b.port_reset_change);
40242 + DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n",
40243 + hcd->flags.b.port_enable_change);
40244 + DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n",
40245 + hcd->flags.b.port_suspend_change);
40246 + DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n",
40247 + hcd->flags.b.port_over_current_change);
40248 + }
40249 +#endif
40250 + return retval;
40251 +}
40252 +
40253 +int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * dwc_otg_hcd)
40254 +{
40255 + hfnum_data_t hfnum;
40256 + hfnum.d32 =
40257 + DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->
40258 + hfnum);
40259 +
40260 +#ifdef DEBUG_SOF
40261 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n",
40262 + hfnum.b.frnum);
40263 +#endif
40264 + return hfnum.b.frnum;
40265 +}
40266 +
40267 +int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
40268 + struct dwc_otg_hcd_function_ops *fops)
40269 +{
40270 + int retval = 0;
40271 +
40272 + hcd->fops = fops;
40273 + if (!dwc_otg_is_device_mode(hcd->core_if) &&
40274 + (!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) {
40275 + dwc_otg_hcd_reinit(hcd);
40276 + } else {
40277 + retval = -DWC_E_NO_DEVICE;
40278 + }
40279 +
40280 + return retval;
40281 +}
40282 +
40283 +void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd)
40284 +{
40285 + return hcd->priv;
40286 +}
40287 +
40288 +void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data)
40289 +{
40290 + hcd->priv = priv_data;
40291 +}
40292 +
40293 +uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd)
40294 +{
40295 + return hcd->otg_port;
40296 +}
40297 +
40298 +uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd)
40299 +{
40300 + uint32_t is_b_host;
40301 + if (hcd->core_if->op_state == B_HOST) {
40302 + is_b_host = 1;
40303 + } else {
40304 + is_b_host = 0;
40305 + }
40306 +
40307 + return is_b_host;
40308 +}
40309 +
40310 +dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
40311 + int iso_desc_count, int atomic_alloc)
40312 +{
40313 + dwc_otg_hcd_urb_t *dwc_otg_urb;
40314 + uint32_t size;
40315 +
40316 + size =
40317 + sizeof(*dwc_otg_urb) +
40318 + iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc);
40319 + if (atomic_alloc)
40320 + dwc_otg_urb = DWC_ALLOC_ATOMIC(size);
40321 + else
40322 + dwc_otg_urb = DWC_ALLOC(size);
40323 +
40324 + if (dwc_otg_urb)
40325 + dwc_otg_urb->packet_count = iso_desc_count;
40326 + else {
40327 + DWC_ERROR("**** DWC OTG HCD URB alloc - "
40328 + "%salloc of %db failed\n",
40329 + atomic_alloc?"atomic ":"", size);
40330 + }
40331 + return dwc_otg_urb;
40332 +}
40333 +
40334 +void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * dwc_otg_urb,
40335 + uint8_t dev_addr, uint8_t ep_num,
40336 + uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
40337 +{
40338 + dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num,
40339 + ep_type, ep_dir, mps);
40340 +#if 0
40341 + DWC_PRINTF
40342 + ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n",
40343 + dev_addr, ep_num, ep_dir, ep_type, mps);
40344 +#endif
40345 +}
40346 +
40347 +void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
40348 + void *urb_handle, void *buf, dwc_dma_t dma,
40349 + uint32_t buflen, void *setup_packet,
40350 + dwc_dma_t setup_dma, uint32_t flags,
40351 + uint16_t interval)
40352 +{
40353 + dwc_otg_urb->priv = urb_handle;
40354 + dwc_otg_urb->buf = buf;
40355 + dwc_otg_urb->dma = dma;
40356 + dwc_otg_urb->length = buflen;
40357 + dwc_otg_urb->setup_packet = setup_packet;
40358 + dwc_otg_urb->setup_dma = setup_dma;
40359 + dwc_otg_urb->flags = flags;
40360 + dwc_otg_urb->interval = interval;
40361 + dwc_otg_urb->status = -DWC_E_IN_PROGRESS;
40362 +}
40363 +
40364 +uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb)
40365 +{
40366 + return dwc_otg_urb->status;
40367 +}
40368 +
40369 +uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t * dwc_otg_urb)
40370 +{
40371 + return dwc_otg_urb->actual_length;
40372 +}
40373 +
40374 +uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t * dwc_otg_urb)
40375 +{
40376 + return dwc_otg_urb->error_count;
40377 +}
40378 +
40379 +void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
40380 + int desc_num, uint32_t offset,
40381 + uint32_t length)
40382 +{
40383 + dwc_otg_urb->iso_descs[desc_num].offset = offset;
40384 + dwc_otg_urb->iso_descs[desc_num].length = length;
40385 +}
40386 +
40387 +uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t * dwc_otg_urb,
40388 + int desc_num)
40389 +{
40390 + return dwc_otg_urb->iso_descs[desc_num].status;
40391 +}
40392 +
40393 +uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
40394 + dwc_otg_urb, int desc_num)
40395 +{
40396 + return dwc_otg_urb->iso_descs[desc_num].actual_length;
40397 +}
40398 +
40399 +int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd, void *ep_handle)
40400 +{
40401 + int allocated = 0;
40402 + dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
40403 +
40404 + if (qh) {
40405 + if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
40406 + allocated = 1;
40407 + }
40408 + }
40409 + return allocated;
40410 +}
40411 +
40412 +int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle)
40413 +{
40414 + dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
40415 + int freed = 0;
40416 + DWC_ASSERT(qh, "qh is not allocated\n");
40417 +
40418 + if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
40419 + freed = 1;
40420 + }
40421 +
40422 + return freed;
40423 +}
40424 +
40425 +uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd, void *ep_handle)
40426 +{
40427 + dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
40428 + DWC_ASSERT(qh, "qh is not allocated\n");
40429 + return qh->usecs;
40430 +}
40431 +
40432 +void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd)
40433 +{
40434 +#ifdef DEBUG
40435 + int num_channels;
40436 + int i;
40437 + gnptxsts_data_t np_tx_status;
40438 + hptxsts_data_t p_tx_status;
40439 +
40440 + num_channels = hcd->core_if->core_params->host_channels;
40441 + DWC_PRINTF("\n");
40442 + DWC_PRINTF
40443 + ("************************************************************\n");
40444 + DWC_PRINTF("HCD State:\n");
40445 + DWC_PRINTF(" Num channels: %d\n", num_channels);
40446 + for (i = 0; i < num_channels; i++) {
40447 + dwc_hc_t *hc = hcd->hc_ptr_array[i];
40448 + DWC_PRINTF(" Channel %d:\n", i);
40449 + DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
40450 + hc->dev_addr, hc->ep_num, hc->ep_is_in);
40451 + DWC_PRINTF(" speed: %d\n", hc->speed);
40452 + DWC_PRINTF(" ep_type: %d\n", hc->ep_type);
40453 + DWC_PRINTF(" max_packet: %d\n", hc->max_packet);
40454 + DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start);
40455 + DWC_PRINTF(" multi_count: %d\n", hc->multi_count);
40456 + DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started);
40457 + DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff);
40458 + DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len);
40459 + DWC_PRINTF(" xfer_count: %d\n", hc->xfer_count);
40460 + DWC_PRINTF(" halt_on_queue: %d\n", hc->halt_on_queue);
40461 + DWC_PRINTF(" halt_pending: %d\n", hc->halt_pending);
40462 + DWC_PRINTF(" halt_status: %d\n", hc->halt_status);
40463 + DWC_PRINTF(" do_split: %d\n", hc->do_split);
40464 + DWC_PRINTF(" complete_split: %d\n", hc->complete_split);
40465 + DWC_PRINTF(" hub_addr: %d\n", hc->hub_addr);
40466 + DWC_PRINTF(" port_addr: %d\n", hc->port_addr);
40467 + DWC_PRINTF(" xact_pos: %d\n", hc->xact_pos);
40468 + DWC_PRINTF(" requests: %d\n", hc->requests);
40469 + DWC_PRINTF(" qh: %p\n", hc->qh);
40470 + if (hc->xfer_started) {
40471 + hfnum_data_t hfnum;
40472 + hcchar_data_t hcchar;
40473 + hctsiz_data_t hctsiz;
40474 + hcint_data_t hcint;
40475 + hcintmsk_data_t hcintmsk;
40476 + hfnum.d32 =
40477 + DWC_READ_REG32(&hcd->core_if->
40478 + host_if->host_global_regs->hfnum);
40479 + hcchar.d32 =
40480 + DWC_READ_REG32(&hcd->core_if->host_if->
40481 + hc_regs[i]->hcchar);
40482 + hctsiz.d32 =
40483 + DWC_READ_REG32(&hcd->core_if->host_if->
40484 + hc_regs[i]->hctsiz);
40485 + hcint.d32 =
40486 + DWC_READ_REG32(&hcd->core_if->host_if->
40487 + hc_regs[i]->hcint);
40488 + hcintmsk.d32 =
40489 + DWC_READ_REG32(&hcd->core_if->host_if->
40490 + hc_regs[i]->hcintmsk);
40491 + DWC_PRINTF(" hfnum: 0x%08x\n", hfnum.d32);
40492 + DWC_PRINTF(" hcchar: 0x%08x\n", hcchar.d32);
40493 + DWC_PRINTF(" hctsiz: 0x%08x\n", hctsiz.d32);
40494 + DWC_PRINTF(" hcint: 0x%08x\n", hcint.d32);
40495 + DWC_PRINTF(" hcintmsk: 0x%08x\n", hcintmsk.d32);
40496 + }
40497 + if (hc->xfer_started && hc->qh) {
40498 + dwc_otg_qtd_t *qtd;
40499 + dwc_otg_hcd_urb_t *urb;
40500 +
40501 + DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list, qtd_list_entry) {
40502 + if (!qtd->in_process)
40503 + break;
40504 +
40505 + urb = qtd->urb;
40506 + DWC_PRINTF(" URB Info:\n");
40507 + DWC_PRINTF(" qtd: %p, urb: %p\n", qtd, urb);
40508 + if (urb) {
40509 + DWC_PRINTF(" Dev: %d, EP: %d %s\n",
40510 + dwc_otg_hcd_get_dev_addr(&urb->
40511 + pipe_info),
40512 + dwc_otg_hcd_get_ep_num(&urb->
40513 + pipe_info),
40514 + dwc_otg_hcd_is_pipe_in(&urb->
40515 + pipe_info) ?
40516 + "IN" : "OUT");
40517 + DWC_PRINTF(" Max packet size: %d\n",
40518 + dwc_otg_hcd_get_mps(&urb->
40519 + pipe_info));
40520 + DWC_PRINTF(" transfer_buffer: %p\n",
40521 + urb->buf);
40522 + DWC_PRINTF(" transfer_dma: %p\n",
40523 + (void *)urb->dma);
40524 + DWC_PRINTF(" transfer_buffer_length: %d\n",
40525 + urb->length);
40526 + DWC_PRINTF(" actual_length: %d\n",
40527 + urb->actual_length);
40528 + }
40529 + }
40530 + }
40531 + }
40532 + DWC_PRINTF(" non_periodic_channels: %d\n", hcd->non_periodic_channels);
40533 + DWC_PRINTF(" periodic_channels: %d\n", hcd->periodic_channels);
40534 + DWC_PRINTF(" periodic_usecs: %d\n", hcd->periodic_usecs);
40535 + np_tx_status.d32 =
40536 + DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts);
40537 + DWC_PRINTF(" NP Tx Req Queue Space Avail: %d\n",
40538 + np_tx_status.b.nptxqspcavail);
40539 + DWC_PRINTF(" NP Tx FIFO Space Avail: %d\n",
40540 + np_tx_status.b.nptxfspcavail);
40541 + p_tx_status.d32 =
40542 + DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts);
40543 + DWC_PRINTF(" P Tx Req Queue Space Avail: %d\n",
40544 + p_tx_status.b.ptxqspcavail);
40545 + DWC_PRINTF(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
40546 + dwc_otg_hcd_dump_frrem(hcd);
40547 + dwc_otg_dump_global_registers(hcd->core_if);
40548 + dwc_otg_dump_host_registers(hcd->core_if);
40549 + DWC_PRINTF
40550 + ("************************************************************\n");
40551 + DWC_PRINTF("\n");
40552 +#endif
40553 +}
40554 +
40555 +#ifdef DEBUG
40556 +void dwc_print_setup_data(uint8_t * setup)
40557 +{
40558 + int i;
40559 + if (CHK_DEBUG_LEVEL(DBG_HCD)) {
40560 + DWC_PRINTF("Setup Data = MSB ");
40561 + for (i = 7; i >= 0; i--)
40562 + DWC_PRINTF("%02x ", setup[i]);
40563 + DWC_PRINTF("\n");
40564 + DWC_PRINTF(" bmRequestType Tranfer = %s\n",
40565 + (setup[0] & 0x80) ? "Device-to-Host" :
40566 + "Host-to-Device");
40567 + DWC_PRINTF(" bmRequestType Type = ");
40568 + switch ((setup[0] & 0x60) >> 5) {
40569 + case 0:
40570 + DWC_PRINTF("Standard\n");
40571 + break;
40572 + case 1:
40573 + DWC_PRINTF("Class\n");
40574 + break;
40575 + case 2:
40576 + DWC_PRINTF("Vendor\n");
40577 + break;
40578 + case 3:
40579 + DWC_PRINTF("Reserved\n");
40580 + break;
40581 + }
40582 + DWC_PRINTF(" bmRequestType Recipient = ");
40583 + switch (setup[0] & 0x1f) {
40584 + case 0:
40585 + DWC_PRINTF("Device\n");
40586 + break;
40587 + case 1:
40588 + DWC_PRINTF("Interface\n");
40589 + break;
40590 + case 2:
40591 + DWC_PRINTF("Endpoint\n");
40592 + break;
40593 + case 3:
40594 + DWC_PRINTF("Other\n");
40595 + break;
40596 + default:
40597 + DWC_PRINTF("Reserved\n");
40598 + break;
40599 + }
40600 + DWC_PRINTF(" bRequest = 0x%0x\n", setup[1]);
40601 + DWC_PRINTF(" wValue = 0x%0x\n", *((uint16_t *) & setup[2]));
40602 + DWC_PRINTF(" wIndex = 0x%0x\n", *((uint16_t *) & setup[4]));
40603 + DWC_PRINTF(" wLength = 0x%0x\n\n", *((uint16_t *) & setup[6]));
40604 + }
40605 +}
40606 +#endif
40607 +
40608 +void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd)
40609 +{
40610 +#if 0
40611 + DWC_PRINTF("Frame remaining at SOF:\n");
40612 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
40613 + hcd->frrem_samples, hcd->frrem_accum,
40614 + (hcd->frrem_samples > 0) ?
40615 + hcd->frrem_accum / hcd->frrem_samples : 0);
40616 +
40617 + DWC_PRINTF("\n");
40618 + DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n");
40619 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
40620 + hcd->core_if->hfnum_7_samples,
40621 + hcd->core_if->hfnum_7_frrem_accum,
40622 + (hcd->core_if->hfnum_7_samples >
40623 + 0) ? hcd->core_if->hfnum_7_frrem_accum /
40624 + hcd->core_if->hfnum_7_samples : 0);
40625 + DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n");
40626 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
40627 + hcd->core_if->hfnum_0_samples,
40628 + hcd->core_if->hfnum_0_frrem_accum,
40629 + (hcd->core_if->hfnum_0_samples >
40630 + 0) ? hcd->core_if->hfnum_0_frrem_accum /
40631 + hcd->core_if->hfnum_0_samples : 0);
40632 + DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n");
40633 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
40634 + hcd->core_if->hfnum_other_samples,
40635 + hcd->core_if->hfnum_other_frrem_accum,
40636 + (hcd->core_if->hfnum_other_samples >
40637 + 0) ? hcd->core_if->hfnum_other_frrem_accum /
40638 + hcd->core_if->hfnum_other_samples : 0);
40639 +
40640 + DWC_PRINTF("\n");
40641 + DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n");
40642 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
40643 + hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
40644 + (hcd->hfnum_7_samples_a > 0) ?
40645 + hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0);
40646 + DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n");
40647 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
40648 + hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
40649 + (hcd->hfnum_0_samples_a > 0) ?
40650 + hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0);
40651 + DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n");
40652 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
40653 + hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
40654 + (hcd->hfnum_other_samples_a > 0) ?
40655 + hcd->hfnum_other_frrem_accum_a /
40656 + hcd->hfnum_other_samples_a : 0);
40657 +
40658 + DWC_PRINTF("\n");
40659 + DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n");
40660 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
40661 + hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
40662 + (hcd->hfnum_7_samples_b > 0) ?
40663 + hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0);
40664 + DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n");
40665 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
40666 + hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
40667 + (hcd->hfnum_0_samples_b > 0) ?
40668 + hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0);
40669 + DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n");
40670 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
40671 + hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
40672 + (hcd->hfnum_other_samples_b > 0) ?
40673 + hcd->hfnum_other_frrem_accum_b /
40674 + hcd->hfnum_other_samples_b : 0);
40675 +#endif
40676 +}
40677 +
40678 +#endif /* DWC_DEVICE_ONLY */
40679 --- /dev/null
40680 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.h
40681 @@ -0,0 +1,862 @@
40682 +/* ==========================================================================
40683 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $
40684 + * $Revision: #58 $
40685 + * $Date: 2011/09/15 $
40686 + * $Change: 1846647 $
40687 + *
40688 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
40689 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
40690 + * otherwise expressly agreed to in writing between Synopsys and you.
40691 + *
40692 + * The Software IS NOT an item of Licensed Software or Licensed Product under
40693 + * any End User Software License Agreement or Agreement for Licensed Product
40694 + * with Synopsys or any supplement thereto. You are permitted to use and
40695 + * redistribute this Software in source and binary forms, with or without
40696 + * modification, provided that redistributions of source code must retain this
40697 + * notice. You may not view, use, disclose, copy or distribute this file or
40698 + * any information contained herein except pursuant to this license grant from
40699 + * Synopsys. If you do not agree with this notice, including the disclaimer
40700 + * below, then you are not authorized to use the Software.
40701 + *
40702 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
40703 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
40704 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
40705 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
40706 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
40707 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
40708 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
40709 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
40710 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40711 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
40712 + * DAMAGE.
40713 + * ========================================================================== */
40714 +#ifndef DWC_DEVICE_ONLY
40715 +#ifndef __DWC_HCD_H__
40716 +#define __DWC_HCD_H__
40717 +
40718 +#include "dwc_otg_os_dep.h"
40719 +#include "usb.h"
40720 +#include "dwc_otg_hcd_if.h"
40721 +#include "dwc_otg_core_if.h"
40722 +#include "dwc_list.h"
40723 +#include "dwc_otg_cil.h"
40724 +#include "dwc_otg_fiq_fsm.h"
40725 +
40726 +
40727 +/**
40728 + * @file
40729 + *
40730 + * This file contains the structures, constants, and interfaces for
40731 + * the Host Contoller Driver (HCD).
40732 + *
40733 + * The Host Controller Driver (HCD) is responsible for translating requests
40734 + * from the USB Driver into the appropriate actions on the DWC_otg controller.
40735 + * It isolates the USBD from the specifics of the controller by providing an
40736 + * API to the USBD.
40737 + */
40738 +
40739 +struct dwc_otg_hcd_pipe_info {
40740 + uint8_t dev_addr;
40741 + uint8_t ep_num;
40742 + uint8_t pipe_type;
40743 + uint8_t pipe_dir;
40744 + uint16_t mps;
40745 +};
40746 +
40747 +struct dwc_otg_hcd_iso_packet_desc {
40748 + uint32_t offset;
40749 + uint32_t length;
40750 + uint32_t actual_length;
40751 + uint32_t status;
40752 +};
40753 +
40754 +struct dwc_otg_qtd;
40755 +
40756 +struct dwc_otg_hcd_urb {
40757 + void *priv;
40758 + struct dwc_otg_qtd *qtd;
40759 + void *buf;
40760 + dwc_dma_t dma;
40761 + void *setup_packet;
40762 + dwc_dma_t setup_dma;
40763 + uint32_t length;
40764 + uint32_t actual_length;
40765 + uint32_t status;
40766 + uint32_t error_count;
40767 + uint32_t packet_count;
40768 + uint32_t flags;
40769 + uint16_t interval;
40770 + struct dwc_otg_hcd_pipe_info pipe_info;
40771 + struct dwc_otg_hcd_iso_packet_desc iso_descs[0];
40772 +};
40773 +
40774 +static inline uint8_t dwc_otg_hcd_get_ep_num(struct dwc_otg_hcd_pipe_info *pipe)
40775 +{
40776 + return pipe->ep_num;
40777 +}
40778 +
40779 +static inline uint8_t dwc_otg_hcd_get_pipe_type(struct dwc_otg_hcd_pipe_info
40780 + *pipe)
40781 +{
40782 + return pipe->pipe_type;
40783 +}
40784 +
40785 +static inline uint16_t dwc_otg_hcd_get_mps(struct dwc_otg_hcd_pipe_info *pipe)
40786 +{
40787 + return pipe->mps;
40788 +}
40789 +
40790 +static inline uint8_t dwc_otg_hcd_get_dev_addr(struct dwc_otg_hcd_pipe_info
40791 + *pipe)
40792 +{
40793 + return pipe->dev_addr;
40794 +}
40795 +
40796 +static inline uint8_t dwc_otg_hcd_is_pipe_isoc(struct dwc_otg_hcd_pipe_info
40797 + *pipe)
40798 +{
40799 + return (pipe->pipe_type == UE_ISOCHRONOUS);
40800 +}
40801 +
40802 +static inline uint8_t dwc_otg_hcd_is_pipe_int(struct dwc_otg_hcd_pipe_info
40803 + *pipe)
40804 +{
40805 + return (pipe->pipe_type == UE_INTERRUPT);
40806 +}
40807 +
40808 +static inline uint8_t dwc_otg_hcd_is_pipe_bulk(struct dwc_otg_hcd_pipe_info
40809 + *pipe)
40810 +{
40811 + return (pipe->pipe_type == UE_BULK);
40812 +}
40813 +
40814 +static inline uint8_t dwc_otg_hcd_is_pipe_control(struct dwc_otg_hcd_pipe_info
40815 + *pipe)
40816 +{
40817 + return (pipe->pipe_type == UE_CONTROL);
40818 +}
40819 +
40820 +static inline uint8_t dwc_otg_hcd_is_pipe_in(struct dwc_otg_hcd_pipe_info *pipe)
40821 +{
40822 + return (pipe->pipe_dir == UE_DIR_IN);
40823 +}
40824 +
40825 +static inline uint8_t dwc_otg_hcd_is_pipe_out(struct dwc_otg_hcd_pipe_info
40826 + *pipe)
40827 +{
40828 + return (!dwc_otg_hcd_is_pipe_in(pipe));
40829 +}
40830 +
40831 +static inline void dwc_otg_hcd_fill_pipe(struct dwc_otg_hcd_pipe_info *pipe,
40832 + uint8_t devaddr, uint8_t ep_num,
40833 + uint8_t pipe_type, uint8_t pipe_dir,
40834 + uint16_t mps)
40835 +{
40836 + pipe->dev_addr = devaddr;
40837 + pipe->ep_num = ep_num;
40838 + pipe->pipe_type = pipe_type;
40839 + pipe->pipe_dir = pipe_dir;
40840 + pipe->mps = mps;
40841 +}
40842 +
40843 +/**
40844 + * Phases for control transfers.
40845 + */
40846 +typedef enum dwc_otg_control_phase {
40847 + DWC_OTG_CONTROL_SETUP,
40848 + DWC_OTG_CONTROL_DATA,
40849 + DWC_OTG_CONTROL_STATUS
40850 +} dwc_otg_control_phase_e;
40851 +
40852 +/** Transaction types. */
40853 +typedef enum dwc_otg_transaction_type {
40854 + DWC_OTG_TRANSACTION_NONE = 0,
40855 + DWC_OTG_TRANSACTION_PERIODIC = 1,
40856 + DWC_OTG_TRANSACTION_NON_PERIODIC = 2,
40857 + DWC_OTG_TRANSACTION_ALL = DWC_OTG_TRANSACTION_PERIODIC + DWC_OTG_TRANSACTION_NON_PERIODIC
40858 +} dwc_otg_transaction_type_e;
40859 +
40860 +struct dwc_otg_qh;
40861 +
40862 +/**
40863 + * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
40864 + * interrupt, or isochronous transfer. A single QTD is created for each URB
40865 + * (of one of these types) submitted to the HCD. The transfer associated with
40866 + * a QTD may require one or multiple transactions.
40867 + *
40868 + * A QTD is linked to a Queue Head, which is entered in either the
40869 + * non-periodic or periodic schedule for execution. When a QTD is chosen for
40870 + * execution, some or all of its transactions may be executed. After
40871 + * execution, the state of the QTD is updated. The QTD may be retired if all
40872 + * its transactions are complete or if an error occurred. Otherwise, it
40873 + * remains in the schedule so more transactions can be executed later.
40874 + */
40875 +typedef struct dwc_otg_qtd {
40876 + /**
40877 + * Determines the PID of the next data packet for the data phase of
40878 + * control transfers. Ignored for other transfer types.<br>
40879 + * One of the following values:
40880 + * - DWC_OTG_HC_PID_DATA0
40881 + * - DWC_OTG_HC_PID_DATA1
40882 + */
40883 + uint8_t data_toggle;
40884 +
40885 + /** Current phase for control transfers (Setup, Data, or Status). */
40886 + dwc_otg_control_phase_e control_phase;
40887 +
40888 + /** Keep track of the current split type
40889 + * for FS/LS endpoints on a HS Hub */
40890 + uint8_t complete_split;
40891 +
40892 + /** How many bytes transferred during SSPLIT OUT */
40893 + uint32_t ssplit_out_xfer_count;
40894 +
40895 + /**
40896 + * Holds the number of bus errors that have occurred for a transaction
40897 + * within this transfer.
40898 + */
40899 + uint8_t error_count;
40900 +
40901 + /**
40902 + * Index of the next frame descriptor for an isochronous transfer. A
40903 + * frame descriptor describes the buffer position and length of the
40904 + * data to be transferred in the next scheduled (micro)frame of an
40905 + * isochronous transfer. It also holds status for that transaction.
40906 + * The frame index starts at 0.
40907 + */
40908 + uint16_t isoc_frame_index;
40909 +
40910 + /** Position of the ISOC split on full/low speed */
40911 + uint8_t isoc_split_pos;
40912 +
40913 + /** Position of the ISOC split in the buffer for the current frame */
40914 + uint16_t isoc_split_offset;
40915 +
40916 + /** URB for this transfer */
40917 + struct dwc_otg_hcd_urb *urb;
40918 +
40919 + struct dwc_otg_qh *qh;
40920 +
40921 + /** This list of QTDs */
40922 + DWC_CIRCLEQ_ENTRY(dwc_otg_qtd) qtd_list_entry;
40923 +
40924 + /** Indicates if this QTD is currently processed by HW. */
40925 + uint8_t in_process;
40926 +
40927 + /** Number of DMA descriptors for this QTD */
40928 + uint8_t n_desc;
40929 +
40930 + /**
40931 + * Last activated frame(packet) index.
40932 + * Used in Descriptor DMA mode only.
40933 + */
40934 + uint16_t isoc_frame_index_last;
40935 +
40936 +} dwc_otg_qtd_t;
40937 +
40938 +DWC_CIRCLEQ_HEAD(dwc_otg_qtd_list, dwc_otg_qtd);
40939 +
40940 +/**
40941 + * A Queue Head (QH) holds the static characteristics of an endpoint and
40942 + * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
40943 + * be entered in either the non-periodic or periodic schedule.
40944 + */
40945 +typedef struct dwc_otg_qh {
40946 + /**
40947 + * Endpoint type.
40948 + * One of the following values:
40949 + * - UE_CONTROL
40950 + * - UE_BULK
40951 + * - UE_INTERRUPT
40952 + * - UE_ISOCHRONOUS
40953 + */
40954 + uint8_t ep_type;
40955 + uint8_t ep_is_in;
40956 +
40957 + /** wMaxPacketSize Field of Endpoint Descriptor. */
40958 + uint16_t maxp;
40959 +
40960 + /**
40961 + * Device speed.
40962 + * One of the following values:
40963 + * - DWC_OTG_EP_SPEED_LOW
40964 + * - DWC_OTG_EP_SPEED_FULL
40965 + * - DWC_OTG_EP_SPEED_HIGH
40966 + */
40967 + uint8_t dev_speed;
40968 +
40969 + /**
40970 + * Determines the PID of the next data packet for non-control
40971 + * transfers. Ignored for control transfers.<br>
40972 + * One of the following values:
40973 + * - DWC_OTG_HC_PID_DATA0
40974 + * - DWC_OTG_HC_PID_DATA1
40975 + */
40976 + uint8_t data_toggle;
40977 +
40978 + /** Ping state if 1. */
40979 + uint8_t ping_state;
40980 +
40981 + /**
40982 + * List of QTDs for this QH.
40983 + */
40984 + struct dwc_otg_qtd_list qtd_list;
40985 +
40986 + /** Host channel currently processing transfers for this QH. */
40987 + struct dwc_hc *channel;
40988 +
40989 + /** Full/low speed endpoint on high-speed hub requires split. */
40990 + uint8_t do_split;
40991 +
40992 + /** @name Periodic schedule information */
40993 + /** @{ */
40994 +
40995 + /** Bandwidth in microseconds per (micro)frame. */
40996 + uint16_t usecs;
40997 +
40998 + /** Interval between transfers in (micro)frames. */
40999 + uint16_t interval;
41000 +
41001 + /**
41002 + * (micro)frame to initialize a periodic transfer. The transfer
41003 + * executes in the following (micro)frame.
41004 + */
41005 + uint16_t sched_frame;
41006 +
41007 + /*
41008 + ** Frame a NAK was received on this queue head, used to minimise NAK retransmission
41009 + */
41010 + uint16_t nak_frame;
41011 +
41012 + /** (micro)frame at which last start split was initialized. */
41013 + uint16_t start_split_frame;
41014 +
41015 + /** @} */
41016 +
41017 + /**
41018 + * Used instead of original buffer if
41019 + * it(physical address) is not dword-aligned.
41020 + */
41021 + uint8_t *dw_align_buf;
41022 + dwc_dma_t dw_align_buf_dma;
41023 +
41024 + /** Entry for QH in either the periodic or non-periodic schedule. */
41025 + dwc_list_link_t qh_list_entry;
41026 +
41027 + /** @name Descriptor DMA support */
41028 + /** @{ */
41029 +
41030 + /** Descriptor List. */
41031 + dwc_otg_host_dma_desc_t *desc_list;
41032 +
41033 + /** Descriptor List physical address. */
41034 + dwc_dma_t desc_list_dma;
41035 +
41036 + /**
41037 + * Xfer Bytes array.
41038 + * Each element corresponds to a descriptor and indicates
41039 + * original XferSize size value for the descriptor.
41040 + */
41041 + uint32_t *n_bytes;
41042 +
41043 + /** Actual number of transfer descriptors in a list. */
41044 + uint16_t ntd;
41045 +
41046 + /** First activated isochronous transfer descriptor index. */
41047 + uint8_t td_first;
41048 + /** Last activated isochronous transfer descriptor index. */
41049 + uint8_t td_last;
41050 +
41051 + /** @} */
41052 +
41053 +
41054 + uint16_t speed;
41055 + uint16_t frame_usecs[8];
41056 +
41057 + uint32_t skip_count;
41058 +} dwc_otg_qh_t;
41059 +
41060 +DWC_CIRCLEQ_HEAD(hc_list, dwc_hc);
41061 +
41062 +typedef struct urb_tq_entry {
41063 + struct urb *urb;
41064 + DWC_TAILQ_ENTRY(urb_tq_entry) urb_tq_entries;
41065 +} urb_tq_entry_t;
41066 +
41067 +DWC_TAILQ_HEAD(urb_list, urb_tq_entry);
41068 +
41069 +/**
41070 + * This structure holds the state of the HCD, including the non-periodic and
41071 + * periodic schedules.
41072 + */
41073 +struct dwc_otg_hcd {
41074 + /** The DWC otg device pointer */
41075 + struct dwc_otg_device *otg_dev;
41076 + /** DWC OTG Core Interface Layer */
41077 + dwc_otg_core_if_t *core_if;
41078 +
41079 + /** Function HCD driver callbacks */
41080 + struct dwc_otg_hcd_function_ops *fops;
41081 +
41082 + /** Internal DWC HCD Flags */
41083 + volatile union dwc_otg_hcd_internal_flags {
41084 + uint32_t d32;
41085 + struct {
41086 + unsigned port_connect_status_change:1;
41087 + unsigned port_connect_status:1;
41088 + unsigned port_reset_change:1;
41089 + unsigned port_enable_change:1;
41090 + unsigned port_suspend_change:1;
41091 + unsigned port_over_current_change:1;
41092 + unsigned port_l1_change:1;
41093 + unsigned reserved:26;
41094 + } b;
41095 + } flags;
41096 +
41097 + /**
41098 + * Inactive items in the non-periodic schedule. This is a list of
41099 + * Queue Heads. Transfers associated with these Queue Heads are not
41100 + * currently assigned to a host channel.
41101 + */
41102 + dwc_list_link_t non_periodic_sched_inactive;
41103 +
41104 + /**
41105 + * Active items in the non-periodic schedule. This is a list of
41106 + * Queue Heads. Transfers associated with these Queue Heads are
41107 + * currently assigned to a host channel.
41108 + */
41109 + dwc_list_link_t non_periodic_sched_active;
41110 +
41111 + /**
41112 + * Pointer to the next Queue Head to process in the active
41113 + * non-periodic schedule.
41114 + */
41115 + dwc_list_link_t *non_periodic_qh_ptr;
41116 +
41117 + /**
41118 + * Inactive items in the periodic schedule. This is a list of QHs for
41119 + * periodic transfers that are _not_ scheduled for the next frame.
41120 + * Each QH in the list has an interval counter that determines when it
41121 + * needs to be scheduled for execution. This scheduling mechanism
41122 + * allows only a simple calculation for periodic bandwidth used (i.e.
41123 + * must assume that all periodic transfers may need to execute in the
41124 + * same frame). However, it greatly simplifies scheduling and should
41125 + * be sufficient for the vast majority of OTG hosts, which need to
41126 + * connect to a small number of peripherals at one time.
41127 + *
41128 + * Items move from this list to periodic_sched_ready when the QH
41129 + * interval counter is 0 at SOF.
41130 + */
41131 + dwc_list_link_t periodic_sched_inactive;
41132 +
41133 + /**
41134 + * List of periodic QHs that are ready for execution in the next
41135 + * frame, but have not yet been assigned to host channels.
41136 + *
41137 + * Items move from this list to periodic_sched_assigned as host
41138 + * channels become available during the current frame.
41139 + */
41140 + dwc_list_link_t periodic_sched_ready;
41141 +
41142 + /**
41143 + * List of periodic QHs to be executed in the next frame that are
41144 + * assigned to host channels.
41145 + *
41146 + * Items move from this list to periodic_sched_queued as the
41147 + * transactions for the QH are queued to the DWC_otg controller.
41148 + */
41149 + dwc_list_link_t periodic_sched_assigned;
41150 +
41151 + /**
41152 + * List of periodic QHs that have been queued for execution.
41153 + *
41154 + * Items move from this list to either periodic_sched_inactive or
41155 + * periodic_sched_ready when the channel associated with the transfer
41156 + * is released. If the interval for the QH is 1, the item moves to
41157 + * periodic_sched_ready because it must be rescheduled for the next
41158 + * frame. Otherwise, the item moves to periodic_sched_inactive.
41159 + */
41160 + dwc_list_link_t periodic_sched_queued;
41161 +
41162 + /**
41163 + * Total bandwidth claimed so far for periodic transfers. This value
41164 + * is in microseconds per (micro)frame. The assumption is that all
41165 + * periodic transfers may occur in the same (micro)frame.
41166 + */
41167 + uint16_t periodic_usecs;
41168 +
41169 + /**
41170 + * Total bandwidth claimed so far for all periodic transfers
41171 + * in a frame.
41172 + * This will include a mixture of HS and FS transfers.
41173 + * Units are microseconds per (micro)frame.
41174 + * We have a budget per frame and have to schedule
41175 + * transactions accordingly.
41176 + * Watch out for the fact that things are actually scheduled for the
41177 + * "next frame".
41178 + */
41179 + uint16_t frame_usecs[8];
41180 +
41181 +
41182 + /**
41183 + * Frame number read from the core at SOF. The value ranges from 0 to
41184 + * DWC_HFNUM_MAX_FRNUM.
41185 + */
41186 + uint16_t frame_number;
41187 +
41188 + /**
41189 + * Count of periodic QHs, if using several eps. For SOF enable/disable.
41190 + */
41191 + uint16_t periodic_qh_count;
41192 +
41193 + /**
41194 + * Free host channels in the controller. This is a list of
41195 + * dwc_hc_t items.
41196 + */
41197 + struct hc_list free_hc_list;
41198 + /**
41199 + * Number of host channels assigned to periodic transfers. Currently
41200 + * assuming that there is a dedicated host channel for each periodic
41201 + * transaction and at least one host channel available for
41202 + * non-periodic transactions.
41203 + */
41204 + int periodic_channels; /* microframe_schedule==0 */
41205 +
41206 + /**
41207 + * Number of host channels assigned to non-periodic transfers.
41208 + */
41209 + int non_periodic_channels; /* microframe_schedule==0 */
41210 +
41211 + /**
41212 + * Number of host channels assigned to non-periodic transfers.
41213 + */
41214 + int available_host_channels;
41215 +
41216 + /**
41217 + * Array of pointers to the host channel descriptors. Allows accessing
41218 + * a host channel descriptor given the host channel number. This is
41219 + * useful in interrupt handlers.
41220 + */
41221 + struct dwc_hc *hc_ptr_array[MAX_EPS_CHANNELS];
41222 +
41223 + /**
41224 + * Buffer to use for any data received during the status phase of a
41225 + * control transfer. Normally no data is transferred during the status
41226 + * phase. This buffer is used as a bit bucket.
41227 + */
41228 + uint8_t *status_buf;
41229 +
41230 + /**
41231 + * DMA address for status_buf.
41232 + */
41233 + dma_addr_t status_buf_dma;
41234 +#define DWC_OTG_HCD_STATUS_BUF_SIZE 64
41235 +
41236 + /**
41237 + * Connection timer. An OTG host must display a message if the device
41238 + * does not connect. Started when the VBus power is turned on via
41239 + * sysfs attribute "buspower".
41240 + */
41241 + dwc_timer_t *conn_timer;
41242 +
41243 + /* Tasket to do a reset */
41244 + dwc_tasklet_t *reset_tasklet;
41245 +
41246 + dwc_tasklet_t *completion_tasklet;
41247 + struct urb_list completed_urb_list;
41248 +
41249 + /* */
41250 + dwc_spinlock_t *lock;
41251 + dwc_spinlock_t *channel_lock;
41252 + /**
41253 + * Private data that could be used by OS wrapper.
41254 + */
41255 + void *priv;
41256 +
41257 + uint8_t otg_port;
41258 +
41259 + /** Frame List */
41260 + uint32_t *frame_list;
41261 +
41262 + /** Hub - Port assignment */
41263 + int hub_port[128];
41264 +#ifdef FIQ_DEBUG
41265 + int hub_port_alloc[2048];
41266 +#endif
41267 +
41268 + /** Frame List DMA address */
41269 + dma_addr_t frame_list_dma;
41270 +
41271 + struct fiq_stack *fiq_stack;
41272 + struct fiq_state *fiq_state;
41273 +
41274 + /** Virtual address for split transaction DMA bounce buffers */
41275 + struct fiq_dma_blob *fiq_dmab;
41276 +
41277 +#ifdef DEBUG
41278 + uint32_t frrem_samples;
41279 + uint64_t frrem_accum;
41280 +
41281 + uint32_t hfnum_7_samples_a;
41282 + uint64_t hfnum_7_frrem_accum_a;
41283 + uint32_t hfnum_0_samples_a;
41284 + uint64_t hfnum_0_frrem_accum_a;
41285 + uint32_t hfnum_other_samples_a;
41286 + uint64_t hfnum_other_frrem_accum_a;
41287 +
41288 + uint32_t hfnum_7_samples_b;
41289 + uint64_t hfnum_7_frrem_accum_b;
41290 + uint32_t hfnum_0_samples_b;
41291 + uint64_t hfnum_0_frrem_accum_b;
41292 + uint32_t hfnum_other_samples_b;
41293 + uint64_t hfnum_other_frrem_accum_b;
41294 +#endif
41295 +};
41296 +
41297 +/** @name Transaction Execution Functions */
41298 +/** @{ */
41299 +extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t
41300 + * hcd);
41301 +extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
41302 + dwc_otg_transaction_type_e tr_type);
41303 +
41304 +int dwc_otg_hcd_allocate_port(dwc_otg_hcd_t * hcd, dwc_otg_qh_t *qh);
41305 +void dwc_otg_hcd_release_port(dwc_otg_hcd_t * dwc_otg_hcd, dwc_otg_qh_t *qh);
41306 +
41307 +extern int fiq_fsm_queue_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
41308 +extern int fiq_fsm_transaction_suitable(dwc_otg_qh_t *qh);
41309 +extern void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num);
41310 +
41311 +/** @} */
41312 +
41313 +/** @name Interrupt Handler Functions */
41314 +/** @{ */
41315 +extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
41316 +extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * dwc_otg_hcd);
41317 +extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *
41318 + dwc_otg_hcd);
41319 +extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *
41320 + dwc_otg_hcd);
41321 +extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *
41322 + dwc_otg_hcd);
41323 +extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *
41324 + dwc_otg_hcd);
41325 +extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd);
41326 +extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *
41327 + dwc_otg_hcd);
41328 +extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t * dwc_otg_hcd);
41329 +extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd);
41330 +extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd,
41331 + uint32_t num);
41332 +extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t * dwc_otg_hcd);
41333 +extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *
41334 + dwc_otg_hcd);
41335 +/** @} */
41336 +
41337 +/** @name Schedule Queue Functions */
41338 +/** @{ */
41339 +
41340 +/* Implemented in dwc_otg_hcd_queue.c */
41341 +extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
41342 + dwc_otg_hcd_urb_t * urb, int atomic_alloc);
41343 +extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
41344 +extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
41345 +extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
41346 +extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
41347 + int sched_csplit);
41348 +
41349 +/** Remove and free a QH */
41350 +static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t * hcd,
41351 + dwc_otg_qh_t * qh)
41352 +{
41353 + dwc_irqflags_t flags;
41354 + DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
41355 + dwc_otg_hcd_qh_remove(hcd, qh);
41356 + DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
41357 + dwc_otg_hcd_qh_free(hcd, qh);
41358 +}
41359 +
41360 +/** Allocates memory for a QH structure.
41361 + * @return Returns the memory allocate or NULL on error. */
41362 +static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(int atomic_alloc)
41363 +{
41364 + if (atomic_alloc)
41365 + return (dwc_otg_qh_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qh_t));
41366 + else
41367 + return (dwc_otg_qh_t *) DWC_ALLOC(sizeof(dwc_otg_qh_t));
41368 +}
41369 +
41370 +extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb,
41371 + int atomic_alloc);
41372 +extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb);
41373 +extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, dwc_otg_hcd_t * dwc_otg_hcd,
41374 + dwc_otg_qh_t ** qh, int atomic_alloc);
41375 +
41376 +/** Allocates memory for a QTD structure.
41377 + * @return Returns the memory allocate or NULL on error. */
41378 +static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(int atomic_alloc)
41379 +{
41380 + if (atomic_alloc)
41381 + return (dwc_otg_qtd_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qtd_t));
41382 + else
41383 + return (dwc_otg_qtd_t *) DWC_ALLOC(sizeof(dwc_otg_qtd_t));
41384 +}
41385 +
41386 +/** Frees the memory for a QTD structure. QTD should already be removed from
41387 + * list.
41388 + * @param qtd QTD to free.*/
41389 +static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t * qtd)
41390 +{
41391 + DWC_FREE(qtd);
41392 +}
41393 +
41394 +/** Removes a QTD from list.
41395 + * @param hcd HCD instance.
41396 + * @param qtd QTD to remove from list.
41397 + * @param qh QTD belongs to.
41398 + */
41399 +static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t * hcd,
41400 + dwc_otg_qtd_t * qtd,
41401 + dwc_otg_qh_t * qh)
41402 +{
41403 + DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);
41404 +}
41405 +
41406 +/** Remove and free a QTD
41407 + * Need to disable IRQ and hold hcd lock while calling this function out of
41408 + * interrupt servicing chain */
41409 +static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t * hcd,
41410 + dwc_otg_qtd_t * qtd,
41411 + dwc_otg_qh_t * qh)
41412 +{
41413 + dwc_otg_hcd_qtd_remove(hcd, qtd, qh);
41414 + dwc_otg_hcd_qtd_free(qtd);
41415 +}
41416 +
41417 +/** @} */
41418 +
41419 +/** @name Descriptor DMA Supporting Functions */
41420 +/** @{ */
41421 +
41422 +extern void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
41423 +extern void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,
41424 + dwc_hc_t * hc,
41425 + dwc_otg_hc_regs_t * hc_regs,
41426 + dwc_otg_halt_status_e halt_status);
41427 +
41428 +extern int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
41429 +extern void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
41430 +
41431 +/** @} */
41432 +
41433 +/** @name Internal Functions */
41434 +/** @{ */
41435 +dwc_otg_qh_t *dwc_urb_to_qh(dwc_otg_hcd_urb_t * urb);
41436 +/** @} */
41437 +
41438 +#ifdef CONFIG_USB_DWC_OTG_LPM
41439 +extern int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd,
41440 + uint8_t devaddr);
41441 +extern void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd);
41442 +#endif
41443 +
41444 +/** Gets the QH that contains the list_head */
41445 +#define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
41446 +
41447 +/** Gets the QTD that contains the list_head */
41448 +#define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
41449 +
41450 +/** Check if QH is non-periodic */
41451 +#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == UE_BULK) || \
41452 + (_qh_ptr_->ep_type == UE_CONTROL))
41453 +
41454 +/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */
41455 +#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
41456 +
41457 +/** Packet size for any kind of endpoint descriptor */
41458 +#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
41459 +
41460 +/**
41461 + * Returns true if _frame1 is less than or equal to _frame2. The comparison is
41462 + * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the
41463 + * frame number when the max frame number is reached.
41464 + */
41465 +static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2)
41466 +{
41467 + return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <=
41468 + (DWC_HFNUM_MAX_FRNUM >> 1);
41469 +}
41470 +
41471 +/**
41472 + * Returns true if _frame1 is greater than _frame2. The comparison is done
41473 + * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
41474 + * number when the max frame number is reached.
41475 + */
41476 +static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2)
41477 +{
41478 + return (frame1 != frame2) &&
41479 + (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) <
41480 + (DWC_HFNUM_MAX_FRNUM >> 1));
41481 +}
41482 +
41483 +/**
41484 + * Increments _frame by the amount specified by _inc. The addition is done
41485 + * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value.
41486 + */
41487 +static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc)
41488 +{
41489 + return (frame + inc) & DWC_HFNUM_MAX_FRNUM;
41490 +}
41491 +
41492 +static inline uint16_t dwc_full_frame_num(uint16_t frame)
41493 +{
41494 + return (frame & DWC_HFNUM_MAX_FRNUM) >> 3;
41495 +}
41496 +
41497 +static inline uint16_t dwc_micro_frame_num(uint16_t frame)
41498 +{
41499 + return frame & 0x7;
41500 +}
41501 +
41502 +void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
41503 + dwc_otg_hc_regs_t * hc_regs,
41504 + dwc_otg_qtd_t * qtd);
41505 +
41506 +#ifdef DEBUG
41507 +/**
41508 + * Macro to sample the remaining PHY clocks left in the current frame. This
41509 + * may be used during debugging to determine the average time it takes to
41510 + * execute sections of code. There are two possible sample points, "a" and
41511 + * "b", so the _letter argument must be one of these values.
41512 + *
41513 + * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
41514 + * example, "cat /sys/devices/lm0/hcd_frrem".
41515 + */
41516 +#define dwc_sample_frrem(_hcd, _qh, _letter) \
41517 +{ \
41518 + hfnum_data_t hfnum; \
41519 + dwc_otg_qtd_t *qtd; \
41520 + qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
41521 + if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
41522 + hfnum.d32 = DWC_READ_REG32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
41523 + switch (hfnum.b.frnum & 0x7) { \
41524 + case 7: \
41525 + _hcd->hfnum_7_samples_##_letter++; \
41526 + _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
41527 + break; \
41528 + case 0: \
41529 + _hcd->hfnum_0_samples_##_letter++; \
41530 + _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
41531 + break; \
41532 + default: \
41533 + _hcd->hfnum_other_samples_##_letter++; \
41534 + _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
41535 + break; \
41536 + } \
41537 + } \
41538 +}
41539 +#else
41540 +#define dwc_sample_frrem(_hcd, _qh, _letter)
41541 +#endif
41542 +#endif
41543 +#endif /* DWC_DEVICE_ONLY */
41544 --- /dev/null
41545 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c
41546 @@ -0,0 +1,1132 @@
41547 +/*==========================================================================
41548 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_ddma.c $
41549 + * $Revision: #10 $
41550 + * $Date: 2011/10/20 $
41551 + * $Change: 1869464 $
41552 + *
41553 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
41554 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
41555 + * otherwise expressly agreed to in writing between Synopsys and you.
41556 + *
41557 + * The Software IS NOT an item of Licensed Software or Licensed Product under
41558 + * any End User Software License Agreement or Agreement for Licensed Product
41559 + * with Synopsys or any supplement thereto. You are permitted to use and
41560 + * redistribute this Software in source and binary forms, with or without
41561 + * modification, provided that redistributions of source code must retain this
41562 + * notice. You may not view, use, disclose, copy or distribute this file or
41563 + * any information contained herein except pursuant to this license grant from
41564 + * Synopsys. If you do not agree with this notice, including the disclaimer
41565 + * below, then you are not authorized to use the Software.
41566 + *
41567 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
41568 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
41569 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
41570 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
41571 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
41572 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
41573 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
41574 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41575 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
41576 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
41577 + * DAMAGE.
41578 + * ========================================================================== */
41579 +#ifndef DWC_DEVICE_ONLY
41580 +
41581 +/** @file
41582 + * This file contains Descriptor DMA support implementation for host mode.
41583 + */
41584 +
41585 +#include "dwc_otg_hcd.h"
41586 +#include "dwc_otg_regs.h"
41587 +
41588 +extern bool microframe_schedule;
41589 +
41590 +static inline uint8_t frame_list_idx(uint16_t frame)
41591 +{
41592 + return (frame & (MAX_FRLIST_EN_NUM - 1));
41593 +}
41594 +
41595 +static inline uint16_t desclist_idx_inc(uint16_t idx, uint16_t inc, uint8_t speed)
41596 +{
41597 + return (idx + inc) &
41598 + (((speed ==
41599 + DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC :
41600 + MAX_DMA_DESC_NUM_GENERIC) - 1);
41601 +}
41602 +
41603 +static inline uint16_t desclist_idx_dec(uint16_t idx, uint16_t inc, uint8_t speed)
41604 +{
41605 + return (idx - inc) &
41606 + (((speed ==
41607 + DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC :
41608 + MAX_DMA_DESC_NUM_GENERIC) - 1);
41609 +}
41610 +
41611 +static inline uint16_t max_desc_num(dwc_otg_qh_t * qh)
41612 +{
41613 + return (((qh->ep_type == UE_ISOCHRONOUS)
41614 + && (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH))
41615 + ? MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC);
41616 +}
41617 +static inline uint16_t frame_incr_val(dwc_otg_qh_t * qh)
41618 +{
41619 + return ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH)
41620 + ? ((qh->interval + 8 - 1) / 8)
41621 + : qh->interval);
41622 +}
41623 +
41624 +static int desc_list_alloc(dwc_otg_qh_t * qh)
41625 +{
41626 + int retval = 0;
41627 +
41628 + qh->desc_list = (dwc_otg_host_dma_desc_t *)
41629 + DWC_DMA_ALLOC(sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh),
41630 + &qh->desc_list_dma);
41631 +
41632 + if (!qh->desc_list) {
41633 + retval = -DWC_E_NO_MEMORY;
41634 + DWC_ERROR("%s: DMA descriptor list allocation failed\n", __func__);
41635 +
41636 + }
41637 +
41638 + dwc_memset(qh->desc_list, 0x00,
41639 + sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
41640 +
41641 + qh->n_bytes =
41642 + (uint32_t *) DWC_ALLOC(sizeof(uint32_t) * max_desc_num(qh));
41643 +
41644 + if (!qh->n_bytes) {
41645 + retval = -DWC_E_NO_MEMORY;
41646 + DWC_ERROR
41647 + ("%s: Failed to allocate array for descriptors' size actual values\n",
41648 + __func__);
41649 +
41650 + }
41651 + return retval;
41652 +
41653 +}
41654 +
41655 +static void desc_list_free(dwc_otg_qh_t * qh)
41656 +{
41657 + if (qh->desc_list) {
41658 + DWC_DMA_FREE(max_desc_num(qh), qh->desc_list,
41659 + qh->desc_list_dma);
41660 + qh->desc_list = NULL;
41661 + }
41662 +
41663 + if (qh->n_bytes) {
41664 + DWC_FREE(qh->n_bytes);
41665 + qh->n_bytes = NULL;
41666 + }
41667 +}
41668 +
41669 +static int frame_list_alloc(dwc_otg_hcd_t * hcd)
41670 +{
41671 + int retval = 0;
41672 + if (hcd->frame_list)
41673 + return 0;
41674 +
41675 + hcd->frame_list = DWC_DMA_ALLOC(4 * MAX_FRLIST_EN_NUM,
41676 + &hcd->frame_list_dma);
41677 + if (!hcd->frame_list) {
41678 + retval = -DWC_E_NO_MEMORY;
41679 + DWC_ERROR("%s: Frame List allocation failed\n", __func__);
41680 + }
41681 +
41682 + dwc_memset(hcd->frame_list, 0x00, 4 * MAX_FRLIST_EN_NUM);
41683 +
41684 + return retval;
41685 +}
41686 +
41687 +static void frame_list_free(dwc_otg_hcd_t * hcd)
41688 +{
41689 + if (!hcd->frame_list)
41690 + return;
41691 +
41692 + DWC_DMA_FREE(4 * MAX_FRLIST_EN_NUM, hcd->frame_list, hcd->frame_list_dma);
41693 + hcd->frame_list = NULL;
41694 +}
41695 +
41696 +static void per_sched_enable(dwc_otg_hcd_t * hcd, uint16_t fr_list_en)
41697 +{
41698 +
41699 + hcfg_data_t hcfg;
41700 +
41701 + hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg);
41702 +
41703 + if (hcfg.b.perschedena) {
41704 + /* already enabled */
41705 + return;
41706 + }
41707 +
41708 + DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hflbaddr,
41709 + hcd->frame_list_dma);
41710 +
41711 + switch (fr_list_en) {
41712 + case 64:
41713 + hcfg.b.frlisten = 3;
41714 + break;
41715 + case 32:
41716 + hcfg.b.frlisten = 2;
41717 + break;
41718 + case 16:
41719 + hcfg.b.frlisten = 1;
41720 + break;
41721 + case 8:
41722 + hcfg.b.frlisten = 0;
41723 + break;
41724 + default:
41725 + break;
41726 + }
41727 +
41728 + hcfg.b.perschedena = 1;
41729 +
41730 + DWC_DEBUGPL(DBG_HCD, "Enabling Periodic schedule\n");
41731 + DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);
41732 +
41733 +}
41734 +
41735 +static void per_sched_disable(dwc_otg_hcd_t * hcd)
41736 +{
41737 + hcfg_data_t hcfg;
41738 +
41739 + hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg);
41740 +
41741 + if (!hcfg.b.perschedena) {
41742 + /* already disabled */
41743 + return;
41744 + }
41745 + hcfg.b.perschedena = 0;
41746 +
41747 + DWC_DEBUGPL(DBG_HCD, "Disabling Periodic schedule\n");
41748 + DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);
41749 +}
41750 +
41751 +/*
41752 + * Activates/Deactivates FrameList entries for the channel
41753 + * based on endpoint servicing period.
41754 + */
41755 +void update_frame_list(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t enable)
41756 +{
41757 + uint16_t i, j, inc;
41758 + dwc_hc_t *hc = NULL;
41759 +
41760 + if (!qh->channel) {
41761 + DWC_ERROR("qh->channel = %p", qh->channel);
41762 + return;
41763 + }
41764 +
41765 + if (!hcd) {
41766 + DWC_ERROR("------hcd = %p", hcd);
41767 + return;
41768 + }
41769 +
41770 + if (!hcd->frame_list) {
41771 + DWC_ERROR("-------hcd->frame_list = %p", hcd->frame_list);
41772 + return;
41773 + }
41774 +
41775 + hc = qh->channel;
41776 + inc = frame_incr_val(qh);
41777 + if (qh->ep_type == UE_ISOCHRONOUS)
41778 + i = frame_list_idx(qh->sched_frame);
41779 + else
41780 + i = 0;
41781 +
41782 + j = i;
41783 + do {
41784 + if (enable)
41785 + hcd->frame_list[j] |= (1 << hc->hc_num);
41786 + else
41787 + hcd->frame_list[j] &= ~(1 << hc->hc_num);
41788 + j = (j + inc) & (MAX_FRLIST_EN_NUM - 1);
41789 + }
41790 + while (j != i);
41791 + if (!enable)
41792 + return;
41793 + hc->schinfo = 0;
41794 + if (qh->channel->speed == DWC_OTG_EP_SPEED_HIGH) {
41795 + j = 1;
41796 + /* TODO - check this */
41797 + inc = (8 + qh->interval - 1) / qh->interval;
41798 + for (i = 0; i < inc; i++) {
41799 + hc->schinfo |= j;
41800 + j = j << qh->interval;
41801 + }
41802 + } else {
41803 + hc->schinfo = 0xff;
41804 + }
41805 +}
41806 +
41807 +#if 1
41808 +void dump_frame_list(dwc_otg_hcd_t * hcd)
41809 +{
41810 + int i = 0;
41811 + DWC_PRINTF("--FRAME LIST (hex) --\n");
41812 + for (i = 0; i < MAX_FRLIST_EN_NUM; i++) {
41813 + DWC_PRINTF("%x\t", hcd->frame_list[i]);
41814 + if (!(i % 8) && i)
41815 + DWC_PRINTF("\n");
41816 + }
41817 + DWC_PRINTF("\n----\n");
41818 +
41819 +}
41820 +#endif
41821 +
41822 +static void release_channel_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
41823 +{
41824 + dwc_irqflags_t flags;
41825 + dwc_spinlock_t *channel_lock = hcd->channel_lock;
41826 +
41827 + dwc_hc_t *hc = qh->channel;
41828 + if (dwc_qh_is_non_per(qh)) {
41829 + DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
41830 + if (!microframe_schedule)
41831 + hcd->non_periodic_channels--;
41832 + else
41833 + hcd->available_host_channels++;
41834 + DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
41835 + } else
41836 + update_frame_list(hcd, qh, 0);
41837 +
41838 + /*
41839 + * The condition is added to prevent double cleanup try in case of device
41840 + * disconnect. See channel cleanup in dwc_otg_hcd_disconnect_cb().
41841 + */
41842 + if (hc->qh) {
41843 + dwc_otg_hc_cleanup(hcd->core_if, hc);
41844 + DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
41845 + hc->qh = NULL;
41846 + }
41847 +
41848 + qh->channel = NULL;
41849 + qh->ntd = 0;
41850 +
41851 + if (qh->desc_list) {
41852 + dwc_memset(qh->desc_list, 0x00,
41853 + sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
41854 + }
41855 +}
41856 +
41857 +/**
41858 + * Initializes a QH structure's Descriptor DMA related members.
41859 + * Allocates memory for descriptor list.
41860 + * On first periodic QH, allocates memory for FrameList
41861 + * and enables periodic scheduling.
41862 + *
41863 + * @param hcd The HCD state structure for the DWC OTG controller.
41864 + * @param qh The QH to init.
41865 + *
41866 + * @return 0 if successful, negative error code otherwise.
41867 + */
41868 +int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
41869 +{
41870 + int retval = 0;
41871 +
41872 + if (qh->do_split) {
41873 + DWC_ERROR("SPLIT Transfers are not supported in Descriptor DMA.\n");
41874 + return -1;
41875 + }
41876 +
41877 + retval = desc_list_alloc(qh);
41878 +
41879 + if ((retval == 0)
41880 + && (qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)) {
41881 + if (!hcd->frame_list) {
41882 + retval = frame_list_alloc(hcd);
41883 + /* Enable periodic schedule on first periodic QH */
41884 + if (retval == 0)
41885 + per_sched_enable(hcd, MAX_FRLIST_EN_NUM);
41886 + }
41887 + }
41888 +
41889 + qh->ntd = 0;
41890 +
41891 + return retval;
41892 +}
41893 +
41894 +/**
41895 + * Frees descriptor list memory associated with the QH.
41896 + * If QH is periodic and the last, frees FrameList memory
41897 + * and disables periodic scheduling.
41898 + *
41899 + * @param hcd The HCD state structure for the DWC OTG controller.
41900 + * @param qh The QH to init.
41901 + */
41902 +void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
41903 +{
41904 + desc_list_free(qh);
41905 +
41906 + /*
41907 + * Channel still assigned due to some reasons.
41908 + * Seen on Isoc URB dequeue. Channel halted but no subsequent
41909 + * ChHalted interrupt to release the channel. Afterwards
41910 + * when it comes here from endpoint disable routine
41911 + * channel remains assigned.
41912 + */
41913 + if (qh->channel)
41914 + release_channel_ddma(hcd, qh);
41915 +
41916 + if ((qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)
41917 + && (microframe_schedule || !hcd->periodic_channels) && hcd->frame_list) {
41918 +
41919 + per_sched_disable(hcd);
41920 + frame_list_free(hcd);
41921 + }
41922 +}
41923 +
41924 +static uint8_t frame_to_desc_idx(dwc_otg_qh_t * qh, uint16_t frame_idx)
41925 +{
41926 + if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
41927 + /*
41928 + * Descriptor set(8 descriptors) index
41929 + * which is 8-aligned.
41930 + */
41931 + return (frame_idx & ((MAX_DMA_DESC_NUM_HS_ISOC / 8) - 1)) * 8;
41932 + } else {
41933 + return (frame_idx & (MAX_DMA_DESC_NUM_GENERIC - 1));
41934 + }
41935 +}
41936 +
41937 +/*
41938 + * Determine starting frame for Isochronous transfer.
41939 + * Few frames skipped to prevent race condition with HC.
41940 + */
41941 +static uint8_t calc_starting_frame(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
41942 + uint8_t * skip_frames)
41943 +{
41944 + uint16_t frame = 0;
41945 + hcd->frame_number = dwc_otg_hcd_get_frame_number(hcd);
41946 +
41947 + /* sched_frame is always frame number(not uFrame) both in FS and HS !! */
41948 +
41949 + /*
41950 + * skip_frames is used to limit activated descriptors number
41951 + * to avoid the situation when HC services the last activated
41952 + * descriptor firstly.
41953 + * Example for FS:
41954 + * Current frame is 1, scheduled frame is 3. Since HC always fetches the descriptor
41955 + * corresponding to curr_frame+1, the descriptor corresponding to frame 2
41956 + * will be fetched. If the number of descriptors is max=64 (or greather) the
41957 + * list will be fully programmed with Active descriptors and it is possible
41958 + * case(rare) that the latest descriptor(considering rollback) corresponding
41959 + * to frame 2 will be serviced first. HS case is more probable because, in fact,
41960 + * up to 11 uframes(16 in the code) may be skipped.
41961 + */
41962 + if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
41963 + /*
41964 + * Consider uframe counter also, to start xfer asap.
41965 + * If half of the frame elapsed skip 2 frames otherwise
41966 + * just 1 frame.
41967 + * Starting descriptor index must be 8-aligned, so
41968 + * if the current frame is near to complete the next one
41969 + * is skipped as well.
41970 + */
41971 +
41972 + if (dwc_micro_frame_num(hcd->frame_number) >= 5) {
41973 + *skip_frames = 2 * 8;
41974 + frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames);
41975 + } else {
41976 + *skip_frames = 1 * 8;
41977 + frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames);
41978 + }
41979 +
41980 + frame = dwc_full_frame_num(frame);
41981 + } else {
41982 + /*
41983 + * Two frames are skipped for FS - the current and the next.
41984 + * But for descriptor programming, 1 frame(descriptor) is enough,
41985 + * see example above.
41986 + */
41987 + *skip_frames = 1;
41988 + frame = dwc_frame_num_inc(hcd->frame_number, 2);
41989 + }
41990 +
41991 + return frame;
41992 +}
41993 +
41994 +/*
41995 + * Calculate initial descriptor index for isochronous transfer
41996 + * based on scheduled frame.
41997 + */
41998 +static uint8_t recalc_initial_desc_idx(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
41999 +{
42000 + uint16_t frame = 0, fr_idx, fr_idx_tmp;
42001 + uint8_t skip_frames = 0;
42002 + /*
42003 + * With current ISOC processing algorithm the channel is being
42004 + * released when no more QTDs in the list(qh->ntd == 0).
42005 + * Thus this function is called only when qh->ntd == 0 and qh->channel == 0.
42006 + *
42007 + * So qh->channel != NULL branch is not used and just not removed from the
42008 + * source file. It is required for another possible approach which is,
42009 + * do not disable and release the channel when ISOC session completed,
42010 + * just move QH to inactive schedule until new QTD arrives.
42011 + * On new QTD, the QH moved back to 'ready' schedule,
42012 + * starting frame and therefore starting desc_index are recalculated.
42013 + * In this case channel is released only on ep_disable.
42014 + */
42015 +
42016 + /* Calculate starting descriptor index. For INTERRUPT endpoint it is always 0. */
42017 + if (qh->channel) {
42018 + frame = calc_starting_frame(hcd, qh, &skip_frames);
42019 + /*
42020 + * Calculate initial descriptor index based on FrameList current bitmap
42021 + * and servicing period.
42022 + */
42023 + fr_idx_tmp = frame_list_idx(frame);
42024 + fr_idx =
42025 + (MAX_FRLIST_EN_NUM + frame_list_idx(qh->sched_frame) -
42026 + fr_idx_tmp)
42027 + % frame_incr_val(qh);
42028 + fr_idx = (fr_idx + fr_idx_tmp) % MAX_FRLIST_EN_NUM;
42029 + } else {
42030 + qh->sched_frame = calc_starting_frame(hcd, qh, &skip_frames);
42031 + fr_idx = frame_list_idx(qh->sched_frame);
42032 + }
42033 +
42034 + qh->td_first = qh->td_last = frame_to_desc_idx(qh, fr_idx);
42035 +
42036 + return skip_frames;
42037 +}
42038 +
42039 +#define ISOC_URB_GIVEBACK_ASAP
42040 +
42041 +#define MAX_ISOC_XFER_SIZE_FS 1023
42042 +#define MAX_ISOC_XFER_SIZE_HS 3072
42043 +#define DESCNUM_THRESHOLD 4
42044 +
42045 +static void init_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
42046 + uint8_t skip_frames)
42047 +{
42048 + struct dwc_otg_hcd_iso_packet_desc *frame_desc;
42049 + dwc_otg_qtd_t *qtd;
42050 + dwc_otg_host_dma_desc_t *dma_desc;
42051 + uint16_t idx, inc, n_desc, ntd_max, max_xfer_size;
42052 +
42053 + idx = qh->td_last;
42054 + inc = qh->interval;
42055 + n_desc = 0;
42056 +
42057 + ntd_max = (max_desc_num(qh) + qh->interval - 1) / qh->interval;
42058 + if (skip_frames && !qh->channel)
42059 + ntd_max = ntd_max - skip_frames / qh->interval;
42060 +
42061 + max_xfer_size =
42062 + (qh->dev_speed ==
42063 + DWC_OTG_EP_SPEED_HIGH) ? MAX_ISOC_XFER_SIZE_HS :
42064 + MAX_ISOC_XFER_SIZE_FS;
42065 +
42066 + DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
42067 + while ((qh->ntd < ntd_max)
42068 + && (qtd->isoc_frame_index_last <
42069 + qtd->urb->packet_count)) {
42070 +
42071 + dma_desc = &qh->desc_list[idx];
42072 + dwc_memset(dma_desc, 0x00, sizeof(dwc_otg_host_dma_desc_t));
42073 +
42074 + frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index_last];
42075 +
42076 + if (frame_desc->length > max_xfer_size)
42077 + qh->n_bytes[idx] = max_xfer_size;
42078 + else
42079 + qh->n_bytes[idx] = frame_desc->length;
42080 + dma_desc->status.b_isoc.n_bytes = qh->n_bytes[idx];
42081 + dma_desc->status.b_isoc.a = 1;
42082 + dma_desc->status.b_isoc.sts = 0;
42083 +
42084 + dma_desc->buf = qtd->urb->dma + frame_desc->offset;
42085 +
42086 + qh->ntd++;
42087 +
42088 + qtd->isoc_frame_index_last++;
42089 +
42090 +#ifdef ISOC_URB_GIVEBACK_ASAP
42091 + /*
42092 + * Set IOC for each descriptor corresponding to the
42093 + * last frame of the URB.
42094 + */
42095 + if (qtd->isoc_frame_index_last ==
42096 + qtd->urb->packet_count)
42097 + dma_desc->status.b_isoc.ioc = 1;
42098 +
42099 +#endif
42100 + idx = desclist_idx_inc(idx, inc, qh->dev_speed);
42101 + n_desc++;
42102 +
42103 + }
42104 + qtd->in_process = 1;
42105 + }
42106 +
42107 + qh->td_last = idx;
42108 +
42109 +#ifdef ISOC_URB_GIVEBACK_ASAP
42110 + /* Set IOC for the last descriptor if descriptor list is full */
42111 + if (qh->ntd == ntd_max) {
42112 + idx = desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
42113 + qh->desc_list[idx].status.b_isoc.ioc = 1;
42114 + }
42115 +#else
42116 + /*
42117 + * Set IOC bit only for one descriptor.
42118 + * Always try to be ahead of HW processing,
42119 + * i.e. on IOC generation driver activates next descriptors but
42120 + * core continues to process descriptors followed the one with IOC set.
42121 + */
42122 +
42123 + if (n_desc > DESCNUM_THRESHOLD) {
42124 + /*
42125 + * Move IOC "up". Required even if there is only one QTD
42126 + * in the list, cause QTDs migth continue to be queued,
42127 + * but during the activation it was only one queued.
42128 + * Actually more than one QTD might be in the list if this function called
42129 + * from XferCompletion - QTDs was queued during HW processing of the previous
42130 + * descriptor chunk.
42131 + */
42132 + idx = dwc_desclist_idx_dec(idx, inc * ((qh->ntd + 1) / 2), qh->dev_speed);
42133 + } else {
42134 + /*
42135 + * Set the IOC for the latest descriptor
42136 + * if either number of descriptor is not greather than threshold
42137 + * or no more new descriptors activated.
42138 + */
42139 + idx = dwc_desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
42140 + }
42141 +
42142 + qh->desc_list[idx].status.b_isoc.ioc = 1;
42143 +#endif
42144 +}
42145 +
42146 +static void init_non_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
42147 +{
42148 +
42149 + dwc_hc_t *hc;
42150 + dwc_otg_host_dma_desc_t *dma_desc;
42151 + dwc_otg_qtd_t *qtd;
42152 + int num_packets, len, n_desc = 0;
42153 +
42154 + hc = qh->channel;
42155 +
42156 + /*
42157 + * Start with hc->xfer_buff initialized in
42158 + * assign_and_init_hc(), then if SG transfer consists of multiple URBs,
42159 + * this pointer re-assigned to the buffer of the currently processed QTD.
42160 + * For non-SG request there is always one QTD active.
42161 + */
42162 +
42163 + DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
42164 +
42165 + if (n_desc) {
42166 + /* SG request - more than 1 QTDs */
42167 + hc->xfer_buff = (uint8_t *)qtd->urb->dma + qtd->urb->actual_length;
42168 + hc->xfer_len = qtd->urb->length - qtd->urb->actual_length;
42169 + }
42170 +
42171 + qtd->n_desc = 0;
42172 +
42173 + do {
42174 + dma_desc = &qh->desc_list[n_desc];
42175 + len = hc->xfer_len;
42176 +
42177 + if (len > MAX_DMA_DESC_SIZE)
42178 + len = MAX_DMA_DESC_SIZE - hc->max_packet + 1;
42179 +
42180 + if (hc->ep_is_in) {
42181 + if (len > 0) {
42182 + num_packets = (len + hc->max_packet - 1) / hc->max_packet;
42183 + } else {
42184 + /* Need 1 packet for transfer length of 0. */
42185 + num_packets = 1;
42186 + }
42187 + /* Always program an integral # of max packets for IN transfers. */
42188 + len = num_packets * hc->max_packet;
42189 + }
42190 +
42191 + dma_desc->status.b.n_bytes = len;
42192 +
42193 + qh->n_bytes[n_desc] = len;
42194 +
42195 + if ((qh->ep_type == UE_CONTROL)
42196 + && (qtd->control_phase == DWC_OTG_CONTROL_SETUP))
42197 + dma_desc->status.b.sup = 1; /* Setup Packet */
42198 +
42199 + dma_desc->status.b.a = 1; /* Active descriptor */
42200 + dma_desc->status.b.sts = 0;
42201 +
42202 + dma_desc->buf =
42203 + ((unsigned long)hc->xfer_buff & 0xffffffff);
42204 +
42205 + /*
42206 + * Last descriptor(or single) of IN transfer
42207 + * with actual size less than MaxPacket.
42208 + */
42209 + if (len > hc->xfer_len) {
42210 + hc->xfer_len = 0;
42211 + } else {
42212 + hc->xfer_buff += len;
42213 + hc->xfer_len -= len;
42214 + }
42215 +
42216 + qtd->n_desc++;
42217 + n_desc++;
42218 + }
42219 + while ((hc->xfer_len > 0) && (n_desc != MAX_DMA_DESC_NUM_GENERIC));
42220 +
42221 +
42222 + qtd->in_process = 1;
42223 +
42224 + if (qh->ep_type == UE_CONTROL)
42225 + break;
42226 +
42227 + if (n_desc == MAX_DMA_DESC_NUM_GENERIC)
42228 + break;
42229 + }
42230 +
42231 + if (n_desc) {
42232 + /* Request Transfer Complete interrupt for the last descriptor */
42233 + qh->desc_list[n_desc - 1].status.b.ioc = 1;
42234 + /* End of List indicator */
42235 + qh->desc_list[n_desc - 1].status.b.eol = 1;
42236 +
42237 + hc->ntd = n_desc;
42238 + }
42239 +}
42240 +
42241 +/**
42242 + * For Control and Bulk endpoints initializes descriptor list
42243 + * and starts the transfer.
42244 + *
42245 + * For Interrupt and Isochronous endpoints initializes descriptor list
42246 + * then updates FrameList, marking appropriate entries as active.
42247 + * In case of Isochronous, the starting descriptor index is calculated based
42248 + * on the scheduled frame, but only on the first transfer descriptor within a session.
42249 + * Then starts the transfer via enabling the channel.
42250 + * For Isochronous endpoint the channel is not halted on XferComplete
42251 + * interrupt so remains assigned to the endpoint(QH) until session is done.
42252 + *
42253 + * @param hcd The HCD state structure for the DWC OTG controller.
42254 + * @param qh The QH to init.
42255 + *
42256 + * @return 0 if successful, negative error code otherwise.
42257 + */
42258 +void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
42259 +{
42260 + /* Channel is already assigned */
42261 + dwc_hc_t *hc = qh->channel;
42262 + uint8_t skip_frames = 0;
42263 +
42264 + switch (hc->ep_type) {
42265 + case DWC_OTG_EP_TYPE_CONTROL:
42266 + case DWC_OTG_EP_TYPE_BULK:
42267 + init_non_isoc_dma_desc(hcd, qh);
42268 +
42269 + dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
42270 + break;
42271 + case DWC_OTG_EP_TYPE_INTR:
42272 + init_non_isoc_dma_desc(hcd, qh);
42273 +
42274 + update_frame_list(hcd, qh, 1);
42275 +
42276 + dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
42277 + break;
42278 + case DWC_OTG_EP_TYPE_ISOC:
42279 +
42280 + if (!qh->ntd)
42281 + skip_frames = recalc_initial_desc_idx(hcd, qh);
42282 +
42283 + init_isoc_dma_desc(hcd, qh, skip_frames);
42284 +
42285 + if (!hc->xfer_started) {
42286 +
42287 + update_frame_list(hcd, qh, 1);
42288 +
42289 + /*
42290 + * Always set to max, instead of actual size.
42291 + * Otherwise ntd will be changed with
42292 + * channel being enabled. Not recommended.
42293 + *
42294 + */
42295 + hc->ntd = max_desc_num(qh);
42296 + /* Enable channel only once for ISOC */
42297 + dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
42298 + }
42299 +
42300 + break;
42301 + default:
42302 +
42303 + break;
42304 + }
42305 +}
42306 +
42307 +static void complete_isoc_xfer_ddma(dwc_otg_hcd_t * hcd,
42308 + dwc_hc_t * hc,
42309 + dwc_otg_hc_regs_t * hc_regs,
42310 + dwc_otg_halt_status_e halt_status)
42311 +{
42312 + struct dwc_otg_hcd_iso_packet_desc *frame_desc;
42313 + dwc_otg_qtd_t *qtd, *qtd_tmp;
42314 + dwc_otg_qh_t *qh;
42315 + dwc_otg_host_dma_desc_t *dma_desc;
42316 + uint16_t idx, remain;
42317 + uint8_t urb_compl;
42318 +
42319 + qh = hc->qh;
42320 + idx = qh->td_first;
42321 +
42322 + if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
42323 + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry)
42324 + qtd->in_process = 0;
42325 + return;
42326 + } else if ((halt_status == DWC_OTG_HC_XFER_AHB_ERR) ||
42327 + (halt_status == DWC_OTG_HC_XFER_BABBLE_ERR)) {
42328 + /*
42329 + * Channel is halted in these error cases.
42330 + * Considered as serious issues.
42331 + * Complete all URBs marking all frames as failed,
42332 + * irrespective whether some of the descriptors(frames) succeeded or no.
42333 + * Pass error code to completion routine as well, to
42334 + * update urb->status, some of class drivers might use it to stop
42335 + * queing transfer requests.
42336 + */
42337 + int err = (halt_status == DWC_OTG_HC_XFER_AHB_ERR)
42338 + ? (-DWC_E_IO)
42339 + : (-DWC_E_OVERFLOW);
42340 +
42341 + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
42342 + for (idx = 0; idx < qtd->urb->packet_count; idx++) {
42343 + frame_desc = &qtd->urb->iso_descs[idx];
42344 + frame_desc->status = err;
42345 + }
42346 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, err);
42347 + dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
42348 + }
42349 + return;
42350 + }
42351 +
42352 + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
42353 +
42354 + if (!qtd->in_process)
42355 + break;
42356 +
42357 + urb_compl = 0;
42358 +
42359 + do {
42360 +
42361 + dma_desc = &qh->desc_list[idx];
42362 +
42363 + frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
42364 + remain = hc->ep_is_in ? dma_desc->status.b_isoc.n_bytes : 0;
42365 +
42366 + if (dma_desc->status.b_isoc.sts == DMA_DESC_STS_PKTERR) {
42367 + /*
42368 + * XactError or, unable to complete all the transactions
42369 + * in the scheduled micro-frame/frame,
42370 + * both indicated by DMA_DESC_STS_PKTERR.
42371 + */
42372 + qtd->urb->error_count++;
42373 + frame_desc->actual_length = qh->n_bytes[idx] - remain;
42374 + frame_desc->status = -DWC_E_PROTOCOL;
42375 + } else {
42376 + /* Success */
42377 +
42378 + frame_desc->actual_length = qh->n_bytes[idx] - remain;
42379 + frame_desc->status = 0;
42380 + }
42381 +
42382 + if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
42383 + /*
42384 + * urb->status is not used for isoc transfers here.
42385 + * The individual frame_desc status are used instead.
42386 + */
42387 +
42388 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
42389 + dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
42390 +
42391 + /*
42392 + * This check is necessary because urb_dequeue can be called
42393 + * from urb complete callback(sound driver example).
42394 + * All pending URBs are dequeued there, so no need for
42395 + * further processing.
42396 + */
42397 + if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
42398 + return;
42399 + }
42400 +
42401 + urb_compl = 1;
42402 +
42403 + }
42404 +
42405 + qh->ntd--;
42406 +
42407 + /* Stop if IOC requested descriptor reached */
42408 + if (dma_desc->status.b_isoc.ioc) {
42409 + idx = desclist_idx_inc(idx, qh->interval, hc->speed);
42410 + goto stop_scan;
42411 + }
42412 +
42413 + idx = desclist_idx_inc(idx, qh->interval, hc->speed);
42414 +
42415 + if (urb_compl)
42416 + break;
42417 + }
42418 + while (idx != qh->td_first);
42419 + }
42420 +stop_scan:
42421 + qh->td_first = idx;
42422 +}
42423 +
42424 +uint8_t update_non_isoc_urb_state_ddma(dwc_otg_hcd_t * hcd,
42425 + dwc_hc_t * hc,
42426 + dwc_otg_qtd_t * qtd,
42427 + dwc_otg_host_dma_desc_t * dma_desc,
42428 + dwc_otg_halt_status_e halt_status,
42429 + uint32_t n_bytes, uint8_t * xfer_done)
42430 +{
42431 +
42432 + uint16_t remain = hc->ep_is_in ? dma_desc->status.b.n_bytes : 0;
42433 + dwc_otg_hcd_urb_t *urb = qtd->urb;
42434 +
42435 + if (halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
42436 + urb->status = -DWC_E_IO;
42437 + return 1;
42438 + }
42439 + if (dma_desc->status.b.sts == DMA_DESC_STS_PKTERR) {
42440 + switch (halt_status) {
42441 + case DWC_OTG_HC_XFER_STALL:
42442 + urb->status = -DWC_E_PIPE;
42443 + break;
42444 + case DWC_OTG_HC_XFER_BABBLE_ERR:
42445 + urb->status = -DWC_E_OVERFLOW;
42446 + break;
42447 + case DWC_OTG_HC_XFER_XACT_ERR:
42448 + urb->status = -DWC_E_PROTOCOL;
42449 + break;
42450 + default:
42451 + DWC_ERROR("%s: Unhandled descriptor error status (%d)\n", __func__,
42452 + halt_status);
42453 + break;
42454 + }
42455 + return 1;
42456 + }
42457 +
42458 + if (dma_desc->status.b.a == 1) {
42459 + DWC_DEBUGPL(DBG_HCDV,
42460 + "Active descriptor encountered on channel %d\n",
42461 + hc->hc_num);
42462 + return 0;
42463 + }
42464 +
42465 + if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL) {
42466 + if (qtd->control_phase == DWC_OTG_CONTROL_DATA) {
42467 + urb->actual_length += n_bytes - remain;
42468 + if (remain || urb->actual_length == urb->length) {
42469 + /*
42470 + * For Control Data stage do not set urb->status=0 to prevent
42471 + * URB callback. Set it when Status phase done. See below.
42472 + */
42473 + *xfer_done = 1;
42474 + }
42475 +
42476 + } else if (qtd->control_phase == DWC_OTG_CONTROL_STATUS) {
42477 + urb->status = 0;
42478 + *xfer_done = 1;
42479 + }
42480 + /* No handling for SETUP stage */
42481 + } else {
42482 + /* BULK and INTR */
42483 + urb->actual_length += n_bytes - remain;
42484 + if (remain || urb->actual_length == urb->length) {
42485 + urb->status = 0;
42486 + *xfer_done = 1;
42487 + }
42488 + }
42489 +
42490 + return 0;
42491 +}
42492 +
42493 +static void complete_non_isoc_xfer_ddma(dwc_otg_hcd_t * hcd,
42494 + dwc_hc_t * hc,
42495 + dwc_otg_hc_regs_t * hc_regs,
42496 + dwc_otg_halt_status_e halt_status)
42497 +{
42498 + dwc_otg_hcd_urb_t *urb = NULL;
42499 + dwc_otg_qtd_t *qtd, *qtd_tmp;
42500 + dwc_otg_qh_t *qh;
42501 + dwc_otg_host_dma_desc_t *dma_desc;
42502 + uint32_t n_bytes, n_desc, i;
42503 + uint8_t failed = 0, xfer_done;
42504 +
42505 + n_desc = 0;
42506 +
42507 + qh = hc->qh;
42508 +
42509 + if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
42510 + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
42511 + qtd->in_process = 0;
42512 + }
42513 + return;
42514 + }
42515 +
42516 + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
42517 +
42518 + urb = qtd->urb;
42519 +
42520 + n_bytes = 0;
42521 + xfer_done = 0;
42522 +
42523 + for (i = 0; i < qtd->n_desc; i++) {
42524 + dma_desc = &qh->desc_list[n_desc];
42525 +
42526 + n_bytes = qh->n_bytes[n_desc];
42527 +
42528 + failed =
42529 + update_non_isoc_urb_state_ddma(hcd, hc, qtd,
42530 + dma_desc,
42531 + halt_status, n_bytes,
42532 + &xfer_done);
42533 +
42534 + if (failed
42535 + || (xfer_done
42536 + && (urb->status != -DWC_E_IN_PROGRESS))) {
42537 +
42538 + hcd->fops->complete(hcd, urb->priv, urb,
42539 + urb->status);
42540 + dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
42541 +
42542 + if (failed)
42543 + goto stop_scan;
42544 + } else if (qh->ep_type == UE_CONTROL) {
42545 + if (qtd->control_phase == DWC_OTG_CONTROL_SETUP) {
42546 + if (urb->length > 0) {
42547 + qtd->control_phase = DWC_OTG_CONTROL_DATA;
42548 + } else {
42549 + qtd->control_phase = DWC_OTG_CONTROL_STATUS;
42550 + }
42551 + DWC_DEBUGPL(DBG_HCDV, " Control setup transaction done\n");
42552 + } else if (qtd->control_phase == DWC_OTG_CONTROL_DATA) {
42553 + if (xfer_done) {
42554 + qtd->control_phase = DWC_OTG_CONTROL_STATUS;
42555 + DWC_DEBUGPL(DBG_HCDV, " Control data transfer done\n");
42556 + } else if (i + 1 == qtd->n_desc) {
42557 + /*
42558 + * Last descriptor for Control data stage which is
42559 + * not completed yet.
42560 + */
42561 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
42562 + }
42563 + }
42564 + }
42565 +
42566 + n_desc++;
42567 + }
42568 +
42569 + }
42570 +
42571 +stop_scan:
42572 +
42573 + if (qh->ep_type != UE_CONTROL) {
42574 + /*
42575 + * Resetting the data toggle for bulk
42576 + * and interrupt endpoints in case of stall. See handle_hc_stall_intr()
42577 + */
42578 + if (halt_status == DWC_OTG_HC_XFER_STALL)
42579 + qh->data_toggle = DWC_OTG_HC_PID_DATA0;
42580 + else
42581 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
42582 + }
42583 +
42584 + if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
42585 + hcint_data_t hcint;
42586 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
42587 + if (hcint.b.nyet) {
42588 + /*
42589 + * Got a NYET on the last transaction of the transfer. It
42590 + * means that the endpoint should be in the PING state at the
42591 + * beginning of the next transfer.
42592 + */
42593 + qh->ping_state = 1;
42594 + clear_hc_int(hc_regs, nyet);
42595 + }
42596 +
42597 + }
42598 +
42599 +}
42600 +
42601 +/**
42602 + * This function is called from interrupt handlers.
42603 + * Scans the descriptor list, updates URB's status and
42604 + * calls completion routine for the URB if it's done.
42605 + * Releases the channel to be used by other transfers.
42606 + * In case of Isochronous endpoint the channel is not halted until
42607 + * the end of the session, i.e. QTD list is empty.
42608 + * If periodic channel released the FrameList is updated accordingly.
42609 + *
42610 + * Calls transaction selection routines to activate pending transfers.
42611 + *
42612 + * @param hcd The HCD state structure for the DWC OTG controller.
42613 + * @param hc Host channel, the transfer is completed on.
42614 + * @param hc_regs Host channel registers.
42615 + * @param halt_status Reason the channel is being halted,
42616 + * or just XferComplete for isochronous transfer
42617 + */
42618 +void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,
42619 + dwc_hc_t * hc,
42620 + dwc_otg_hc_regs_t * hc_regs,
42621 + dwc_otg_halt_status_e halt_status)
42622 +{
42623 + uint8_t continue_isoc_xfer = 0;
42624 + dwc_otg_transaction_type_e tr_type;
42625 + dwc_otg_qh_t *qh = hc->qh;
42626 +
42627 + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
42628 +
42629 + complete_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
42630 +
42631 + /* Release the channel if halted or session completed */
42632 + if (halt_status != DWC_OTG_HC_XFER_COMPLETE ||
42633 + DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
42634 +
42635 + /* Halt the channel if session completed */
42636 + if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
42637 + dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
42638 + }
42639 +
42640 + release_channel_ddma(hcd, qh);
42641 + dwc_otg_hcd_qh_remove(hcd, qh);
42642 + } else {
42643 + /* Keep in assigned schedule to continue transfer */
42644 + DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
42645 + &qh->qh_list_entry);
42646 + continue_isoc_xfer = 1;
42647 +
42648 + }
42649 + /** @todo Consider the case when period exceeds FrameList size.
42650 + * Frame Rollover interrupt should be used.
42651 + */
42652 + } else {
42653 + /* Scan descriptor list to complete the URB(s), then release the channel */
42654 + complete_non_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
42655 +
42656 + release_channel_ddma(hcd, qh);
42657 + dwc_otg_hcd_qh_remove(hcd, qh);
42658 +
42659 + if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
42660 + /* Add back to inactive non-periodic schedule on normal completion */
42661 + dwc_otg_hcd_qh_add(hcd, qh);
42662 + }
42663 +
42664 + }
42665 + tr_type = dwc_otg_hcd_select_transactions(hcd);
42666 + if (tr_type != DWC_OTG_TRANSACTION_NONE || continue_isoc_xfer) {
42667 + if (continue_isoc_xfer) {
42668 + if (tr_type == DWC_OTG_TRANSACTION_NONE) {
42669 + tr_type = DWC_OTG_TRANSACTION_PERIODIC;
42670 + } else if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC) {
42671 + tr_type = DWC_OTG_TRANSACTION_ALL;
42672 + }
42673 + }
42674 + dwc_otg_hcd_queue_transactions(hcd, tr_type);
42675 + }
42676 +}
42677 +
42678 +#endif /* DWC_DEVICE_ONLY */
42679 --- /dev/null
42680 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h
42681 @@ -0,0 +1,417 @@
42682 +/* ==========================================================================
42683 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_if.h $
42684 + * $Revision: #12 $
42685 + * $Date: 2011/10/26 $
42686 + * $Change: 1873028 $
42687 + *
42688 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
42689 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
42690 + * otherwise expressly agreed to in writing between Synopsys and you.
42691 + *
42692 + * The Software IS NOT an item of Licensed Software or Licensed Product under
42693 + * any End User Software License Agreement or Agreement for Licensed Product
42694 + * with Synopsys or any supplement thereto. You are permitted to use and
42695 + * redistribute this Software in source and binary forms, with or without
42696 + * modification, provided that redistributions of source code must retain this
42697 + * notice. You may not view, use, disclose, copy or distribute this file or
42698 + * any information contained herein except pursuant to this license grant from
42699 + * Synopsys. If you do not agree with this notice, including the disclaimer
42700 + * below, then you are not authorized to use the Software.
42701 + *
42702 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
42703 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42704 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
42705 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
42706 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
42707 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
42708 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
42709 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
42710 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42711 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
42712 + * DAMAGE.
42713 + * ========================================================================== */
42714 +#ifndef DWC_DEVICE_ONLY
42715 +#ifndef __DWC_HCD_IF_H__
42716 +#define __DWC_HCD_IF_H__
42717 +
42718 +#include "dwc_otg_core_if.h"
42719 +
42720 +/** @file
42721 + * This file defines DWC_OTG HCD Core API.
42722 + */
42723 +
42724 +struct dwc_otg_hcd;
42725 +typedef struct dwc_otg_hcd dwc_otg_hcd_t;
42726 +
42727 +struct dwc_otg_hcd_urb;
42728 +typedef struct dwc_otg_hcd_urb dwc_otg_hcd_urb_t;
42729 +
42730 +/** @name HCD Function Driver Callbacks */
42731 +/** @{ */
42732 +
42733 +/** This function is called whenever core switches to host mode. */
42734 +typedef int (*dwc_otg_hcd_start_cb_t) (dwc_otg_hcd_t * hcd);
42735 +
42736 +/** This function is called when device has been disconnected */
42737 +typedef int (*dwc_otg_hcd_disconnect_cb_t) (dwc_otg_hcd_t * hcd);
42738 +
42739 +/** Wrapper provides this function to HCD to core, so it can get hub information to which device is connected */
42740 +typedef int (*dwc_otg_hcd_hub_info_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
42741 + void *urb_handle,
42742 + uint32_t * hub_addr,
42743 + uint32_t * port_addr);
42744 +/** Via this function HCD core gets device speed */
42745 +typedef int (*dwc_otg_hcd_speed_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
42746 + void *urb_handle);
42747 +
42748 +/** This function is called when urb is completed */
42749 +typedef int (*dwc_otg_hcd_complete_urb_cb_t) (dwc_otg_hcd_t * hcd,
42750 + void *urb_handle,
42751 + dwc_otg_hcd_urb_t * dwc_otg_urb,
42752 + int32_t status);
42753 +
42754 +/** Via this function HCD core gets b_hnp_enable parameter */
42755 +typedef int (*dwc_otg_hcd_get_b_hnp_enable) (dwc_otg_hcd_t * hcd);
42756 +
42757 +struct dwc_otg_hcd_function_ops {
42758 + dwc_otg_hcd_start_cb_t start;
42759 + dwc_otg_hcd_disconnect_cb_t disconnect;
42760 + dwc_otg_hcd_hub_info_from_urb_cb_t hub_info;
42761 + dwc_otg_hcd_speed_from_urb_cb_t speed;
42762 + dwc_otg_hcd_complete_urb_cb_t complete;
42763 + dwc_otg_hcd_get_b_hnp_enable get_b_hnp_enable;
42764 +};
42765 +/** @} */
42766 +
42767 +/** @name HCD Core API */
42768 +/** @{ */
42769 +/** This function allocates dwc_otg_hcd structure and returns pointer on it. */
42770 +extern dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void);
42771 +
42772 +/** This function should be called to initiate HCD Core.
42773 + *
42774 + * @param hcd The HCD
42775 + * @param core_if The DWC_OTG Core
42776 + *
42777 + * Returns -DWC_E_NO_MEMORY if no enough memory.
42778 + * Returns 0 on success
42779 + */
42780 +extern int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if);
42781 +
42782 +/** Frees HCD
42783 + *
42784 + * @param hcd The HCD
42785 + */
42786 +extern void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd);
42787 +
42788 +/** This function should be called on every hardware interrupt.
42789 + *
42790 + * @param dwc_otg_hcd The HCD
42791 + *
42792 + * Returns non zero if interrupt is handled
42793 + * Return 0 if interrupt is not handled
42794 + */
42795 +extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
42796 +
42797 +/** This function is used to handle the fast interrupt
42798 + *
42799 + */
42800 +extern void __attribute__ ((naked)) dwc_otg_hcd_handle_fiq(void);
42801 +
42802 +/**
42803 + * Returns private data set by
42804 + * dwc_otg_hcd_set_priv_data function.
42805 + *
42806 + * @param hcd The HCD
42807 + */
42808 +extern void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd);
42809 +
42810 +/**
42811 + * Set private data.
42812 + *
42813 + * @param hcd The HCD
42814 + * @param priv_data pointer to be stored in private data
42815 + */
42816 +extern void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data);
42817 +
42818 +/**
42819 + * This function initializes the HCD Core.
42820 + *
42821 + * @param hcd The HCD
42822 + * @param fops The Function Driver Operations data structure containing pointers to all callbacks.
42823 + *
42824 + * Returns -DWC_E_NO_DEVICE if Core is currently is in device mode.
42825 + * Returns 0 on success
42826 + */
42827 +extern int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
42828 + struct dwc_otg_hcd_function_ops *fops);
42829 +
42830 +/**
42831 + * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
42832 + * stopped.
42833 + *
42834 + * @param hcd The HCD
42835 + */
42836 +extern void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd);
42837 +
42838 +/**
42839 + * Handles hub class-specific requests.
42840 + *
42841 + * @param dwc_otg_hcd The HCD
42842 + * @param typeReq Request Type
42843 + * @param wValue wValue from control request
42844 + * @param wIndex wIndex from control request
42845 + * @param buf data buffer
42846 + * @param wLength data buffer length
42847 + *
42848 + * Returns -DWC_E_INVALID if invalid argument is passed
42849 + * Returns 0 on success
42850 + */
42851 +extern int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
42852 + uint16_t typeReq, uint16_t wValue,
42853 + uint16_t wIndex, uint8_t * buf,
42854 + uint16_t wLength);
42855 +
42856 +/**
42857 + * Returns otg port number.
42858 + *
42859 + * @param hcd The HCD
42860 + */
42861 +extern uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd);
42862 +
42863 +/**
42864 + * Returns OTG version - either 1.3 or 2.0.
42865 + *
42866 + * @param core_if The core_if structure pointer
42867 + */
42868 +extern uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if);
42869 +
42870 +/**
42871 + * Returns 1 if currently core is acting as B host, and 0 otherwise.
42872 + *
42873 + * @param hcd The HCD
42874 + */
42875 +extern uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd);
42876 +
42877 +/**
42878 + * Returns current frame number.
42879 + *
42880 + * @param hcd The HCD
42881 + */
42882 +extern int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * hcd);
42883 +
42884 +/**
42885 + * Dumps hcd state.
42886 + *
42887 + * @param hcd The HCD
42888 + */
42889 +extern void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd);
42890 +
42891 +/**
42892 + * Dump the average frame remaining at SOF. This can be used to
42893 + * determine average interrupt latency. Frame remaining is also shown for
42894 + * start transfer and two additional sample points.
42895 + * Currently this function is not implemented.
42896 + *
42897 + * @param hcd The HCD
42898 + */
42899 +extern void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd);
42900 +
42901 +/**
42902 + * Sends LPM transaction to the local device.
42903 + *
42904 + * @param hcd The HCD
42905 + * @param devaddr Device Address
42906 + * @param hird Host initiated resume duration
42907 + * @param bRemoteWake Value of bRemoteWake field in LPM transaction
42908 + *
42909 + * Returns negative value if sending LPM transaction was not succeeded.
42910 + * Returns 0 on success.
42911 + */
42912 +extern int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr,
42913 + uint8_t hird, uint8_t bRemoteWake);
42914 +
42915 +/* URB interface */
42916 +
42917 +/**
42918 + * Allocates memory for dwc_otg_hcd_urb structure.
42919 + * Allocated memory should be freed by call of DWC_FREE.
42920 + *
42921 + * @param hcd The HCD
42922 + * @param iso_desc_count Count of ISOC descriptors
42923 + * @param atomic_alloc Specefies whether to perform atomic allocation.
42924 + */
42925 +extern dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
42926 + int iso_desc_count,
42927 + int atomic_alloc);
42928 +
42929 +/**
42930 + * Set pipe information in URB.
42931 + *
42932 + * @param hcd_urb DWC_OTG URB
42933 + * @param devaddr Device Address
42934 + * @param ep_num Endpoint Number
42935 + * @param ep_type Endpoint Type
42936 + * @param ep_dir Endpoint Direction
42937 + * @param mps Max Packet Size
42938 + */
42939 +extern void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * hcd_urb,
42940 + uint8_t devaddr, uint8_t ep_num,
42941 + uint8_t ep_type, uint8_t ep_dir,
42942 + uint16_t mps);
42943 +
42944 +/* Transfer flags */
42945 +#define URB_GIVEBACK_ASAP 0x1
42946 +#define URB_SEND_ZERO_PACKET 0x2
42947 +
42948 +/**
42949 + * Sets dwc_otg_hcd_urb parameters.
42950 + *
42951 + * @param urb DWC_OTG URB allocated by dwc_otg_hcd_urb_alloc function.
42952 + * @param urb_handle Unique handle for request, this will be passed back
42953 + * to function driver in completion callback.
42954 + * @param buf The buffer for the data
42955 + * @param dma The DMA buffer for the data
42956 + * @param buflen Transfer length
42957 + * @param sp Buffer for setup data
42958 + * @param sp_dma DMA address of setup data buffer
42959 + * @param flags Transfer flags
42960 + * @param interval Polling interval for interrupt or isochronous transfers.
42961 + */
42962 +extern void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * urb,
42963 + void *urb_handle, void *buf,
42964 + dwc_dma_t dma, uint32_t buflen, void *sp,
42965 + dwc_dma_t sp_dma, uint32_t flags,
42966 + uint16_t interval);
42967 +
42968 +/** Gets status from dwc_otg_hcd_urb
42969 + *
42970 + * @param dwc_otg_urb DWC_OTG URB
42971 + */
42972 +extern uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb);
42973 +
42974 +/** Gets actual length from dwc_otg_hcd_urb
42975 + *
42976 + * @param dwc_otg_urb DWC_OTG URB
42977 + */
42978 +extern uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *
42979 + dwc_otg_urb);
42980 +
42981 +/** Gets error count from dwc_otg_hcd_urb. Only for ISOC URBs
42982 + *
42983 + * @param dwc_otg_urb DWC_OTG URB
42984 + */
42985 +extern uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *
42986 + dwc_otg_urb);
42987 +
42988 +/** Set ISOC descriptor offset and length
42989 + *
42990 + * @param dwc_otg_urb DWC_OTG URB
42991 + * @param desc_num ISOC descriptor number
42992 + * @param offset Offset from beginig of buffer.
42993 + * @param length Transaction length
42994 + */
42995 +extern void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
42996 + int desc_num, uint32_t offset,
42997 + uint32_t length);
42998 +
42999 +/** Get status of ISOC descriptor, specified by desc_num
43000 + *
43001 + * @param dwc_otg_urb DWC_OTG URB
43002 + * @param desc_num ISOC descriptor number
43003 + */
43004 +extern uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *
43005 + dwc_otg_urb, int desc_num);
43006 +
43007 +/** Get actual length of ISOC descriptor, specified by desc_num
43008 + *
43009 + * @param dwc_otg_urb DWC_OTG URB
43010 + * @param desc_num ISOC descriptor number
43011 + */
43012 +extern uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
43013 + dwc_otg_urb,
43014 + int desc_num);
43015 +
43016 +/** Queue URB. After transfer is completes, the complete callback will be called with the URB status
43017 + *
43018 + * @param dwc_otg_hcd The HCD
43019 + * @param dwc_otg_urb DWC_OTG URB
43020 + * @param ep_handle Out parameter for returning endpoint handle
43021 + * @param atomic_alloc Flag to do atomic allocation if needed
43022 + *
43023 + * Returns -DWC_E_NO_DEVICE if no device is connected.
43024 + * Returns -DWC_E_NO_MEMORY if there is no enough memory.
43025 + * Returns 0 on success.
43026 + */
43027 +extern int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * dwc_otg_hcd,
43028 + dwc_otg_hcd_urb_t * dwc_otg_urb,
43029 + void **ep_handle, int atomic_alloc);
43030 +
43031 +/** De-queue the specified URB
43032 + *
43033 + * @param dwc_otg_hcd The HCD
43034 + * @param dwc_otg_urb DWC_OTG URB
43035 + */
43036 +extern int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * dwc_otg_hcd,
43037 + dwc_otg_hcd_urb_t * dwc_otg_urb);
43038 +
43039 +/** Frees resources in the DWC_otg controller related to a given endpoint.
43040 + * Any URBs for the endpoint must already be dequeued.
43041 + *
43042 + * @param hcd The HCD
43043 + * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
43044 + * @param retry Number of retries if there are queued transfers.
43045 + *
43046 + * Returns -DWC_E_INVALID if invalid arguments are passed.
43047 + * Returns 0 on success
43048 + */
43049 +extern int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
43050 + int retry);
43051 +
43052 +/* Resets the data toggle in qh structure. This function can be called from
43053 + * usb_clear_halt routine.
43054 + *
43055 + * @param hcd The HCD
43056 + * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
43057 + *
43058 + * Returns -DWC_E_INVALID if invalid arguments are passed.
43059 + * Returns 0 on success
43060 + */
43061 +extern int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle);
43062 +
43063 +/** Returns 1 if status of specified port is changed and 0 otherwise.
43064 + *
43065 + * @param hcd The HCD
43066 + * @param port Port number
43067 + */
43068 +extern int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port);
43069 +
43070 +/** Call this function to check if bandwidth was allocated for specified endpoint.
43071 + * Only for ISOC and INTERRUPT endpoints.
43072 + *
43073 + * @param hcd The HCD
43074 + * @param ep_handle Endpoint handle
43075 + */
43076 +extern int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd,
43077 + void *ep_handle);
43078 +
43079 +/** Call this function to check if bandwidth was freed for specified endpoint.
43080 + *
43081 + * @param hcd The HCD
43082 + * @param ep_handle Endpoint handle
43083 + */
43084 +extern int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle);
43085 +
43086 +/** Returns bandwidth allocated for specified endpoint in microseconds.
43087 + * Only for ISOC and INTERRUPT endpoints.
43088 + *
43089 + * @param hcd The HCD
43090 + * @param ep_handle Endpoint handle
43091 + */
43092 +extern uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd,
43093 + void *ep_handle);
43094 +
43095 +/** @} */
43096 +
43097 +#endif /* __DWC_HCD_IF_H__ */
43098 +#endif /* DWC_DEVICE_ONLY */
43099 --- /dev/null
43100 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
43101 @@ -0,0 +1,2713 @@
43102 +/* ==========================================================================
43103 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
43104 + * $Revision: #89 $
43105 + * $Date: 2011/10/20 $
43106 + * $Change: 1869487 $
43107 + *
43108 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
43109 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
43110 + * otherwise expressly agreed to in writing between Synopsys and you.
43111 + *
43112 + * The Software IS NOT an item of Licensed Software or Licensed Product under
43113 + * any End User Software License Agreement or Agreement for Licensed Product
43114 + * with Synopsys or any supplement thereto. You are permitted to use and
43115 + * redistribute this Software in source and binary forms, with or without
43116 + * modification, provided that redistributions of source code must retain this
43117 + * notice. You may not view, use, disclose, copy or distribute this file or
43118 + * any information contained herein except pursuant to this license grant from
43119 + * Synopsys. If you do not agree with this notice, including the disclaimer
43120 + * below, then you are not authorized to use the Software.
43121 + *
43122 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
43123 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43124 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43125 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
43126 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
43127 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
43128 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
43129 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43130 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
43131 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
43132 + * DAMAGE.
43133 + * ========================================================================== */
43134 +#ifndef DWC_DEVICE_ONLY
43135 +
43136 +#include "dwc_otg_hcd.h"
43137 +#include "dwc_otg_regs.h"
43138 +
43139 +#include <linux/jiffies.h>
43140 +#include <mach/hardware.h>
43141 +#include <asm/fiq.h>
43142 +
43143 +
43144 +extern bool microframe_schedule;
43145 +
43146 +/** @file
43147 + * This file contains the implementation of the HCD Interrupt handlers.
43148 + */
43149 +
43150 +int fiq_done, int_done;
43151 +
43152 +#ifdef FIQ_DEBUG
43153 +char buffer[1000*16];
43154 +int wptr;
43155 +void notrace _fiq_print(FIQDBG_T dbg_lvl, char *fmt, ...)
43156 +{
43157 + FIQDBG_T dbg_lvl_req = FIQDBG_PORTHUB;
43158 + va_list args;
43159 + char text[17];
43160 + hfnum_data_t hfnum = { .d32 = FIQ_READ(dwc_regs_base + 0x408) };
43161 +
43162 + if(dbg_lvl & dbg_lvl_req || dbg_lvl == FIQDBG_ERR)
43163 + {
43164 + local_fiq_disable();
43165 + snprintf(text, 9, "%4d%d:%d ", hfnum.b.frnum/8, hfnum.b.frnum%8, 8 - hfnum.b.frrem/937);
43166 + va_start(args, fmt);
43167 + vsnprintf(text+8, 9, fmt, args);
43168 + va_end(args);
43169 +
43170 + memcpy(buffer + wptr, text, 16);
43171 + wptr = (wptr + 16) % sizeof(buffer);
43172 + local_fiq_enable();
43173 + }
43174 +}
43175 +#endif
43176 +
43177 +/** This function handles interrupts for the HCD. */
43178 +int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd)
43179 +{
43180 + int retval = 0;
43181 + static int last_time;
43182 + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
43183 + gintsts_data_t gintsts;
43184 + gintmsk_data_t gintmsk;
43185 + hfnum_data_t hfnum;
43186 + haintmsk_data_t haintmsk;
43187 +
43188 +#ifdef DEBUG
43189 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
43190 +
43191 +#endif
43192 +
43193 + gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
43194 + gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
43195 +
43196 + /* Exit from ISR if core is hibernated */
43197 + if (core_if->hibernation_suspend == 1) {
43198 + goto exit_handler_routine;
43199 + }
43200 + DWC_SPINLOCK(dwc_otg_hcd->lock);
43201 + /* Check if HOST Mode */
43202 + if (dwc_otg_is_host_mode(core_if)) {
43203 + if (fiq_enable) {
43204 + local_fiq_disable();
43205 + fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
43206 + /* Pull in from the FIQ's disabled mask */
43207 + gintmsk.d32 = gintmsk.d32 | ~(dwc_otg_hcd->fiq_state->gintmsk_saved.d32);
43208 + dwc_otg_hcd->fiq_state->gintmsk_saved.d32 = ~0;
43209 + }
43210 +
43211 + if (fiq_fsm_enable && ( 0x0000FFFF & ~(dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint))) {
43212 + gintsts.b.hcintr = 1;
43213 + }
43214 +
43215 + /* Danger will robinson: fake a SOF if necessary */
43216 + if (fiq_fsm_enable && (dwc_otg_hcd->fiq_state->gintmsk_saved.b.sofintr == 1)) {
43217 + gintsts.b.sofintr = 1;
43218 + }
43219 + gintsts.d32 &= gintmsk.d32;
43220 +
43221 + if (fiq_enable) {
43222 + fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
43223 + local_fiq_enable();
43224 + }
43225 +
43226 + if (!gintsts.d32) {
43227 + goto exit_handler_routine;
43228 + }
43229 +
43230 +#ifdef DEBUG
43231 + // We should be OK doing this because the common interrupts should already have been serviced
43232 + /* Don't print debug message in the interrupt handler on SOF */
43233 +#ifndef DEBUG_SOF
43234 + if (gintsts.d32 != DWC_SOF_INTR_MASK)
43235 +#endif
43236 + DWC_DEBUGPL(DBG_HCDI, "\n");
43237 +#endif
43238 +
43239 +#ifdef DEBUG
43240 +#ifndef DEBUG_SOF
43241 + if (gintsts.d32 != DWC_SOF_INTR_MASK)
43242 +#endif
43243 + DWC_DEBUGPL(DBG_HCDI,
43244 + "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x core_if=%p\n",
43245 + gintsts.d32, core_if);
43246 +#endif
43247 + hfnum.d32 = DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->hfnum);
43248 + if (gintsts.b.sofintr) {
43249 + retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);
43250 + }
43251 +
43252 + if (gintsts.b.rxstsqlvl) {
43253 + retval |=
43254 + dwc_otg_hcd_handle_rx_status_q_level_intr
43255 + (dwc_otg_hcd);
43256 + }
43257 + if (gintsts.b.nptxfempty) {
43258 + retval |=
43259 + dwc_otg_hcd_handle_np_tx_fifo_empty_intr
43260 + (dwc_otg_hcd);
43261 + }
43262 + if (gintsts.b.i2cintr) {
43263 + /** @todo Implement i2cintr handler. */
43264 + }
43265 + if (gintsts.b.portintr) {
43266 +
43267 + gintmsk_data_t gintmsk = { .b.portintr = 1};
43268 + retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
43269 + if (fiq_enable) {
43270 + local_fiq_disable();
43271 + fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
43272 + DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
43273 + fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
43274 + local_fiq_enable();
43275 + } else {
43276 + DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
43277 + }
43278 + }
43279 + if (gintsts.b.hcintr) {
43280 + retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
43281 + }
43282 + if (gintsts.b.ptxfempty) {
43283 + retval |=
43284 + dwc_otg_hcd_handle_perio_tx_fifo_empty_intr
43285 + (dwc_otg_hcd);
43286 + }
43287 +#ifdef DEBUG
43288 +#ifndef DEBUG_SOF
43289 + if (gintsts.d32 != DWC_SOF_INTR_MASK)
43290 +#endif
43291 + {
43292 + DWC_DEBUGPL(DBG_HCDI,
43293 + "DWC OTG HCD Finished Servicing Interrupts\n");
43294 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
43295 + DWC_READ_REG32(&global_regs->gintsts));
43296 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
43297 + DWC_READ_REG32(&global_regs->gintmsk));
43298 + }
43299 +#endif
43300 +
43301 +#ifdef DEBUG
43302 +#ifndef DEBUG_SOF
43303 + if (gintsts.d32 != DWC_SOF_INTR_MASK)
43304 +#endif
43305 + DWC_DEBUGPL(DBG_HCDI, "\n");
43306 +#endif
43307 +
43308 + }
43309 +
43310 +exit_handler_routine:
43311 + if (fiq_enable) {
43312 + gintmsk_data_t gintmsk_new;
43313 + haintmsk_data_t haintmsk_new;
43314 + local_fiq_disable();
43315 + fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
43316 + gintmsk_new.d32 = *(volatile uint32_t *)&dwc_otg_hcd->fiq_state->gintmsk_saved.d32;
43317 + if(fiq_fsm_enable)
43318 + haintmsk_new.d32 = *(volatile uint32_t *)&dwc_otg_hcd->fiq_state->haintmsk_saved.d32;
43319 + else
43320 + haintmsk_new.d32 = 0x0000FFFF;
43321 +
43322 + /* The FIQ could have sneaked another interrupt in. If so, don't clear MPHI */
43323 + if ((gintmsk_new.d32 == ~0) && (haintmsk_new.d32 == 0x0000FFFF)) {
43324 + DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.intstat, (1<<16));
43325 + if (dwc_otg_hcd->fiq_state->mphi_int_count >= 50) {
43326 + fiq_print(FIQDBG_INT, dwc_otg_hcd->fiq_state, "MPHI CLR");
43327 + DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, ((1<<31) + (1<<16)));
43328 + while (!(DWC_READ_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & (1 << 17)))
43329 + ;
43330 + DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, (1<<31));
43331 + dwc_otg_hcd->fiq_state->mphi_int_count = 0;
43332 + }
43333 + int_done++;
43334 + }
43335 + haintmsk.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk);
43336 + /* Re-enable interrupts that the FIQ masked (first time round) */
43337 + FIQ_WRITE(dwc_otg_hcd->fiq_state->dwc_regs_base + GINTMSK, gintmsk.d32);
43338 + fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
43339 + local_fiq_enable();
43340 +
43341 + if ((jiffies / HZ) > last_time) {
43342 + //dwc_otg_qh_t *qh;
43343 + //dwc_list_link_t *cur;
43344 + /* Once a second output the fiq and irq numbers, useful for debug */
43345 + last_time = jiffies / HZ;
43346 + // DWC_WARN("np_kick=%d AHC=%d sched_frame=%d cur_frame=%d int_done=%d fiq_done=%d",
43347 + // dwc_otg_hcd->fiq_state->kick_np_queues, dwc_otg_hcd->available_host_channels,
43348 + // dwc_otg_hcd->fiq_state->next_sched_frame, hfnum.b.frnum, int_done, dwc_otg_hcd->fiq_state->fiq_done);
43349 + //printk(KERN_WARNING "Periodic queues:\n");
43350 + }
43351 + }
43352 +
43353 + DWC_SPINUNLOCK(dwc_otg_hcd->lock);
43354 + return retval;
43355 +}
43356 +
43357 +#ifdef DWC_TRACK_MISSED_SOFS
43358 +
43359 +#warning Compiling code to track missed SOFs
43360 +#define FRAME_NUM_ARRAY_SIZE 1000
43361 +/**
43362 + * This function is for debug only.
43363 + */
43364 +static inline void track_missed_sofs(uint16_t curr_frame_number)
43365 +{
43366 + static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
43367 + static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
43368 + static int frame_num_idx = 0;
43369 + static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
43370 + static int dumped_frame_num_array = 0;
43371 +
43372 + if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
43373 + if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) !=
43374 + curr_frame_number) {
43375 + frame_num_array[frame_num_idx] = curr_frame_number;
43376 + last_frame_num_array[frame_num_idx++] = last_frame_num;
43377 + }
43378 + } else if (!dumped_frame_num_array) {
43379 + int i;
43380 + DWC_PRINTF("Frame Last Frame\n");
43381 + DWC_PRINTF("----- ----------\n");
43382 + for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
43383 + DWC_PRINTF("0x%04x 0x%04x\n",
43384 + frame_num_array[i], last_frame_num_array[i]);
43385 + }
43386 + dumped_frame_num_array = 1;
43387 + }
43388 + last_frame_num = curr_frame_number;
43389 +}
43390 +#endif
43391 +
43392 +/**
43393 + * Handles the start-of-frame interrupt in host mode. Non-periodic
43394 + * transactions may be queued to the DWC_otg controller for the current
43395 + * (micro)frame. Periodic transactions may be queued to the controller for the
43396 + * next (micro)frame.
43397 + */
43398 +int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd)
43399 +{
43400 + hfnum_data_t hfnum;
43401 + gintsts_data_t gintsts = { .d32 = 0 };
43402 + dwc_list_link_t *qh_entry;
43403 + dwc_otg_qh_t *qh;
43404 + dwc_otg_transaction_type_e tr_type;
43405 + int did_something = 0;
43406 + int32_t next_sched_frame = -1;
43407 +
43408 + hfnum.d32 =
43409 + DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
43410 +
43411 +#ifdef DEBUG_SOF
43412 + DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
43413 +#endif
43414 + hcd->frame_number = hfnum.b.frnum;
43415 +
43416 +#ifdef DEBUG
43417 + hcd->frrem_accum += hfnum.b.frrem;
43418 + hcd->frrem_samples++;
43419 +#endif
43420 +
43421 +#ifdef DWC_TRACK_MISSED_SOFS
43422 + track_missed_sofs(hcd->frame_number);
43423 +#endif
43424 + /* Determine whether any periodic QHs should be executed. */
43425 + qh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive);
43426 + while (qh_entry != &hcd->periodic_sched_inactive) {
43427 + qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry);
43428 + qh_entry = qh_entry->next;
43429 + if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
43430 +
43431 + /*
43432 + * Move QH to the ready list to be executed next
43433 + * (micro)frame.
43434 + */
43435 + DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
43436 + &qh->qh_list_entry);
43437 +
43438 + did_something = 1;
43439 + }
43440 + else
43441 + {
43442 + if(next_sched_frame < 0 || dwc_frame_num_le(qh->sched_frame, next_sched_frame))
43443 + {
43444 + next_sched_frame = qh->sched_frame;
43445 + }
43446 + }
43447 + }
43448 + if (fiq_enable)
43449 + hcd->fiq_state->next_sched_frame = next_sched_frame;
43450 +
43451 + tr_type = dwc_otg_hcd_select_transactions(hcd);
43452 + if (tr_type != DWC_OTG_TRANSACTION_NONE) {
43453 + dwc_otg_hcd_queue_transactions(hcd, tr_type);
43454 + did_something = 1;
43455 + }
43456 +
43457 + /* Clear interrupt - but do not trample on the FIQ sof */
43458 + if (!fiq_fsm_enable) {
43459 + gintsts.b.sofintr = 1;
43460 + DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
43461 + }
43462 + return 1;
43463 +}
43464 +
43465 +/** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
43466 + * least one packet in the Rx FIFO. The packets are moved from the FIFO to
43467 + * memory if the DWC_otg controller is operating in Slave mode. */
43468 +int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * dwc_otg_hcd)
43469 +{
43470 + host_grxsts_data_t grxsts;
43471 + dwc_hc_t *hc = NULL;
43472 +
43473 + DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
43474 +
43475 + grxsts.d32 =
43476 + DWC_READ_REG32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
43477 +
43478 + hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
43479 + if (!hc) {
43480 + DWC_ERROR("Unable to get corresponding channel\n");
43481 + return 0;
43482 + }
43483 +
43484 + /* Packet Status */
43485 + DWC_DEBUGPL(DBG_HCDV, " Ch num = %d\n", grxsts.b.chnum);
43486 + DWC_DEBUGPL(DBG_HCDV, " Count = %d\n", grxsts.b.bcnt);
43487 + DWC_DEBUGPL(DBG_HCDV, " DPID = %d, hc.dpid = %d\n", grxsts.b.dpid,
43488 + hc->data_pid_start);
43489 + DWC_DEBUGPL(DBG_HCDV, " PStatus = %d\n", grxsts.b.pktsts);
43490 +
43491 + switch (grxsts.b.pktsts) {
43492 + case DWC_GRXSTS_PKTSTS_IN:
43493 + /* Read the data into the host buffer. */
43494 + if (grxsts.b.bcnt > 0) {
43495 + dwc_otg_read_packet(dwc_otg_hcd->core_if,
43496 + hc->xfer_buff, grxsts.b.bcnt);
43497 +
43498 + /* Update the HC fields for the next packet received. */
43499 + hc->xfer_count += grxsts.b.bcnt;
43500 + hc->xfer_buff += grxsts.b.bcnt;
43501 + }
43502 +
43503 + case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
43504 + case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
43505 + case DWC_GRXSTS_PKTSTS_CH_HALTED:
43506 + /* Handled in interrupt, just ignore data */
43507 + break;
43508 + default:
43509 + DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n",
43510 + grxsts.b.pktsts);
43511 + break;
43512 + }
43513 +
43514 + return 1;
43515 +}
43516 +
43517 +/** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
43518 + * data packets may be written to the FIFO for OUT transfers. More requests
43519 + * may be written to the non-periodic request queue for IN transfers. This
43520 + * interrupt is enabled only in Slave mode. */
43521 +int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
43522 +{
43523 + DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
43524 + dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
43525 + DWC_OTG_TRANSACTION_NON_PERIODIC);
43526 + return 1;
43527 +}
43528 +
43529 +/** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
43530 + * packets may be written to the FIFO for OUT transfers. More requests may be
43531 + * written to the periodic request queue for IN transfers. This interrupt is
43532 + * enabled only in Slave mode. */
43533 +int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
43534 +{
43535 + DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
43536 + dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
43537 + DWC_OTG_TRANSACTION_PERIODIC);
43538 + return 1;
43539 +}
43540 +
43541 +/** There are multiple conditions that can cause a port interrupt. This function
43542 + * determines which interrupt conditions have occurred and handles them
43543 + * appropriately. */
43544 +int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd)
43545 +{
43546 + int retval = 0;
43547 + hprt0_data_t hprt0;
43548 + hprt0_data_t hprt0_modify;
43549 +
43550 + hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
43551 + hprt0_modify.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
43552 +
43553 + /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
43554 + * GINTSTS */
43555 +
43556 + hprt0_modify.b.prtena = 0;
43557 + hprt0_modify.b.prtconndet = 0;
43558 + hprt0_modify.b.prtenchng = 0;
43559 + hprt0_modify.b.prtovrcurrchng = 0;
43560 +
43561 + /* Port Connect Detected
43562 + * Set flag and clear if detected */
43563 + if (dwc_otg_hcd->core_if->hibernation_suspend == 1) {
43564 + // Dont modify port status if we are in hibernation state
43565 + hprt0_modify.b.prtconndet = 1;
43566 + hprt0_modify.b.prtenchng = 1;
43567 + DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
43568 + hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
43569 + return retval;
43570 + }
43571 +
43572 + if (hprt0.b.prtconndet) {
43573 + /** @todo - check if steps performed in 'else' block should be perfromed regardles adp */
43574 + if (dwc_otg_hcd->core_if->adp_enable &&
43575 + dwc_otg_hcd->core_if->adp.vbuson_timer_started == 1) {
43576 + DWC_PRINTF("PORT CONNECT DETECTED ----------------\n");
43577 + DWC_TIMER_CANCEL(dwc_otg_hcd->core_if->adp.vbuson_timer);
43578 + dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
43579 + /* TODO - check if this is required, as
43580 + * host initialization was already performed
43581 + * after initial ADP probing
43582 + */
43583 + /*dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
43584 + dwc_otg_core_init(dwc_otg_hcd->core_if);
43585 + dwc_otg_enable_global_interrupts(dwc_otg_hcd->core_if);
43586 + cil_hcd_start(dwc_otg_hcd->core_if);*/
43587 + } else {
43588 +
43589 + DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
43590 + "Port Connect Detected--\n", hprt0.d32);
43591 + dwc_otg_hcd->flags.b.port_connect_status_change = 1;
43592 + dwc_otg_hcd->flags.b.port_connect_status = 1;
43593 + hprt0_modify.b.prtconndet = 1;
43594 +
43595 + /* B-Device has connected, Delete the connection timer. */
43596 + DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer);
43597 + }
43598 + /* The Hub driver asserts a reset when it sees port connect
43599 + * status change flag */
43600 + retval |= 1;
43601 + }
43602 +
43603 + /* Port Enable Changed
43604 + * Clear if detected - Set internal flag if disabled */
43605 + if (hprt0.b.prtenchng) {
43606 + DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
43607 + "Port Enable Changed--\n", hprt0.d32);
43608 + hprt0_modify.b.prtenchng = 1;
43609 + if (hprt0.b.prtena == 1) {
43610 + hfir_data_t hfir;
43611 + int do_reset = 0;
43612 + dwc_otg_core_params_t *params =
43613 + dwc_otg_hcd->core_if->core_params;
43614 + dwc_otg_core_global_regs_t *global_regs =
43615 + dwc_otg_hcd->core_if->core_global_regs;
43616 + dwc_otg_host_if_t *host_if =
43617 + dwc_otg_hcd->core_if->host_if;
43618 +
43619 + /* Every time when port enables calculate
43620 + * HFIR.FrInterval
43621 + */
43622 + hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
43623 + hfir.b.frint = calc_frame_interval(dwc_otg_hcd->core_if);
43624 + DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
43625 +
43626 + /* Check if we need to adjust the PHY clock speed for
43627 + * low power and adjust it */
43628 + if (params->host_support_fs_ls_low_power) {
43629 + gusbcfg_data_t usbcfg;
43630 +
43631 + usbcfg.d32 =
43632 + DWC_READ_REG32(&global_regs->gusbcfg);
43633 +
43634 + if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED
43635 + || hprt0.b.prtspd ==
43636 + DWC_HPRT0_PRTSPD_FULL_SPEED) {
43637 + /*
43638 + * Low power
43639 + */
43640 + hcfg_data_t hcfg;
43641 + if (usbcfg.b.phylpwrclksel == 0) {
43642 + /* Set PHY low power clock select for FS/LS devices */
43643 + usbcfg.b.phylpwrclksel = 1;
43644 + DWC_WRITE_REG32
43645 + (&global_regs->gusbcfg,
43646 + usbcfg.d32);
43647 + do_reset = 1;
43648 + }
43649 +
43650 + hcfg.d32 =
43651 + DWC_READ_REG32
43652 + (&host_if->host_global_regs->hcfg);
43653 +
43654 + if (hprt0.b.prtspd ==
43655 + DWC_HPRT0_PRTSPD_LOW_SPEED
43656 + && params->host_ls_low_power_phy_clk
43657 + ==
43658 + DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)
43659 + {
43660 + /* 6 MHZ */
43661 + DWC_DEBUGPL(DBG_CIL,
43662 + "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
43663 + if (hcfg.b.fslspclksel !=
43664 + DWC_HCFG_6_MHZ) {
43665 + hcfg.b.fslspclksel =
43666 + DWC_HCFG_6_MHZ;
43667 + DWC_WRITE_REG32
43668 + (&host_if->host_global_regs->hcfg,
43669 + hcfg.d32);
43670 + do_reset = 1;
43671 + }
43672 + } else {
43673 + /* 48 MHZ */
43674 + DWC_DEBUGPL(DBG_CIL,
43675 + "FS_PHY programming HCFG to 48 MHz ()\n");
43676 + if (hcfg.b.fslspclksel !=
43677 + DWC_HCFG_48_MHZ) {
43678 + hcfg.b.fslspclksel =
43679 + DWC_HCFG_48_MHZ;
43680 + DWC_WRITE_REG32
43681 + (&host_if->host_global_regs->hcfg,
43682 + hcfg.d32);
43683 + do_reset = 1;
43684 + }
43685 + }
43686 + } else {
43687 + /*
43688 + * Not low power
43689 + */
43690 + if (usbcfg.b.phylpwrclksel == 1) {
43691 + usbcfg.b.phylpwrclksel = 0;
43692 + DWC_WRITE_REG32
43693 + (&global_regs->gusbcfg,
43694 + usbcfg.d32);
43695 + do_reset = 1;
43696 + }
43697 + }
43698 +
43699 + if (do_reset) {
43700 + DWC_TASK_SCHEDULE(dwc_otg_hcd->reset_tasklet);
43701 + }
43702 + }
43703 +
43704 + if (!do_reset) {
43705 + /* Port has been enabled set the reset change flag */
43706 + dwc_otg_hcd->flags.b.port_reset_change = 1;
43707 + }
43708 + } else {
43709 + dwc_otg_hcd->flags.b.port_enable_change = 1;
43710 + }
43711 + retval |= 1;
43712 + }
43713 +
43714 + /** Overcurrent Change Interrupt */
43715 + if (hprt0.b.prtovrcurrchng) {
43716 + DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
43717 + "Port Overcurrent Changed--\n", hprt0.d32);
43718 + dwc_otg_hcd->flags.b.port_over_current_change = 1;
43719 + hprt0_modify.b.prtovrcurrchng = 1;
43720 + retval |= 1;
43721 + }
43722 +
43723 + /* Clear Port Interrupts */
43724 + DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
43725 +
43726 + return retval;
43727 +}
43728 +
43729 +/** This interrupt indicates that one or more host channels has a pending
43730 + * interrupt. There are multiple conditions that can cause each host channel
43731 + * interrupt. This function determines which conditions have occurred for each
43732 + * host channel interrupt and handles them appropriately. */
43733 +int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd)
43734 +{
43735 + int i;
43736 + int retval = 0;
43737 + haint_data_t haint = { .d32 = 0 } ;
43738 +
43739 + /* Clear appropriate bits in HCINTn to clear the interrupt bit in
43740 + * GINTSTS */
43741 +
43742 + if (!fiq_fsm_enable)
43743 + haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
43744 +
43745 + // Overwrite with saved interrupts from fiq handler
43746 + if(fiq_fsm_enable)
43747 + {
43748 + /* check the mask? */
43749 + local_fiq_disable();
43750 + fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
43751 + haint.b2.chint |= ~(dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint);
43752 + dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint = ~0;
43753 + fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
43754 + local_fiq_enable();
43755 + }
43756 +
43757 + for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
43758 + if (haint.b2.chint & (1 << i)) {
43759 + retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
43760 + }
43761 + }
43762 +
43763 + return retval;
43764 +}
43765 +
43766 +/**
43767 + * Gets the actual length of a transfer after the transfer halts. _halt_status
43768 + * holds the reason for the halt.
43769 + *
43770 + * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE,
43771 + * *short_read is set to 1 upon return if less than the requested
43772 + * number of bytes were transferred. Otherwise, *short_read is set to 0 upon
43773 + * return. short_read may also be NULL on entry, in which case it remains
43774 + * unchanged.
43775 + */
43776 +static uint32_t get_actual_xfer_length(dwc_hc_t * hc,
43777 + dwc_otg_hc_regs_t * hc_regs,
43778 + dwc_otg_qtd_t * qtd,
43779 + dwc_otg_halt_status_e halt_status,
43780 + int *short_read)
43781 +{
43782 + hctsiz_data_t hctsiz;
43783 + uint32_t length;
43784 +
43785 + if (short_read != NULL) {
43786 + *short_read = 0;
43787 + }
43788 + hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
43789 +
43790 + if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
43791 + if (hc->ep_is_in) {
43792 + length = hc->xfer_len - hctsiz.b.xfersize;
43793 + if (short_read != NULL) {
43794 + *short_read = (hctsiz.b.xfersize != 0);
43795 + }
43796 + } else if (hc->qh->do_split) {
43797 + //length = split_out_xfersize[hc->hc_num];
43798 + length = qtd->ssplit_out_xfer_count;
43799 + } else {
43800 + length = hc->xfer_len;
43801 + }
43802 + } else {
43803 + /*
43804 + * Must use the hctsiz.pktcnt field to determine how much data
43805 + * has been transferred. This field reflects the number of
43806 + * packets that have been transferred via the USB. This is
43807 + * always an integral number of packets if the transfer was
43808 + * halted before its normal completion. (Can't use the
43809 + * hctsiz.xfersize field because that reflects the number of
43810 + * bytes transferred via the AHB, not the USB).
43811 + */
43812 + length =
43813 + (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
43814 + }
43815 +
43816 + return length;
43817 +}
43818 +
43819 +/**
43820 + * Updates the state of the URB after a Transfer Complete interrupt on the
43821 + * host channel. Updates the actual_length field of the URB based on the
43822 + * number of bytes transferred via the host channel. Sets the URB status
43823 + * if the data transfer is finished.
43824 + *
43825 + * @return 1 if the data transfer specified by the URB is completely finished,
43826 + * 0 otherwise.
43827 + */
43828 +static int update_urb_state_xfer_comp(dwc_hc_t * hc,
43829 + dwc_otg_hc_regs_t * hc_regs,
43830 + dwc_otg_hcd_urb_t * urb,
43831 + dwc_otg_qtd_t * qtd)
43832 +{
43833 + int xfer_done = 0;
43834 + int short_read = 0;
43835 +
43836 + int xfer_length;
43837 +
43838 + xfer_length = get_actual_xfer_length(hc, hc_regs, qtd,
43839 + DWC_OTG_HC_XFER_COMPLETE,
43840 + &short_read);
43841 +
43842 + /* non DWORD-aligned buffer case handling. */
43843 + if (hc->align_buff && xfer_length && hc->ep_is_in) {
43844 + dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
43845 + xfer_length);
43846 + }
43847 +
43848 + urb->actual_length += xfer_length;
43849 +
43850 + if (xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) &&
43851 + (urb->flags & URB_SEND_ZERO_PACKET)
43852 + && (urb->actual_length == urb->length)
43853 + && !(urb->length % hc->max_packet)) {
43854 + xfer_done = 0;
43855 + } else if (short_read || urb->actual_length >= urb->length) {
43856 + xfer_done = 1;
43857 + urb->status = 0;
43858 + }
43859 +
43860 +#ifdef DEBUG
43861 + {
43862 + hctsiz_data_t hctsiz;
43863 + hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
43864 + DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
43865 + __func__, (hc->ep_is_in ? "IN" : "OUT"),
43866 + hc->hc_num);
43867 + DWC_DEBUGPL(DBG_HCDV, " hc->xfer_len %d\n", hc->xfer_len);
43868 + DWC_DEBUGPL(DBG_HCDV, " hctsiz.xfersize %d\n",
43869 + hctsiz.b.xfersize);
43870 + DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n",
43871 + urb->length);
43872 + DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n",
43873 + urb->actual_length);
43874 + DWC_DEBUGPL(DBG_HCDV, " short_read %d, xfer_done %d\n",
43875 + short_read, xfer_done);
43876 + }
43877 +#endif
43878 +
43879 + return xfer_done;
43880 +}
43881 +
43882 +/*
43883 + * Save the starting data toggle for the next transfer. The data toggle is
43884 + * saved in the QH for non-control transfers and it's saved in the QTD for
43885 + * control transfers.
43886 + */
43887 +void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
43888 + dwc_otg_hc_regs_t * hc_regs, dwc_otg_qtd_t * qtd)
43889 +{
43890 + hctsiz_data_t hctsiz;
43891 + hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
43892 +
43893 + if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
43894 + dwc_otg_qh_t *qh = hc->qh;
43895 + if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
43896 + qh->data_toggle = DWC_OTG_HC_PID_DATA0;
43897 + } else {
43898 + qh->data_toggle = DWC_OTG_HC_PID_DATA1;
43899 + }
43900 + } else {
43901 + if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
43902 + qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
43903 + } else {
43904 + qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
43905 + }
43906 + }
43907 +}
43908 +
43909 +/**
43910 + * Updates the state of an Isochronous URB when the transfer is stopped for
43911 + * any reason. The fields of the current entry in the frame descriptor array
43912 + * are set based on the transfer state and the input _halt_status. Completes
43913 + * the Isochronous URB if all the URB frames have been completed.
43914 + *
43915 + * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
43916 + * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
43917 + */
43918 +static dwc_otg_halt_status_e
43919 +update_isoc_urb_state(dwc_otg_hcd_t * hcd,
43920 + dwc_hc_t * hc,
43921 + dwc_otg_hc_regs_t * hc_regs,
43922 + dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
43923 +{
43924 + dwc_otg_hcd_urb_t *urb = qtd->urb;
43925 + dwc_otg_halt_status_e ret_val = halt_status;
43926 + struct dwc_otg_hcd_iso_packet_desc *frame_desc;
43927 +
43928 + frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
43929 + switch (halt_status) {
43930 + case DWC_OTG_HC_XFER_COMPLETE:
43931 + frame_desc->status = 0;
43932 + frame_desc->actual_length =
43933 + get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
43934 +
43935 + /* non DWORD-aligned buffer case handling. */
43936 + if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
43937 + dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
43938 + hc->qh->dw_align_buf, frame_desc->actual_length);
43939 + }
43940 +
43941 + break;
43942 + case DWC_OTG_HC_XFER_FRAME_OVERRUN:
43943 + urb->error_count++;
43944 + if (hc->ep_is_in) {
43945 + frame_desc->status = -DWC_E_NO_STREAM_RES;
43946 + } else {
43947 + frame_desc->status = -DWC_E_COMMUNICATION;
43948 + }
43949 + frame_desc->actual_length = 0;
43950 + break;
43951 + case DWC_OTG_HC_XFER_BABBLE_ERR:
43952 + urb->error_count++;
43953 + frame_desc->status = -DWC_E_OVERFLOW;
43954 + /* Don't need to update actual_length in this case. */
43955 + break;
43956 + case DWC_OTG_HC_XFER_XACT_ERR:
43957 + urb->error_count++;
43958 + frame_desc->status = -DWC_E_PROTOCOL;
43959 + frame_desc->actual_length =
43960 + get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
43961 +
43962 + /* non DWORD-aligned buffer case handling. */
43963 + if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
43964 + dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
43965 + hc->qh->dw_align_buf, frame_desc->actual_length);
43966 + }
43967 + /* Skip whole frame */
43968 + if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) &&
43969 + hc->ep_is_in && hcd->core_if->dma_enable) {
43970 + qtd->complete_split = 0;
43971 + qtd->isoc_split_offset = 0;
43972 + }
43973 +
43974 + break;
43975 + default:
43976 + DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status);
43977 + break;
43978 + }
43979 + if (++qtd->isoc_frame_index == urb->packet_count) {
43980 + /*
43981 + * urb->status is not used for isoc transfers.
43982 + * The individual frame_desc statuses are used instead.
43983 + */
43984 + hcd->fops->complete(hcd, urb->priv, urb, 0);
43985 + ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
43986 + } else {
43987 + ret_val = DWC_OTG_HC_XFER_COMPLETE;
43988 + }
43989 + return ret_val;
43990 +}
43991 +
43992 +/**
43993 + * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
43994 + * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
43995 + * still linked to the QH, the QH is added to the end of the inactive
43996 + * non-periodic schedule. For periodic QHs, removes the QH from the periodic
43997 + * schedule if no more QTDs are linked to the QH.
43998 + */
43999 +static void deactivate_qh(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, int free_qtd)
44000 +{
44001 + int continue_split = 0;
44002 + dwc_otg_qtd_t *qtd;
44003 +
44004 + DWC_DEBUGPL(DBG_HCDV, " %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
44005 +
44006 + qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
44007 +
44008 + if (qtd->complete_split) {
44009 + continue_split = 1;
44010 + } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
44011 + qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
44012 + continue_split = 1;
44013 + }
44014 +
44015 + if (free_qtd) {
44016 + dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
44017 + continue_split = 0;
44018 + }
44019 +
44020 + qh->channel = NULL;
44021 + dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
44022 +}
44023 +
44024 +/**
44025 + * Releases a host channel for use by other transfers. Attempts to select and
44026 + * queue more transactions since at least one host channel is available.
44027 + *
44028 + * @param hcd The HCD state structure.
44029 + * @param hc The host channel to release.
44030 + * @param qtd The QTD associated with the host channel. This QTD may be freed
44031 + * if the transfer is complete or an error has occurred.
44032 + * @param halt_status Reason the channel is being released. This status
44033 + * determines the actions taken by this function.
44034 + */
44035 +static void release_channel(dwc_otg_hcd_t * hcd,
44036 + dwc_hc_t * hc,
44037 + dwc_otg_qtd_t * qtd,
44038 + dwc_otg_halt_status_e halt_status)
44039 +{
44040 + dwc_otg_transaction_type_e tr_type;
44041 + int free_qtd;
44042 + dwc_irqflags_t flags;
44043 + dwc_spinlock_t *channel_lock = hcd->channel_lock;
44044 +
44045 + int hog_port = 0;
44046 +
44047 + DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d, xfer_len %d\n",
44048 + __func__, hc->hc_num, halt_status, hc->xfer_len);
44049 +
44050 + if(fiq_fsm_enable && hc->do_split) {
44051 + if(!hc->ep_is_in && hc->ep_type == UE_ISOCHRONOUS) {
44052 + if(hc->xact_pos == DWC_HCSPLIT_XACTPOS_MID ||
44053 + hc->xact_pos == DWC_HCSPLIT_XACTPOS_BEGIN) {
44054 + hog_port = 0;
44055 + }
44056 + }
44057 + }
44058 +
44059 + switch (halt_status) {
44060 + case DWC_OTG_HC_XFER_URB_COMPLETE:
44061 + free_qtd = 1;
44062 + break;
44063 + case DWC_OTG_HC_XFER_AHB_ERR:
44064 + case DWC_OTG_HC_XFER_STALL:
44065 + case DWC_OTG_HC_XFER_BABBLE_ERR:
44066 + free_qtd = 1;
44067 + break;
44068 + case DWC_OTG_HC_XFER_XACT_ERR:
44069 + if (qtd->error_count >= 3) {
44070 + DWC_DEBUGPL(DBG_HCDV,
44071 + " Complete URB with transaction error\n");
44072 + free_qtd = 1;
44073 + qtd->urb->status = -DWC_E_PROTOCOL;
44074 + hcd->fops->complete(hcd, qtd->urb->priv,
44075 + qtd->urb, -DWC_E_PROTOCOL);
44076 + } else {
44077 + free_qtd = 0;
44078 + }
44079 + break;
44080 + case DWC_OTG_HC_XFER_URB_DEQUEUE:
44081 + /*
44082 + * The QTD has already been removed and the QH has been
44083 + * deactivated. Don't want to do anything except release the
44084 + * host channel and try to queue more transfers.
44085 + */
44086 + goto cleanup;
44087 + case DWC_OTG_HC_XFER_NO_HALT_STATUS:
44088 + free_qtd = 0;
44089 + break;
44090 + case DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE:
44091 + DWC_DEBUGPL(DBG_HCDV,
44092 + " Complete URB with I/O error\n");
44093 + free_qtd = 1;
44094 + qtd->urb->status = -DWC_E_IO;
44095 + hcd->fops->complete(hcd, qtd->urb->priv,
44096 + qtd->urb, -DWC_E_IO);
44097 + break;
44098 + default:
44099 + free_qtd = 0;
44100 + break;
44101 + }
44102 +
44103 + deactivate_qh(hcd, hc->qh, free_qtd);
44104 +
44105 +cleanup:
44106 + /*
44107 + * Release the host channel for use by other transfers. The cleanup
44108 + * function clears the channel interrupt enables and conditions, so
44109 + * there's no need to clear the Channel Halted interrupt separately.
44110 + */
44111 + if (fiq_fsm_enable && hcd->fiq_state->channel[hc->hc_num].fsm != FIQ_PASSTHROUGH)
44112 + dwc_otg_cleanup_fiq_channel(hcd, hc->hc_num);
44113 + dwc_otg_hc_cleanup(hcd->core_if, hc);
44114 + DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
44115 +
44116 + if (!microframe_schedule) {
44117 + switch (hc->ep_type) {
44118 + case DWC_OTG_EP_TYPE_CONTROL:
44119 + case DWC_OTG_EP_TYPE_BULK:
44120 + hcd->non_periodic_channels--;
44121 + break;
44122 +
44123 + default:
44124 + /*
44125 + * Don't release reservations for periodic channels here.
44126 + * That's done when a periodic transfer is descheduled (i.e.
44127 + * when the QH is removed from the periodic schedule).
44128 + */
44129 + break;
44130 + }
44131 + } else {
44132 +
44133 + DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
44134 + hcd->available_host_channels++;
44135 + fiq_print(FIQDBG_INT, hcd->fiq_state, "AHC = %d ", hcd->available_host_channels);
44136 + DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
44137 + }
44138 +
44139 + /* Try to queue more transfers now that there's a free channel. */
44140 + tr_type = dwc_otg_hcd_select_transactions(hcd);
44141 + if (tr_type != DWC_OTG_TRANSACTION_NONE) {
44142 + dwc_otg_hcd_queue_transactions(hcd, tr_type);
44143 + }
44144 +}
44145 +
44146 +/**
44147 + * Halts a host channel. If the channel cannot be halted immediately because
44148 + * the request queue is full, this function ensures that the FIFO empty
44149 + * interrupt for the appropriate queue is enabled so that the halt request can
44150 + * be queued when there is space in the request queue.
44151 + *
44152 + * This function may also be called in DMA mode. In that case, the channel is
44153 + * simply released since the core always halts the channel automatically in
44154 + * DMA mode.
44155 + */
44156 +static void halt_channel(dwc_otg_hcd_t * hcd,
44157 + dwc_hc_t * hc,
44158 + dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
44159 +{
44160 + if (hcd->core_if->dma_enable) {
44161 + release_channel(hcd, hc, qtd, halt_status);
44162 + return;
44163 + }
44164 +
44165 + /* Slave mode processing... */
44166 + dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
44167 +
44168 + if (hc->halt_on_queue) {
44169 + gintmsk_data_t gintmsk = {.d32 = 0 };
44170 + dwc_otg_core_global_regs_t *global_regs;
44171 + global_regs = hcd->core_if->core_global_regs;
44172 +
44173 + if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
44174 + hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
44175 + /*
44176 + * Make sure the Non-periodic Tx FIFO empty interrupt
44177 + * is enabled so that the non-periodic schedule will
44178 + * be processed.
44179 + */
44180 + gintmsk.b.nptxfempty = 1;
44181 + if (fiq_enable) {
44182 + local_fiq_disable();
44183 + fiq_fsm_spin_lock(&hcd->fiq_state->lock);
44184 + DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
44185 + fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
44186 + local_fiq_enable();
44187 + } else {
44188 + DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
44189 + }
44190 + } else {
44191 + /*
44192 + * Move the QH from the periodic queued schedule to
44193 + * the periodic assigned schedule. This allows the
44194 + * halt to be queued when the periodic schedule is
44195 + * processed.
44196 + */
44197 + DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
44198 + &hc->qh->qh_list_entry);
44199 +
44200 + /*
44201 + * Make sure the Periodic Tx FIFO Empty interrupt is
44202 + * enabled so that the periodic schedule will be
44203 + * processed.
44204 + */
44205 + gintmsk.b.ptxfempty = 1;
44206 + if (fiq_enable) {
44207 + local_fiq_disable();
44208 + fiq_fsm_spin_lock(&hcd->fiq_state->lock);
44209 + DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
44210 + fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
44211 + local_fiq_enable();
44212 + } else {
44213 + DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
44214 + }
44215 + }
44216 + }
44217 +}
44218 +
44219 +/**
44220 + * Performs common cleanup for non-periodic transfers after a Transfer
44221 + * Complete interrupt. This function should be called after any endpoint type
44222 + * specific handling is finished to release the host channel.
44223 + */
44224 +static void complete_non_periodic_xfer(dwc_otg_hcd_t * hcd,
44225 + dwc_hc_t * hc,
44226 + dwc_otg_hc_regs_t * hc_regs,
44227 + dwc_otg_qtd_t * qtd,
44228 + dwc_otg_halt_status_e halt_status)
44229 +{
44230 + hcint_data_t hcint;
44231 +
44232 + qtd->error_count = 0;
44233 +
44234 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
44235 + if (hcint.b.nyet) {
44236 + /*
44237 + * Got a NYET on the last transaction of the transfer. This
44238 + * means that the endpoint should be in the PING state at the
44239 + * beginning of the next transfer.
44240 + */
44241 + hc->qh->ping_state = 1;
44242 + clear_hc_int(hc_regs, nyet);
44243 + }
44244 +
44245 + /*
44246 + * Always halt and release the host channel to make it available for
44247 + * more transfers. There may still be more phases for a control
44248 + * transfer or more data packets for a bulk transfer at this point,
44249 + * but the host channel is still halted. A channel will be reassigned
44250 + * to the transfer when the non-periodic schedule is processed after
44251 + * the channel is released. This allows transactions to be queued
44252 + * properly via dwc_otg_hcd_queue_transactions, which also enables the
44253 + * Tx FIFO Empty interrupt if necessary.
44254 + */
44255 + if (hc->ep_is_in) {
44256 + /*
44257 + * IN transfers in Slave mode require an explicit disable to
44258 + * halt the channel. (In DMA mode, this call simply releases
44259 + * the channel.)
44260 + */
44261 + halt_channel(hcd, hc, qtd, halt_status);
44262 + } else {
44263 + /*
44264 + * The channel is automatically disabled by the core for OUT
44265 + * transfers in Slave mode.
44266 + */
44267 + release_channel(hcd, hc, qtd, halt_status);
44268 + }
44269 +}
44270 +
44271 +/**
44272 + * Performs common cleanup for periodic transfers after a Transfer Complete
44273 + * interrupt. This function should be called after any endpoint type specific
44274 + * handling is finished to release the host channel.
44275 + */
44276 +static void complete_periodic_xfer(dwc_otg_hcd_t * hcd,
44277 + dwc_hc_t * hc,
44278 + dwc_otg_hc_regs_t * hc_regs,
44279 + dwc_otg_qtd_t * qtd,
44280 + dwc_otg_halt_status_e halt_status)
44281 +{
44282 + hctsiz_data_t hctsiz;
44283 + qtd->error_count = 0;
44284 +
44285 + hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
44286 + if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {
44287 + /* Core halts channel in these cases. */
44288 + release_channel(hcd, hc, qtd, halt_status);
44289 + } else {
44290 + /* Flush any outstanding requests from the Tx queue. */
44291 + halt_channel(hcd, hc, qtd, halt_status);
44292 + }
44293 +}
44294 +
44295 +static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t * hcd,
44296 + dwc_hc_t * hc,
44297 + dwc_otg_hc_regs_t * hc_regs,
44298 + dwc_otg_qtd_t * qtd)
44299 +{
44300 + uint32_t len;
44301 + struct dwc_otg_hcd_iso_packet_desc *frame_desc;
44302 + frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
44303 +
44304 + len = get_actual_xfer_length(hc, hc_regs, qtd,
44305 + DWC_OTG_HC_XFER_COMPLETE, NULL);
44306 +
44307 + if (!len) {
44308 + qtd->complete_split = 0;
44309 + qtd->isoc_split_offset = 0;
44310 + return 0;
44311 + }
44312 + frame_desc->actual_length += len;
44313 +
44314 + if (hc->align_buff && len)
44315 + dwc_memcpy(qtd->urb->buf + frame_desc->offset +
44316 + qtd->isoc_split_offset, hc->qh->dw_align_buf, len);
44317 + qtd->isoc_split_offset += len;
44318 +
44319 + if (frame_desc->length == frame_desc->actual_length) {
44320 + frame_desc->status = 0;
44321 + qtd->isoc_frame_index++;
44322 + qtd->complete_split = 0;
44323 + qtd->isoc_split_offset = 0;
44324 + }
44325 +
44326 + if (qtd->isoc_frame_index == qtd->urb->packet_count) {
44327 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
44328 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
44329 + } else {
44330 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
44331 + }
44332 +
44333 + return 1; /* Indicates that channel released */
44334 +}
44335 +
44336 +/**
44337 + * Handles a host channel Transfer Complete interrupt. This handler may be
44338 + * called in either DMA mode or Slave mode.
44339 + */
44340 +static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t * hcd,
44341 + dwc_hc_t * hc,
44342 + dwc_otg_hc_regs_t * hc_regs,
44343 + dwc_otg_qtd_t * qtd)
44344 +{
44345 + int urb_xfer_done;
44346 + dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
44347 + dwc_otg_hcd_urb_t *urb = qtd->urb;
44348 + int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
44349 +
44350 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
44351 + "Transfer Complete--\n", hc->hc_num);
44352 +
44353 + if (hcd->core_if->dma_desc_enable) {
44354 + dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status);
44355 + if (pipe_type == UE_ISOCHRONOUS) {
44356 + /* Do not disable the interrupt, just clear it */
44357 + clear_hc_int(hc_regs, xfercomp);
44358 + return 1;
44359 + }
44360 + goto handle_xfercomp_done;
44361 + }
44362 +
44363 + /*
44364 + * Handle xfer complete on CSPLIT.
44365 + */
44366 +
44367 + if (hc->qh->do_split) {
44368 + if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in
44369 + && hcd->core_if->dma_enable) {
44370 + if (qtd->complete_split
44371 + && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs,
44372 + qtd))
44373 + goto handle_xfercomp_done;
44374 + } else {
44375 + qtd->complete_split = 0;
44376 + }
44377 + }
44378 +
44379 + /* Update the QTD and URB states. */
44380 + switch (pipe_type) {
44381 + case UE_CONTROL:
44382 + switch (qtd->control_phase) {
44383 + case DWC_OTG_CONTROL_SETUP:
44384 + if (urb->length > 0) {
44385 + qtd->control_phase = DWC_OTG_CONTROL_DATA;
44386 + } else {
44387 + qtd->control_phase = DWC_OTG_CONTROL_STATUS;
44388 + }
44389 + DWC_DEBUGPL(DBG_HCDV,
44390 + " Control setup transaction done\n");
44391 + halt_status = DWC_OTG_HC_XFER_COMPLETE;
44392 + break;
44393 + case DWC_OTG_CONTROL_DATA:{
44394 + urb_xfer_done =
44395 + update_urb_state_xfer_comp(hc, hc_regs, urb,
44396 + qtd);
44397 + if (urb_xfer_done) {
44398 + qtd->control_phase =
44399 + DWC_OTG_CONTROL_STATUS;
44400 + DWC_DEBUGPL(DBG_HCDV,
44401 + " Control data transfer done\n");
44402 + } else {
44403 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
44404 + }
44405 + halt_status = DWC_OTG_HC_XFER_COMPLETE;
44406 + break;
44407 + }
44408 + case DWC_OTG_CONTROL_STATUS:
44409 + DWC_DEBUGPL(DBG_HCDV, " Control transfer complete\n");
44410 + if (urb->status == -DWC_E_IN_PROGRESS) {
44411 + urb->status = 0;
44412 + }
44413 + hcd->fops->complete(hcd, urb->priv, urb, urb->status);
44414 + halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
44415 + break;
44416 + }
44417 +
44418 + complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
44419 + break;
44420 + case UE_BULK:
44421 + DWC_DEBUGPL(DBG_HCDV, " Bulk transfer complete\n");
44422 + urb_xfer_done =
44423 + update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
44424 + if (urb_xfer_done) {
44425 + hcd->fops->complete(hcd, urb->priv, urb, urb->status);
44426 + halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
44427 + } else {
44428 + halt_status = DWC_OTG_HC_XFER_COMPLETE;
44429 + }
44430 +
44431 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
44432 + complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
44433 + break;
44434 + case UE_INTERRUPT:
44435 + DWC_DEBUGPL(DBG_HCDV, " Interrupt transfer complete\n");
44436 + urb_xfer_done =
44437 + update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
44438 +
44439 + /*
44440 + * Interrupt URB is done on the first transfer complete
44441 + * interrupt.
44442 + */
44443 + if (urb_xfer_done) {
44444 + hcd->fops->complete(hcd, urb->priv, urb, urb->status);
44445 + halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
44446 + } else {
44447 + halt_status = DWC_OTG_HC_XFER_COMPLETE;
44448 + }
44449 +
44450 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
44451 + complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
44452 + break;
44453 + case UE_ISOCHRONOUS:
44454 + DWC_DEBUGPL(DBG_HCDV, " Isochronous transfer complete\n");
44455 + if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
44456 + halt_status =
44457 + update_isoc_urb_state(hcd, hc, hc_regs, qtd,
44458 + DWC_OTG_HC_XFER_COMPLETE);
44459 + }
44460 + complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
44461 + break;
44462 + }
44463 +
44464 +handle_xfercomp_done:
44465 + disable_hc_int(hc_regs, xfercompl);
44466 +
44467 + return 1;
44468 +}
44469 +
44470 +/**
44471 + * Handles a host channel STALL interrupt. This handler may be called in
44472 + * either DMA mode or Slave mode.
44473 + */
44474 +static int32_t handle_hc_stall_intr(dwc_otg_hcd_t * hcd,
44475 + dwc_hc_t * hc,
44476 + dwc_otg_hc_regs_t * hc_regs,
44477 + dwc_otg_qtd_t * qtd)
44478 +{
44479 + dwc_otg_hcd_urb_t *urb = qtd->urb;
44480 + int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
44481 +
44482 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
44483 + "STALL Received--\n", hc->hc_num);
44484 +
44485 + if (hcd->core_if->dma_desc_enable) {
44486 + dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_STALL);
44487 + goto handle_stall_done;
44488 + }
44489 +
44490 + if (pipe_type == UE_CONTROL) {
44491 + hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
44492 + }
44493 +
44494 + if (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) {
44495 + hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
44496 + /*
44497 + * USB protocol requires resetting the data toggle for bulk
44498 + * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
44499 + * setup command is issued to the endpoint. Anticipate the
44500 + * CLEAR_FEATURE command since a STALL has occurred and reset
44501 + * the data toggle now.
44502 + */
44503 + hc->qh->data_toggle = 0;
44504 + }
44505 +
44506 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
44507 +
44508 +handle_stall_done:
44509 + disable_hc_int(hc_regs, stall);
44510 +
44511 + return 1;
44512 +}
44513 +
44514 +/*
44515 + * Updates the state of the URB when a transfer has been stopped due to an
44516 + * abnormal condition before the transfer completes. Modifies the
44517 + * actual_length field of the URB to reflect the number of bytes that have
44518 + * actually been transferred via the host channel.
44519 + */
44520 +static void update_urb_state_xfer_intr(dwc_hc_t * hc,
44521 + dwc_otg_hc_regs_t * hc_regs,
44522 + dwc_otg_hcd_urb_t * urb,
44523 + dwc_otg_qtd_t * qtd,
44524 + dwc_otg_halt_status_e halt_status)
44525 +{
44526 + uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,
44527 + halt_status, NULL);
44528 + /* non DWORD-aligned buffer case handling. */
44529 + if (hc->align_buff && bytes_transferred && hc->ep_is_in) {
44530 + dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
44531 + bytes_transferred);
44532 + }
44533 +
44534 + urb->actual_length += bytes_transferred;
44535 +
44536 +#ifdef DEBUG
44537 + {
44538 + hctsiz_data_t hctsiz;
44539 + hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
44540 + DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
44541 + __func__, (hc->ep_is_in ? "IN" : "OUT"),
44542 + hc->hc_num);
44543 + DWC_DEBUGPL(DBG_HCDV, " hc->start_pkt_count %d\n",
44544 + hc->start_pkt_count);
44545 + DWC_DEBUGPL(DBG_HCDV, " hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
44546 + DWC_DEBUGPL(DBG_HCDV, " hc->max_packet %d\n", hc->max_packet);
44547 + DWC_DEBUGPL(DBG_HCDV, " bytes_transferred %d\n",
44548 + bytes_transferred);
44549 + DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n",
44550 + urb->actual_length);
44551 + DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n",
44552 + urb->length);
44553 + }
44554 +#endif
44555 +}
44556 +
44557 +/**
44558 + * Handles a host channel NAK interrupt. This handler may be called in either
44559 + * DMA mode or Slave mode.
44560 + */
44561 +static int32_t handle_hc_nak_intr(dwc_otg_hcd_t * hcd,
44562 + dwc_hc_t * hc,
44563 + dwc_otg_hc_regs_t * hc_regs,
44564 + dwc_otg_qtd_t * qtd)
44565 +{
44566 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
44567 + "NAK Received--\n", hc->hc_num);
44568 +
44569 + /*
44570 + * When we get bulk NAKs then remember this so we holdoff on this qh until
44571 + * the beginning of the next frame
44572 + */
44573 + switch(dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
44574 + case UE_BULK:
44575 + case UE_CONTROL:
44576 + if (nak_holdoff && qtd->qh->do_split)
44577 + hc->qh->nak_frame = dwc_otg_hcd_get_frame_number(hcd);
44578 + }
44579 +
44580 + /*
44581 + * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
44582 + * interrupt. Re-start the SSPLIT transfer.
44583 + */
44584 + if (hc->do_split) {
44585 + if (hc->complete_split) {
44586 + qtd->error_count = 0;
44587 + }
44588 + qtd->complete_split = 0;
44589 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
44590 + goto handle_nak_done;
44591 + }
44592 +
44593 + switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
44594 + case UE_CONTROL:
44595 + case UE_BULK:
44596 + if (hcd->core_if->dma_enable && hc->ep_is_in) {
44597 + /*
44598 + * NAK interrupts are enabled on bulk/control IN
44599 + * transfers in DMA mode for the sole purpose of
44600 + * resetting the error count after a transaction error
44601 + * occurs. The core will continue transferring data.
44602 + * Disable other interrupts unmasked for the same
44603 + * reason.
44604 + */
44605 + disable_hc_int(hc_regs, datatglerr);
44606 + disable_hc_int(hc_regs, ack);
44607 + qtd->error_count = 0;
44608 + goto handle_nak_done;
44609 + }
44610 +
44611 + /*
44612 + * NAK interrupts normally occur during OUT transfers in DMA
44613 + * or Slave mode. For IN transfers, more requests will be
44614 + * queued as request queue space is available.
44615 + */
44616 + qtd->error_count = 0;
44617 +
44618 + if (!hc->qh->ping_state) {
44619 + update_urb_state_xfer_intr(hc, hc_regs,
44620 + qtd->urb, qtd,
44621 + DWC_OTG_HC_XFER_NAK);
44622 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
44623 +
44624 + if (hc->speed == DWC_OTG_EP_SPEED_HIGH)
44625 + hc->qh->ping_state = 1;
44626 + }
44627 +
44628 + /*
44629 + * Halt the channel so the transfer can be re-started from
44630 + * the appropriate point or the PING protocol will
44631 + * start/continue.
44632 + */
44633 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
44634 + break;
44635 + case UE_INTERRUPT:
44636 + qtd->error_count = 0;
44637 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
44638 + break;
44639 + case UE_ISOCHRONOUS:
44640 + /* Should never get called for isochronous transfers. */
44641 + DWC_ASSERT(1, "NACK interrupt for ISOC transfer\n");
44642 + break;
44643 + }
44644 +
44645 +handle_nak_done:
44646 + disable_hc_int(hc_regs, nak);
44647 +
44648 + return 1;
44649 +}
44650 +
44651 +/**
44652 + * Handles a host channel ACK interrupt. This interrupt is enabled when
44653 + * performing the PING protocol in Slave mode, when errors occur during
44654 + * either Slave mode or DMA mode, and during Start Split transactions.
44655 + */
44656 +static int32_t handle_hc_ack_intr(dwc_otg_hcd_t * hcd,
44657 + dwc_hc_t * hc,
44658 + dwc_otg_hc_regs_t * hc_regs,
44659 + dwc_otg_qtd_t * qtd)
44660 +{
44661 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
44662 + "ACK Received--\n", hc->hc_num);
44663 +
44664 + if (hc->do_split) {
44665 + /*
44666 + * Handle ACK on SSPLIT.
44667 + * ACK should not occur in CSPLIT.
44668 + */
44669 + if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {
44670 + qtd->ssplit_out_xfer_count = hc->xfer_len;
44671 + }
44672 + if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {
44673 + /* Don't need complete for isochronous out transfers. */
44674 + qtd->complete_split = 1;
44675 + }
44676 +
44677 + /* ISOC OUT */
44678 + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
44679 + switch (hc->xact_pos) {
44680 + case DWC_HCSPLIT_XACTPOS_ALL:
44681 + break;
44682 + case DWC_HCSPLIT_XACTPOS_END:
44683 + qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
44684 + qtd->isoc_split_offset = 0;
44685 + break;
44686 + case DWC_HCSPLIT_XACTPOS_BEGIN:
44687 + case DWC_HCSPLIT_XACTPOS_MID:
44688 + /*
44689 + * For BEGIN or MID, calculate the length for
44690 + * the next microframe to determine the correct
44691 + * SSPLIT token, either MID or END.
44692 + */
44693 + {
44694 + struct dwc_otg_hcd_iso_packet_desc
44695 + *frame_desc;
44696 +
44697 + frame_desc =
44698 + &qtd->urb->
44699 + iso_descs[qtd->isoc_frame_index];
44700 + qtd->isoc_split_offset += 188;
44701 +
44702 + if ((frame_desc->length -
44703 + qtd->isoc_split_offset) <= 188) {
44704 + qtd->isoc_split_pos =
44705 + DWC_HCSPLIT_XACTPOS_END;
44706 + } else {
44707 + qtd->isoc_split_pos =
44708 + DWC_HCSPLIT_XACTPOS_MID;
44709 + }
44710 +
44711 + }
44712 + break;
44713 + }
44714 + } else {
44715 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
44716 + }
44717 + } else {
44718 + /*
44719 + * An unmasked ACK on a non-split DMA transaction is
44720 + * for the sole purpose of resetting error counts. Disable other
44721 + * interrupts unmasked for the same reason.
44722 + */
44723 + if(hcd->core_if->dma_enable) {
44724 + disable_hc_int(hc_regs, datatglerr);
44725 + disable_hc_int(hc_regs, nak);
44726 + }
44727 + qtd->error_count = 0;
44728 +
44729 + if (hc->qh->ping_state) {
44730 + hc->qh->ping_state = 0;
44731 + /*
44732 + * Halt the channel so the transfer can be re-started
44733 + * from the appropriate point. This only happens in
44734 + * Slave mode. In DMA mode, the ping_state is cleared
44735 + * when the transfer is started because the core
44736 + * automatically executes the PING, then the transfer.
44737 + */
44738 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
44739 + }
44740 + }
44741 +
44742 + /*
44743 + * If the ACK occurred when _not_ in the PING state, let the channel
44744 + * continue transferring data after clearing the error count.
44745 + */
44746 +
44747 + disable_hc_int(hc_regs, ack);
44748 +
44749 + return 1;
44750 +}
44751 +
44752 +/**
44753 + * Handles a host channel NYET interrupt. This interrupt should only occur on
44754 + * Bulk and Control OUT endpoints and for complete split transactions. If a
44755 + * NYET occurs at the same time as a Transfer Complete interrupt, it is
44756 + * handled in the xfercomp interrupt handler, not here. This handler may be
44757 + * called in either DMA mode or Slave mode.
44758 + */
44759 +static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t * hcd,
44760 + dwc_hc_t * hc,
44761 + dwc_otg_hc_regs_t * hc_regs,
44762 + dwc_otg_qtd_t * qtd)
44763 +{
44764 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
44765 + "NYET Received--\n", hc->hc_num);
44766 +
44767 + /*
44768 + * NYET on CSPLIT
44769 + * re-do the CSPLIT immediately on non-periodic
44770 + */
44771 + if (hc->do_split && hc->complete_split) {
44772 + if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
44773 + && hcd->core_if->dma_enable) {
44774 + qtd->complete_split = 0;
44775 + qtd->isoc_split_offset = 0;
44776 + if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
44777 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
44778 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
44779 + }
44780 + else
44781 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
44782 + goto handle_nyet_done;
44783 + }
44784 +
44785 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
44786 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
44787 + int frnum = dwc_otg_hcd_get_frame_number(hcd);
44788 +
44789 + // With the FIQ running we only ever see the failed NYET
44790 + if (dwc_full_frame_num(frnum) !=
44791 + dwc_full_frame_num(hc->qh->sched_frame) ||
44792 + fiq_fsm_enable) {
44793 + /*
44794 + * No longer in the same full speed frame.
44795 + * Treat this as a transaction error.
44796 + */
44797 +#if 0
44798 + /** @todo Fix system performance so this can
44799 + * be treated as an error. Right now complete
44800 + * splits cannot be scheduled precisely enough
44801 + * due to other system activity, so this error
44802 + * occurs regularly in Slave mode.
44803 + */
44804 + qtd->error_count++;
44805 +#endif
44806 + qtd->complete_split = 0;
44807 + halt_channel(hcd, hc, qtd,
44808 + DWC_OTG_HC_XFER_XACT_ERR);
44809 + /** @todo add support for isoc release */
44810 + goto handle_nyet_done;
44811 + }
44812 + }
44813 +
44814 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
44815 + goto handle_nyet_done;
44816 + }
44817 +
44818 + hc->qh->ping_state = 1;
44819 + qtd->error_count = 0;
44820 +
44821 + update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,
44822 + DWC_OTG_HC_XFER_NYET);
44823 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
44824 +
44825 + /*
44826 + * Halt the channel and re-start the transfer so the PING
44827 + * protocol will start.
44828 + */
44829 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
44830 +
44831 +handle_nyet_done:
44832 + disable_hc_int(hc_regs, nyet);
44833 + return 1;
44834 +}
44835 +
44836 +/**
44837 + * Handles a host channel babble interrupt. This handler may be called in
44838 + * either DMA mode or Slave mode.
44839 + */
44840 +static int32_t handle_hc_babble_intr(dwc_otg_hcd_t * hcd,
44841 + dwc_hc_t * hc,
44842 + dwc_otg_hc_regs_t * hc_regs,
44843 + dwc_otg_qtd_t * qtd)
44844 +{
44845 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
44846 + "Babble Error--\n", hc->hc_num);
44847 +
44848 + if (hcd->core_if->dma_desc_enable) {
44849 + dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
44850 + DWC_OTG_HC_XFER_BABBLE_ERR);
44851 + goto handle_babble_done;
44852 + }
44853 +
44854 + if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
44855 + hcd->fops->complete(hcd, qtd->urb->priv,
44856 + qtd->urb, -DWC_E_OVERFLOW);
44857 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
44858 + } else {
44859 + dwc_otg_halt_status_e halt_status;
44860 + halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
44861 + DWC_OTG_HC_XFER_BABBLE_ERR);
44862 + halt_channel(hcd, hc, qtd, halt_status);
44863 + }
44864 +
44865 +handle_babble_done:
44866 + disable_hc_int(hc_regs, bblerr);
44867 + return 1;
44868 +}
44869 +
44870 +/**
44871 + * Handles a host channel AHB error interrupt. This handler is only called in
44872 + * DMA mode.
44873 + */
44874 +static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t * hcd,
44875 + dwc_hc_t * hc,
44876 + dwc_otg_hc_regs_t * hc_regs,
44877 + dwc_otg_qtd_t * qtd)
44878 +{
44879 + hcchar_data_t hcchar;
44880 + hcsplt_data_t hcsplt;
44881 + hctsiz_data_t hctsiz;
44882 + uint32_t hcdma;
44883 + char *pipetype, *speed;
44884 +
44885 + dwc_otg_hcd_urb_t *urb = qtd->urb;
44886 +
44887 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
44888 + "AHB Error--\n", hc->hc_num);
44889 +
44890 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
44891 + hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
44892 + hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
44893 + hcdma = DWC_READ_REG32(&hc_regs->hcdma);
44894 +
44895 + DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num);
44896 + DWC_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
44897 + DWC_ERROR(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
44898 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
44899 + DWC_ERROR(" Device address: %d\n",
44900 + dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
44901 + DWC_ERROR(" Endpoint: %d, %s\n",
44902 + dwc_otg_hcd_get_ep_num(&urb->pipe_info),
44903 + (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"));
44904 +
44905 + switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
44906 + case UE_CONTROL:
44907 + pipetype = "CONTROL";
44908 + break;
44909 + case UE_BULK:
44910 + pipetype = "BULK";
44911 + break;
44912 + case UE_INTERRUPT:
44913 + pipetype = "INTERRUPT";
44914 + break;
44915 + case UE_ISOCHRONOUS:
44916 + pipetype = "ISOCHRONOUS";
44917 + break;
44918 + default:
44919 + pipetype = "UNKNOWN";
44920 + break;
44921 + }
44922 +
44923 + DWC_ERROR(" Endpoint type: %s\n", pipetype);
44924 +
44925 + switch (hc->speed) {
44926 + case DWC_OTG_EP_SPEED_HIGH:
44927 + speed = "HIGH";
44928 + break;
44929 + case DWC_OTG_EP_SPEED_FULL:
44930 + speed = "FULL";
44931 + break;
44932 + case DWC_OTG_EP_SPEED_LOW:
44933 + speed = "LOW";
44934 + break;
44935 + default:
44936 + speed = "UNKNOWN";
44937 + break;
44938 + };
44939 +
44940 + DWC_ERROR(" Speed: %s\n", speed);
44941 +
44942 + DWC_ERROR(" Max packet size: %d\n",
44943 + dwc_otg_hcd_get_mps(&urb->pipe_info));
44944 + DWC_ERROR(" Data buffer length: %d\n", urb->length);
44945 + DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n",
44946 + urb->buf, (void *)urb->dma);
44947 + DWC_ERROR(" Setup buffer: %p, Setup DMA: %p\n",
44948 + urb->setup_packet, (void *)urb->setup_dma);
44949 + DWC_ERROR(" Interval: %d\n", urb->interval);
44950 +
44951 + /* Core haltes the channel for Descriptor DMA mode */
44952 + if (hcd->core_if->dma_desc_enable) {
44953 + dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
44954 + DWC_OTG_HC_XFER_AHB_ERR);
44955 + goto handle_ahberr_done;
44956 + }
44957 +
44958 + hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_IO);
44959 +
44960 + /*
44961 + * Force a channel halt. Don't call halt_channel because that won't
44962 + * write to the HCCHARn register in DMA mode to force the halt.
44963 + */
44964 + dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
44965 +handle_ahberr_done:
44966 + disable_hc_int(hc_regs, ahberr);
44967 + return 1;
44968 +}
44969 +
44970 +/**
44971 + * Handles a host channel transaction error interrupt. This handler may be
44972 + * called in either DMA mode or Slave mode.
44973 + */
44974 +static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t * hcd,
44975 + dwc_hc_t * hc,
44976 + dwc_otg_hc_regs_t * hc_regs,
44977 + dwc_otg_qtd_t * qtd)
44978 +{
44979 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
44980 + "Transaction Error--\n", hc->hc_num);
44981 +
44982 + if (hcd->core_if->dma_desc_enable) {
44983 + dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
44984 + DWC_OTG_HC_XFER_XACT_ERR);
44985 + goto handle_xacterr_done;
44986 + }
44987 +
44988 + switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
44989 + case UE_CONTROL:
44990 + case UE_BULK:
44991 + qtd->error_count++;
44992 + if (!hc->qh->ping_state) {
44993 +
44994 + update_urb_state_xfer_intr(hc, hc_regs,
44995 + qtd->urb, qtd,
44996 + DWC_OTG_HC_XFER_XACT_ERR);
44997 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
44998 + if (!hc->ep_is_in && hc->speed == DWC_OTG_EP_SPEED_HIGH) {
44999 + hc->qh->ping_state = 1;
45000 + }
45001 + }
45002 +
45003 + /*
45004 + * Halt the channel so the transfer can be re-started from
45005 + * the appropriate point or the PING protocol will start.
45006 + */
45007 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
45008 + break;
45009 + case UE_INTERRUPT:
45010 + qtd->error_count++;
45011 + if (hc->do_split && hc->complete_split) {
45012 + qtd->complete_split = 0;
45013 + }
45014 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
45015 + break;
45016 + case UE_ISOCHRONOUS:
45017 + {
45018 + dwc_otg_halt_status_e halt_status;
45019 + halt_status =
45020 + update_isoc_urb_state(hcd, hc, hc_regs, qtd,
45021 + DWC_OTG_HC_XFER_XACT_ERR);
45022 +
45023 + halt_channel(hcd, hc, qtd, halt_status);
45024 + }
45025 + break;
45026 + }
45027 +handle_xacterr_done:
45028 + disable_hc_int(hc_regs, xacterr);
45029 +
45030 + return 1;
45031 +}
45032 +
45033 +/**
45034 + * Handles a host channel frame overrun interrupt. This handler may be called
45035 + * in either DMA mode or Slave mode.
45036 + */
45037 +static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t * hcd,
45038 + dwc_hc_t * hc,
45039 + dwc_otg_hc_regs_t * hc_regs,
45040 + dwc_otg_qtd_t * qtd)
45041 +{
45042 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
45043 + "Frame Overrun--\n", hc->hc_num);
45044 +
45045 + switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
45046 + case UE_CONTROL:
45047 + case UE_BULK:
45048 + break;
45049 + case UE_INTERRUPT:
45050 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
45051 + break;
45052 + case UE_ISOCHRONOUS:
45053 + {
45054 + dwc_otg_halt_status_e halt_status;
45055 + halt_status =
45056 + update_isoc_urb_state(hcd, hc, hc_regs, qtd,
45057 + DWC_OTG_HC_XFER_FRAME_OVERRUN);
45058 +
45059 + halt_channel(hcd, hc, qtd, halt_status);
45060 + }
45061 + break;
45062 + }
45063 +
45064 + disable_hc_int(hc_regs, frmovrun);
45065 +
45066 + return 1;
45067 +}
45068 +
45069 +/**
45070 + * Handles a host channel data toggle error interrupt. This handler may be
45071 + * called in either DMA mode or Slave mode.
45072 + */
45073 +static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t * hcd,
45074 + dwc_hc_t * hc,
45075 + dwc_otg_hc_regs_t * hc_regs,
45076 + dwc_otg_qtd_t * qtd)
45077 +{
45078 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
45079 + "Data Toggle Error on %s transfer--\n",
45080 + hc->hc_num, (hc->ep_is_in ? "IN" : "OUT"));
45081 +
45082 + /* Data toggles on split transactions cause the hc to halt.
45083 + * restart transfer */
45084 + if(hc->qh->do_split)
45085 + {
45086 + qtd->error_count++;
45087 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
45088 + update_urb_state_xfer_intr(hc, hc_regs,
45089 + qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);
45090 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
45091 + } else if (hc->ep_is_in) {
45092 + /* An unmasked data toggle error on a non-split DMA transaction is
45093 + * for the sole purpose of resetting error counts. Disable other
45094 + * interrupts unmasked for the same reason.
45095 + */
45096 + if(hcd->core_if->dma_enable) {
45097 + disable_hc_int(hc_regs, ack);
45098 + disable_hc_int(hc_regs, nak);
45099 + }
45100 + qtd->error_count = 0;
45101 + }
45102 +
45103 + disable_hc_int(hc_regs, datatglerr);
45104 +
45105 + return 1;
45106 +}
45107 +
45108 +#ifdef DEBUG
45109 +/**
45110 + * This function is for debug only. It checks that a valid halt status is set
45111 + * and that HCCHARn.chdis is clear. If there's a problem, corrective action is
45112 + * taken and a warning is issued.
45113 + * @return 1 if halt status is ok, 0 otherwise.
45114 + */
45115 +static inline int halt_status_ok(dwc_otg_hcd_t * hcd,
45116 + dwc_hc_t * hc,
45117 + dwc_otg_hc_regs_t * hc_regs,
45118 + dwc_otg_qtd_t * qtd)
45119 +{
45120 + hcchar_data_t hcchar;
45121 + hctsiz_data_t hctsiz;
45122 + hcint_data_t hcint;
45123 + hcintmsk_data_t hcintmsk;
45124 + hcsplt_data_t hcsplt;
45125 +
45126 + if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
45127 + /*
45128 + * This code is here only as a check. This condition should
45129 + * never happen. Ignore the halt if it does occur.
45130 + */
45131 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
45132 + hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
45133 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
45134 + hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
45135 + hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
45136 + DWC_WARN
45137 + ("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "
45138 + "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
45139 + "hcint 0x%08x, hcintmsk 0x%08x, "
45140 + "hcsplt 0x%08x, qtd->complete_split %d\n", __func__,
45141 + hc->hc_num, hcchar.d32, hctsiz.d32, hcint.d32,
45142 + hcintmsk.d32, hcsplt.d32, qtd->complete_split);
45143 +
45144 + DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
45145 + __func__, hc->hc_num);
45146 + DWC_WARN("\n");
45147 + clear_hc_int(hc_regs, chhltd);
45148 + return 0;
45149 + }
45150 +
45151 + /*
45152 + * This code is here only as a check. hcchar.chdis should
45153 + * never be set when the halt interrupt occurs. Halt the
45154 + * channel again if it does occur.
45155 + */
45156 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
45157 + if (hcchar.b.chdis) {
45158 + DWC_WARN("%s: hcchar.chdis set unexpectedly, "
45159 + "hcchar 0x%08x, trying to halt again\n",
45160 + __func__, hcchar.d32);
45161 + clear_hc_int(hc_regs, chhltd);
45162 + hc->halt_pending = 0;
45163 + halt_channel(hcd, hc, qtd, hc->halt_status);
45164 + return 0;
45165 + }
45166 +
45167 + return 1;
45168 +}
45169 +#endif
45170 +
45171 +/**
45172 + * Handles a host Channel Halted interrupt in DMA mode. This handler
45173 + * determines the reason the channel halted and proceeds accordingly.
45174 + */
45175 +static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd,
45176 + dwc_hc_t * hc,
45177 + dwc_otg_hc_regs_t * hc_regs,
45178 + dwc_otg_qtd_t * qtd)
45179 +{
45180 + int out_nak_enh = 0;
45181 + hcint_data_t hcint;
45182 + hcintmsk_data_t hcintmsk;
45183 + /* For core with OUT NAK enhancement, the flow for high-
45184 + * speed CONTROL/BULK OUT is handled a little differently.
45185 + */
45186 + if (hcd->core_if->snpsid >= OTG_CORE_REV_2_71a) {
45187 + if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
45188 + (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
45189 + hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
45190 + out_nak_enh = 1;
45191 + }
45192 + }
45193 +
45194 + if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
45195 + (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR
45196 + && !hcd->core_if->dma_desc_enable)) {
45197 + /*
45198 + * Just release the channel. A dequeue can happen on a
45199 + * transfer timeout. In the case of an AHB Error, the channel
45200 + * was forced to halt because there's no way to gracefully
45201 + * recover.
45202 + */
45203 + if (hcd->core_if->dma_desc_enable)
45204 + dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
45205 + hc->halt_status);
45206 + else
45207 + release_channel(hcd, hc, qtd, hc->halt_status);
45208 + return;
45209 + }
45210 +
45211 + /* Read the HCINTn register to determine the cause for the halt. */
45212 +
45213 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
45214 + hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
45215 +
45216 + if (hcint.b.xfercomp) {
45217 + /** @todo This is here because of a possible hardware bug. Spec
45218 + * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
45219 + * interrupt w/ACK bit set should occur, but I only see the
45220 + * XFERCOMP bit, even with it masked out. This is a workaround
45221 + * for that behavior. Should fix this when hardware is fixed.
45222 + */
45223 + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
45224 + handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
45225 + }
45226 + handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
45227 + } else if (hcint.b.stall) {
45228 + handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
45229 + } else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) {
45230 + if (out_nak_enh) {
45231 + if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
45232 + DWC_DEBUGPL(DBG_HCD, "XactErr with NYET/NAK/ACK\n");
45233 + qtd->error_count = 0;
45234 + } else {
45235 + DWC_DEBUGPL(DBG_HCD, "XactErr without NYET/NAK/ACK\n");
45236 + }
45237 + }
45238 +
45239 + /*
45240 + * Must handle xacterr before nak or ack. Could get a xacterr
45241 + * at the same time as either of these on a BULK/CONTROL OUT
45242 + * that started with a PING. The xacterr takes precedence.
45243 + */
45244 + handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
45245 + } else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) {
45246 + handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
45247 + } else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) {
45248 + handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
45249 + } else if (hcint.b.bblerr) {
45250 + handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
45251 + } else if (hcint.b.frmovrun) {
45252 + handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
45253 + } else if (hcint.b.datatglerr) {
45254 + handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd);
45255 + } else if (!out_nak_enh) {
45256 + if (hcint.b.nyet) {
45257 + /*
45258 + * Must handle nyet before nak or ack. Could get a nyet at the
45259 + * same time as either of those on a BULK/CONTROL OUT that
45260 + * started with a PING. The nyet takes precedence.
45261 + */
45262 + handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
45263 + } else if (hcint.b.nak && !hcintmsk.b.nak) {
45264 + /*
45265 + * If nak is not masked, it's because a non-split IN transfer
45266 + * is in an error state. In that case, the nak is handled by
45267 + * the nak interrupt handler, not here. Handle nak here for
45268 + * BULK/CONTROL OUT transfers, which halt on a NAK to allow
45269 + * rewinding the buffer pointer.
45270 + */
45271 + handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
45272 + } else if (hcint.b.ack && !hcintmsk.b.ack) {
45273 + /*
45274 + * If ack is not masked, it's because a non-split IN transfer
45275 + * is in an error state. In that case, the ack is handled by
45276 + * the ack interrupt handler, not here. Handle ack here for
45277 + * split transfers. Start splits halt on ACK.
45278 + */
45279 + handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
45280 + } else {
45281 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
45282 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
45283 + /*
45284 + * A periodic transfer halted with no other channel
45285 + * interrupts set. Assume it was halted by the core
45286 + * because it could not be completed in its scheduled
45287 + * (micro)frame.
45288 + */
45289 +#ifdef DEBUG
45290 + DWC_PRINTF
45291 + ("%s: Halt channel %d (assume incomplete periodic transfer)\n",
45292 + __func__, hc->hc_num);
45293 +#endif
45294 + halt_channel(hcd, hc, qtd,
45295 + DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
45296 + } else {
45297 + DWC_ERROR
45298 + ("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
45299 + "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
45300 + __func__, hc->hc_num, hcint.d32,
45301 + DWC_READ_REG32(&hcd->
45302 + core_if->core_global_regs->
45303 + gintsts));
45304 + /* Failthrough: use 3-strikes rule */
45305 + qtd->error_count++;
45306 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
45307 + update_urb_state_xfer_intr(hc, hc_regs,
45308 + qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);
45309 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
45310 + }
45311 +
45312 + }
45313 + } else {
45314 + DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n",
45315 + hcint.d32);
45316 + /* Failthrough: use 3-strikes rule */
45317 + qtd->error_count++;
45318 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
45319 + update_urb_state_xfer_intr(hc, hc_regs,
45320 + qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);
45321 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
45322 + }
45323 +}
45324 +
45325 +/**
45326 + * Handles a host channel Channel Halted interrupt.
45327 + *
45328 + * In slave mode, this handler is called only when the driver specifically
45329 + * requests a halt. This occurs during handling other host channel interrupts
45330 + * (e.g. nak, xacterr, stall, nyet, etc.).
45331 + *
45332 + * In DMA mode, this is the interrupt that occurs when the core has finished
45333 + * processing a transfer on a channel. Other host channel interrupts (except
45334 + * ahberr) are disabled in DMA mode.
45335 + */
45336 +static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t * hcd,
45337 + dwc_hc_t * hc,
45338 + dwc_otg_hc_regs_t * hc_regs,
45339 + dwc_otg_qtd_t * qtd)
45340 +{
45341 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
45342 + "Channel Halted--\n", hc->hc_num);
45343 +
45344 + if (hcd->core_if->dma_enable) {
45345 + handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);
45346 + } else {
45347 +#ifdef DEBUG
45348 + if (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
45349 + return 1;
45350 + }
45351 +#endif
45352 + release_channel(hcd, hc, qtd, hc->halt_status);
45353 + }
45354 +
45355 + return 1;
45356 +}
45357 +
45358 +
45359 +/**
45360 + * dwc_otg_fiq_unmangle_isoc() - Update the iso_frame_desc structure on
45361 + * FIQ transfer completion
45362 + * @hcd: Pointer to dwc_otg_hcd struct
45363 + * @num: Host channel number
45364 + *
45365 + * 1. Un-mangle the status as recorded in each iso_frame_desc status
45366 + * 2. Copy it from the dwc_otg_urb into the real URB
45367 + */
45368 +void dwc_otg_fiq_unmangle_isoc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num)
45369 +{
45370 + struct dwc_otg_hcd_urb *dwc_urb = qtd->urb;
45371 + int nr_frames = dwc_urb->packet_count;
45372 + int i;
45373 + hcint_data_t frame_hcint;
45374 +
45375 + for (i = 0; i < nr_frames; i++) {
45376 + frame_hcint.d32 = dwc_urb->iso_descs[i].status;
45377 + if (frame_hcint.b.xfercomp) {
45378 + dwc_urb->iso_descs[i].status = 0;
45379 + dwc_urb->actual_length += dwc_urb->iso_descs[i].actual_length;
45380 + } else if (frame_hcint.b.frmovrun) {
45381 + if (qh->ep_is_in)
45382 + dwc_urb->iso_descs[i].status = -DWC_E_NO_STREAM_RES;
45383 + else
45384 + dwc_urb->iso_descs[i].status = -DWC_E_COMMUNICATION;
45385 + dwc_urb->error_count++;
45386 + dwc_urb->iso_descs[i].actual_length = 0;
45387 + } else if (frame_hcint.b.xacterr) {
45388 + dwc_urb->iso_descs[i].status = -DWC_E_PROTOCOL;
45389 + dwc_urb->error_count++;
45390 + dwc_urb->iso_descs[i].actual_length = 0;
45391 + } else if (frame_hcint.b.bblerr) {
45392 + dwc_urb->iso_descs[i].status = -DWC_E_OVERFLOW;
45393 + dwc_urb->error_count++;
45394 + dwc_urb->iso_descs[i].actual_length = 0;
45395 + } else {
45396 + /* Something went wrong */
45397 + dwc_urb->iso_descs[i].status = -1;
45398 + dwc_urb->iso_descs[i].actual_length = 0;
45399 + dwc_urb->error_count++;
45400 + }
45401 + }
45402 + //printk_ratelimited(KERN_INFO "%s: HS isochronous of %d/%d frames with %d errors complete\n",
45403 + // __FUNCTION__, i, dwc_urb->packet_count, dwc_urb->error_count);
45404 + hcd->fops->complete(hcd, dwc_urb->priv, dwc_urb, 0);
45405 + release_channel(hcd, qh->channel, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
45406 +}
45407 +
45408 +/**
45409 + * dwc_otg_fiq_unsetup_per_dma() - Remove data from bounce buffers for split transactions
45410 + * @hcd: Pointer to dwc_otg_hcd struct
45411 + * @num: Host channel number
45412 + *
45413 + * Copies data from the FIQ bounce buffers into the URB's transfer buffer. Does not modify URB state.
45414 + * Returns total length of data or -1 if the buffers were not used.
45415 + *
45416 + */
45417 +int dwc_otg_fiq_unsetup_per_dma(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num)
45418 +{
45419 + dwc_hc_t *hc = qh->channel;
45420 + struct fiq_dma_blob *blob = hcd->fiq_dmab;
45421 + struct fiq_channel_state *st = &hcd->fiq_state->channel[num];
45422 + uint8_t *ptr = NULL;
45423 + int index = 0, len = 0;
45424 + int i = 0;
45425 + if (hc->ep_is_in) {
45426 + /* Copy data out of the DMA bounce buffers to the URB's buffer.
45427 + * The align_buf is ignored as this is ignored on FSM enqueue. */
45428 + ptr = qtd->urb->buf;
45429 + if (qh->ep_type == UE_ISOCHRONOUS) {
45430 + /* Isoc IN transactions - grab the offset of the iso_frame_desc into the URB transfer buffer */
45431 + index = qtd->isoc_frame_index;
45432 + ptr += qtd->urb->iso_descs[index].offset;
45433 + } else {
45434 + /* Need to increment by actual_length for interrupt IN */
45435 + ptr += qtd->urb->actual_length;
45436 + }
45437 +
45438 + for (i = 0; i < st->dma_info.index; i++) {
45439 + len += st->dma_info.slot_len[i];
45440 + dwc_memcpy(ptr, &blob->channel[num].index[i].buf[0], st->dma_info.slot_len[i]);
45441 + ptr += st->dma_info.slot_len[i];
45442 + }
45443 + return len;
45444 + } else {
45445 + /* OUT endpoints - nothing to do. */
45446 + return -1;
45447 + }
45448 +
45449 +}
45450 +/**
45451 + * dwc_otg_hcd_handle_hc_fsm() - handle an unmasked channel interrupt
45452 + * from a channel handled in the FIQ
45453 + * @hcd: Pointer to dwc_otg_hcd struct
45454 + * @num: Host channel number
45455 + *
45456 + * If a host channel interrupt was received by the IRQ and this was a channel
45457 + * used by the FIQ, the execution flow for transfer completion is substantially
45458 + * different from the normal (messy) path. This function and its friends handles
45459 + * channel cleanup and transaction completion from a FIQ transaction.
45460 + */
45461 +void dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd_t *hcd, uint32_t num)
45462 +{
45463 + struct fiq_channel_state *st = &hcd->fiq_state->channel[num];
45464 + dwc_hc_t *hc = hcd->hc_ptr_array[num];
45465 + dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
45466 + dwc_otg_qh_t *qh = hc->qh;
45467 + dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[num];
45468 + hcint_data_t hcint = hcd->fiq_state->channel[num].hcint_copy;
45469 + int hostchannels = 0;
45470 + fiq_print(FIQDBG_INT, hcd->fiq_state, "OUT %01d %01d ", num , st->fsm);
45471 +
45472 + hostchannels = hcd->available_host_channels;
45473 + switch (st->fsm) {
45474 + case FIQ_TEST:
45475 + break;
45476 +
45477 + case FIQ_DEQUEUE_ISSUED:
45478 + /* hc_halt was called. QTD no longer exists. */
45479 + /* TODO: for a nonperiodic split transaction, need to issue a
45480 + * CLEAR_TT_BUFFER hub command if we were in the start-split phase.
45481 + */
45482 + release_channel(hcd, hc, NULL, hc->halt_status);
45483 + break;
45484 +
45485 + case FIQ_NP_SPLIT_DONE:
45486 + /* Nonperiodic transaction complete. */
45487 + if (!hc->ep_is_in) {
45488 + qtd->ssplit_out_xfer_count = hc->xfer_len;
45489 + }
45490 + if (hcint.b.xfercomp) {
45491 + handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
45492 + } else if (hcint.b.nak) {
45493 + handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
45494 + }
45495 + break;
45496 +
45497 + case FIQ_NP_SPLIT_HS_ABORTED:
45498 + /* A HS abort is a 3-strikes on the HS bus at any point in the transaction.
45499 + * Normally a CLEAR_TT_BUFFER hub command would be required: we can't do that
45500 + * because there's no guarantee which order a non-periodic split happened in.
45501 + * We could end up clearing a perfectly good transaction out of the buffer.
45502 + */
45503 + if (hcint.b.xacterr) {
45504 + qtd->error_count += st->nr_errors;
45505 + handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
45506 + } else if (hcint.b.ahberr) {
45507 + handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
45508 + } else {
45509 + local_fiq_disable();
45510 + BUG();
45511 + }
45512 + break;
45513 +
45514 + case FIQ_NP_SPLIT_LS_ABORTED:
45515 + /* A few cases can cause this - either an unknown state on a SSPLIT or
45516 + * STALL/data toggle error response on a CSPLIT */
45517 + if (hcint.b.stall) {
45518 + handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
45519 + } else if (hcint.b.datatglerr) {
45520 + handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd);
45521 + } else if (hcint.b.bblerr) {
45522 + handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
45523 + } else if (hcint.b.ahberr) {
45524 + handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
45525 + } else {
45526 + local_fiq_disable();
45527 + BUG();
45528 + }
45529 + break;
45530 +
45531 + case FIQ_PER_SPLIT_DONE:
45532 + /* Isoc IN or Interrupt IN/OUT */
45533 +
45534 + /* Flow control here is different from the normal execution by the driver.
45535 + * We need to completely ignore most of the driver's method of handling
45536 + * split transactions and do it ourselves.
45537 + */
45538 + if (hc->ep_type == UE_INTERRUPT) {
45539 + if (hcint.b.nak) {
45540 + handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
45541 + } else if (hc->ep_is_in) {
45542 + int len;
45543 + len = dwc_otg_fiq_unsetup_per_dma(hcd, hc->qh, qtd, num);
45544 + //printk(KERN_NOTICE "FIQ Transaction: hc=%d len=%d urb_len = %d\n", num, len, qtd->urb->length);
45545 + qtd->urb->actual_length += len;
45546 + if (qtd->urb->actual_length >= qtd->urb->length) {
45547 + qtd->urb->status = 0;
45548 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status);
45549 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
45550 + } else {
45551 + /* Interrupt transfer not complete yet - is it a short read? */
45552 + if (len < hc->max_packet) {
45553 + /* Interrupt transaction complete */
45554 + qtd->urb->status = 0;
45555 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status);
45556 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
45557 + } else {
45558 + /* Further transactions required */
45559 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
45560 + }
45561 + }
45562 + } else {
45563 + /* Interrupt OUT complete. */
45564 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
45565 + qtd->urb->actual_length += hc->xfer_len;
45566 + if (qtd->urb->actual_length >= qtd->urb->length) {
45567 + qtd->urb->status = 0;
45568 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status);
45569 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
45570 + } else {
45571 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
45572 + }
45573 + }
45574 + } else {
45575 + /* ISOC IN complete. */
45576 + struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
45577 + int len = 0;
45578 + /* Record errors, update qtd. */
45579 + if (st->nr_errors) {
45580 + frame_desc->actual_length = 0;
45581 + frame_desc->status = -DWC_E_PROTOCOL;
45582 + } else {
45583 + frame_desc->status = 0;
45584 + /* Unswizzle dma */
45585 + len = dwc_otg_fiq_unsetup_per_dma(hcd, qh, qtd, num);
45586 + frame_desc->actual_length = len;
45587 + }
45588 + qtd->isoc_frame_index++;
45589 + if (qtd->isoc_frame_index == qtd->urb->packet_count) {
45590 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
45591 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
45592 + } else {
45593 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
45594 + }
45595 + }
45596 + break;
45597 +
45598 + case FIQ_PER_ISO_OUT_DONE: {
45599 + struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
45600 + /* Record errors, update qtd. */
45601 + if (st->nr_errors) {
45602 + frame_desc->actual_length = 0;
45603 + frame_desc->status = -DWC_E_PROTOCOL;
45604 + } else {
45605 + frame_desc->status = 0;
45606 + frame_desc->actual_length = frame_desc->length;
45607 + }
45608 + qtd->isoc_frame_index++;
45609 + qtd->isoc_split_offset = 0;
45610 + if (qtd->isoc_frame_index == qtd->urb->packet_count) {
45611 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
45612 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
45613 + } else {
45614 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
45615 + }
45616 + }
45617 + break;
45618 +
45619 + case FIQ_PER_SPLIT_NYET_ABORTED:
45620 + /* Doh. lost the data. */
45621 + printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x frame %d failed "
45622 + "- FIQ reported NYET. Data may have been lost.\n",
45623 + hc->dev_addr, hc->ep_num, dwc_otg_hcd_get_frame_number(hcd) >> 3);
45624 + if (hc->ep_type == UE_ISOCHRONOUS) {
45625 + struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
45626 + /* Record errors, update qtd. */
45627 + frame_desc->actual_length = 0;
45628 + frame_desc->status = -DWC_E_PROTOCOL;
45629 + qtd->isoc_frame_index++;
45630 + qtd->isoc_split_offset = 0;
45631 + if (qtd->isoc_frame_index == qtd->urb->packet_count) {
45632 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
45633 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
45634 + } else {
45635 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
45636 + }
45637 + } else {
45638 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
45639 + }
45640 + break;
45641 +
45642 + case FIQ_HS_ISOC_DONE:
45643 + /* The FIQ has performed a whole pile of isochronous transactions.
45644 + * The status is recorded as the interrupt state should the transaction
45645 + * fail.
45646 + */
45647 + dwc_otg_fiq_unmangle_isoc(hcd, qh, qtd, num);
45648 + break;
45649 +
45650 + case FIQ_PER_SPLIT_LS_ABORTED:
45651 + if (hcint.b.xacterr) {
45652 + /* Hub has responded with an ERR packet. Device
45653 + * has been unplugged or the port has been disabled.
45654 + * TODO: need to issue a reset to the hub port. */
45655 + qtd->error_count += 3;
45656 + handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
45657 + } else if (hcint.b.stall) {
45658 + handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
45659 + } else if (hcint.b.bblerr) {
45660 + handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
45661 + } else {
45662 + printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x failed "
45663 + "- FIQ reported FSM=%d. Data may have been lost.\n",
45664 + st->fsm, hc->dev_addr, hc->ep_num);
45665 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
45666 + }
45667 + break;
45668 +
45669 + case FIQ_PER_SPLIT_HS_ABORTED:
45670 + /* Either the SSPLIT phase suffered transaction errors or something
45671 + * unexpected happened.
45672 + */
45673 + qtd->error_count += 3;
45674 + handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
45675 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
45676 + break;
45677 +
45678 + case FIQ_PER_SPLIT_TIMEOUT:
45679 + /* Couldn't complete in the nominated frame */
45680 + printk(KERN_INFO "Transfer to device %d endpoint 0x%x frame %d failed "
45681 + "- FIQ timed out. Data may have been lost.\n",
45682 + hc->dev_addr, hc->ep_num, dwc_otg_hcd_get_frame_number(hcd) >> 3);
45683 + if (hc->ep_type == UE_ISOCHRONOUS) {
45684 + struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
45685 + /* Record errors, update qtd. */
45686 + frame_desc->actual_length = 0;
45687 + if (hc->ep_is_in) {
45688 + frame_desc->status = -DWC_E_NO_STREAM_RES;
45689 + } else {
45690 + frame_desc->status = -DWC_E_COMMUNICATION;
45691 + }
45692 + qtd->isoc_frame_index++;
45693 + if (qtd->isoc_frame_index == qtd->urb->packet_count) {
45694 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
45695 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
45696 + } else {
45697 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
45698 + }
45699 + } else {
45700 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
45701 + }
45702 + break;
45703 +
45704 + default:
45705 + DWC_WARN("Unexpected state received on hc=%d fsm=%d on transfer to device %d ep 0x%x",
45706 + hc->hc_num, st->fsm, hc->dev_addr, hc->ep_num);
45707 + qtd->error_count++;
45708 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
45709 + }
45710 + return;
45711 +}
45712 +
45713 +/** Handles interrupt for a specific Host Channel */
45714 +int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num)
45715 +{
45716 + int retval = 0;
45717 + hcint_data_t hcint;
45718 + hcintmsk_data_t hcintmsk;
45719 + dwc_hc_t *hc;
45720 + dwc_otg_hc_regs_t *hc_regs;
45721 + dwc_otg_qtd_t *qtd;
45722 +
45723 + DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num);
45724 +
45725 + hc = dwc_otg_hcd->hc_ptr_array[num];
45726 + hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];
45727 + if(hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
45728 + /* We are responding to a channel disable. Driver
45729 + * state is cleared - our qtd has gone away.
45730 + */
45731 + release_channel(dwc_otg_hcd, hc, NULL, hc->halt_status);
45732 + return 1;
45733 + }
45734 + qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
45735 +
45736 + /*
45737 + * FSM mode: Check to see if this is a HC interrupt from a channel handled by the FIQ.
45738 + * Execution path is fundamentally different for the channels after a FIQ has completed
45739 + * a split transaction.
45740 + */
45741 + if (fiq_fsm_enable) {
45742 + switch (dwc_otg_hcd->fiq_state->channel[num].fsm) {
45743 + case FIQ_PASSTHROUGH:
45744 + break;
45745 + case FIQ_PASSTHROUGH_ERRORSTATE:
45746 + /* Hook into the error count */
45747 + fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "HCDERR%02d", num);
45748 + if (!dwc_otg_hcd->fiq_state->channel[num].nr_errors) {
45749 + qtd->error_count = 0;
45750 + fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "RESET ");
45751 + }
45752 + break;
45753 + default:
45754 + dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd, num);
45755 + return 1;
45756 + }
45757 + }
45758 +
45759 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
45760 + hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
45761 + hcint.d32 = hcint.d32 & hcintmsk.d32;
45762 + if (!dwc_otg_hcd->core_if->dma_enable) {
45763 + if (hcint.b.chhltd && hcint.d32 != 0x2) {
45764 + hcint.b.chhltd = 0;
45765 + }
45766 + }
45767 +
45768 + if (hcint.b.xfercomp) {
45769 + retval |=
45770 + handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);
45771 + /*
45772 + * If NYET occurred at same time as Xfer Complete, the NYET is
45773 + * handled by the Xfer Complete interrupt handler. Don't want
45774 + * to call the NYET interrupt handler in this case.
45775 + */
45776 + hcint.b.nyet = 0;
45777 + }
45778 + if (hcint.b.chhltd) {
45779 + retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);
45780 + }
45781 + if (hcint.b.ahberr) {
45782 + retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
45783 + }
45784 + if (hcint.b.stall) {
45785 + retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);
45786 + }
45787 + if (hcint.b.nak) {
45788 + retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);
45789 + }
45790 + if (hcint.b.ack) {
45791 + if(!hcint.b.chhltd)
45792 + retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);
45793 + }
45794 + if (hcint.b.nyet) {
45795 + retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);
45796 + }
45797 + if (hcint.b.xacterr) {
45798 + retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
45799 + }
45800 + if (hcint.b.bblerr) {
45801 + retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);
45802 + }
45803 + if (hcint.b.frmovrun) {
45804 + retval |=
45805 + handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);
45806 + }
45807 + if (hcint.b.datatglerr) {
45808 + retval |=
45809 + handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
45810 + }
45811 +
45812 + return retval;
45813 +}
45814 +#endif /* DWC_DEVICE_ONLY */
45815 --- /dev/null
45816 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
45817 @@ -0,0 +1,995 @@
45818 +
45819 +/* ==========================================================================
45820 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_linux.c $
45821 + * $Revision: #20 $
45822 + * $Date: 2011/10/26 $
45823 + * $Change: 1872981 $
45824 + *
45825 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
45826 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
45827 + * otherwise expressly agreed to in writing between Synopsys and you.
45828 + *
45829 + * The Software IS NOT an item of Licensed Software or Licensed Product under
45830 + * any End User Software License Agreement or Agreement for Licensed Product
45831 + * with Synopsys or any supplement thereto. You are permitted to use and
45832 + * redistribute this Software in source and binary forms, with or without
45833 + * modification, provided that redistributions of source code must retain this
45834 + * notice. You may not view, use, disclose, copy or distribute this file or
45835 + * any information contained herein except pursuant to this license grant from
45836 + * Synopsys. If you do not agree with this notice, including the disclaimer
45837 + * below, then you are not authorized to use the Software.
45838 + *
45839 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
45840 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
45841 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
45842 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
45843 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
45844 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
45845 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
45846 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
45847 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
45848 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
45849 + * DAMAGE.
45850 + * ========================================================================== */
45851 +#ifndef DWC_DEVICE_ONLY
45852 +
45853 +/**
45854 + * @file
45855 + *
45856 + * This file contains the implementation of the HCD. In Linux, the HCD
45857 + * implements the hc_driver API.
45858 + */
45859 +#include <linux/kernel.h>
45860 +#include <linux/module.h>
45861 +#include <linux/moduleparam.h>
45862 +#include <linux/init.h>
45863 +#include <linux/device.h>
45864 +#include <linux/errno.h>
45865 +#include <linux/list.h>
45866 +#include <linux/interrupt.h>
45867 +#include <linux/string.h>
45868 +#include <linux/dma-mapping.h>
45869 +#include <linux/version.h>
45870 +#include <asm/io.h>
45871 +#include <asm/fiq.h>
45872 +#include <linux/usb.h>
45873 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
45874 +#include <../drivers/usb/core/hcd.h>
45875 +#else
45876 +#include <linux/usb/hcd.h>
45877 +#endif
45878 +#include <asm/bug.h>
45879 +
45880 +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))
45881 +#define USB_URB_EP_LINKING 1
45882 +#else
45883 +#define USB_URB_EP_LINKING 0
45884 +#endif
45885 +
45886 +#include "dwc_otg_hcd_if.h"
45887 +#include "dwc_otg_dbg.h"
45888 +#include "dwc_otg_driver.h"
45889 +#include "dwc_otg_hcd.h"
45890 +
45891 +extern unsigned char _dwc_otg_fiq_stub, _dwc_otg_fiq_stub_end;
45892 +
45893 +/**
45894 + * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is
45895 + * qualified with its direction (possible 32 endpoints per device).
45896 + */
45897 +#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
45898 + ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
45899 +
45900 +static const char dwc_otg_hcd_name[] = "dwc_otg_hcd";
45901 +
45902 +extern bool fiq_enable;
45903 +
45904 +/** @name Linux HC Driver API Functions */
45905 +/** @{ */
45906 +/* manage i/o requests, device state */
45907 +static int dwc_otg_urb_enqueue(struct usb_hcd *hcd,
45908 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
45909 + struct usb_host_endpoint *ep,
45910 +#endif
45911 + struct urb *urb, gfp_t mem_flags);
45912 +
45913 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
45914 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
45915 +static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb);
45916 +#endif
45917 +#else /* kernels at or post 2.6.30 */
45918 +static int dwc_otg_urb_dequeue(struct usb_hcd *hcd,
45919 + struct urb *urb, int status);
45920 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) */
45921 +
45922 +static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
45923 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
45924 +static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
45925 +#endif
45926 +static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd);
45927 +extern int hcd_start(struct usb_hcd *hcd);
45928 +extern void hcd_stop(struct usb_hcd *hcd);
45929 +static int get_frame_number(struct usb_hcd *hcd);
45930 +extern int hub_status_data(struct usb_hcd *hcd, char *buf);
45931 +extern int hub_control(struct usb_hcd *hcd,
45932 + u16 typeReq,
45933 + u16 wValue, u16 wIndex, char *buf, u16 wLength);
45934 +
45935 +struct wrapper_priv_data {
45936 + dwc_otg_hcd_t *dwc_otg_hcd;
45937 +};
45938 +
45939 +/** @} */
45940 +
45941 +static struct hc_driver dwc_otg_hc_driver = {
45942 +
45943 + .description = dwc_otg_hcd_name,
45944 + .product_desc = "DWC OTG Controller",
45945 + .hcd_priv_size = sizeof(struct wrapper_priv_data),
45946 +
45947 + .irq = dwc_otg_hcd_irq,
45948 +
45949 + .flags = HCD_MEMORY | HCD_USB2,
45950 +
45951 + //.reset =
45952 + .start = hcd_start,
45953 + //.suspend =
45954 + //.resume =
45955 + .stop = hcd_stop,
45956 +
45957 + .urb_enqueue = dwc_otg_urb_enqueue,
45958 + .urb_dequeue = dwc_otg_urb_dequeue,
45959 + .endpoint_disable = endpoint_disable,
45960 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
45961 + .endpoint_reset = endpoint_reset,
45962 +#endif
45963 + .get_frame_number = get_frame_number,
45964 +
45965 + .hub_status_data = hub_status_data,
45966 + .hub_control = hub_control,
45967 + //.bus_suspend =
45968 + //.bus_resume =
45969 +};
45970 +
45971 +/** Gets the dwc_otg_hcd from a struct usb_hcd */
45972 +static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)
45973 +{
45974 + struct wrapper_priv_data *p;
45975 + p = (struct wrapper_priv_data *)(hcd->hcd_priv);
45976 + return p->dwc_otg_hcd;
45977 +}
45978 +
45979 +/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */
45980 +static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t * dwc_otg_hcd)
45981 +{
45982 + return dwc_otg_hcd_get_priv_data(dwc_otg_hcd);
45983 +}
45984 +
45985 +/** Gets the usb_host_endpoint associated with an URB. */
45986 +inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb)
45987 +{
45988 + struct usb_device *dev = urb->dev;
45989 + int ep_num = usb_pipeendpoint(urb->pipe);
45990 +
45991 + if (usb_pipein(urb->pipe))
45992 + return dev->ep_in[ep_num];
45993 + else
45994 + return dev->ep_out[ep_num];
45995 +}
45996 +
45997 +static int _disconnect(dwc_otg_hcd_t * hcd)
45998 +{
45999 + struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
46000 +
46001 + usb_hcd->self.is_b_host = 0;
46002 + return 0;
46003 +}
46004 +
46005 +static int _start(dwc_otg_hcd_t * hcd)
46006 +{
46007 + struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
46008 +
46009 + usb_hcd->self.is_b_host = dwc_otg_hcd_is_b_host(hcd);
46010 + hcd_start(usb_hcd);
46011 +
46012 + return 0;
46013 +}
46014 +
46015 +static int _hub_info(dwc_otg_hcd_t * hcd, void *urb_handle, uint32_t * hub_addr,
46016 + uint32_t * port_addr)
46017 +{
46018 + struct urb *urb = (struct urb *)urb_handle;
46019 + struct usb_bus *bus;
46020 +#if 1 //GRAYG - temporary
46021 + if (NULL == urb_handle)
46022 + DWC_ERROR("**** %s - NULL URB handle\n", __func__);//GRAYG
46023 + if (NULL == urb->dev)
46024 + DWC_ERROR("**** %s - URB has no device\n", __func__);//GRAYG
46025 + if (NULL == port_addr)
46026 + DWC_ERROR("**** %s - NULL port_address\n", __func__);//GRAYG
46027 +#endif
46028 + if (urb->dev->tt) {
46029 + if (NULL == urb->dev->tt->hub) {
46030 + DWC_ERROR("**** %s - (URB's transactor has no TT - giving no hub)\n",
46031 + __func__); //GRAYG
46032 + //*hub_addr = (u8)usb_pipedevice(urb->pipe); //GRAYG
46033 + *hub_addr = 0; //GRAYG
46034 + // we probably shouldn't have a transaction translator if
46035 + // there's no associated hub?
46036 + } else {
46037 + bus = hcd_to_bus(dwc_otg_hcd_to_hcd(hcd));
46038 + if (urb->dev->tt->hub == bus->root_hub)
46039 + *hub_addr = 0;
46040 + else
46041 + *hub_addr = urb->dev->tt->hub->devnum;
46042 + }
46043 + *port_addr = urb->dev->tt->multi ? urb->dev->ttport : 1;
46044 + } else {
46045 + *hub_addr = 0;
46046 + *port_addr = urb->dev->ttport;
46047 + }
46048 + return 0;
46049 +}
46050 +
46051 +static int _speed(dwc_otg_hcd_t * hcd, void *urb_handle)
46052 +{
46053 + struct urb *urb = (struct urb *)urb_handle;
46054 + return urb->dev->speed;
46055 +}
46056 +
46057 +static int _get_b_hnp_enable(dwc_otg_hcd_t * hcd)
46058 +{
46059 + struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
46060 + return usb_hcd->self.b_hnp_enable;
46061 +}
46062 +
46063 +static void allocate_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,
46064 + struct urb *urb)
46065 +{
46066 + hcd_to_bus(hcd)->bandwidth_allocated += bw / urb->interval;
46067 + if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
46068 + hcd_to_bus(hcd)->bandwidth_isoc_reqs++;
46069 + } else {
46070 + hcd_to_bus(hcd)->bandwidth_int_reqs++;
46071 + }
46072 +}
46073 +
46074 +static void free_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,
46075 + struct urb *urb)
46076 +{
46077 + hcd_to_bus(hcd)->bandwidth_allocated -= bw / urb->interval;
46078 + if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
46079 + hcd_to_bus(hcd)->bandwidth_isoc_reqs--;
46080 + } else {
46081 + hcd_to_bus(hcd)->bandwidth_int_reqs--;
46082 + }
46083 +}
46084 +
46085 +/**
46086 + * Sets the final status of an URB and returns it to the device driver. Any
46087 + * required cleanup of the URB is performed. The HCD lock should be held on
46088 + * entry.
46089 + */
46090 +static int _complete(dwc_otg_hcd_t * hcd, void *urb_handle,
46091 + dwc_otg_hcd_urb_t * dwc_otg_urb, int32_t status)
46092 +{
46093 + struct urb *urb = (struct urb *)urb_handle;
46094 + urb_tq_entry_t *new_entry;
46095 + int rc = 0;
46096 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
46097 + DWC_PRINTF("%s: urb %p, device %d, ep %d %s, status=%d\n",
46098 + __func__, urb, usb_pipedevice(urb->pipe),
46099 + usb_pipeendpoint(urb->pipe),
46100 + usb_pipein(urb->pipe) ? "IN" : "OUT", status);
46101 + if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
46102 + int i;
46103 + for (i = 0; i < urb->number_of_packets; i++) {
46104 + DWC_PRINTF(" ISO Desc %d status: %d\n",
46105 + i, urb->iso_frame_desc[i].status);
46106 + }
46107 + }
46108 + }
46109 + new_entry = DWC_ALLOC_ATOMIC(sizeof(urb_tq_entry_t));
46110 + urb->actual_length = dwc_otg_hcd_urb_get_actual_length(dwc_otg_urb);
46111 + /* Convert status value. */
46112 + switch (status) {
46113 + case -DWC_E_PROTOCOL:
46114 + status = -EPROTO;
46115 + break;
46116 + case -DWC_E_IN_PROGRESS:
46117 + status = -EINPROGRESS;
46118 + break;
46119 + case -DWC_E_PIPE:
46120 + status = -EPIPE;
46121 + break;
46122 + case -DWC_E_IO:
46123 + status = -EIO;
46124 + break;
46125 + case -DWC_E_TIMEOUT:
46126 + status = -ETIMEDOUT;
46127 + break;
46128 + case -DWC_E_OVERFLOW:
46129 + status = -EOVERFLOW;
46130 + break;
46131 + case -DWC_E_SHUTDOWN:
46132 + status = -ESHUTDOWN;
46133 + break;
46134 + default:
46135 + if (status) {
46136 + DWC_PRINTF("Uknown urb status %d\n", status);
46137 +
46138 + }
46139 + }
46140 +
46141 + if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
46142 + int i;
46143 +
46144 + urb->error_count = dwc_otg_hcd_urb_get_error_count(dwc_otg_urb);
46145 + for (i = 0; i < urb->number_of_packets; ++i) {
46146 + urb->iso_frame_desc[i].actual_length =
46147 + dwc_otg_hcd_urb_get_iso_desc_actual_length
46148 + (dwc_otg_urb, i);
46149 + urb->iso_frame_desc[i].status =
46150 + dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_urb, i);
46151 + }
46152 + }
46153 +
46154 + urb->status = status;
46155 + urb->hcpriv = NULL;
46156 + if (!status) {
46157 + if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
46158 + (urb->actual_length < urb->transfer_buffer_length)) {
46159 + urb->status = -EREMOTEIO;
46160 + }
46161 + }
46162 +
46163 + if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) ||
46164 + (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
46165 + struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb);
46166 + if (ep) {
46167 + free_bus_bandwidth(dwc_otg_hcd_to_hcd(hcd),
46168 + dwc_otg_hcd_get_ep_bandwidth(hcd,
46169 + ep->hcpriv),
46170 + urb);
46171 + }
46172 + }
46173 + DWC_FREE(dwc_otg_urb);
46174 + if (!new_entry) {
46175 + DWC_ERROR("dwc_otg_hcd: complete: cannot allocate URB TQ entry\n");
46176 + urb->status = -EPROTO;
46177 + /* don't schedule the tasklet -
46178 + * directly return the packet here with error. */
46179 +#if USB_URB_EP_LINKING
46180 + usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb);
46181 +#endif
46182 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
46183 + usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb);
46184 +#else
46185 + usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, urb->status);
46186 +#endif
46187 + } else {
46188 + new_entry->urb = urb;
46189 +#if USB_URB_EP_LINKING
46190 + rc = usb_hcd_check_unlink_urb(dwc_otg_hcd_to_hcd(hcd), urb, urb->status);
46191 + if(0 == rc) {
46192 + usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb);
46193 + }
46194 +#endif
46195 + if(0 == rc) {
46196 + DWC_TAILQ_INSERT_TAIL(&hcd->completed_urb_list, new_entry,
46197 + urb_tq_entries);
46198 + DWC_TASK_HI_SCHEDULE(hcd->completion_tasklet);
46199 + }
46200 + }
46201 + return 0;
46202 +}
46203 +
46204 +static struct dwc_otg_hcd_function_ops hcd_fops = {
46205 + .start = _start,
46206 + .disconnect = _disconnect,
46207 + .hub_info = _hub_info,
46208 + .speed = _speed,
46209 + .complete = _complete,
46210 + .get_b_hnp_enable = _get_b_hnp_enable,
46211 +};
46212 +
46213 +static struct fiq_handler fh = {
46214 + .name = "usb_fiq",
46215 +};
46216 +
46217 +static void hcd_init_fiq(void *cookie)
46218 +{
46219 + dwc_otg_device_t *otg_dev = cookie;
46220 + dwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd;
46221 + struct pt_regs regs;
46222 +
46223 + if (claim_fiq(&fh)) {
46224 + DWC_ERROR("Can't claim FIQ");
46225 + BUG();
46226 + }
46227 + DWC_WARN("FIQ on core %d at 0x%08x",
46228 + smp_processor_id(),
46229 + (fiq_fsm_enable ? (int)&dwc_otg_fiq_fsm : (int)&dwc_otg_fiq_nop));
46230 + DWC_WARN("FIQ ASM at 0x%08x length %d", (int)&_dwc_otg_fiq_stub, (int)(&_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub));
46231 + set_fiq_handler((void *) &_dwc_otg_fiq_stub, &_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub);
46232 + memset(&regs,0,sizeof(regs));
46233 +
46234 + regs.ARM_r8 = (long) dwc_otg_hcd->fiq_state;
46235 + if (fiq_fsm_enable) {
46236 + regs.ARM_r9 = dwc_otg_hcd->core_if->core_params->host_channels;
46237 + //regs.ARM_r10 = dwc_otg_hcd->dma;
46238 + regs.ARM_fp = (long) dwc_otg_fiq_fsm;
46239 + } else {
46240 + regs.ARM_fp = (long) dwc_otg_fiq_nop;
46241 + }
46242 +
46243 + regs.ARM_sp = (long) dwc_otg_hcd->fiq_stack + (sizeof(struct fiq_stack) - 4);
46244 +
46245 +// __show_regs(&regs);
46246 + set_fiq_regs(&regs);
46247 +
46248 + //Set the mphi periph to the required registers
46249 + dwc_otg_hcd->fiq_state->mphi_regs.base = otg_dev->os_dep.mphi_base;
46250 + dwc_otg_hcd->fiq_state->mphi_regs.ctrl = otg_dev->os_dep.mphi_base + 0x4c;
46251 + dwc_otg_hcd->fiq_state->mphi_regs.outdda = otg_dev->os_dep.mphi_base + 0x28;
46252 + dwc_otg_hcd->fiq_state->mphi_regs.outddb = otg_dev->os_dep.mphi_base + 0x2c;
46253 + dwc_otg_hcd->fiq_state->mphi_regs.intstat = otg_dev->os_dep.mphi_base + 0x50;
46254 + dwc_otg_hcd->fiq_state->dwc_regs_base = otg_dev->os_dep.base;
46255 + DWC_WARN("MPHI regs_base at 0x%08x", (int)dwc_otg_hcd->fiq_state->mphi_regs.base);
46256 + //Enable mphi peripheral
46257 + writel((1<<31),dwc_otg_hcd->fiq_state->mphi_regs.ctrl);
46258 +#ifdef DEBUG
46259 + if (readl(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & 0x80000000)
46260 + DWC_WARN("MPHI periph has been enabled");
46261 + else
46262 + DWC_WARN("MPHI periph has NOT been enabled");
46263 +#endif
46264 + // Enable FIQ interrupt from USB peripheral
46265 + enable_fiq(INTERRUPT_VC_USB);
46266 + local_fiq_enable();
46267 +}
46268 +
46269 +/**
46270 + * Initializes the HCD. This function allocates memory for and initializes the
46271 + * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the
46272 + * USB bus with the core and calls the hc_driver->start() function. It returns
46273 + * a negative error on failure.
46274 + */
46275 +int hcd_init(dwc_bus_dev_t *_dev)
46276 +{
46277 + struct usb_hcd *hcd = NULL;
46278 + dwc_otg_hcd_t *dwc_otg_hcd = NULL;
46279 + dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
46280 + int retval = 0;
46281 + u64 dmamask;
46282 +
46283 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT otg_dev=%p\n", otg_dev);
46284 +
46285 + /* Set device flags indicating whether the HCD supports DMA. */
46286 + if (dwc_otg_is_dma_enable(otg_dev->core_if))
46287 + dmamask = DMA_BIT_MASK(32);
46288 + else
46289 + dmamask = 0;
46290 +
46291 +#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
46292 + dma_set_mask(&_dev->dev, dmamask);
46293 + dma_set_coherent_mask(&_dev->dev, dmamask);
46294 +#elif defined(PCI_INTERFACE)
46295 + pci_set_dma_mask(_dev, dmamask);
46296 + pci_set_consistent_dma_mask(_dev, dmamask);
46297 +#endif
46298 +
46299 + /*
46300 + * Allocate memory for the base HCD plus the DWC OTG HCD.
46301 + * Initialize the base HCD.
46302 + */
46303 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
46304 + hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, _dev->dev.bus_id);
46305 +#else
46306 + hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, dev_name(&_dev->dev));
46307 + hcd->has_tt = 1;
46308 +// hcd->uses_new_polling = 1;
46309 +// hcd->poll_rh = 0;
46310 +#endif
46311 + if (!hcd) {
46312 + retval = -ENOMEM;
46313 + goto error1;
46314 + }
46315 +
46316 + hcd->regs = otg_dev->os_dep.base;
46317 +
46318 +
46319 + /* Initialize the DWC OTG HCD. */
46320 + dwc_otg_hcd = dwc_otg_hcd_alloc_hcd();
46321 + if (!dwc_otg_hcd) {
46322 + goto error2;
46323 + }
46324 + ((struct wrapper_priv_data *)(hcd->hcd_priv))->dwc_otg_hcd =
46325 + dwc_otg_hcd;
46326 + otg_dev->hcd = dwc_otg_hcd;
46327 +
46328 + if (dwc_otg_hcd_init(dwc_otg_hcd, otg_dev->core_if)) {
46329 + goto error2;
46330 + }
46331 +
46332 + if (fiq_enable) {
46333 + if (num_online_cpus() > 1) {
46334 + /* bcm2709: can run the FIQ on a separate core to IRQs */
46335 + smp_call_function_single(1, hcd_init_fiq, otg_dev, 1);
46336 + } else {
46337 + smp_call_function_single(0, hcd_init_fiq, otg_dev, 1);
46338 + }
46339 + }
46340 +
46341 + otg_dev->hcd->otg_dev = otg_dev;
46342 + hcd->self.otg_port = dwc_otg_hcd_otg_port(dwc_otg_hcd);
46343 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,33) //don't support for LM(with 2.6.20.1 kernel)
46344 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) //version field absent later
46345 + hcd->self.otg_version = dwc_otg_get_otg_version(otg_dev->core_if);
46346 +#endif
46347 + /* Don't support SG list at this point */
46348 + hcd->self.sg_tablesize = 0;
46349 +#endif
46350 + /*
46351 + * Finish generic HCD initialization and start the HCD. This function
46352 + * allocates the DMA buffer pool, registers the USB bus, requests the
46353 + * IRQ line, and calls hcd_start method.
46354 + */
46355 +#ifdef PLATFORM_INTERFACE
46356 + retval = usb_add_hcd(hcd, platform_get_irq(_dev, fiq_enable ? 0 : 1), IRQF_SHARED);
46357 +#else
46358 + retval = usb_add_hcd(hcd, _dev->irq, IRQF_SHARED);
46359 +#endif
46360 + if (retval < 0) {
46361 + goto error2;
46362 + }
46363 +
46364 + dwc_otg_hcd_set_priv_data(dwc_otg_hcd, hcd);
46365 + return 0;
46366 +
46367 +error2:
46368 + usb_put_hcd(hcd);
46369 +error1:
46370 + return retval;
46371 +}
46372 +
46373 +/**
46374 + * Removes the HCD.
46375 + * Frees memory and resources associated with the HCD and deregisters the bus.
46376 + */
46377 +void hcd_remove(dwc_bus_dev_t *_dev)
46378 +{
46379 + dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
46380 + dwc_otg_hcd_t *dwc_otg_hcd;
46381 + struct usb_hcd *hcd;
46382 +
46383 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE otg_dev=%p\n", otg_dev);
46384 +
46385 + if (!otg_dev) {
46386 + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
46387 + return;
46388 + }
46389 +
46390 + dwc_otg_hcd = otg_dev->hcd;
46391 +
46392 + if (!dwc_otg_hcd) {
46393 + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
46394 + return;
46395 + }
46396 +
46397 + hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
46398 +
46399 + if (!hcd) {
46400 + DWC_DEBUGPL(DBG_ANY,
46401 + "%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\n",
46402 + __func__);
46403 + return;
46404 + }
46405 + usb_remove_hcd(hcd);
46406 + dwc_otg_hcd_set_priv_data(dwc_otg_hcd, NULL);
46407 + dwc_otg_hcd_remove(dwc_otg_hcd);
46408 + usb_put_hcd(hcd);
46409 +}
46410 +
46411 +/* =========================================================================
46412 + * Linux HC Driver Functions
46413 + * ========================================================================= */
46414 +
46415 +/** Initializes the DWC_otg controller and its root hub and prepares it for host
46416 + * mode operation. Activates the root port. Returns 0 on success and a negative
46417 + * error code on failure. */
46418 +int hcd_start(struct usb_hcd *hcd)
46419 +{
46420 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
46421 + struct usb_bus *bus;
46422 +
46423 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
46424 + bus = hcd_to_bus(hcd);
46425 +
46426 + hcd->state = HC_STATE_RUNNING;
46427 + if (dwc_otg_hcd_start(dwc_otg_hcd, &hcd_fops)) {
46428 + return 0;
46429 + }
46430 +
46431 + /* Initialize and connect root hub if one is not already attached */
46432 + if (bus->root_hub) {
46433 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
46434 + /* Inform the HUB driver to resume. */
46435 + usb_hcd_resume_root_hub(hcd);
46436 + }
46437 +
46438 + return 0;
46439 +}
46440 +
46441 +/**
46442 + * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
46443 + * stopped.
46444 + */
46445 +void hcd_stop(struct usb_hcd *hcd)
46446 +{
46447 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
46448 +
46449 + dwc_otg_hcd_stop(dwc_otg_hcd);
46450 +}
46451 +
46452 +/** Returns the current frame number. */
46453 +static int get_frame_number(struct usb_hcd *hcd)
46454 +{
46455 + hprt0_data_t hprt0;
46456 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
46457 + hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
46458 + if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
46459 + return dwc_otg_hcd_get_frame_number(dwc_otg_hcd) >> 3;
46460 + else
46461 + return dwc_otg_hcd_get_frame_number(dwc_otg_hcd);
46462 +}
46463 +
46464 +#ifdef DEBUG
46465 +static void dump_urb_info(struct urb *urb, char *fn_name)
46466 +{
46467 + DWC_PRINTF("%s, urb %p\n", fn_name, urb);
46468 + DWC_PRINTF(" Device address: %d\n", usb_pipedevice(urb->pipe));
46469 + DWC_PRINTF(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
46470 + (usb_pipein(urb->pipe) ? "IN" : "OUT"));
46471 + DWC_PRINTF(" Endpoint type: %s\n", ( {
46472 + char *pipetype;
46473 + switch (usb_pipetype(urb->pipe)) {
46474 +case PIPE_CONTROL:
46475 +pipetype = "CONTROL"; break; case PIPE_BULK:
46476 +pipetype = "BULK"; break; case PIPE_INTERRUPT:
46477 +pipetype = "INTERRUPT"; break; case PIPE_ISOCHRONOUS:
46478 +pipetype = "ISOCHRONOUS"; break; default:
46479 + pipetype = "UNKNOWN"; break;};
46480 + pipetype;}
46481 + )) ;
46482 + DWC_PRINTF(" Speed: %s\n", ( {
46483 + char *speed; switch (urb->dev->speed) {
46484 +case USB_SPEED_HIGH:
46485 +speed = "HIGH"; break; case USB_SPEED_FULL:
46486 +speed = "FULL"; break; case USB_SPEED_LOW:
46487 +speed = "LOW"; break; default:
46488 + speed = "UNKNOWN"; break;};
46489 + speed;}
46490 + )) ;
46491 + DWC_PRINTF(" Max packet size: %d\n",
46492 + usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
46493 + DWC_PRINTF(" Data buffer length: %d\n", urb->transfer_buffer_length);
46494 + DWC_PRINTF(" Transfer buffer: %p, Transfer DMA: %p\n",
46495 + urb->transfer_buffer, (void *)urb->transfer_dma);
46496 + DWC_PRINTF(" Setup buffer: %p, Setup DMA: %p\n",
46497 + urb->setup_packet, (void *)urb->setup_dma);
46498 + DWC_PRINTF(" Interval: %d\n", urb->interval);
46499 + if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
46500 + int i;
46501 + for (i = 0; i < urb->number_of_packets; i++) {
46502 + DWC_PRINTF(" ISO Desc %d:\n", i);
46503 + DWC_PRINTF(" offset: %d, length %d\n",
46504 + urb->iso_frame_desc[i].offset,
46505 + urb->iso_frame_desc[i].length);
46506 + }
46507 + }
46508 +}
46509 +#endif
46510 +
46511 +/** Starts processing a USB transfer request specified by a USB Request Block
46512 + * (URB). mem_flags indicates the type of memory allocation to use while
46513 + * processing this URB. */
46514 +static int dwc_otg_urb_enqueue(struct usb_hcd *hcd,
46515 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
46516 + struct usb_host_endpoint *ep,
46517 +#endif
46518 + struct urb *urb, gfp_t mem_flags)
46519 +{
46520 + int retval = 0;
46521 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
46522 + struct usb_host_endpoint *ep = urb->ep;
46523 +#endif
46524 + dwc_irqflags_t irqflags;
46525 + void **ref_ep_hcpriv = &ep->hcpriv;
46526 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
46527 + dwc_otg_hcd_urb_t *dwc_otg_urb;
46528 + int i;
46529 + int alloc_bandwidth = 0;
46530 + uint8_t ep_type = 0;
46531 + uint32_t flags = 0;
46532 + void *buf;
46533 +
46534 +#ifdef DEBUG
46535 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
46536 + dump_urb_info(urb, "dwc_otg_urb_enqueue");
46537 + }
46538 +#endif
46539 +
46540 + if (!urb->transfer_buffer && urb->transfer_buffer_length)
46541 + return -EINVAL;
46542 +
46543 + if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
46544 + || (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
46545 + if (!dwc_otg_hcd_is_bandwidth_allocated
46546 + (dwc_otg_hcd, ref_ep_hcpriv)) {
46547 + alloc_bandwidth = 1;
46548 + }
46549 + }
46550 +
46551 + switch (usb_pipetype(urb->pipe)) {
46552 + case PIPE_CONTROL:
46553 + ep_type = USB_ENDPOINT_XFER_CONTROL;
46554 + break;
46555 + case PIPE_ISOCHRONOUS:
46556 + ep_type = USB_ENDPOINT_XFER_ISOC;
46557 + break;
46558 + case PIPE_BULK:
46559 + ep_type = USB_ENDPOINT_XFER_BULK;
46560 + break;
46561 + case PIPE_INTERRUPT:
46562 + ep_type = USB_ENDPOINT_XFER_INT;
46563 + break;
46564 + default:
46565 + DWC_WARN("Wrong EP type - %d\n", usb_pipetype(urb->pipe));
46566 + }
46567 +
46568 + /* # of packets is often 0 - do we really need to call this then? */
46569 + dwc_otg_urb = dwc_otg_hcd_urb_alloc(dwc_otg_hcd,
46570 + urb->number_of_packets,
46571 + mem_flags == GFP_ATOMIC ? 1 : 0);
46572 +
46573 + if(dwc_otg_urb == NULL)
46574 + return -ENOMEM;
46575 +
46576 + if (!dwc_otg_urb && urb->number_of_packets)
46577 + return -ENOMEM;
46578 +
46579 + dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_urb, usb_pipedevice(urb->pipe),
46580 + usb_pipeendpoint(urb->pipe), ep_type,
46581 + usb_pipein(urb->pipe),
46582 + usb_maxpacket(urb->dev, urb->pipe,
46583 + !(usb_pipein(urb->pipe))));
46584 +
46585 + buf = urb->transfer_buffer;
46586 + if (hcd->self.uses_dma && !buf && urb->transfer_buffer_length) {
46587 + /*
46588 + * Calculate virtual address from physical address,
46589 + * because some class driver may not fill transfer_buffer.
46590 + * In Buffer DMA mode virual address is used,
46591 + * when handling non DWORD aligned buffers.
46592 + */
46593 + buf = (void *)__bus_to_virt((unsigned long)urb->transfer_dma);
46594 + dev_warn_once(&urb->dev->dev,
46595 + "USB transfer_buffer was NULL, will use __bus_to_virt(%pad)=%p\n",
46596 + &urb->transfer_dma, buf);
46597 + }
46598 +
46599 + if (!(urb->transfer_flags & URB_NO_INTERRUPT))
46600 + flags |= URB_GIVEBACK_ASAP;
46601 + if (urb->transfer_flags & URB_ZERO_PACKET)
46602 + flags |= URB_SEND_ZERO_PACKET;
46603 +
46604 + dwc_otg_hcd_urb_set_params(dwc_otg_urb, urb, buf,
46605 + urb->transfer_dma,
46606 + urb->transfer_buffer_length,
46607 + urb->setup_packet,
46608 + urb->setup_dma, flags, urb->interval);
46609 +
46610 + for (i = 0; i < urb->number_of_packets; ++i) {
46611 + dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_urb, i,
46612 + urb->
46613 + iso_frame_desc[i].offset,
46614 + urb->
46615 + iso_frame_desc[i].length);
46616 + }
46617 +
46618 + DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &irqflags);
46619 + urb->hcpriv = dwc_otg_urb;
46620 +#if USB_URB_EP_LINKING
46621 + retval = usb_hcd_link_urb_to_ep(hcd, urb);
46622 + if (0 == retval)
46623 +#endif
46624 + {
46625 + retval = dwc_otg_hcd_urb_enqueue(dwc_otg_hcd, dwc_otg_urb,
46626 + /*(dwc_otg_qh_t **)*/
46627 + ref_ep_hcpriv, 1);
46628 + if (0 == retval) {
46629 + if (alloc_bandwidth) {
46630 + allocate_bus_bandwidth(hcd,
46631 + dwc_otg_hcd_get_ep_bandwidth(
46632 + dwc_otg_hcd, *ref_ep_hcpriv),
46633 + urb);
46634 + }
46635 + } else {
46636 + DWC_DEBUGPL(DBG_HCD, "DWC OTG dwc_otg_hcd_urb_enqueue failed rc %d\n", retval);
46637 +#if USB_URB_EP_LINKING
46638 + usb_hcd_unlink_urb_from_ep(hcd, urb);
46639 +#endif
46640 + DWC_FREE(dwc_otg_urb);
46641 + urb->hcpriv = NULL;
46642 + if (retval == -DWC_E_NO_DEVICE)
46643 + retval = -ENODEV;
46644 + }
46645 + }
46646 +#if USB_URB_EP_LINKING
46647 + else
46648 + {
46649 + DWC_FREE(dwc_otg_urb);
46650 + urb->hcpriv = NULL;
46651 + }
46652 +#endif
46653 + DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, irqflags);
46654 + return retval;
46655 +}
46656 +
46657 +/** Aborts/cancels a USB transfer request. Always returns 0 to indicate
46658 + * success. */
46659 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
46660 +static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
46661 +#else
46662 +static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
46663 +#endif
46664 +{
46665 + dwc_irqflags_t flags;
46666 + dwc_otg_hcd_t *dwc_otg_hcd;
46667 + int rc;
46668 +
46669 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
46670 +
46671 + dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
46672 +
46673 +#ifdef DEBUG
46674 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
46675 + dump_urb_info(urb, "dwc_otg_urb_dequeue");
46676 + }
46677 +#endif
46678 +
46679 + DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
46680 + rc = usb_hcd_check_unlink_urb(hcd, urb, status);
46681 + if (0 == rc) {
46682 + if(urb->hcpriv != NULL) {
46683 + dwc_otg_hcd_urb_dequeue(dwc_otg_hcd,
46684 + (dwc_otg_hcd_urb_t *)urb->hcpriv);
46685 +
46686 + DWC_FREE(urb->hcpriv);
46687 + urb->hcpriv = NULL;
46688 + }
46689 + }
46690 +
46691 + if (0 == rc) {
46692 + /* Higher layer software sets URB status. */
46693 +#if USB_URB_EP_LINKING
46694 + usb_hcd_unlink_urb_from_ep(hcd, urb);
46695 +#endif
46696 + DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
46697 +
46698 +
46699 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
46700 + usb_hcd_giveback_urb(hcd, urb);
46701 +#else
46702 + usb_hcd_giveback_urb(hcd, urb, status);
46703 +#endif
46704 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
46705 + DWC_PRINTF("Called usb_hcd_giveback_urb() \n");
46706 + DWC_PRINTF(" 1urb->status = %d\n", urb->status);
46707 + }
46708 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue OK\n");
46709 + } else {
46710 + DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
46711 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue failed - rc %d\n",
46712 + rc);
46713 + }
46714 +
46715 + return rc;
46716 +}
46717 +
46718 +/* Frees resources in the DWC_otg controller related to a given endpoint. Also
46719 + * clears state in the HCD related to the endpoint. Any URBs for the endpoint
46720 + * must already be dequeued. */
46721 +static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
46722 +{
46723 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
46724 +
46725 + DWC_DEBUGPL(DBG_HCD,
46726 + "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
46727 + "endpoint=%d\n", ep->desc.bEndpointAddress,
46728 + dwc_ep_addr_to_endpoint(ep->desc.bEndpointAddress));
46729 + dwc_otg_hcd_endpoint_disable(dwc_otg_hcd, ep->hcpriv, 250);
46730 + ep->hcpriv = NULL;
46731 +}
46732 +
46733 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
46734 +/* Resets endpoint specific parameter values, in current version used to reset
46735 + * the data toggle(as a WA). This function can be called from usb_clear_halt routine */
46736 +static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
46737 +{
46738 + dwc_irqflags_t flags;
46739 + struct usb_device *udev = NULL;
46740 + int epnum = usb_endpoint_num(&ep->desc);
46741 + int is_out = usb_endpoint_dir_out(&ep->desc);
46742 + int is_control = usb_endpoint_xfer_control(&ep->desc);
46743 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
46744 + struct device *dev = DWC_OTG_OS_GETDEV(dwc_otg_hcd->otg_dev->os_dep);
46745 +
46746 + if (dev)
46747 + udev = to_usb_device(dev);
46748 + else
46749 + return;
46750 +
46751 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP RESET: Endpoint Num=0x%02d\n", epnum);
46752 +
46753 + DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
46754 + usb_settoggle(udev, epnum, is_out, 0);
46755 + if (is_control)
46756 + usb_settoggle(udev, epnum, !is_out, 0);
46757 +
46758 + if (ep->hcpriv) {
46759 + dwc_otg_hcd_endpoint_reset(dwc_otg_hcd, ep->hcpriv);
46760 + }
46761 + DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
46762 +}
46763 +#endif
46764 +
46765 +/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
46766 + * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
46767 + * interrupt.
46768 + *
46769 + * This function is called by the USB core when an interrupt occurs */
46770 +static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd)
46771 +{
46772 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
46773 + int32_t retval = dwc_otg_hcd_handle_intr(dwc_otg_hcd);
46774 + if (retval != 0) {
46775 + S3C2410X_CLEAR_EINTPEND();
46776 + }
46777 + return IRQ_RETVAL(retval);
46778 +}
46779 +
46780 +/** Creates Status Change bitmap for the root hub and root port. The bitmap is
46781 + * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
46782 + * is the status change indicator for the single root port. Returns 1 if either
46783 + * change indicator is 1, otherwise returns 0. */
46784 +int hub_status_data(struct usb_hcd *hcd, char *buf)
46785 +{
46786 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
46787 +
46788 + buf[0] = 0;
46789 + buf[0] |= (dwc_otg_hcd_is_status_changed(dwc_otg_hcd, 1)) << 1;
46790 +
46791 + return (buf[0] != 0);
46792 +}
46793 +
46794 +/** Handles hub class-specific requests. */
46795 +int hub_control(struct usb_hcd *hcd,
46796 + u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength)
46797 +{
46798 + int retval;
46799 +
46800 + retval = dwc_otg_hcd_hub_control(hcd_to_dwc_otg_hcd(hcd),
46801 + typeReq, wValue, wIndex, buf, wLength);
46802 +
46803 + switch (retval) {
46804 + case -DWC_E_INVALID:
46805 + retval = -EINVAL;
46806 + break;
46807 + }
46808 +
46809 + return retval;
46810 +}
46811 +
46812 +#endif /* DWC_DEVICE_ONLY */
46813 --- /dev/null
46814 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c
46815 @@ -0,0 +1,957 @@
46816 +/* ==========================================================================
46817 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $
46818 + * $Revision: #44 $
46819 + * $Date: 2011/10/26 $
46820 + * $Change: 1873028 $
46821 + *
46822 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
46823 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
46824 + * otherwise expressly agreed to in writing between Synopsys and you.
46825 + *
46826 + * The Software IS NOT an item of Licensed Software or Licensed Product under
46827 + * any End User Software License Agreement or Agreement for Licensed Product
46828 + * with Synopsys or any supplement thereto. You are permitted to use and
46829 + * redistribute this Software in source and binary forms, with or without
46830 + * modification, provided that redistributions of source code must retain this
46831 + * notice. You may not view, use, disclose, copy or distribute this file or
46832 + * any information contained herein except pursuant to this license grant from
46833 + * Synopsys. If you do not agree with this notice, including the disclaimer
46834 + * below, then you are not authorized to use the Software.
46835 + *
46836 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
46837 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
46838 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
46839 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
46840 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46841 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
46842 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
46843 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
46844 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
46845 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
46846 + * DAMAGE.
46847 + * ========================================================================== */
46848 +#ifndef DWC_DEVICE_ONLY
46849 +
46850 +/**
46851 + * @file
46852 + *
46853 + * This file contains the functions to manage Queue Heads and Queue
46854 + * Transfer Descriptors.
46855 + */
46856 +
46857 +#include "dwc_otg_hcd.h"
46858 +#include "dwc_otg_regs.h"
46859 +
46860 +extern bool microframe_schedule;
46861 +
46862 +/**
46863 + * Free each QTD in the QH's QTD-list then free the QH. QH should already be
46864 + * removed from a list. QTD list should already be empty if called from URB
46865 + * Dequeue.
46866 + *
46867 + * @param hcd HCD instance.
46868 + * @param qh The QH to free.
46869 + */
46870 +void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
46871 +{
46872 + dwc_otg_qtd_t *qtd, *qtd_tmp;
46873 + dwc_irqflags_t flags;
46874 +
46875 + /* Free each QTD in the QTD list */
46876 + DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
46877 + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
46878 + DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);
46879 + dwc_otg_hcd_qtd_free(qtd);
46880 + }
46881 +
46882 + if (hcd->core_if->dma_desc_enable) {
46883 + dwc_otg_hcd_qh_free_ddma(hcd, qh);
46884 + } else if (qh->dw_align_buf) {
46885 + uint32_t buf_size;
46886 + if (qh->ep_type == UE_ISOCHRONOUS) {
46887 + buf_size = 4096;
46888 + } else {
46889 + buf_size = hcd->core_if->core_params->max_transfer_size;
46890 + }
46891 + DWC_DMA_FREE(buf_size, qh->dw_align_buf, qh->dw_align_buf_dma);
46892 + }
46893 +
46894 + DWC_FREE(qh);
46895 + DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
46896 + return;
46897 +}
46898 +
46899 +#define BitStuffTime(bytecount) ((8 * 7* bytecount) / 6)
46900 +#define HS_HOST_DELAY 5 /* nanoseconds */
46901 +#define FS_LS_HOST_DELAY 1000 /* nanoseconds */
46902 +#define HUB_LS_SETUP 333 /* nanoseconds */
46903 +#define NS_TO_US(ns) ((ns + 500) / 1000)
46904 + /* convert & round nanoseconds to microseconds */
46905 +
46906 +static uint32_t calc_bus_time(int speed, int is_in, int is_isoc, int bytecount)
46907 +{
46908 + unsigned long retval;
46909 +
46910 + switch (speed) {
46911 + case USB_SPEED_HIGH:
46912 + if (is_isoc) {
46913 + retval =
46914 + ((38 * 8 * 2083) +
46915 + (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
46916 + HS_HOST_DELAY;
46917 + } else {
46918 + retval =
46919 + ((55 * 8 * 2083) +
46920 + (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
46921 + HS_HOST_DELAY;
46922 + }
46923 + break;
46924 + case USB_SPEED_FULL:
46925 + if (is_isoc) {
46926 + retval =
46927 + (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
46928 + if (is_in) {
46929 + retval = 7268 + FS_LS_HOST_DELAY + retval;
46930 + } else {
46931 + retval = 6265 + FS_LS_HOST_DELAY + retval;
46932 + }
46933 + } else {
46934 + retval =
46935 + (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
46936 + retval = 9107 + FS_LS_HOST_DELAY + retval;
46937 + }
46938 + break;
46939 + case USB_SPEED_LOW:
46940 + if (is_in) {
46941 + retval =
46942 + (67667 * (31 + 10 * BitStuffTime(bytecount))) /
46943 + 1000;
46944 + retval =
46945 + 64060 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
46946 + retval;
46947 + } else {
46948 + retval =
46949 + (66700 * (31 + 10 * BitStuffTime(bytecount))) /
46950 + 1000;
46951 + retval =
46952 + 64107 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
46953 + retval;
46954 + }
46955 + break;
46956 + default:
46957 + DWC_WARN("Unknown device speed\n");
46958 + retval = -1;
46959 + }
46960 +
46961 + return NS_TO_US(retval);
46962 +}
46963 +
46964 +/**
46965 + * Initializes a QH structure.
46966 + *
46967 + * @param hcd The HCD state structure for the DWC OTG controller.
46968 + * @param qh The QH to init.
46969 + * @param urb Holds the information about the device/endpoint that we need
46970 + * to initialize the QH.
46971 + */
46972 +#define SCHEDULE_SLOP 10
46973 +void qh_init(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, dwc_otg_hcd_urb_t * urb)
46974 +{
46975 + char *speed, *type;
46976 + int dev_speed;
46977 + uint32_t hub_addr, hub_port;
46978 +
46979 + dwc_memset(qh, 0, sizeof(dwc_otg_qh_t));
46980 +
46981 + /* Initialize QH */
46982 + qh->ep_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
46983 + qh->ep_is_in = dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0;
46984 +
46985 + qh->data_toggle = DWC_OTG_HC_PID_DATA0;
46986 + qh->maxp = dwc_otg_hcd_get_mps(&urb->pipe_info);
46987 + DWC_CIRCLEQ_INIT(&qh->qtd_list);
46988 + DWC_LIST_INIT(&qh->qh_list_entry);
46989 + qh->channel = NULL;
46990 +
46991 + /* FS/LS Enpoint on HS Hub
46992 + * NOT virtual root hub */
46993 + dev_speed = hcd->fops->speed(hcd, urb->priv);
46994 +
46995 + hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &hub_port);
46996 + qh->do_split = 0;
46997 + if (microframe_schedule)
46998 + qh->speed = dev_speed;
46999 +
47000 + qh->nak_frame = 0xffff;
47001 +
47002 + if (((dev_speed == USB_SPEED_LOW) ||
47003 + (dev_speed == USB_SPEED_FULL)) &&
47004 + (hub_addr != 0 && hub_addr != 1)) {
47005 + DWC_DEBUGPL(DBG_HCD,
47006 + "QH init: EP %d: TT found at hub addr %d, for port %d\n",
47007 + dwc_otg_hcd_get_ep_num(&urb->pipe_info), hub_addr,
47008 + hub_port);
47009 + qh->do_split = 1;
47010 + qh->skip_count = 0;
47011 + }
47012 +
47013 + if (qh->ep_type == UE_INTERRUPT || qh->ep_type == UE_ISOCHRONOUS) {
47014 + /* Compute scheduling parameters once and save them. */
47015 + hprt0_data_t hprt;
47016 +
47017 + /** @todo Account for split transfers in the bus time. */
47018 + int bytecount =
47019 + dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp);
47020 +
47021 + qh->usecs =
47022 + calc_bus_time((qh->do_split ? USB_SPEED_HIGH : dev_speed),
47023 + qh->ep_is_in, (qh->ep_type == UE_ISOCHRONOUS),
47024 + bytecount);
47025 + /* Start in a slightly future (micro)frame. */
47026 + qh->sched_frame = dwc_frame_num_inc(hcd->frame_number,
47027 + SCHEDULE_SLOP);
47028 + qh->interval = urb->interval;
47029 +
47030 +#if 0
47031 + /* Increase interrupt polling rate for debugging. */
47032 + if (qh->ep_type == UE_INTERRUPT) {
47033 + qh->interval = 8;
47034 + }
47035 +#endif
47036 + hprt.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0);
47037 + if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
47038 + ((dev_speed == USB_SPEED_LOW) ||
47039 + (dev_speed == USB_SPEED_FULL))) {
47040 + qh->interval *= 8;
47041 + qh->sched_frame |= 0x7;
47042 + qh->start_split_frame = qh->sched_frame;
47043 + }
47044 +
47045 + }
47046 +
47047 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
47048 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", qh);
47049 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n",
47050 + dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
47051 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n",
47052 + dwc_otg_hcd_get_ep_num(&urb->pipe_info),
47053 + dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
47054 + switch (dev_speed) {
47055 + case USB_SPEED_LOW:
47056 + qh->dev_speed = DWC_OTG_EP_SPEED_LOW;
47057 + speed = "low";
47058 + break;
47059 + case USB_SPEED_FULL:
47060 + qh->dev_speed = DWC_OTG_EP_SPEED_FULL;
47061 + speed = "full";
47062 + break;
47063 + case USB_SPEED_HIGH:
47064 + qh->dev_speed = DWC_OTG_EP_SPEED_HIGH;
47065 + speed = "high";
47066 + break;
47067 + default:
47068 + speed = "?";
47069 + break;
47070 + }
47071 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n", speed);
47072 +
47073 + switch (qh->ep_type) {
47074 + case UE_ISOCHRONOUS:
47075 + type = "isochronous";
47076 + break;
47077 + case UE_INTERRUPT:
47078 + type = "interrupt";
47079 + break;
47080 + case UE_CONTROL:
47081 + type = "control";
47082 + break;
47083 + case UE_BULK:
47084 + type = "bulk";
47085 + break;
47086 + default:
47087 + type = "?";
47088 + break;
47089 + }
47090 +
47091 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n", type);
47092 +
47093 +#ifdef DEBUG
47094 + if (qh->ep_type == UE_INTERRUPT) {
47095 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
47096 + qh->usecs);
47097 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
47098 + qh->interval);
47099 + }
47100 +#endif
47101 +
47102 +}
47103 +
47104 +/**
47105 + * This function allocates and initializes a QH.
47106 + *
47107 + * @param hcd The HCD state structure for the DWC OTG controller.
47108 + * @param urb Holds the information about the device/endpoint that we need
47109 + * to initialize the QH.
47110 + * @param atomic_alloc Flag to do atomic allocation if needed
47111 + *
47112 + * @return Returns pointer to the newly allocated QH, or NULL on error. */
47113 +dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
47114 + dwc_otg_hcd_urb_t * urb, int atomic_alloc)
47115 +{
47116 + dwc_otg_qh_t *qh;
47117 +
47118 + /* Allocate memory */
47119 + /** @todo add memflags argument */
47120 + qh = dwc_otg_hcd_qh_alloc(atomic_alloc);
47121 + if (qh == NULL) {
47122 + DWC_ERROR("qh allocation failed");
47123 + return NULL;
47124 + }
47125 +
47126 + qh_init(hcd, qh, urb);
47127 +
47128 + if (hcd->core_if->dma_desc_enable
47129 + && (dwc_otg_hcd_qh_init_ddma(hcd, qh) < 0)) {
47130 + dwc_otg_hcd_qh_free(hcd, qh);
47131 + return NULL;
47132 + }
47133 +
47134 + return qh;
47135 +}
47136 +
47137 +/* microframe_schedule=0 start */
47138 +
47139 +/**
47140 + * Checks that a channel is available for a periodic transfer.
47141 + *
47142 + * @return 0 if successful, negative error code otherise.
47143 + */
47144 +static int periodic_channel_available(dwc_otg_hcd_t * hcd)
47145 +{
47146 + /*
47147 + * Currently assuming that there is a dedicated host channnel for each
47148 + * periodic transaction plus at least one host channel for
47149 + * non-periodic transactions.
47150 + */
47151 + int status;
47152 + int num_channels;
47153 +
47154 + num_channels = hcd->core_if->core_params->host_channels;
47155 + if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels)
47156 + && (hcd->periodic_channels < num_channels - 1)) {
47157 + status = 0;
47158 + } else {
47159 + DWC_INFO("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
47160 + __func__, num_channels, hcd->periodic_channels, hcd->non_periodic_channels); //NOTICE
47161 + status = -DWC_E_NO_SPACE;
47162 + }
47163 +
47164 + return status;
47165 +}
47166 +
47167 +/**
47168 + * Checks that there is sufficient bandwidth for the specified QH in the
47169 + * periodic schedule. For simplicity, this calculation assumes that all the
47170 + * transfers in the periodic schedule may occur in the same (micro)frame.
47171 + *
47172 + * @param hcd The HCD state structure for the DWC OTG controller.
47173 + * @param qh QH containing periodic bandwidth required.
47174 + *
47175 + * @return 0 if successful, negative error code otherwise.
47176 + */
47177 +static int check_periodic_bandwidth(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
47178 +{
47179 + int status;
47180 + int16_t max_claimed_usecs;
47181 +
47182 + status = 0;
47183 +
47184 + if ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) || qh->do_split) {
47185 + /*
47186 + * High speed mode.
47187 + * Max periodic usecs is 80% x 125 usec = 100 usec.
47188 + */
47189 +
47190 + max_claimed_usecs = 100 - qh->usecs;
47191 + } else {
47192 + /*
47193 + * Full speed mode.
47194 + * Max periodic usecs is 90% x 1000 usec = 900 usec.
47195 + */
47196 + max_claimed_usecs = 900 - qh->usecs;
47197 + }
47198 +
47199 + if (hcd->periodic_usecs > max_claimed_usecs) {
47200 + DWC_INFO("%s: already claimed usecs %d, required usecs %d\n", __func__, hcd->periodic_usecs, qh->usecs); //NOTICE
47201 + status = -DWC_E_NO_SPACE;
47202 + }
47203 +
47204 + return status;
47205 +}
47206 +
47207 +/* microframe_schedule=0 end */
47208 +
47209 +/**
47210 + * Microframe scheduler
47211 + * track the total use in hcd->frame_usecs
47212 + * keep each qh use in qh->frame_usecs
47213 + * when surrendering the qh then donate the time back
47214 + */
47215 +const unsigned short max_uframe_usecs[]={ 100, 100, 100, 100, 100, 100, 30, 0 };
47216 +
47217 +/*
47218 + * called from dwc_otg_hcd.c:dwc_otg_hcd_init
47219 + */
47220 +int init_hcd_usecs(dwc_otg_hcd_t *_hcd)
47221 +{
47222 + int i;
47223 + for (i=0; i<8; i++) {
47224 + _hcd->frame_usecs[i] = max_uframe_usecs[i];
47225 + }
47226 + return 0;
47227 +}
47228 +
47229 +static int find_single_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
47230 +{
47231 + int i;
47232 + unsigned short utime;
47233 + int t_left;
47234 + int ret;
47235 + int done;
47236 +
47237 + ret = -1;
47238 + utime = _qh->usecs;
47239 + t_left = utime;
47240 + i = 0;
47241 + done = 0;
47242 + while (done == 0) {
47243 + /* At the start _hcd->frame_usecs[i] = max_uframe_usecs[i]; */
47244 + if (utime <= _hcd->frame_usecs[i]) {
47245 + _hcd->frame_usecs[i] -= utime;
47246 + _qh->frame_usecs[i] += utime;
47247 + t_left -= utime;
47248 + ret = i;
47249 + done = 1;
47250 + return ret;
47251 + } else {
47252 + i++;
47253 + if (i == 8) {
47254 + done = 1;
47255 + ret = -1;
47256 + }
47257 + }
47258 + }
47259 + return ret;
47260 + }
47261 +
47262 +/*
47263 + * use this for FS apps that can span multiple uframes
47264 + */
47265 +static int find_multi_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
47266 +{
47267 + int i;
47268 + int j;
47269 + unsigned short utime;
47270 + int t_left;
47271 + int ret;
47272 + int done;
47273 + unsigned short xtime;
47274 +
47275 + ret = -1;
47276 + utime = _qh->usecs;
47277 + t_left = utime;
47278 + i = 0;
47279 + done = 0;
47280 +loop:
47281 + while (done == 0) {
47282 + if(_hcd->frame_usecs[i] <= 0) {
47283 + i++;
47284 + if (i == 8) {
47285 + done = 1;
47286 + ret = -1;
47287 + }
47288 + goto loop;
47289 + }
47290 +
47291 + /*
47292 + * we need n consecutive slots
47293 + * so use j as a start slot j plus j+1 must be enough time (for now)
47294 + */
47295 + xtime= _hcd->frame_usecs[i];
47296 + for (j = i+1 ; j < 8 ; j++ ) {
47297 + /*
47298 + * if we add this frame remaining time to xtime we may
47299 + * be OK, if not we need to test j for a complete frame
47300 + */
47301 + if ((xtime+_hcd->frame_usecs[j]) < utime) {
47302 + if (_hcd->frame_usecs[j] < max_uframe_usecs[j]) {
47303 + j = 8;
47304 + ret = -1;
47305 + continue;
47306 + }
47307 + }
47308 + if (xtime >= utime) {
47309 + ret = i;
47310 + j = 8; /* stop loop with a good value ret */
47311 + continue;
47312 + }
47313 + /* add the frame time to x time */
47314 + xtime += _hcd->frame_usecs[j];
47315 + /* we must have a fully available next frame or break */
47316 + if ((xtime < utime)
47317 + && (_hcd->frame_usecs[j] == max_uframe_usecs[j])) {
47318 + ret = -1;
47319 + j = 8; /* stop loop with a bad value ret */
47320 + continue;
47321 + }
47322 + }
47323 + if (ret >= 0) {
47324 + t_left = utime;
47325 + for (j = i; (t_left>0) && (j < 8); j++ ) {
47326 + t_left -= _hcd->frame_usecs[j];
47327 + if ( t_left <= 0 ) {
47328 + _qh->frame_usecs[j] += _hcd->frame_usecs[j] + t_left;
47329 + _hcd->frame_usecs[j]= -t_left;
47330 + ret = i;
47331 + done = 1;
47332 + } else {
47333 + _qh->frame_usecs[j] += _hcd->frame_usecs[j];
47334 + _hcd->frame_usecs[j] = 0;
47335 + }
47336 + }
47337 + } else {
47338 + i++;
47339 + if (i == 8) {
47340 + done = 1;
47341 + ret = -1;
47342 + }
47343 + }
47344 + }
47345 + return ret;
47346 +}
47347 +
47348 +static int find_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
47349 +{
47350 + int ret;
47351 + ret = -1;
47352 +
47353 + if (_qh->speed == USB_SPEED_HIGH) {
47354 + /* if this is a hs transaction we need a full frame */
47355 + ret = find_single_uframe(_hcd, _qh);
47356 + } else {
47357 + /* if this is a fs transaction we may need a sequence of frames */
47358 + ret = find_multi_uframe(_hcd, _qh);
47359 + }
47360 + return ret;
47361 +}
47362 +
47363 +/**
47364 + * Checks that the max transfer size allowed in a host channel is large enough
47365 + * to handle the maximum data transfer in a single (micro)frame for a periodic
47366 + * transfer.
47367 + *
47368 + * @param hcd The HCD state structure for the DWC OTG controller.
47369 + * @param qh QH for a periodic endpoint.
47370 + *
47371 + * @return 0 if successful, negative error code otherwise.
47372 + */
47373 +static int check_max_xfer_size(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
47374 +{
47375 + int status;
47376 + uint32_t max_xfer_size;
47377 + uint32_t max_channel_xfer_size;
47378 +
47379 + status = 0;
47380 +
47381 + max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp);
47382 + max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size;
47383 +
47384 + if (max_xfer_size > max_channel_xfer_size) {
47385 + DWC_INFO("%s: Periodic xfer length %d > " "max xfer length for channel %d\n",
47386 + __func__, max_xfer_size, max_channel_xfer_size); //NOTICE
47387 + status = -DWC_E_NO_SPACE;
47388 + }
47389 +
47390 + return status;
47391 +}
47392 +
47393 +
47394 +
47395 +/**
47396 + * Schedules an interrupt or isochronous transfer in the periodic schedule.
47397 + *
47398 + * @param hcd The HCD state structure for the DWC OTG controller.
47399 + * @param qh QH for the periodic transfer. The QH should already contain the
47400 + * scheduling information.
47401 + *
47402 + * @return 0 if successful, negative error code otherwise.
47403 + */
47404 +static int schedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
47405 +{
47406 + int status = 0;
47407 +
47408 + if (microframe_schedule) {
47409 + int frame;
47410 + status = find_uframe(hcd, qh);
47411 + frame = -1;
47412 + if (status == 0) {
47413 + frame = 7;
47414 + } else {
47415 + if (status > 0 )
47416 + frame = status-1;
47417 + }
47418 +
47419 + /* Set the new frame up */
47420 + if (frame > -1) {
47421 + qh->sched_frame &= ~0x7;
47422 + qh->sched_frame |= (frame & 7);
47423 + }
47424 +
47425 + if (status != -1)
47426 + status = 0;
47427 + } else {
47428 + status = periodic_channel_available(hcd);
47429 + if (status) {
47430 + DWC_INFO("%s: No host channel available for periodic " "transfer.\n", __func__); //NOTICE
47431 + return status;
47432 + }
47433 +
47434 + status = check_periodic_bandwidth(hcd, qh);
47435 + }
47436 + if (status) {
47437 + DWC_INFO("%s: Insufficient periodic bandwidth for "
47438 + "periodic transfer.\n", __func__);
47439 + return status;
47440 + }
47441 + status = check_max_xfer_size(hcd, qh);
47442 + if (status) {
47443 + DWC_INFO("%s: Channel max transfer size too small "
47444 + "for periodic transfer.\n", __func__);
47445 + return status;
47446 + }
47447 +
47448 + if (hcd->core_if->dma_desc_enable) {
47449 + /* Don't rely on SOF and start in ready schedule */
47450 + DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_ready, &qh->qh_list_entry);
47451 + }
47452 + else {
47453 + if(fiq_enable && (DWC_LIST_EMPTY(&hcd->periodic_sched_inactive) || dwc_frame_num_le(qh->sched_frame, hcd->fiq_state->next_sched_frame)))
47454 + {
47455 + hcd->fiq_state->next_sched_frame = qh->sched_frame;
47456 +
47457 + }
47458 + /* Always start in the inactive schedule. */
47459 + DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_inactive, &qh->qh_list_entry);
47460 + }
47461 +
47462 + if (!microframe_schedule) {
47463 + /* Reserve the periodic channel. */
47464 + hcd->periodic_channels++;
47465 + }
47466 +
47467 + /* Update claimed usecs per (micro)frame. */
47468 + hcd->periodic_usecs += qh->usecs;
47469 +
47470 + return status;
47471 +}
47472 +
47473 +
47474 +/**
47475 + * This function adds a QH to either the non periodic or periodic schedule if
47476 + * it is not already in the schedule. If the QH is already in the schedule, no
47477 + * action is taken.
47478 + *
47479 + * @return 0 if successful, negative error code otherwise.
47480 + */
47481 +int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
47482 +{
47483 + int status = 0;
47484 + gintmsk_data_t intr_mask = {.d32 = 0 };
47485 +
47486 + if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
47487 + /* QH already in a schedule. */
47488 + return status;
47489 + }
47490 +
47491 + /* Add the new QH to the appropriate schedule */
47492 + if (dwc_qh_is_non_per(qh)) {
47493 + /* Always start in the inactive schedule. */
47494 + DWC_LIST_INSERT_TAIL(&hcd->non_periodic_sched_inactive,
47495 + &qh->qh_list_entry);
47496 + //hcd->fiq_state->kick_np_queues = 1;
47497 + } else {
47498 + status = schedule_periodic(hcd, qh);
47499 + if ( !hcd->periodic_qh_count ) {
47500 + intr_mask.b.sofintr = 1;
47501 + if (fiq_enable) {
47502 + local_fiq_disable();
47503 + fiq_fsm_spin_lock(&hcd->fiq_state->lock);
47504 + DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
47505 + fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
47506 + local_fiq_enable();
47507 + } else {
47508 + DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
47509 + }
47510 + }
47511 + hcd->periodic_qh_count++;
47512 + }
47513 +
47514 + return status;
47515 +}
47516 +
47517 +/**
47518 + * Removes an interrupt or isochronous transfer from the periodic schedule.
47519 + *
47520 + * @param hcd The HCD state structure for the DWC OTG controller.
47521 + * @param qh QH for the periodic transfer.
47522 + */
47523 +static void deschedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
47524 +{
47525 + int i;
47526 + DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
47527 +
47528 + /* Update claimed usecs per (micro)frame. */
47529 + hcd->periodic_usecs -= qh->usecs;
47530 +
47531 + if (!microframe_schedule) {
47532 + /* Release the periodic channel reservation. */
47533 + hcd->periodic_channels--;
47534 + } else {
47535 + for (i = 0; i < 8; i++) {
47536 + hcd->frame_usecs[i] += qh->frame_usecs[i];
47537 + qh->frame_usecs[i] = 0;
47538 + }
47539 + }
47540 +}
47541 +
47542 +/**
47543 + * Removes a QH from either the non-periodic or periodic schedule. Memory is
47544 + * not freed.
47545 + *
47546 + * @param hcd The HCD state structure.
47547 + * @param qh QH to remove from schedule. */
47548 +void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
47549 +{
47550 + gintmsk_data_t intr_mask = {.d32 = 0 };
47551 +
47552 + if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
47553 + /* QH is not in a schedule. */
47554 + return;
47555 + }
47556 +
47557 + if (dwc_qh_is_non_per(qh)) {
47558 + if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) {
47559 + hcd->non_periodic_qh_ptr =
47560 + hcd->non_periodic_qh_ptr->next;
47561 + }
47562 + DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
47563 + //if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_inactive))
47564 + // hcd->fiq_state->kick_np_queues = 1;
47565 + } else {
47566 + deschedule_periodic(hcd, qh);
47567 + hcd->periodic_qh_count--;
47568 + if( !hcd->periodic_qh_count && !fiq_fsm_enable ) {
47569 + intr_mask.b.sofintr = 1;
47570 + if (fiq_enable) {
47571 + local_fiq_disable();
47572 + fiq_fsm_spin_lock(&hcd->fiq_state->lock);
47573 + DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
47574 + fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
47575 + local_fiq_enable();
47576 + } else {
47577 + DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
47578 + }
47579 + }
47580 + }
47581 +}
47582 +
47583 +/**
47584 + * Deactivates a QH. For non-periodic QHs, removes the QH from the active
47585 + * non-periodic schedule. The QH is added to the inactive non-periodic
47586 + * schedule if any QTDs are still attached to the QH.
47587 + *
47588 + * For periodic QHs, the QH is removed from the periodic queued schedule. If
47589 + * there are any QTDs still attached to the QH, the QH is added to either the
47590 + * periodic inactive schedule or the periodic ready schedule and its next
47591 + * scheduled frame is calculated. The QH is placed in the ready schedule if
47592 + * the scheduled frame has been reached already. Otherwise it's placed in the
47593 + * inactive schedule. If there are no QTDs attached to the QH, the QH is
47594 + * completely removed from the periodic schedule.
47595 + */
47596 +void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
47597 + int sched_next_periodic_split)
47598 +{
47599 + if (dwc_qh_is_non_per(qh)) {
47600 + dwc_otg_hcd_qh_remove(hcd, qh);
47601 + if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
47602 + /* Add back to inactive non-periodic schedule. */
47603 + dwc_otg_hcd_qh_add(hcd, qh);
47604 + //hcd->fiq_state->kick_np_queues = 1;
47605 + }
47606 + } else {
47607 + uint16_t frame_number = dwc_otg_hcd_get_frame_number(hcd);
47608 +
47609 + if (qh->do_split) {
47610 + /* Schedule the next continuing periodic split transfer */
47611 + if (sched_next_periodic_split) {
47612 +
47613 + qh->sched_frame = frame_number;
47614 +
47615 + if (dwc_frame_num_le(frame_number,
47616 + dwc_frame_num_inc
47617 + (qh->start_split_frame,
47618 + 1))) {
47619 + /*
47620 + * Allow one frame to elapse after start
47621 + * split microframe before scheduling
47622 + * complete split, but DONT if we are
47623 + * doing the next start split in the
47624 + * same frame for an ISOC out.
47625 + */
47626 + if ((qh->ep_type != UE_ISOCHRONOUS) ||
47627 + (qh->ep_is_in != 0)) {
47628 + qh->sched_frame =
47629 + dwc_frame_num_inc(qh->sched_frame, 1);
47630 + }
47631 + }
47632 + } else {
47633 + qh->sched_frame =
47634 + dwc_frame_num_inc(qh->start_split_frame,
47635 + qh->interval);
47636 + if (dwc_frame_num_le
47637 + (qh->sched_frame, frame_number)) {
47638 + qh->sched_frame = frame_number;
47639 + }
47640 + qh->sched_frame |= 0x7;
47641 + qh->start_split_frame = qh->sched_frame;
47642 + }
47643 + } else {
47644 + qh->sched_frame =
47645 + dwc_frame_num_inc(qh->sched_frame, qh->interval);
47646 + if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
47647 + qh->sched_frame = frame_number;
47648 + }
47649 + }
47650 +
47651 + if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
47652 + dwc_otg_hcd_qh_remove(hcd, qh);
47653 + } else {
47654 + /*
47655 + * Remove from periodic_sched_queued and move to
47656 + * appropriate queue.
47657 + */
47658 + if ((microframe_schedule && dwc_frame_num_le(qh->sched_frame, frame_number)) ||
47659 + (!microframe_schedule && qh->sched_frame == frame_number)) {
47660 + DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
47661 + &qh->qh_list_entry);
47662 + } else {
47663 + if(fiq_enable && !dwc_frame_num_le(hcd->fiq_state->next_sched_frame, qh->sched_frame))
47664 + {
47665 + hcd->fiq_state->next_sched_frame = qh->sched_frame;
47666 + }
47667 +
47668 + DWC_LIST_MOVE_HEAD
47669 + (&hcd->periodic_sched_inactive,
47670 + &qh->qh_list_entry);
47671 + }
47672 + }
47673 + }
47674 +}
47675 +
47676 +/**
47677 + * This function allocates and initializes a QTD.
47678 + *
47679 + * @param urb The URB to create a QTD from. Each URB-QTD pair will end up
47680 + * pointing to each other so each pair should have a unique correlation.
47681 + * @param atomic_alloc Flag to do atomic alloc if needed
47682 + *
47683 + * @return Returns pointer to the newly allocated QTD, or NULL on error. */
47684 +dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb, int atomic_alloc)
47685 +{
47686 + dwc_otg_qtd_t *qtd;
47687 +
47688 + qtd = dwc_otg_hcd_qtd_alloc(atomic_alloc);
47689 + if (qtd == NULL) {
47690 + return NULL;
47691 + }
47692 +
47693 + dwc_otg_hcd_qtd_init(qtd, urb);
47694 + return qtd;
47695 +}
47696 +
47697 +/**
47698 + * Initializes a QTD structure.
47699 + *
47700 + * @param qtd The QTD to initialize.
47701 + * @param urb The URB to use for initialization. */
47702 +void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb)
47703 +{
47704 + dwc_memset(qtd, 0, sizeof(dwc_otg_qtd_t));
47705 + qtd->urb = urb;
47706 + if (dwc_otg_hcd_get_pipe_type(&urb->pipe_info) == UE_CONTROL) {
47707 + /*
47708 + * The only time the QTD data toggle is used is on the data
47709 + * phase of control transfers. This phase always starts with
47710 + * DATA1.
47711 + */
47712 + qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
47713 + qtd->control_phase = DWC_OTG_CONTROL_SETUP;
47714 + }
47715 +
47716 + /* start split */
47717 + qtd->complete_split = 0;
47718 + qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
47719 + qtd->isoc_split_offset = 0;
47720 + qtd->in_process = 0;
47721 +
47722 + /* Store the qtd ptr in the urb to reference what QTD. */
47723 + urb->qtd = qtd;
47724 + return;
47725 +}
47726 +
47727 +/**
47728 + * This function adds a QTD to the QTD-list of a QH. It will find the correct
47729 + * QH to place the QTD into. If it does not find a QH, then it will create a
47730 + * new QH. If the QH to which the QTD is added is not currently scheduled, it
47731 + * is placed into the proper schedule based on its EP type.
47732 + * HCD lock must be held and interrupts must be disabled on entry
47733 + *
47734 + * @param[in] qtd The QTD to add
47735 + * @param[in] hcd The DWC HCD structure
47736 + * @param[out] qh out parameter to return queue head
47737 + * @param atomic_alloc Flag to do atomic alloc if needed
47738 + *
47739 + * @return 0 if successful, negative error code otherwise.
47740 + */
47741 +int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd,
47742 + dwc_otg_hcd_t * hcd, dwc_otg_qh_t ** qh, int atomic_alloc)
47743 +{
47744 + int retval = 0;
47745 + dwc_otg_hcd_urb_t *urb = qtd->urb;
47746 +
47747 + /*
47748 + * Get the QH which holds the QTD-list to insert to. Create QH if it
47749 + * doesn't exist.
47750 + */
47751 + if (*qh == NULL) {
47752 + *qh = dwc_otg_hcd_qh_create(hcd, urb, atomic_alloc);
47753 + if (*qh == NULL) {
47754 + retval = -DWC_E_NO_MEMORY;
47755 + goto done;
47756 + } else {
47757 + if (fiq_enable)
47758 + hcd->fiq_state->kick_np_queues = 1;
47759 + }
47760 + }
47761 + retval = dwc_otg_hcd_qh_add(hcd, *qh);
47762 + if (retval == 0) {
47763 + DWC_CIRCLEQ_INSERT_TAIL(&((*qh)->qtd_list), qtd,
47764 + qtd_list_entry);
47765 + qtd->qh = *qh;
47766 + }
47767 +done:
47768 +
47769 + return retval;
47770 +}
47771 +
47772 +#endif /* DWC_DEVICE_ONLY */
47773 --- /dev/null
47774 +++ b/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h
47775 @@ -0,0 +1,188 @@
47776 +#ifndef _DWC_OS_DEP_H_
47777 +#define _DWC_OS_DEP_H_
47778 +
47779 +/**
47780 + * @file
47781 + *
47782 + * This file contains OS dependent structures.
47783 + *
47784 + */
47785 +
47786 +#include <linux/kernel.h>
47787 +#include <linux/module.h>
47788 +#include <linux/moduleparam.h>
47789 +#include <linux/init.h>
47790 +#include <linux/device.h>
47791 +#include <linux/errno.h>
47792 +#include <linux/types.h>
47793 +#include <linux/slab.h>
47794 +#include <linux/list.h>
47795 +#include <linux/interrupt.h>
47796 +#include <linux/ctype.h>
47797 +#include <linux/string.h>
47798 +#include <linux/dma-mapping.h>
47799 +#include <linux/jiffies.h>
47800 +#include <linux/delay.h>
47801 +#include <linux/timer.h>
47802 +#include <linux/workqueue.h>
47803 +#include <linux/stat.h>
47804 +#include <linux/pci.h>
47805 +
47806 +#include <linux/version.h>
47807 +
47808 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
47809 +# include <linux/irq.h>
47810 +#endif
47811 +
47812 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
47813 +# include <linux/usb/ch9.h>
47814 +#else
47815 +# include <linux/usb_ch9.h>
47816 +#endif
47817 +
47818 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
47819 +# include <linux/usb/gadget.h>
47820 +#else
47821 +# include <linux/usb_gadget.h>
47822 +#endif
47823 +
47824 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
47825 +# include <asm/irq.h>
47826 +#endif
47827 +
47828 +#ifdef PCI_INTERFACE
47829 +# include <asm/io.h>
47830 +#endif
47831 +
47832 +#ifdef LM_INTERFACE
47833 +# include <asm/unaligned.h>
47834 +# include <asm/sizes.h>
47835 +# include <asm/param.h>
47836 +# include <asm/io.h>
47837 +# if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
47838 +# include <asm/arch/hardware.h>
47839 +# include <asm/arch/lm.h>
47840 +# include <asm/arch/irqs.h>
47841 +# include <asm/arch/regs-irq.h>
47842 +# else
47843 +/* in 2.6.31, at least, we seem to have lost the generic LM infrastructure -
47844 + here we assume that the machine architecture provides definitions
47845 + in its own header
47846 +*/
47847 +# include <mach/lm.h>
47848 +# include <mach/hardware.h>
47849 +# endif
47850 +#endif
47851 +
47852 +#ifdef PLATFORM_INTERFACE
47853 +#include <linux/platform_device.h>
47854 +#include <asm/mach/map.h>
47855 +#endif
47856 +
47857 +/** The OS page size */
47858 +#define DWC_OS_PAGE_SIZE PAGE_SIZE
47859 +
47860 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14)
47861 +typedef int gfp_t;
47862 +#endif
47863 +
47864 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)
47865 +# define IRQF_SHARED SA_SHIRQ
47866 +#endif
47867 +
47868 +typedef struct os_dependent {
47869 + /** Base address returned from ioremap() */
47870 + void *base;
47871 +
47872 + /** Register offset for Diagnostic API */
47873 + uint32_t reg_offset;
47874 +
47875 + /** Base address for MPHI peripheral */
47876 + void *mphi_base;
47877 +
47878 +#ifdef LM_INTERFACE
47879 + struct lm_device *lmdev;
47880 +#elif defined(PCI_INTERFACE)
47881 + struct pci_dev *pcidev;
47882 +
47883 + /** Start address of a PCI region */
47884 + resource_size_t rsrc_start;
47885 +
47886 + /** Length address of a PCI region */
47887 + resource_size_t rsrc_len;
47888 +#elif defined(PLATFORM_INTERFACE)
47889 + struct platform_device *platformdev;
47890 +#endif
47891 +
47892 +} os_dependent_t;
47893 +
47894 +#ifdef __cplusplus
47895 +}
47896 +#endif
47897 +
47898 +
47899 +
47900 +/* Type for the our device on the chosen bus */
47901 +#if defined(LM_INTERFACE)
47902 +typedef struct lm_device dwc_bus_dev_t;
47903 +#elif defined(PCI_INTERFACE)
47904 +typedef struct pci_dev dwc_bus_dev_t;
47905 +#elif defined(PLATFORM_INTERFACE)
47906 +typedef struct platform_device dwc_bus_dev_t;
47907 +#endif
47908 +
47909 +/* Helper macro to retrieve drvdata from the device on the chosen bus */
47910 +#if defined(LM_INTERFACE)
47911 +#define DWC_OTG_BUSDRVDATA(_dev) lm_get_drvdata(_dev)
47912 +#elif defined(PCI_INTERFACE)
47913 +#define DWC_OTG_BUSDRVDATA(_dev) pci_get_drvdata(_dev)
47914 +#elif defined(PLATFORM_INTERFACE)
47915 +#define DWC_OTG_BUSDRVDATA(_dev) platform_get_drvdata(_dev)
47916 +#endif
47917 +
47918 +/**
47919 + * Helper macro returning the otg_device structure of a given struct device
47920 + *
47921 + * c.f. static dwc_otg_device_t *dwc_otg_drvdev(struct device *_dev)
47922 + */
47923 +#ifdef LM_INTERFACE
47924 +#define DWC_OTG_GETDRVDEV(_var, _dev) do { \
47925 + struct lm_device *lm_dev = \
47926 + container_of(_dev, struct lm_device, dev); \
47927 + _var = lm_get_drvdata(lm_dev); \
47928 + } while (0)
47929 +
47930 +#elif defined(PCI_INTERFACE)
47931 +#define DWC_OTG_GETDRVDEV(_var, _dev) do { \
47932 + _var = dev_get_drvdata(_dev); \
47933 + } while (0)
47934 +
47935 +#elif defined(PLATFORM_INTERFACE)
47936 +#define DWC_OTG_GETDRVDEV(_var, _dev) do { \
47937 + struct platform_device *platform_dev = \
47938 + container_of(_dev, struct platform_device, dev); \
47939 + _var = platform_get_drvdata(platform_dev); \
47940 + } while (0)
47941 +#endif
47942 +
47943 +
47944 +/**
47945 + * Helper macro returning the struct dev of the given struct os_dependent
47946 + *
47947 + * c.f. static struct device *dwc_otg_getdev(struct os_dependent *osdep)
47948 + */
47949 +#ifdef LM_INTERFACE
47950 +#define DWC_OTG_OS_GETDEV(_osdep) \
47951 + ((_osdep).lmdev == NULL? NULL: &(_osdep).lmdev->dev)
47952 +#elif defined(PCI_INTERFACE)
47953 +#define DWC_OTG_OS_GETDEV(_osdep) \
47954 + ((_osdep).pci_dev == NULL? NULL: &(_osdep).pci_dev->dev)
47955 +#elif defined(PLATFORM_INTERFACE)
47956 +#define DWC_OTG_OS_GETDEV(_osdep) \
47957 + ((_osdep).platformdev == NULL? NULL: &(_osdep).platformdev->dev)
47958 +#endif
47959 +
47960 +
47961 +
47962 +
47963 +#endif /* _DWC_OS_DEP_H_ */
47964 --- /dev/null
47965 +++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd.c
47966 @@ -0,0 +1,2712 @@
47967 +/* ==========================================================================
47968 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $
47969 + * $Revision: #101 $
47970 + * $Date: 2012/08/10 $
47971 + * $Change: 2047372 $
47972 + *
47973 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
47974 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
47975 + * otherwise expressly agreed to in writing between Synopsys and you.
47976 + *
47977 + * The Software IS NOT an item of Licensed Software or Licensed Product under
47978 + * any End User Software License Agreement or Agreement for Licensed Product
47979 + * with Synopsys or any supplement thereto. You are permitted to use and
47980 + * redistribute this Software in source and binary forms, with or without
47981 + * modification, provided that redistributions of source code must retain this
47982 + * notice. You may not view, use, disclose, copy or distribute this file or
47983 + * any information contained herein except pursuant to this license grant from
47984 + * Synopsys. If you do not agree with this notice, including the disclaimer
47985 + * below, then you are not authorized to use the Software.
47986 + *
47987 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
47988 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
47989 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
47990 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
47991 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
47992 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
47993 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
47994 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
47995 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
47996 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
47997 + * DAMAGE.
47998 + * ========================================================================== */
47999 +#ifndef DWC_HOST_ONLY
48000 +
48001 +/** @file
48002 + * This file implements PCD Core. All code in this file is portable and doesn't
48003 + * use any OS specific functions.
48004 + * PCD Core provides Interface, defined in <code><dwc_otg_pcd_if.h></code>
48005 + * header file, which can be used to implement OS specific PCD interface.
48006 + *
48007 + * An important function of the PCD is managing interrupts generated
48008 + * by the DWC_otg controller. The implementation of the DWC_otg device
48009 + * mode interrupt service routines is in dwc_otg_pcd_intr.c.
48010 + *
48011 + * @todo Add Device Mode test modes (Test J mode, Test K mode, etc).
48012 + * @todo Does it work when the request size is greater than DEPTSIZ
48013 + * transfer size
48014 + *
48015 + */
48016 +
48017 +#include "dwc_otg_pcd.h"
48018 +
48019 +#ifdef DWC_UTE_CFI
48020 +#include "dwc_otg_cfi.h"
48021 +
48022 +extern int init_cfi(cfiobject_t * cfiobj);
48023 +#endif
48024 +
48025 +/**
48026 + * Choose endpoint from ep arrays using usb_ep structure.
48027 + */
48028 +static dwc_otg_pcd_ep_t *get_ep_from_handle(dwc_otg_pcd_t * pcd, void *handle)
48029 +{
48030 + int i;
48031 + if (pcd->ep0.priv == handle) {
48032 + return &pcd->ep0;
48033 + }
48034 + for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) {
48035 + if (pcd->in_ep[i].priv == handle)
48036 + return &pcd->in_ep[i];
48037 + if (pcd->out_ep[i].priv == handle)
48038 + return &pcd->out_ep[i];
48039 + }
48040 +
48041 + return NULL;
48042 +}
48043 +
48044 +/**
48045 + * This function completes a request. It call's the request call back.
48046 + */
48047 +void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req,
48048 + int32_t status)
48049 +{
48050 + unsigned stopped = ep->stopped;
48051 +
48052 + DWC_DEBUGPL(DBG_PCDV, "%s(ep %p req %p)\n", __func__, ep, req);
48053 + DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry);
48054 +
48055 + /* don't modify queue heads during completion callback */
48056 + ep->stopped = 1;
48057 + /* spin_unlock/spin_lock now done in fops->complete() */
48058 + ep->pcd->fops->complete(ep->pcd, ep->priv, req->priv, status,
48059 + req->actual);
48060 +
48061 + if (ep->pcd->request_pending > 0) {
48062 + --ep->pcd->request_pending;
48063 + }
48064 +
48065 + ep->stopped = stopped;
48066 + DWC_FREE(req);
48067 +}
48068 +
48069 +/**
48070 + * This function terminates all the requsts in the EP request queue.
48071 + */
48072 +void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep)
48073 +{
48074 + dwc_otg_pcd_request_t *req;
48075 +
48076 + ep->stopped = 1;
48077 +
48078 + /* called with irqs blocked?? */
48079 + while (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
48080 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
48081 + dwc_otg_request_done(ep, req, -DWC_E_SHUTDOWN);
48082 + }
48083 +}
48084 +
48085 +void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
48086 + const struct dwc_otg_pcd_function_ops *fops)
48087 +{
48088 + pcd->fops = fops;
48089 +}
48090 +
48091 +/**
48092 + * PCD Callback function for initializing the PCD when switching to
48093 + * device mode.
48094 + *
48095 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
48096 + */
48097 +static int32_t dwc_otg_pcd_start_cb(void *p)
48098 +{
48099 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
48100 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
48101 +
48102 + /*
48103 + * Initialized the Core for Device mode.
48104 + */
48105 + if (dwc_otg_is_device_mode(core_if)) {
48106 + dwc_otg_core_dev_init(core_if);
48107 + /* Set core_if's lock pointer to the pcd->lock */
48108 + core_if->lock = pcd->lock;
48109 + }
48110 + return 1;
48111 +}
48112 +
48113 +/** CFI-specific buffer allocation function for EP */
48114 +#ifdef DWC_UTE_CFI
48115 +uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
48116 + size_t buflen, int flags)
48117 +{
48118 + dwc_otg_pcd_ep_t *ep;
48119 + ep = get_ep_from_handle(pcd, pep);
48120 + if (!ep) {
48121 + DWC_WARN("bad ep\n");
48122 + return -DWC_E_INVALID;
48123 + }
48124 +
48125 + return pcd->cfi->ops.ep_alloc_buf(pcd->cfi, pcd, ep, addr, buflen,
48126 + flags);
48127 +}
48128 +#else
48129 +uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
48130 + size_t buflen, int flags);
48131 +#endif
48132 +
48133 +/**
48134 + * PCD Callback function for notifying the PCD when resuming from
48135 + * suspend.
48136 + *
48137 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
48138 + */
48139 +static int32_t dwc_otg_pcd_resume_cb(void *p)
48140 +{
48141 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
48142 +
48143 + if (pcd->fops->resume) {
48144 + pcd->fops->resume(pcd);
48145 + }
48146 +
48147 + /* Stop the SRP timeout timer. */
48148 + if ((GET_CORE_IF(pcd)->core_params->phy_type != DWC_PHY_TYPE_PARAM_FS)
48149 + || (!GET_CORE_IF(pcd)->core_params->i2c_enable)) {
48150 + if (GET_CORE_IF(pcd)->srp_timer_started) {
48151 + GET_CORE_IF(pcd)->srp_timer_started = 0;
48152 + DWC_TIMER_CANCEL(GET_CORE_IF(pcd)->srp_timer);
48153 + }
48154 + }
48155 + return 1;
48156 +}
48157 +
48158 +/**
48159 + * PCD Callback function for notifying the PCD device is suspended.
48160 + *
48161 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
48162 + */
48163 +static int32_t dwc_otg_pcd_suspend_cb(void *p)
48164 +{
48165 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
48166 +
48167 + if (pcd->fops->suspend) {
48168 + DWC_SPINUNLOCK(pcd->lock);
48169 + pcd->fops->suspend(pcd);
48170 + DWC_SPINLOCK(pcd->lock);
48171 + }
48172 +
48173 + return 1;
48174 +}
48175 +
48176 +/**
48177 + * PCD Callback function for stopping the PCD when switching to Host
48178 + * mode.
48179 + *
48180 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
48181 + */
48182 +static int32_t dwc_otg_pcd_stop_cb(void *p)
48183 +{
48184 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
48185 + extern void dwc_otg_pcd_stop(dwc_otg_pcd_t * _pcd);
48186 +
48187 + dwc_otg_pcd_stop(pcd);
48188 + return 1;
48189 +}
48190 +
48191 +/**
48192 + * PCD Callback structure for handling mode switching.
48193 + */
48194 +static dwc_otg_cil_callbacks_t pcd_callbacks = {
48195 + .start = dwc_otg_pcd_start_cb,
48196 + .stop = dwc_otg_pcd_stop_cb,
48197 + .suspend = dwc_otg_pcd_suspend_cb,
48198 + .resume_wakeup = dwc_otg_pcd_resume_cb,
48199 + .p = 0, /* Set at registration */
48200 +};
48201 +
48202 +/**
48203 + * This function allocates a DMA Descriptor chain for the Endpoint
48204 + * buffer to be used for a transfer to/from the specified endpoint.
48205 + */
48206 +dwc_otg_dev_dma_desc_t *dwc_otg_ep_alloc_desc_chain(dwc_dma_t * dma_desc_addr,
48207 + uint32_t count)
48208 +{
48209 + return DWC_DMA_ALLOC_ATOMIC(count * sizeof(dwc_otg_dev_dma_desc_t),
48210 + dma_desc_addr);
48211 +}
48212 +
48213 +/**
48214 + * This function frees a DMA Descriptor chain that was allocated by ep_alloc_desc.
48215 + */
48216 +void dwc_otg_ep_free_desc_chain(dwc_otg_dev_dma_desc_t * desc_addr,
48217 + uint32_t dma_desc_addr, uint32_t count)
48218 +{
48219 + DWC_DMA_FREE(count * sizeof(dwc_otg_dev_dma_desc_t), desc_addr,
48220 + dma_desc_addr);
48221 +}
48222 +
48223 +#ifdef DWC_EN_ISOC
48224 +
48225 +/**
48226 + * This function initializes a descriptor chain for Isochronous transfer
48227 + *
48228 + * @param core_if Programming view of DWC_otg controller.
48229 + * @param dwc_ep The EP to start the transfer on.
48230 + *
48231 + */
48232 +void dwc_otg_iso_ep_start_ddma_transfer(dwc_otg_core_if_t * core_if,
48233 + dwc_ep_t * dwc_ep)
48234 +{
48235 +
48236 + dsts_data_t dsts = {.d32 = 0 };
48237 + depctl_data_t depctl = {.d32 = 0 };
48238 + volatile uint32_t *addr;
48239 + int i, j;
48240 + uint32_t len;
48241 +
48242 + if (dwc_ep->is_in)
48243 + dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl / dwc_ep->bInterval;
48244 + else
48245 + dwc_ep->desc_cnt =
48246 + dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
48247 + dwc_ep->bInterval;
48248 +
48249 + /** Allocate descriptors for double buffering */
48250 + dwc_ep->iso_desc_addr =
48251 + dwc_otg_ep_alloc_desc_chain(&dwc_ep->iso_dma_desc_addr,
48252 + dwc_ep->desc_cnt * 2);
48253 + if (dwc_ep->desc_addr) {
48254 + DWC_WARN("%s, can't allocate DMA descriptor chain\n", __func__);
48255 + return;
48256 + }
48257 +
48258 + dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
48259 +
48260 + /** ISO OUT EP */
48261 + if (dwc_ep->is_in == 0) {
48262 + dev_dma_desc_sts_t sts = {.d32 = 0 };
48263 + dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
48264 + dma_addr_t dma_ad;
48265 + uint32_t data_per_desc;
48266 + dwc_otg_dev_out_ep_regs_t *out_regs =
48267 + core_if->dev_if->out_ep_regs[dwc_ep->num];
48268 + int offset;
48269 +
48270 + addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
48271 + dma_ad = (dma_addr_t) DWC_READ_REG32(&(out_regs->doepdma));
48272 +
48273 + /** Buffer 0 descriptors setup */
48274 + dma_ad = dwc_ep->dma_addr0;
48275 +
48276 + sts.b_iso_out.bs = BS_HOST_READY;
48277 + sts.b_iso_out.rxsts = 0;
48278 + sts.b_iso_out.l = 0;
48279 + sts.b_iso_out.sp = 0;
48280 + sts.b_iso_out.ioc = 0;
48281 + sts.b_iso_out.pid = 0;
48282 + sts.b_iso_out.framenum = 0;
48283 +
48284 + offset = 0;
48285 + for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
48286 + i += dwc_ep->pkt_per_frm) {
48287 +
48288 + for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
48289 + uint32_t len = (j + 1) * dwc_ep->maxpacket;
48290 + if (len > dwc_ep->data_per_frame)
48291 + data_per_desc =
48292 + dwc_ep->data_per_frame -
48293 + j * dwc_ep->maxpacket;
48294 + else
48295 + data_per_desc = dwc_ep->maxpacket;
48296 + len = data_per_desc % 4;
48297 + if (len)
48298 + data_per_desc += 4 - len;
48299 +
48300 + sts.b_iso_out.rxbytes = data_per_desc;
48301 + dma_desc->buf = dma_ad;
48302 + dma_desc->status.d32 = sts.d32;
48303 +
48304 + offset += data_per_desc;
48305 + dma_desc++;
48306 + dma_ad += data_per_desc;
48307 + }
48308 + }
48309 +
48310 + for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
48311 + uint32_t len = (j + 1) * dwc_ep->maxpacket;
48312 + if (len > dwc_ep->data_per_frame)
48313 + data_per_desc =
48314 + dwc_ep->data_per_frame -
48315 + j * dwc_ep->maxpacket;
48316 + else
48317 + data_per_desc = dwc_ep->maxpacket;
48318 + len = data_per_desc % 4;
48319 + if (len)
48320 + data_per_desc += 4 - len;
48321 + sts.b_iso_out.rxbytes = data_per_desc;
48322 + dma_desc->buf = dma_ad;
48323 + dma_desc->status.d32 = sts.d32;
48324 +
48325 + offset += data_per_desc;
48326 + dma_desc++;
48327 + dma_ad += data_per_desc;
48328 + }
48329 +
48330 + sts.b_iso_out.ioc = 1;
48331 + len = (j + 1) * dwc_ep->maxpacket;
48332 + if (len > dwc_ep->data_per_frame)
48333 + data_per_desc =
48334 + dwc_ep->data_per_frame - j * dwc_ep->maxpacket;
48335 + else
48336 + data_per_desc = dwc_ep->maxpacket;
48337 + len = data_per_desc % 4;
48338 + if (len)
48339 + data_per_desc += 4 - len;
48340 + sts.b_iso_out.rxbytes = data_per_desc;
48341 +
48342 + dma_desc->buf = dma_ad;
48343 + dma_desc->status.d32 = sts.d32;
48344 + dma_desc++;
48345 +
48346 + /** Buffer 1 descriptors setup */
48347 + sts.b_iso_out.ioc = 0;
48348 + dma_ad = dwc_ep->dma_addr1;
48349 +
48350 + offset = 0;
48351 + for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
48352 + i += dwc_ep->pkt_per_frm) {
48353 + for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
48354 + uint32_t len = (j + 1) * dwc_ep->maxpacket;
48355 + if (len > dwc_ep->data_per_frame)
48356 + data_per_desc =
48357 + dwc_ep->data_per_frame -
48358 + j * dwc_ep->maxpacket;
48359 + else
48360 + data_per_desc = dwc_ep->maxpacket;
48361 + len = data_per_desc % 4;
48362 + if (len)
48363 + data_per_desc += 4 - len;
48364 +
48365 + data_per_desc =
48366 + sts.b_iso_out.rxbytes = data_per_desc;
48367 + dma_desc->buf = dma_ad;
48368 + dma_desc->status.d32 = sts.d32;
48369 +
48370 + offset += data_per_desc;
48371 + dma_desc++;
48372 + dma_ad += data_per_desc;
48373 + }
48374 + }
48375 + for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
48376 + data_per_desc =
48377 + ((j + 1) * dwc_ep->maxpacket >
48378 + dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
48379 + j * dwc_ep->maxpacket : dwc_ep->maxpacket;
48380 + data_per_desc +=
48381 + (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
48382 + sts.b_iso_out.rxbytes = data_per_desc;
48383 + dma_desc->buf = dma_ad;
48384 + dma_desc->status.d32 = sts.d32;
48385 +
48386 + offset += data_per_desc;
48387 + dma_desc++;
48388 + dma_ad += data_per_desc;
48389 + }
48390 +
48391 + sts.b_iso_out.ioc = 1;
48392 + sts.b_iso_out.l = 1;
48393 + data_per_desc =
48394 + ((j + 1) * dwc_ep->maxpacket >
48395 + dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
48396 + j * dwc_ep->maxpacket : dwc_ep->maxpacket;
48397 + data_per_desc +=
48398 + (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
48399 + sts.b_iso_out.rxbytes = data_per_desc;
48400 +
48401 + dma_desc->buf = dma_ad;
48402 + dma_desc->status.d32 = sts.d32;
48403 +
48404 + dwc_ep->next_frame = 0;
48405 +
48406 + /** Write dma_ad into DOEPDMA register */
48407 + DWC_WRITE_REG32(&(out_regs->doepdma),
48408 + (uint32_t) dwc_ep->iso_dma_desc_addr);
48409 +
48410 + }
48411 + /** ISO IN EP */
48412 + else {
48413 + dev_dma_desc_sts_t sts = {.d32 = 0 };
48414 + dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
48415 + dma_addr_t dma_ad;
48416 + dwc_otg_dev_in_ep_regs_t *in_regs =
48417 + core_if->dev_if->in_ep_regs[dwc_ep->num];
48418 + unsigned int frmnumber;
48419 + fifosize_data_t txfifosize, rxfifosize;
48420 +
48421 + txfifosize.d32 =
48422 + DWC_READ_REG32(&core_if->dev_if->in_ep_regs[dwc_ep->num]->
48423 + dtxfsts);
48424 + rxfifosize.d32 =
48425 + DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
48426 +
48427 + addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
48428 +
48429 + dma_ad = dwc_ep->dma_addr0;
48430 +
48431 + dsts.d32 =
48432 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
48433 +
48434 + sts.b_iso_in.bs = BS_HOST_READY;
48435 + sts.b_iso_in.txsts = 0;
48436 + sts.b_iso_in.sp =
48437 + (dwc_ep->data_per_frame % dwc_ep->maxpacket) ? 1 : 0;
48438 + sts.b_iso_in.ioc = 0;
48439 + sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
48440 +
48441 + frmnumber = dwc_ep->next_frame;
48442 +
48443 + sts.b_iso_in.framenum = frmnumber;
48444 + sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
48445 + sts.b_iso_in.l = 0;
48446 +
48447 + /** Buffer 0 descriptors setup */
48448 + for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
48449 + dma_desc->buf = dma_ad;
48450 + dma_desc->status.d32 = sts.d32;
48451 + dma_desc++;
48452 +
48453 + dma_ad += dwc_ep->data_per_frame;
48454 + sts.b_iso_in.framenum += dwc_ep->bInterval;
48455 + }
48456 +
48457 + sts.b_iso_in.ioc = 1;
48458 + dma_desc->buf = dma_ad;
48459 + dma_desc->status.d32 = sts.d32;
48460 + ++dma_desc;
48461 +
48462 + /** Buffer 1 descriptors setup */
48463 + sts.b_iso_in.ioc = 0;
48464 + dma_ad = dwc_ep->dma_addr1;
48465 +
48466 + for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
48467 + i += dwc_ep->pkt_per_frm) {
48468 + dma_desc->buf = dma_ad;
48469 + dma_desc->status.d32 = sts.d32;
48470 + dma_desc++;
48471 +
48472 + dma_ad += dwc_ep->data_per_frame;
48473 + sts.b_iso_in.framenum += dwc_ep->bInterval;
48474 +
48475 + sts.b_iso_in.ioc = 0;
48476 + }
48477 + sts.b_iso_in.ioc = 1;
48478 + sts.b_iso_in.l = 1;
48479 +
48480 + dma_desc->buf = dma_ad;
48481 + dma_desc->status.d32 = sts.d32;
48482 +
48483 + dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval;
48484 +
48485 + /** Write dma_ad into diepdma register */
48486 + DWC_WRITE_REG32(&(in_regs->diepdma),
48487 + (uint32_t) dwc_ep->iso_dma_desc_addr);
48488 + }
48489 + /** Enable endpoint, clear nak */
48490 + depctl.d32 = 0;
48491 + depctl.b.epena = 1;
48492 + depctl.b.usbactep = 1;
48493 + depctl.b.cnak = 1;
48494 +
48495 + DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
48496 + depctl.d32 = DWC_READ_REG32(addr);
48497 +}
48498 +
48499 +/**
48500 + * This function initializes a descriptor chain for Isochronous transfer
48501 + *
48502 + * @param core_if Programming view of DWC_otg controller.
48503 + * @param ep The EP to start the transfer on.
48504 + *
48505 + */
48506 +void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
48507 + dwc_ep_t * ep)
48508 +{
48509 + depctl_data_t depctl = {.d32 = 0 };
48510 + volatile uint32_t *addr;
48511 +
48512 + if (ep->is_in) {
48513 + addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
48514 + } else {
48515 + addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
48516 + }
48517 +
48518 + if (core_if->dma_enable == 0 || core_if->dma_desc_enable != 0) {
48519 + return;
48520 + } else {
48521 + deptsiz_data_t deptsiz = {.d32 = 0 };
48522 +
48523 + ep->xfer_len =
48524 + ep->data_per_frame * ep->buf_proc_intrvl / ep->bInterval;
48525 + ep->pkt_cnt =
48526 + (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
48527 + ep->xfer_count = 0;
48528 + ep->xfer_buff =
48529 + (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
48530 + ep->dma_addr =
48531 + (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
48532 +
48533 + if (ep->is_in) {
48534 + /* Program the transfer size and packet count
48535 + * as follows: xfersize = N * maxpacket +
48536 + * short_packet pktcnt = N + (short_packet
48537 + * exist ? 1 : 0)
48538 + */
48539 + deptsiz.b.mc = ep->pkt_per_frm;
48540 + deptsiz.b.xfersize = ep->xfer_len;
48541 + deptsiz.b.pktcnt =
48542 + (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
48543 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
48544 + dieptsiz, deptsiz.d32);
48545 +
48546 + /* Write the DMA register */
48547 + DWC_WRITE_REG32(&
48548 + (core_if->dev_if->in_ep_regs[ep->num]->
48549 + diepdma), (uint32_t) ep->dma_addr);
48550 +
48551 + } else {
48552 + deptsiz.b.pktcnt =
48553 + (ep->xfer_len + (ep->maxpacket - 1)) /
48554 + ep->maxpacket;
48555 + deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
48556 +
48557 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
48558 + doeptsiz, deptsiz.d32);
48559 +
48560 + /* Write the DMA register */
48561 + DWC_WRITE_REG32(&
48562 + (core_if->dev_if->out_ep_regs[ep->num]->
48563 + doepdma), (uint32_t) ep->dma_addr);
48564 +
48565 + }
48566 + /** Enable endpoint, clear nak */
48567 + depctl.d32 = 0;
48568 + depctl.b.epena = 1;
48569 + depctl.b.cnak = 1;
48570 +
48571 + DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
48572 + }
48573 +}
48574 +
48575 +/**
48576 + * This function does the setup for a data transfer for an EP and
48577 + * starts the transfer. For an IN transfer, the packets will be
48578 + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
48579 + * the packets are unloaded from the Rx FIFO in the ISR.
48580 + *
48581 + * @param core_if Programming view of DWC_otg controller.
48582 + * @param ep The EP to start the transfer on.
48583 + */
48584 +
48585 +static void dwc_otg_iso_ep_start_transfer(dwc_otg_core_if_t * core_if,
48586 + dwc_ep_t * ep)
48587 +{
48588 + if (core_if->dma_enable) {
48589 + if (core_if->dma_desc_enable) {
48590 + if (ep->is_in) {
48591 + ep->desc_cnt = ep->pkt_cnt / ep->pkt_per_frm;
48592 + } else {
48593 + ep->desc_cnt = ep->pkt_cnt;
48594 + }
48595 + dwc_otg_iso_ep_start_ddma_transfer(core_if, ep);
48596 + } else {
48597 + if (core_if->pti_enh_enable) {
48598 + dwc_otg_iso_ep_start_buf_transfer(core_if, ep);
48599 + } else {
48600 + ep->cur_pkt_addr =
48601 + (ep->proc_buf_num) ? ep->xfer_buff1 : ep->
48602 + xfer_buff0;
48603 + ep->cur_pkt_dma_addr =
48604 + (ep->proc_buf_num) ? ep->dma_addr1 : ep->
48605 + dma_addr0;
48606 + dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
48607 + }
48608 + }
48609 + } else {
48610 + ep->cur_pkt_addr =
48611 + (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
48612 + ep->cur_pkt_dma_addr =
48613 + (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
48614 + dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
48615 + }
48616 +}
48617 +
48618 +/**
48619 + * This function stops transfer for an EP and
48620 + * resets the ep's variables.
48621 + *
48622 + * @param core_if Programming view of DWC_otg controller.
48623 + * @param ep The EP to start the transfer on.
48624 + */
48625 +
48626 +void dwc_otg_iso_ep_stop_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
48627 +{
48628 + depctl_data_t depctl = {.d32 = 0 };
48629 + volatile uint32_t *addr;
48630 +
48631 + if (ep->is_in == 1) {
48632 + addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
48633 + } else {
48634 + addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
48635 + }
48636 +
48637 + /* disable the ep */
48638 + depctl.d32 = DWC_READ_REG32(addr);
48639 +
48640 + depctl.b.epdis = 1;
48641 + depctl.b.snak = 1;
48642 +
48643 + DWC_WRITE_REG32(addr, depctl.d32);
48644 +
48645 + if (core_if->dma_desc_enable &&
48646 + ep->iso_desc_addr && ep->iso_dma_desc_addr) {
48647 + dwc_otg_ep_free_desc_chain(ep->iso_desc_addr,
48648 + ep->iso_dma_desc_addr,
48649 + ep->desc_cnt * 2);
48650 + }
48651 +
48652 + /* reset varibales */
48653 + ep->dma_addr0 = 0;
48654 + ep->dma_addr1 = 0;
48655 + ep->xfer_buff0 = 0;
48656 + ep->xfer_buff1 = 0;
48657 + ep->data_per_frame = 0;
48658 + ep->data_pattern_frame = 0;
48659 + ep->sync_frame = 0;
48660 + ep->buf_proc_intrvl = 0;
48661 + ep->bInterval = 0;
48662 + ep->proc_buf_num = 0;
48663 + ep->pkt_per_frm = 0;
48664 + ep->pkt_per_frm = 0;
48665 + ep->desc_cnt = 0;
48666 + ep->iso_desc_addr = 0;
48667 + ep->iso_dma_desc_addr = 0;
48668 +}
48669 +
48670 +int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
48671 + uint8_t * buf0, uint8_t * buf1, dwc_dma_t dma0,
48672 + dwc_dma_t dma1, int sync_frame, int dp_frame,
48673 + int data_per_frame, int start_frame,
48674 + int buf_proc_intrvl, void *req_handle,
48675 + int atomic_alloc)
48676 +{
48677 + dwc_otg_pcd_ep_t *ep;
48678 + dwc_irqflags_t flags = 0;
48679 + dwc_ep_t *dwc_ep;
48680 + int32_t frm_data;
48681 + dsts_data_t dsts;
48682 + dwc_otg_core_if_t *core_if;
48683 +
48684 + ep = get_ep_from_handle(pcd, ep_handle);
48685 +
48686 + if (!ep || !ep->desc || ep->dwc_ep.num == 0) {
48687 + DWC_WARN("bad ep\n");
48688 + return -DWC_E_INVALID;
48689 + }
48690 +
48691 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
48692 + core_if = GET_CORE_IF(pcd);
48693 + dwc_ep = &ep->dwc_ep;
48694 +
48695 + if (ep->iso_req_handle) {
48696 + DWC_WARN("ISO request in progress\n");
48697 + }
48698 +
48699 + dwc_ep->dma_addr0 = dma0;
48700 + dwc_ep->dma_addr1 = dma1;
48701 +
48702 + dwc_ep->xfer_buff0 = buf0;
48703 + dwc_ep->xfer_buff1 = buf1;
48704 +
48705 + dwc_ep->data_per_frame = data_per_frame;
48706 +
48707 + /** @todo - pattern data support is to be implemented in the future */
48708 + dwc_ep->data_pattern_frame = dp_frame;
48709 + dwc_ep->sync_frame = sync_frame;
48710 +
48711 + dwc_ep->buf_proc_intrvl = buf_proc_intrvl;
48712 +
48713 + dwc_ep->bInterval = 1 << (ep->desc->bInterval - 1);
48714 +
48715 + dwc_ep->proc_buf_num = 0;
48716 +
48717 + dwc_ep->pkt_per_frm = 0;
48718 + frm_data = ep->dwc_ep.data_per_frame;
48719 + while (frm_data > 0) {
48720 + dwc_ep->pkt_per_frm++;
48721 + frm_data -= ep->dwc_ep.maxpacket;
48722 + }
48723 +
48724 + dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
48725 +
48726 + if (start_frame == -1) {
48727 + dwc_ep->next_frame = dsts.b.soffn + 1;
48728 + if (dwc_ep->bInterval != 1) {
48729 + dwc_ep->next_frame =
48730 + dwc_ep->next_frame + (dwc_ep->bInterval - 1 -
48731 + dwc_ep->next_frame %
48732 + dwc_ep->bInterval);
48733 + }
48734 + } else {
48735 + dwc_ep->next_frame = start_frame;
48736 + }
48737 +
48738 + if (!core_if->pti_enh_enable) {
48739 + dwc_ep->pkt_cnt =
48740 + dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
48741 + dwc_ep->bInterval;
48742 + } else {
48743 + dwc_ep->pkt_cnt =
48744 + (dwc_ep->data_per_frame *
48745 + (dwc_ep->buf_proc_intrvl / dwc_ep->bInterval)
48746 + - 1 + dwc_ep->maxpacket) / dwc_ep->maxpacket;
48747 + }
48748 +
48749 + if (core_if->dma_desc_enable) {
48750 + dwc_ep->desc_cnt =
48751 + dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
48752 + dwc_ep->bInterval;
48753 + }
48754 +
48755 + if (atomic_alloc) {
48756 + dwc_ep->pkt_info =
48757 + DWC_ALLOC_ATOMIC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
48758 + } else {
48759 + dwc_ep->pkt_info =
48760 + DWC_ALLOC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
48761 + }
48762 + if (!dwc_ep->pkt_info) {
48763 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
48764 + return -DWC_E_NO_MEMORY;
48765 + }
48766 + if (core_if->pti_enh_enable) {
48767 + dwc_memset(dwc_ep->pkt_info, 0,
48768 + sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
48769 + }
48770 +
48771 + dwc_ep->cur_pkt = 0;
48772 + ep->iso_req_handle = req_handle;
48773 +
48774 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
48775 + dwc_otg_iso_ep_start_transfer(core_if, dwc_ep);
48776 + return 0;
48777 +}
48778 +
48779 +int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
48780 + void *req_handle)
48781 +{
48782 + dwc_irqflags_t flags = 0;
48783 + dwc_otg_pcd_ep_t *ep;
48784 + dwc_ep_t *dwc_ep;
48785 +
48786 + ep = get_ep_from_handle(pcd, ep_handle);
48787 + if (!ep || !ep->desc || ep->dwc_ep.num == 0) {
48788 + DWC_WARN("bad ep\n");
48789 + return -DWC_E_INVALID;
48790 + }
48791 + dwc_ep = &ep->dwc_ep;
48792 +
48793 + dwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd), dwc_ep);
48794 +
48795 + DWC_FREE(dwc_ep->pkt_info);
48796 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
48797 + if (ep->iso_req_handle != req_handle) {
48798 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
48799 + return -DWC_E_INVALID;
48800 + }
48801 +
48802 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
48803 +
48804 + ep->iso_req_handle = 0;
48805 + return 0;
48806 +}
48807 +
48808 +/**
48809 + * This function is used for perodical data exchnage between PCD and gadget drivers.
48810 + * for Isochronous EPs
48811 + *
48812 + * - Every time a sync period completes this function is called to
48813 + * perform data exchange between PCD and gadget
48814 + */
48815 +void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
48816 + void *req_handle)
48817 +{
48818 + int i;
48819 + dwc_ep_t *dwc_ep;
48820 +
48821 + dwc_ep = &ep->dwc_ep;
48822 +
48823 + DWC_SPINUNLOCK(ep->pcd->lock);
48824 + pcd->fops->isoc_complete(pcd, ep->priv, ep->iso_req_handle,
48825 + dwc_ep->proc_buf_num ^ 0x1);
48826 + DWC_SPINLOCK(ep->pcd->lock);
48827 +
48828 + for (i = 0; i < dwc_ep->pkt_cnt; ++i) {
48829 + dwc_ep->pkt_info[i].status = 0;
48830 + dwc_ep->pkt_info[i].offset = 0;
48831 + dwc_ep->pkt_info[i].length = 0;
48832 + }
48833 +}
48834 +
48835 +int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd, void *ep_handle,
48836 + void *iso_req_handle)
48837 +{
48838 + dwc_otg_pcd_ep_t *ep;
48839 + dwc_ep_t *dwc_ep;
48840 +
48841 + ep = get_ep_from_handle(pcd, ep_handle);
48842 + if (!ep->desc || ep->dwc_ep.num == 0) {
48843 + DWC_WARN("bad ep\n");
48844 + return -DWC_E_INVALID;
48845 + }
48846 + dwc_ep = &ep->dwc_ep;
48847 +
48848 + return dwc_ep->pkt_cnt;
48849 +}
48850 +
48851 +void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd, void *ep_handle,
48852 + void *iso_req_handle, int packet,
48853 + int *status, int *actual, int *offset)
48854 +{
48855 + dwc_otg_pcd_ep_t *ep;
48856 + dwc_ep_t *dwc_ep;
48857 +
48858 + ep = get_ep_from_handle(pcd, ep_handle);
48859 + if (!ep)
48860 + DWC_WARN("bad ep\n");
48861 +
48862 + dwc_ep = &ep->dwc_ep;
48863 +
48864 + *status = dwc_ep->pkt_info[packet].status;
48865 + *actual = dwc_ep->pkt_info[packet].length;
48866 + *offset = dwc_ep->pkt_info[packet].offset;
48867 +}
48868 +
48869 +#endif /* DWC_EN_ISOC */
48870 +
48871 +static void dwc_otg_pcd_init_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * pcd_ep,
48872 + uint32_t is_in, uint32_t ep_num)
48873 +{
48874 + /* Init EP structure */
48875 + pcd_ep->desc = 0;
48876 + pcd_ep->pcd = pcd;
48877 + pcd_ep->stopped = 1;
48878 + pcd_ep->queue_sof = 0;
48879 +
48880 + /* Init DWC ep structure */
48881 + pcd_ep->dwc_ep.is_in = is_in;
48882 + pcd_ep->dwc_ep.num = ep_num;
48883 + pcd_ep->dwc_ep.active = 0;
48884 + pcd_ep->dwc_ep.tx_fifo_num = 0;
48885 + /* Control until ep is actvated */
48886 + pcd_ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
48887 + pcd_ep->dwc_ep.maxpacket = MAX_PACKET_SIZE;
48888 + pcd_ep->dwc_ep.dma_addr = 0;
48889 + pcd_ep->dwc_ep.start_xfer_buff = 0;
48890 + pcd_ep->dwc_ep.xfer_buff = 0;
48891 + pcd_ep->dwc_ep.xfer_len = 0;
48892 + pcd_ep->dwc_ep.xfer_count = 0;
48893 + pcd_ep->dwc_ep.sent_zlp = 0;
48894 + pcd_ep->dwc_ep.total_len = 0;
48895 + pcd_ep->dwc_ep.desc_addr = 0;
48896 + pcd_ep->dwc_ep.dma_desc_addr = 0;
48897 + DWC_CIRCLEQ_INIT(&pcd_ep->queue);
48898 +}
48899 +
48900 +/**
48901 + * Initialize ep's
48902 + */
48903 +static void dwc_otg_pcd_reinit(dwc_otg_pcd_t * pcd)
48904 +{
48905 + int i;
48906 + uint32_t hwcfg1;
48907 + dwc_otg_pcd_ep_t *ep;
48908 + int in_ep_cntr, out_ep_cntr;
48909 + uint32_t num_in_eps = (GET_CORE_IF(pcd))->dev_if->num_in_eps;
48910 + uint32_t num_out_eps = (GET_CORE_IF(pcd))->dev_if->num_out_eps;
48911 +
48912 + /**
48913 + * Initialize the EP0 structure.
48914 + */
48915 + ep = &pcd->ep0;
48916 + dwc_otg_pcd_init_ep(pcd, ep, 0, 0);
48917 +
48918 + in_ep_cntr = 0;
48919 + hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 3;
48920 + for (i = 1; in_ep_cntr < num_in_eps; i++) {
48921 + if ((hwcfg1 & 0x1) == 0) {
48922 + dwc_otg_pcd_ep_t *ep = &pcd->in_ep[in_ep_cntr];
48923 + in_ep_cntr++;
48924 + /**
48925 + * @todo NGS: Add direction to EP, based on contents
48926 + * of HWCFG1. Need a copy of HWCFG1 in pcd structure?
48927 + * sprintf(";r
48928 + */
48929 + dwc_otg_pcd_init_ep(pcd, ep, 1 /* IN */ , i);
48930 +
48931 + DWC_CIRCLEQ_INIT(&ep->queue);
48932 + }
48933 + hwcfg1 >>= 2;
48934 + }
48935 +
48936 + out_ep_cntr = 0;
48937 + hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 2;
48938 + for (i = 1; out_ep_cntr < num_out_eps; i++) {
48939 + if ((hwcfg1 & 0x1) == 0) {
48940 + dwc_otg_pcd_ep_t *ep = &pcd->out_ep[out_ep_cntr];
48941 + out_ep_cntr++;
48942 + /**
48943 + * @todo NGS: Add direction to EP, based on contents
48944 + * of HWCFG1. Need a copy of HWCFG1 in pcd structure?
48945 + * sprintf(";r
48946 + */
48947 + dwc_otg_pcd_init_ep(pcd, ep, 0 /* OUT */ , i);
48948 + DWC_CIRCLEQ_INIT(&ep->queue);
48949 + }
48950 + hwcfg1 >>= 2;
48951 + }
48952 +
48953 + pcd->ep0state = EP0_DISCONNECT;
48954 + pcd->ep0.dwc_ep.maxpacket = MAX_EP0_SIZE;
48955 + pcd->ep0.dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
48956 +}
48957 +
48958 +/**
48959 + * This function is called when the SRP timer expires. The SRP should
48960 + * complete within 6 seconds.
48961 + */
48962 +static void srp_timeout(void *ptr)
48963 +{
48964 + gotgctl_data_t gotgctl;
48965 + dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
48966 + volatile uint32_t *addr = &core_if->core_global_regs->gotgctl;
48967 +
48968 + gotgctl.d32 = DWC_READ_REG32(addr);
48969 +
48970 + core_if->srp_timer_started = 0;
48971 +
48972 + if (core_if->adp_enable) {
48973 + if (gotgctl.b.bsesvld == 0) {
48974 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
48975 + DWC_PRINTF("SRP Timeout BSESSVLD = 0\n");
48976 + /* Power off the core */
48977 + if (core_if->power_down == 2) {
48978 + gpwrdn.b.pwrdnswtch = 1;
48979 + DWC_MODIFY_REG32(&core_if->
48980 + core_global_regs->gpwrdn,
48981 + gpwrdn.d32, 0);
48982 + }
48983 +
48984 + gpwrdn.d32 = 0;
48985 + gpwrdn.b.pmuintsel = 1;
48986 + gpwrdn.b.pmuactv = 1;
48987 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
48988 + gpwrdn.d32);
48989 + dwc_otg_adp_probe_start(core_if);
48990 + } else {
48991 + DWC_PRINTF("SRP Timeout BSESSVLD = 1\n");
48992 + core_if->op_state = B_PERIPHERAL;
48993 + dwc_otg_core_init(core_if);
48994 + dwc_otg_enable_global_interrupts(core_if);
48995 + cil_pcd_start(core_if);
48996 + }
48997 + }
48998 +
48999 + if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
49000 + (core_if->core_params->i2c_enable)) {
49001 + DWC_PRINTF("SRP Timeout\n");
49002 +
49003 + if ((core_if->srp_success) && (gotgctl.b.bsesvld)) {
49004 + if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
49005 + core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
49006 + }
49007 +
49008 + /* Clear Session Request */
49009 + gotgctl.d32 = 0;
49010 + gotgctl.b.sesreq = 1;
49011 + DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl,
49012 + gotgctl.d32, 0);
49013 +
49014 + core_if->srp_success = 0;
49015 + } else {
49016 + __DWC_ERROR("Device not connected/responding\n");
49017 + gotgctl.b.sesreq = 0;
49018 + DWC_WRITE_REG32(addr, gotgctl.d32);
49019 + }
49020 + } else if (gotgctl.b.sesreq) {
49021 + DWC_PRINTF("SRP Timeout\n");
49022 +
49023 + __DWC_ERROR("Device not connected/responding\n");
49024 + gotgctl.b.sesreq = 0;
49025 + DWC_WRITE_REG32(addr, gotgctl.d32);
49026 + } else {
49027 + DWC_PRINTF(" SRP GOTGCTL=%0x\n", gotgctl.d32);
49028 + }
49029 +}
49030 +
49031 +/**
49032 + * Tasklet
49033 + *
49034 + */
49035 +extern void start_next_request(dwc_otg_pcd_ep_t * ep);
49036 +
49037 +static void start_xfer_tasklet_func(void *data)
49038 +{
49039 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
49040 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
49041 +
49042 + int i;
49043 + depctl_data_t diepctl;
49044 +
49045 + DWC_DEBUGPL(DBG_PCDV, "Start xfer tasklet\n");
49046 +
49047 + diepctl.d32 = DWC_READ_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl);
49048 +
49049 + if (pcd->ep0.queue_sof) {
49050 + pcd->ep0.queue_sof = 0;
49051 + start_next_request(&pcd->ep0);
49052 + // break;
49053 + }
49054 +
49055 + for (i = 0; i < core_if->dev_if->num_in_eps; i++) {
49056 + depctl_data_t diepctl;
49057 + diepctl.d32 =
49058 + DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl);
49059 +
49060 + if (pcd->in_ep[i].queue_sof) {
49061 + pcd->in_ep[i].queue_sof = 0;
49062 + start_next_request(&pcd->in_ep[i]);
49063 + // break;
49064 + }
49065 + }
49066 +
49067 + return;
49068 +}
49069 +
49070 +/**
49071 + * This function initialized the PCD portion of the driver.
49072 + *
49073 + */
49074 +dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if)
49075 +{
49076 + dwc_otg_pcd_t *pcd = NULL;
49077 + dwc_otg_dev_if_t *dev_if;
49078 + int i;
49079 +
49080 + /*
49081 + * Allocate PCD structure
49082 + */
49083 + pcd = DWC_ALLOC(sizeof(dwc_otg_pcd_t));
49084 +
49085 + if (pcd == NULL) {
49086 + return NULL;
49087 + }
49088 +
49089 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))
49090 + DWC_SPINLOCK_ALLOC_LINUX_DEBUG(pcd->lock);
49091 +#else
49092 + pcd->lock = DWC_SPINLOCK_ALLOC();
49093 +#endif
49094 + DWC_DEBUGPL(DBG_HCDV, "Init of PCD %p given core_if %p\n",
49095 + pcd, core_if);//GRAYG
49096 + if (!pcd->lock) {
49097 + DWC_ERROR("Could not allocate lock for pcd");
49098 + DWC_FREE(pcd);
49099 + return NULL;
49100 + }
49101 + /* Set core_if's lock pointer to hcd->lock */
49102 + core_if->lock = pcd->lock;
49103 + pcd->core_if = core_if;
49104 +
49105 + dev_if = core_if->dev_if;
49106 + dev_if->isoc_ep = NULL;
49107 +
49108 + if (core_if->hwcfg4.b.ded_fifo_en) {
49109 + DWC_PRINTF("Dedicated Tx FIFOs mode\n");
49110 + } else {
49111 + DWC_PRINTF("Shared Tx FIFO mode\n");
49112 + }
49113 +
49114 + /*
49115 + * Initialized the Core for Device mode here if there is nod ADP support.
49116 + * Otherwise it will be done later in dwc_otg_adp_start routine.
49117 + */
49118 + if (dwc_otg_is_device_mode(core_if) /*&& !core_if->adp_enable*/) {
49119 + dwc_otg_core_dev_init(core_if);
49120 + }
49121 +
49122 + /*
49123 + * Register the PCD Callbacks.
49124 + */
49125 + dwc_otg_cil_register_pcd_callbacks(core_if, &pcd_callbacks, pcd);
49126 +
49127 + /*
49128 + * Initialize the DMA buffer for SETUP packets
49129 + */
49130 + if (GET_CORE_IF(pcd)->dma_enable) {
49131 + pcd->setup_pkt =
49132 + DWC_DMA_ALLOC(sizeof(*pcd->setup_pkt) * 5,
49133 + &pcd->setup_pkt_dma_handle);
49134 + if (pcd->setup_pkt == NULL) {
49135 + DWC_FREE(pcd);
49136 + return NULL;
49137 + }
49138 +
49139 + pcd->status_buf =
49140 + DWC_DMA_ALLOC(sizeof(uint16_t),
49141 + &pcd->status_buf_dma_handle);
49142 + if (pcd->status_buf == NULL) {
49143 + DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5,
49144 + pcd->setup_pkt, pcd->setup_pkt_dma_handle);
49145 + DWC_FREE(pcd);
49146 + return NULL;
49147 + }
49148 +
49149 + if (GET_CORE_IF(pcd)->dma_desc_enable) {
49150 + dev_if->setup_desc_addr[0] =
49151 + dwc_otg_ep_alloc_desc_chain
49152 + (&dev_if->dma_setup_desc_addr[0], 1);
49153 + dev_if->setup_desc_addr[1] =
49154 + dwc_otg_ep_alloc_desc_chain
49155 + (&dev_if->dma_setup_desc_addr[1], 1);
49156 + dev_if->in_desc_addr =
49157 + dwc_otg_ep_alloc_desc_chain
49158 + (&dev_if->dma_in_desc_addr, 1);
49159 + dev_if->out_desc_addr =
49160 + dwc_otg_ep_alloc_desc_chain
49161 + (&dev_if->dma_out_desc_addr, 1);
49162 + pcd->data_terminated = 0;
49163 +
49164 + if (dev_if->setup_desc_addr[0] == 0
49165 + || dev_if->setup_desc_addr[1] == 0
49166 + || dev_if->in_desc_addr == 0
49167 + || dev_if->out_desc_addr == 0) {
49168 +
49169 + if (dev_if->out_desc_addr)
49170 + dwc_otg_ep_free_desc_chain
49171 + (dev_if->out_desc_addr,
49172 + dev_if->dma_out_desc_addr, 1);
49173 + if (dev_if->in_desc_addr)
49174 + dwc_otg_ep_free_desc_chain
49175 + (dev_if->in_desc_addr,
49176 + dev_if->dma_in_desc_addr, 1);
49177 + if (dev_if->setup_desc_addr[1])
49178 + dwc_otg_ep_free_desc_chain
49179 + (dev_if->setup_desc_addr[1],
49180 + dev_if->dma_setup_desc_addr[1], 1);
49181 + if (dev_if->setup_desc_addr[0])
49182 + dwc_otg_ep_free_desc_chain
49183 + (dev_if->setup_desc_addr[0],
49184 + dev_if->dma_setup_desc_addr[0], 1);
49185 +
49186 + DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5,
49187 + pcd->setup_pkt,
49188 + pcd->setup_pkt_dma_handle);
49189 + DWC_DMA_FREE(sizeof(*pcd->status_buf),
49190 + pcd->status_buf,
49191 + pcd->status_buf_dma_handle);
49192 +
49193 + DWC_FREE(pcd);
49194 +
49195 + return NULL;
49196 + }
49197 + }
49198 + } else {
49199 + pcd->setup_pkt = DWC_ALLOC(sizeof(*pcd->setup_pkt) * 5);
49200 + if (pcd->setup_pkt == NULL) {
49201 + DWC_FREE(pcd);
49202 + return NULL;
49203 + }
49204 +
49205 + pcd->status_buf = DWC_ALLOC(sizeof(uint16_t));
49206 + if (pcd->status_buf == NULL) {
49207 + DWC_FREE(pcd->setup_pkt);
49208 + DWC_FREE(pcd);
49209 + return NULL;
49210 + }
49211 + }
49212 +
49213 + dwc_otg_pcd_reinit(pcd);
49214 +
49215 + /* Allocate the cfi object for the PCD */
49216 +#ifdef DWC_UTE_CFI
49217 + pcd->cfi = DWC_ALLOC(sizeof(cfiobject_t));
49218 + if (NULL == pcd->cfi)
49219 + goto fail;
49220 + if (init_cfi(pcd->cfi)) {
49221 + CFI_INFO("%s: Failed to init the CFI object\n", __func__);
49222 + goto fail;
49223 + }
49224 +#endif
49225 +
49226 + /* Initialize tasklets */
49227 + pcd->start_xfer_tasklet = DWC_TASK_ALLOC("xfer_tasklet",
49228 + start_xfer_tasklet_func, pcd);
49229 + pcd->test_mode_tasklet = DWC_TASK_ALLOC("test_mode_tasklet",
49230 + do_test_mode, pcd);
49231 +
49232 + /* Initialize SRP timer */
49233 + core_if->srp_timer = DWC_TIMER_ALLOC("SRP TIMER", srp_timeout, core_if);
49234 +
49235 + if (core_if->core_params->dev_out_nak) {
49236 + /**
49237 + * Initialize xfer timeout timer. Implemented for
49238 + * 2.93a feature "Device DDMA OUT NAK Enhancement"
49239 + */
49240 + for(i = 0; i < MAX_EPS_CHANNELS; i++) {
49241 + pcd->core_if->ep_xfer_timer[i] =
49242 + DWC_TIMER_ALLOC("ep timer", ep_xfer_timeout,
49243 + &pcd->core_if->ep_xfer_info[i]);
49244 + }
49245 + }
49246 +
49247 + return pcd;
49248 +#ifdef DWC_UTE_CFI
49249 +fail:
49250 +#endif
49251 + if (pcd->setup_pkt)
49252 + DWC_FREE(pcd->setup_pkt);
49253 + if (pcd->status_buf)
49254 + DWC_FREE(pcd->status_buf);
49255 +#ifdef DWC_UTE_CFI
49256 + if (pcd->cfi)
49257 + DWC_FREE(pcd->cfi);
49258 +#endif
49259 + if (pcd)
49260 + DWC_FREE(pcd);
49261 + return NULL;
49262 +
49263 +}
49264 +
49265 +/**
49266 + * Remove PCD specific data
49267 + */
49268 +void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd)
49269 +{
49270 + dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
49271 + int i;
49272 + if (pcd->core_if->core_params->dev_out_nak) {
49273 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
49274 + DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[i]);
49275 + pcd->core_if->ep_xfer_info[i].state = 0;
49276 + }
49277 + }
49278 +
49279 + if (GET_CORE_IF(pcd)->dma_enable) {
49280 + DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5, pcd->setup_pkt,
49281 + pcd->setup_pkt_dma_handle);
49282 + DWC_DMA_FREE(sizeof(uint16_t), pcd->status_buf,
49283 + pcd->status_buf_dma_handle);
49284 + if (GET_CORE_IF(pcd)->dma_desc_enable) {
49285 + dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0],
49286 + dev_if->dma_setup_desc_addr
49287 + [0], 1);
49288 + dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1],
49289 + dev_if->dma_setup_desc_addr
49290 + [1], 1);
49291 + dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr,
49292 + dev_if->dma_in_desc_addr, 1);
49293 + dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr,
49294 + dev_if->dma_out_desc_addr,
49295 + 1);
49296 + }
49297 + } else {
49298 + DWC_FREE(pcd->setup_pkt);
49299 + DWC_FREE(pcd->status_buf);
49300 + }
49301 + DWC_SPINLOCK_FREE(pcd->lock);
49302 + /* Set core_if's lock pointer to NULL */
49303 + pcd->core_if->lock = NULL;
49304 +
49305 + DWC_TASK_FREE(pcd->start_xfer_tasklet);
49306 + DWC_TASK_FREE(pcd->test_mode_tasklet);
49307 + if (pcd->core_if->core_params->dev_out_nak) {
49308 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
49309 + if (pcd->core_if->ep_xfer_timer[i]) {
49310 + DWC_TIMER_FREE(pcd->core_if->ep_xfer_timer[i]);
49311 + }
49312 + }
49313 + }
49314 +
49315 +/* Release the CFI object's dynamic memory */
49316 +#ifdef DWC_UTE_CFI
49317 + if (pcd->cfi->ops.release) {
49318 + pcd->cfi->ops.release(pcd->cfi);
49319 + }
49320 +#endif
49321 +
49322 + DWC_FREE(pcd);
49323 +}
49324 +
49325 +/**
49326 + * Returns whether registered pcd is dual speed or not
49327 + */
49328 +uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd)
49329 +{
49330 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
49331 +
49332 + if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) ||
49333 + ((core_if->hwcfg2.b.hs_phy_type == 2) &&
49334 + (core_if->hwcfg2.b.fs_phy_type == 1) &&
49335 + (core_if->core_params->ulpi_fs_ls))) {
49336 + return 0;
49337 + }
49338 +
49339 + return 1;
49340 +}
49341 +
49342 +/**
49343 + * Returns whether registered pcd is OTG capable or not
49344 + */
49345 +uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd)
49346 +{
49347 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
49348 + gusbcfg_data_t usbcfg = {.d32 = 0 };
49349 +
49350 + usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
49351 + if (!usbcfg.b.srpcap || !usbcfg.b.hnpcap) {
49352 + return 0;
49353 + }
49354 +
49355 + return 1;
49356 +}
49357 +
49358 +/**
49359 + * This function assigns periodic Tx FIFO to an periodic EP
49360 + * in shared Tx FIFO mode
49361 + */
49362 +static uint32_t assign_tx_fifo(dwc_otg_core_if_t * core_if)
49363 +{
49364 + uint32_t TxMsk = 1;
49365 + int i;
49366 +
49367 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; ++i) {
49368 + if ((TxMsk & core_if->tx_msk) == 0) {
49369 + core_if->tx_msk |= TxMsk;
49370 + return i + 1;
49371 + }
49372 + TxMsk <<= 1;
49373 + }
49374 + return 0;
49375 +}
49376 +
49377 +/**
49378 + * This function assigns periodic Tx FIFO to an periodic EP
49379 + * in shared Tx FIFO mode
49380 + */
49381 +static uint32_t assign_perio_tx_fifo(dwc_otg_core_if_t * core_if)
49382 +{
49383 + uint32_t PerTxMsk = 1;
49384 + int i;
49385 + for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; ++i) {
49386 + if ((PerTxMsk & core_if->p_tx_msk) == 0) {
49387 + core_if->p_tx_msk |= PerTxMsk;
49388 + return i + 1;
49389 + }
49390 + PerTxMsk <<= 1;
49391 + }
49392 + return 0;
49393 +}
49394 +
49395 +/**
49396 + * This function releases periodic Tx FIFO
49397 + * in shared Tx FIFO mode
49398 + */
49399 +static void release_perio_tx_fifo(dwc_otg_core_if_t * core_if,
49400 + uint32_t fifo_num)
49401 +{
49402 + core_if->p_tx_msk =
49403 + (core_if->p_tx_msk & (1 << (fifo_num - 1))) ^ core_if->p_tx_msk;
49404 +}
49405 +
49406 +/**
49407 + * This function releases periodic Tx FIFO
49408 + * in shared Tx FIFO mode
49409 + */
49410 +static void release_tx_fifo(dwc_otg_core_if_t * core_if, uint32_t fifo_num)
49411 +{
49412 + core_if->tx_msk =
49413 + (core_if->tx_msk & (1 << (fifo_num - 1))) ^ core_if->tx_msk;
49414 +}
49415 +
49416 +/**
49417 + * This function is being called from gadget
49418 + * to enable PCD endpoint.
49419 + */
49420 +int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
49421 + const uint8_t * ep_desc, void *usb_ep)
49422 +{
49423 + int num, dir;
49424 + dwc_otg_pcd_ep_t *ep = NULL;
49425 + const usb_endpoint_descriptor_t *desc;
49426 + dwc_irqflags_t flags;
49427 + fifosize_data_t dptxfsiz = {.d32 = 0 };
49428 + gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
49429 + gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 };
49430 + int retval = 0;
49431 + int i, epcount;
49432 +
49433 + desc = (const usb_endpoint_descriptor_t *)ep_desc;
49434 +
49435 + if (!desc) {
49436 + pcd->ep0.priv = usb_ep;
49437 + ep = &pcd->ep0;
49438 + retval = -DWC_E_INVALID;
49439 + goto out;
49440 + }
49441 +
49442 + num = UE_GET_ADDR(desc->bEndpointAddress);
49443 + dir = UE_GET_DIR(desc->bEndpointAddress);
49444 +
49445 + if (!desc->wMaxPacketSize) {
49446 + DWC_WARN("bad maxpacketsize\n");
49447 + retval = -DWC_E_INVALID;
49448 + goto out;
49449 + }
49450 +
49451 + if (dir == UE_DIR_IN) {
49452 + epcount = pcd->core_if->dev_if->num_in_eps;
49453 + for (i = 0; i < epcount; i++) {
49454 + if (num == pcd->in_ep[i].dwc_ep.num) {
49455 + ep = &pcd->in_ep[i];
49456 + break;
49457 + }
49458 + }
49459 + } else {
49460 + epcount = pcd->core_if->dev_if->num_out_eps;
49461 + for (i = 0; i < epcount; i++) {
49462 + if (num == pcd->out_ep[i].dwc_ep.num) {
49463 + ep = &pcd->out_ep[i];
49464 + break;
49465 + }
49466 + }
49467 + }
49468 +
49469 + if (!ep) {
49470 + DWC_WARN("bad address\n");
49471 + retval = -DWC_E_INVALID;
49472 + goto out;
49473 + }
49474 +
49475 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
49476 +
49477 + ep->desc = desc;
49478 + ep->priv = usb_ep;
49479 +
49480 + /*
49481 + * Activate the EP
49482 + */
49483 + ep->stopped = 0;
49484 +
49485 + ep->dwc_ep.is_in = (dir == UE_DIR_IN);
49486 + ep->dwc_ep.maxpacket = UGETW(desc->wMaxPacketSize);
49487 +
49488 + ep->dwc_ep.type = desc->bmAttributes & UE_XFERTYPE;
49489 +
49490 + if (ep->dwc_ep.is_in) {
49491 + if (!GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
49492 + ep->dwc_ep.tx_fifo_num = 0;
49493 +
49494 + if (ep->dwc_ep.type == UE_ISOCHRONOUS) {
49495 + /*
49496 + * if ISOC EP then assign a Periodic Tx FIFO.
49497 + */
49498 + ep->dwc_ep.tx_fifo_num =
49499 + assign_perio_tx_fifo(GET_CORE_IF(pcd));
49500 + }
49501 + } else {
49502 + /*
49503 + * if Dedicated FIFOs mode is on then assign a Tx FIFO.
49504 + */
49505 + ep->dwc_ep.tx_fifo_num =
49506 + assign_tx_fifo(GET_CORE_IF(pcd));
49507 + }
49508 +
49509 + /* Calculating EP info controller base address */
49510 + if (ep->dwc_ep.tx_fifo_num
49511 + && GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
49512 + gdfifocfg.d32 =
49513 + DWC_READ_REG32(&GET_CORE_IF(pcd)->
49514 + core_global_regs->gdfifocfg);
49515 + gdfifocfgbase.d32 = gdfifocfg.d32 >> 16;
49516 + dptxfsiz.d32 =
49517 + (DWC_READ_REG32
49518 + (&GET_CORE_IF(pcd)->core_global_regs->
49519 + dtxfsiz[ep->dwc_ep.tx_fifo_num - 1]) >> 16);
49520 + gdfifocfg.b.epinfobase =
49521 + gdfifocfgbase.d32 + dptxfsiz.d32;
49522 + if (GET_CORE_IF(pcd)->snpsid <= OTG_CORE_REV_2_94a) {
49523 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->
49524 + core_global_regs->gdfifocfg,
49525 + gdfifocfg.d32);
49526 + }
49527 + }
49528 + }
49529 + /* Set initial data PID. */
49530 + if (ep->dwc_ep.type == UE_BULK) {
49531 + ep->dwc_ep.data_pid_start = 0;
49532 + }
49533 +
49534 + /* Alloc DMA Descriptors */
49535 + if (GET_CORE_IF(pcd)->dma_desc_enable) {
49536 +#ifndef DWC_UTE_PER_IO
49537 + if (ep->dwc_ep.type != UE_ISOCHRONOUS) {
49538 +#endif
49539 + ep->dwc_ep.desc_addr =
49540 + dwc_otg_ep_alloc_desc_chain(&ep->
49541 + dwc_ep.dma_desc_addr,
49542 + MAX_DMA_DESC_CNT);
49543 + if (!ep->dwc_ep.desc_addr) {
49544 + DWC_WARN("%s, can't allocate DMA descriptor\n",
49545 + __func__);
49546 + retval = -DWC_E_SHUTDOWN;
49547 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
49548 + goto out;
49549 + }
49550 +#ifndef DWC_UTE_PER_IO
49551 + }
49552 +#endif
49553 + }
49554 +
49555 + DWC_DEBUGPL(DBG_PCD, "Activate %s: type=%d, mps=%d desc=%p\n",
49556 + (ep->dwc_ep.is_in ? "IN" : "OUT"),
49557 + ep->dwc_ep.type, ep->dwc_ep.maxpacket, ep->desc);
49558 +#ifdef DWC_UTE_PER_IO
49559 + ep->dwc_ep.xiso_bInterval = 1 << (ep->desc->bInterval - 1);
49560 +#endif
49561 + if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
49562 + ep->dwc_ep.bInterval = 1 << (ep->desc->bInterval - 1);
49563 + ep->dwc_ep.frame_num = 0xFFFFFFFF;
49564 + }
49565 +
49566 + dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
49567 +
49568 +#ifdef DWC_UTE_CFI
49569 + if (pcd->cfi->ops.ep_enable) {
49570 + pcd->cfi->ops.ep_enable(pcd->cfi, pcd, ep);
49571 + }
49572 +#endif
49573 +
49574 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
49575 +
49576 +out:
49577 + return retval;
49578 +}
49579 +
49580 +/**
49581 + * This function is being called from gadget
49582 + * to disable PCD endpoint.
49583 + */
49584 +int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle)
49585 +{
49586 + dwc_otg_pcd_ep_t *ep;
49587 + dwc_irqflags_t flags;
49588 + dwc_otg_dev_dma_desc_t *desc_addr;
49589 + dwc_dma_t dma_desc_addr;
49590 + gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 };
49591 + gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
49592 + fifosize_data_t dptxfsiz = {.d32 = 0 };
49593 +
49594 + ep = get_ep_from_handle(pcd, ep_handle);
49595 +
49596 + if (!ep || !ep->desc) {
49597 + DWC_DEBUGPL(DBG_PCD, "bad ep address\n");
49598 + return -DWC_E_INVALID;
49599 + }
49600 +
49601 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
49602 +
49603 + dwc_otg_request_nuke(ep);
49604 +
49605 + dwc_otg_ep_deactivate(GET_CORE_IF(pcd), &ep->dwc_ep);
49606 + if (pcd->core_if->core_params->dev_out_nak) {
49607 + DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[ep->dwc_ep.num]);
49608 + pcd->core_if->ep_xfer_info[ep->dwc_ep.num].state = 0;
49609 + }
49610 + ep->desc = NULL;
49611 + ep->stopped = 1;
49612 +
49613 + gdfifocfg.d32 =
49614 + DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg);
49615 + gdfifocfgbase.d32 = gdfifocfg.d32 >> 16;
49616 +
49617 + if (ep->dwc_ep.is_in) {
49618 + if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
49619 + /* Flush the Tx FIFO */
49620 + dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd),
49621 + ep->dwc_ep.tx_fifo_num);
49622 + }
49623 + release_perio_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
49624 + release_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
49625 + if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
49626 + /* Decreasing EPinfo Base Addr */
49627 + dptxfsiz.d32 =
49628 + (DWC_READ_REG32
49629 + (&GET_CORE_IF(pcd)->
49630 + core_global_regs->dtxfsiz[ep->dwc_ep.tx_fifo_num-1]) >> 16);
49631 + gdfifocfg.b.epinfobase = gdfifocfgbase.d32 - dptxfsiz.d32;
49632 + if (GET_CORE_IF(pcd)->snpsid <= OTG_CORE_REV_2_94a) {
49633 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg,
49634 + gdfifocfg.d32);
49635 + }
49636 + }
49637 + }
49638 +
49639 + /* Free DMA Descriptors */
49640 + if (GET_CORE_IF(pcd)->dma_desc_enable) {
49641 + if (ep->dwc_ep.type != UE_ISOCHRONOUS) {
49642 + desc_addr = ep->dwc_ep.desc_addr;
49643 + dma_desc_addr = ep->dwc_ep.dma_desc_addr;
49644 +
49645 + /* Cannot call dma_free_coherent() with IRQs disabled */
49646 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
49647 + dwc_otg_ep_free_desc_chain(desc_addr, dma_desc_addr,
49648 + MAX_DMA_DESC_CNT);
49649 +
49650 + goto out_unlocked;
49651 + }
49652 + }
49653 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
49654 +
49655 +out_unlocked:
49656 + DWC_DEBUGPL(DBG_PCD, "%d %s disabled\n", ep->dwc_ep.num,
49657 + ep->dwc_ep.is_in ? "IN" : "OUT");
49658 + return 0;
49659 +
49660 +}
49661 +
49662 +/******************************************************************************/
49663 +#ifdef DWC_UTE_PER_IO
49664 +
49665 +/**
49666 + * Free the request and its extended parts
49667 + *
49668 + */
49669 +void dwc_pcd_xiso_ereq_free(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req)
49670 +{
49671 + DWC_FREE(req->ext_req.per_io_frame_descs);
49672 + DWC_FREE(req);
49673 +}
49674 +
49675 +/**
49676 + * Start the next request in the endpoint's queue.
49677 + *
49678 + */
49679 +int dwc_otg_pcd_xiso_start_next_request(dwc_otg_pcd_t * pcd,
49680 + dwc_otg_pcd_ep_t * ep)
49681 +{
49682 + int i;
49683 + dwc_otg_pcd_request_t *req = NULL;
49684 + dwc_ep_t *dwcep = NULL;
49685 + struct dwc_iso_xreq_port *ereq = NULL;
49686 + struct dwc_iso_pkt_desc_port *ddesc_iso;
49687 + uint16_t nat;
49688 + depctl_data_t diepctl;
49689 +
49690 + dwcep = &ep->dwc_ep;
49691 +
49692 + if (dwcep->xiso_active_xfers > 0) {
49693 +#if 0 //Disable this to decrease s/w overhead that is crucial for Isoc transfers
49694 + DWC_WARN("There are currently active transfers for EP%d \
49695 + (active=%d; queued=%d)", dwcep->num, dwcep->xiso_active_xfers,
49696 + dwcep->xiso_queued_xfers);
49697 +#endif
49698 + return 0;
49699 + }
49700 +
49701 + nat = UGETW(ep->desc->wMaxPacketSize);
49702 + nat = (nat >> 11) & 0x03;
49703 +
49704 + if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
49705 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
49706 + ereq = &req->ext_req;
49707 + ep->stopped = 0;
49708 +
49709 + /* Get the frame number */
49710 + dwcep->xiso_frame_num =
49711 + dwc_otg_get_frame_number(GET_CORE_IF(pcd));
49712 + DWC_DEBUG("FRM_NUM=%d", dwcep->xiso_frame_num);
49713 +
49714 + ddesc_iso = ereq->per_io_frame_descs;
49715 +
49716 + if (dwcep->is_in) {
49717 + /* Setup DMA Descriptor chain for IN Isoc request */
49718 + for (i = 0; i < ereq->pio_pkt_count; i++) {
49719 + //if ((i % (nat + 1)) == 0)
49720 + if ( i > 0 )
49721 + dwcep->xiso_frame_num =
49722 + (dwcep->xiso_bInterval +
49723 + dwcep->xiso_frame_num) & 0x3FFF;
49724 + dwcep->desc_addr[i].buf =
49725 + req->dma + ddesc_iso[i].offset;
49726 + dwcep->desc_addr[i].status.b_iso_in.txbytes =
49727 + ddesc_iso[i].length;
49728 + dwcep->desc_addr[i].status.b_iso_in.framenum =
49729 + dwcep->xiso_frame_num;
49730 + dwcep->desc_addr[i].status.b_iso_in.bs =
49731 + BS_HOST_READY;
49732 + dwcep->desc_addr[i].status.b_iso_in.txsts = 0;
49733 + dwcep->desc_addr[i].status.b_iso_in.sp =
49734 + (ddesc_iso[i].length %
49735 + dwcep->maxpacket) ? 1 : 0;
49736 + dwcep->desc_addr[i].status.b_iso_in.ioc = 0;
49737 + dwcep->desc_addr[i].status.b_iso_in.pid = nat + 1;
49738 + dwcep->desc_addr[i].status.b_iso_in.l = 0;
49739 +
49740 + /* Process the last descriptor */
49741 + if (i == ereq->pio_pkt_count - 1) {
49742 + dwcep->desc_addr[i].status.b_iso_in.ioc = 1;
49743 + dwcep->desc_addr[i].status.b_iso_in.l = 1;
49744 + }
49745 + }
49746 +
49747 + /* Setup and start the transfer for this endpoint */
49748 + dwcep->xiso_active_xfers++;
49749 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->dev_if->
49750 + in_ep_regs[dwcep->num]->diepdma,
49751 + dwcep->dma_desc_addr);
49752 + diepctl.d32 = 0;
49753 + diepctl.b.epena = 1;
49754 + diepctl.b.cnak = 1;
49755 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if->
49756 + in_ep_regs[dwcep->num]->diepctl, 0,
49757 + diepctl.d32);
49758 + } else {
49759 + /* Setup DMA Descriptor chain for OUT Isoc request */
49760 + for (i = 0; i < ereq->pio_pkt_count; i++) {
49761 + //if ((i % (nat + 1)) == 0)
49762 + dwcep->xiso_frame_num = (dwcep->xiso_bInterval +
49763 + dwcep->xiso_frame_num) & 0x3FFF;
49764 + dwcep->desc_addr[i].buf =
49765 + req->dma + ddesc_iso[i].offset;
49766 + dwcep->desc_addr[i].status.b_iso_out.rxbytes =
49767 + ddesc_iso[i].length;
49768 + dwcep->desc_addr[i].status.b_iso_out.framenum =
49769 + dwcep->xiso_frame_num;
49770 + dwcep->desc_addr[i].status.b_iso_out.bs =
49771 + BS_HOST_READY;
49772 + dwcep->desc_addr[i].status.b_iso_out.rxsts = 0;
49773 + dwcep->desc_addr[i].status.b_iso_out.sp =
49774 + (ddesc_iso[i].length %
49775 + dwcep->maxpacket) ? 1 : 0;
49776 + dwcep->desc_addr[i].status.b_iso_out.ioc = 0;
49777 + dwcep->desc_addr[i].status.b_iso_out.pid = nat + 1;
49778 + dwcep->desc_addr[i].status.b_iso_out.l = 0;
49779 +
49780 + /* Process the last descriptor */
49781 + if (i == ereq->pio_pkt_count - 1) {
49782 + dwcep->desc_addr[i].status.b_iso_out.ioc = 1;
49783 + dwcep->desc_addr[i].status.b_iso_out.l = 1;
49784 + }
49785 + }
49786 +
49787 + /* Setup and start the transfer for this endpoint */
49788 + dwcep->xiso_active_xfers++;
49789 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->
49790 + dev_if->out_ep_regs[dwcep->num]->
49791 + doepdma, dwcep->dma_desc_addr);
49792 + diepctl.d32 = 0;
49793 + diepctl.b.epena = 1;
49794 + diepctl.b.cnak = 1;
49795 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->
49796 + dev_if->out_ep_regs[dwcep->num]->
49797 + doepctl, 0, diepctl.d32);
49798 + }
49799 +
49800 + } else {
49801 + ep->stopped = 1;
49802 + }
49803 +
49804 + return 0;
49805 +}
49806 +
49807 +/**
49808 + * - Remove the request from the queue
49809 + */
49810 +void complete_xiso_ep(dwc_otg_pcd_ep_t * ep)
49811 +{
49812 + dwc_otg_pcd_request_t *req = NULL;
49813 + struct dwc_iso_xreq_port *ereq = NULL;
49814 + struct dwc_iso_pkt_desc_port *ddesc_iso = NULL;
49815 + dwc_ep_t *dwcep = NULL;
49816 + int i;
49817 +
49818 + //DWC_DEBUG();
49819 + dwcep = &ep->dwc_ep;
49820 +
49821 + /* Get the first pending request from the queue */
49822 + if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
49823 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
49824 + if (!req) {
49825 + DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
49826 + return;
49827 + }
49828 + dwcep->xiso_active_xfers--;
49829 + dwcep->xiso_queued_xfers--;
49830 + /* Remove this request from the queue */
49831 + DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry);
49832 + } else {
49833 + DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
49834 + return;
49835 + }
49836 +
49837 + ep->stopped = 1;
49838 + ereq = &req->ext_req;
49839 + ddesc_iso = ereq->per_io_frame_descs;
49840 +
49841 + if (dwcep->xiso_active_xfers < 0) {
49842 + DWC_WARN("EP#%d (xiso_active_xfers=%d)", dwcep->num,
49843 + dwcep->xiso_active_xfers);
49844 + }
49845 +
49846 + /* Fill the Isoc descs of portable extended req from dma descriptors */
49847 + for (i = 0; i < ereq->pio_pkt_count; i++) {
49848 + if (dwcep->is_in) { /* IN endpoints */
49849 + ddesc_iso[i].actual_length = ddesc_iso[i].length -
49850 + dwcep->desc_addr[i].status.b_iso_in.txbytes;
49851 + ddesc_iso[i].status =
49852 + dwcep->desc_addr[i].status.b_iso_in.txsts;
49853 + } else { /* OUT endpoints */
49854 + ddesc_iso[i].actual_length = ddesc_iso[i].length -
49855 + dwcep->desc_addr[i].status.b_iso_out.rxbytes;
49856 + ddesc_iso[i].status =
49857 + dwcep->desc_addr[i].status.b_iso_out.rxsts;
49858 + }
49859 + }
49860 +
49861 + DWC_SPINUNLOCK(ep->pcd->lock);
49862 +
49863 + /* Call the completion function in the non-portable logic */
49864 + ep->pcd->fops->xisoc_complete(ep->pcd, ep->priv, req->priv, 0,
49865 + &req->ext_req);
49866 +
49867 + DWC_SPINLOCK(ep->pcd->lock);
49868 +
49869 + /* Free the request - specific freeing needed for extended request object */
49870 + dwc_pcd_xiso_ereq_free(ep, req);
49871 +
49872 + /* Start the next request */
49873 + dwc_otg_pcd_xiso_start_next_request(ep->pcd, ep);
49874 +
49875 + return;
49876 +}
49877 +
49878 +/**
49879 + * Create and initialize the Isoc pkt descriptors of the extended request.
49880 + *
49881 + */
49882 +static int dwc_otg_pcd_xiso_create_pkt_descs(dwc_otg_pcd_request_t * req,
49883 + void *ereq_nonport,
49884 + int atomic_alloc)
49885 +{
49886 + struct dwc_iso_xreq_port *ereq = NULL;
49887 + struct dwc_iso_xreq_port *req_mapped = NULL;
49888 + struct dwc_iso_pkt_desc_port *ipds = NULL; /* To be created in this function */
49889 + uint32_t pkt_count;
49890 + int i;
49891 +
49892 + ereq = &req->ext_req;
49893 + req_mapped = (struct dwc_iso_xreq_port *)ereq_nonport;
49894 + pkt_count = req_mapped->pio_pkt_count;
49895 +
49896 + /* Create the isoc descs */
49897 + if (atomic_alloc) {
49898 + ipds = DWC_ALLOC_ATOMIC(sizeof(*ipds) * pkt_count);
49899 + } else {
49900 + ipds = DWC_ALLOC(sizeof(*ipds) * pkt_count);
49901 + }
49902 +
49903 + if (!ipds) {
49904 + DWC_ERROR("Failed to allocate isoc descriptors");
49905 + return -DWC_E_NO_MEMORY;
49906 + }
49907 +
49908 + /* Initialize the extended request fields */
49909 + ereq->per_io_frame_descs = ipds;
49910 + ereq->error_count = 0;
49911 + ereq->pio_alloc_pkt_count = pkt_count;
49912 + ereq->pio_pkt_count = pkt_count;
49913 + ereq->tr_sub_flags = req_mapped->tr_sub_flags;
49914 +
49915 + /* Init the Isoc descriptors */
49916 + for (i = 0; i < pkt_count; i++) {
49917 + ipds[i].length = req_mapped->per_io_frame_descs[i].length;
49918 + ipds[i].offset = req_mapped->per_io_frame_descs[i].offset;
49919 + ipds[i].status = req_mapped->per_io_frame_descs[i].status; /* 0 */
49920 + ipds[i].actual_length =
49921 + req_mapped->per_io_frame_descs[i].actual_length;
49922 + }
49923 +
49924 + return 0;
49925 +}
49926 +
49927 +static void prn_ext_request(struct dwc_iso_xreq_port *ereq)
49928 +{
49929 + struct dwc_iso_pkt_desc_port *xfd = NULL;
49930 + int i;
49931 +
49932 + DWC_DEBUG("per_io_frame_descs=%p", ereq->per_io_frame_descs);
49933 + DWC_DEBUG("tr_sub_flags=%d", ereq->tr_sub_flags);
49934 + DWC_DEBUG("error_count=%d", ereq->error_count);
49935 + DWC_DEBUG("pio_alloc_pkt_count=%d", ereq->pio_alloc_pkt_count);
49936 + DWC_DEBUG("pio_pkt_count=%d", ereq->pio_pkt_count);
49937 + DWC_DEBUG("res=%d", ereq->res);
49938 +
49939 + for (i = 0; i < ereq->pio_pkt_count; i++) {
49940 + xfd = &ereq->per_io_frame_descs[0];
49941 + DWC_DEBUG("FD #%d", i);
49942 +
49943 + DWC_DEBUG("xfd->actual_length=%d", xfd->actual_length);
49944 + DWC_DEBUG("xfd->length=%d", xfd->length);
49945 + DWC_DEBUG("xfd->offset=%d", xfd->offset);
49946 + DWC_DEBUG("xfd->status=%d", xfd->status);
49947 + }
49948 +}
49949 +
49950 +/**
49951 + *
49952 + */
49953 +int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
49954 + uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen,
49955 + int zero, void *req_handle, int atomic_alloc,
49956 + void *ereq_nonport)
49957 +{
49958 + dwc_otg_pcd_request_t *req = NULL;
49959 + dwc_otg_pcd_ep_t *ep;
49960 + dwc_irqflags_t flags;
49961 + int res;
49962 +
49963 + ep = get_ep_from_handle(pcd, ep_handle);
49964 + if (!ep) {
49965 + DWC_WARN("bad ep\n");
49966 + return -DWC_E_INVALID;
49967 + }
49968 +
49969 + /* We support this extension only for DDMA mode */
49970 + if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
49971 + if (!GET_CORE_IF(pcd)->dma_desc_enable)
49972 + return -DWC_E_INVALID;
49973 +
49974 + /* Create a dwc_otg_pcd_request_t object */
49975 + if (atomic_alloc) {
49976 + req = DWC_ALLOC_ATOMIC(sizeof(*req));
49977 + } else {
49978 + req = DWC_ALLOC(sizeof(*req));
49979 + }
49980 +
49981 + if (!req) {
49982 + return -DWC_E_NO_MEMORY;
49983 + }
49984 +
49985 + /* Create the Isoc descs for this request which shall be the exact match
49986 + * of the structure sent to us from the non-portable logic */
49987 + res =
49988 + dwc_otg_pcd_xiso_create_pkt_descs(req, ereq_nonport, atomic_alloc);
49989 + if (res) {
49990 + DWC_WARN("Failed to init the Isoc descriptors");
49991 + DWC_FREE(req);
49992 + return res;
49993 + }
49994 +
49995 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
49996 +
49997 + DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry);
49998 + req->buf = buf;
49999 + req->dma = dma_buf;
50000 + req->length = buflen;
50001 + req->sent_zlp = zero;
50002 + req->priv = req_handle;
50003 +
50004 + //DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
50005 + ep->dwc_ep.dma_addr = dma_buf;
50006 + ep->dwc_ep.start_xfer_buff = buf;
50007 + ep->dwc_ep.xfer_buff = buf;
50008 + ep->dwc_ep.xfer_len = 0;
50009 + ep->dwc_ep.xfer_count = 0;
50010 + ep->dwc_ep.sent_zlp = 0;
50011 + ep->dwc_ep.total_len = buflen;
50012 +
50013 + /* Add this request to the tail */
50014 + DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
50015 + ep->dwc_ep.xiso_queued_xfers++;
50016 +
50017 +//DWC_DEBUG("CP_0");
50018 +//DWC_DEBUG("req->ext_req.tr_sub_flags=%d", req->ext_req.tr_sub_flags);
50019 +//prn_ext_request((struct dwc_iso_xreq_port *) ereq_nonport);
50020 +//prn_ext_request(&req->ext_req);
50021 +
50022 + //DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50023 +
50024 + /* If the req->status == ASAP then check if there is any active transfer
50025 + * for this endpoint. If no active transfers, then get the first entry
50026 + * from the queue and start that transfer
50027 + */
50028 + if (req->ext_req.tr_sub_flags == DWC_EREQ_TF_ASAP) {
50029 + res = dwc_otg_pcd_xiso_start_next_request(pcd, ep);
50030 + if (res) {
50031 + DWC_WARN("Failed to start the next Isoc transfer");
50032 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50033 + DWC_FREE(req);
50034 + return res;
50035 + }
50036 + }
50037 +
50038 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50039 + return 0;
50040 +}
50041 +
50042 +#endif
50043 +/* END ifdef DWC_UTE_PER_IO ***************************************************/
50044 +int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
50045 + uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen,
50046 + int zero, void *req_handle, int atomic_alloc)
50047 +{
50048 + dwc_irqflags_t flags;
50049 + dwc_otg_pcd_request_t *req;
50050 + dwc_otg_pcd_ep_t *ep;
50051 + uint32_t max_transfer;
50052 +
50053 + ep = get_ep_from_handle(pcd, ep_handle);
50054 + if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) {
50055 + DWC_WARN("bad ep\n");
50056 + return -DWC_E_INVALID;
50057 + }
50058 +
50059 + if (atomic_alloc) {
50060 + req = DWC_ALLOC_ATOMIC(sizeof(*req));
50061 + } else {
50062 + req = DWC_ALLOC(sizeof(*req));
50063 + }
50064 +
50065 + if (!req) {
50066 + return -DWC_E_NO_MEMORY;
50067 + }
50068 + DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry);
50069 + if (!GET_CORE_IF(pcd)->core_params->opt) {
50070 + if (ep->dwc_ep.num != 0) {
50071 + DWC_ERROR("queue req %p, len %d buf %p\n",
50072 + req_handle, buflen, buf);
50073 + }
50074 + }
50075 +
50076 + req->buf = buf;
50077 + req->dma = dma_buf;
50078 + req->length = buflen;
50079 + req->sent_zlp = zero;
50080 + req->priv = req_handle;
50081 + req->dw_align_buf = NULL;
50082 + if ((dma_buf & 0x3) && GET_CORE_IF(pcd)->dma_enable
50083 + && !GET_CORE_IF(pcd)->dma_desc_enable)
50084 + req->dw_align_buf = DWC_DMA_ALLOC(buflen,
50085 + &req->dw_align_buf_dma);
50086 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
50087 +
50088 + /*
50089 + * After adding request to the queue for IN ISOC wait for In Token Received
50090 + * when TX FIFO is empty interrupt and for OUT ISOC wait for OUT Token
50091 + * Received when EP is disabled interrupt to obtain starting microframe
50092 + * (odd/even) start transfer
50093 + */
50094 + if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
50095 + if (req != 0) {
50096 + depctl_data_t depctl = {.d32 =
50097 + DWC_READ_REG32(&pcd->core_if->dev_if->
50098 + in_ep_regs[ep->dwc_ep.num]->
50099 + diepctl) };
50100 + ++pcd->request_pending;
50101 +
50102 + DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
50103 + if (ep->dwc_ep.is_in) {
50104 + depctl.b.cnak = 1;
50105 + DWC_WRITE_REG32(&pcd->core_if->dev_if->
50106 + in_ep_regs[ep->dwc_ep.num]->
50107 + diepctl, depctl.d32);
50108 + }
50109 +
50110 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50111 + }
50112 + return 0;
50113 + }
50114 +
50115 + /*
50116 + * For EP0 IN without premature status, zlp is required?
50117 + */
50118 + if (ep->dwc_ep.num == 0 && ep->dwc_ep.is_in) {
50119 + DWC_DEBUGPL(DBG_PCDV, "%d-OUT ZLP\n", ep->dwc_ep.num);
50120 + //_req->zero = 1;
50121 + }
50122 +
50123 + /* Start the transfer */
50124 + if (DWC_CIRCLEQ_EMPTY(&ep->queue) && !ep->stopped) {
50125 + /* EP0 Transfer? */
50126 + if (ep->dwc_ep.num == 0) {
50127 + switch (pcd->ep0state) {
50128 + case EP0_IN_DATA_PHASE:
50129 + DWC_DEBUGPL(DBG_PCD,
50130 + "%s ep0: EP0_IN_DATA_PHASE\n",
50131 + __func__);
50132 + break;
50133 +
50134 + case EP0_OUT_DATA_PHASE:
50135 + DWC_DEBUGPL(DBG_PCD,
50136 + "%s ep0: EP0_OUT_DATA_PHASE\n",
50137 + __func__);
50138 + if (pcd->request_config) {
50139 + /* Complete STATUS PHASE */
50140 + ep->dwc_ep.is_in = 1;
50141 + pcd->ep0state = EP0_IN_STATUS_PHASE;
50142 + }
50143 + break;
50144 +
50145 + case EP0_IN_STATUS_PHASE:
50146 + DWC_DEBUGPL(DBG_PCD,
50147 + "%s ep0: EP0_IN_STATUS_PHASE\n",
50148 + __func__);
50149 + break;
50150 +
50151 + default:
50152 + DWC_DEBUGPL(DBG_ANY, "ep0: odd state %d\n",
50153 + pcd->ep0state);
50154 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50155 + return -DWC_E_SHUTDOWN;
50156 + }
50157 +
50158 + ep->dwc_ep.dma_addr = dma_buf;
50159 + ep->dwc_ep.start_xfer_buff = buf;
50160 + ep->dwc_ep.xfer_buff = buf;
50161 + ep->dwc_ep.xfer_len = buflen;
50162 + ep->dwc_ep.xfer_count = 0;
50163 + ep->dwc_ep.sent_zlp = 0;
50164 + ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
50165 +
50166 + if (zero) {
50167 + if ((ep->dwc_ep.xfer_len %
50168 + ep->dwc_ep.maxpacket == 0)
50169 + && (ep->dwc_ep.xfer_len != 0)) {
50170 + ep->dwc_ep.sent_zlp = 1;
50171 + }
50172 +
50173 + }
50174 +
50175 + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd),
50176 + &ep->dwc_ep);
50177 + } // non-ep0 endpoints
50178 + else {
50179 +#ifdef DWC_UTE_CFI
50180 + if (ep->dwc_ep.buff_mode != BM_STANDARD) {
50181 + /* store the request length */
50182 + ep->dwc_ep.cfi_req_len = buflen;
50183 + pcd->cfi->ops.build_descriptors(pcd->cfi, pcd,
50184 + ep, req);
50185 + } else {
50186 +#endif
50187 + max_transfer =
50188 + GET_CORE_IF(ep->pcd)->core_params->
50189 + max_transfer_size;
50190 +
50191 + /* Setup and start the Transfer */
50192 + if (req->dw_align_buf){
50193 + if (ep->dwc_ep.is_in)
50194 + dwc_memcpy(req->dw_align_buf,
50195 + buf, buflen);
50196 + ep->dwc_ep.dma_addr =
50197 + req->dw_align_buf_dma;
50198 + ep->dwc_ep.start_xfer_buff =
50199 + req->dw_align_buf;
50200 + ep->dwc_ep.xfer_buff =
50201 + req->dw_align_buf;
50202 + } else {
50203 + ep->dwc_ep.dma_addr = dma_buf;
50204 + ep->dwc_ep.start_xfer_buff = buf;
50205 + ep->dwc_ep.xfer_buff = buf;
50206 + }
50207 + ep->dwc_ep.xfer_len = 0;
50208 + ep->dwc_ep.xfer_count = 0;
50209 + ep->dwc_ep.sent_zlp = 0;
50210 + ep->dwc_ep.total_len = buflen;
50211 +
50212 + ep->dwc_ep.maxxfer = max_transfer;
50213 + if (GET_CORE_IF(pcd)->dma_desc_enable) {
50214 + uint32_t out_max_xfer =
50215 + DDMA_MAX_TRANSFER_SIZE -
50216 + (DDMA_MAX_TRANSFER_SIZE % 4);
50217 + if (ep->dwc_ep.is_in) {
50218 + if (ep->dwc_ep.maxxfer >
50219 + DDMA_MAX_TRANSFER_SIZE) {
50220 + ep->dwc_ep.maxxfer =
50221 + DDMA_MAX_TRANSFER_SIZE;
50222 + }
50223 + } else {
50224 + if (ep->dwc_ep.maxxfer >
50225 + out_max_xfer) {
50226 + ep->dwc_ep.maxxfer =
50227 + out_max_xfer;
50228 + }
50229 + }
50230 + }
50231 + if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
50232 + ep->dwc_ep.maxxfer -=
50233 + (ep->dwc_ep.maxxfer %
50234 + ep->dwc_ep.maxpacket);
50235 + }
50236 +
50237 + if (zero) {
50238 + if ((ep->dwc_ep.total_len %
50239 + ep->dwc_ep.maxpacket == 0)
50240 + && (ep->dwc_ep.total_len != 0)) {
50241 + ep->dwc_ep.sent_zlp = 1;
50242 + }
50243 + }
50244 +#ifdef DWC_UTE_CFI
50245 + }
50246 +#endif
50247 + dwc_otg_ep_start_transfer(GET_CORE_IF(pcd),
50248 + &ep->dwc_ep);
50249 + }
50250 + }
50251 +
50252 + if (req != 0) {
50253 + ++pcd->request_pending;
50254 + DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
50255 + if (ep->dwc_ep.is_in && ep->stopped
50256 + && !(GET_CORE_IF(pcd)->dma_enable)) {
50257 + /** @todo NGS Create a function for this. */
50258 + diepmsk_data_t diepmsk = {.d32 = 0 };
50259 + diepmsk.b.intktxfemp = 1;
50260 + if (GET_CORE_IF(pcd)->multiproc_int_enable) {
50261 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->
50262 + dev_if->dev_global_regs->diepeachintmsk
50263 + [ep->dwc_ep.num], 0,
50264 + diepmsk.d32);
50265 + } else {
50266 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->
50267 + dev_if->dev_global_regs->
50268 + diepmsk, 0, diepmsk.d32);
50269 + }
50270 +
50271 + }
50272 + }
50273 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50274 +
50275 + return 0;
50276 +}
50277 +
50278 +int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
50279 + void *req_handle)
50280 +{
50281 + dwc_irqflags_t flags;
50282 + dwc_otg_pcd_request_t *req;
50283 + dwc_otg_pcd_ep_t *ep;
50284 +
50285 + ep = get_ep_from_handle(pcd, ep_handle);
50286 + if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) {
50287 + DWC_WARN("bad argument\n");
50288 + return -DWC_E_INVALID;
50289 + }
50290 +
50291 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
50292 +
50293 + /* make sure it's actually queued on this endpoint */
50294 + DWC_CIRCLEQ_FOREACH(req, &ep->queue, queue_entry) {
50295 + if (req->priv == (void *)req_handle) {
50296 + break;
50297 + }
50298 + }
50299 +
50300 + if (req->priv != (void *)req_handle) {
50301 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50302 + return -DWC_E_INVALID;
50303 + }
50304 +
50305 + if (!DWC_CIRCLEQ_EMPTY_ENTRY(req, queue_entry)) {
50306 + dwc_otg_request_done(ep, req, -DWC_E_RESTART);
50307 + } else {
50308 + req = NULL;
50309 + }
50310 +
50311 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50312 +
50313 + return req ? 0 : -DWC_E_SHUTDOWN;
50314 +
50315 +}
50316 +
50317 +/**
50318 + * dwc_otg_pcd_ep_wedge - sets the halt feature and ignores clear requests
50319 + *
50320 + * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT)
50321 + * requests. If the gadget driver clears the halt status, it will
50322 + * automatically unwedge the endpoint.
50323 + *
50324 + * Returns zero on success, else negative DWC error code.
50325 + */
50326 +int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle)
50327 +{
50328 + dwc_otg_pcd_ep_t *ep;
50329 + dwc_irqflags_t flags;
50330 + int retval = 0;
50331 +
50332 + ep = get_ep_from_handle(pcd, ep_handle);
50333 +
50334 + if ((!ep->desc && ep != &pcd->ep0) ||
50335 + (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) {
50336 + DWC_WARN("%s, bad ep\n", __func__);
50337 + return -DWC_E_INVALID;
50338 + }
50339 +
50340 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
50341 + if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
50342 + DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num,
50343 + ep->dwc_ep.is_in ? "IN" : "OUT");
50344 + retval = -DWC_E_AGAIN;
50345 + } else {
50346 + /* This code needs to be reviewed */
50347 + if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) {
50348 + dtxfsts_data_t txstatus;
50349 + fifosize_data_t txfifosize;
50350 +
50351 + txfifosize.d32 =
50352 + DWC_READ_REG32(&GET_CORE_IF(pcd)->
50353 + core_global_regs->dtxfsiz[ep->dwc_ep.
50354 + tx_fifo_num]);
50355 + txstatus.d32 =
50356 + DWC_READ_REG32(&GET_CORE_IF(pcd)->
50357 + dev_if->in_ep_regs[ep->dwc_ep.num]->
50358 + dtxfsts);
50359 +
50360 + if (txstatus.b.txfspcavail < txfifosize.b.depth) {
50361 + DWC_WARN("%s() Data In Tx Fifo\n", __func__);
50362 + retval = -DWC_E_AGAIN;
50363 + } else {
50364 + if (ep->dwc_ep.num == 0) {
50365 + pcd->ep0state = EP0_STALL;
50366 + }
50367 +
50368 + ep->stopped = 1;
50369 + dwc_otg_ep_set_stall(GET_CORE_IF(pcd),
50370 + &ep->dwc_ep);
50371 + }
50372 + } else {
50373 + if (ep->dwc_ep.num == 0) {
50374 + pcd->ep0state = EP0_STALL;
50375 + }
50376 +
50377 + ep->stopped = 1;
50378 + dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
50379 + }
50380 + }
50381 +
50382 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50383 +
50384 + return retval;
50385 +}
50386 +
50387 +int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value)
50388 +{
50389 + dwc_otg_pcd_ep_t *ep;
50390 + dwc_irqflags_t flags;
50391 + int retval = 0;
50392 +
50393 + ep = get_ep_from_handle(pcd, ep_handle);
50394 +
50395 + if (!ep || (!ep->desc && ep != &pcd->ep0) ||
50396 + (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) {
50397 + DWC_WARN("%s, bad ep\n", __func__);
50398 + return -DWC_E_INVALID;
50399 + }
50400 +
50401 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
50402 + if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
50403 + DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num,
50404 + ep->dwc_ep.is_in ? "IN" : "OUT");
50405 + retval = -DWC_E_AGAIN;
50406 + } else if (value == 0) {
50407 + dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
50408 + } else if (value == 1) {
50409 + if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) {
50410 + dtxfsts_data_t txstatus;
50411 + fifosize_data_t txfifosize;
50412 +
50413 + txfifosize.d32 =
50414 + DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->
50415 + dtxfsiz[ep->dwc_ep.tx_fifo_num]);
50416 + txstatus.d32 =
50417 + DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
50418 + in_ep_regs[ep->dwc_ep.num]->dtxfsts);
50419 +
50420 + if (txstatus.b.txfspcavail < txfifosize.b.depth) {
50421 + DWC_WARN("%s() Data In Tx Fifo\n", __func__);
50422 + retval = -DWC_E_AGAIN;
50423 + } else {
50424 + if (ep->dwc_ep.num == 0) {
50425 + pcd->ep0state = EP0_STALL;
50426 + }
50427 +
50428 + ep->stopped = 1;
50429 + dwc_otg_ep_set_stall(GET_CORE_IF(pcd),
50430 + &ep->dwc_ep);
50431 + }
50432 + } else {
50433 + if (ep->dwc_ep.num == 0) {
50434 + pcd->ep0state = EP0_STALL;
50435 + }
50436 +
50437 + ep->stopped = 1;
50438 + dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
50439 + }
50440 + } else if (value == 2) {
50441 + ep->dwc_ep.stall_clear_flag = 0;
50442 + } else if (value == 3) {
50443 + ep->dwc_ep.stall_clear_flag = 1;
50444 + }
50445 +
50446 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50447 +
50448 + return retval;
50449 +}
50450 +
50451 +/**
50452 + * This function initiates remote wakeup of the host from suspend state.
50453 + */
50454 +void dwc_otg_pcd_rem_wkup_from_suspend(dwc_otg_pcd_t * pcd, int set)
50455 +{
50456 + dctl_data_t dctl = { 0 };
50457 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
50458 + dsts_data_t dsts;
50459 +
50460 + dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
50461 + if (!dsts.b.suspsts) {
50462 + DWC_WARN("Remote wakeup while is not in suspend state\n");
50463 + }
50464 + /* Check if DEVICE_REMOTE_WAKEUP feature enabled */
50465 + if (pcd->remote_wakeup_enable) {
50466 + if (set) {
50467 +
50468 + if (core_if->adp_enable) {
50469 + gpwrdn_data_t gpwrdn;
50470 +
50471 + dwc_otg_adp_probe_stop(core_if);
50472 +
50473 + /* Mask SRP detected interrupt from Power Down Logic */
50474 + gpwrdn.d32 = 0;
50475 + gpwrdn.b.srp_det_msk = 1;
50476 + DWC_MODIFY_REG32(&core_if->
50477 + core_global_regs->gpwrdn,
50478 + gpwrdn.d32, 0);
50479 +
50480 + /* Disable Power Down Logic */
50481 + gpwrdn.d32 = 0;
50482 + gpwrdn.b.pmuactv = 1;
50483 + DWC_MODIFY_REG32(&core_if->
50484 + core_global_regs->gpwrdn,
50485 + gpwrdn.d32, 0);
50486 +
50487 + /*
50488 + * Initialize the Core for Device mode.
50489 + */
50490 + core_if->op_state = B_PERIPHERAL;
50491 + dwc_otg_core_init(core_if);
50492 + dwc_otg_enable_global_interrupts(core_if);
50493 + cil_pcd_start(core_if);
50494 +
50495 + dwc_otg_initiate_srp(core_if);
50496 + }
50497 +
50498 + dctl.b.rmtwkupsig = 1;
50499 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
50500 + dctl, 0, dctl.d32);
50501 + DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
50502 +
50503 + dwc_mdelay(2);
50504 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
50505 + dctl, dctl.d32, 0);
50506 + DWC_DEBUGPL(DBG_PCD, "Clear Remote Wakeup\n");
50507 + }
50508 + } else {
50509 + DWC_DEBUGPL(DBG_PCD, "Remote Wakeup is disabled\n");
50510 + }
50511 +}
50512 +
50513 +#ifdef CONFIG_USB_DWC_OTG_LPM
50514 +/**
50515 + * This function initiates remote wakeup of the host from L1 sleep state.
50516 + */
50517 +void dwc_otg_pcd_rem_wkup_from_sleep(dwc_otg_pcd_t * pcd, int set)
50518 +{
50519 + glpmcfg_data_t lpmcfg;
50520 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
50521 +
50522 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
50523 +
50524 + /* Check if we are in L1 state */
50525 + if (!lpmcfg.b.prt_sleep_sts) {
50526 + DWC_DEBUGPL(DBG_PCD, "Device is not in sleep state\n");
50527 + return;
50528 + }
50529 +
50530 + /* Check if host allows remote wakeup */
50531 + if (!lpmcfg.b.rem_wkup_en) {
50532 + DWC_DEBUGPL(DBG_PCD, "Host does not allow remote wakeup\n");
50533 + return;
50534 + }
50535 +
50536 + /* Check if Resume OK */
50537 + if (!lpmcfg.b.sleep_state_resumeok) {
50538 + DWC_DEBUGPL(DBG_PCD, "Sleep state resume is not OK\n");
50539 + return;
50540 + }
50541 +
50542 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
50543 + lpmcfg.b.en_utmi_sleep = 0;
50544 + lpmcfg.b.hird_thres &= (~(1 << 4));
50545 + DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
50546 +
50547 + if (set) {
50548 + dctl_data_t dctl = {.d32 = 0 };
50549 + dctl.b.rmtwkupsig = 1;
50550 + /* Set RmtWkUpSig bit to start remote wakup signaling.
50551 + * Hardware will automatically clear this bit.
50552 + */
50553 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl,
50554 + 0, dctl.d32);
50555 + DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
50556 + }
50557 +
50558 +}
50559 +#endif
50560 +
50561 +/**
50562 + * Performs remote wakeup.
50563 + */
50564 +void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set)
50565 +{
50566 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
50567 + dwc_irqflags_t flags;
50568 + if (dwc_otg_is_device_mode(core_if)) {
50569 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
50570 +#ifdef CONFIG_USB_DWC_OTG_LPM
50571 + if (core_if->lx_state == DWC_OTG_L1) {
50572 + dwc_otg_pcd_rem_wkup_from_sleep(pcd, set);
50573 + } else {
50574 +#endif
50575 + dwc_otg_pcd_rem_wkup_from_suspend(pcd, set);
50576 +#ifdef CONFIG_USB_DWC_OTG_LPM
50577 + }
50578 +#endif
50579 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50580 + }
50581 + return;
50582 +}
50583 +
50584 +void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs)
50585 +{
50586 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
50587 + dctl_data_t dctl = { 0 };
50588 +
50589 + if (dwc_otg_is_device_mode(core_if)) {
50590 + dctl.b.sftdiscon = 1;
50591 + DWC_PRINTF("Soft disconnect for %d useconds\n",no_of_usecs);
50592 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
50593 + dwc_udelay(no_of_usecs);
50594 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32,0);
50595 +
50596 + } else{
50597 + DWC_PRINTF("NOT SUPPORTED IN HOST MODE\n");
50598 + }
50599 + return;
50600 +
50601 +}
50602 +
50603 +int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd)
50604 +{
50605 + dsts_data_t dsts;
50606 + gotgctl_data_t gotgctl;
50607 +
50608 + /*
50609 + * This function starts the Protocol if no session is in progress. If
50610 + * a session is already in progress, but the device is suspended,
50611 + * remote wakeup signaling is started.
50612 + */
50613 +
50614 + /* Check if valid session */
50615 + gotgctl.d32 =
50616 + DWC_READ_REG32(&(GET_CORE_IF(pcd)->core_global_regs->gotgctl));
50617 + if (gotgctl.b.bsesvld) {
50618 + /* Check if suspend state */
50619 + dsts.d32 =
50620 + DWC_READ_REG32(&
50621 + (GET_CORE_IF(pcd)->dev_if->
50622 + dev_global_regs->dsts));
50623 + if (dsts.b.suspsts) {
50624 + dwc_otg_pcd_remote_wakeup(pcd, 1);
50625 + }
50626 + } else {
50627 + dwc_otg_pcd_initiate_srp(pcd);
50628 + }
50629 +
50630 + return 0;
50631 +
50632 +}
50633 +
50634 +/**
50635 + * Start the SRP timer to detect when the SRP does not complete within
50636 + * 6 seconds.
50637 + *
50638 + * @param pcd the pcd structure.
50639 + */
50640 +void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd)
50641 +{
50642 + dwc_irqflags_t flags;
50643 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
50644 + dwc_otg_initiate_srp(GET_CORE_IF(pcd));
50645 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50646 +}
50647 +
50648 +int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd)
50649 +{
50650 + return dwc_otg_get_frame_number(GET_CORE_IF(pcd));
50651 +}
50652 +
50653 +int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd)
50654 +{
50655 + return GET_CORE_IF(pcd)->core_params->lpm_enable;
50656 +}
50657 +
50658 +uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd)
50659 +{
50660 + return pcd->b_hnp_enable;
50661 +}
50662 +
50663 +uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd)
50664 +{
50665 + return pcd->a_hnp_support;
50666 +}
50667 +
50668 +uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd)
50669 +{
50670 + return pcd->a_alt_hnp_support;
50671 +}
50672 +
50673 +int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd)
50674 +{
50675 + return pcd->remote_wakeup_enable;
50676 +}
50677 +
50678 +#endif /* DWC_HOST_ONLY */
50679 --- /dev/null
50680 +++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd.h
50681 @@ -0,0 +1,266 @@
50682 +/* ==========================================================================
50683 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $
50684 + * $Revision: #48 $
50685 + * $Date: 2012/08/10 $
50686 + * $Change: 2047372 $
50687 + *
50688 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
50689 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
50690 + * otherwise expressly agreed to in writing between Synopsys and you.
50691 + *
50692 + * The Software IS NOT an item of Licensed Software or Licensed Product under
50693 + * any End User Software License Agreement or Agreement for Licensed Product
50694 + * with Synopsys or any supplement thereto. You are permitted to use and
50695 + * redistribute this Software in source and binary forms, with or without
50696 + * modification, provided that redistributions of source code must retain this
50697 + * notice. You may not view, use, disclose, copy or distribute this file or
50698 + * any information contained herein except pursuant to this license grant from
50699 + * Synopsys. If you do not agree with this notice, including the disclaimer
50700 + * below, then you are not authorized to use the Software.
50701 + *
50702 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
50703 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
50704 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
50705 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
50706 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
50707 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
50708 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
50709 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
50710 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50711 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
50712 + * DAMAGE.
50713 + * ========================================================================== */
50714 +#ifndef DWC_HOST_ONLY
50715 +#if !defined(__DWC_PCD_H__)
50716 +#define __DWC_PCD_H__
50717 +
50718 +#include "dwc_otg_os_dep.h"
50719 +#include "usb.h"
50720 +#include "dwc_otg_cil.h"
50721 +#include "dwc_otg_pcd_if.h"
50722 +struct cfiobject;
50723 +
50724 +/**
50725 + * @file
50726 + *
50727 + * This file contains the structures, constants, and interfaces for
50728 + * the Perpherial Contoller Driver (PCD).
50729 + *
50730 + * The Peripheral Controller Driver (PCD) for Linux will implement the
50731 + * Gadget API, so that the existing Gadget drivers can be used. For
50732 + * the Mass Storage Function driver the File-backed USB Storage Gadget
50733 + * (FBS) driver will be used. The FBS driver supports the
50734 + * Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only
50735 + * transports.
50736 + *
50737 + */
50738 +
50739 +/** Invalid DMA Address */
50740 +#define DWC_DMA_ADDR_INVALID (~(dwc_dma_t)0)
50741 +
50742 +/** Max Transfer size for any EP */
50743 +#define DDMA_MAX_TRANSFER_SIZE 65535
50744 +
50745 +/**
50746 + * Get the pointer to the core_if from the pcd pointer.
50747 + */
50748 +#define GET_CORE_IF( _pcd ) (_pcd->core_if)
50749 +
50750 +/**
50751 + * States of EP0.
50752 + */
50753 +typedef enum ep0_state {
50754 + EP0_DISCONNECT, /* no host */
50755 + EP0_IDLE,
50756 + EP0_IN_DATA_PHASE,
50757 + EP0_OUT_DATA_PHASE,
50758 + EP0_IN_STATUS_PHASE,
50759 + EP0_OUT_STATUS_PHASE,
50760 + EP0_STALL,
50761 +} ep0state_e;
50762 +
50763 +/** Fordward declaration.*/
50764 +struct dwc_otg_pcd;
50765 +
50766 +/** DWC_otg iso request structure.
50767 + *
50768 + */
50769 +typedef struct usb_iso_request dwc_otg_pcd_iso_request_t;
50770 +
50771 +#ifdef DWC_UTE_PER_IO
50772 +
50773 +/**
50774 + * This shall be the exact analogy of the same type structure defined in the
50775 + * usb_gadget.h. Each descriptor contains
50776 + */
50777 +struct dwc_iso_pkt_desc_port {
50778 + uint32_t offset;
50779 + uint32_t length; /* expected length */
50780 + uint32_t actual_length;
50781 + uint32_t status;
50782 +};
50783 +
50784 +struct dwc_iso_xreq_port {
50785 + /** transfer/submission flag */
50786 + uint32_t tr_sub_flags;
50787 + /** Start the request ASAP */
50788 +#define DWC_EREQ_TF_ASAP 0x00000002
50789 + /** Just enqueue the request w/o initiating a transfer */
50790 +#define DWC_EREQ_TF_ENQUEUE 0x00000004
50791 +
50792 + /**
50793 + * count of ISO packets attached to this request - shall
50794 + * not exceed the pio_alloc_pkt_count
50795 + */
50796 + uint32_t pio_pkt_count;
50797 + /** count of ISO packets allocated for this request */
50798 + uint32_t pio_alloc_pkt_count;
50799 + /** number of ISO packet errors */
50800 + uint32_t error_count;
50801 + /** reserved for future extension */
50802 + uint32_t res;
50803 + /** Will be allocated and freed in the UTE gadget and based on the CFC value */
50804 + struct dwc_iso_pkt_desc_port *per_io_frame_descs;
50805 +};
50806 +#endif
50807 +/** DWC_otg request structure.
50808 + * This structure is a list of requests.
50809 + */
50810 +typedef struct dwc_otg_pcd_request {
50811 + void *priv;
50812 + void *buf;
50813 + dwc_dma_t dma;
50814 + uint32_t length;
50815 + uint32_t actual;
50816 + unsigned sent_zlp:1;
50817 + /**
50818 + * Used instead of original buffer if
50819 + * it(physical address) is not dword-aligned.
50820 + **/
50821 + uint8_t *dw_align_buf;
50822 + dwc_dma_t dw_align_buf_dma;
50823 +
50824 + DWC_CIRCLEQ_ENTRY(dwc_otg_pcd_request) queue_entry;
50825 +#ifdef DWC_UTE_PER_IO
50826 + struct dwc_iso_xreq_port ext_req;
50827 + //void *priv_ereq_nport; /* */
50828 +#endif
50829 +} dwc_otg_pcd_request_t;
50830 +
50831 +DWC_CIRCLEQ_HEAD(req_list, dwc_otg_pcd_request);
50832 +
50833 +/** PCD EP structure.
50834 + * This structure describes an EP, there is an array of EPs in the PCD
50835 + * structure.
50836 + */
50837 +typedef struct dwc_otg_pcd_ep {
50838 + /** USB EP Descriptor */
50839 + const usb_endpoint_descriptor_t *desc;
50840 +
50841 + /** queue of dwc_otg_pcd_requests. */
50842 + struct req_list queue;
50843 + unsigned stopped:1;
50844 + unsigned disabling:1;
50845 + unsigned dma:1;
50846 + unsigned queue_sof:1;
50847 +
50848 +#ifdef DWC_EN_ISOC
50849 + /** ISOC req handle passed */
50850 + void *iso_req_handle;
50851 +#endif //_EN_ISOC_
50852 +
50853 + /** DWC_otg ep data. */
50854 + dwc_ep_t dwc_ep;
50855 +
50856 + /** Pointer to PCD */
50857 + struct dwc_otg_pcd *pcd;
50858 +
50859 + void *priv;
50860 +} dwc_otg_pcd_ep_t;
50861 +
50862 +/** DWC_otg PCD Structure.
50863 + * This structure encapsulates the data for the dwc_otg PCD.
50864 + */
50865 +struct dwc_otg_pcd {
50866 + const struct dwc_otg_pcd_function_ops *fops;
50867 + /** The DWC otg device pointer */
50868 + struct dwc_otg_device *otg_dev;
50869 + /** Core Interface */
50870 + dwc_otg_core_if_t *core_if;
50871 + /** State of EP0 */
50872 + ep0state_e ep0state;
50873 + /** EP0 Request is pending */
50874 + unsigned ep0_pending:1;
50875 + /** Indicates when SET CONFIGURATION Request is in process */
50876 + unsigned request_config:1;
50877 + /** The state of the Remote Wakeup Enable. */
50878 + unsigned remote_wakeup_enable:1;
50879 + /** The state of the B-Device HNP Enable. */
50880 + unsigned b_hnp_enable:1;
50881 + /** The state of A-Device HNP Support. */
50882 + unsigned a_hnp_support:1;
50883 + /** The state of the A-Device Alt HNP support. */
50884 + unsigned a_alt_hnp_support:1;
50885 + /** Count of pending Requests */
50886 + unsigned request_pending;
50887 +
50888 + /** SETUP packet for EP0
50889 + * This structure is allocated as a DMA buffer on PCD initialization
50890 + * with enough space for up to 3 setup packets.
50891 + */
50892 + union {
50893 + usb_device_request_t req;
50894 + uint32_t d32[2];
50895 + } *setup_pkt;
50896 +
50897 + dwc_dma_t setup_pkt_dma_handle;
50898 +
50899 + /* Additional buffer and flag for CTRL_WR premature case */
50900 + uint8_t *backup_buf;
50901 + unsigned data_terminated;
50902 +
50903 + /** 2-byte dma buffer used to return status from GET_STATUS */
50904 + uint16_t *status_buf;
50905 + dwc_dma_t status_buf_dma_handle;
50906 +
50907 + /** EP0 */
50908 + dwc_otg_pcd_ep_t ep0;
50909 +
50910 + /** Array of IN EPs. */
50911 + dwc_otg_pcd_ep_t in_ep[MAX_EPS_CHANNELS - 1];
50912 + /** Array of OUT EPs. */
50913 + dwc_otg_pcd_ep_t out_ep[MAX_EPS_CHANNELS - 1];
50914 + /** number of valid EPs in the above array. */
50915 +// unsigned num_eps : 4;
50916 + dwc_spinlock_t *lock;
50917 +
50918 + /** Tasklet to defer starting of TEST mode transmissions until
50919 + * Status Phase has been completed.
50920 + */
50921 + dwc_tasklet_t *test_mode_tasklet;
50922 +
50923 + /** Tasklet to delay starting of xfer in DMA mode */
50924 + dwc_tasklet_t *start_xfer_tasklet;
50925 +
50926 + /** The test mode to enter when the tasklet is executed. */
50927 + unsigned test_mode;
50928 + /** The cfi_api structure that implements most of the CFI API
50929 + * and OTG specific core configuration functionality
50930 + */
50931 +#ifdef DWC_UTE_CFI
50932 + struct cfiobject *cfi;
50933 +#endif
50934 +
50935 +};
50936 +
50937 +//FIXME this functions should be static, and this prototypes should be removed
50938 +extern void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep);
50939 +extern void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep,
50940 + dwc_otg_pcd_request_t * req, int32_t status);
50941 +
50942 +void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
50943 + void *req_handle);
50944 +
50945 +extern void do_test_mode(void *data);
50946 +#endif
50947 +#endif /* DWC_HOST_ONLY */
50948 --- /dev/null
50949 +++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h
50950 @@ -0,0 +1,360 @@
50951 +/* ==========================================================================
50952 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_if.h $
50953 + * $Revision: #11 $
50954 + * $Date: 2011/10/26 $
50955 + * $Change: 1873028 $
50956 + *
50957 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
50958 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
50959 + * otherwise expressly agreed to in writing between Synopsys and you.
50960 + *
50961 + * The Software IS NOT an item of Licensed Software or Licensed Product under
50962 + * any End User Software License Agreement or Agreement for Licensed Product
50963 + * with Synopsys or any supplement thereto. You are permitted to use and
50964 + * redistribute this Software in source and binary forms, with or without
50965 + * modification, provided that redistributions of source code must retain this
50966 + * notice. You may not view, use, disclose, copy or distribute this file or
50967 + * any information contained herein except pursuant to this license grant from
50968 + * Synopsys. If you do not agree with this notice, including the disclaimer
50969 + * below, then you are not authorized to use the Software.
50970 + *
50971 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
50972 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
50973 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
50974 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
50975 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
50976 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
50977 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
50978 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
50979 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50980 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
50981 + * DAMAGE.
50982 + * ========================================================================== */
50983 +#ifndef DWC_HOST_ONLY
50984 +
50985 +#if !defined(__DWC_PCD_IF_H__)
50986 +#define __DWC_PCD_IF_H__
50987 +
50988 +//#include "dwc_os.h"
50989 +#include "dwc_otg_core_if.h"
50990 +
50991 +/** @file
50992 + * This file defines DWC_OTG PCD Core API.
50993 + */
50994 +
50995 +struct dwc_otg_pcd;
50996 +typedef struct dwc_otg_pcd dwc_otg_pcd_t;
50997 +
50998 +/** Maxpacket size for EP0 */
50999 +#define MAX_EP0_SIZE 64
51000 +/** Maxpacket size for any EP */
51001 +#define MAX_PACKET_SIZE 1024
51002 +
51003 +/** @name Function Driver Callbacks */
51004 +/** @{ */
51005 +
51006 +/** This function will be called whenever a previously queued request has
51007 + * completed. The status value will be set to -DWC_E_SHUTDOWN to indicated a
51008 + * failed or aborted transfer, or -DWC_E_RESTART to indicate the device was reset,
51009 + * or -DWC_E_TIMEOUT to indicate it timed out, or -DWC_E_INVALID to indicate invalid
51010 + * parameters. */
51011 +typedef int (*dwc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
51012 + void *req_handle, int32_t status,
51013 + uint32_t actual);
51014 +/**
51015 + * This function will be called whenever a previousle queued ISOC request has
51016 + * completed. Count of ISOC packets could be read using dwc_otg_pcd_get_iso_packet_count
51017 + * function.
51018 + * The status of each ISOC packet could be read using dwc_otg_pcd_get_iso_packet_*
51019 + * functions.
51020 + */
51021 +typedef int (*dwc_isoc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
51022 + void *req_handle, int proc_buf_num);
51023 +/** This function should handle any SETUP request that cannot be handled by the
51024 + * PCD Core. This includes most GET_DESCRIPTORs, SET_CONFIGS, Any
51025 + * class-specific requests, etc. The function must non-blocking.
51026 + *
51027 + * Returns 0 on success.
51028 + * Returns -DWC_E_NOT_SUPPORTED if the request is not supported.
51029 + * Returns -DWC_E_INVALID if the setup request had invalid parameters or bytes.
51030 + * Returns -DWC_E_SHUTDOWN on any other error. */
51031 +typedef int (*dwc_setup_cb_t) (dwc_otg_pcd_t * pcd, uint8_t * bytes);
51032 +/** This is called whenever the device has been disconnected. The function
51033 + * driver should take appropriate action to clean up all pending requests in the
51034 + * PCD Core, remove all endpoints (except ep0), and initialize back to reset
51035 + * state. */
51036 +typedef int (*dwc_disconnect_cb_t) (dwc_otg_pcd_t * pcd);
51037 +/** This function is called when device has been connected. */
51038 +typedef int (*dwc_connect_cb_t) (dwc_otg_pcd_t * pcd, int speed);
51039 +/** This function is called when device has been suspended */
51040 +typedef int (*dwc_suspend_cb_t) (dwc_otg_pcd_t * pcd);
51041 +/** This function is called when device has received LPM tokens, i.e.
51042 + * device has been sent to sleep state. */
51043 +typedef int (*dwc_sleep_cb_t) (dwc_otg_pcd_t * pcd);
51044 +/** This function is called when device has been resumed
51045 + * from suspend(L2) or L1 sleep state. */
51046 +typedef int (*dwc_resume_cb_t) (dwc_otg_pcd_t * pcd);
51047 +/** This function is called whenever hnp params has been changed.
51048 + * User can call get_b_hnp_enable, get_a_hnp_support, get_a_alt_hnp_support functions
51049 + * to get hnp parameters. */
51050 +typedef int (*dwc_hnp_params_changed_cb_t) (dwc_otg_pcd_t * pcd);
51051 +/** This function is called whenever USB RESET is detected. */
51052 +typedef int (*dwc_reset_cb_t) (dwc_otg_pcd_t * pcd);
51053 +
51054 +typedef int (*cfi_setup_cb_t) (dwc_otg_pcd_t * pcd, void *ctrl_req_bytes);
51055 +
51056 +/**
51057 + *
51058 + * @param ep_handle Void pointer to the usb_ep structure
51059 + * @param ereq_port Pointer to the extended request structure created in the
51060 + * portable part.
51061 + */
51062 +typedef int (*xiso_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
51063 + void *req_handle, int32_t status,
51064 + void *ereq_port);
51065 +/** Function Driver Ops Data Structure */
51066 +struct dwc_otg_pcd_function_ops {
51067 + dwc_connect_cb_t connect;
51068 + dwc_disconnect_cb_t disconnect;
51069 + dwc_setup_cb_t setup;
51070 + dwc_completion_cb_t complete;
51071 + dwc_isoc_completion_cb_t isoc_complete;
51072 + dwc_suspend_cb_t suspend;
51073 + dwc_sleep_cb_t sleep;
51074 + dwc_resume_cb_t resume;
51075 + dwc_reset_cb_t reset;
51076 + dwc_hnp_params_changed_cb_t hnp_changed;
51077 + cfi_setup_cb_t cfi_setup;
51078 +#ifdef DWC_UTE_PER_IO
51079 + xiso_completion_cb_t xisoc_complete;
51080 +#endif
51081 +};
51082 +/** @} */
51083 +
51084 +/** @name Function Driver Functions */
51085 +/** @{ */
51086 +
51087 +/** Call this function to get pointer on dwc_otg_pcd_t,
51088 + * this pointer will be used for all PCD API functions.
51089 + *
51090 + * @param core_if The DWC_OTG Core
51091 + */
51092 +extern dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if);
51093 +
51094 +/** Frees PCD allocated by dwc_otg_pcd_init
51095 + *
51096 + * @param pcd The PCD
51097 + */
51098 +extern void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd);
51099 +
51100 +/** Call this to bind the function driver to the PCD Core.
51101 + *
51102 + * @param pcd Pointer on dwc_otg_pcd_t returned by dwc_otg_pcd_init function.
51103 + * @param fops The Function Driver Ops data structure containing pointers to all callbacks.
51104 + */
51105 +extern void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
51106 + const struct dwc_otg_pcd_function_ops *fops);
51107 +
51108 +/** Enables an endpoint for use. This function enables an endpoint in
51109 + * the PCD. The endpoint is described by the ep_desc which has the
51110 + * same format as a USB ep descriptor. The ep_handle parameter is used to refer
51111 + * to the endpoint from other API functions and in callbacks. Normally this
51112 + * should be called after a SET_CONFIGURATION/SET_INTERFACE to configure the
51113 + * core for that interface.
51114 + *
51115 + * Returns -DWC_E_INVALID if invalid parameters were passed.
51116 + * Returns -DWC_E_SHUTDOWN if any other error ocurred.
51117 + * Returns 0 on success.
51118 + *
51119 + * @param pcd The PCD
51120 + * @param ep_desc Endpoint descriptor
51121 + * @param usb_ep Handle on endpoint, that will be used to identify endpoint.
51122 + */
51123 +extern int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
51124 + const uint8_t * ep_desc, void *usb_ep);
51125 +
51126 +/** Disable the endpoint referenced by ep_handle.
51127 + *
51128 + * Returns -DWC_E_INVALID if invalid parameters were passed.
51129 + * Returns -DWC_E_SHUTDOWN if any other error occurred.
51130 + * Returns 0 on success. */
51131 +extern int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle);
51132 +
51133 +/** Queue a data transfer request on the endpoint referenced by ep_handle.
51134 + * After the transfer is completes, the complete callback will be called with
51135 + * the request status.
51136 + *
51137 + * @param pcd The PCD
51138 + * @param ep_handle The handle of the endpoint
51139 + * @param buf The buffer for the data
51140 + * @param dma_buf The DMA buffer for the data
51141 + * @param buflen The length of the data transfer
51142 + * @param zero Specifies whether to send zero length last packet.
51143 + * @param req_handle Set this handle to any value to use to reference this
51144 + * request in the ep_dequeue function or from the complete callback
51145 + * @param atomic_alloc If driver need to perform atomic allocations
51146 + * for internal data structures.
51147 + *
51148 + * Returns -DWC_E_INVALID if invalid parameters were passed.
51149 + * Returns -DWC_E_SHUTDOWN if any other error ocurred.
51150 + * Returns 0 on success. */
51151 +extern int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
51152 + uint8_t * buf, dwc_dma_t dma_buf,
51153 + uint32_t buflen, int zero, void *req_handle,
51154 + int atomic_alloc);
51155 +#ifdef DWC_UTE_PER_IO
51156 +/**
51157 + *
51158 + * @param ereq_nonport Pointer to the extended request part of the
51159 + * usb_request structure defined in usb_gadget.h file.
51160 + */
51161 +extern int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
51162 + uint8_t * buf, dwc_dma_t dma_buf,
51163 + uint32_t buflen, int zero,
51164 + void *req_handle, int atomic_alloc,
51165 + void *ereq_nonport);
51166 +
51167 +#endif
51168 +
51169 +/** De-queue the specified data transfer that has not yet completed.
51170 + *
51171 + * Returns -DWC_E_INVALID if invalid parameters were passed.
51172 + * Returns -DWC_E_SHUTDOWN if any other error ocurred.
51173 + * Returns 0 on success. */
51174 +extern int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
51175 + void *req_handle);
51176 +
51177 +/** Halt (STALL) an endpoint or clear it.
51178 + *
51179 + * Returns -DWC_E_INVALID if invalid parameters were passed.
51180 + * Returns -DWC_E_SHUTDOWN if any other error ocurred.
51181 + * Returns -DWC_E_AGAIN if the STALL cannot be sent and must be tried again later
51182 + * Returns 0 on success. */
51183 +extern int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value);
51184 +
51185 +/** This function */
51186 +extern int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle);
51187 +
51188 +/** This function should be called on every hardware interrupt */
51189 +extern int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd);
51190 +
51191 +/** This function returns current frame number */
51192 +extern int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd);
51193 +
51194 +/**
51195 + * Start isochronous transfers on the endpoint referenced by ep_handle.
51196 + * For isochronous transfers duble buffering is used.
51197 + * After processing each of buffers comlete callback will be called with
51198 + * status for each transaction.
51199 + *
51200 + * @param pcd The PCD
51201 + * @param ep_handle The handle of the endpoint
51202 + * @param buf0 The virtual address of first data buffer
51203 + * @param buf1 The virtual address of second data buffer
51204 + * @param dma0 The DMA address of first data buffer
51205 + * @param dma1 The DMA address of second data buffer
51206 + * @param sync_frame Data pattern frame number
51207 + * @param dp_frame Data size for pattern frame
51208 + * @param data_per_frame Data size for regular frame
51209 + * @param start_frame Frame number to start transfers, if -1 then start transfers ASAP.
51210 + * @param buf_proc_intrvl Interval of ISOC Buffer processing
51211 + * @param req_handle Handle of ISOC request
51212 + * @param atomic_alloc Specefies whether to perform atomic allocation for
51213 + * internal data structures.
51214 + *
51215 + * Returns -DWC_E_NO_MEMORY if there is no enough memory.
51216 + * Returns -DWC_E_INVALID if incorrect arguments are passed to the function.
51217 + * Returns -DW_E_SHUTDOWN for any other error.
51218 + * Returns 0 on success
51219 + */
51220 +extern int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
51221 + uint8_t * buf0, uint8_t * buf1,
51222 + dwc_dma_t dma0, dwc_dma_t dma1,
51223 + int sync_frame, int dp_frame,
51224 + int data_per_frame, int start_frame,
51225 + int buf_proc_intrvl, void *req_handle,
51226 + int atomic_alloc);
51227 +
51228 +/** Stop ISOC transfers on endpoint referenced by ep_handle.
51229 + *
51230 + * @param pcd The PCD
51231 + * @param ep_handle The handle of the endpoint
51232 + * @param req_handle Handle of ISOC request
51233 + *
51234 + * Returns -DWC_E_INVALID if incorrect arguments are passed to the function
51235 + * Returns 0 on success
51236 + */
51237 +int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
51238 + void *req_handle);
51239 +
51240 +/** Get ISOC packet status.
51241 + *
51242 + * @param pcd The PCD
51243 + * @param ep_handle The handle of the endpoint
51244 + * @param iso_req_handle Isochronoush request handle
51245 + * @param packet Number of packet
51246 + * @param status Out parameter for returning status
51247 + * @param actual Out parameter for returning actual length
51248 + * @param offset Out parameter for returning offset
51249 + *
51250 + */
51251 +extern void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd,
51252 + void *ep_handle,
51253 + void *iso_req_handle, int packet,
51254 + int *status, int *actual,
51255 + int *offset);
51256 +
51257 +/** Get ISOC packet count.
51258 + *
51259 + * @param pcd The PCD
51260 + * @param ep_handle The handle of the endpoint
51261 + * @param iso_req_handle
51262 + */
51263 +extern int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd,
51264 + void *ep_handle,
51265 + void *iso_req_handle);
51266 +
51267 +/** This function starts the SRP Protocol if no session is in progress. If
51268 + * a session is already in progress, but the device is suspended,
51269 + * remote wakeup signaling is started.
51270 + */
51271 +extern int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd);
51272 +
51273 +/** This function returns 1 if LPM support is enabled, and 0 otherwise. */
51274 +extern int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd);
51275 +
51276 +/** This function returns 1 if remote wakeup is allowed and 0, otherwise. */
51277 +extern int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd);
51278 +
51279 +/** Initiate SRP */
51280 +extern void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd);
51281 +
51282 +/** Starts remote wakeup signaling. */
51283 +extern void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set);
51284 +
51285 +/** Starts micorsecond soft disconnect. */
51286 +extern void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs);
51287 +/** This function returns whether device is dualspeed.*/
51288 +extern uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd);
51289 +
51290 +/** This function returns whether device is otg. */
51291 +extern uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd);
51292 +
51293 +/** These functions allow to get hnp parameters */
51294 +extern uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd);
51295 +extern uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd);
51296 +extern uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd);
51297 +
51298 +/** CFI specific Interface functions */
51299 +/** Allocate a cfi buffer */
51300 +extern uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep,
51301 + dwc_dma_t * addr, size_t buflen,
51302 + int flags);
51303 +
51304 +/******************************************************************************/
51305 +
51306 +/** @} */
51307 +
51308 +#endif /* __DWC_PCD_IF_H__ */
51309 +
51310 +#endif /* DWC_HOST_ONLY */
51311 --- /dev/null
51312 +++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c
51313 @@ -0,0 +1,5147 @@
51314 +/* ==========================================================================
51315 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $
51316 + * $Revision: #116 $
51317 + * $Date: 2012/08/10 $
51318 + * $Change: 2047372 $
51319 + *
51320 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
51321 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
51322 + * otherwise expressly agreed to in writing between Synopsys and you.
51323 + *
51324 + * The Software IS NOT an item of Licensed Software or Licensed Product under
51325 + * any End User Software License Agreement or Agreement for Licensed Product
51326 + * with Synopsys or any supplement thereto. You are permitted to use and
51327 + * redistribute this Software in source and binary forms, with or without
51328 + * modification, provided that redistributions of source code must retain this
51329 + * notice. You may not view, use, disclose, copy or distribute this file or
51330 + * any information contained herein except pursuant to this license grant from
51331 + * Synopsys. If you do not agree with this notice, including the disclaimer
51332 + * below, then you are not authorized to use the Software.
51333 + *
51334 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
51335 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
51336 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
51337 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
51338 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
51339 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
51340 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
51341 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
51342 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
51343 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
51344 + * DAMAGE.
51345 + * ========================================================================== */
51346 +#ifndef DWC_HOST_ONLY
51347 +
51348 +#include "dwc_otg_pcd.h"
51349 +
51350 +#ifdef DWC_UTE_CFI
51351 +#include "dwc_otg_cfi.h"
51352 +#endif
51353 +
51354 +#ifdef DWC_UTE_PER_IO
51355 +extern void complete_xiso_ep(dwc_otg_pcd_ep_t * ep);
51356 +#endif
51357 +//#define PRINT_CFI_DMA_DESCS
51358 +
51359 +#define DEBUG_EP0
51360 +
51361 +/**
51362 + * This function updates OTG.
51363 + */
51364 +static void dwc_otg_pcd_update_otg(dwc_otg_pcd_t * pcd, const unsigned reset)
51365 +{
51366 +
51367 + if (reset) {
51368 + pcd->b_hnp_enable = 0;
51369 + pcd->a_hnp_support = 0;
51370 + pcd->a_alt_hnp_support = 0;
51371 + }
51372 +
51373 + if (pcd->fops->hnp_changed) {
51374 + pcd->fops->hnp_changed(pcd);
51375 + }
51376 +}
51377 +
51378 +/** @file
51379 + * This file contains the implementation of the PCD Interrupt handlers.
51380 + *
51381 + * The PCD handles the device interrupts. Many conditions can cause a
51382 + * device interrupt. When an interrupt occurs, the device interrupt
51383 + * service routine determines the cause of the interrupt and
51384 + * dispatches handling to the appropriate function. These interrupt
51385 + * handling functions are described below.
51386 + * All interrupt registers are processed from LSB to MSB.
51387 + */
51388 +
51389 +/**
51390 + * This function prints the ep0 state for debug purposes.
51391 + */
51392 +static inline void print_ep0_state(dwc_otg_pcd_t * pcd)
51393 +{
51394 +#ifdef DEBUG
51395 + char str[40];
51396 +
51397 + switch (pcd->ep0state) {
51398 + case EP0_DISCONNECT:
51399 + dwc_strcpy(str, "EP0_DISCONNECT");
51400 + break;
51401 + case EP0_IDLE:
51402 + dwc_strcpy(str, "EP0_IDLE");
51403 + break;
51404 + case EP0_IN_DATA_PHASE:
51405 + dwc_strcpy(str, "EP0_IN_DATA_PHASE");
51406 + break;
51407 + case EP0_OUT_DATA_PHASE:
51408 + dwc_strcpy(str, "EP0_OUT_DATA_PHASE");
51409 + break;
51410 + case EP0_IN_STATUS_PHASE:
51411 + dwc_strcpy(str, "EP0_IN_STATUS_PHASE");
51412 + break;
51413 + case EP0_OUT_STATUS_PHASE:
51414 + dwc_strcpy(str, "EP0_OUT_STATUS_PHASE");
51415 + break;
51416 + case EP0_STALL:
51417 + dwc_strcpy(str, "EP0_STALL");
51418 + break;
51419 + default:
51420 + dwc_strcpy(str, "EP0_INVALID");
51421 + }
51422 +
51423 + DWC_DEBUGPL(DBG_ANY, "%s(%d)\n", str, pcd->ep0state);
51424 +#endif
51425 +}
51426 +
51427 +/**
51428 + * This function calculate the size of the payload in the memory
51429 + * for out endpoints and prints size for debug purposes(used in
51430 + * 2.93a DevOutNak feature).
51431 + */
51432 +static inline void print_memory_payload(dwc_otg_pcd_t * pcd, dwc_ep_t * ep)
51433 +{
51434 +#ifdef DEBUG
51435 + deptsiz_data_t deptsiz_init = {.d32 = 0 };
51436 + deptsiz_data_t deptsiz_updt = {.d32 = 0 };
51437 + int pack_num;
51438 + unsigned payload;
51439 +
51440 + deptsiz_init.d32 = pcd->core_if->start_doeptsiz_val[ep->num];
51441 + deptsiz_updt.d32 =
51442 + DWC_READ_REG32(&pcd->core_if->dev_if->
51443 + out_ep_regs[ep->num]->doeptsiz);
51444 + /* Payload will be */
51445 + payload = deptsiz_init.b.xfersize - deptsiz_updt.b.xfersize;
51446 + /* Packet count is decremented every time a packet
51447 + * is written to the RxFIFO not in to the external memory
51448 + * So, if payload == 0, then it means no packet was sent to ext memory*/
51449 + pack_num = (!payload) ? 0 : (deptsiz_init.b.pktcnt - deptsiz_updt.b.pktcnt);
51450 + DWC_DEBUGPL(DBG_PCDV,
51451 + "Payload for EP%d-%s\n",
51452 + ep->num, (ep->is_in ? "IN" : "OUT"));
51453 + DWC_DEBUGPL(DBG_PCDV,
51454 + "Number of transfered bytes = 0x%08x\n", payload);
51455 + DWC_DEBUGPL(DBG_PCDV,
51456 + "Number of transfered packets = %d\n", pack_num);
51457 +#endif
51458 +}
51459 +
51460 +
51461 +#ifdef DWC_UTE_CFI
51462 +static inline void print_desc(struct dwc_otg_dma_desc *ddesc,
51463 + const uint8_t * epname, int descnum)
51464 +{
51465 + CFI_INFO
51466 + ("%s DMA_DESC(%d) buf=0x%08x bytes=0x%04x; sp=0x%x; l=0x%x; sts=0x%02x; bs=0x%02x\n",
51467 + epname, descnum, ddesc->buf, ddesc->status.b.bytes,
51468 + ddesc->status.b.sp, ddesc->status.b.l, ddesc->status.b.sts,
51469 + ddesc->status.b.bs);
51470 +}
51471 +#endif
51472 +
51473 +/**
51474 + * This function returns pointer to in ep struct with number ep_num
51475 + */
51476 +static inline dwc_otg_pcd_ep_t *get_in_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
51477 +{
51478 + int i;
51479 + int num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
51480 + if (ep_num == 0) {
51481 + return &pcd->ep0;
51482 + } else {
51483 + for (i = 0; i < num_in_eps; ++i) {
51484 + if (pcd->in_ep[i].dwc_ep.num == ep_num)
51485 + return &pcd->in_ep[i];
51486 + }
51487 + return 0;
51488 + }
51489 +}
51490 +
51491 +/**
51492 + * This function returns pointer to out ep struct with number ep_num
51493 + */
51494 +static inline dwc_otg_pcd_ep_t *get_out_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
51495 +{
51496 + int i;
51497 + int num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
51498 + if (ep_num == 0) {
51499 + return &pcd->ep0;
51500 + } else {
51501 + for (i = 0; i < num_out_eps; ++i) {
51502 + if (pcd->out_ep[i].dwc_ep.num == ep_num)
51503 + return &pcd->out_ep[i];
51504 + }
51505 + return 0;
51506 + }
51507 +}
51508 +
51509 +/**
51510 + * This functions gets a pointer to an EP from the wIndex address
51511 + * value of the control request.
51512 + */
51513 +dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex)
51514 +{
51515 + dwc_otg_pcd_ep_t *ep;
51516 + uint32_t ep_num = UE_GET_ADDR(wIndex);
51517 +
51518 + if (ep_num == 0) {
51519 + ep = &pcd->ep0;
51520 + } else if (UE_GET_DIR(wIndex) == UE_DIR_IN) { /* in ep */
51521 + ep = &pcd->in_ep[ep_num - 1];
51522 + } else {
51523 + ep = &pcd->out_ep[ep_num - 1];
51524 + }
51525 +
51526 + return ep;
51527 +}
51528 +
51529 +/**
51530 + * This function checks the EP request queue, if the queue is not
51531 + * empty the next request is started.
51532 + */
51533 +void start_next_request(dwc_otg_pcd_ep_t * ep)
51534 +{
51535 + dwc_otg_pcd_request_t *req = 0;
51536 + uint32_t max_transfer =
51537 + GET_CORE_IF(ep->pcd)->core_params->max_transfer_size;
51538 +
51539 +#ifdef DWC_UTE_CFI
51540 + struct dwc_otg_pcd *pcd;
51541 + pcd = ep->pcd;
51542 +#endif
51543 +
51544 + if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
51545 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
51546 +
51547 +#ifdef DWC_UTE_CFI
51548 + if (ep->dwc_ep.buff_mode != BM_STANDARD) {
51549 + ep->dwc_ep.cfi_req_len = req->length;
51550 + pcd->cfi->ops.build_descriptors(pcd->cfi, pcd, ep, req);
51551 + } else {
51552 +#endif
51553 + /* Setup and start the Transfer */
51554 + if (req->dw_align_buf) {
51555 + ep->dwc_ep.dma_addr = req->dw_align_buf_dma;
51556 + ep->dwc_ep.start_xfer_buff = req->dw_align_buf;
51557 + ep->dwc_ep.xfer_buff = req->dw_align_buf;
51558 + } else {
51559 + ep->dwc_ep.dma_addr = req->dma;
51560 + ep->dwc_ep.start_xfer_buff = req->buf;
51561 + ep->dwc_ep.xfer_buff = req->buf;
51562 + }
51563 + ep->dwc_ep.sent_zlp = 0;
51564 + ep->dwc_ep.total_len = req->length;
51565 + ep->dwc_ep.xfer_len = 0;
51566 + ep->dwc_ep.xfer_count = 0;
51567 +
51568 + ep->dwc_ep.maxxfer = max_transfer;
51569 + if (GET_CORE_IF(ep->pcd)->dma_desc_enable) {
51570 + uint32_t out_max_xfer = DDMA_MAX_TRANSFER_SIZE
51571 + - (DDMA_MAX_TRANSFER_SIZE % 4);
51572 + if (ep->dwc_ep.is_in) {
51573 + if (ep->dwc_ep.maxxfer >
51574 + DDMA_MAX_TRANSFER_SIZE) {
51575 + ep->dwc_ep.maxxfer =
51576 + DDMA_MAX_TRANSFER_SIZE;
51577 + }
51578 + } else {
51579 + if (ep->dwc_ep.maxxfer > out_max_xfer) {
51580 + ep->dwc_ep.maxxfer =
51581 + out_max_xfer;
51582 + }
51583 + }
51584 + }
51585 + if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
51586 + ep->dwc_ep.maxxfer -=
51587 + (ep->dwc_ep.maxxfer % ep->dwc_ep.maxpacket);
51588 + }
51589 + if (req->sent_zlp) {
51590 + if ((ep->dwc_ep.total_len %
51591 + ep->dwc_ep.maxpacket == 0)
51592 + && (ep->dwc_ep.total_len != 0)) {
51593 + ep->dwc_ep.sent_zlp = 1;
51594 + }
51595 +
51596 + }
51597 +#ifdef DWC_UTE_CFI
51598 + }
51599 +#endif
51600 + dwc_otg_ep_start_transfer(GET_CORE_IF(ep->pcd), &ep->dwc_ep);
51601 + } else if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
51602 + DWC_PRINTF("There are no more ISOC requests \n");
51603 + ep->dwc_ep.frame_num = 0xFFFFFFFF;
51604 + }
51605 +}
51606 +
51607 +/**
51608 + * This function handles the SOF Interrupts. At this time the SOF
51609 + * Interrupt is disabled.
51610 + */
51611 +int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t * pcd)
51612 +{
51613 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
51614 +
51615 + gintsts_data_t gintsts;
51616 +
51617 + DWC_DEBUGPL(DBG_PCD, "SOF\n");
51618 +
51619 + /* Clear interrupt */
51620 + gintsts.d32 = 0;
51621 + gintsts.b.sofintr = 1;
51622 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
51623 +
51624 + return 1;
51625 +}
51626 +
51627 +/**
51628 + * This function handles the Rx Status Queue Level Interrupt, which
51629 + * indicates that there is a least one packet in the Rx FIFO. The
51630 + * packets are moved from the FIFO to memory, where they will be
51631 + * processed when the Endpoint Interrupt Register indicates Transfer
51632 + * Complete or SETUP Phase Done.
51633 + *
51634 + * Repeat the following until the Rx Status Queue is empty:
51635 + * -# Read the Receive Status Pop Register (GRXSTSP) to get Packet
51636 + * info
51637 + * -# If Receive FIFO is empty then skip to step Clear the interrupt
51638 + * and exit
51639 + * -# If SETUP Packet call dwc_otg_read_setup_packet to copy the
51640 + * SETUP data to the buffer
51641 + * -# If OUT Data Packet call dwc_otg_read_packet to copy the data
51642 + * to the destination buffer
51643 + */
51644 +int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t * pcd)
51645 +{
51646 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
51647 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
51648 + gintmsk_data_t gintmask = {.d32 = 0 };
51649 + device_grxsts_data_t status;
51650 + dwc_otg_pcd_ep_t *ep;
51651 + gintsts_data_t gintsts;
51652 +#ifdef DEBUG
51653 + static char *dpid_str[] = { "D0", "D2", "D1", "MDATA" };
51654 +#endif
51655 +
51656 + //DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd);
51657 + /* Disable the Rx Status Queue Level interrupt */
51658 + gintmask.b.rxstsqlvl = 1;
51659 + DWC_MODIFY_REG32(&global_regs->gintmsk, gintmask.d32, 0);
51660 +
51661 + /* Get the Status from the top of the FIFO */
51662 + status.d32 = DWC_READ_REG32(&global_regs->grxstsp);
51663 +
51664 + DWC_DEBUGPL(DBG_PCD, "EP:%d BCnt:%d DPID:%s "
51665 + "pktsts:%x Frame:%d(0x%0x)\n",
51666 + status.b.epnum, status.b.bcnt,
51667 + dpid_str[status.b.dpid],
51668 + status.b.pktsts, status.b.fn, status.b.fn);
51669 + /* Get pointer to EP structure */
51670 + ep = get_out_ep(pcd, status.b.epnum);
51671 +
51672 + switch (status.b.pktsts) {
51673 + case DWC_DSTS_GOUT_NAK:
51674 + DWC_DEBUGPL(DBG_PCDV, "Global OUT NAK\n");
51675 + break;
51676 + case DWC_STS_DATA_UPDT:
51677 + DWC_DEBUGPL(DBG_PCDV, "OUT Data Packet\n");
51678 + if (status.b.bcnt && ep->dwc_ep.xfer_buff) {
51679 + /** @todo NGS Check for buffer overflow? */
51680 + dwc_otg_read_packet(core_if,
51681 + ep->dwc_ep.xfer_buff,
51682 + status.b.bcnt);
51683 + ep->dwc_ep.xfer_count += status.b.bcnt;
51684 + ep->dwc_ep.xfer_buff += status.b.bcnt;
51685 + }
51686 + break;
51687 + case DWC_STS_XFER_COMP:
51688 + DWC_DEBUGPL(DBG_PCDV, "OUT Complete\n");
51689 + break;
51690 + case DWC_DSTS_SETUP_COMP:
51691 +#ifdef DEBUG_EP0
51692 + DWC_DEBUGPL(DBG_PCDV, "Setup Complete\n");
51693 +#endif
51694 + break;
51695 + case DWC_DSTS_SETUP_UPDT:
51696 + dwc_otg_read_setup_packet(core_if, pcd->setup_pkt->d32);
51697 +#ifdef DEBUG_EP0
51698 + DWC_DEBUGPL(DBG_PCD,
51699 + "SETUP PKT: %02x.%02x v%04x i%04x l%04x\n",
51700 + pcd->setup_pkt->req.bmRequestType,
51701 + pcd->setup_pkt->req.bRequest,
51702 + UGETW(pcd->setup_pkt->req.wValue),
51703 + UGETW(pcd->setup_pkt->req.wIndex),
51704 + UGETW(pcd->setup_pkt->req.wLength));
51705 +#endif
51706 + ep->dwc_ep.xfer_count += status.b.bcnt;
51707 + break;
51708 + default:
51709 + DWC_DEBUGPL(DBG_PCDV, "Invalid Packet Status (0x%0x)\n",
51710 + status.b.pktsts);
51711 + break;
51712 + }
51713 +
51714 + /* Enable the Rx Status Queue Level interrupt */
51715 + DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmask.d32);
51716 + /* Clear interrupt */
51717 + gintsts.d32 = 0;
51718 + gintsts.b.rxstsqlvl = 1;
51719 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
51720 +
51721 + //DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__);
51722 + return 1;
51723 +}
51724 +
51725 +/**
51726 + * This function examines the Device IN Token Learning Queue to
51727 + * determine the EP number of the last IN token received. This
51728 + * implementation is for the Mass Storage device where there are only
51729 + * 2 IN EPs (Control-IN and BULK-IN).
51730 + *
51731 + * The EP numbers for the first six IN Tokens are in DTKNQR1 and there
51732 + * are 8 EP Numbers in each of the other possible DTKNQ Registers.
51733 + *
51734 + * @param core_if Programming view of DWC_otg controller.
51735 + *
51736 + */
51737 +static inline int get_ep_of_last_in_token(dwc_otg_core_if_t * core_if)
51738 +{
51739 + dwc_otg_device_global_regs_t *dev_global_regs =
51740 + core_if->dev_if->dev_global_regs;
51741 + const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
51742 + /* Number of Token Queue Registers */
51743 + const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
51744 + dtknq1_data_t dtknqr1;
51745 + uint32_t in_tkn_epnums[4];
51746 + int ndx = 0;
51747 + int i = 0;
51748 + volatile uint32_t *addr = &dev_global_regs->dtknqr1;
51749 + int epnum = 0;
51750 +
51751 + //DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
51752 +
51753 + /* Read the DTKNQ Registers */
51754 + for (i = 0; i < DTKNQ_REG_CNT; i++) {
51755 + in_tkn_epnums[i] = DWC_READ_REG32(addr);
51756 + DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1,
51757 + in_tkn_epnums[i]);
51758 + if (addr == &dev_global_regs->dvbusdis) {
51759 + addr = &dev_global_regs->dtknqr3_dthrctl;
51760 + } else {
51761 + ++addr;
51762 + }
51763 +
51764 + }
51765 +
51766 + /* Copy the DTKNQR1 data to the bit field. */
51767 + dtknqr1.d32 = in_tkn_epnums[0];
51768 + /* Get the EP numbers */
51769 + in_tkn_epnums[0] = dtknqr1.b.epnums0_5;
51770 + ndx = dtknqr1.b.intknwptr - 1;
51771 +
51772 + //DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx);
51773 + if (ndx == -1) {
51774 + /** @todo Find a simpler way to calculate the max
51775 + * queue position.*/
51776 + int cnt = TOKEN_Q_DEPTH;
51777 + if (TOKEN_Q_DEPTH <= 6) {
51778 + cnt = TOKEN_Q_DEPTH - 1;
51779 + } else if (TOKEN_Q_DEPTH <= 14) {
51780 + cnt = TOKEN_Q_DEPTH - 7;
51781 + } else if (TOKEN_Q_DEPTH <= 22) {
51782 + cnt = TOKEN_Q_DEPTH - 15;
51783 + } else {
51784 + cnt = TOKEN_Q_DEPTH - 23;
51785 + }
51786 + epnum = (in_tkn_epnums[DTKNQ_REG_CNT - 1] >> (cnt * 4)) & 0xF;
51787 + } else {
51788 + if (ndx <= 5) {
51789 + epnum = (in_tkn_epnums[0] >> (ndx * 4)) & 0xF;
51790 + } else if (ndx <= 13) {
51791 + ndx -= 6;
51792 + epnum = (in_tkn_epnums[1] >> (ndx * 4)) & 0xF;
51793 + } else if (ndx <= 21) {
51794 + ndx -= 14;
51795 + epnum = (in_tkn_epnums[2] >> (ndx * 4)) & 0xF;
51796 + } else if (ndx <= 29) {
51797 + ndx -= 22;
51798 + epnum = (in_tkn_epnums[3] >> (ndx * 4)) & 0xF;
51799 + }
51800 + }
51801 + //DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum);
51802 + return epnum;
51803 +}
51804 +
51805 +/**
51806 + * This interrupt occurs when the non-periodic Tx FIFO is half-empty.
51807 + * The active request is checked for the next packet to be loaded into
51808 + * the non-periodic Tx FIFO.
51809 + */
51810 +int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t * pcd)
51811 +{
51812 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
51813 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
51814 + dwc_otg_dev_in_ep_regs_t *ep_regs;
51815 + gnptxsts_data_t txstatus = {.d32 = 0 };
51816 + gintsts_data_t gintsts;
51817 +
51818 + int epnum = 0;
51819 + dwc_otg_pcd_ep_t *ep = 0;
51820 + uint32_t len = 0;
51821 + int dwords;
51822 +
51823 + /* Get the epnum from the IN Token Learning Queue. */
51824 + epnum = get_ep_of_last_in_token(core_if);
51825 + ep = get_in_ep(pcd, epnum);
51826 +
51827 + DWC_DEBUGPL(DBG_PCD, "NP TxFifo Empty: %d \n", epnum);
51828 +
51829 + ep_regs = core_if->dev_if->in_ep_regs[epnum];
51830 +
51831 + len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
51832 + if (len > ep->dwc_ep.maxpacket) {
51833 + len = ep->dwc_ep.maxpacket;
51834 + }
51835 + dwords = (len + 3) / 4;
51836 +
51837 + /* While there is space in the queue and space in the FIFO and
51838 + * More data to tranfer, Write packets to the Tx FIFO */
51839 + txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
51840 + DWC_DEBUGPL(DBG_PCDV, "b4 GNPTXSTS=0x%08x\n", txstatus.d32);
51841 +
51842 + while (txstatus.b.nptxqspcavail > 0 &&
51843 + txstatus.b.nptxfspcavail > dwords &&
51844 + ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len) {
51845 + /* Write the FIFO */
51846 + dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
51847 + len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
51848 +
51849 + if (len > ep->dwc_ep.maxpacket) {
51850 + len = ep->dwc_ep.maxpacket;
51851 + }
51852 +
51853 + dwords = (len + 3) / 4;
51854 + txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
51855 + DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n", txstatus.d32);
51856 + }
51857 +
51858 + DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n",
51859 + DWC_READ_REG32(&global_regs->gnptxsts));
51860 +
51861 + /* Clear interrupt */
51862 + gintsts.d32 = 0;
51863 + gintsts.b.nptxfempty = 1;
51864 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
51865 +
51866 + return 1;
51867 +}
51868 +
51869 +/**
51870 + * This function is called when dedicated Tx FIFO Empty interrupt occurs.
51871 + * The active request is checked for the next packet to be loaded into
51872 + * apropriate Tx FIFO.
51873 + */
51874 +static int32_t write_empty_tx_fifo(dwc_otg_pcd_t * pcd, uint32_t epnum)
51875 +{
51876 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
51877 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
51878 + dwc_otg_dev_in_ep_regs_t *ep_regs;
51879 + dtxfsts_data_t txstatus = {.d32 = 0 };
51880 + dwc_otg_pcd_ep_t *ep = 0;
51881 + uint32_t len = 0;
51882 + int dwords;
51883 +
51884 + ep = get_in_ep(pcd, epnum);
51885 +
51886 + DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
51887 +
51888 + ep_regs = core_if->dev_if->in_ep_regs[epnum];
51889 +
51890 + len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
51891 +
51892 + if (len > ep->dwc_ep.maxpacket) {
51893 + len = ep->dwc_ep.maxpacket;
51894 + }
51895 +
51896 + dwords = (len + 3) / 4;
51897 +
51898 + /* While there is space in the queue and space in the FIFO and
51899 + * More data to tranfer, Write packets to the Tx FIFO */
51900 + txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
51901 + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
51902 +
51903 + while (txstatus.b.txfspcavail > dwords &&
51904 + ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len &&
51905 + ep->dwc_ep.xfer_len != 0) {
51906 + /* Write the FIFO */
51907 + dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
51908 +
51909 + len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
51910 + if (len > ep->dwc_ep.maxpacket) {
51911 + len = ep->dwc_ep.maxpacket;
51912 + }
51913 +
51914 + dwords = (len + 3) / 4;
51915 + txstatus.d32 =
51916 + DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
51917 + DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
51918 + txstatus.d32);
51919 + }
51920 +
51921 + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
51922 + DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));
51923 +
51924 + return 1;
51925 +}
51926 +
51927 +/**
51928 + * This function is called when the Device is disconnected. It stops
51929 + * any active requests and informs the Gadget driver of the
51930 + * disconnect.
51931 + */
51932 +void dwc_otg_pcd_stop(dwc_otg_pcd_t * pcd)
51933 +{
51934 + int i, num_in_eps, num_out_eps;
51935 + dwc_otg_pcd_ep_t *ep;
51936 +
51937 + gintmsk_data_t intr_mask = {.d32 = 0 };
51938 +
51939 + DWC_SPINLOCK(pcd->lock);
51940 +
51941 + num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
51942 + num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
51943 +
51944 + DWC_DEBUGPL(DBG_PCDV, "%s() \n", __func__);
51945 + /* don't disconnect drivers more than once */
51946 + if (pcd->ep0state == EP0_DISCONNECT) {
51947 + DWC_DEBUGPL(DBG_ANY, "%s() Already Disconnected\n", __func__);
51948 + DWC_SPINUNLOCK(pcd->lock);
51949 + return;
51950 + }
51951 + pcd->ep0state = EP0_DISCONNECT;
51952 +
51953 + /* Reset the OTG state. */
51954 + dwc_otg_pcd_update_otg(pcd, 1);
51955 +
51956 + /* Disable the NP Tx Fifo Empty Interrupt. */
51957 + intr_mask.b.nptxfempty = 1;
51958 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
51959 + intr_mask.d32, 0);
51960 +
51961 + /* Flush the FIFOs */
51962 + /**@todo NGS Flush Periodic FIFOs */
51963 + dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), 0x10);
51964 + dwc_otg_flush_rx_fifo(GET_CORE_IF(pcd));
51965 +
51966 + /* prevent new request submissions, kill any outstanding requests */
51967 + ep = &pcd->ep0;
51968 + dwc_otg_request_nuke(ep);
51969 + /* prevent new request submissions, kill any outstanding requests */
51970 + for (i = 0; i < num_in_eps; i++) {
51971 + dwc_otg_pcd_ep_t *ep = &pcd->in_ep[i];
51972 + dwc_otg_request_nuke(ep);
51973 + }
51974 + /* prevent new request submissions, kill any outstanding requests */
51975 + for (i = 0; i < num_out_eps; i++) {
51976 + dwc_otg_pcd_ep_t *ep = &pcd->out_ep[i];
51977 + dwc_otg_request_nuke(ep);
51978 + }
51979 +
51980 + /* report disconnect; the driver is already quiesced */
51981 + if (pcd->fops->disconnect) {
51982 + DWC_SPINUNLOCK(pcd->lock);
51983 + pcd->fops->disconnect(pcd);
51984 + DWC_SPINLOCK(pcd->lock);
51985 + }
51986 + DWC_SPINUNLOCK(pcd->lock);
51987 +}
51988 +
51989 +/**
51990 + * This interrupt indicates that ...
51991 + */
51992 +int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t * pcd)
51993 +{
51994 + gintmsk_data_t intr_mask = {.d32 = 0 };
51995 + gintsts_data_t gintsts;
51996 +
51997 + DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "i2cintr");
51998 + intr_mask.b.i2cintr = 1;
51999 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
52000 + intr_mask.d32, 0);
52001 +
52002 + /* Clear interrupt */
52003 + gintsts.d32 = 0;
52004 + gintsts.b.i2cintr = 1;
52005 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
52006 + gintsts.d32);
52007 + return 1;
52008 +}
52009 +
52010 +/**
52011 + * This interrupt indicates that ...
52012 + */
52013 +int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t * pcd)
52014 +{
52015 + gintsts_data_t gintsts;
52016 +#if defined(VERBOSE)
52017 + DWC_PRINTF("Early Suspend Detected\n");
52018 +#endif
52019 +
52020 + /* Clear interrupt */
52021 + gintsts.d32 = 0;
52022 + gintsts.b.erlysuspend = 1;
52023 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
52024 + gintsts.d32);
52025 + return 1;
52026 +}
52027 +
52028 +/**
52029 + * This function configures EPO to receive SETUP packets.
52030 + *
52031 + * @todo NGS: Update the comments from the HW FS.
52032 + *
52033 + * -# Program the following fields in the endpoint specific registers
52034 + * for Control OUT EP 0, in order to receive a setup packet
52035 + * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
52036 + * setup packets)
52037 + * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
52038 + * to back setup packets)
52039 + * - In DMA mode, DOEPDMA0 Register with a memory address to
52040 + * store any setup packets received
52041 + *
52042 + * @param core_if Programming view of DWC_otg controller.
52043 + * @param pcd Programming view of the PCD.
52044 + */
52045 +static inline void ep0_out_start(dwc_otg_core_if_t * core_if,
52046 + dwc_otg_pcd_t * pcd)
52047 +{
52048 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
52049 + deptsiz0_data_t doeptsize0 = {.d32 = 0 };
52050 + dwc_otg_dev_dma_desc_t *dma_desc;
52051 + depctl_data_t doepctl = {.d32 = 0 };
52052 +
52053 +#ifdef VERBOSE
52054 + DWC_DEBUGPL(DBG_PCDV, "%s() doepctl0=%0x\n", __func__,
52055 + DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
52056 +#endif
52057 + if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
52058 + doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl);
52059 + if (doepctl.b.epena) {
52060 + return;
52061 + }
52062 + }
52063 +
52064 + doeptsize0.b.supcnt = 3;
52065 + doeptsize0.b.pktcnt = 1;
52066 + doeptsize0.b.xfersize = 8 * 3;
52067 +
52068 + if (core_if->dma_enable) {
52069 + if (!core_if->dma_desc_enable) {
52070 + /** put here as for Hermes mode deptisz register should not be written */
52071 + DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz,
52072 + doeptsize0.d32);
52073 +
52074 + /** @todo dma needs to handle multiple setup packets (up to 3) */
52075 + DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma,
52076 + pcd->setup_pkt_dma_handle);
52077 + } else {
52078 + dev_if->setup_desc_index =
52079 + (dev_if->setup_desc_index + 1) & 1;
52080 + dma_desc =
52081 + dev_if->setup_desc_addr[dev_if->setup_desc_index];
52082 +
52083 + /** DMA Descriptor Setup */
52084 + dma_desc->status.b.bs = BS_HOST_BUSY;
52085 + if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
52086 + dma_desc->status.b.sr = 0;
52087 + dma_desc->status.b.mtrf = 0;
52088 + }
52089 + dma_desc->status.b.l = 1;
52090 + dma_desc->status.b.ioc = 1;
52091 + dma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket;
52092 + dma_desc->buf = pcd->setup_pkt_dma_handle;
52093 + dma_desc->status.b.sts = 0;
52094 + dma_desc->status.b.bs = BS_HOST_READY;
52095 +
52096 + /** DOEPDMA0 Register write */
52097 + DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma,
52098 + dev_if->dma_setup_desc_addr
52099 + [dev_if->setup_desc_index]);
52100 + }
52101 +
52102 + } else {
52103 + /** put here as for Hermes mode deptisz register should not be written */
52104 + DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz,
52105 + doeptsize0.d32);
52106 + }
52107 +
52108 + /** DOEPCTL0 Register write cnak will be set after setup interrupt */
52109 + doepctl.d32 = 0;
52110 + doepctl.b.epena = 1;
52111 + if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
52112 + doepctl.b.cnak = 1;
52113 + DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
52114 + } else {
52115 + DWC_MODIFY_REG32(&dev_if->out_ep_regs[0]->doepctl, 0, doepctl.d32);
52116 + }
52117 +
52118 +#ifdef VERBOSE
52119 + DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
52120 + DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
52121 + DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
52122 + DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));
52123 +#endif
52124 +}
52125 +
52126 +/**
52127 + * This interrupt occurs when a USB Reset is detected. When the USB
52128 + * Reset Interrupt occurs the device state is set to DEFAULT and the
52129 + * EP0 state is set to IDLE.
52130 + * -# Set the NAK bit for all OUT endpoints (DOEPCTLn.SNAK = 1)
52131 + * -# Unmask the following interrupt bits
52132 + * - DAINTMSK.INEP0 = 1 (Control 0 IN endpoint)
52133 + * - DAINTMSK.OUTEP0 = 1 (Control 0 OUT endpoint)
52134 + * - DOEPMSK.SETUP = 1
52135 + * - DOEPMSK.XferCompl = 1
52136 + * - DIEPMSK.XferCompl = 1
52137 + * - DIEPMSK.TimeOut = 1
52138 + * -# Program the following fields in the endpoint specific registers
52139 + * for Control OUT EP 0, in order to receive a setup packet
52140 + * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
52141 + * setup packets)
52142 + * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
52143 + * to back setup packets)
52144 + * - In DMA mode, DOEPDMA0 Register with a memory address to
52145 + * store any setup packets received
52146 + * At this point, all the required initialization, except for enabling
52147 + * the control 0 OUT endpoint is done, for receiving SETUP packets.
52148 + */
52149 +int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t * pcd)
52150 +{
52151 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
52152 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
52153 + depctl_data_t doepctl = {.d32 = 0 };
52154 + depctl_data_t diepctl = {.d32 = 0 };
52155 + daint_data_t daintmsk = {.d32 = 0 };
52156 + doepmsk_data_t doepmsk = {.d32 = 0 };
52157 + diepmsk_data_t diepmsk = {.d32 = 0 };
52158 + dcfg_data_t dcfg = {.d32 = 0 };
52159 + grstctl_t resetctl = {.d32 = 0 };
52160 + dctl_data_t dctl = {.d32 = 0 };
52161 + int i = 0;
52162 + gintsts_data_t gintsts;
52163 + pcgcctl_data_t power = {.d32 = 0 };
52164 +
52165 + power.d32 = DWC_READ_REG32(core_if->pcgcctl);
52166 + if (power.b.stoppclk) {
52167 + power.d32 = 0;
52168 + power.b.stoppclk = 1;
52169 + DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
52170 +
52171 + power.b.pwrclmp = 1;
52172 + DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
52173 +
52174 + power.b.rstpdwnmodule = 1;
52175 + DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
52176 + }
52177 +
52178 + core_if->lx_state = DWC_OTG_L0;
52179 +
52180 + DWC_PRINTF("USB RESET\n");
52181 +#ifdef DWC_EN_ISOC
52182 + for (i = 1; i < 16; ++i) {
52183 + dwc_otg_pcd_ep_t *ep;
52184 + dwc_ep_t *dwc_ep;
52185 + ep = get_in_ep(pcd, i);
52186 + if (ep != 0) {
52187 + dwc_ep = &ep->dwc_ep;
52188 + dwc_ep->next_frame = 0xffffffff;
52189 + }
52190 + }
52191 +#endif /* DWC_EN_ISOC */
52192 +
52193 + /* reset the HNP settings */
52194 + dwc_otg_pcd_update_otg(pcd, 1);
52195 +
52196 + /* Clear the Remote Wakeup Signalling */
52197 + dctl.b.rmtwkupsig = 1;
52198 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
52199 +
52200 + /* Set NAK for all OUT EPs */
52201 + doepctl.b.snak = 1;
52202 + for (i = 0; i <= dev_if->num_out_eps; i++) {
52203 + DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
52204 + }
52205 +
52206 + /* Flush the NP Tx FIFO */
52207 + dwc_otg_flush_tx_fifo(core_if, 0x10);
52208 + /* Flush the Learning Queue */
52209 + resetctl.b.intknqflsh = 1;
52210 + DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
52211 +
52212 + if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
52213 + core_if->start_predict = 0;
52214 + for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) {
52215 + core_if->nextep_seq[i] = 0xff; // 0xff - EP not active
52216 + }
52217 + core_if->nextep_seq[0] = 0;
52218 + core_if->first_in_nextep_seq = 0;
52219 + diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
52220 + diepctl.b.nextep = 0;
52221 + DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
52222 +
52223 + /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */
52224 + dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
52225 + dcfg.b.epmscnt = 2;
52226 + DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
52227 +
52228 + DWC_DEBUGPL(DBG_PCDV,
52229 + "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
52230 + __func__, core_if->first_in_nextep_seq);
52231 + for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
52232 + DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
52233 + }
52234 + }
52235 +
52236 + if (core_if->multiproc_int_enable) {
52237 + daintmsk.b.inep0 = 1;
52238 + daintmsk.b.outep0 = 1;
52239 + DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk,
52240 + daintmsk.d32);
52241 +
52242 + doepmsk.b.setup = 1;
52243 + doepmsk.b.xfercompl = 1;
52244 + doepmsk.b.ahberr = 1;
52245 + doepmsk.b.epdisabled = 1;
52246 +
52247 + if ((core_if->dma_desc_enable) ||
52248 + (core_if->dma_enable
52249 + && core_if->snpsid >= OTG_CORE_REV_3_00a)) {
52250 + doepmsk.b.stsphsercvd = 1;
52251 + }
52252 + if (core_if->dma_desc_enable)
52253 + doepmsk.b.bna = 1;
52254 +/*
52255 + doepmsk.b.babble = 1;
52256 + doepmsk.b.nyet = 1;
52257 +
52258 + if (core_if->dma_enable) {
52259 + doepmsk.b.nak = 1;
52260 + }
52261 +*/
52262 + DWC_WRITE_REG32(&dev_if->dev_global_regs->doepeachintmsk[0],
52263 + doepmsk.d32);
52264 +
52265 + diepmsk.b.xfercompl = 1;
52266 + diepmsk.b.timeout = 1;
52267 + diepmsk.b.epdisabled = 1;
52268 + diepmsk.b.ahberr = 1;
52269 + diepmsk.b.intknepmis = 1;
52270 + if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
52271 + diepmsk.b.intknepmis = 0;
52272 +
52273 +/* if (core_if->dma_desc_enable) {
52274 + diepmsk.b.bna = 1;
52275 + }
52276 +*/
52277 +/*
52278 + if (core_if->dma_enable) {
52279 + diepmsk.b.nak = 1;
52280 + }
52281 +*/
52282 + DWC_WRITE_REG32(&dev_if->dev_global_regs->diepeachintmsk[0],
52283 + diepmsk.d32);
52284 + } else {
52285 + daintmsk.b.inep0 = 1;
52286 + daintmsk.b.outep0 = 1;
52287 + DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk,
52288 + daintmsk.d32);
52289 +
52290 + doepmsk.b.setup = 1;
52291 + doepmsk.b.xfercompl = 1;
52292 + doepmsk.b.ahberr = 1;
52293 + doepmsk.b.epdisabled = 1;
52294 +
52295 + if ((core_if->dma_desc_enable) ||
52296 + (core_if->dma_enable
52297 + && core_if->snpsid >= OTG_CORE_REV_3_00a)) {
52298 + doepmsk.b.stsphsercvd = 1;
52299 + }
52300 + if (core_if->dma_desc_enable)
52301 + doepmsk.b.bna = 1;
52302 + DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32);
52303 +
52304 + diepmsk.b.xfercompl = 1;
52305 + diepmsk.b.timeout = 1;
52306 + diepmsk.b.epdisabled = 1;
52307 + diepmsk.b.ahberr = 1;
52308 + if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
52309 + diepmsk.b.intknepmis = 0;
52310 +/*
52311 + if (core_if->dma_desc_enable) {
52312 + diepmsk.b.bna = 1;
52313 + }
52314 +*/
52315 +
52316 + DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32);
52317 + }
52318 +
52319 + /* Reset Device Address */
52320 + dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
52321 + dcfg.b.devaddr = 0;
52322 + DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
52323 +
52324 + /* setup EP0 to receive SETUP packets */
52325 + if (core_if->snpsid <= OTG_CORE_REV_2_94a)
52326 + ep0_out_start(core_if, pcd);
52327 +
52328 + /* Clear interrupt */
52329 + gintsts.d32 = 0;
52330 + gintsts.b.usbreset = 1;
52331 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
52332 +
52333 + return 1;
52334 +}
52335 +
52336 +/**
52337 + * Get the device speed from the device status register and convert it
52338 + * to USB speed constant.
52339 + *
52340 + * @param core_if Programming view of DWC_otg controller.
52341 + */
52342 +static int get_device_speed(dwc_otg_core_if_t * core_if)
52343 +{
52344 + dsts_data_t dsts;
52345 + int speed = 0;
52346 + dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
52347 +
52348 + switch (dsts.b.enumspd) {
52349 + case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
52350 + speed = USB_SPEED_HIGH;
52351 + break;
52352 + case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
52353 + case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
52354 + speed = USB_SPEED_FULL;
52355 + break;
52356 +
52357 + case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
52358 + speed = USB_SPEED_LOW;
52359 + break;
52360 + }
52361 +
52362 + return speed;
52363 +}
52364 +
52365 +/**
52366 + * Read the device status register and set the device speed in the
52367 + * data structure.
52368 + * Set up EP0 to receive SETUP packets by calling dwc_ep0_activate.
52369 + */
52370 +int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t * pcd)
52371 +{
52372 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
52373 + gintsts_data_t gintsts;
52374 + gusbcfg_data_t gusbcfg;
52375 + dwc_otg_core_global_regs_t *global_regs =
52376 + GET_CORE_IF(pcd)->core_global_regs;
52377 + uint8_t utmi16b, utmi8b;
52378 + int speed;
52379 + DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n");
52380 +
52381 + if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_2_60a) {
52382 + utmi16b = 6; //vahrama old value was 6;
52383 + utmi8b = 9;
52384 + } else {
52385 + utmi16b = 4;
52386 + utmi8b = 8;
52387 + }
52388 + dwc_otg_ep0_activate(GET_CORE_IF(pcd), &ep0->dwc_ep);
52389 + if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a) {
52390 + ep0_out_start(GET_CORE_IF(pcd), pcd);
52391 + }
52392 +
52393 +#ifdef DEBUG_EP0
52394 + print_ep0_state(pcd);
52395 +#endif
52396 +
52397 + if (pcd->ep0state == EP0_DISCONNECT) {
52398 + pcd->ep0state = EP0_IDLE;
52399 + } else if (pcd->ep0state == EP0_STALL) {
52400 + pcd->ep0state = EP0_IDLE;
52401 + }
52402 +
52403 + pcd->ep0state = EP0_IDLE;
52404 +
52405 + ep0->stopped = 0;
52406 +
52407 + speed = get_device_speed(GET_CORE_IF(pcd));
52408 + pcd->fops->connect(pcd, speed);
52409 +
52410 + /* Set USB turnaround time based on device speed and PHY interface. */
52411 + gusbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
52412 + if (speed == USB_SPEED_HIGH) {
52413 + if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
52414 + DWC_HWCFG2_HS_PHY_TYPE_ULPI) {
52415 + /* ULPI interface */
52416 + gusbcfg.b.usbtrdtim = 9;
52417 + }
52418 + if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
52419 + DWC_HWCFG2_HS_PHY_TYPE_UTMI) {
52420 + /* UTMI+ interface */
52421 + if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 0) {
52422 + gusbcfg.b.usbtrdtim = utmi8b;
52423 + } else if (GET_CORE_IF(pcd)->hwcfg4.
52424 + b.utmi_phy_data_width == 1) {
52425 + gusbcfg.b.usbtrdtim = utmi16b;
52426 + } else if (GET_CORE_IF(pcd)->
52427 + core_params->phy_utmi_width == 8) {
52428 + gusbcfg.b.usbtrdtim = utmi8b;
52429 + } else {
52430 + gusbcfg.b.usbtrdtim = utmi16b;
52431 + }
52432 + }
52433 + if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
52434 + DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI) {
52435 + /* UTMI+ OR ULPI interface */
52436 + if (gusbcfg.b.ulpi_utmi_sel == 1) {
52437 + /* ULPI interface */
52438 + gusbcfg.b.usbtrdtim = 9;
52439 + } else {
52440 + /* UTMI+ interface */
52441 + if (GET_CORE_IF(pcd)->
52442 + core_params->phy_utmi_width == 16) {
52443 + gusbcfg.b.usbtrdtim = utmi16b;
52444 + } else {
52445 + gusbcfg.b.usbtrdtim = utmi8b;
52446 + }
52447 + }
52448 + }
52449 + } else {
52450 + /* Full or low speed */
52451 + gusbcfg.b.usbtrdtim = 9;
52452 + }
52453 + DWC_WRITE_REG32(&global_regs->gusbcfg, gusbcfg.d32);
52454 +
52455 + /* Clear interrupt */
52456 + gintsts.d32 = 0;
52457 + gintsts.b.enumdone = 1;
52458 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
52459 + gintsts.d32);
52460 + return 1;
52461 +}
52462 +
52463 +/**
52464 + * This interrupt indicates that the ISO OUT Packet was dropped due to
52465 + * Rx FIFO full or Rx Status Queue Full. If this interrupt occurs
52466 + * read all the data from the Rx FIFO.
52467 + */
52468 +int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t * pcd)
52469 +{
52470 + gintmsk_data_t intr_mask = {.d32 = 0 };
52471 + gintsts_data_t gintsts;
52472 +
52473 + DWC_WARN("INTERRUPT Handler not implemented for %s\n",
52474 + "ISOC Out Dropped");
52475 +
52476 + intr_mask.b.isooutdrop = 1;
52477 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
52478 + intr_mask.d32, 0);
52479 +
52480 + /* Clear interrupt */
52481 + gintsts.d32 = 0;
52482 + gintsts.b.isooutdrop = 1;
52483 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
52484 + gintsts.d32);
52485 +
52486 + return 1;
52487 +}
52488 +
52489 +/**
52490 + * This interrupt indicates the end of the portion of the micro-frame
52491 + * for periodic transactions. If there is a periodic transaction for
52492 + * the next frame, load the packets into the EP periodic Tx FIFO.
52493 + */
52494 +int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t * pcd)
52495 +{
52496 + gintmsk_data_t intr_mask = {.d32 = 0 };
52497 + gintsts_data_t gintsts;
52498 + DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "EOP");
52499 +
52500 + intr_mask.b.eopframe = 1;
52501 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
52502 + intr_mask.d32, 0);
52503 +
52504 + /* Clear interrupt */
52505 + gintsts.d32 = 0;
52506 + gintsts.b.eopframe = 1;
52507 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
52508 + gintsts.d32);
52509 +
52510 + return 1;
52511 +}
52512 +
52513 +/**
52514 + * This interrupt indicates that EP of the packet on the top of the
52515 + * non-periodic Tx FIFO does not match EP of the IN Token received.
52516 + *
52517 + * The "Device IN Token Queue" Registers are read to determine the
52518 + * order the IN Tokens have been received. The non-periodic Tx FIFO
52519 + * is flushed, so it can be reloaded in the order seen in the IN Token
52520 + * Queue.
52521 + */
52522 +int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_pcd_t * pcd)
52523 +{
52524 + gintsts_data_t gintsts;
52525 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
52526 + dctl_data_t dctl;
52527 + gintmsk_data_t intr_mask = {.d32 = 0 };
52528 +
52529 + if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) {
52530 + core_if->start_predict = 1;
52531 +
52532 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
52533 +
52534 + gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
52535 + if (!gintsts.b.ginnakeff) {
52536 + /* Disable EP Mismatch interrupt */
52537 + intr_mask.d32 = 0;
52538 + intr_mask.b.epmismatch = 1;
52539 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
52540 + /* Enable the Global IN NAK Effective Interrupt */
52541 + intr_mask.d32 = 0;
52542 + intr_mask.b.ginnakeff = 1;
52543 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);
52544 + /* Set the global non-periodic IN NAK handshake */
52545 + dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
52546 + dctl.b.sgnpinnak = 1;
52547 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
52548 + } else {
52549 + DWC_PRINTF("gintsts.b.ginnakeff = 1! dctl.b.sgnpinnak not set\n");
52550 + }
52551 + /* Disabling of all EP's will be done in dwc_otg_pcd_handle_in_nak_effective()
52552 + * handler after Global IN NAK Effective interrupt will be asserted */
52553 + }
52554 + /* Clear interrupt */
52555 + gintsts.d32 = 0;
52556 + gintsts.b.epmismatch = 1;
52557 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
52558 +
52559 + return 1;
52560 +}
52561 +
52562 +/**
52563 + * This interrupt is valid only in DMA mode. This interrupt indicates that the
52564 + * core has stopped fetching data for IN endpoints due to the unavailability of
52565 + * TxFIFO space or Request Queue space. This interrupt is used by the
52566 + * application for an endpoint mismatch algorithm.
52567 + *
52568 + * @param pcd The PCD
52569 + */
52570 +int32_t dwc_otg_pcd_handle_ep_fetsusp_intr(dwc_otg_pcd_t * pcd)
52571 +{
52572 + gintsts_data_t gintsts;
52573 + gintmsk_data_t gintmsk_data;
52574 + dctl_data_t dctl;
52575 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
52576 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
52577 +
52578 + /* Clear the global non-periodic IN NAK handshake */
52579 + dctl.d32 = 0;
52580 + dctl.b.cgnpinnak = 1;
52581 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
52582 +
52583 + /* Mask GINTSTS.FETSUSP interrupt */
52584 + gintmsk_data.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
52585 + gintmsk_data.b.fetsusp = 0;
52586 + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_data.d32);
52587 +
52588 + /* Clear interrupt */
52589 + gintsts.d32 = 0;
52590 + gintsts.b.fetsusp = 1;
52591 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
52592 +
52593 + return 1;
52594 +}
52595 +/**
52596 + * This funcion stalls EP0.
52597 + */
52598 +static inline void ep0_do_stall(dwc_otg_pcd_t * pcd, const int err_val)
52599 +{
52600 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
52601 + usb_device_request_t *ctrl = &pcd->setup_pkt->req;
52602 + DWC_WARN("req %02x.%02x protocol STALL; err %d\n",
52603 + ctrl->bmRequestType, ctrl->bRequest, err_val);
52604 +
52605 + ep0->dwc_ep.is_in = 1;
52606 + dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep0->dwc_ep);
52607 + pcd->ep0.stopped = 1;
52608 + pcd->ep0state = EP0_IDLE;
52609 + ep0_out_start(GET_CORE_IF(pcd), pcd);
52610 +}
52611 +
52612 +/**
52613 + * This functions delegates the setup command to the gadget driver.
52614 + */
52615 +static inline void do_gadget_setup(dwc_otg_pcd_t * pcd,
52616 + usb_device_request_t * ctrl)
52617 +{
52618 + int ret = 0;
52619 + DWC_SPINUNLOCK(pcd->lock);
52620 + ret = pcd->fops->setup(pcd, (uint8_t *) ctrl);
52621 + DWC_SPINLOCK(pcd->lock);
52622 + if (ret < 0) {
52623 + ep0_do_stall(pcd, ret);
52624 + }
52625 +
52626 + /** @todo This is a g_file_storage gadget driver specific
52627 + * workaround: a DELAYED_STATUS result from the fsg_setup
52628 + * routine will result in the gadget queueing a EP0 IN status
52629 + * phase for a two-stage control transfer. Exactly the same as
52630 + * a SET_CONFIGURATION/SET_INTERFACE except that this is a class
52631 + * specific request. Need a generic way to know when the gadget
52632 + * driver will queue the status phase. Can we assume when we
52633 + * call the gadget driver setup() function that it will always
52634 + * queue and require the following flag? Need to look into
52635 + * this.
52636 + */
52637 +
52638 + if (ret == 256 + 999) {
52639 + pcd->request_config = 1;
52640 + }
52641 +}
52642 +
52643 +#ifdef DWC_UTE_CFI
52644 +/**
52645 + * This functions delegates the CFI setup commands to the gadget driver.
52646 + * This function will return a negative value to indicate a failure.
52647 + */
52648 +static inline int cfi_gadget_setup(dwc_otg_pcd_t * pcd,
52649 + struct cfi_usb_ctrlrequest *ctrl_req)
52650 +{
52651 + int ret = 0;
52652 +
52653 + if (pcd->fops && pcd->fops->cfi_setup) {
52654 + DWC_SPINUNLOCK(pcd->lock);
52655 + ret = pcd->fops->cfi_setup(pcd, ctrl_req);
52656 + DWC_SPINLOCK(pcd->lock);
52657 + if (ret < 0) {
52658 + ep0_do_stall(pcd, ret);
52659 + return ret;
52660 + }
52661 + }
52662 +
52663 + return ret;
52664 +}
52665 +#endif
52666 +
52667 +/**
52668 + * This function starts the Zero-Length Packet for the IN status phase
52669 + * of a 2 stage control transfer.
52670 + */
52671 +static inline void do_setup_in_status_phase(dwc_otg_pcd_t * pcd)
52672 +{
52673 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
52674 + if (pcd->ep0state == EP0_STALL) {
52675 + return;
52676 + }
52677 +
52678 + pcd->ep0state = EP0_IN_STATUS_PHASE;
52679 +
52680 + /* Prepare for more SETUP Packets */
52681 + DWC_DEBUGPL(DBG_PCD, "EP0 IN ZLP\n");
52682 + if ((GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a)
52683 + && (pcd->core_if->dma_desc_enable)
52684 + && (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len)) {
52685 + DWC_DEBUGPL(DBG_PCDV,
52686 + "Data terminated wait next packet in out_desc_addr\n");
52687 + pcd->backup_buf = phys_to_virt(ep0->dwc_ep.dma_addr);
52688 + pcd->data_terminated = 1;
52689 + }
52690 + ep0->dwc_ep.xfer_len = 0;
52691 + ep0->dwc_ep.xfer_count = 0;
52692 + ep0->dwc_ep.is_in = 1;
52693 + ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
52694 + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
52695 +
52696 + /* Prepare for more SETUP Packets */
52697 + //ep0_out_start(GET_CORE_IF(pcd), pcd);
52698 +}
52699 +
52700 +/**
52701 + * This function starts the Zero-Length Packet for the OUT status phase
52702 + * of a 2 stage control transfer.
52703 + */
52704 +static inline void do_setup_out_status_phase(dwc_otg_pcd_t * pcd)
52705 +{
52706 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
52707 + if (pcd->ep0state == EP0_STALL) {
52708 + DWC_DEBUGPL(DBG_PCD, "EP0 STALLED\n");
52709 + return;
52710 + }
52711 + pcd->ep0state = EP0_OUT_STATUS_PHASE;
52712 +
52713 + DWC_DEBUGPL(DBG_PCD, "EP0 OUT ZLP\n");
52714 + ep0->dwc_ep.xfer_len = 0;
52715 + ep0->dwc_ep.xfer_count = 0;
52716 + ep0->dwc_ep.is_in = 0;
52717 + ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
52718 + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
52719 +
52720 + /* Prepare for more SETUP Packets */
52721 + if (GET_CORE_IF(pcd)->dma_enable == 0) {
52722 + ep0_out_start(GET_CORE_IF(pcd), pcd);
52723 + }
52724 +}
52725 +
52726 +/**
52727 + * Clear the EP halt (STALL) and if pending requests start the
52728 + * transfer.
52729 + */
52730 +static inline void pcd_clear_halt(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
52731 +{
52732 + if (ep->dwc_ep.stall_clear_flag == 0)
52733 + dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
52734 +
52735 + /* Reactive the EP */
52736 + dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
52737 + if (ep->stopped) {
52738 + ep->stopped = 0;
52739 + /* If there is a request in the EP queue start it */
52740 +
52741 + /** @todo FIXME: this causes an EP mismatch in DMA mode.
52742 + * epmismatch not yet implemented. */
52743 +
52744 + /*
52745 + * Above fixme is solved by implmenting a tasklet to call the
52746 + * start_next_request(), outside of interrupt context at some
52747 + * time after the current time, after a clear-halt setup packet.
52748 + * Still need to implement ep mismatch in the future if a gadget
52749 + * ever uses more than one endpoint at once
52750 + */
52751 + ep->queue_sof = 1;
52752 + DWC_TASK_SCHEDULE(pcd->start_xfer_tasklet);
52753 + }
52754 + /* Start Control Status Phase */
52755 + do_setup_in_status_phase(pcd);
52756 +}
52757 +
52758 +/**
52759 + * This function is called when the SET_FEATURE TEST_MODE Setup packet
52760 + * is sent from the host. The Device Control register is written with
52761 + * the Test Mode bits set to the specified Test Mode. This is done as
52762 + * a tasklet so that the "Status" phase of the control transfer
52763 + * completes before transmitting the TEST packets.
52764 + *
52765 + * @todo This has not been tested since the tasklet struct was put
52766 + * into the PCD struct!
52767 + *
52768 + */
52769 +void do_test_mode(void *data)
52770 +{
52771 + dctl_data_t dctl;
52772 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
52773 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
52774 + int test_mode = pcd->test_mode;
52775 +
52776 +// DWC_WARN("%s() has not been tested since being rewritten!\n", __func__);
52777 +
52778 + dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
52779 + switch (test_mode) {
52780 + case 1: // TEST_J
52781 + dctl.b.tstctl = 1;
52782 + break;
52783 +
52784 + case 2: // TEST_K
52785 + dctl.b.tstctl = 2;
52786 + break;
52787 +
52788 + case 3: // TEST_SE0_NAK
52789 + dctl.b.tstctl = 3;
52790 + break;
52791 +
52792 + case 4: // TEST_PACKET
52793 + dctl.b.tstctl = 4;
52794 + break;
52795 +
52796 + case 5: // TEST_FORCE_ENABLE
52797 + dctl.b.tstctl = 5;
52798 + break;
52799 + }
52800 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
52801 +}
52802 +
52803 +/**
52804 + * This function process the GET_STATUS Setup Commands.
52805 + */
52806 +static inline void do_get_status(dwc_otg_pcd_t * pcd)
52807 +{
52808 + usb_device_request_t ctrl = pcd->setup_pkt->req;
52809 + dwc_otg_pcd_ep_t *ep;
52810 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
52811 + uint16_t *status = pcd->status_buf;
52812 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
52813 +
52814 +#ifdef DEBUG_EP0
52815 + DWC_DEBUGPL(DBG_PCD,
52816 + "GET_STATUS %02x.%02x v%04x i%04x l%04x\n",
52817 + ctrl.bmRequestType, ctrl.bRequest,
52818 + UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
52819 + UGETW(ctrl.wLength));
52820 +#endif
52821 +
52822 + switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
52823 + case UT_DEVICE:
52824 + if(UGETW(ctrl.wIndex) == 0xF000) { /* OTG Status selector */
52825 + DWC_PRINTF("wIndex - %d\n", UGETW(ctrl.wIndex));
52826 + DWC_PRINTF("OTG VERSION - %d\n", core_if->otg_ver);
52827 + DWC_PRINTF("OTG CAP - %d, %d\n",
52828 + core_if->core_params->otg_cap,
52829 + DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
52830 + if (core_if->otg_ver == 1
52831 + && core_if->core_params->otg_cap ==
52832 + DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
52833 + uint8_t *otgsts = (uint8_t*)pcd->status_buf;
52834 + *otgsts = (core_if->otg_sts & 0x1);
52835 + pcd->ep0_pending = 1;
52836 + ep0->dwc_ep.start_xfer_buff =
52837 + (uint8_t *) otgsts;
52838 + ep0->dwc_ep.xfer_buff = (uint8_t *) otgsts;
52839 + ep0->dwc_ep.dma_addr =
52840 + pcd->status_buf_dma_handle;
52841 + ep0->dwc_ep.xfer_len = 1;
52842 + ep0->dwc_ep.xfer_count = 0;
52843 + ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
52844 + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd),
52845 + &ep0->dwc_ep);
52846 + return;
52847 + } else {
52848 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
52849 + return;
52850 + }
52851 + break;
52852 + } else {
52853 + *status = 0x1; /* Self powered */
52854 + *status |= pcd->remote_wakeup_enable << 1;
52855 + break;
52856 + }
52857 + case UT_INTERFACE:
52858 + *status = 0;
52859 + break;
52860 +
52861 + case UT_ENDPOINT:
52862 + ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
52863 + if (ep == 0 || UGETW(ctrl.wLength) > 2) {
52864 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
52865 + return;
52866 + }
52867 + /** @todo check for EP stall */
52868 + *status = ep->stopped;
52869 + break;
52870 + }
52871 + pcd->ep0_pending = 1;
52872 + ep0->dwc_ep.start_xfer_buff = (uint8_t *) status;
52873 + ep0->dwc_ep.xfer_buff = (uint8_t *) status;
52874 + ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle;
52875 + ep0->dwc_ep.xfer_len = 2;
52876 + ep0->dwc_ep.xfer_count = 0;
52877 + ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
52878 + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
52879 +}
52880 +
52881 +/**
52882 + * This function process the SET_FEATURE Setup Commands.
52883 + */
52884 +static inline void do_set_feature(dwc_otg_pcd_t * pcd)
52885 +{
52886 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
52887 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
52888 + usb_device_request_t ctrl = pcd->setup_pkt->req;
52889 + dwc_otg_pcd_ep_t *ep = 0;
52890 + int32_t otg_cap_param = core_if->core_params->otg_cap;
52891 + gotgctl_data_t gotgctl = {.d32 = 0 };
52892 +
52893 + DWC_DEBUGPL(DBG_PCD, "SET_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
52894 + ctrl.bmRequestType, ctrl.bRequest,
52895 + UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
52896 + UGETW(ctrl.wLength));
52897 + DWC_DEBUGPL(DBG_PCD, "otg_cap=%d\n", otg_cap_param);
52898 +
52899 + switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
52900 + case UT_DEVICE:
52901 + switch (UGETW(ctrl.wValue)) {
52902 + case UF_DEVICE_REMOTE_WAKEUP:
52903 + pcd->remote_wakeup_enable = 1;
52904 + break;
52905 +
52906 + case UF_TEST_MODE:
52907 + /* Setup the Test Mode tasklet to do the Test
52908 + * Packet generation after the SETUP Status
52909 + * phase has completed. */
52910 +
52911 + /** @todo This has not been tested since the
52912 + * tasklet struct was put into the PCD
52913 + * struct! */
52914 + pcd->test_mode = UGETW(ctrl.wIndex) >> 8;
52915 + DWC_TASK_SCHEDULE(pcd->test_mode_tasklet);
52916 + break;
52917 +
52918 + case UF_DEVICE_B_HNP_ENABLE:
52919 + DWC_DEBUGPL(DBG_PCDV,
52920 + "SET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
52921 +
52922 + /* dev may initiate HNP */
52923 + if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
52924 + pcd->b_hnp_enable = 1;
52925 + dwc_otg_pcd_update_otg(pcd, 0);
52926 + DWC_DEBUGPL(DBG_PCD, "Request B HNP\n");
52927 + /**@todo Is the gotgctl.devhnpen cleared
52928 + * by a USB Reset? */
52929 + gotgctl.b.devhnpen = 1;
52930 + gotgctl.b.hnpreq = 1;
52931 + DWC_WRITE_REG32(&global_regs->gotgctl,
52932 + gotgctl.d32);
52933 + } else {
52934 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
52935 + return;
52936 + }
52937 + break;
52938 +
52939 + case UF_DEVICE_A_HNP_SUPPORT:
52940 + /* RH port supports HNP */
52941 + DWC_DEBUGPL(DBG_PCDV,
52942 + "SET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\n");
52943 + if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
52944 + pcd->a_hnp_support = 1;
52945 + dwc_otg_pcd_update_otg(pcd, 0);
52946 + } else {
52947 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
52948 + return;
52949 + }
52950 + break;
52951 +
52952 + case UF_DEVICE_A_ALT_HNP_SUPPORT:
52953 + /* other RH port does */
52954 + DWC_DEBUGPL(DBG_PCDV,
52955 + "SET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
52956 + if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
52957 + pcd->a_alt_hnp_support = 1;
52958 + dwc_otg_pcd_update_otg(pcd, 0);
52959 + } else {
52960 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
52961 + return;
52962 + }
52963 + break;
52964 +
52965 + default:
52966 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
52967 + return;
52968 +
52969 + }
52970 + do_setup_in_status_phase(pcd);
52971 + break;
52972 +
52973 + case UT_INTERFACE:
52974 + do_gadget_setup(pcd, &ctrl);
52975 + break;
52976 +
52977 + case UT_ENDPOINT:
52978 + if (UGETW(ctrl.wValue) == UF_ENDPOINT_HALT) {
52979 + ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
52980 + if (ep == 0) {
52981 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
52982 + return;
52983 + }
52984 + ep->stopped = 1;
52985 + dwc_otg_ep_set_stall(core_if, &ep->dwc_ep);
52986 + }
52987 + do_setup_in_status_phase(pcd);
52988 + break;
52989 + }
52990 +}
52991 +
52992 +/**
52993 + * This function process the CLEAR_FEATURE Setup Commands.
52994 + */
52995 +static inline void do_clear_feature(dwc_otg_pcd_t * pcd)
52996 +{
52997 + usb_device_request_t ctrl = pcd->setup_pkt->req;
52998 + dwc_otg_pcd_ep_t *ep = 0;
52999 +
53000 + DWC_DEBUGPL(DBG_PCD,
53001 + "CLEAR_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
53002 + ctrl.bmRequestType, ctrl.bRequest,
53003 + UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
53004 + UGETW(ctrl.wLength));
53005 +
53006 + switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
53007 + case UT_DEVICE:
53008 + switch (UGETW(ctrl.wValue)) {
53009 + case UF_DEVICE_REMOTE_WAKEUP:
53010 + pcd->remote_wakeup_enable = 0;
53011 + break;
53012 +
53013 + case UF_TEST_MODE:
53014 + /** @todo Add CLEAR_FEATURE for TEST modes. */
53015 + break;
53016 +
53017 + default:
53018 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
53019 + return;
53020 + }
53021 + do_setup_in_status_phase(pcd);
53022 + break;
53023 +
53024 + case UT_ENDPOINT:
53025 + ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
53026 + if (ep == 0) {
53027 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
53028 + return;
53029 + }
53030 +
53031 + pcd_clear_halt(pcd, ep);
53032 +
53033 + break;
53034 + }
53035 +}
53036 +
53037 +/**
53038 + * This function process the SET_ADDRESS Setup Commands.
53039 + */
53040 +static inline void do_set_address(dwc_otg_pcd_t * pcd)
53041 +{
53042 + dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
53043 + usb_device_request_t ctrl = pcd->setup_pkt->req;
53044 +
53045 + if (ctrl.bmRequestType == UT_DEVICE) {
53046 + dcfg_data_t dcfg = {.d32 = 0 };
53047 +
53048 +#ifdef DEBUG_EP0
53049 +// DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue);
53050 +#endif
53051 + dcfg.b.devaddr = UGETW(ctrl.wValue);
53052 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32);
53053 + do_setup_in_status_phase(pcd);
53054 + }
53055 +}
53056 +
53057 +/**
53058 + * This function processes SETUP commands. In Linux, the USB Command
53059 + * processing is done in two places - the first being the PCD and the
53060 + * second in the Gadget Driver (for example, the File-Backed Storage
53061 + * Gadget Driver).
53062 + *
53063 + * <table>
53064 + * <tr><td>Command </td><td>Driver </td><td>Description</td></tr>
53065 + *
53066 + * <tr><td>GET_STATUS </td><td>PCD </td><td>Command is processed as
53067 + * defined in chapter 9 of the USB 2.0 Specification chapter 9
53068 + * </td></tr>
53069 + *
53070 + * <tr><td>CLEAR_FEATURE </td><td>PCD </td><td>The Device and Endpoint
53071 + * requests are the ENDPOINT_HALT feature is procesed, all others the
53072 + * interface requests are ignored.</td></tr>
53073 + *
53074 + * <tr><td>SET_FEATURE </td><td>PCD </td><td>The Device and Endpoint
53075 + * requests are processed by the PCD. Interface requests are passed
53076 + * to the Gadget Driver.</td></tr>
53077 + *
53078 + * <tr><td>SET_ADDRESS </td><td>PCD </td><td>Program the DCFG reg,
53079 + * with device address received </td></tr>
53080 + *
53081 + * <tr><td>GET_DESCRIPTOR </td><td>Gadget Driver </td><td>Return the
53082 + * requested descriptor</td></tr>
53083 + *
53084 + * <tr><td>SET_DESCRIPTOR </td><td>Gadget Driver </td><td>Optional -
53085 + * not implemented by any of the existing Gadget Drivers.</td></tr>
53086 + *
53087 + * <tr><td>SET_CONFIGURATION </td><td>Gadget Driver </td><td>Disable
53088 + * all EPs and enable EPs for new configuration.</td></tr>
53089 + *
53090 + * <tr><td>GET_CONFIGURATION </td><td>Gadget Driver </td><td>Return
53091 + * the current configuration</td></tr>
53092 + *
53093 + * <tr><td>SET_INTERFACE </td><td>Gadget Driver </td><td>Disable all
53094 + * EPs and enable EPs for new configuration.</td></tr>
53095 + *
53096 + * <tr><td>GET_INTERFACE </td><td>Gadget Driver </td><td>Return the
53097 + * current interface.</td></tr>
53098 + *
53099 + * <tr><td>SYNC_FRAME </td><td>PCD </td><td>Display debug
53100 + * message.</td></tr>
53101 + * </table>
53102 + *
53103 + * When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are
53104 + * processed by pcd_setup. Calling the Function Driver's setup function from
53105 + * pcd_setup processes the gadget SETUP commands.
53106 + */
53107 +static inline void pcd_setup(dwc_otg_pcd_t * pcd)
53108 +{
53109 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
53110 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
53111 + usb_device_request_t ctrl = pcd->setup_pkt->req;
53112 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
53113 +
53114 + deptsiz0_data_t doeptsize0 = {.d32 = 0 };
53115 +
53116 +#ifdef DWC_UTE_CFI
53117 + int retval = 0;
53118 + struct cfi_usb_ctrlrequest cfi_req;
53119 +#endif
53120 +
53121 + doeptsize0.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doeptsiz);
53122 +
53123 + /** In BDMA more then 1 setup packet is not supported till 3.00a */
53124 + if (core_if->dma_enable && core_if->dma_desc_enable == 0
53125 + && (doeptsize0.b.supcnt < 2)
53126 + && (core_if->snpsid < OTG_CORE_REV_2_94a)) {
53127 + DWC_ERROR
53128 + ("\n\n----------- CANNOT handle > 1 setup packet in DMA mode\n\n");
53129 + }
53130 + if ((core_if->snpsid >= OTG_CORE_REV_3_00a)
53131 + && (core_if->dma_enable == 1) && (core_if->dma_desc_enable == 0)) {
53132 + ctrl =
53133 + (pcd->setup_pkt +
53134 + (3 - doeptsize0.b.supcnt - 1 +
53135 + ep0->dwc_ep.stp_rollover))->req;
53136 + }
53137 +#ifdef DEBUG_EP0
53138 + DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n",
53139 + ctrl.bmRequestType, ctrl.bRequest,
53140 + UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
53141 + UGETW(ctrl.wLength));
53142 +#endif
53143 +
53144 + /* Clean up the request queue */
53145 + dwc_otg_request_nuke(ep0);
53146 + ep0->stopped = 0;
53147 +
53148 + if (ctrl.bmRequestType & UE_DIR_IN) {
53149 + ep0->dwc_ep.is_in = 1;
53150 + pcd->ep0state = EP0_IN_DATA_PHASE;
53151 + } else {
53152 + ep0->dwc_ep.is_in = 0;
53153 + pcd->ep0state = EP0_OUT_DATA_PHASE;
53154 + }
53155 +
53156 + if (UGETW(ctrl.wLength) == 0) {
53157 + ep0->dwc_ep.is_in = 1;
53158 + pcd->ep0state = EP0_IN_STATUS_PHASE;
53159 + }
53160 +
53161 + if (UT_GET_TYPE(ctrl.bmRequestType) != UT_STANDARD) {
53162 +
53163 +#ifdef DWC_UTE_CFI
53164 + DWC_MEMCPY(&cfi_req, &ctrl, sizeof(usb_device_request_t));
53165 +
53166 + //printk(KERN_ALERT "CFI: req_type=0x%02x; req=0x%02x\n",
53167 + ctrl.bRequestType, ctrl.bRequest);
53168 + if (UT_GET_TYPE(cfi_req.bRequestType) == UT_VENDOR) {
53169 + if (cfi_req.bRequest > 0xB0 && cfi_req.bRequest < 0xBF) {
53170 + retval = cfi_setup(pcd, &cfi_req);
53171 + if (retval < 0) {
53172 + ep0_do_stall(pcd, retval);
53173 + pcd->ep0_pending = 0;
53174 + return;
53175 + }
53176 +
53177 + /* if need gadget setup then call it and check the retval */
53178 + if (pcd->cfi->need_gadget_att) {
53179 + retval =
53180 + cfi_gadget_setup(pcd,
53181 + &pcd->
53182 + cfi->ctrl_req);
53183 + if (retval < 0) {
53184 + pcd->ep0_pending = 0;
53185 + return;
53186 + }
53187 + }
53188 +
53189 + if (pcd->cfi->need_status_in_complete) {
53190 + do_setup_in_status_phase(pcd);
53191 + }
53192 + return;
53193 + }
53194 + }
53195 +#endif
53196 +
53197 + /* handle non-standard (class/vendor) requests in the gadget driver */
53198 + do_gadget_setup(pcd, &ctrl);
53199 + return;
53200 + }
53201 +
53202 + /** @todo NGS: Handle bad setup packet? */
53203 +
53204 +///////////////////////////////////////////
53205 +//// --- Standard Request handling --- ////
53206 +
53207 + switch (ctrl.bRequest) {
53208 + case UR_GET_STATUS:
53209 + do_get_status(pcd);
53210 + break;
53211 +
53212 + case UR_CLEAR_FEATURE:
53213 + do_clear_feature(pcd);
53214 + break;
53215 +
53216 + case UR_SET_FEATURE:
53217 + do_set_feature(pcd);
53218 + break;
53219 +
53220 + case UR_SET_ADDRESS:
53221 + do_set_address(pcd);
53222 + break;
53223 +
53224 + case UR_SET_INTERFACE:
53225 + case UR_SET_CONFIG:
53226 +// _pcd->request_config = 1; /* Configuration changed */
53227 + do_gadget_setup(pcd, &ctrl);
53228 + break;
53229 +
53230 + case UR_SYNCH_FRAME:
53231 + do_gadget_setup(pcd, &ctrl);
53232 + break;
53233 +
53234 + default:
53235 + /* Call the Gadget Driver's setup functions */
53236 + do_gadget_setup(pcd, &ctrl);
53237 + break;
53238 + }
53239 +}
53240 +
53241 +/**
53242 + * This function completes the ep0 control transfer.
53243 + */
53244 +static int32_t ep0_complete_request(dwc_otg_pcd_ep_t * ep)
53245 +{
53246 + dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
53247 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
53248 + dwc_otg_dev_in_ep_regs_t *in_ep_regs =
53249 + dev_if->in_ep_regs[ep->dwc_ep.num];
53250 +#ifdef DEBUG_EP0
53251 + dwc_otg_dev_out_ep_regs_t *out_ep_regs =
53252 + dev_if->out_ep_regs[ep->dwc_ep.num];
53253 +#endif
53254 + deptsiz0_data_t deptsiz;
53255 + dev_dma_desc_sts_t desc_sts;
53256 + dwc_otg_pcd_request_t *req;
53257 + int is_last = 0;
53258 + dwc_otg_pcd_t *pcd = ep->pcd;
53259 +
53260 +#ifdef DWC_UTE_CFI
53261 + struct cfi_usb_ctrlrequest *ctrlreq;
53262 + int retval = -DWC_E_NOT_SUPPORTED;
53263 +#endif
53264 +
53265 + desc_sts.b.bytes = 0;
53266 +
53267 + if (pcd->ep0_pending && DWC_CIRCLEQ_EMPTY(&ep->queue)) {
53268 + if (ep->dwc_ep.is_in) {
53269 +#ifdef DEBUG_EP0
53270 + DWC_DEBUGPL(DBG_PCDV, "Do setup OUT status phase\n");
53271 +#endif
53272 + do_setup_out_status_phase(pcd);
53273 + } else {
53274 +#ifdef DEBUG_EP0
53275 + DWC_DEBUGPL(DBG_PCDV, "Do setup IN status phase\n");
53276 +#endif
53277 +
53278 +#ifdef DWC_UTE_CFI
53279 + ctrlreq = &pcd->cfi->ctrl_req;
53280 +
53281 + if (UT_GET_TYPE(ctrlreq->bRequestType) == UT_VENDOR) {
53282 + if (ctrlreq->bRequest > 0xB0
53283 + && ctrlreq->bRequest < 0xBF) {
53284 +
53285 + /* Return if the PCD failed to handle the request */
53286 + if ((retval =
53287 + pcd->cfi->ops.
53288 + ctrl_write_complete(pcd->cfi,
53289 + pcd)) < 0) {
53290 + CFI_INFO
53291 + ("ERROR setting a new value in the PCD(%d)\n",
53292 + retval);
53293 + ep0_do_stall(pcd, retval);
53294 + pcd->ep0_pending = 0;
53295 + return 0;
53296 + }
53297 +
53298 + /* If the gadget needs to be notified on the request */
53299 + if (pcd->cfi->need_gadget_att == 1) {
53300 + //retval = do_gadget_setup(pcd, &pcd->cfi->ctrl_req);
53301 + retval =
53302 + cfi_gadget_setup(pcd,
53303 + &pcd->cfi->
53304 + ctrl_req);
53305 +
53306 + /* Return from the function if the gadget failed to process
53307 + * the request properly - this should never happen !!!
53308 + */
53309 + if (retval < 0) {
53310 + CFI_INFO
53311 + ("ERROR setting a new value in the gadget(%d)\n",
53312 + retval);
53313 + pcd->ep0_pending = 0;
53314 + return 0;
53315 + }
53316 + }
53317 +
53318 + CFI_INFO("%s: RETVAL=%d\n", __func__,
53319 + retval);
53320 + /* If we hit here then the PCD and the gadget has properly
53321 + * handled the request - so send the ZLP IN to the host.
53322 + */
53323 + /* @todo: MAS - decide whether we need to start the setup
53324 + * stage based on the need_setup value of the cfi object
53325 + */
53326 + do_setup_in_status_phase(pcd);
53327 + pcd->ep0_pending = 0;
53328 + return 1;
53329 + }
53330 + }
53331 +#endif
53332 +
53333 + do_setup_in_status_phase(pcd);
53334 + }
53335 + pcd->ep0_pending = 0;
53336 + return 1;
53337 + }
53338 +
53339 + if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
53340 + return 0;
53341 + }
53342 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
53343 +
53344 + if (pcd->ep0state == EP0_OUT_STATUS_PHASE
53345 + || pcd->ep0state == EP0_IN_STATUS_PHASE) {
53346 + is_last = 1;
53347 + } else if (ep->dwc_ep.is_in) {
53348 + deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz);
53349 + if (core_if->dma_desc_enable != 0)
53350 + desc_sts = dev_if->in_desc_addr->status;
53351 +#ifdef DEBUG_EP0
53352 + DWC_DEBUGPL(DBG_PCDV, "%d len=%d xfersize=%d pktcnt=%d\n",
53353 + ep->dwc_ep.num, ep->dwc_ep.xfer_len,
53354 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
53355 +#endif
53356 +
53357 + if (((core_if->dma_desc_enable == 0)
53358 + && (deptsiz.b.xfersize == 0))
53359 + || ((core_if->dma_desc_enable != 0)
53360 + && (desc_sts.b.bytes == 0))) {
53361 + req->actual = ep->dwc_ep.xfer_count;
53362 + /* Is a Zero Len Packet needed? */
53363 + if (req->sent_zlp) {
53364 +#ifdef DEBUG_EP0
53365 + DWC_DEBUGPL(DBG_PCD, "Setup Rx ZLP\n");
53366 +#endif
53367 + req->sent_zlp = 0;
53368 + }
53369 + do_setup_out_status_phase(pcd);
53370 + }
53371 + } else {
53372 + /* ep0-OUT */
53373 +#ifdef DEBUG_EP0
53374 + deptsiz.d32 = DWC_READ_REG32(&out_ep_regs->doeptsiz);
53375 + DWC_DEBUGPL(DBG_PCDV, "%d len=%d xsize=%d pktcnt=%d\n",
53376 + ep->dwc_ep.num, ep->dwc_ep.xfer_len,
53377 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
53378 +#endif
53379 + req->actual = ep->dwc_ep.xfer_count;
53380 +
53381 + /* Is a Zero Len Packet needed? */
53382 + if (req->sent_zlp) {
53383 +#ifdef DEBUG_EP0
53384 + DWC_DEBUGPL(DBG_PCDV, "Setup Tx ZLP\n");
53385 +#endif
53386 + req->sent_zlp = 0;
53387 + }
53388 + /* For older cores do setup in status phase in Slave/BDMA modes,
53389 + * starting from 3.00 do that only in slave, and for DMA modes
53390 + * just re-enable ep 0 OUT here*/
53391 + if (core_if->dma_enable == 0
53392 + || (core_if->dma_desc_enable == 0
53393 + && core_if->snpsid <= OTG_CORE_REV_2_94a)) {
53394 + do_setup_in_status_phase(pcd);
53395 + } else if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
53396 + DWC_DEBUGPL(DBG_PCDV,
53397 + "Enable out ep before in status phase\n");
53398 + ep0_out_start(core_if, pcd);
53399 + }
53400 + }
53401 +
53402 + /* Complete the request */
53403 + if (is_last) {
53404 + dwc_otg_request_done(ep, req, 0);
53405 + ep->dwc_ep.start_xfer_buff = 0;
53406 + ep->dwc_ep.xfer_buff = 0;
53407 + ep->dwc_ep.xfer_len = 0;
53408 + return 1;
53409 + }
53410 + return 0;
53411 +}
53412 +
53413 +#ifdef DWC_UTE_CFI
53414 +/**
53415 + * This function calculates traverses all the CFI DMA descriptors and
53416 + * and accumulates the bytes that are left to be transfered.
53417 + *
53418 + * @return The total bytes left to transfered, or a negative value as failure
53419 + */
53420 +static inline int cfi_calc_desc_residue(dwc_otg_pcd_ep_t * ep)
53421 +{
53422 + int32_t ret = 0;
53423 + int i;
53424 + struct dwc_otg_dma_desc *ddesc = NULL;
53425 + struct cfi_ep *cfiep;
53426 +
53427 + /* See if the pcd_ep has its respective cfi_ep mapped */
53428 + cfiep = get_cfi_ep_by_pcd_ep(ep->pcd->cfi, ep);
53429 + if (!cfiep) {
53430 + CFI_INFO("%s: Failed to find ep\n", __func__);
53431 + return -1;
53432 + }
53433 +
53434 + ddesc = ep->dwc_ep.descs;
53435 +
53436 + for (i = 0; (i < cfiep->desc_count) && (i < MAX_DMA_DESCS_PER_EP); i++) {
53437 +
53438 +#if defined(PRINT_CFI_DMA_DESCS)
53439 + print_desc(ddesc, ep->ep.name, i);
53440 +#endif
53441 + ret += ddesc->status.b.bytes;
53442 + ddesc++;
53443 + }
53444 +
53445 + if (ret)
53446 + CFI_INFO("!!!!!!!!!! WARNING (%s) - residue=%d\n", __func__,
53447 + ret);
53448 +
53449 + return ret;
53450 +}
53451 +#endif
53452 +
53453 +/**
53454 + * This function completes the request for the EP. If there are
53455 + * additional requests for the EP in the queue they will be started.
53456 + */
53457 +static void complete_ep(dwc_otg_pcd_ep_t * ep)
53458 +{
53459 + dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
53460 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
53461 + dwc_otg_dev_in_ep_regs_t *in_ep_regs =
53462 + dev_if->in_ep_regs[ep->dwc_ep.num];
53463 + deptsiz_data_t deptsiz;
53464 + dev_dma_desc_sts_t desc_sts;
53465 + dwc_otg_pcd_request_t *req = 0;
53466 + dwc_otg_dev_dma_desc_t *dma_desc;
53467 + uint32_t byte_count = 0;
53468 + int is_last = 0;
53469 + int i;
53470 +
53471 + DWC_DEBUGPL(DBG_PCDV, "%s() %d-%s\n", __func__, ep->dwc_ep.num,
53472 + (ep->dwc_ep.is_in ? "IN" : "OUT"));
53473 +
53474 + /* Get any pending requests */
53475 + if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
53476 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
53477 + if (!req) {
53478 + DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
53479 + return;
53480 + }
53481 + } else {
53482 + DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
53483 + return;
53484 + }
53485 +
53486 + DWC_DEBUGPL(DBG_PCD, "Requests %d\n", ep->pcd->request_pending);
53487 +
53488 + if (ep->dwc_ep.is_in) {
53489 + deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz);
53490 +
53491 + if (core_if->dma_enable) {
53492 + if (core_if->dma_desc_enable == 0) {
53493 + if (deptsiz.b.xfersize == 0
53494 + && deptsiz.b.pktcnt == 0) {
53495 + byte_count =
53496 + ep->dwc_ep.xfer_len -
53497 + ep->dwc_ep.xfer_count;
53498 +
53499 + ep->dwc_ep.xfer_buff += byte_count;
53500 + ep->dwc_ep.dma_addr += byte_count;
53501 + ep->dwc_ep.xfer_count += byte_count;
53502 +
53503 + DWC_DEBUGPL(DBG_PCDV,
53504 + "%d-%s len=%d xfersize=%d pktcnt=%d\n",
53505 + ep->dwc_ep.num,
53506 + (ep->dwc_ep.
53507 + is_in ? "IN" : "OUT"),
53508 + ep->dwc_ep.xfer_len,
53509 + deptsiz.b.xfersize,
53510 + deptsiz.b.pktcnt);
53511 +
53512 + if (ep->dwc_ep.xfer_len <
53513 + ep->dwc_ep.total_len) {
53514 + dwc_otg_ep_start_transfer
53515 + (core_if, &ep->dwc_ep);
53516 + } else if (ep->dwc_ep.sent_zlp) {
53517 + /*
53518 + * This fragment of code should initiate 0
53519 + * length transfer in case if it is queued
53520 + * a transfer with size divisible to EPs max
53521 + * packet size and with usb_request zero field
53522 + * is set, which means that after data is transfered,
53523 + * it is also should be transfered
53524 + * a 0 length packet at the end. For Slave and
53525 + * Buffer DMA modes in this case SW has
53526 + * to initiate 2 transfers one with transfer size,
53527 + * and the second with 0 size. For Descriptor
53528 + * DMA mode SW is able to initiate a transfer,
53529 + * which will handle all the packets including
53530 + * the last 0 length.
53531 + */
53532 + ep->dwc_ep.sent_zlp = 0;
53533 + dwc_otg_ep_start_zl_transfer
53534 + (core_if, &ep->dwc_ep);
53535 + } else {
53536 + is_last = 1;
53537 + }
53538 + } else {
53539 + if (ep->dwc_ep.type ==
53540 + DWC_OTG_EP_TYPE_ISOC) {
53541 + req->actual = 0;
53542 + dwc_otg_request_done(ep, req, 0);
53543 +
53544 + ep->dwc_ep.start_xfer_buff = 0;
53545 + ep->dwc_ep.xfer_buff = 0;
53546 + ep->dwc_ep.xfer_len = 0;
53547 +
53548 + /* If there is a request in the queue start it. */
53549 + start_next_request(ep);
53550 + } else
53551 + DWC_WARN
53552 + ("Incomplete transfer (%d - %s [siz=%d pkt=%d])\n",
53553 + ep->dwc_ep.num,
53554 + (ep->dwc_ep.is_in ? "IN" : "OUT"),
53555 + deptsiz.b.xfersize,
53556 + deptsiz.b.pktcnt);
53557 + }
53558 + } else {
53559 + dma_desc = ep->dwc_ep.desc_addr;
53560 + byte_count = 0;
53561 + ep->dwc_ep.sent_zlp = 0;
53562 +
53563 +#ifdef DWC_UTE_CFI
53564 + CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
53565 + ep->dwc_ep.buff_mode);
53566 + if (ep->dwc_ep.buff_mode != BM_STANDARD) {
53567 + int residue;
53568 +
53569 + residue = cfi_calc_desc_residue(ep);
53570 + if (residue < 0)
53571 + return;
53572 +
53573 + byte_count = residue;
53574 + } else {
53575 +#endif
53576 + for (i = 0; i < ep->dwc_ep.desc_cnt;
53577 + ++i) {
53578 + desc_sts = dma_desc->status;
53579 + byte_count += desc_sts.b.bytes;
53580 + dma_desc++;
53581 + }
53582 +#ifdef DWC_UTE_CFI
53583 + }
53584 +#endif
53585 + if (byte_count == 0) {
53586 + ep->dwc_ep.xfer_count =
53587 + ep->dwc_ep.total_len;
53588 + is_last = 1;
53589 + } else {
53590 + DWC_WARN("Incomplete transfer\n");
53591 + }
53592 + }
53593 + } else {
53594 + if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) {
53595 + DWC_DEBUGPL(DBG_PCDV,
53596 + "%d-%s len=%d xfersize=%d pktcnt=%d\n",
53597 + ep->dwc_ep.num,
53598 + ep->dwc_ep.is_in ? "IN" : "OUT",
53599 + ep->dwc_ep.xfer_len,
53600 + deptsiz.b.xfersize,
53601 + deptsiz.b.pktcnt);
53602 +
53603 + /* Check if the whole transfer was completed,
53604 + * if no, setup transfer for next portion of data
53605 + */
53606 + if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
53607 + dwc_otg_ep_start_transfer(core_if,
53608 + &ep->dwc_ep);
53609 + } else if (ep->dwc_ep.sent_zlp) {
53610 + /*
53611 + * This fragment of code should initiate 0
53612 + * length trasfer in case if it is queued
53613 + * a trasfer with size divisible to EPs max
53614 + * packet size and with usb_request zero field
53615 + * is set, which means that after data is transfered,
53616 + * it is also should be transfered
53617 + * a 0 length packet at the end. For Slave and
53618 + * Buffer DMA modes in this case SW has
53619 + * to initiate 2 transfers one with transfer size,
53620 + * and the second with 0 size. For Desriptor
53621 + * DMA mode SW is able to initiate a transfer,
53622 + * which will handle all the packets including
53623 + * the last 0 legth.
53624 + */
53625 + ep->dwc_ep.sent_zlp = 0;
53626 + dwc_otg_ep_start_zl_transfer(core_if,
53627 + &ep->dwc_ep);
53628 + } else {
53629 + is_last = 1;
53630 + }
53631 + } else {
53632 + DWC_WARN
53633 + ("Incomplete transfer (%d-%s [siz=%d pkt=%d])\n",
53634 + ep->dwc_ep.num,
53635 + (ep->dwc_ep.is_in ? "IN" : "OUT"),
53636 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
53637 + }
53638 + }
53639 + } else {
53640 + dwc_otg_dev_out_ep_regs_t *out_ep_regs =
53641 + dev_if->out_ep_regs[ep->dwc_ep.num];
53642 + desc_sts.d32 = 0;
53643 + if (core_if->dma_enable) {
53644 + if (core_if->dma_desc_enable) {
53645 + dma_desc = ep->dwc_ep.desc_addr;
53646 + byte_count = 0;
53647 + ep->dwc_ep.sent_zlp = 0;
53648 +
53649 +#ifdef DWC_UTE_CFI
53650 + CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
53651 + ep->dwc_ep.buff_mode);
53652 + if (ep->dwc_ep.buff_mode != BM_STANDARD) {
53653 + int residue;
53654 + residue = cfi_calc_desc_residue(ep);
53655 + if (residue < 0)
53656 + return;
53657 + byte_count = residue;
53658 + } else {
53659 +#endif
53660 +
53661 + for (i = 0; i < ep->dwc_ep.desc_cnt;
53662 + ++i) {
53663 + desc_sts = dma_desc->status;
53664 + byte_count += desc_sts.b.bytes;
53665 + dma_desc++;
53666 + }
53667 +
53668 +#ifdef DWC_UTE_CFI
53669 + }
53670 +#endif
53671 + /* Checking for interrupt Out transfers with not
53672 + * dword aligned mps sizes
53673 + */
53674 + if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_INTR &&
53675 + (ep->dwc_ep.maxpacket%4)) {
53676 + ep->dwc_ep.xfer_count =
53677 + ep->dwc_ep.total_len - byte_count;
53678 + if ((ep->dwc_ep.xfer_len %
53679 + ep->dwc_ep.maxpacket)
53680 + && (ep->dwc_ep.xfer_len /
53681 + ep->dwc_ep.maxpacket <
53682 + MAX_DMA_DESC_CNT))
53683 + ep->dwc_ep.xfer_len -=
53684 + (ep->dwc_ep.desc_cnt -
53685 + 1) * ep->dwc_ep.maxpacket +
53686 + ep->dwc_ep.xfer_len %
53687 + ep->dwc_ep.maxpacket;
53688 + else
53689 + ep->dwc_ep.xfer_len -=
53690 + ep->dwc_ep.desc_cnt *
53691 + ep->dwc_ep.maxpacket;
53692 + if (ep->dwc_ep.xfer_len > 0) {
53693 + dwc_otg_ep_start_transfer
53694 + (core_if, &ep->dwc_ep);
53695 + } else {
53696 + is_last = 1;
53697 + }
53698 + } else {
53699 + ep->dwc_ep.xfer_count =
53700 + ep->dwc_ep.total_len - byte_count +
53701 + ((4 -
53702 + (ep->dwc_ep.
53703 + total_len & 0x3)) & 0x3);
53704 + is_last = 1;
53705 + }
53706 + } else {
53707 + deptsiz.d32 = 0;
53708 + deptsiz.d32 =
53709 + DWC_READ_REG32(&out_ep_regs->doeptsiz);
53710 +
53711 + byte_count = (ep->dwc_ep.xfer_len -
53712 + ep->dwc_ep.xfer_count -
53713 + deptsiz.b.xfersize);
53714 + ep->dwc_ep.xfer_buff += byte_count;
53715 + ep->dwc_ep.dma_addr += byte_count;
53716 + ep->dwc_ep.xfer_count += byte_count;
53717 +
53718 + /* Check if the whole transfer was completed,
53719 + * if no, setup transfer for next portion of data
53720 + */
53721 + if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
53722 + dwc_otg_ep_start_transfer(core_if,
53723 + &ep->dwc_ep);
53724 + } else if (ep->dwc_ep.sent_zlp) {
53725 + /*
53726 + * This fragment of code should initiate 0
53727 + * length trasfer in case if it is queued
53728 + * a trasfer with size divisible to EPs max
53729 + * packet size and with usb_request zero field
53730 + * is set, which means that after data is transfered,
53731 + * it is also should be transfered
53732 + * a 0 length packet at the end. For Slave and
53733 + * Buffer DMA modes in this case SW has
53734 + * to initiate 2 transfers one with transfer size,
53735 + * and the second with 0 size. For Desriptor
53736 + * DMA mode SW is able to initiate a transfer,
53737 + * which will handle all the packets including
53738 + * the last 0 legth.
53739 + */
53740 + ep->dwc_ep.sent_zlp = 0;
53741 + dwc_otg_ep_start_zl_transfer(core_if,
53742 + &ep->dwc_ep);
53743 + } else {
53744 + is_last = 1;
53745 + }
53746 + }
53747 + } else {
53748 + /* Check if the whole transfer was completed,
53749 + * if no, setup transfer for next portion of data
53750 + */
53751 + if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
53752 + dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
53753 + } else if (ep->dwc_ep.sent_zlp) {
53754 + /*
53755 + * This fragment of code should initiate 0
53756 + * length transfer in case if it is queued
53757 + * a transfer with size divisible to EPs max
53758 + * packet size and with usb_request zero field
53759 + * is set, which means that after data is transfered,
53760 + * it is also should be transfered
53761 + * a 0 length packet at the end. For Slave and
53762 + * Buffer DMA modes in this case SW has
53763 + * to initiate 2 transfers one with transfer size,
53764 + * and the second with 0 size. For Descriptor
53765 + * DMA mode SW is able to initiate a transfer,
53766 + * which will handle all the packets including
53767 + * the last 0 length.
53768 + */
53769 + ep->dwc_ep.sent_zlp = 0;
53770 + dwc_otg_ep_start_zl_transfer(core_if,
53771 + &ep->dwc_ep);
53772 + } else {
53773 + is_last = 1;
53774 + }
53775 + }
53776 +
53777 + DWC_DEBUGPL(DBG_PCDV,
53778 + "addr %p, %d-%s len=%d cnt=%d xsize=%d pktcnt=%d\n",
53779 + &out_ep_regs->doeptsiz, ep->dwc_ep.num,
53780 + ep->dwc_ep.is_in ? "IN" : "OUT",
53781 + ep->dwc_ep.xfer_len, ep->dwc_ep.xfer_count,
53782 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
53783 + }
53784 +
53785 + /* Complete the request */
53786 + if (is_last) {
53787 +#ifdef DWC_UTE_CFI
53788 + if (ep->dwc_ep.buff_mode != BM_STANDARD) {
53789 + req->actual = ep->dwc_ep.cfi_req_len - byte_count;
53790 + } else {
53791 +#endif
53792 + req->actual = ep->dwc_ep.xfer_count;
53793 +#ifdef DWC_UTE_CFI
53794 + }
53795 +#endif
53796 + if (req->dw_align_buf) {
53797 + if (!ep->dwc_ep.is_in) {
53798 + dwc_memcpy(req->buf, req->dw_align_buf, req->length);
53799 + }
53800 + DWC_DMA_FREE(req->length, req->dw_align_buf,
53801 + req->dw_align_buf_dma);
53802 + }
53803 +
53804 + dwc_otg_request_done(ep, req, 0);
53805 +
53806 + ep->dwc_ep.start_xfer_buff = 0;
53807 + ep->dwc_ep.xfer_buff = 0;
53808 + ep->dwc_ep.xfer_len = 0;
53809 +
53810 + /* If there is a request in the queue start it. */
53811 + start_next_request(ep);
53812 + }
53813 +}
53814 +
53815 +#ifdef DWC_EN_ISOC
53816 +
53817 +/**
53818 + * This function BNA interrupt for Isochronous EPs
53819 + *
53820 + */
53821 +static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t * ep)
53822 +{
53823 + dwc_ep_t *dwc_ep = &ep->dwc_ep;
53824 + volatile uint32_t *addr;
53825 + depctl_data_t depctl = {.d32 = 0 };
53826 + dwc_otg_pcd_t *pcd = ep->pcd;
53827 + dwc_otg_dev_dma_desc_t *dma_desc;
53828 + int i;
53829 +
53830 + dma_desc =
53831 + dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * (dwc_ep->proc_buf_num);
53832 +
53833 + if (dwc_ep->is_in) {
53834 + dev_dma_desc_sts_t sts = {.d32 = 0 };
53835 + for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
53836 + sts.d32 = dma_desc->status.d32;
53837 + sts.b_iso_in.bs = BS_HOST_READY;
53838 + dma_desc->status.d32 = sts.d32;
53839 + }
53840 + } else {
53841 + dev_dma_desc_sts_t sts = {.d32 = 0 };
53842 + for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
53843 + sts.d32 = dma_desc->status.d32;
53844 + sts.b_iso_out.bs = BS_HOST_READY;
53845 + dma_desc->status.d32 = sts.d32;
53846 + }
53847 + }
53848 +
53849 + if (dwc_ep->is_in == 0) {
53850 + addr =
53851 + &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->
53852 + num]->doepctl;
53853 + } else {
53854 + addr =
53855 + &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
53856 + }
53857 + depctl.b.epena = 1;
53858 + DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
53859 +}
53860 +
53861 +/**
53862 + * This function sets latest iso packet information(non-PTI mode)
53863 + *
53864 + * @param core_if Programming view of DWC_otg controller.
53865 + * @param ep The EP to start the transfer on.
53866 + *
53867 + */
53868 +void set_current_pkt_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
53869 +{
53870 + deptsiz_data_t deptsiz = {.d32 = 0 };
53871 + dma_addr_t dma_addr;
53872 + uint32_t offset;
53873 +
53874 + if (ep->proc_buf_num)
53875 + dma_addr = ep->dma_addr1;
53876 + else
53877 + dma_addr = ep->dma_addr0;
53878 +
53879 + if (ep->is_in) {
53880 + deptsiz.d32 =
53881 + DWC_READ_REG32(&core_if->dev_if->
53882 + in_ep_regs[ep->num]->dieptsiz);
53883 + offset = ep->data_per_frame;
53884 + } else {
53885 + deptsiz.d32 =
53886 + DWC_READ_REG32(&core_if->dev_if->
53887 + out_ep_regs[ep->num]->doeptsiz);
53888 + offset =
53889 + ep->data_per_frame +
53890 + (0x4 & (0x4 - (ep->data_per_frame & 0x3)));
53891 + }
53892 +
53893 + if (!deptsiz.b.xfersize) {
53894 + ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
53895 + ep->pkt_info[ep->cur_pkt].offset =
53896 + ep->cur_pkt_dma_addr - dma_addr;
53897 + ep->pkt_info[ep->cur_pkt].status = 0;
53898 + } else {
53899 + ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
53900 + ep->pkt_info[ep->cur_pkt].offset =
53901 + ep->cur_pkt_dma_addr - dma_addr;
53902 + ep->pkt_info[ep->cur_pkt].status = -DWC_E_NO_DATA;
53903 + }
53904 + ep->cur_pkt_addr += offset;
53905 + ep->cur_pkt_dma_addr += offset;
53906 + ep->cur_pkt++;
53907 +}
53908 +
53909 +/**
53910 + * This function sets latest iso packet information(DDMA mode)
53911 + *
53912 + * @param core_if Programming view of DWC_otg controller.
53913 + * @param dwc_ep The EP to start the transfer on.
53914 + *
53915 + */
53916 +static void set_ddma_iso_pkts_info(dwc_otg_core_if_t * core_if,
53917 + dwc_ep_t * dwc_ep)
53918 +{
53919 + dwc_otg_dev_dma_desc_t *dma_desc;
53920 + dev_dma_desc_sts_t sts = {.d32 = 0 };
53921 + iso_pkt_info_t *iso_packet;
53922 + uint32_t data_per_desc;
53923 + uint32_t offset;
53924 + int i, j;
53925 +
53926 + iso_packet = dwc_ep->pkt_info;
53927 +
53928 + /** Reinit closed DMA Descriptors*/
53929 + /** ISO OUT EP */
53930 + if (dwc_ep->is_in == 0) {
53931 + dma_desc =
53932 + dwc_ep->iso_desc_addr +
53933 + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
53934 + offset = 0;
53935 +
53936 + for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
53937 + i += dwc_ep->pkt_per_frm) {
53938 + for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
53939 + data_per_desc =
53940 + ((j + 1) * dwc_ep->maxpacket >
53941 + dwc_ep->
53942 + data_per_frame) ? dwc_ep->data_per_frame -
53943 + j * dwc_ep->maxpacket : dwc_ep->maxpacket;
53944 + data_per_desc +=
53945 + (data_per_desc % 4) ? (4 -
53946 + data_per_desc %
53947 + 4) : 0;
53948 +
53949 + sts.d32 = dma_desc->status.d32;
53950 +
53951 + /* Write status in iso_packet_decsriptor */
53952 + iso_packet->status =
53953 + sts.b_iso_out.rxsts +
53954 + (sts.b_iso_out.bs ^ BS_DMA_DONE);
53955 + if (iso_packet->status) {
53956 + iso_packet->status = -DWC_E_NO_DATA;
53957 + }
53958 +
53959 + /* Received data length */
53960 + if (!sts.b_iso_out.rxbytes) {
53961 + iso_packet->length =
53962 + data_per_desc -
53963 + sts.b_iso_out.rxbytes;
53964 + } else {
53965 + iso_packet->length =
53966 + data_per_desc -
53967 + sts.b_iso_out.rxbytes + (4 -
53968 + dwc_ep->data_per_frame
53969 + % 4);
53970 + }
53971 +
53972 + iso_packet->offset = offset;
53973 +
53974 + offset += data_per_desc;
53975 + dma_desc++;
53976 + iso_packet++;
53977 + }
53978 + }
53979 +
53980 + for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
53981 + data_per_desc =
53982 + ((j + 1) * dwc_ep->maxpacket >
53983 + dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
53984 + j * dwc_ep->maxpacket : dwc_ep->maxpacket;
53985 + data_per_desc +=
53986 + (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
53987 +
53988 + sts.d32 = dma_desc->status.d32;
53989 +
53990 + /* Write status in iso_packet_decsriptor */
53991 + iso_packet->status =
53992 + sts.b_iso_out.rxsts +
53993 + (sts.b_iso_out.bs ^ BS_DMA_DONE);
53994 + if (iso_packet->status) {
53995 + iso_packet->status = -DWC_E_NO_DATA;
53996 + }
53997 +
53998 + /* Received data length */
53999 + iso_packet->length =
54000 + dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
54001 +
54002 + iso_packet->offset = offset;
54003 +
54004 + offset += data_per_desc;
54005 + iso_packet++;
54006 + dma_desc++;
54007 + }
54008 +
54009 + sts.d32 = dma_desc->status.d32;
54010 +
54011 + /* Write status in iso_packet_decsriptor */
54012 + iso_packet->status =
54013 + sts.b_iso_out.rxsts + (sts.b_iso_out.bs ^ BS_DMA_DONE);
54014 + if (iso_packet->status) {
54015 + iso_packet->status = -DWC_E_NO_DATA;
54016 + }
54017 + /* Received data length */
54018 + if (!sts.b_iso_out.rxbytes) {
54019 + iso_packet->length =
54020 + dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
54021 + } else {
54022 + iso_packet->length =
54023 + dwc_ep->data_per_frame - sts.b_iso_out.rxbytes +
54024 + (4 - dwc_ep->data_per_frame % 4);
54025 + }
54026 +
54027 + iso_packet->offset = offset;
54028 + } else {
54029 +/** ISO IN EP */
54030 +
54031 + dma_desc =
54032 + dwc_ep->iso_desc_addr +
54033 + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
54034 +
54035 + for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
54036 + sts.d32 = dma_desc->status.d32;
54037 +
54038 + /* Write status in iso packet descriptor */
54039 + iso_packet->status =
54040 + sts.b_iso_in.txsts +
54041 + (sts.b_iso_in.bs ^ BS_DMA_DONE);
54042 + if (iso_packet->status != 0) {
54043 + iso_packet->status = -DWC_E_NO_DATA;
54044 +
54045 + }
54046 + /* Bytes has been transfered */
54047 + iso_packet->length =
54048 + dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
54049 +
54050 + dma_desc++;
54051 + iso_packet++;
54052 + }
54053 +
54054 + sts.d32 = dma_desc->status.d32;
54055 + while (sts.b_iso_in.bs == BS_DMA_BUSY) {
54056 + sts.d32 = dma_desc->status.d32;
54057 + }
54058 +
54059 + /* Write status in iso packet descriptor ??? do be done with ERROR codes */
54060 + iso_packet->status =
54061 + sts.b_iso_in.txsts + (sts.b_iso_in.bs ^ BS_DMA_DONE);
54062 + if (iso_packet->status != 0) {
54063 + iso_packet->status = -DWC_E_NO_DATA;
54064 + }
54065 +
54066 + /* Bytes has been transfered */
54067 + iso_packet->length =
54068 + dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
54069 + }
54070 +}
54071 +
54072 +/**
54073 + * This function reinitialize DMA Descriptors for Isochronous transfer
54074 + *
54075 + * @param core_if Programming view of DWC_otg controller.
54076 + * @param dwc_ep The EP to start the transfer on.
54077 + *
54078 + */
54079 +static void reinit_ddma_iso_xfer(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
54080 +{
54081 + int i, j;
54082 + dwc_otg_dev_dma_desc_t *dma_desc;
54083 + dma_addr_t dma_ad;
54084 + volatile uint32_t *addr;
54085 + dev_dma_desc_sts_t sts = {.d32 = 0 };
54086 + uint32_t data_per_desc;
54087 +
54088 + if (dwc_ep->is_in == 0) {
54089 + addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
54090 + } else {
54091 + addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
54092 + }
54093 +
54094 + if (dwc_ep->proc_buf_num == 0) {
54095 + /** Buffer 0 descriptors setup */
54096 + dma_ad = dwc_ep->dma_addr0;
54097 + } else {
54098 + /** Buffer 1 descriptors setup */
54099 + dma_ad = dwc_ep->dma_addr1;
54100 + }
54101 +
54102 + /** Reinit closed DMA Descriptors*/
54103 + /** ISO OUT EP */
54104 + if (dwc_ep->is_in == 0) {
54105 + dma_desc =
54106 + dwc_ep->iso_desc_addr +
54107 + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
54108 +
54109 + sts.b_iso_out.bs = BS_HOST_READY;
54110 + sts.b_iso_out.rxsts = 0;
54111 + sts.b_iso_out.l = 0;
54112 + sts.b_iso_out.sp = 0;
54113 + sts.b_iso_out.ioc = 0;
54114 + sts.b_iso_out.pid = 0;
54115 + sts.b_iso_out.framenum = 0;
54116 +
54117 + for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
54118 + i += dwc_ep->pkt_per_frm) {
54119 + for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
54120 + data_per_desc =
54121 + ((j + 1) * dwc_ep->maxpacket >
54122 + dwc_ep->
54123 + data_per_frame) ? dwc_ep->data_per_frame -
54124 + j * dwc_ep->maxpacket : dwc_ep->maxpacket;
54125 + data_per_desc +=
54126 + (data_per_desc % 4) ? (4 -
54127 + data_per_desc %
54128 + 4) : 0;
54129 + sts.b_iso_out.rxbytes = data_per_desc;
54130 + dma_desc->buf = dma_ad;
54131 + dma_desc->status.d32 = sts.d32;
54132 +
54133 + dma_ad += data_per_desc;
54134 + dma_desc++;
54135 + }
54136 + }
54137 +
54138 + for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
54139 +
54140 + data_per_desc =
54141 + ((j + 1) * dwc_ep->maxpacket >
54142 + dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
54143 + j * dwc_ep->maxpacket : dwc_ep->maxpacket;
54144 + data_per_desc +=
54145 + (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
54146 + sts.b_iso_out.rxbytes = data_per_desc;
54147 +
54148 + dma_desc->buf = dma_ad;
54149 + dma_desc->status.d32 = sts.d32;
54150 +
54151 + dma_desc++;
54152 + dma_ad += data_per_desc;
54153 + }
54154 +
54155 + sts.b_iso_out.ioc = 1;
54156 + sts.b_iso_out.l = dwc_ep->proc_buf_num;
54157 +
54158 + data_per_desc =
54159 + ((j + 1) * dwc_ep->maxpacket >
54160 + dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
54161 + j * dwc_ep->maxpacket : dwc_ep->maxpacket;
54162 + data_per_desc +=
54163 + (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
54164 + sts.b_iso_out.rxbytes = data_per_desc;
54165 +
54166 + dma_desc->buf = dma_ad;
54167 + dma_desc->status.d32 = sts.d32;
54168 + } else {
54169 +/** ISO IN EP */
54170 +
54171 + dma_desc =
54172 + dwc_ep->iso_desc_addr +
54173 + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
54174 +
54175 + sts.b_iso_in.bs = BS_HOST_READY;
54176 + sts.b_iso_in.txsts = 0;
54177 + sts.b_iso_in.sp = 0;
54178 + sts.b_iso_in.ioc = 0;
54179 + sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
54180 + sts.b_iso_in.framenum = dwc_ep->next_frame;
54181 + sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
54182 + sts.b_iso_in.l = 0;
54183 +
54184 + for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
54185 + dma_desc->buf = dma_ad;
54186 + dma_desc->status.d32 = sts.d32;
54187 +
54188 + sts.b_iso_in.framenum += dwc_ep->bInterval;
54189 + dma_ad += dwc_ep->data_per_frame;
54190 + dma_desc++;
54191 + }
54192 +
54193 + sts.b_iso_in.ioc = 1;
54194 + sts.b_iso_in.l = dwc_ep->proc_buf_num;
54195 +
54196 + dma_desc->buf = dma_ad;
54197 + dma_desc->status.d32 = sts.d32;
54198 +
54199 + dwc_ep->next_frame =
54200 + sts.b_iso_in.framenum + dwc_ep->bInterval * 1;
54201 + }
54202 + dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
54203 +}
54204 +
54205 +/**
54206 + * This function is to handle Iso EP transfer complete interrupt
54207 + * in case Iso out packet was dropped
54208 + *
54209 + * @param core_if Programming view of DWC_otg controller.
54210 + * @param dwc_ep The EP for wihich transfer complete was asserted
54211 + *
54212 + */
54213 +static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t * core_if,
54214 + dwc_ep_t * dwc_ep)
54215 +{
54216 + uint32_t dma_addr;
54217 + uint32_t drp_pkt;
54218 + uint32_t drp_pkt_cnt;
54219 + deptsiz_data_t deptsiz = {.d32 = 0 };
54220 + depctl_data_t depctl = {.d32 = 0 };
54221 + int i;
54222 +
54223 + deptsiz.d32 =
54224 + DWC_READ_REG32(&core_if->dev_if->
54225 + out_ep_regs[dwc_ep->num]->doeptsiz);
54226 +
54227 + drp_pkt = dwc_ep->pkt_cnt - deptsiz.b.pktcnt;
54228 + drp_pkt_cnt = dwc_ep->pkt_per_frm - (drp_pkt % dwc_ep->pkt_per_frm);
54229 +
54230 + /* Setting dropped packets status */
54231 + for (i = 0; i < drp_pkt_cnt; ++i) {
54232 + dwc_ep->pkt_info[drp_pkt].status = -DWC_E_NO_DATA;
54233 + drp_pkt++;
54234 + deptsiz.b.pktcnt--;
54235 + }
54236 +
54237 + if (deptsiz.b.pktcnt > 0) {
54238 + deptsiz.b.xfersize =
54239 + dwc_ep->xfer_len - (dwc_ep->pkt_cnt -
54240 + deptsiz.b.pktcnt) * dwc_ep->maxpacket;
54241 + } else {
54242 + deptsiz.b.xfersize = 0;
54243 + deptsiz.b.pktcnt = 0;
54244 + }
54245 +
54246 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz,
54247 + deptsiz.d32);
54248 +
54249 + if (deptsiz.b.pktcnt > 0) {
54250 + if (dwc_ep->proc_buf_num) {
54251 + dma_addr =
54252 + dwc_ep->dma_addr1 + dwc_ep->xfer_len -
54253 + deptsiz.b.xfersize;
54254 + } else {
54255 + dma_addr =
54256 + dwc_ep->dma_addr0 + dwc_ep->xfer_len -
54257 + deptsiz.b.xfersize;;
54258 + }
54259 +
54260 + DWC_WRITE_REG32(&core_if->dev_if->
54261 + out_ep_regs[dwc_ep->num]->doepdma, dma_addr);
54262 +
54263 + /** Re-enable endpoint, clear nak */
54264 + depctl.d32 = 0;
54265 + depctl.b.epena = 1;
54266 + depctl.b.cnak = 1;
54267 +
54268 + DWC_MODIFY_REG32(&core_if->dev_if->
54269 + out_ep_regs[dwc_ep->num]->doepctl, depctl.d32,
54270 + depctl.d32);
54271 + return 0;
54272 + } else {
54273 + return 1;
54274 + }
54275 +}
54276 +
54277 +/**
54278 + * This function sets iso packets information(PTI mode)
54279 + *
54280 + * @param core_if Programming view of DWC_otg controller.
54281 + * @param ep The EP to start the transfer on.
54282 + *
54283 + */
54284 +static uint32_t set_iso_pkts_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
54285 +{
54286 + int i, j;
54287 + dma_addr_t dma_ad;
54288 + iso_pkt_info_t *packet_info = ep->pkt_info;
54289 + uint32_t offset;
54290 + uint32_t frame_data;
54291 + deptsiz_data_t deptsiz;
54292 +
54293 + if (ep->proc_buf_num == 0) {
54294 + /** Buffer 0 descriptors setup */
54295 + dma_ad = ep->dma_addr0;
54296 + } else {
54297 + /** Buffer 1 descriptors setup */
54298 + dma_ad = ep->dma_addr1;
54299 + }
54300 +
54301 + if (ep->is_in) {
54302 + deptsiz.d32 =
54303 + DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
54304 + dieptsiz);
54305 + } else {
54306 + deptsiz.d32 =
54307 + DWC_READ_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
54308 + doeptsiz);
54309 + }
54310 +
54311 + if (!deptsiz.b.xfersize) {
54312 + offset = 0;
54313 + for (i = 0; i < ep->pkt_cnt; i += ep->pkt_per_frm) {
54314 + frame_data = ep->data_per_frame;
54315 + for (j = 0; j < ep->pkt_per_frm; ++j) {
54316 +
54317 + /* Packet status - is not set as initially
54318 + * it is set to 0 and if packet was sent
54319 + successfully, status field will remain 0*/
54320 +
54321 + /* Bytes has been transfered */
54322 + packet_info->length =
54323 + (ep->maxpacket <
54324 + frame_data) ? ep->maxpacket : frame_data;
54325 +
54326 + /* Received packet offset */
54327 + packet_info->offset = offset;
54328 + offset += packet_info->length;
54329 + frame_data -= packet_info->length;
54330 +
54331 + packet_info++;
54332 + }
54333 + }
54334 + return 1;
54335 + } else {
54336 + /* This is a workaround for in case of Transfer Complete with
54337 + * PktDrpSts interrupts merging - in this case Transfer complete
54338 + * interrupt for Isoc Out Endpoint is asserted without PktDrpSts
54339 + * set and with DOEPTSIZ register non zero. Investigations showed,
54340 + * that this happens when Out packet is dropped, but because of
54341 + * interrupts merging during first interrupt handling PktDrpSts
54342 + * bit is cleared and for next merged interrupts it is not reset.
54343 + * In this case SW hadles the interrupt as if PktDrpSts bit is set.
54344 + */
54345 + if (ep->is_in) {
54346 + return 1;
54347 + } else {
54348 + return handle_iso_out_pkt_dropped(core_if, ep);
54349 + }
54350 + }
54351 +}
54352 +
54353 +/**
54354 + * This function is to handle Iso EP transfer complete interrupt
54355 + *
54356 + * @param pcd The PCD
54357 + * @param ep The EP for which transfer complete was asserted
54358 + *
54359 + */
54360 +static void complete_iso_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
54361 +{
54362 + dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
54363 + dwc_ep_t *dwc_ep = &ep->dwc_ep;
54364 + uint8_t is_last = 0;
54365 +
54366 + if (ep->dwc_ep.next_frame == 0xffffffff) {
54367 + DWC_WARN("Next frame is not set!\n");
54368 + return;
54369 + }
54370 +
54371 + if (core_if->dma_enable) {
54372 + if (core_if->dma_desc_enable) {
54373 + set_ddma_iso_pkts_info(core_if, dwc_ep);
54374 + reinit_ddma_iso_xfer(core_if, dwc_ep);
54375 + is_last = 1;
54376 + } else {
54377 + if (core_if->pti_enh_enable) {
54378 + if (set_iso_pkts_info(core_if, dwc_ep)) {
54379 + dwc_ep->proc_buf_num =
54380 + (dwc_ep->proc_buf_num ^ 1) & 0x1;
54381 + dwc_otg_iso_ep_start_buf_transfer
54382 + (core_if, dwc_ep);
54383 + is_last = 1;
54384 + }
54385 + } else {
54386 + set_current_pkt_info(core_if, dwc_ep);
54387 + if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
54388 + is_last = 1;
54389 + dwc_ep->cur_pkt = 0;
54390 + dwc_ep->proc_buf_num =
54391 + (dwc_ep->proc_buf_num ^ 1) & 0x1;
54392 + if (dwc_ep->proc_buf_num) {
54393 + dwc_ep->cur_pkt_addr =
54394 + dwc_ep->xfer_buff1;
54395 + dwc_ep->cur_pkt_dma_addr =
54396 + dwc_ep->dma_addr1;
54397 + } else {
54398 + dwc_ep->cur_pkt_addr =
54399 + dwc_ep->xfer_buff0;
54400 + dwc_ep->cur_pkt_dma_addr =
54401 + dwc_ep->dma_addr0;
54402 + }
54403 +
54404 + }
54405 + dwc_otg_iso_ep_start_frm_transfer(core_if,
54406 + dwc_ep);
54407 + }
54408 + }
54409 + } else {
54410 + set_current_pkt_info(core_if, dwc_ep);
54411 + if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
54412 + is_last = 1;
54413 + dwc_ep->cur_pkt = 0;
54414 + dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
54415 + if (dwc_ep->proc_buf_num) {
54416 + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
54417 + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
54418 + } else {
54419 + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
54420 + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
54421 + }
54422 +
54423 + }
54424 + dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep);
54425 + }
54426 + if (is_last)
54427 + dwc_otg_iso_buffer_done(pcd, ep, ep->iso_req_handle);
54428 +}
54429 +#endif /* DWC_EN_ISOC */
54430 +
54431 +/**
54432 + * This function handle BNA interrupt for Non Isochronous EPs
54433 + *
54434 + */
54435 +static void dwc_otg_pcd_handle_noniso_bna(dwc_otg_pcd_ep_t * ep)
54436 +{
54437 + dwc_ep_t *dwc_ep = &ep->dwc_ep;
54438 + volatile uint32_t *addr;
54439 + depctl_data_t depctl = {.d32 = 0 };
54440 + dwc_otg_pcd_t *pcd = ep->pcd;
54441 + dwc_otg_dev_dma_desc_t *dma_desc;
54442 + dev_dma_desc_sts_t sts = {.d32 = 0 };
54443 + dwc_otg_core_if_t *core_if = ep->pcd->core_if;
54444 + int i, start;
54445 +
54446 + if (!dwc_ep->desc_cnt)
54447 + DWC_WARN("Ep%d %s Descriptor count = %d \n", dwc_ep->num,
54448 + (dwc_ep->is_in ? "IN" : "OUT"), dwc_ep->desc_cnt);
54449 +
54450 + if (core_if->core_params->cont_on_bna && !dwc_ep->is_in
54451 + && dwc_ep->type != DWC_OTG_EP_TYPE_CONTROL) {
54452 + uint32_t doepdma;
54453 + dwc_otg_dev_out_ep_regs_t *out_regs =
54454 + core_if->dev_if->out_ep_regs[dwc_ep->num];
54455 + doepdma = DWC_READ_REG32(&(out_regs->doepdma));
54456 + start = (doepdma - dwc_ep->dma_desc_addr)/sizeof(dwc_otg_dev_dma_desc_t);
54457 + dma_desc = &(dwc_ep->desc_addr[start]);
54458 + } else {
54459 + start = 0;
54460 + dma_desc = dwc_ep->desc_addr;
54461 + }
54462 +
54463 +
54464 + for (i = start; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
54465 + sts.d32 = dma_desc->status.d32;
54466 + sts.b.bs = BS_HOST_READY;
54467 + dma_desc->status.d32 = sts.d32;
54468 + }
54469 +
54470 + if (dwc_ep->is_in == 0) {
54471 + addr =
54472 + &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->num]->
54473 + doepctl;
54474 + } else {
54475 + addr =
54476 + &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
54477 + }
54478 + depctl.b.epena = 1;
54479 + depctl.b.cnak = 1;
54480 + DWC_MODIFY_REG32(addr, 0, depctl.d32);
54481 +}
54482 +
54483 +/**
54484 + * This function handles EP0 Control transfers.
54485 + *
54486 + * The state of the control transfers are tracked in
54487 + * <code>ep0state</code>.
54488 + */
54489 +static void handle_ep0(dwc_otg_pcd_t * pcd)
54490 +{
54491 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
54492 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
54493 + dev_dma_desc_sts_t desc_sts;
54494 + deptsiz0_data_t deptsiz;
54495 + uint32_t byte_count;
54496 +
54497 +#ifdef DEBUG_EP0
54498 + DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
54499 + print_ep0_state(pcd);
54500 +#endif
54501 +
54502 +// DWC_PRINTF("HANDLE EP0\n");
54503 +
54504 + switch (pcd->ep0state) {
54505 + case EP0_DISCONNECT:
54506 + break;
54507 +
54508 + case EP0_IDLE:
54509 + pcd->request_config = 0;
54510 +
54511 + pcd_setup(pcd);
54512 + break;
54513 +
54514 + case EP0_IN_DATA_PHASE:
54515 +#ifdef DEBUG_EP0
54516 + DWC_DEBUGPL(DBG_PCD, "DATA_IN EP%d-%s: type=%d, mps=%d\n",
54517 + ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
54518 + ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
54519 +#endif
54520 +
54521 + if (core_if->dma_enable != 0) {
54522 + /*
54523 + * For EP0 we can only program 1 packet at a time so we
54524 + * need to do the make calculations after each complete.
54525 + * Call write_packet to make the calculations, as in
54526 + * slave mode, and use those values to determine if we
54527 + * can complete.
54528 + */
54529 + if (core_if->dma_desc_enable == 0) {
54530 + deptsiz.d32 =
54531 + DWC_READ_REG32(&core_if->
54532 + dev_if->in_ep_regs[0]->
54533 + dieptsiz);
54534 + byte_count =
54535 + ep0->dwc_ep.xfer_len - deptsiz.b.xfersize;
54536 + } else {
54537 + desc_sts =
54538 + core_if->dev_if->in_desc_addr->status;
54539 + byte_count =
54540 + ep0->dwc_ep.xfer_len - desc_sts.b.bytes;
54541 + }
54542 + ep0->dwc_ep.xfer_count += byte_count;
54543 + ep0->dwc_ep.xfer_buff += byte_count;
54544 + ep0->dwc_ep.dma_addr += byte_count;
54545 + }
54546 + if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
54547 + dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
54548 + &ep0->dwc_ep);
54549 + DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
54550 + } else if (ep0->dwc_ep.sent_zlp) {
54551 + dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
54552 + &ep0->dwc_ep);
54553 + ep0->dwc_ep.sent_zlp = 0;
54554 + DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER sent zlp\n");
54555 + } else {
54556 + ep0_complete_request(ep0);
54557 + DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
54558 + }
54559 + break;
54560 + case EP0_OUT_DATA_PHASE:
54561 +#ifdef DEBUG_EP0
54562 + DWC_DEBUGPL(DBG_PCD, "DATA_OUT EP%d-%s: type=%d, mps=%d\n",
54563 + ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
54564 + ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
54565 +#endif
54566 + if (core_if->dma_enable != 0) {
54567 + if (core_if->dma_desc_enable == 0) {
54568 + deptsiz.d32 =
54569 + DWC_READ_REG32(&core_if->
54570 + dev_if->out_ep_regs[0]->
54571 + doeptsiz);
54572 + byte_count =
54573 + ep0->dwc_ep.maxpacket - deptsiz.b.xfersize;
54574 + } else {
54575 + desc_sts =
54576 + core_if->dev_if->out_desc_addr->status;
54577 + byte_count =
54578 + ep0->dwc_ep.maxpacket - desc_sts.b.bytes;
54579 + }
54580 + ep0->dwc_ep.xfer_count += byte_count;
54581 + ep0->dwc_ep.xfer_buff += byte_count;
54582 + ep0->dwc_ep.dma_addr += byte_count;
54583 + }
54584 + if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
54585 + dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
54586 + &ep0->dwc_ep);
54587 + DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
54588 + } else if (ep0->dwc_ep.sent_zlp) {
54589 + dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
54590 + &ep0->dwc_ep);
54591 + ep0->dwc_ep.sent_zlp = 0;
54592 + DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER sent zlp\n");
54593 + } else {
54594 + ep0_complete_request(ep0);
54595 + DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
54596 + }
54597 + break;
54598 +
54599 + case EP0_IN_STATUS_PHASE:
54600 + case EP0_OUT_STATUS_PHASE:
54601 + DWC_DEBUGPL(DBG_PCD, "CASE: EP0_STATUS\n");
54602 + ep0_complete_request(ep0);
54603 + pcd->ep0state = EP0_IDLE;
54604 + ep0->stopped = 1;
54605 + ep0->dwc_ep.is_in = 0; /* OUT for next SETUP */
54606 +
54607 + /* Prepare for more SETUP Packets */
54608 + if (core_if->dma_enable) {
54609 + ep0_out_start(core_if, pcd);
54610 + }
54611 + break;
54612 +
54613 + case EP0_STALL:
54614 + DWC_ERROR("EP0 STALLed, should not get here pcd_setup()\n");
54615 + break;
54616 + }
54617 +#ifdef DEBUG_EP0
54618 + print_ep0_state(pcd);
54619 +#endif
54620 +}
54621 +
54622 +/**
54623 + * Restart transfer
54624 + */
54625 +static void restart_transfer(dwc_otg_pcd_t * pcd, const uint32_t epnum)
54626 +{
54627 + dwc_otg_core_if_t *core_if;
54628 + dwc_otg_dev_if_t *dev_if;
54629 + deptsiz_data_t dieptsiz = {.d32 = 0 };
54630 + dwc_otg_pcd_ep_t *ep;
54631 +
54632 + ep = get_in_ep(pcd, epnum);
54633 +
54634 +#ifdef DWC_EN_ISOC
54635 + if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
54636 + return;
54637 + }
54638 +#endif /* DWC_EN_ISOC */
54639 +
54640 + core_if = GET_CORE_IF(pcd);
54641 + dev_if = core_if->dev_if;
54642 +
54643 + dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz);
54644 +
54645 + DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x xfer_len=%0x"
54646 + " stopped=%d\n", ep->dwc_ep.xfer_buff,
54647 + ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len, ep->stopped);
54648 + /*
54649 + * If xfersize is 0 and pktcnt in not 0, resend the last packet.
54650 + */
54651 + if (dieptsiz.b.pktcnt && dieptsiz.b.xfersize == 0 &&
54652 + ep->dwc_ep.start_xfer_buff != 0) {
54653 + if (ep->dwc_ep.total_len <= ep->dwc_ep.maxpacket) {
54654 + ep->dwc_ep.xfer_count = 0;
54655 + ep->dwc_ep.xfer_buff = ep->dwc_ep.start_xfer_buff;
54656 + ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
54657 + } else {
54658 + ep->dwc_ep.xfer_count -= ep->dwc_ep.maxpacket;
54659 + /* convert packet size to dwords. */
54660 + ep->dwc_ep.xfer_buff -= ep->dwc_ep.maxpacket;
54661 + ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
54662 + }
54663 + ep->stopped = 0;
54664 + DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x "
54665 + "xfer_len=%0x stopped=%d\n",
54666 + ep->dwc_ep.xfer_buff,
54667 + ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len,
54668 + ep->stopped);
54669 + if (epnum == 0) {
54670 + dwc_otg_ep0_start_transfer(core_if, &ep->dwc_ep);
54671 + } else {
54672 + dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
54673 + }
54674 + }
54675 +}
54676 +
54677 +/*
54678 + * This function create new nextep sequnce based on Learn Queue.
54679 + *
54680 + * @param core_if Programming view of DWC_otg controller
54681 + */
54682 +void predict_nextep_seq( dwc_otg_core_if_t * core_if)
54683 +{
54684 + dwc_otg_device_global_regs_t *dev_global_regs =
54685 + core_if->dev_if->dev_global_regs;
54686 + const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
54687 + /* Number of Token Queue Registers */
54688 + const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
54689 + dtknq1_data_t dtknqr1;
54690 + uint32_t in_tkn_epnums[4];
54691 + uint8_t seqnum[MAX_EPS_CHANNELS];
54692 + uint8_t intkn_seq[TOKEN_Q_DEPTH];
54693 + grstctl_t resetctl = {.d32 = 0 };
54694 + uint8_t temp;
54695 + int ndx = 0;
54696 + int start = 0;
54697 + int end = 0;
54698 + int sort_done = 0;
54699 + int i = 0;
54700 + volatile uint32_t *addr = &dev_global_regs->dtknqr1;
54701 +
54702 +
54703 + DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
54704 +
54705 + /* Read the DTKNQ Registers */
54706 + for (i = 0; i < DTKNQ_REG_CNT; i++) {
54707 + in_tkn_epnums[i] = DWC_READ_REG32(addr);
54708 + DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1,
54709 + in_tkn_epnums[i]);
54710 + if (addr == &dev_global_regs->dvbusdis) {
54711 + addr = &dev_global_regs->dtknqr3_dthrctl;
54712 + } else {
54713 + ++addr;
54714 + }
54715 +
54716 + }
54717 +
54718 + /* Copy the DTKNQR1 data to the bit field. */
54719 + dtknqr1.d32 = in_tkn_epnums[0];
54720 + if (dtknqr1.b.wrap_bit) {
54721 + ndx = dtknqr1.b.intknwptr;
54722 + end = ndx -1;
54723 + if (end < 0)
54724 + end = TOKEN_Q_DEPTH -1;
54725 + } else {
54726 + ndx = 0;
54727 + end = dtknqr1.b.intknwptr -1;
54728 + if (end < 0)
54729 + end = 0;
54730 + }
54731 + start = ndx;
54732 +
54733 + /* Fill seqnum[] by initial values: EP number + 31 */
54734 + for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
54735 + seqnum[i] = i +31;
54736 + }
54737 +
54738 + /* Fill intkn_seq[] from in_tkn_epnums[0] */
54739 + for (i=0; i < 6; i++)
54740 + intkn_seq[i] = (in_tkn_epnums[0] >> ((7-i) * 4)) & 0xf;
54741 +
54742 + if (TOKEN_Q_DEPTH > 6) {
54743 + /* Fill intkn_seq[] from in_tkn_epnums[1] */
54744 + for (i=6; i < 14; i++)
54745 + intkn_seq[i] =
54746 + (in_tkn_epnums[1] >> ((7 - (i - 6)) * 4)) & 0xf;
54747 + }
54748 +
54749 + if (TOKEN_Q_DEPTH > 14) {
54750 + /* Fill intkn_seq[] from in_tkn_epnums[1] */
54751 + for (i=14; i < 22; i++)
54752 + intkn_seq[i] =
54753 + (in_tkn_epnums[2] >> ((7 - (i - 14)) * 4)) & 0xf;
54754 + }
54755 +
54756 + if (TOKEN_Q_DEPTH > 22) {
54757 + /* Fill intkn_seq[] from in_tkn_epnums[1] */
54758 + for (i=22; i < 30; i++)
54759 + intkn_seq[i] =
54760 + (in_tkn_epnums[3] >> ((7 - (i - 22)) * 4)) & 0xf;
54761 + }
54762 +
54763 + DWC_DEBUGPL(DBG_PCDV, "%s start=%d end=%d intkn_seq[]:\n", __func__,
54764 + start, end);
54765 + for (i=0; i<TOKEN_Q_DEPTH; i++)
54766 + DWC_DEBUGPL(DBG_PCDV,"%d\n", intkn_seq[i]);
54767 +
54768 + /* Update seqnum based on intkn_seq[] */
54769 + i = 0;
54770 + do {
54771 + seqnum[intkn_seq[ndx]] = i;
54772 + ndx++;
54773 + i++;
54774 + if (ndx == TOKEN_Q_DEPTH)
54775 + ndx = 0;
54776 + } while ( i < TOKEN_Q_DEPTH );
54777 +
54778 + /* Mark non active EP's in seqnum[] by 0xff */
54779 + for (i=0; i<=core_if->dev_if->num_in_eps; i++) {
54780 + if (core_if->nextep_seq[i] == 0xff )
54781 + seqnum[i] = 0xff;
54782 + }
54783 +
54784 + /* Sort seqnum[] */
54785 + sort_done = 0;
54786 + while (!sort_done) {
54787 + sort_done = 1;
54788 + for (i=0; i<core_if->dev_if->num_in_eps; i++) {
54789 + if (seqnum[i] > seqnum[i+1]) {
54790 + temp = seqnum[i];
54791 + seqnum[i] = seqnum[i+1];
54792 + seqnum[i+1] = temp;
54793 + sort_done = 0;
54794 + }
54795 + }
54796 + }
54797 +
54798 + ndx = start + seqnum[0];
54799 + if (ndx >= TOKEN_Q_DEPTH)
54800 + ndx = ndx % TOKEN_Q_DEPTH;
54801 + core_if->first_in_nextep_seq = intkn_seq[ndx];
54802 +
54803 + /* Update seqnum[] by EP numbers */
54804 + for (i=0; i<=core_if->dev_if->num_in_eps; i++) {
54805 + ndx = start + i;
54806 + if (seqnum[i] < 31) {
54807 + ndx = start + seqnum[i];
54808 + if (ndx >= TOKEN_Q_DEPTH)
54809 + ndx = ndx % TOKEN_Q_DEPTH;
54810 + seqnum[i] = intkn_seq[ndx];
54811 + } else {
54812 + if (seqnum[i] < 0xff) {
54813 + seqnum[i] = seqnum[i] - 31;
54814 + } else {
54815 + break;
54816 + }
54817 + }
54818 + }
54819 +
54820 + /* Update nextep_seq[] based on seqnum[] */
54821 + for (i=0; i<core_if->dev_if->num_in_eps; i++) {
54822 + if (seqnum[i] != 0xff) {
54823 + if (seqnum[i+1] != 0xff) {
54824 + core_if->nextep_seq[seqnum[i]] = seqnum[i+1];
54825 + } else {
54826 + core_if->nextep_seq[seqnum[i]] = core_if->first_in_nextep_seq;
54827 + break;
54828 + }
54829 + } else {
54830 + break;
54831 + }
54832 + }
54833 +
54834 + DWC_DEBUGPL(DBG_PCDV, "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
54835 + __func__, core_if->first_in_nextep_seq);
54836 + for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
54837 + DWC_DEBUGPL(DBG_PCDV,"%2d\n", core_if->nextep_seq[i]);
54838 + }
54839 +
54840 + /* Flush the Learning Queue */
54841 + resetctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->grstctl);
54842 + resetctl.b.intknqflsh = 1;
54843 + DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
54844 +
54845 +
54846 +}
54847 +
54848 +/**
54849 + * handle the IN EP disable interrupt.
54850 + */
54851 +static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t * pcd,
54852 + const uint32_t epnum)
54853 +{
54854 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
54855 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
54856 + deptsiz_data_t dieptsiz = {.d32 = 0 };
54857 + dctl_data_t dctl = {.d32 = 0 };
54858 + dwc_otg_pcd_ep_t *ep;
54859 + dwc_ep_t *dwc_ep;
54860 + gintmsk_data_t gintmsk_data;
54861 + depctl_data_t depctl;
54862 + uint32_t diepdma;
54863 + uint32_t remain_to_transfer = 0;
54864 + uint8_t i;
54865 + uint32_t xfer_size;
54866 +
54867 + ep = get_in_ep(pcd, epnum);
54868 + dwc_ep = &ep->dwc_ep;
54869 +
54870 + if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
54871 + dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
54872 + complete_ep(ep);
54873 + return;
54874 + }
54875 +
54876 + DWC_DEBUGPL(DBG_PCD, "diepctl%d=%0x\n", epnum,
54877 + DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl));
54878 + dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz);
54879 + depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
54880 +
54881 + DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
54882 + dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
54883 +
54884 + if ((core_if->start_predict == 0) || (depctl.b.eptype & 1)) {
54885 + if (ep->stopped) {
54886 + if (core_if->en_multiple_tx_fifo)
54887 + /* Flush the Tx FIFO */
54888 + dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
54889 + /* Clear the Global IN NP NAK */
54890 + dctl.d32 = 0;
54891 + dctl.b.cgnpinnak = 1;
54892 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
54893 + /* Restart the transaction */
54894 + if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
54895 + restart_transfer(pcd, epnum);
54896 + }
54897 + } else {
54898 + /* Restart the transaction */
54899 + if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
54900 + restart_transfer(pcd, epnum);
54901 + }
54902 + DWC_DEBUGPL(DBG_ANY, "STOPPED!!!\n");
54903 + }
54904 + return;
54905 + }
54906 +
54907 + if (core_if->start_predict > 2) { // NP IN EP
54908 + core_if->start_predict--;
54909 + return;
54910 + }
54911 +
54912 + core_if->start_predict--;
54913 +
54914 + if (core_if->start_predict == 1) { // All NP IN Ep's disabled now
54915 +
54916 + predict_nextep_seq(core_if);
54917 +
54918 + /* Update all active IN EP's NextEP field based of nextep_seq[] */
54919 + for ( i = 0; i <= core_if->dev_if->num_in_eps; i++) {
54920 + depctl.d32 =
54921 + DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
54922 + if (core_if->nextep_seq[i] != 0xff) { // Active NP IN EP
54923 + depctl.b.nextep = core_if->nextep_seq[i];
54924 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
54925 + }
54926 + }
54927 + /* Flush Shared NP TxFIFO */
54928 + dwc_otg_flush_tx_fifo(core_if, 0);
54929 + /* Rewind buffers */
54930 + if (!core_if->dma_desc_enable) {
54931 + i = core_if->first_in_nextep_seq;
54932 + do {
54933 + ep = get_in_ep(pcd, i);
54934 + dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
54935 + xfer_size = ep->dwc_ep.total_len - ep->dwc_ep.xfer_count;
54936 + if (xfer_size > ep->dwc_ep.maxxfer)
54937 + xfer_size = ep->dwc_ep.maxxfer;
54938 + depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
54939 + if (dieptsiz.b.pktcnt != 0) {
54940 + if (xfer_size == 0) {
54941 + remain_to_transfer = 0;
54942 + } else {
54943 + if ((xfer_size % ep->dwc_ep.maxpacket) == 0) {
54944 + remain_to_transfer =
54945 + dieptsiz.b.pktcnt * ep->dwc_ep.maxpacket;
54946 + } else {
54947 + remain_to_transfer = ((dieptsiz.b.pktcnt -1) * ep->dwc_ep.maxpacket)
54948 + + (xfer_size % ep->dwc_ep.maxpacket);
54949 + }
54950 + }
54951 + diepdma = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepdma);
54952 + dieptsiz.b.xfersize = remain_to_transfer;
54953 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, dieptsiz.d32);
54954 + diepdma = ep->dwc_ep.dma_addr + (xfer_size - remain_to_transfer);
54955 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, diepdma);
54956 + }
54957 + i = core_if->nextep_seq[i];
54958 + } while (i != core_if->first_in_nextep_seq);
54959 + } else { // dma_desc_enable
54960 + DWC_PRINTF("%s Learning Queue not supported in DDMA\n", __func__);
54961 + }
54962 +
54963 + /* Restart transfers in predicted sequences */
54964 + i = core_if->first_in_nextep_seq;
54965 + do {
54966 + dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
54967 + depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
54968 + if (dieptsiz.b.pktcnt != 0) {
54969 + depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
54970 + depctl.b.epena = 1;
54971 + depctl.b.cnak = 1;
54972 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
54973 + }
54974 + i = core_if->nextep_seq[i];
54975 + } while (i != core_if->first_in_nextep_seq);
54976 +
54977 + /* Clear the global non-periodic IN NAK handshake */
54978 + dctl.d32 = 0;
54979 + dctl.b.cgnpinnak = 1;
54980 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
54981 +
54982 + /* Unmask EP Mismatch interrupt */
54983 + gintmsk_data.d32 = 0;
54984 + gintmsk_data.b.epmismatch = 1;
54985 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk_data.d32);
54986 +
54987 + core_if->start_predict = 0;
54988 +
54989 + }
54990 +}
54991 +
54992 +/**
54993 + * Handler for the IN EP timeout handshake interrupt.
54994 + */
54995 +static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t * pcd,
54996 + const uint32_t epnum)
54997 +{
54998 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
54999 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
55000 +
55001 +#ifdef DEBUG
55002 + deptsiz_data_t dieptsiz = {.d32 = 0 };
55003 + uint32_t num = 0;
55004 +#endif
55005 + dctl_data_t dctl = {.d32 = 0 };
55006 + dwc_otg_pcd_ep_t *ep;
55007 +
55008 + gintmsk_data_t intr_mask = {.d32 = 0 };
55009 +
55010 + ep = get_in_ep(pcd, epnum);
55011 +
55012 + /* Disable the NP Tx Fifo Empty Interrrupt */
55013 + if (!core_if->dma_enable) {
55014 + intr_mask.b.nptxfempty = 1;
55015 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
55016 + intr_mask.d32, 0);
55017 + }
55018 + /** @todo NGS Check EP type.
55019 + * Implement for Periodic EPs */
55020 + /*
55021 + * Non-periodic EP
55022 + */
55023 + /* Enable the Global IN NAK Effective Interrupt */
55024 + intr_mask.b.ginnakeff = 1;
55025 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);
55026 +
55027 + /* Set Global IN NAK */
55028 + dctl.b.sgnpinnak = 1;
55029 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
55030 +
55031 + ep->stopped = 1;
55032 +
55033 +#ifdef DEBUG
55034 + dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[num]->dieptsiz);
55035 + DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
55036 + dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
55037 +#endif
55038 +
55039 +#ifdef DISABLE_PERIODIC_EP
55040 + /*
55041 + * Set the NAK bit for this EP to
55042 + * start the disable process.
55043 + */
55044 + diepctl.d32 = 0;
55045 + diepctl.b.snak = 1;
55046 + DWC_MODIFY_REG32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32,
55047 + diepctl.d32);
55048 + ep->disabling = 1;
55049 + ep->stopped = 1;
55050 +#endif
55051 +}
55052 +
55053 +/**
55054 + * Handler for the IN EP NAK interrupt.
55055 + */
55056 +static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t * pcd,
55057 + const uint32_t epnum)
55058 +{
55059 + /** @todo implement ISR */
55060 + dwc_otg_core_if_t *core_if;
55061 + diepmsk_data_t intr_mask = {.d32 = 0 };
55062 +
55063 + DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "IN EP NAK");
55064 + core_if = GET_CORE_IF(pcd);
55065 + intr_mask.b.nak = 1;
55066 +
55067 + if (core_if->multiproc_int_enable) {
55068 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
55069 + diepeachintmsk[epnum], intr_mask.d32, 0);
55070 + } else {
55071 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->diepmsk,
55072 + intr_mask.d32, 0);
55073 + }
55074 +
55075 + return 1;
55076 +}
55077 +
55078 +/**
55079 + * Handler for the OUT EP Babble interrupt.
55080 + */
55081 +static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t * pcd,
55082 + const uint32_t epnum)
55083 +{
55084 + /** @todo implement ISR */
55085 + dwc_otg_core_if_t *core_if;
55086 + doepmsk_data_t intr_mask = {.d32 = 0 };
55087 +
55088 + DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
55089 + "OUT EP Babble");
55090 + core_if = GET_CORE_IF(pcd);
55091 + intr_mask.b.babble = 1;
55092 +
55093 + if (core_if->multiproc_int_enable) {
55094 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
55095 + doepeachintmsk[epnum], intr_mask.d32, 0);
55096 + } else {
55097 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
55098 + intr_mask.d32, 0);
55099 + }
55100 +
55101 + return 1;
55102 +}
55103 +
55104 +/**
55105 + * Handler for the OUT EP NAK interrupt.
55106 + */
55107 +static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t * pcd,
55108 + const uint32_t epnum)
55109 +{
55110 + /** @todo implement ISR */
55111 + dwc_otg_core_if_t *core_if;
55112 + doepmsk_data_t intr_mask = {.d32 = 0 };
55113 +
55114 + DWC_DEBUGPL(DBG_ANY, "INTERRUPT Handler not implemented for %s\n", "OUT EP NAK");
55115 + core_if = GET_CORE_IF(pcd);
55116 + intr_mask.b.nak = 1;
55117 +
55118 + if (core_if->multiproc_int_enable) {
55119 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
55120 + doepeachintmsk[epnum], intr_mask.d32, 0);
55121 + } else {
55122 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
55123 + intr_mask.d32, 0);
55124 + }
55125 +
55126 + return 1;
55127 +}
55128 +
55129 +/**
55130 + * Handler for the OUT EP NYET interrupt.
55131 + */
55132 +static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t * pcd,
55133 + const uint32_t epnum)
55134 +{
55135 + /** @todo implement ISR */
55136 + dwc_otg_core_if_t *core_if;
55137 + doepmsk_data_t intr_mask = {.d32 = 0 };
55138 +
55139 + DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "OUT EP NYET");
55140 + core_if = GET_CORE_IF(pcd);
55141 + intr_mask.b.nyet = 1;
55142 +
55143 + if (core_if->multiproc_int_enable) {
55144 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
55145 + doepeachintmsk[epnum], intr_mask.d32, 0);
55146 + } else {
55147 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
55148 + intr_mask.d32, 0);
55149 + }
55150 +
55151 + return 1;
55152 +}
55153 +
55154 +/**
55155 + * This interrupt indicates that an IN EP has a pending Interrupt.
55156 + * The sequence for handling the IN EP interrupt is shown below:
55157 + * -# Read the Device All Endpoint Interrupt register
55158 + * -# Repeat the following for each IN EP interrupt bit set (from
55159 + * LSB to MSB).
55160 + * -# Read the Device Endpoint Interrupt (DIEPINTn) register
55161 + * -# If "Transfer Complete" call the request complete function
55162 + * -# If "Endpoint Disabled" complete the EP disable procedure.
55163 + * -# If "AHB Error Interrupt" log error
55164 + * -# If "Time-out Handshake" log error
55165 + * -# If "IN Token Received when TxFIFO Empty" write packet to Tx
55166 + * FIFO.
55167 + * -# If "IN Token EP Mismatch" (disable, this is handled by EP
55168 + * Mismatch Interrupt)
55169 + */
55170 +static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t * pcd)
55171 +{
55172 +#define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \
55173 +do { \
55174 + diepint_data_t diepint = {.d32=0}; \
55175 + diepint.b.__intr = 1; \
55176 + DWC_WRITE_REG32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \
55177 + diepint.d32); \
55178 +} while (0)
55179 +
55180 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
55181 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
55182 + diepint_data_t diepint = {.d32 = 0 };
55183 + depctl_data_t depctl = {.d32 = 0 };
55184 + uint32_t ep_intr;
55185 + uint32_t epnum = 0;
55186 + dwc_otg_pcd_ep_t *ep;
55187 + dwc_ep_t *dwc_ep;
55188 + gintmsk_data_t intr_mask = {.d32 = 0 };
55189 +
55190 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd);
55191 +
55192 + /* Read in the device interrupt bits */
55193 + ep_intr = dwc_otg_read_dev_all_in_ep_intr(core_if);
55194 +
55195 + /* Service the Device IN interrupts for each endpoint */
55196 + while (ep_intr) {
55197 + if (ep_intr & 0x1) {
55198 + uint32_t empty_msk;
55199 + /* Get EP pointer */
55200 + ep = get_in_ep(pcd, epnum);
55201 + dwc_ep = &ep->dwc_ep;
55202 +
55203 + depctl.d32 =
55204 + DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
55205 + empty_msk =
55206 + DWC_READ_REG32(&dev_if->
55207 + dev_global_regs->dtknqr4_fifoemptymsk);
55208 +
55209 + DWC_DEBUGPL(DBG_PCDV,
55210 + "IN EP INTERRUPT - %d\nepmty_msk - %8x diepctl - %8x\n",
55211 + epnum, empty_msk, depctl.d32);
55212 +
55213 + DWC_DEBUGPL(DBG_PCD,
55214 + "EP%d-%s: type=%d, mps=%d\n",
55215 + dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
55216 + dwc_ep->type, dwc_ep->maxpacket);
55217 +
55218 + diepint.d32 =
55219 + dwc_otg_read_dev_in_ep_intr(core_if, dwc_ep);
55220 +
55221 + DWC_DEBUGPL(DBG_PCDV,
55222 + "EP %d Interrupt Register - 0x%x\n", epnum,
55223 + diepint.d32);
55224 + /* Transfer complete */
55225 + if (diepint.b.xfercompl) {
55226 + /* Disable the NP Tx FIFO Empty
55227 + * Interrupt */
55228 + if (core_if->en_multiple_tx_fifo == 0) {
55229 + intr_mask.b.nptxfempty = 1;
55230 + DWC_MODIFY_REG32
55231 + (&core_if->core_global_regs->gintmsk,
55232 + intr_mask.d32, 0);
55233 + } else {
55234 + /* Disable the Tx FIFO Empty Interrupt for this EP */
55235 + uint32_t fifoemptymsk =
55236 + 0x1 << dwc_ep->num;
55237 + DWC_MODIFY_REG32(&core_if->
55238 + dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
55239 + fifoemptymsk, 0);
55240 + }
55241 + /* Clear the bit in DIEPINTn for this interrupt */
55242 + CLEAR_IN_EP_INTR(core_if, epnum, xfercompl);
55243 +
55244 + /* Complete the transfer */
55245 + if (epnum == 0) {
55246 + handle_ep0(pcd);
55247 + }
55248 +#ifdef DWC_EN_ISOC
55249 + else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
55250 + if (!ep->stopped)
55251 + complete_iso_ep(pcd, ep);
55252 + }
55253 +#endif /* DWC_EN_ISOC */
55254 +#ifdef DWC_UTE_PER_IO
55255 + else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
55256 + if (!ep->stopped)
55257 + complete_xiso_ep(ep);
55258 + }
55259 +#endif /* DWC_UTE_PER_IO */
55260 + else {
55261 + if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC &&
55262 + dwc_ep->bInterval > 1) {
55263 + dwc_ep->frame_num += dwc_ep->bInterval;
55264 + if (dwc_ep->frame_num > 0x3FFF)
55265 + {
55266 + dwc_ep->frm_overrun = 1;
55267 + dwc_ep->frame_num &= 0x3FFF;
55268 + } else
55269 + dwc_ep->frm_overrun = 0;
55270 + }
55271 + complete_ep(ep);
55272 + if(diepint.b.nak)
55273 + CLEAR_IN_EP_INTR(core_if, epnum, nak);
55274 + }
55275 + }
55276 + /* Endpoint disable */
55277 + if (diepint.b.epdisabled) {
55278 + DWC_DEBUGPL(DBG_ANY, "EP%d IN disabled\n",
55279 + epnum);
55280 + handle_in_ep_disable_intr(pcd, epnum);
55281 +
55282 + /* Clear the bit in DIEPINTn for this interrupt */
55283 + CLEAR_IN_EP_INTR(core_if, epnum, epdisabled);
55284 + }
55285 + /* AHB Error */
55286 + if (diepint.b.ahberr) {
55287 + DWC_ERROR("EP%d IN AHB Error\n", epnum);
55288 + /* Clear the bit in DIEPINTn for this interrupt */
55289 + CLEAR_IN_EP_INTR(core_if, epnum, ahberr);
55290 + }
55291 + /* TimeOUT Handshake (non-ISOC IN EPs) */
55292 + if (diepint.b.timeout) {
55293 + DWC_ERROR("EP%d IN Time-out\n", epnum);
55294 + handle_in_ep_timeout_intr(pcd, epnum);
55295 +
55296 + CLEAR_IN_EP_INTR(core_if, epnum, timeout);
55297 + }
55298 + /** IN Token received with TxF Empty */
55299 + if (diepint.b.intktxfemp) {
55300 + DWC_DEBUGPL(DBG_ANY,
55301 + "EP%d IN TKN TxFifo Empty\n",
55302 + epnum);
55303 + if (!ep->stopped && epnum != 0) {
55304 +
55305 + diepmsk_data_t diepmsk = {.d32 = 0 };
55306 + diepmsk.b.intktxfemp = 1;
55307 +
55308 + if (core_if->multiproc_int_enable) {
55309 + DWC_MODIFY_REG32
55310 + (&dev_if->dev_global_regs->diepeachintmsk
55311 + [epnum], diepmsk.d32, 0);
55312 + } else {
55313 + DWC_MODIFY_REG32
55314 + (&dev_if->dev_global_regs->diepmsk,
55315 + diepmsk.d32, 0);
55316 + }
55317 + } else if (core_if->dma_desc_enable
55318 + && epnum == 0
55319 + && pcd->ep0state ==
55320 + EP0_OUT_STATUS_PHASE) {
55321 + // EP0 IN set STALL
55322 + depctl.d32 =
55323 + DWC_READ_REG32(&dev_if->in_ep_regs
55324 + [epnum]->diepctl);
55325 +
55326 + /* set the disable and stall bits */
55327 + if (depctl.b.epena) {
55328 + depctl.b.epdis = 1;
55329 + }
55330 + depctl.b.stall = 1;
55331 + DWC_WRITE_REG32(&dev_if->in_ep_regs
55332 + [epnum]->diepctl,
55333 + depctl.d32);
55334 + }
55335 + CLEAR_IN_EP_INTR(core_if, epnum, intktxfemp);
55336 + }
55337 + /** IN Token Received with EP mismatch */
55338 + if (diepint.b.intknepmis) {
55339 + DWC_DEBUGPL(DBG_ANY,
55340 + "EP%d IN TKN EP Mismatch\n", epnum);
55341 + CLEAR_IN_EP_INTR(core_if, epnum, intknepmis);
55342 + }
55343 + /** IN Endpoint NAK Effective */
55344 + if (diepint.b.inepnakeff) {
55345 + DWC_DEBUGPL(DBG_ANY,
55346 + "EP%d IN EP NAK Effective\n",
55347 + epnum);
55348 + /* Periodic EP */
55349 + if (ep->disabling) {
55350 + depctl.d32 = 0;
55351 + depctl.b.snak = 1;
55352 + depctl.b.epdis = 1;
55353 + DWC_MODIFY_REG32(&dev_if->in_ep_regs
55354 + [epnum]->diepctl,
55355 + depctl.d32,
55356 + depctl.d32);
55357 + }
55358 + CLEAR_IN_EP_INTR(core_if, epnum, inepnakeff);
55359 +
55360 + }
55361 +
55362 + /** IN EP Tx FIFO Empty Intr */
55363 + if (diepint.b.emptyintr) {
55364 + DWC_DEBUGPL(DBG_ANY,
55365 + "EP%d Tx FIFO Empty Intr \n",
55366 + epnum);
55367 + write_empty_tx_fifo(pcd, epnum);
55368 +
55369 + CLEAR_IN_EP_INTR(core_if, epnum, emptyintr);
55370 +
55371 + }
55372 +
55373 + /** IN EP BNA Intr */
55374 + if (diepint.b.bna) {
55375 + CLEAR_IN_EP_INTR(core_if, epnum, bna);
55376 + if (core_if->dma_desc_enable) {
55377 +#ifdef DWC_EN_ISOC
55378 + if (dwc_ep->type ==
55379 + DWC_OTG_EP_TYPE_ISOC) {
55380 + /*
55381 + * This checking is performed to prevent first "false" BNA
55382 + * handling occuring right after reconnect
55383 + */
55384 + if (dwc_ep->next_frame !=
55385 + 0xffffffff)
55386 + dwc_otg_pcd_handle_iso_bna(ep);
55387 + } else
55388 +#endif /* DWC_EN_ISOC */
55389 + {
55390 + dwc_otg_pcd_handle_noniso_bna(ep);
55391 + }
55392 + }
55393 + }
55394 + /* NAK Interrutp */
55395 + if (diepint.b.nak) {
55396 + DWC_DEBUGPL(DBG_ANY, "EP%d IN NAK Interrupt\n",
55397 + epnum);
55398 + if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
55399 + depctl_data_t depctl;
55400 + if (ep->dwc_ep.frame_num == 0xFFFFFFFF) {
55401 + ep->dwc_ep.frame_num = core_if->frame_num;
55402 + if (ep->dwc_ep.bInterval > 1) {
55403 + depctl.d32 = 0;
55404 + depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
55405 + if (ep->dwc_ep.frame_num & 0x1) {
55406 + depctl.b.setd1pid = 1;
55407 + depctl.b.setd0pid = 0;
55408 + } else {
55409 + depctl.b.setd0pid = 1;
55410 + depctl.b.setd1pid = 0;
55411 + }
55412 + DWC_WRITE_REG32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32);
55413 + }
55414 + start_next_request(ep);
55415 + }
55416 + ep->dwc_ep.frame_num += ep->dwc_ep.bInterval;
55417 + if (dwc_ep->frame_num > 0x3FFF) {
55418 + dwc_ep->frm_overrun = 1;
55419 + dwc_ep->frame_num &= 0x3FFF;
55420 + } else
55421 + dwc_ep->frm_overrun = 0;
55422 + }
55423 +
55424 + CLEAR_IN_EP_INTR(core_if, epnum, nak);
55425 + }
55426 + }
55427 + epnum++;
55428 + ep_intr >>= 1;
55429 + }
55430 +
55431 + return 1;
55432 +#undef CLEAR_IN_EP_INTR
55433 +}
55434 +
55435 +/**
55436 + * This interrupt indicates that an OUT EP has a pending Interrupt.
55437 + * The sequence for handling the OUT EP interrupt is shown below:
55438 + * -# Read the Device All Endpoint Interrupt register
55439 + * -# Repeat the following for each OUT EP interrupt bit set (from
55440 + * LSB to MSB).
55441 + * -# Read the Device Endpoint Interrupt (DOEPINTn) register
55442 + * -# If "Transfer Complete" call the request complete function
55443 + * -# If "Endpoint Disabled" complete the EP disable procedure.
55444 + * -# If "AHB Error Interrupt" log error
55445 + * -# If "Setup Phase Done" process Setup Packet (See Standard USB
55446 + * Command Processing)
55447 + */
55448 +static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t * pcd)
55449 +{
55450 +#define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \
55451 +do { \
55452 + doepint_data_t doepint = {.d32=0}; \
55453 + doepint.b.__intr = 1; \
55454 + DWC_WRITE_REG32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \
55455 + doepint.d32); \
55456 +} while (0)
55457 +
55458 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
55459 + uint32_t ep_intr;
55460 + doepint_data_t doepint = {.d32 = 0 };
55461 + uint32_t epnum = 0;
55462 + dwc_otg_pcd_ep_t *ep;
55463 + dwc_ep_t *dwc_ep;
55464 + dctl_data_t dctl = {.d32 = 0 };
55465 + gintmsk_data_t gintmsk = {.d32 = 0 };
55466 +
55467 +
55468 + DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
55469 +
55470 + /* Read in the device interrupt bits */
55471 + ep_intr = dwc_otg_read_dev_all_out_ep_intr(core_if);
55472 +
55473 + while (ep_intr) {
55474 + if (ep_intr & 0x1) {
55475 + /* Get EP pointer */
55476 + ep = get_out_ep(pcd, epnum);
55477 + dwc_ep = &ep->dwc_ep;
55478 +
55479 +#ifdef VERBOSE
55480 + DWC_DEBUGPL(DBG_PCDV,
55481 + "EP%d-%s: type=%d, mps=%d\n",
55482 + dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
55483 + dwc_ep->type, dwc_ep->maxpacket);
55484 +#endif
55485 + doepint.d32 =
55486 + dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep);
55487 + /* Moved this interrupt upper due to core deffect of asserting
55488 + * OUT EP 0 xfercompl along with stsphsrcvd in BDMA */
55489 + if (doepint.b.stsphsercvd) {
55490 + deptsiz0_data_t deptsiz;
55491 + CLEAR_OUT_EP_INTR(core_if, epnum, stsphsercvd);
55492 + deptsiz.d32 =
55493 + DWC_READ_REG32(&core_if->dev_if->
55494 + out_ep_regs[0]->doeptsiz);
55495 + if (core_if->snpsid >= OTG_CORE_REV_3_00a
55496 + && core_if->dma_enable
55497 + && core_if->dma_desc_enable == 0
55498 + && doepint.b.xfercompl
55499 + && deptsiz.b.xfersize == 24) {
55500 + CLEAR_OUT_EP_INTR(core_if, epnum,
55501 + xfercompl);
55502 + doepint.b.xfercompl = 0;
55503 + ep0_out_start(core_if, pcd);
55504 + }
55505 + if ((core_if->dma_desc_enable) ||
55506 + (core_if->dma_enable
55507 + && core_if->snpsid >=
55508 + OTG_CORE_REV_3_00a)) {
55509 + do_setup_in_status_phase(pcd);
55510 + }
55511 + }
55512 + /* Transfer complete */
55513 + if (doepint.b.xfercompl) {
55514 +
55515 + if (epnum == 0) {
55516 + /* Clear the bit in DOEPINTn for this interrupt */
55517 + CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl);
55518 + if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
55519 + DWC_DEBUGPL(DBG_PCDV, "DOEPINT=%x doepint=%x\n",
55520 + DWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepint),
55521 + doepint.d32);
55522 + DWC_DEBUGPL(DBG_PCDV, "DOEPCTL=%x \n",
55523 + DWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepctl));
55524 +
55525 + if (core_if->snpsid >= OTG_CORE_REV_3_00a
55526 + && core_if->dma_enable == 0) {
55527 + doepint_data_t doepint;
55528 + doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
55529 + out_ep_regs[0]->doepint);
55530 + if (pcd->ep0state == EP0_IDLE && doepint.b.sr) {
55531 + CLEAR_OUT_EP_INTR(core_if, epnum, sr);
55532 + goto exit_xfercompl;
55533 + }
55534 + }
55535 + /* In case of DDMA look at SR bit to go to the Data Stage */
55536 + if (core_if->dma_desc_enable) {
55537 + dev_dma_desc_sts_t status = {.d32 = 0};
55538 + if (pcd->ep0state == EP0_IDLE) {
55539 + status.d32 = core_if->dev_if->setup_desc_addr[core_if->
55540 + dev_if->setup_desc_index]->status.d32;
55541 + if(pcd->data_terminated) {
55542 + pcd->data_terminated = 0;
55543 + status.d32 = core_if->dev_if->out_desc_addr->status.d32;
55544 + dwc_memcpy(&pcd->setup_pkt->req, pcd->backup_buf, 8);
55545 + }
55546 + if (status.b.sr) {
55547 + if (doepint.b.setup) {
55548 + DWC_DEBUGPL(DBG_PCDV, "DMA DESC EP0_IDLE SR=1 setup=1\n");
55549 + /* Already started data stage, clear setup */
55550 + CLEAR_OUT_EP_INTR(core_if, epnum, setup);
55551 + doepint.b.setup = 0;
55552 + handle_ep0(pcd);
55553 + /* Prepare for more setup packets */
55554 + if (pcd->ep0state == EP0_IN_STATUS_PHASE ||
55555 + pcd->ep0state == EP0_IN_DATA_PHASE) {
55556 + ep0_out_start(core_if, pcd);
55557 + }
55558 +
55559 + goto exit_xfercompl;
55560 + } else {
55561 + /* Prepare for more setup packets */
55562 + DWC_DEBUGPL(DBG_PCDV,
55563 + "EP0_IDLE SR=1 setup=0 new setup comes\n");
55564 + ep0_out_start(core_if, pcd);
55565 + }
55566 + }
55567 + } else {
55568 + dwc_otg_pcd_request_t *req;
55569 + dev_dma_desc_sts_t status = {.d32 = 0};
55570 + diepint_data_t diepint0;
55571 + diepint0.d32 = DWC_READ_REG32(&core_if->dev_if->
55572 + in_ep_regs[0]->diepint);
55573 +
55574 + if (pcd->ep0state == EP0_STALL || pcd->ep0state == EP0_DISCONNECT) {
55575 + DWC_ERROR("EP0 is stalled/disconnected\n");
55576 + }
55577 +
55578 + /* Clear IN xfercompl if set */
55579 + if (diepint0.b.xfercompl && (pcd->ep0state == EP0_IN_STATUS_PHASE
55580 + || pcd->ep0state == EP0_IN_DATA_PHASE)) {
55581 + DWC_WRITE_REG32(&core_if->dev_if->
55582 + in_ep_regs[0]->diepint, diepint0.d32);
55583 + }
55584 +
55585 + status.d32 = core_if->dev_if->setup_desc_addr[core_if->
55586 + dev_if->setup_desc_index]->status.d32;
55587 +
55588 + if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len
55589 + && (pcd->ep0state == EP0_OUT_DATA_PHASE))
55590 + status.d32 = core_if->dev_if->out_desc_addr->status.d32;
55591 + if (pcd->ep0state == EP0_OUT_STATUS_PHASE)
55592 + status.d32 = core_if->dev_if->
55593 + out_desc_addr->status.d32;
55594 +
55595 + if (status.b.sr) {
55596 + if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
55597 + DWC_DEBUGPL(DBG_PCDV, "Request queue empty!!\n");
55598 + } else {
55599 + DWC_DEBUGPL(DBG_PCDV, "complete req!!\n");
55600 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
55601 + if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len &&
55602 + pcd->ep0state == EP0_OUT_DATA_PHASE) {
55603 + /* Read arrived setup packet from req->buf */
55604 + dwc_memcpy(&pcd->setup_pkt->req,
55605 + req->buf + ep->dwc_ep.xfer_count, 8);
55606 + }
55607 + req->actual = ep->dwc_ep.xfer_count;
55608 + dwc_otg_request_done(ep, req, -ECONNRESET);
55609 + ep->dwc_ep.start_xfer_buff = 0;
55610 + ep->dwc_ep.xfer_buff = 0;
55611 + ep->dwc_ep.xfer_len = 0;
55612 + }
55613 + pcd->ep0state = EP0_IDLE;
55614 + if (doepint.b.setup) {
55615 + DWC_DEBUGPL(DBG_PCDV, "EP0_IDLE SR=1 setup=1\n");
55616 + /* Data stage started, clear setup */
55617 + CLEAR_OUT_EP_INTR(core_if, epnum, setup);
55618 + doepint.b.setup = 0;
55619 + handle_ep0(pcd);
55620 + /* Prepare for setup packets if ep0in was enabled*/
55621 + if (pcd->ep0state == EP0_IN_STATUS_PHASE) {
55622 + ep0_out_start(core_if, pcd);
55623 + }
55624 +
55625 + goto exit_xfercompl;
55626 + } else {
55627 + /* Prepare for more setup packets */
55628 + DWC_DEBUGPL(DBG_PCDV,
55629 + "EP0_IDLE SR=1 setup=0 new setup comes 2\n");
55630 + ep0_out_start(core_if, pcd);
55631 + }
55632 + }
55633 + }
55634 + }
55635 + if (core_if->snpsid >= OTG_CORE_REV_2_94a && core_if->dma_enable
55636 + && core_if->dma_desc_enable == 0) {
55637 + doepint_data_t doepint_temp = {.d32 = 0};
55638 + deptsiz0_data_t doeptsize0 = {.d32 = 0 };
55639 + doepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if->
55640 + out_ep_regs[ep->dwc_ep.num]->doepint);
55641 + doeptsize0.d32 = DWC_READ_REG32(&core_if->dev_if->
55642 + out_ep_regs[ep->dwc_ep.num]->doeptsiz);
55643 + if (pcd->ep0state == EP0_IDLE) {
55644 + if (doepint_temp.b.sr) {
55645 + CLEAR_OUT_EP_INTR(core_if, epnum, sr);
55646 + }
55647 + doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
55648 + out_ep_regs[0]->doepint);
55649 + if (doeptsize0.b.supcnt == 3) {
55650 + DWC_DEBUGPL(DBG_ANY, "Rolling over!!!!!!!\n");
55651 + ep->dwc_ep.stp_rollover = 1;
55652 + }
55653 + if (doepint.b.setup) {
55654 +retry:
55655 + /* Already started data stage, clear setup */
55656 + CLEAR_OUT_EP_INTR(core_if, epnum, setup);
55657 + doepint.b.setup = 0;
55658 + handle_ep0(pcd);
55659 + ep->dwc_ep.stp_rollover = 0;
55660 + /* Prepare for more setup packets */
55661 + if (pcd->ep0state == EP0_IN_STATUS_PHASE ||
55662 + pcd->ep0state == EP0_IN_DATA_PHASE) {
55663 + ep0_out_start(core_if, pcd);
55664 + }
55665 + goto exit_xfercompl;
55666 + } else {
55667 + /* Prepare for more setup packets */
55668 + DWC_DEBUGPL(DBG_ANY,
55669 + "EP0_IDLE SR=1 setup=0 new setup comes\n");
55670 + doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
55671 + out_ep_regs[0]->doepint);
55672 + if(doepint.b.setup)
55673 + goto retry;
55674 + ep0_out_start(core_if, pcd);
55675 + }
55676 + } else {
55677 + dwc_otg_pcd_request_t *req;
55678 + diepint_data_t diepint0 = {.d32 = 0};
55679 + doepint_data_t doepint_temp = {.d32 = 0};
55680 + depctl_data_t diepctl0;
55681 + diepint0.d32 = DWC_READ_REG32(&core_if->dev_if->
55682 + in_ep_regs[0]->diepint);
55683 + diepctl0.d32 = DWC_READ_REG32(&core_if->dev_if->
55684 + in_ep_regs[0]->diepctl);
55685 +
55686 + if (pcd->ep0state == EP0_IN_DATA_PHASE
55687 + || pcd->ep0state == EP0_IN_STATUS_PHASE) {
55688 + if (diepint0.b.xfercompl) {
55689 + DWC_WRITE_REG32(&core_if->dev_if->
55690 + in_ep_regs[0]->diepint, diepint0.d32);
55691 + }
55692 + if (diepctl0.b.epena) {
55693 + diepint_data_t diepint = {.d32 = 0};
55694 + diepctl0.b.snak = 1;
55695 + DWC_WRITE_REG32(&core_if->dev_if->
55696 + in_ep_regs[0]->diepctl, diepctl0.d32);
55697 + do {
55698 + dwc_udelay(10);
55699 + diepint.d32 = DWC_READ_REG32(&core_if->dev_if->
55700 + in_ep_regs[0]->diepint);
55701 + } while (!diepint.b.inepnakeff);
55702 + diepint.b.inepnakeff = 1;
55703 + DWC_WRITE_REG32(&core_if->dev_if->
55704 + in_ep_regs[0]->diepint, diepint.d32);
55705 + diepctl0.d32 = 0;
55706 + diepctl0.b.epdis = 1;
55707 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl,
55708 + diepctl0.d32);
55709 + do {
55710 + dwc_udelay(10);
55711 + diepint.d32 = DWC_READ_REG32(&core_if->dev_if->
55712 + in_ep_regs[0]->diepint);
55713 + } while (!diepint.b.epdisabled);
55714 + diepint.b.epdisabled = 1;
55715 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepint,
55716 + diepint.d32);
55717 + }
55718 + }
55719 + doepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if->
55720 + out_ep_regs[ep->dwc_ep.num]->doepint);
55721 + if (doepint_temp.b.sr) {
55722 + CLEAR_OUT_EP_INTR(core_if, epnum, sr);
55723 + if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
55724 + DWC_DEBUGPL(DBG_PCDV, "Request queue empty!!\n");
55725 + } else {
55726 + DWC_DEBUGPL(DBG_PCDV, "complete req!!\n");
55727 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
55728 + if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len &&
55729 + pcd->ep0state == EP0_OUT_DATA_PHASE) {
55730 + /* Read arrived setup packet from req->buf */
55731 + dwc_memcpy(&pcd->setup_pkt->req,
55732 + req->buf + ep->dwc_ep.xfer_count, 8);
55733 + }
55734 + req->actual = ep->dwc_ep.xfer_count;
55735 + dwc_otg_request_done(ep, req, -ECONNRESET);
55736 + ep->dwc_ep.start_xfer_buff = 0;
55737 + ep->dwc_ep.xfer_buff = 0;
55738 + ep->dwc_ep.xfer_len = 0;
55739 + }
55740 + pcd->ep0state = EP0_IDLE;
55741 + if (doepint.b.setup) {
55742 + DWC_DEBUGPL(DBG_PCDV, "EP0_IDLE SR=1 setup=1\n");
55743 + /* Data stage started, clear setup */
55744 + CLEAR_OUT_EP_INTR(core_if, epnum, setup);
55745 + doepint.b.setup = 0;
55746 + handle_ep0(pcd);
55747 + /* Prepare for setup packets if ep0in was enabled*/
55748 + if (pcd->ep0state == EP0_IN_STATUS_PHASE) {
55749 + ep0_out_start(core_if, pcd);
55750 + }
55751 + goto exit_xfercompl;
55752 + } else {
55753 + /* Prepare for more setup packets */
55754 + DWC_DEBUGPL(DBG_PCDV,
55755 + "EP0_IDLE SR=1 setup=0 new setup comes 2\n");
55756 + ep0_out_start(core_if, pcd);
55757 + }
55758 + }
55759 + }
55760 + }
55761 + if (core_if->dma_enable == 0 || pcd->ep0state != EP0_IDLE)
55762 + handle_ep0(pcd);
55763 +exit_xfercompl:
55764 + DWC_DEBUGPL(DBG_PCDV, "DOEPINT=%x doepint=%x\n",
55765 + dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep), doepint.d32);
55766 + } else {
55767 + if (core_if->dma_desc_enable == 0
55768 + || pcd->ep0state != EP0_IDLE)
55769 + handle_ep0(pcd);
55770 + }
55771 +#ifdef DWC_EN_ISOC
55772 + } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
55773 + if (doepint.b.pktdrpsts == 0) {
55774 + /* Clear the bit in DOEPINTn for this interrupt */
55775 + CLEAR_OUT_EP_INTR(core_if,
55776 + epnum,
55777 + xfercompl);
55778 + complete_iso_ep(pcd, ep);
55779 + } else {
55780 +
55781 + doepint_data_t doepint = {.d32 = 0 };
55782 + doepint.b.xfercompl = 1;
55783 + doepint.b.pktdrpsts = 1;
55784 + DWC_WRITE_REG32
55785 + (&core_if->dev_if->out_ep_regs
55786 + [epnum]->doepint,
55787 + doepint.d32);
55788 + if (handle_iso_out_pkt_dropped
55789 + (core_if, dwc_ep)) {
55790 + complete_iso_ep(pcd,
55791 + ep);
55792 + }
55793 + }
55794 +#endif /* DWC_EN_ISOC */
55795 +#ifdef DWC_UTE_PER_IO
55796 + } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
55797 + CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl);
55798 + if (!ep->stopped)
55799 + complete_xiso_ep(ep);
55800 +#endif /* DWC_UTE_PER_IO */
55801 + } else {
55802 + /* Clear the bit in DOEPINTn for this interrupt */
55803 + CLEAR_OUT_EP_INTR(core_if, epnum,
55804 + xfercompl);
55805 +
55806 + if (core_if->core_params->dev_out_nak) {
55807 + DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[epnum]);
55808 + pcd->core_if->ep_xfer_info[epnum].state = 0;
55809 +#ifdef DEBUG
55810 + print_memory_payload(pcd, dwc_ep);
55811 +#endif
55812 + }
55813 + complete_ep(ep);
55814 + }
55815 +
55816 + }
55817 +
55818 + /* Endpoint disable */
55819 + if (doepint.b.epdisabled) {
55820 +
55821 + /* Clear the bit in DOEPINTn for this interrupt */
55822 + CLEAR_OUT_EP_INTR(core_if, epnum, epdisabled);
55823 + if (core_if->core_params->dev_out_nak) {
55824 +#ifdef DEBUG
55825 + print_memory_payload(pcd, dwc_ep);
55826 +#endif
55827 + /* In case of timeout condition */
55828 + if (core_if->ep_xfer_info[epnum].state == 2) {
55829 + dctl.d32 = DWC_READ_REG32(&core_if->dev_if->
55830 + dev_global_regs->dctl);
55831 + dctl.b.cgoutnak = 1;
55832 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
55833 + dctl.d32);
55834 + /* Unmask goutnakeff interrupt which was masked
55835 + * during handle nak out interrupt */
55836 + gintmsk.b.goutnakeff = 1;
55837 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
55838 + 0, gintmsk.d32);
55839 +
55840 + complete_ep(ep);
55841 + }
55842 + }
55843 + if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
55844 + {
55845 + dctl_data_t dctl;
55846 + gintmsk_data_t intr_mask = {.d32 = 0};
55847 + dwc_otg_pcd_request_t *req = 0;
55848 +
55849 + dctl.d32 = DWC_READ_REG32(&core_if->dev_if->
55850 + dev_global_regs->dctl);
55851 + dctl.b.cgoutnak = 1;
55852 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
55853 + dctl.d32);
55854 +
55855 + intr_mask.d32 = 0;
55856 + intr_mask.b.incomplisoout = 1;
55857 +
55858 + /* Get any pending requests */
55859 + if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
55860 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
55861 + if (!req) {
55862 + DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
55863 + } else {
55864 + dwc_otg_request_done(ep, req, 0);
55865 + start_next_request(ep);
55866 + }
55867 + } else {
55868 + DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
55869 + }
55870 + }
55871 + }
55872 + /* AHB Error */
55873 + if (doepint.b.ahberr) {
55874 + DWC_ERROR("EP%d OUT AHB Error\n", epnum);
55875 + DWC_ERROR("EP%d DEPDMA=0x%08x \n",
55876 + epnum, core_if->dev_if->out_ep_regs[epnum]->doepdma);
55877 + CLEAR_OUT_EP_INTR(core_if, epnum, ahberr);
55878 + }
55879 + /* Setup Phase Done (contorl EPs) */
55880 + if (doepint.b.setup) {
55881 +#ifdef DEBUG_EP0
55882 + DWC_DEBUGPL(DBG_PCD, "EP%d SETUP Done\n", epnum);
55883 +#endif
55884 + CLEAR_OUT_EP_INTR(core_if, epnum, setup);
55885 +
55886 + handle_ep0(pcd);
55887 + }
55888 +
55889 + /** OUT EP BNA Intr */
55890 + if (doepint.b.bna) {
55891 + CLEAR_OUT_EP_INTR(core_if, epnum, bna);
55892 + if (core_if->dma_desc_enable) {
55893 +#ifdef DWC_EN_ISOC
55894 + if (dwc_ep->type ==
55895 + DWC_OTG_EP_TYPE_ISOC) {
55896 + /*
55897 + * This checking is performed to prevent first "false" BNA
55898 + * handling occuring right after reconnect
55899 + */
55900 + if (dwc_ep->next_frame !=
55901 + 0xffffffff)
55902 + dwc_otg_pcd_handle_iso_bna(ep);
55903 + } else
55904 +#endif /* DWC_EN_ISOC */
55905 + {
55906 + dwc_otg_pcd_handle_noniso_bna(ep);
55907 + }
55908 + }
55909 + }
55910 + /* Babble Interrupt */
55911 + if (doepint.b.babble) {
55912 + DWC_DEBUGPL(DBG_ANY, "EP%d OUT Babble\n",
55913 + epnum);
55914 + handle_out_ep_babble_intr(pcd, epnum);
55915 +
55916 + CLEAR_OUT_EP_INTR(core_if, epnum, babble);
55917 + }
55918 + if (doepint.b.outtknepdis) {
55919 + DWC_DEBUGPL(DBG_ANY, "EP%d OUT Token received when EP is \
55920 + disabled\n",epnum);
55921 + if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
55922 + doepmsk_data_t doepmsk = {.d32 = 0};
55923 + ep->dwc_ep.frame_num = core_if->frame_num;
55924 + if (ep->dwc_ep.bInterval > 1) {
55925 + depctl_data_t depctl;
55926 + depctl.d32 = DWC_READ_REG32(&core_if->dev_if->
55927 + out_ep_regs[epnum]->doepctl);
55928 + if (ep->dwc_ep.frame_num & 0x1) {
55929 + depctl.b.setd1pid = 1;
55930 + depctl.b.setd0pid = 0;
55931 + } else {
55932 + depctl.b.setd0pid = 1;
55933 + depctl.b.setd1pid = 0;
55934 + }
55935 + DWC_WRITE_REG32(&core_if->dev_if->
55936 + out_ep_regs[epnum]->doepctl, depctl.d32);
55937 + }
55938 + start_next_request(ep);
55939 + doepmsk.b.outtknepdis = 1;
55940 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
55941 + doepmsk.d32, 0);
55942 + }
55943 + CLEAR_OUT_EP_INTR(core_if, epnum, outtknepdis);
55944 + }
55945 +
55946 + /* NAK Interrutp */
55947 + if (doepint.b.nak) {
55948 + DWC_DEBUGPL(DBG_ANY, "EP%d OUT NAK\n", epnum);
55949 + handle_out_ep_nak_intr(pcd, epnum);
55950 +
55951 + CLEAR_OUT_EP_INTR(core_if, epnum, nak);
55952 + }
55953 + /* NYET Interrutp */
55954 + if (doepint.b.nyet) {
55955 + DWC_DEBUGPL(DBG_ANY, "EP%d OUT NYET\n", epnum);
55956 + handle_out_ep_nyet_intr(pcd, epnum);
55957 +
55958 + CLEAR_OUT_EP_INTR(core_if, epnum, nyet);
55959 + }
55960 + }
55961 +
55962 + epnum++;
55963 + ep_intr >>= 1;
55964 + }
55965 +
55966 + return 1;
55967 +
55968 +#undef CLEAR_OUT_EP_INTR
55969 +}
55970 +static int drop_transfer(uint32_t trgt_fr, uint32_t curr_fr, uint8_t frm_overrun)
55971 +{
55972 + int retval = 0;
55973 + if(!frm_overrun && curr_fr >= trgt_fr)
55974 + retval = 1;
55975 + else if (frm_overrun
55976 + && (curr_fr >= trgt_fr && ((curr_fr - trgt_fr) < 0x3FFF / 2)))
55977 + retval = 1;
55978 + return retval;
55979 +}
55980 +/**
55981 + * Incomplete ISO IN Transfer Interrupt.
55982 + * This interrupt indicates one of the following conditions occurred
55983 + * while transmitting an ISOC transaction.
55984 + * - Corrupted IN Token for ISOC EP.
55985 + * - Packet not complete in FIFO.
55986 + * The follow actions will be taken:
55987 + * -# Determine the EP
55988 + * -# Set incomplete flag in dwc_ep structure
55989 + * -# Disable EP; when "Endpoint Disabled" interrupt is received
55990 + * Flush FIFO
55991 + */
55992 +int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t * pcd)
55993 +{
55994 + gintsts_data_t gintsts;
55995 +
55996 +#ifdef DWC_EN_ISOC
55997 + dwc_otg_dev_if_t *dev_if;
55998 + deptsiz_data_t deptsiz = {.d32 = 0 };
55999 + depctl_data_t depctl = {.d32 = 0 };
56000 + dsts_data_t dsts = {.d32 = 0 };
56001 + dwc_ep_t *dwc_ep;
56002 + int i;
56003 +
56004 + dev_if = GET_CORE_IF(pcd)->dev_if;
56005 +
56006 + for (i = 1; i <= dev_if->num_in_eps; ++i) {
56007 + dwc_ep = &pcd->in_ep[i].dwc_ep;
56008 + if (dwc_ep->active && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
56009 + deptsiz.d32 =
56010 + DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
56011 + depctl.d32 =
56012 + DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
56013 +
56014 + if (depctl.b.epdis && deptsiz.d32) {
56015 + set_current_pkt_info(GET_CORE_IF(pcd), dwc_ep);
56016 + if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
56017 + dwc_ep->cur_pkt = 0;
56018 + dwc_ep->proc_buf_num =
56019 + (dwc_ep->proc_buf_num ^ 1) & 0x1;
56020 +
56021 + if (dwc_ep->proc_buf_num) {
56022 + dwc_ep->cur_pkt_addr =
56023 + dwc_ep->xfer_buff1;
56024 + dwc_ep->cur_pkt_dma_addr =
56025 + dwc_ep->dma_addr1;
56026 + } else {
56027 + dwc_ep->cur_pkt_addr =
56028 + dwc_ep->xfer_buff0;
56029 + dwc_ep->cur_pkt_dma_addr =
56030 + dwc_ep->dma_addr0;
56031 + }
56032 +
56033 + }
56034 +
56035 + dsts.d32 =
56036 + DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
56037 + dev_global_regs->dsts);
56038 + dwc_ep->next_frame = dsts.b.soffn;
56039 +
56040 + dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
56041 + (pcd),
56042 + dwc_ep);
56043 + }
56044 + }
56045 + }
56046 +
56047 +#else
56048 + depctl_data_t depctl = {.d32 = 0 };
56049 + dwc_ep_t *dwc_ep;
56050 + dwc_otg_dev_if_t *dev_if;
56051 + int i;
56052 + dev_if = GET_CORE_IF(pcd)->dev_if;
56053 +
56054 + DWC_DEBUGPL(DBG_PCD,"Incomplete ISO IN \n");
56055 +
56056 + for (i = 1; i <= dev_if->num_in_eps; ++i) {
56057 + dwc_ep = &pcd->in_ep[i-1].dwc_ep;
56058 + depctl.d32 =
56059 + DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
56060 + if (depctl.b.epena && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
56061 + if (drop_transfer(dwc_ep->frame_num, GET_CORE_IF(pcd)->frame_num,
56062 + dwc_ep->frm_overrun))
56063 + {
56064 + depctl.d32 =
56065 + DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
56066 + depctl.b.snak = 1;
56067 + depctl.b.epdis = 1;
56068 + DWC_MODIFY_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32, depctl.d32);
56069 + }
56070 + }
56071 + }
56072 +
56073 + /*intr_mask.b.incomplisoin = 1;
56074 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
56075 + intr_mask.d32, 0); */
56076 +#endif //DWC_EN_ISOC
56077 +
56078 + /* Clear interrupt */
56079 + gintsts.d32 = 0;
56080 + gintsts.b.incomplisoin = 1;
56081 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
56082 + gintsts.d32);
56083 +
56084 + return 1;
56085 +}
56086 +
56087 +/**
56088 + * Incomplete ISO OUT Transfer Interrupt.
56089 + *
56090 + * This interrupt indicates that the core has dropped an ISO OUT
56091 + * packet. The following conditions can be the cause:
56092 + * - FIFO Full, the entire packet would not fit in the FIFO.
56093 + * - CRC Error
56094 + * - Corrupted Token
56095 + * The follow actions will be taken:
56096 + * -# Determine the EP
56097 + * -# Set incomplete flag in dwc_ep structure
56098 + * -# Read any data from the FIFO
56099 + * -# Disable EP. When "Endpoint Disabled" interrupt is received
56100 + * re-enable EP.
56101 + */
56102 +int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t * pcd)
56103 +{
56104 +
56105 + gintsts_data_t gintsts;
56106 +
56107 +#ifdef DWC_EN_ISOC
56108 + dwc_otg_dev_if_t *dev_if;
56109 + deptsiz_data_t deptsiz = {.d32 = 0 };
56110 + depctl_data_t depctl = {.d32 = 0 };
56111 + dsts_data_t dsts = {.d32 = 0 };
56112 + dwc_ep_t *dwc_ep;
56113 + int i;
56114 +
56115 + dev_if = GET_CORE_IF(pcd)->dev_if;
56116 +
56117 + for (i = 1; i <= dev_if->num_out_eps; ++i) {
56118 + dwc_ep = &pcd->in_ep[i].dwc_ep;
56119 + if (pcd->out_ep[i].dwc_ep.active &&
56120 + pcd->out_ep[i].dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
56121 + deptsiz.d32 =
56122 + DWC_READ_REG32(&dev_if->out_ep_regs[i]->doeptsiz);
56123 + depctl.d32 =
56124 + DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
56125 +
56126 + if (depctl.b.epdis && deptsiz.d32) {
56127 + set_current_pkt_info(GET_CORE_IF(pcd),
56128 + &pcd->out_ep[i].dwc_ep);
56129 + if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
56130 + dwc_ep->cur_pkt = 0;
56131 + dwc_ep->proc_buf_num =
56132 + (dwc_ep->proc_buf_num ^ 1) & 0x1;
56133 +
56134 + if (dwc_ep->proc_buf_num) {
56135 + dwc_ep->cur_pkt_addr =
56136 + dwc_ep->xfer_buff1;
56137 + dwc_ep->cur_pkt_dma_addr =
56138 + dwc_ep->dma_addr1;
56139 + } else {
56140 + dwc_ep->cur_pkt_addr =
56141 + dwc_ep->xfer_buff0;
56142 + dwc_ep->cur_pkt_dma_addr =
56143 + dwc_ep->dma_addr0;
56144 + }
56145 +
56146 + }
56147 +
56148 + dsts.d32 =
56149 + DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
56150 + dev_global_regs->dsts);
56151 + dwc_ep->next_frame = dsts.b.soffn;
56152 +
56153 + dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
56154 + (pcd),
56155 + dwc_ep);
56156 + }
56157 + }
56158 + }
56159 +#else
56160 + /** @todo implement ISR */
56161 + gintmsk_data_t intr_mask = {.d32 = 0 };
56162 + dwc_otg_core_if_t *core_if;
56163 + deptsiz_data_t deptsiz = {.d32 = 0 };
56164 + depctl_data_t depctl = {.d32 = 0 };
56165 + dctl_data_t dctl = {.d32 = 0 };
56166 + dwc_ep_t *dwc_ep = NULL;
56167 + int i;
56168 + core_if = GET_CORE_IF(pcd);
56169 +
56170 + for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
56171 + dwc_ep = &pcd->out_ep[i].dwc_ep;
56172 + depctl.d32 =
56173 + DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl);
56174 + if (depctl.b.epena && depctl.b.dpid == (core_if->frame_num & 0x1)) {
56175 + core_if->dev_if->isoc_ep = dwc_ep;
56176 + deptsiz.d32 =
56177 + DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz);
56178 + break;
56179 + }
56180 + }
56181 + dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
56182 + gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
56183 + intr_mask.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
56184 +
56185 + if (!intr_mask.b.goutnakeff) {
56186 + /* Unmask it */
56187 + intr_mask.b.goutnakeff = 1;
56188 + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32);
56189 + }
56190 + if (!gintsts.b.goutnakeff) {
56191 + dctl.b.sgoutnak = 1;
56192 + }
56193 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
56194 +
56195 + depctl.d32 = DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl);
56196 + if (depctl.b.epena) {
56197 + depctl.b.epdis = 1;
56198 + depctl.b.snak = 1;
56199 + }
56200 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl, depctl.d32);
56201 +
56202 + intr_mask.d32 = 0;
56203 + intr_mask.b.incomplisoout = 1;
56204 +
56205 +#endif /* DWC_EN_ISOC */
56206 +
56207 + /* Clear interrupt */
56208 + gintsts.d32 = 0;
56209 + gintsts.b.incomplisoout = 1;
56210 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
56211 + gintsts.d32);
56212 +
56213 + return 1;
56214 +}
56215 +
56216 +/**
56217 + * This function handles the Global IN NAK Effective interrupt.
56218 + *
56219 + */
56220 +int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t * pcd)
56221 +{
56222 + dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
56223 + depctl_data_t diepctl = {.d32 = 0 };
56224 + gintmsk_data_t intr_mask = {.d32 = 0 };
56225 + gintsts_data_t gintsts;
56226 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
56227 + int i;
56228 +
56229 + DWC_DEBUGPL(DBG_PCD, "Global IN NAK Effective\n");
56230 +
56231 + /* Disable all active IN EPs */
56232 + for (i = 0; i <= dev_if->num_in_eps; i++) {
56233 + diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
56234 + if (!(diepctl.b.eptype & 1) && diepctl.b.epena) {
56235 + if (core_if->start_predict > 0)
56236 + core_if->start_predict++;
56237 + diepctl.b.epdis = 1;
56238 + diepctl.b.snak = 1;
56239 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, diepctl.d32);
56240 + }
56241 + }
56242 +
56243 +
56244 + /* Disable the Global IN NAK Effective Interrupt */
56245 + intr_mask.b.ginnakeff = 1;
56246 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
56247 + intr_mask.d32, 0);
56248 +
56249 + /* Clear interrupt */
56250 + gintsts.d32 = 0;
56251 + gintsts.b.ginnakeff = 1;
56252 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
56253 + gintsts.d32);
56254 +
56255 + return 1;
56256 +}
56257 +
56258 +/**
56259 + * OUT NAK Effective.
56260 + *
56261 + */
56262 +int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t * pcd)
56263 +{
56264 + dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
56265 + gintmsk_data_t intr_mask = {.d32 = 0 };
56266 + gintsts_data_t gintsts;
56267 + depctl_data_t doepctl;
56268 + int i;
56269 +
56270 + /* Disable the Global OUT NAK Effective Interrupt */
56271 + intr_mask.b.goutnakeff = 1;
56272 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
56273 + intr_mask.d32, 0);
56274 +
56275 + /* If DEV OUT NAK enabled*/
56276 + if (pcd->core_if->core_params->dev_out_nak) {
56277 + /* Run over all out endpoints to determine the ep number on
56278 + * which the timeout has happened
56279 + */
56280 + for (i = 0; i <= dev_if->num_out_eps; i++) {
56281 + if ( pcd->core_if->ep_xfer_info[i].state == 2 )
56282 + break;
56283 + }
56284 + if (i > dev_if->num_out_eps) {
56285 + dctl_data_t dctl;
56286 + dctl.d32 =
56287 + DWC_READ_REG32(&dev_if->dev_global_regs->dctl);
56288 + dctl.b.cgoutnak = 1;
56289 + DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl,
56290 + dctl.d32);
56291 + goto out;
56292 + }
56293 +
56294 + /* Disable the endpoint */
56295 + doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
56296 + if (doepctl.b.epena) {
56297 + doepctl.b.epdis = 1;
56298 + doepctl.b.snak = 1;
56299 + }
56300 + DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
56301 + return 1;
56302 + }
56303 + /* We come here from Incomplete ISO OUT handler */
56304 + if (dev_if->isoc_ep) {
56305 + dwc_ep_t *dwc_ep = (dwc_ep_t *)dev_if->isoc_ep;
56306 + uint32_t epnum = dwc_ep->num;
56307 + doepint_data_t doepint;
56308 + doepint.d32 =
56309 + DWC_READ_REG32(&dev_if->out_ep_regs[dwc_ep->num]->doepint);
56310 + dev_if->isoc_ep = NULL;
56311 + doepctl.d32 =
56312 + DWC_READ_REG32(&dev_if->out_ep_regs[epnum]->doepctl);
56313 + DWC_PRINTF("Before disable DOEPCTL = %08x\n", doepctl.d32);
56314 + if (doepctl.b.epena) {
56315 + doepctl.b.epdis = 1;
56316 + doepctl.b.snak = 1;
56317 + }
56318 + DWC_WRITE_REG32(&dev_if->out_ep_regs[epnum]->doepctl,
56319 + doepctl.d32);
56320 + return 1;
56321 + } else
56322 + DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
56323 + "Global OUT NAK Effective\n");
56324 +
56325 +out:
56326 + /* Clear interrupt */
56327 + gintsts.d32 = 0;
56328 + gintsts.b.goutnakeff = 1;
56329 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
56330 + gintsts.d32);
56331 +
56332 + return 1;
56333 +}
56334 +
56335 +/**
56336 + * PCD interrupt handler.
56337 + *
56338 + * The PCD handles the device interrupts. Many conditions can cause a
56339 + * device interrupt. When an interrupt occurs, the device interrupt
56340 + * service routine determines the cause of the interrupt and
56341 + * dispatches handling to the appropriate function. These interrupt
56342 + * handling functions are described below.
56343 + *
56344 + * All interrupt registers are processed from LSB to MSB.
56345 + *
56346 + */
56347 +int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd)
56348 +{
56349 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
56350 +#ifdef VERBOSE
56351 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
56352 +#endif
56353 + gintsts_data_t gintr_status;
56354 + int32_t retval = 0;
56355 +
56356 + /* Exit from ISR if core is hibernated */
56357 + if (core_if->hibernation_suspend == 1) {
56358 + return retval;
56359 + }
56360 +#ifdef VERBOSE
56361 + DWC_DEBUGPL(DBG_ANY, "%s() gintsts=%08x gintmsk=%08x\n",
56362 + __func__,
56363 + DWC_READ_REG32(&global_regs->gintsts),
56364 + DWC_READ_REG32(&global_regs->gintmsk));
56365 +#endif
56366 +
56367 + if (dwc_otg_is_device_mode(core_if)) {
56368 + DWC_SPINLOCK(pcd->lock);
56369 +#ifdef VERBOSE
56370 + DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%08x gintmsk=%08x\n",
56371 + __func__,
56372 + DWC_READ_REG32(&global_regs->gintsts),
56373 + DWC_READ_REG32(&global_regs->gintmsk));
56374 +#endif
56375 +
56376 + gintr_status.d32 = dwc_otg_read_core_intr(core_if);
56377 +
56378 + DWC_DEBUGPL(DBG_PCDV, "%s: gintsts&gintmsk=%08x\n",
56379 + __func__, gintr_status.d32);
56380 +
56381 + if (gintr_status.b.sofintr) {
56382 + retval |= dwc_otg_pcd_handle_sof_intr(pcd);
56383 + }
56384 + if (gintr_status.b.rxstsqlvl) {
56385 + retval |=
56386 + dwc_otg_pcd_handle_rx_status_q_level_intr(pcd);
56387 + }
56388 + if (gintr_status.b.nptxfempty) {
56389 + retval |= dwc_otg_pcd_handle_np_tx_fifo_empty_intr(pcd);
56390 + }
56391 + if (gintr_status.b.goutnakeff) {
56392 + retval |= dwc_otg_pcd_handle_out_nak_effective(pcd);
56393 + }
56394 + if (gintr_status.b.i2cintr) {
56395 + retval |= dwc_otg_pcd_handle_i2c_intr(pcd);
56396 + }
56397 + if (gintr_status.b.erlysuspend) {
56398 + retval |= dwc_otg_pcd_handle_early_suspend_intr(pcd);
56399 + }
56400 + if (gintr_status.b.usbreset) {
56401 + retval |= dwc_otg_pcd_handle_usb_reset_intr(pcd);
56402 + }
56403 + if (gintr_status.b.enumdone) {
56404 + retval |= dwc_otg_pcd_handle_enum_done_intr(pcd);
56405 + }
56406 + if (gintr_status.b.isooutdrop) {
56407 + retval |=
56408 + dwc_otg_pcd_handle_isoc_out_packet_dropped_intr
56409 + (pcd);
56410 + }
56411 + if (gintr_status.b.eopframe) {
56412 + retval |=
56413 + dwc_otg_pcd_handle_end_periodic_frame_intr(pcd);
56414 + }
56415 + if (gintr_status.b.inepint) {
56416 + if (!core_if->multiproc_int_enable) {
56417 + retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
56418 + }
56419 + }
56420 + if (gintr_status.b.outepintr) {
56421 + if (!core_if->multiproc_int_enable) {
56422 + retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
56423 + }
56424 + }
56425 + if (gintr_status.b.epmismatch) {
56426 + retval |= dwc_otg_pcd_handle_ep_mismatch_intr(pcd);
56427 + }
56428 + if (gintr_status.b.fetsusp) {
56429 + retval |= dwc_otg_pcd_handle_ep_fetsusp_intr(pcd);
56430 + }
56431 + if (gintr_status.b.ginnakeff) {
56432 + retval |= dwc_otg_pcd_handle_in_nak_effective(pcd);
56433 + }
56434 + if (gintr_status.b.incomplisoin) {
56435 + retval |=
56436 + dwc_otg_pcd_handle_incomplete_isoc_in_intr(pcd);
56437 + }
56438 + if (gintr_status.b.incomplisoout) {
56439 + retval |=
56440 + dwc_otg_pcd_handle_incomplete_isoc_out_intr(pcd);
56441 + }
56442 +
56443 + /* In MPI mode Device Endpoints interrupts are asserted
56444 + * without setting outepintr and inepint bits set, so these
56445 + * Interrupt handlers are called without checking these bit-fields
56446 + */
56447 + if (core_if->multiproc_int_enable) {
56448 + retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
56449 + retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
56450 + }
56451 +#ifdef VERBOSE
56452 + DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%0x\n", __func__,
56453 + DWC_READ_REG32(&global_regs->gintsts));
56454 +#endif
56455 + DWC_SPINUNLOCK(pcd->lock);
56456 + }
56457 + return retval;
56458 +}
56459 +
56460 +#endif /* DWC_HOST_ONLY */
56461 --- /dev/null
56462 +++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c
56463 @@ -0,0 +1,1360 @@
56464 + /* ==========================================================================
56465 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_linux.c $
56466 + * $Revision: #21 $
56467 + * $Date: 2012/08/10 $
56468 + * $Change: 2047372 $
56469 + *
56470 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
56471 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
56472 + * otherwise expressly agreed to in writing between Synopsys and you.
56473 + *
56474 + * The Software IS NOT an item of Licensed Software or Licensed Product under
56475 + * any End User Software License Agreement or Agreement for Licensed Product
56476 + * with Synopsys or any supplement thereto. You are permitted to use and
56477 + * redistribute this Software in source and binary forms, with or without
56478 + * modification, provided that redistributions of source code must retain this
56479 + * notice. You may not view, use, disclose, copy or distribute this file or
56480 + * any information contained herein except pursuant to this license grant from
56481 + * Synopsys. If you do not agree with this notice, including the disclaimer
56482 + * below, then you are not authorized to use the Software.
56483 + *
56484 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
56485 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
56486 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
56487 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
56488 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
56489 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
56490 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
56491 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
56492 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
56493 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
56494 + * DAMAGE.
56495 + * ========================================================================== */
56496 +#ifndef DWC_HOST_ONLY
56497 +
56498 +/** @file
56499 + * This file implements the Peripheral Controller Driver.
56500 + *
56501 + * The Peripheral Controller Driver (PCD) is responsible for
56502 + * translating requests from the Function Driver into the appropriate
56503 + * actions on the DWC_otg controller. It isolates the Function Driver
56504 + * from the specifics of the controller by providing an API to the
56505 + * Function Driver.
56506 + *
56507 + * The Peripheral Controller Driver for Linux will implement the
56508 + * Gadget API, so that the existing Gadget drivers can be used.
56509 + * (Gadget Driver is the Linux terminology for a Function Driver.)
56510 + *
56511 + * The Linux Gadget API is defined in the header file
56512 + * <code><linux/usb_gadget.h></code>. The USB EP operations API is
56513 + * defined in the structure <code>usb_ep_ops</code> and the USB
56514 + * Controller API is defined in the structure
56515 + * <code>usb_gadget_ops</code>.
56516 + *
56517 + */
56518 +
56519 +#include "dwc_otg_os_dep.h"
56520 +#include "dwc_otg_pcd_if.h"
56521 +#include "dwc_otg_pcd.h"
56522 +#include "dwc_otg_driver.h"
56523 +#include "dwc_otg_dbg.h"
56524 +
56525 +extern bool fiq_enable;
56526 +
56527 +static struct gadget_wrapper {
56528 + dwc_otg_pcd_t *pcd;
56529 +
56530 + struct usb_gadget gadget;
56531 + struct usb_gadget_driver *driver;
56532 +
56533 + struct usb_ep ep0;
56534 + struct usb_ep in_ep[16];
56535 + struct usb_ep out_ep[16];
56536 +
56537 +} *gadget_wrapper;
56538 +
56539 +/* Display the contents of the buffer */
56540 +extern void dump_msg(const u8 * buf, unsigned int length);
56541 +/**
56542 + * Get the dwc_otg_pcd_ep_t* from usb_ep* pointer - NULL in case
56543 + * if the endpoint is not found
56544 + */
56545 +static struct dwc_otg_pcd_ep *ep_from_handle(dwc_otg_pcd_t * pcd, void *handle)
56546 +{
56547 + int i;
56548 + if (pcd->ep0.priv == handle) {
56549 + return &pcd->ep0;
56550 + }
56551 +
56552 + for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) {
56553 + if (pcd->in_ep[i].priv == handle)
56554 + return &pcd->in_ep[i];
56555 + if (pcd->out_ep[i].priv == handle)
56556 + return &pcd->out_ep[i];
56557 + }
56558 +
56559 + return NULL;
56560 +}
56561 +
56562 +/* USB Endpoint Operations */
56563 +/*
56564 + * The following sections briefly describe the behavior of the Gadget
56565 + * API endpoint operations implemented in the DWC_otg driver
56566 + * software. Detailed descriptions of the generic behavior of each of
56567 + * these functions can be found in the Linux header file
56568 + * include/linux/usb_gadget.h.
56569 + *
56570 + * The Gadget API provides wrapper functions for each of the function
56571 + * pointers defined in usb_ep_ops. The Gadget Driver calls the wrapper
56572 + * function, which then calls the underlying PCD function. The
56573 + * following sections are named according to the wrapper
56574 + * functions. Within each section, the corresponding DWC_otg PCD
56575 + * function name is specified.
56576 + *
56577 + */
56578 +
56579 +/**
56580 + * This function is called by the Gadget Driver for each EP to be
56581 + * configured for the current configuration (SET_CONFIGURATION).
56582 + *
56583 + * This function initializes the dwc_otg_ep_t data structure, and then
56584 + * calls dwc_otg_ep_activate.
56585 + */
56586 +static int ep_enable(struct usb_ep *usb_ep,
56587 + const struct usb_endpoint_descriptor *ep_desc)
56588 +{
56589 + int retval;
56590 +
56591 + DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, ep_desc);
56592 +
56593 + if (!usb_ep || !ep_desc || ep_desc->bDescriptorType != USB_DT_ENDPOINT) {
56594 + DWC_WARN("%s, bad ep or descriptor\n", __func__);
56595 + return -EINVAL;
56596 + }
56597 + if (usb_ep == &gadget_wrapper->ep0) {
56598 + DWC_WARN("%s, bad ep(0)\n", __func__);
56599 + return -EINVAL;
56600 + }
56601 +
56602 + /* Check FIFO size? */
56603 + if (!ep_desc->wMaxPacketSize) {
56604 + DWC_WARN("%s, bad %s maxpacket\n", __func__, usb_ep->name);
56605 + return -ERANGE;
56606 + }
56607 +
56608 + if (!gadget_wrapper->driver ||
56609 + gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
56610 + DWC_WARN("%s, bogus device state\n", __func__);
56611 + return -ESHUTDOWN;
56612 + }
56613 +
56614 + /* Delete after check - MAS */
56615 +#if 0
56616 + nat = (uint32_t) ep_desc->wMaxPacketSize;
56617 + printk(KERN_ALERT "%s: nat (before) =%d\n", __func__, nat);
56618 + nat = (nat >> 11) & 0x03;
56619 + printk(KERN_ALERT "%s: nat (after) =%d\n", __func__, nat);
56620 +#endif
56621 + retval = dwc_otg_pcd_ep_enable(gadget_wrapper->pcd,
56622 + (const uint8_t *)ep_desc,
56623 + (void *)usb_ep);
56624 + if (retval) {
56625 + DWC_WARN("dwc_otg_pcd_ep_enable failed\n");
56626 + return -EINVAL;
56627 + }
56628 +
56629 + usb_ep->maxpacket = le16_to_cpu(ep_desc->wMaxPacketSize);
56630 +
56631 + return 0;
56632 +}
56633 +
56634 +/**
56635 + * This function is called when an EP is disabled due to disconnect or
56636 + * change in configuration. Any pending requests will terminate with a
56637 + * status of -ESHUTDOWN.
56638 + *
56639 + * This function modifies the dwc_otg_ep_t data structure for this EP,
56640 + * and then calls dwc_otg_ep_deactivate.
56641 + */
56642 +static int ep_disable(struct usb_ep *usb_ep)
56643 +{
56644 + int retval;
56645 +
56646 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, usb_ep);
56647 + if (!usb_ep) {
56648 + DWC_DEBUGPL(DBG_PCD, "%s, %s not enabled\n", __func__,
56649 + usb_ep ? usb_ep->name : NULL);
56650 + return -EINVAL;
56651 + }
56652 +
56653 + retval = dwc_otg_pcd_ep_disable(gadget_wrapper->pcd, usb_ep);
56654 + if (retval) {
56655 + retval = -EINVAL;
56656 + }
56657 +
56658 + return retval;
56659 +}
56660 +
56661 +/**
56662 + * This function allocates a request object to use with the specified
56663 + * endpoint.
56664 + *
56665 + * @param ep The endpoint to be used with with the request
56666 + * @param gfp_flags the GFP_* flags to use.
56667 + */
56668 +static struct usb_request *dwc_otg_pcd_alloc_request(struct usb_ep *ep,
56669 + gfp_t gfp_flags)
56670 +{
56671 + struct usb_request *usb_req;
56672 +
56673 + DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d)\n", __func__, ep, gfp_flags);
56674 + if (0 == ep) {
56675 + DWC_WARN("%s() %s\n", __func__, "Invalid EP!\n");
56676 + return 0;
56677 + }
56678 + usb_req = kmalloc(sizeof(*usb_req), gfp_flags);
56679 + if (0 == usb_req) {
56680 + DWC_WARN("%s() %s\n", __func__, "request allocation failed!\n");
56681 + return 0;
56682 + }
56683 + memset(usb_req, 0, sizeof(*usb_req));
56684 + usb_req->dma = DWC_DMA_ADDR_INVALID;
56685 +
56686 + return usb_req;
56687 +}
56688 +
56689 +/**
56690 + * This function frees a request object.
56691 + *
56692 + * @param ep The endpoint associated with the request
56693 + * @param req The request being freed
56694 + */
56695 +static void dwc_otg_pcd_free_request(struct usb_ep *ep, struct usb_request *req)
56696 +{
56697 + DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, ep, req);
56698 +
56699 + if (0 == ep || 0 == req) {
56700 + DWC_WARN("%s() %s\n", __func__,
56701 + "Invalid ep or req argument!\n");
56702 + return;
56703 + }
56704 +
56705 + kfree(req);
56706 +}
56707 +
56708 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
56709 +/**
56710 + * This function allocates an I/O buffer to be used for a transfer
56711 + * to/from the specified endpoint.
56712 + *
56713 + * @param usb_ep The endpoint to be used with with the request
56714 + * @param bytes The desired number of bytes for the buffer
56715 + * @param dma Pointer to the buffer's DMA address; must be valid
56716 + * @param gfp_flags the GFP_* flags to use.
56717 + * @return address of a new buffer or null is buffer could not be allocated.
56718 + */
56719 +static void *dwc_otg_pcd_alloc_buffer(struct usb_ep *usb_ep, unsigned bytes,
56720 + dma_addr_t * dma, gfp_t gfp_flags)
56721 +{
56722 + void *buf;
56723 + dwc_otg_pcd_t *pcd = 0;
56724 +
56725 + pcd = gadget_wrapper->pcd;
56726 +
56727 + DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d,%p,%0x)\n", __func__, usb_ep, bytes,
56728 + dma, gfp_flags);
56729 +
56730 + /* Check dword alignment */
56731 + if ((bytes & 0x3UL) != 0) {
56732 + DWC_WARN("%s() Buffer size is not a multiple of"
56733 + "DWORD size (%d)", __func__, bytes);
56734 + }
56735 +
56736 + buf = dma_alloc_coherent(NULL, bytes, dma, gfp_flags);
56737 +
56738 + /* Check dword alignment */
56739 + if (((int)buf & 0x3UL) != 0) {
56740 + DWC_WARN("%s() Buffer is not DWORD aligned (%p)",
56741 + __func__, buf);
56742 + }
56743 +
56744 + return buf;
56745 +}
56746 +
56747 +/**
56748 + * This function frees an I/O buffer that was allocated by alloc_buffer.
56749 + *
56750 + * @param usb_ep the endpoint associated with the buffer
56751 + * @param buf address of the buffer
56752 + * @param dma The buffer's DMA address
56753 + * @param bytes The number of bytes of the buffer
56754 + */
56755 +static void dwc_otg_pcd_free_buffer(struct usb_ep *usb_ep, void *buf,
56756 + dma_addr_t dma, unsigned bytes)
56757 +{
56758 + dwc_otg_pcd_t *pcd = 0;
56759 +
56760 + pcd = gadget_wrapper->pcd;
56761 +
56762 + DWC_DEBUGPL(DBG_PCDV, "%s(%p,%0x,%d)\n", __func__, buf, dma, bytes);
56763 +
56764 + dma_free_coherent(NULL, bytes, buf, dma);
56765 +}
56766 +#endif
56767 +
56768 +/**
56769 + * This function is used to submit an I/O Request to an EP.
56770 + *
56771 + * - When the request completes the request's completion callback
56772 + * is called to return the request to the driver.
56773 + * - An EP, except control EPs, may have multiple requests
56774 + * pending.
56775 + * - Once submitted the request cannot be examined or modified.
56776 + * - Each request is turned into one or more packets.
56777 + * - A BULK EP can queue any amount of data; the transfer is
56778 + * packetized.
56779 + * - Zero length Packets are specified with the request 'zero'
56780 + * flag.
56781 + */
56782 +static int ep_queue(struct usb_ep *usb_ep, struct usb_request *usb_req,
56783 + gfp_t gfp_flags)
56784 +{
56785 + dwc_otg_pcd_t *pcd;
56786 + struct dwc_otg_pcd_ep *ep = NULL;
56787 + int retval = 0, is_isoc_ep = 0;
56788 + dma_addr_t dma_addr = DWC_DMA_ADDR_INVALID;
56789 +
56790 + DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p,%d)\n",
56791 + __func__, usb_ep, usb_req, gfp_flags);
56792 +
56793 + if (!usb_req || !usb_req->complete || !usb_req->buf) {
56794 + DWC_WARN("bad params\n");
56795 + return -EINVAL;
56796 + }
56797 +
56798 + if (!usb_ep) {
56799 + DWC_WARN("bad ep\n");
56800 + return -EINVAL;
56801 + }
56802 +
56803 + pcd = gadget_wrapper->pcd;
56804 + if (!gadget_wrapper->driver ||
56805 + gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
56806 + DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n",
56807 + gadget_wrapper->gadget.speed);
56808 + DWC_WARN("bogus device state\n");
56809 + return -ESHUTDOWN;
56810 + }
56811 +
56812 + DWC_DEBUGPL(DBG_PCD, "%s queue req %p, len %d buf %p\n",
56813 + usb_ep->name, usb_req, usb_req->length, usb_req->buf);
56814 +
56815 + usb_req->status = -EINPROGRESS;
56816 + usb_req->actual = 0;
56817 +
56818 + ep = ep_from_handle(pcd, usb_ep);
56819 + if (ep == NULL)
56820 + is_isoc_ep = 0;
56821 + else
56822 + is_isoc_ep = (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ? 1 : 0;
56823 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
56824 + dma_addr = usb_req->dma;
56825 +#else
56826 + if (GET_CORE_IF(pcd)->dma_enable) {
56827 + dwc_otg_device_t *otg_dev = gadget_wrapper->pcd->otg_dev;
56828 + struct device *dev = NULL;
56829 +
56830 + if (otg_dev != NULL)
56831 + dev = DWC_OTG_OS_GETDEV(otg_dev->os_dep);
56832 +
56833 + if (usb_req->length != 0 &&
56834 + usb_req->dma == DWC_DMA_ADDR_INVALID) {
56835 + dma_addr = dma_map_single(dev, usb_req->buf,
56836 + usb_req->length,
56837 + ep->dwc_ep.is_in ?
56838 + DMA_TO_DEVICE:
56839 + DMA_FROM_DEVICE);
56840 + }
56841 + }
56842 +#endif
56843 +
56844 +#ifdef DWC_UTE_PER_IO
56845 + if (is_isoc_ep == 1) {
56846 + retval = dwc_otg_pcd_xiso_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr,
56847 + usb_req->length, usb_req->zero, usb_req,
56848 + gfp_flags == GFP_ATOMIC ? 1 : 0, &usb_req->ext_req);
56849 + if (retval)
56850 + return -EINVAL;
56851 +
56852 + return 0;
56853 + }
56854 +#endif
56855 + retval = dwc_otg_pcd_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr,
56856 + usb_req->length, usb_req->zero, usb_req,
56857 + gfp_flags == GFP_ATOMIC ? 1 : 0);
56858 + if (retval) {
56859 + return -EINVAL;
56860 + }
56861 +
56862 + return 0;
56863 +}
56864 +
56865 +/**
56866 + * This function cancels an I/O request from an EP.
56867 + */
56868 +static int ep_dequeue(struct usb_ep *usb_ep, struct usb_request *usb_req)
56869 +{
56870 + DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, usb_req);
56871 +
56872 + if (!usb_ep || !usb_req) {
56873 + DWC_WARN("bad argument\n");
56874 + return -EINVAL;
56875 + }
56876 + if (!gadget_wrapper->driver ||
56877 + gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
56878 + DWC_WARN("bogus device state\n");
56879 + return -ESHUTDOWN;
56880 + }
56881 + if (dwc_otg_pcd_ep_dequeue(gadget_wrapper->pcd, usb_ep, usb_req)) {
56882 + return -EINVAL;
56883 + }
56884 +
56885 + return 0;
56886 +}
56887 +
56888 +/**
56889 + * usb_ep_set_halt stalls an endpoint.
56890 + *
56891 + * usb_ep_clear_halt clears an endpoint halt and resets its data
56892 + * toggle.
56893 + *
56894 + * Both of these functions are implemented with the same underlying
56895 + * function. The behavior depends on the value argument.
56896 + *
56897 + * @param[in] usb_ep the Endpoint to halt or clear halt.
56898 + * @param[in] value
56899 + * - 0 means clear_halt.
56900 + * - 1 means set_halt,
56901 + * - 2 means clear stall lock flag.
56902 + * - 3 means set stall lock flag.
56903 + */
56904 +static int ep_halt(struct usb_ep *usb_ep, int value)
56905 +{
56906 + int retval = 0;
56907 +
56908 + DWC_DEBUGPL(DBG_PCD, "HALT %s %d\n", usb_ep->name, value);
56909 +
56910 + if (!usb_ep) {
56911 + DWC_WARN("bad ep\n");
56912 + return -EINVAL;
56913 + }
56914 +
56915 + retval = dwc_otg_pcd_ep_halt(gadget_wrapper->pcd, usb_ep, value);
56916 + if (retval == -DWC_E_AGAIN) {
56917 + return -EAGAIN;
56918 + } else if (retval) {
56919 + retval = -EINVAL;
56920 + }
56921 +
56922 + return retval;
56923 +}
56924 +
56925 +//#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))
56926 +#if 0
56927 +/**
56928 + * ep_wedge: sets the halt feature and ignores clear requests
56929 + *
56930 + * @usb_ep: the endpoint being wedged
56931 + *
56932 + * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT)
56933 + * requests. If the gadget driver clears the halt status, it will
56934 + * automatically unwedge the endpoint.
56935 + *
56936 + * Returns zero on success, else negative errno. *
56937 + * Check usb_ep_set_wedge() at "usb_gadget.h" for details
56938 + */
56939 +static int ep_wedge(struct usb_ep *usb_ep)
56940 +{
56941 + int retval = 0;
56942 +
56943 + DWC_DEBUGPL(DBG_PCD, "WEDGE %s\n", usb_ep->name);
56944 +
56945 + if (!usb_ep) {
56946 + DWC_WARN("bad ep\n");
56947 + return -EINVAL;
56948 + }
56949 +
56950 + retval = dwc_otg_pcd_ep_wedge(gadget_wrapper->pcd, usb_ep);
56951 + if (retval == -DWC_E_AGAIN) {
56952 + retval = -EAGAIN;
56953 + } else if (retval) {
56954 + retval = -EINVAL;
56955 + }
56956 +
56957 + return retval;
56958 +}
56959 +#endif
56960 +
56961 +#ifdef DWC_EN_ISOC
56962 +/**
56963 + * This function is used to submit an ISOC Transfer Request to an EP.
56964 + *
56965 + * - Every time a sync period completes the request's completion callback
56966 + * is called to provide data to the gadget driver.
56967 + * - Once submitted the request cannot be modified.
56968 + * - Each request is turned into periodic data packets untill ISO
56969 + * Transfer is stopped..
56970 + */
56971 +static int iso_ep_start(struct usb_ep *usb_ep, struct usb_iso_request *req,
56972 + gfp_t gfp_flags)
56973 +{
56974 + int retval = 0;
56975 +
56976 + if (!req || !req->process_buffer || !req->buf0 || !req->buf1) {
56977 + DWC_WARN("bad params\n");
56978 + return -EINVAL;
56979 + }
56980 +
56981 + if (!usb_ep) {
56982 + DWC_PRINTF("bad params\n");
56983 + return -EINVAL;
56984 + }
56985 +
56986 + req->status = -EINPROGRESS;
56987 +
56988 + retval =
56989 + dwc_otg_pcd_iso_ep_start(gadget_wrapper->pcd, usb_ep, req->buf0,
56990 + req->buf1, req->dma0, req->dma1,
56991 + req->sync_frame, req->data_pattern_frame,
56992 + req->data_per_frame,
56993 + req->
56994 + flags & USB_REQ_ISO_ASAP ? -1 :
56995 + req->start_frame, req->buf_proc_intrvl,
56996 + req, gfp_flags == GFP_ATOMIC ? 1 : 0);
56997 +
56998 + if (retval) {
56999 + return -EINVAL;
57000 + }
57001 +
57002 + return retval;
57003 +}
57004 +
57005 +/**
57006 + * This function stops ISO EP Periodic Data Transfer.
57007 + */
57008 +static int iso_ep_stop(struct usb_ep *usb_ep, struct usb_iso_request *req)
57009 +{
57010 + int retval = 0;
57011 + if (!usb_ep) {
57012 + DWC_WARN("bad ep\n");
57013 + }
57014 +
57015 + if (!gadget_wrapper->driver ||
57016 + gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
57017 + DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n",
57018 + gadget_wrapper->gadget.speed);
57019 + DWC_WARN("bogus device state\n");
57020 + }
57021 +
57022 + dwc_otg_pcd_iso_ep_stop(gadget_wrapper->pcd, usb_ep, req);
57023 + if (retval) {
57024 + retval = -EINVAL;
57025 + }
57026 +
57027 + return retval;
57028 +}
57029 +
57030 +static struct usb_iso_request *alloc_iso_request(struct usb_ep *ep,
57031 + int packets, gfp_t gfp_flags)
57032 +{
57033 + struct usb_iso_request *pReq = NULL;
57034 + uint32_t req_size;
57035 +
57036 + req_size = sizeof(struct usb_iso_request);
57037 + req_size +=
57038 + (2 * packets * (sizeof(struct usb_gadget_iso_packet_descriptor)));
57039 +
57040 + pReq = kmalloc(req_size, gfp_flags);
57041 + if (!pReq) {
57042 + DWC_WARN("Can't allocate Iso Request\n");
57043 + return 0;
57044 + }
57045 + pReq->iso_packet_desc0 = (void *)(pReq + 1);
57046 +
57047 + pReq->iso_packet_desc1 = pReq->iso_packet_desc0 + packets;
57048 +
57049 + return pReq;
57050 +}
57051 +
57052 +static void free_iso_request(struct usb_ep *ep, struct usb_iso_request *req)
57053 +{
57054 + kfree(req);
57055 +}
57056 +
57057 +static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops = {
57058 + .ep_ops = {
57059 + .enable = ep_enable,
57060 + .disable = ep_disable,
57061 +
57062 + .alloc_request = dwc_otg_pcd_alloc_request,
57063 + .free_request = dwc_otg_pcd_free_request,
57064 +
57065 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
57066 + .alloc_buffer = dwc_otg_pcd_alloc_buffer,
57067 + .free_buffer = dwc_otg_pcd_free_buffer,
57068 +#endif
57069 +
57070 + .queue = ep_queue,
57071 + .dequeue = ep_dequeue,
57072 +
57073 + .set_halt = ep_halt,
57074 + .fifo_status = 0,
57075 + .fifo_flush = 0,
57076 + },
57077 + .iso_ep_start = iso_ep_start,
57078 + .iso_ep_stop = iso_ep_stop,
57079 + .alloc_iso_request = alloc_iso_request,
57080 + .free_iso_request = free_iso_request,
57081 +};
57082 +
57083 +#else
57084 +
57085 + int (*enable) (struct usb_ep *ep,
57086 + const struct usb_endpoint_descriptor *desc);
57087 + int (*disable) (struct usb_ep *ep);
57088 +
57089 + struct usb_request *(*alloc_request) (struct usb_ep *ep,
57090 + gfp_t gfp_flags);
57091 + void (*free_request) (struct usb_ep *ep, struct usb_request *req);
57092 +
57093 + int (*queue) (struct usb_ep *ep, struct usb_request *req,
57094 + gfp_t gfp_flags);
57095 + int (*dequeue) (struct usb_ep *ep, struct usb_request *req);
57096 +
57097 + int (*set_halt) (struct usb_ep *ep, int value);
57098 + int (*set_wedge) (struct usb_ep *ep);
57099 +
57100 + int (*fifo_status) (struct usb_ep *ep);
57101 + void (*fifo_flush) (struct usb_ep *ep);
57102 +static struct usb_ep_ops dwc_otg_pcd_ep_ops = {
57103 + .enable = ep_enable,
57104 + .disable = ep_disable,
57105 +
57106 + .alloc_request = dwc_otg_pcd_alloc_request,
57107 + .free_request = dwc_otg_pcd_free_request,
57108 +
57109 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
57110 + .alloc_buffer = dwc_otg_pcd_alloc_buffer,
57111 + .free_buffer = dwc_otg_pcd_free_buffer,
57112 +#else
57113 + /* .set_wedge = ep_wedge, */
57114 + .set_wedge = NULL, /* uses set_halt instead */
57115 +#endif
57116 +
57117 + .queue = ep_queue,
57118 + .dequeue = ep_dequeue,
57119 +
57120 + .set_halt = ep_halt,
57121 + .fifo_status = 0,
57122 + .fifo_flush = 0,
57123 +
57124 +};
57125 +
57126 +#endif /* _EN_ISOC_ */
57127 +/* Gadget Operations */
57128 +/**
57129 + * The following gadget operations will be implemented in the DWC_otg
57130 + * PCD. Functions in the API that are not described below are not
57131 + * implemented.
57132 + *
57133 + * The Gadget API provides wrapper functions for each of the function
57134 + * pointers defined in usb_gadget_ops. The Gadget Driver calls the
57135 + * wrapper function, which then calls the underlying PCD function. The
57136 + * following sections are named according to the wrapper functions
57137 + * (except for ioctl, which doesn't have a wrapper function). Within
57138 + * each section, the corresponding DWC_otg PCD function name is
57139 + * specified.
57140 + *
57141 + */
57142 +
57143 +/**
57144 + *Gets the USB Frame number of the last SOF.
57145 + */
57146 +static int get_frame_number(struct usb_gadget *gadget)
57147 +{
57148 + struct gadget_wrapper *d;
57149 +
57150 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget);
57151 +
57152 + if (gadget == 0) {
57153 + return -ENODEV;
57154 + }
57155 +
57156 + d = container_of(gadget, struct gadget_wrapper, gadget);
57157 + return dwc_otg_pcd_get_frame_number(d->pcd);
57158 +}
57159 +
57160 +#ifdef CONFIG_USB_DWC_OTG_LPM
57161 +static int test_lpm_enabled(struct usb_gadget *gadget)
57162 +{
57163 + struct gadget_wrapper *d;
57164 +
57165 + d = container_of(gadget, struct gadget_wrapper, gadget);
57166 +
57167 + return dwc_otg_pcd_is_lpm_enabled(d->pcd);
57168 +}
57169 +#endif
57170 +
57171 +/**
57172 + * Initiates Session Request Protocol (SRP) to wakeup the host if no
57173 + * session is in progress. If a session is already in progress, but
57174 + * the device is suspended, remote wakeup signaling is started.
57175 + *
57176 + */
57177 +static int wakeup(struct usb_gadget *gadget)
57178 +{
57179 + struct gadget_wrapper *d;
57180 +
57181 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget);
57182 +
57183 + if (gadget == 0) {
57184 + return -ENODEV;
57185 + } else {
57186 + d = container_of(gadget, struct gadget_wrapper, gadget);
57187 + }
57188 + dwc_otg_pcd_wakeup(d->pcd);
57189 + return 0;
57190 +}
57191 +
57192 +static const struct usb_gadget_ops dwc_otg_pcd_ops = {
57193 + .get_frame = get_frame_number,
57194 + .wakeup = wakeup,
57195 +#ifdef CONFIG_USB_DWC_OTG_LPM
57196 + .lpm_support = test_lpm_enabled,
57197 +#endif
57198 + // current versions must always be self-powered
57199 +};
57200 +
57201 +static int _setup(dwc_otg_pcd_t * pcd, uint8_t * bytes)
57202 +{
57203 + int retval = -DWC_E_NOT_SUPPORTED;
57204 + if (gadget_wrapper->driver && gadget_wrapper->driver->setup) {
57205 + retval = gadget_wrapper->driver->setup(&gadget_wrapper->gadget,
57206 + (struct usb_ctrlrequest
57207 + *)bytes);
57208 + }
57209 +
57210 + if (retval == -ENOTSUPP) {
57211 + retval = -DWC_E_NOT_SUPPORTED;
57212 + } else if (retval < 0) {
57213 + retval = -DWC_E_INVALID;
57214 + }
57215 +
57216 + return retval;
57217 +}
57218 +
57219 +#ifdef DWC_EN_ISOC
57220 +static int _isoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle,
57221 + void *req_handle, int proc_buf_num)
57222 +{
57223 + int i, packet_count;
57224 + struct usb_gadget_iso_packet_descriptor *iso_packet = 0;
57225 + struct usb_iso_request *iso_req = req_handle;
57226 +
57227 + if (proc_buf_num) {
57228 + iso_packet = iso_req->iso_packet_desc1;
57229 + } else {
57230 + iso_packet = iso_req->iso_packet_desc0;
57231 + }
57232 + packet_count =
57233 + dwc_otg_pcd_get_iso_packet_count(pcd, ep_handle, req_handle);
57234 + for (i = 0; i < packet_count; ++i) {
57235 + int status;
57236 + int actual;
57237 + int offset;
57238 + dwc_otg_pcd_get_iso_packet_params(pcd, ep_handle, req_handle,
57239 + i, &status, &actual, &offset);
57240 + switch (status) {
57241 + case -DWC_E_NO_DATA:
57242 + status = -ENODATA;
57243 + break;
57244 + default:
57245 + if (status) {
57246 + DWC_PRINTF("unknown status in isoc packet\n");
57247 + }
57248 +
57249 + }
57250 + iso_packet[i].status = status;
57251 + iso_packet[i].offset = offset;
57252 + iso_packet[i].actual_length = actual;
57253 + }
57254 +
57255 + iso_req->status = 0;
57256 + iso_req->process_buffer(ep_handle, iso_req);
57257 +
57258 + return 0;
57259 +}
57260 +#endif /* DWC_EN_ISOC */
57261 +
57262 +#ifdef DWC_UTE_PER_IO
57263 +/**
57264 + * Copy the contents of the extended request to the Linux usb_request's
57265 + * extended part and call the gadget's completion.
57266 + *
57267 + * @param pcd Pointer to the pcd structure
57268 + * @param ep_handle Void pointer to the usb_ep structure
57269 + * @param req_handle Void pointer to the usb_request structure
57270 + * @param status Request status returned from the portable logic
57271 + * @param ereq_port Void pointer to the extended request structure
57272 + * created in the the portable part that contains the
57273 + * results of the processed iso packets.
57274 + */
57275 +static int _xisoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle,
57276 + void *req_handle, int32_t status, void *ereq_port)
57277 +{
57278 + struct dwc_ute_iso_req_ext *ereqorg = NULL;
57279 + struct dwc_iso_xreq_port *ereqport = NULL;
57280 + struct dwc_ute_iso_packet_descriptor *desc_org = NULL;
57281 + int i;
57282 + struct usb_request *req;
57283 + //struct dwc_ute_iso_packet_descriptor *
57284 + //int status = 0;
57285 +
57286 + req = (struct usb_request *)req_handle;
57287 + ereqorg = &req->ext_req;
57288 + ereqport = (struct dwc_iso_xreq_port *)ereq_port;
57289 + desc_org = ereqorg->per_io_frame_descs;
57290 +
57291 + if (req && req->complete) {
57292 + /* Copy the request data from the portable logic to our request */
57293 + for (i = 0; i < ereqport->pio_pkt_count; i++) {
57294 + desc_org[i].actual_length =
57295 + ereqport->per_io_frame_descs[i].actual_length;
57296 + desc_org[i].status =
57297 + ereqport->per_io_frame_descs[i].status;
57298 + }
57299 +
57300 + switch (status) {
57301 + case -DWC_E_SHUTDOWN:
57302 + req->status = -ESHUTDOWN;
57303 + break;
57304 + case -DWC_E_RESTART:
57305 + req->status = -ECONNRESET;
57306 + break;
57307 + case -DWC_E_INVALID:
57308 + req->status = -EINVAL;
57309 + break;
57310 + case -DWC_E_TIMEOUT:
57311 + req->status = -ETIMEDOUT;
57312 + break;
57313 + default:
57314 + req->status = status;
57315 + }
57316 +
57317 + /* And call the gadget's completion */
57318 + req->complete(ep_handle, req);
57319 + }
57320 +
57321 + return 0;
57322 +}
57323 +#endif /* DWC_UTE_PER_IO */
57324 +
57325 +static int _complete(dwc_otg_pcd_t * pcd, void *ep_handle,
57326 + void *req_handle, int32_t status, uint32_t actual)
57327 +{
57328 + struct usb_request *req = (struct usb_request *)req_handle;
57329 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)
57330 + struct dwc_otg_pcd_ep *ep = NULL;
57331 +#endif
57332 +
57333 + if (req && req->complete) {
57334 + switch (status) {
57335 + case -DWC_E_SHUTDOWN:
57336 + req->status = -ESHUTDOWN;
57337 + break;
57338 + case -DWC_E_RESTART:
57339 + req->status = -ECONNRESET;
57340 + break;
57341 + case -DWC_E_INVALID:
57342 + req->status = -EINVAL;
57343 + break;
57344 + case -DWC_E_TIMEOUT:
57345 + req->status = -ETIMEDOUT;
57346 + break;
57347 + default:
57348 + req->status = status;
57349 +
57350 + }
57351 +
57352 + req->actual = actual;
57353 + DWC_SPINUNLOCK(pcd->lock);
57354 + req->complete(ep_handle, req);
57355 + DWC_SPINLOCK(pcd->lock);
57356 + }
57357 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)
57358 + ep = ep_from_handle(pcd, ep_handle);
57359 + if (GET_CORE_IF(pcd)->dma_enable) {
57360 + if (req->length != 0) {
57361 + dwc_otg_device_t *otg_dev = gadget_wrapper->pcd->otg_dev;
57362 + struct device *dev = NULL;
57363 +
57364 + if (otg_dev != NULL)
57365 + dev = DWC_OTG_OS_GETDEV(otg_dev->os_dep);
57366 +
57367 + dma_unmap_single(dev, req->dma, req->length,
57368 + ep->dwc_ep.is_in ?
57369 + DMA_TO_DEVICE: DMA_FROM_DEVICE);
57370 + }
57371 + }
57372 +#endif
57373 +
57374 + return 0;
57375 +}
57376 +
57377 +static int _connect(dwc_otg_pcd_t * pcd, int speed)
57378 +{
57379 + gadget_wrapper->gadget.speed = speed;
57380 + return 0;
57381 +}
57382 +
57383 +static int _disconnect(dwc_otg_pcd_t * pcd)
57384 +{
57385 + if (gadget_wrapper->driver && gadget_wrapper->driver->disconnect) {
57386 + gadget_wrapper->driver->disconnect(&gadget_wrapper->gadget);
57387 + }
57388 + return 0;
57389 +}
57390 +
57391 +static int _resume(dwc_otg_pcd_t * pcd)
57392 +{
57393 + if (gadget_wrapper->driver && gadget_wrapper->driver->resume) {
57394 + gadget_wrapper->driver->resume(&gadget_wrapper->gadget);
57395 + }
57396 +
57397 + return 0;
57398 +}
57399 +
57400 +static int _suspend(dwc_otg_pcd_t * pcd)
57401 +{
57402 + if (gadget_wrapper->driver && gadget_wrapper->driver->suspend) {
57403 + gadget_wrapper->driver->suspend(&gadget_wrapper->gadget);
57404 + }
57405 + return 0;
57406 +}
57407 +
57408 +/**
57409 + * This function updates the otg values in the gadget structure.
57410 + */
57411 +static int _hnp_changed(dwc_otg_pcd_t * pcd)
57412 +{
57413 +
57414 + if (!gadget_wrapper->gadget.is_otg)
57415 + return 0;
57416 +
57417 + gadget_wrapper->gadget.b_hnp_enable = get_b_hnp_enable(pcd);
57418 + gadget_wrapper->gadget.a_hnp_support = get_a_hnp_support(pcd);
57419 + gadget_wrapper->gadget.a_alt_hnp_support = get_a_alt_hnp_support(pcd);
57420 + return 0;
57421 +}
57422 +
57423 +static int _reset(dwc_otg_pcd_t * pcd)
57424 +{
57425 + return 0;
57426 +}
57427 +
57428 +#ifdef DWC_UTE_CFI
57429 +static int _cfi_setup(dwc_otg_pcd_t * pcd, void *cfi_req)
57430 +{
57431 + int retval = -DWC_E_INVALID;
57432 + if (gadget_wrapper->driver->cfi_feature_setup) {
57433 + retval =
57434 + gadget_wrapper->driver->
57435 + cfi_feature_setup(&gadget_wrapper->gadget,
57436 + (struct cfi_usb_ctrlrequest *)cfi_req);
57437 + }
57438 +
57439 + return retval;
57440 +}
57441 +#endif
57442 +
57443 +static const struct dwc_otg_pcd_function_ops fops = {
57444 + .complete = _complete,
57445 +#ifdef DWC_EN_ISOC
57446 + .isoc_complete = _isoc_complete,
57447 +#endif
57448 + .setup = _setup,
57449 + .disconnect = _disconnect,
57450 + .connect = _connect,
57451 + .resume = _resume,
57452 + .suspend = _suspend,
57453 + .hnp_changed = _hnp_changed,
57454 + .reset = _reset,
57455 +#ifdef DWC_UTE_CFI
57456 + .cfi_setup = _cfi_setup,
57457 +#endif
57458 +#ifdef DWC_UTE_PER_IO
57459 + .xisoc_complete = _xisoc_complete,
57460 +#endif
57461 +};
57462 +
57463 +/**
57464 + * This function is the top level PCD interrupt handler.
57465 + */
57466 +static irqreturn_t dwc_otg_pcd_irq(int irq, void *dev)
57467 +{
57468 + dwc_otg_pcd_t *pcd = dev;
57469 + int32_t retval = IRQ_NONE;
57470 +
57471 + retval = dwc_otg_pcd_handle_intr(pcd);
57472 + if (retval != 0) {
57473 + S3C2410X_CLEAR_EINTPEND();
57474 + }
57475 + return IRQ_RETVAL(retval);
57476 +}
57477 +
57478 +/**
57479 + * This function initialized the usb_ep structures to there default
57480 + * state.
57481 + *
57482 + * @param d Pointer on gadget_wrapper.
57483 + */
57484 +void gadget_add_eps(struct gadget_wrapper *d)
57485 +{
57486 + static const char *names[] = {
57487 +
57488 + "ep0",
57489 + "ep1in",
57490 + "ep2in",
57491 + "ep3in",
57492 + "ep4in",
57493 + "ep5in",
57494 + "ep6in",
57495 + "ep7in",
57496 + "ep8in",
57497 + "ep9in",
57498 + "ep10in",
57499 + "ep11in",
57500 + "ep12in",
57501 + "ep13in",
57502 + "ep14in",
57503 + "ep15in",
57504 + "ep1out",
57505 + "ep2out",
57506 + "ep3out",
57507 + "ep4out",
57508 + "ep5out",
57509 + "ep6out",
57510 + "ep7out",
57511 + "ep8out",
57512 + "ep9out",
57513 + "ep10out",
57514 + "ep11out",
57515 + "ep12out",
57516 + "ep13out",
57517 + "ep14out",
57518 + "ep15out"
57519 + };
57520 +
57521 + int i;
57522 + struct usb_ep *ep;
57523 + int8_t dev_endpoints;
57524 +
57525 + DWC_DEBUGPL(DBG_PCDV, "%s\n", __func__);
57526 +
57527 + INIT_LIST_HEAD(&d->gadget.ep_list);
57528 + d->gadget.ep0 = &d->ep0;
57529 + d->gadget.speed = USB_SPEED_UNKNOWN;
57530 +
57531 + INIT_LIST_HEAD(&d->gadget.ep0->ep_list);
57532 +
57533 + /**
57534 + * Initialize the EP0 structure.
57535 + */
57536 + ep = &d->ep0;
57537 +
57538 + /* Init the usb_ep structure. */
57539 + ep->name = names[0];
57540 + ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
57541 +
57542 + /**
57543 + * @todo NGS: What should the max packet size be set to
57544 + * here? Before EP type is set?
57545 + */
57546 + ep->maxpacket = MAX_PACKET_SIZE;
57547 + dwc_otg_pcd_ep_enable(d->pcd, NULL, ep);
57548 +
57549 + list_add_tail(&ep->ep_list, &d->gadget.ep_list);
57550 +
57551 + /**
57552 + * Initialize the EP structures.
57553 + */
57554 + dev_endpoints = d->pcd->core_if->dev_if->num_in_eps;
57555 +
57556 + for (i = 0; i < dev_endpoints; i++) {
57557 + ep = &d->in_ep[i];
57558 +
57559 + /* Init the usb_ep structure. */
57560 + ep->name = names[d->pcd->in_ep[i].dwc_ep.num];
57561 + ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
57562 +
57563 + /**
57564 + * @todo NGS: What should the max packet size be set to
57565 + * here? Before EP type is set?
57566 + */
57567 + ep->maxpacket = MAX_PACKET_SIZE;
57568 + list_add_tail(&ep->ep_list, &d->gadget.ep_list);
57569 + }
57570 +
57571 + dev_endpoints = d->pcd->core_if->dev_if->num_out_eps;
57572 +
57573 + for (i = 0; i < dev_endpoints; i++) {
57574 + ep = &d->out_ep[i];
57575 +
57576 + /* Init the usb_ep structure. */
57577 + ep->name = names[15 + d->pcd->out_ep[i].dwc_ep.num];
57578 + ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
57579 +
57580 + /**
57581 + * @todo NGS: What should the max packet size be set to
57582 + * here? Before EP type is set?
57583 + */
57584 + ep->maxpacket = MAX_PACKET_SIZE;
57585 +
57586 + list_add_tail(&ep->ep_list, &d->gadget.ep_list);
57587 + }
57588 +
57589 + /* remove ep0 from the list. There is a ep0 pointer. */
57590 + list_del_init(&d->ep0.ep_list);
57591 +
57592 + d->ep0.maxpacket = MAX_EP0_SIZE;
57593 +}
57594 +
57595 +/**
57596 + * This function releases the Gadget device.
57597 + * required by device_unregister().
57598 + *
57599 + * @todo Should this do something? Should it free the PCD?
57600 + */
57601 +static void dwc_otg_pcd_gadget_release(struct device *dev)
57602 +{
57603 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, dev);
57604 +}
57605 +
57606 +static struct gadget_wrapper *alloc_wrapper(dwc_bus_dev_t *_dev)
57607 +{
57608 + static char pcd_name[] = "dwc_otg_pcd";
57609 + dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
57610 + struct gadget_wrapper *d;
57611 + int retval;
57612 +
57613 + d = DWC_ALLOC(sizeof(*d));
57614 + if (d == NULL) {
57615 + return NULL;
57616 + }
57617 +
57618 + memset(d, 0, sizeof(*d));
57619 +
57620 + d->gadget.name = pcd_name;
57621 + d->pcd = otg_dev->pcd;
57622 +
57623 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
57624 + strcpy(d->gadget.dev.bus_id, "gadget");
57625 +#else
57626 + dev_set_name(&d->gadget.dev, "%s", "gadget");
57627 +#endif
57628 +
57629 + d->gadget.dev.parent = &_dev->dev;
57630 + d->gadget.dev.release = dwc_otg_pcd_gadget_release;
57631 + d->gadget.ops = &dwc_otg_pcd_ops;
57632 + d->gadget.max_speed = dwc_otg_pcd_is_dualspeed(otg_dev->pcd) ? USB_SPEED_HIGH:USB_SPEED_FULL;
57633 + d->gadget.is_otg = dwc_otg_pcd_is_otg(otg_dev->pcd);
57634 +
57635 + d->driver = 0;
57636 + /* Register the gadget device */
57637 + retval = device_register(&d->gadget.dev);
57638 + if (retval != 0) {
57639 + DWC_ERROR("device_register failed\n");
57640 + DWC_FREE(d);
57641 + return NULL;
57642 + }
57643 +
57644 + return d;
57645 +}
57646 +
57647 +static void free_wrapper(struct gadget_wrapper *d)
57648 +{
57649 + if (d->driver) {
57650 + /* should have been done already by driver model core */
57651 + DWC_WARN("driver '%s' is still registered\n",
57652 + d->driver->driver.name);
57653 + usb_gadget_unregister_driver(d->driver);
57654 + }
57655 +
57656 + device_unregister(&d->gadget.dev);
57657 + DWC_FREE(d);
57658 +}
57659 +
57660 +/**
57661 + * This function initialized the PCD portion of the driver.
57662 + *
57663 + */
57664 +int pcd_init(dwc_bus_dev_t *_dev)
57665 +{
57666 + dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
57667 + int retval = 0;
57668 +
57669 + DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev=%p\n", __func__, _dev, otg_dev);
57670 +
57671 + otg_dev->pcd = dwc_otg_pcd_init(otg_dev->core_if);
57672 +
57673 + if (!otg_dev->pcd) {
57674 + DWC_ERROR("dwc_otg_pcd_init failed\n");
57675 + return -ENOMEM;
57676 + }
57677 +
57678 + otg_dev->pcd->otg_dev = otg_dev;
57679 + gadget_wrapper = alloc_wrapper(_dev);
57680 +
57681 + /*
57682 + * Initialize EP structures
57683 + */
57684 + gadget_add_eps(gadget_wrapper);
57685 + /*
57686 + * Setup interupt handler
57687 + */
57688 +#ifdef PLATFORM_INTERFACE
57689 + DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n",
57690 + platform_get_irq(_dev, fiq_enable ? 0 : 1));
57691 + retval = request_irq(platform_get_irq(_dev, fiq_enable ? 0 : 1), dwc_otg_pcd_irq,
57692 + IRQF_SHARED, gadget_wrapper->gadget.name,
57693 + otg_dev->pcd);
57694 + if (retval != 0) {
57695 + DWC_ERROR("request of irq%d failed\n",
57696 + platform_get_irq(_dev, fiq_enable ? 0 : 1));
57697 + free_wrapper(gadget_wrapper);
57698 + return -EBUSY;
57699 + }
57700 +#else
57701 + DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n",
57702 + _dev->irq);
57703 + retval = request_irq(_dev->irq, dwc_otg_pcd_irq,
57704 + IRQF_SHARED | IRQF_DISABLED,
57705 + gadget_wrapper->gadget.name, otg_dev->pcd);
57706 + if (retval != 0) {
57707 + DWC_ERROR("request of irq%d failed\n", _dev->irq);
57708 + free_wrapper(gadget_wrapper);
57709 + return -EBUSY;
57710 + }
57711 +#endif
57712 +
57713 + dwc_otg_pcd_start(gadget_wrapper->pcd, &fops);
57714 +
57715 + return retval;
57716 +}
57717 +
57718 +/**
57719 + * Cleanup the PCD.
57720 + */
57721 +void pcd_remove(dwc_bus_dev_t *_dev)
57722 +{
57723 + dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
57724 + dwc_otg_pcd_t *pcd = otg_dev->pcd;
57725 +
57726 + DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev);
57727 +
57728 + /*
57729 + * Free the IRQ
57730 + */
57731 +#ifdef PLATFORM_INTERFACE
57732 + free_irq(platform_get_irq(_dev, 0), pcd);
57733 +#else
57734 + free_irq(_dev->irq, pcd);
57735 +#endif
57736 + dwc_otg_pcd_remove(otg_dev->pcd);
57737 + free_wrapper(gadget_wrapper);
57738 + otg_dev->pcd = 0;
57739 +}
57740 +
57741 +/**
57742 + * This function registers a gadget driver with the PCD.
57743 + *
57744 + * When a driver is successfully registered, it will receive control
57745 + * requests including set_configuration(), which enables non-control
57746 + * requests. then usb traffic follows until a disconnect is reported.
57747 + * then a host may connect again, or the driver might get unbound.
57748 + *
57749 + * @param driver The driver being registered
57750 + * @param bind The bind function of gadget driver
57751 + */
57752 +
57753 +int usb_gadget_probe_driver(struct usb_gadget_driver *driver)
57754 +{
57755 + int retval;
57756 +
57757 + DWC_DEBUGPL(DBG_PCD, "registering gadget driver '%s'\n",
57758 + driver->driver.name);
57759 +
57760 + if (!driver || driver->max_speed == USB_SPEED_UNKNOWN ||
57761 + !driver->bind ||
57762 + !driver->unbind || !driver->disconnect || !driver->setup) {
57763 + DWC_DEBUGPL(DBG_PCDV, "EINVAL\n");
57764 + return -EINVAL;
57765 + }
57766 + if (gadget_wrapper == 0) {
57767 + DWC_DEBUGPL(DBG_PCDV, "ENODEV\n");
57768 + return -ENODEV;
57769 + }
57770 + if (gadget_wrapper->driver != 0) {
57771 + DWC_DEBUGPL(DBG_PCDV, "EBUSY (%p)\n", gadget_wrapper->driver);
57772 + return -EBUSY;
57773 + }
57774 +
57775 + /* hook up the driver */
57776 + gadget_wrapper->driver = driver;
57777 + gadget_wrapper->gadget.dev.driver = &driver->driver;
57778 +
57779 + DWC_DEBUGPL(DBG_PCD, "bind to driver %s\n", driver->driver.name);
57780 + retval = driver->bind(&gadget_wrapper->gadget, gadget_wrapper->driver);
57781 + if (retval) {
57782 + DWC_ERROR("bind to driver %s --> error %d\n",
57783 + driver->driver.name, retval);
57784 + gadget_wrapper->driver = 0;
57785 + gadget_wrapper->gadget.dev.driver = 0;
57786 + return retval;
57787 + }
57788 + DWC_DEBUGPL(DBG_ANY, "registered gadget driver '%s'\n",
57789 + driver->driver.name);
57790 + return 0;
57791 +}
57792 +EXPORT_SYMBOL(usb_gadget_probe_driver);
57793 +
57794 +/**
57795 + * This function unregisters a gadget driver
57796 + *
57797 + * @param driver The driver being unregistered
57798 + */
57799 +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
57800 +{
57801 + //DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, _driver);
57802 +
57803 + if (gadget_wrapper == 0) {
57804 + DWC_DEBUGPL(DBG_ANY, "%s Return(%d): s_pcd==0\n", __func__,
57805 + -ENODEV);
57806 + return -ENODEV;
57807 + }
57808 + if (driver == 0 || driver != gadget_wrapper->driver) {
57809 + DWC_DEBUGPL(DBG_ANY, "%s Return(%d): driver?\n", __func__,
57810 + -EINVAL);
57811 + return -EINVAL;
57812 + }
57813 +
57814 + driver->unbind(&gadget_wrapper->gadget);
57815 + gadget_wrapper->driver = 0;
57816 +
57817 + DWC_DEBUGPL(DBG_ANY, "unregistered driver '%s'\n", driver->driver.name);
57818 + return 0;
57819 +}
57820 +
57821 +EXPORT_SYMBOL(usb_gadget_unregister_driver);
57822 +
57823 +#endif /* DWC_HOST_ONLY */
57824 --- /dev/null
57825 +++ b/drivers/usb/host/dwc_otg/dwc_otg_regs.h
57826 @@ -0,0 +1,2550 @@
57827 +/* ==========================================================================
57828 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $
57829 + * $Revision: #98 $
57830 + * $Date: 2012/08/10 $
57831 + * $Change: 2047372 $
57832 + *
57833 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
57834 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
57835 + * otherwise expressly agreed to in writing between Synopsys and you.
57836 + *
57837 + * The Software IS NOT an item of Licensed Software or Licensed Product under
57838 + * any End User Software License Agreement or Agreement for Licensed Product
57839 + * with Synopsys or any supplement thereto. You are permitted to use and
57840 + * redistribute this Software in source and binary forms, with or without
57841 + * modification, provided that redistributions of source code must retain this
57842 + * notice. You may not view, use, disclose, copy or distribute this file or
57843 + * any information contained herein except pursuant to this license grant from
57844 + * Synopsys. If you do not agree with this notice, including the disclaimer
57845 + * below, then you are not authorized to use the Software.
57846 + *
57847 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
57848 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
57849 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
57850 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
57851 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
57852 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
57853 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
57854 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
57855 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
57856 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
57857 + * DAMAGE.
57858 + * ========================================================================== */
57859 +
57860 +#ifndef __DWC_OTG_REGS_H__
57861 +#define __DWC_OTG_REGS_H__
57862 +
57863 +#include "dwc_otg_core_if.h"
57864 +
57865 +/**
57866 + * @file
57867 + *
57868 + * This file contains the data structures for accessing the DWC_otg core registers.
57869 + *
57870 + * The application interfaces with the HS OTG core by reading from and
57871 + * writing to the Control and Status Register (CSR) space through the
57872 + * AHB Slave interface. These registers are 32 bits wide, and the
57873 + * addresses are 32-bit-block aligned.
57874 + * CSRs are classified as follows:
57875 + * - Core Global Registers
57876 + * - Device Mode Registers
57877 + * - Device Global Registers
57878 + * - Device Endpoint Specific Registers
57879 + * - Host Mode Registers
57880 + * - Host Global Registers
57881 + * - Host Port CSRs
57882 + * - Host Channel Specific Registers
57883 + *
57884 + * Only the Core Global registers can be accessed in both Device and
57885 + * Host modes. When the HS OTG core is operating in one mode, either
57886 + * Device or Host, the application must not access registers from the
57887 + * other mode. When the core switches from one mode to another, the
57888 + * registers in the new mode of operation must be reprogrammed as they
57889 + * would be after a power-on reset.
57890 + */
57891 +
57892 +/****************************************************************************/
57893 +/** DWC_otg Core registers .
57894 + * The dwc_otg_core_global_regs structure defines the size
57895 + * and relative field offsets for the Core Global registers.
57896 + */
57897 +typedef struct dwc_otg_core_global_regs {
57898 + /** OTG Control and Status Register. <i>Offset: 000h</i> */
57899 + volatile uint32_t gotgctl;
57900 + /** OTG Interrupt Register. <i>Offset: 004h</i> */
57901 + volatile uint32_t gotgint;
57902 + /**Core AHB Configuration Register. <i>Offset: 008h</i> */
57903 + volatile uint32_t gahbcfg;
57904 +
57905 +#define DWC_GLBINTRMASK 0x0001
57906 +#define DWC_DMAENABLE 0x0020
57907 +#define DWC_NPTXEMPTYLVL_EMPTY 0x0080
57908 +#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000
57909 +#define DWC_PTXEMPTYLVL_EMPTY 0x0100
57910 +#define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000
57911 +
57912 + /**Core USB Configuration Register. <i>Offset: 00Ch</i> */
57913 + volatile uint32_t gusbcfg;
57914 + /**Core Reset Register. <i>Offset: 010h</i> */
57915 + volatile uint32_t grstctl;
57916 + /**Core Interrupt Register. <i>Offset: 014h</i> */
57917 + volatile uint32_t gintsts;
57918 + /**Core Interrupt Mask Register. <i>Offset: 018h</i> */
57919 + volatile uint32_t gintmsk;
57920 + /**Receive Status Queue Read Register (Read Only). <i>Offset: 01Ch</i> */
57921 + volatile uint32_t grxstsr;
57922 + /**Receive Status Queue Read & POP Register (Read Only). <i>Offset: 020h</i>*/
57923 + volatile uint32_t grxstsp;
57924 + /**Receive FIFO Size Register. <i>Offset: 024h</i> */
57925 + volatile uint32_t grxfsiz;
57926 + /**Non Periodic Transmit FIFO Size Register. <i>Offset: 028h</i> */
57927 + volatile uint32_t gnptxfsiz;
57928 + /**Non Periodic Transmit FIFO/Queue Status Register (Read
57929 + * Only). <i>Offset: 02Ch</i> */
57930 + volatile uint32_t gnptxsts;
57931 + /**I2C Access Register. <i>Offset: 030h</i> */
57932 + volatile uint32_t gi2cctl;
57933 + /**PHY Vendor Control Register. <i>Offset: 034h</i> */
57934 + volatile uint32_t gpvndctl;
57935 + /**General Purpose Input/Output Register. <i>Offset: 038h</i> */
57936 + volatile uint32_t ggpio;
57937 + /**User ID Register. <i>Offset: 03Ch</i> */
57938 + volatile uint32_t guid;
57939 + /**Synopsys ID Register (Read Only). <i>Offset: 040h</i> */
57940 + volatile uint32_t gsnpsid;
57941 + /**User HW Config1 Register (Read Only). <i>Offset: 044h</i> */
57942 + volatile uint32_t ghwcfg1;
57943 + /**User HW Config2 Register (Read Only). <i>Offset: 048h</i> */
57944 + volatile uint32_t ghwcfg2;
57945 +#define DWC_SLAVE_ONLY_ARCH 0
57946 +#define DWC_EXT_DMA_ARCH 1
57947 +#define DWC_INT_DMA_ARCH 2
57948 +
57949 +#define DWC_MODE_HNP_SRP_CAPABLE 0
57950 +#define DWC_MODE_SRP_ONLY_CAPABLE 1
57951 +#define DWC_MODE_NO_HNP_SRP_CAPABLE 2
57952 +#define DWC_MODE_SRP_CAPABLE_DEVICE 3
57953 +#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4
57954 +#define DWC_MODE_SRP_CAPABLE_HOST 5
57955 +#define DWC_MODE_NO_SRP_CAPABLE_HOST 6
57956 +
57957 + /**User HW Config3 Register (Read Only). <i>Offset: 04Ch</i> */
57958 + volatile uint32_t ghwcfg3;
57959 + /**User HW Config4 Register (Read Only). <i>Offset: 050h</i>*/
57960 + volatile uint32_t ghwcfg4;
57961 + /** Core LPM Configuration register <i>Offset: 054h</i>*/
57962 + volatile uint32_t glpmcfg;
57963 + /** Global PowerDn Register <i>Offset: 058h</i> */
57964 + volatile uint32_t gpwrdn;
57965 + /** Global DFIFO SW Config Register <i>Offset: 05Ch</i> */
57966 + volatile uint32_t gdfifocfg;
57967 + /** ADP Control Register <i>Offset: 060h</i> */
57968 + volatile uint32_t adpctl;
57969 + /** Reserved <i>Offset: 064h-0FFh</i> */
57970 + volatile uint32_t reserved39[39];
57971 + /** Host Periodic Transmit FIFO Size Register. <i>Offset: 100h</i> */
57972 + volatile uint32_t hptxfsiz;
57973 + /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled,
57974 + otherwise Device Transmit FIFO#n Register.
57975 + * <i>Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).</i> */
57976 + volatile uint32_t dtxfsiz[15];
57977 +} dwc_otg_core_global_regs_t;
57978 +
57979 +/**
57980 + * This union represents the bit fields of the Core OTG Control
57981 + * and Status Register (GOTGCTL). Set the bits using the bit
57982 + * fields then write the <i>d32</i> value to the register.
57983 + */
57984 +typedef union gotgctl_data {
57985 + /** raw register data */
57986 + uint32_t d32;
57987 + /** register bits */
57988 + struct {
57989 + unsigned sesreqscs:1;
57990 + unsigned sesreq:1;
57991 + unsigned vbvalidoven:1;
57992 + unsigned vbvalidovval:1;
57993 + unsigned avalidoven:1;
57994 + unsigned avalidovval:1;
57995 + unsigned bvalidoven:1;
57996 + unsigned bvalidovval:1;
57997 + unsigned hstnegscs:1;
57998 + unsigned hnpreq:1;
57999 + unsigned hstsethnpen:1;
58000 + unsigned devhnpen:1;
58001 + unsigned reserved12_15:4;
58002 + unsigned conidsts:1;
58003 + unsigned dbnctime:1;
58004 + unsigned asesvld:1;
58005 + unsigned bsesvld:1;
58006 + unsigned otgver:1;
58007 + unsigned reserved1:1;
58008 + unsigned multvalidbc:5;
58009 + unsigned chirpen:1;
58010 + unsigned reserved28_31:4;
58011 + } b;
58012 +} gotgctl_data_t;
58013 +
58014 +/**
58015 + * This union represents the bit fields of the Core OTG Interrupt Register
58016 + * (GOTGINT). Set/clear the bits using the bit fields then write the <i>d32</i>
58017 + * value to the register.
58018 + */
58019 +typedef union gotgint_data {
58020 + /** raw register data */
58021 + uint32_t d32;
58022 + /** register bits */
58023 + struct {
58024 + /** Current Mode */
58025 + unsigned reserved0_1:2;
58026 +
58027 + /** Session End Detected */
58028 + unsigned sesenddet:1;
58029 +
58030 + unsigned reserved3_7:5;
58031 +
58032 + /** Session Request Success Status Change */
58033 + unsigned sesreqsucstschng:1;
58034 + /** Host Negotiation Success Status Change */
58035 + unsigned hstnegsucstschng:1;
58036 +
58037 + unsigned reserved10_16:7;
58038 +
58039 + /** Host Negotiation Detected */
58040 + unsigned hstnegdet:1;
58041 + /** A-Device Timeout Change */
58042 + unsigned adevtoutchng:1;
58043 + /** Debounce Done */
58044 + unsigned debdone:1;
58045 + /** Multi-Valued input changed */
58046 + unsigned mvic:1;
58047 +
58048 + unsigned reserved31_21:11;
58049 +
58050 + } b;
58051 +} gotgint_data_t;
58052 +
58053 +/**
58054 + * This union represents the bit fields of the Core AHB Configuration
58055 + * Register (GAHBCFG). Set/clear the bits using the bit fields then
58056 + * write the <i>d32</i> value to the register.
58057 + */
58058 +typedef union gahbcfg_data {
58059 + /** raw register data */
58060 + uint32_t d32;
58061 + /** register bits */
58062 + struct {
58063 + unsigned glblintrmsk:1;
58064 +#define DWC_GAHBCFG_GLBINT_ENABLE 1
58065 +
58066 + unsigned hburstlen:4;
58067 +#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0
58068 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1
58069 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3
58070 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5
58071 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7
58072 +
58073 + unsigned dmaenable:1;
58074 +#define DWC_GAHBCFG_DMAENABLE 1
58075 + unsigned reserved:1;
58076 + unsigned nptxfemplvl_txfemplvl:1;
58077 + unsigned ptxfemplvl:1;
58078 +#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1
58079 +#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
58080 + unsigned reserved9_20:12;
58081 + unsigned remmemsupp:1;
58082 + unsigned notialldmawrit:1;
58083 + unsigned ahbsingle:1;
58084 + unsigned reserved24_31:8;
58085 + } b;
58086 +} gahbcfg_data_t;
58087 +
58088 +/**
58089 + * This union represents the bit fields of the Core USB Configuration
58090 + * Register (GUSBCFG). Set the bits using the bit fields then write
58091 + * the <i>d32</i> value to the register.
58092 + */
58093 +typedef union gusbcfg_data {
58094 + /** raw register data */
58095 + uint32_t d32;
58096 + /** register bits */
58097 + struct {
58098 + unsigned toutcal:3;
58099 + unsigned phyif:1;
58100 + unsigned ulpi_utmi_sel:1;
58101 + unsigned fsintf:1;
58102 + unsigned physel:1;
58103 + unsigned ddrsel:1;
58104 + unsigned srpcap:1;
58105 + unsigned hnpcap:1;
58106 + unsigned usbtrdtim:4;
58107 + unsigned reserved1:1;
58108 + unsigned phylpwrclksel:1;
58109 + unsigned otgutmifssel:1;
58110 + unsigned ulpi_fsls:1;
58111 + unsigned ulpi_auto_res:1;
58112 + unsigned ulpi_clk_sus_m:1;
58113 + unsigned ulpi_ext_vbus_drv:1;
58114 + unsigned ulpi_int_vbus_indicator:1;
58115 + unsigned term_sel_dl_pulse:1;
58116 + unsigned indicator_complement:1;
58117 + unsigned indicator_pass_through:1;
58118 + unsigned ulpi_int_prot_dis:1;
58119 + unsigned ic_usb_cap:1;
58120 + unsigned ic_traffic_pull_remove:1;
58121 + unsigned tx_end_delay:1;
58122 + unsigned force_host_mode:1;
58123 + unsigned force_dev_mode:1;
58124 + unsigned reserved31:1;
58125 + } b;
58126 +} gusbcfg_data_t;
58127 +
58128 +/**
58129 + * This union represents the bit fields of the Core Reset Register
58130 + * (GRSTCTL). Set/clear the bits using the bit fields then write the
58131 + * <i>d32</i> value to the register.
58132 + */
58133 +typedef union grstctl_data {
58134 + /** raw register data */
58135 + uint32_t d32;
58136 + /** register bits */
58137 + struct {
58138 + /** Core Soft Reset (CSftRst) (Device and Host)
58139 + *
58140 + * The application can flush the control logic in the
58141 + * entire core using this bit. This bit resets the
58142 + * pipelines in the AHB Clock domain as well as the
58143 + * PHY Clock domain.
58144 + *
58145 + * The state machines are reset to an IDLE state, the
58146 + * control bits in the CSRs are cleared, all the
58147 + * transmit FIFOs and the receive FIFO are flushed.
58148 + *
58149 + * The status mask bits that control the generation of
58150 + * the interrupt, are cleared, to clear the
58151 + * interrupt. The interrupt status bits are not
58152 + * cleared, so the application can get the status of
58153 + * any events that occurred in the core after it has
58154 + * set this bit.
58155 + *
58156 + * Any transactions on the AHB are terminated as soon
58157 + * as possible following the protocol. Any
58158 + * transactions on the USB are terminated immediately.
58159 + *
58160 + * The configuration settings in the CSRs are
58161 + * unchanged, so the software doesn't have to
58162 + * reprogram these registers (Device
58163 + * Configuration/Host Configuration/Core System
58164 + * Configuration/Core PHY Configuration).
58165 + *
58166 + * The application can write to this bit, any time it
58167 + * wants to reset the core. This is a self clearing
58168 + * bit and the core clears this bit after all the
58169 + * necessary logic is reset in the core, which may
58170 + * take several clocks, depending on the current state
58171 + * of the core.
58172 + */
58173 + unsigned csftrst:1;
58174 + /** Hclk Soft Reset
58175 + *
58176 + * The application uses this bit to reset the control logic in
58177 + * the AHB clock domain. Only AHB clock domain pipelines are
58178 + * reset.
58179 + */
58180 + unsigned hsftrst:1;
58181 + /** Host Frame Counter Reset (Host Only)<br>
58182 + *
58183 + * The application can reset the (micro)frame number
58184 + * counter inside the core, using this bit. When the
58185 + * (micro)frame counter is reset, the subsequent SOF
58186 + * sent out by the core, will have a (micro)frame
58187 + * number of 0.
58188 + */
58189 + unsigned hstfrm:1;
58190 + /** In Token Sequence Learning Queue Flush
58191 + * (INTknQFlsh) (Device Only)
58192 + */
58193 + unsigned intknqflsh:1;
58194 + /** RxFIFO Flush (RxFFlsh) (Device and Host)
58195 + *
58196 + * The application can flush the entire Receive FIFO
58197 + * using this bit. The application must first
58198 + * ensure that the core is not in the middle of a
58199 + * transaction. The application should write into
58200 + * this bit, only after making sure that neither the
58201 + * DMA engine is reading from the RxFIFO nor the MAC
58202 + * is writing the data in to the FIFO. The
58203 + * application should wait until the bit is cleared
58204 + * before performing any other operations. This bit
58205 + * will takes 8 clocks (slowest of PHY or AHB clock)
58206 + * to clear.
58207 + */
58208 + unsigned rxfflsh:1;
58209 + /** TxFIFO Flush (TxFFlsh) (Device and Host).
58210 + *
58211 + * This bit is used to selectively flush a single or
58212 + * all transmit FIFOs. The application must first
58213 + * ensure that the core is not in the middle of a
58214 + * transaction. The application should write into
58215 + * this bit, only after making sure that neither the
58216 + * DMA engine is writing into the TxFIFO nor the MAC
58217 + * is reading the data out of the FIFO. The
58218 + * application should wait until the core clears this
58219 + * bit, before performing any operations. This bit
58220 + * will takes 8 clocks (slowest of PHY or AHB clock)
58221 + * to clear.
58222 + */
58223 + unsigned txfflsh:1;
58224 +
58225 + /** TxFIFO Number (TxFNum) (Device and Host).
58226 + *
58227 + * This is the FIFO number which needs to be flushed,
58228 + * using the TxFIFO Flush bit. This field should not
58229 + * be changed until the TxFIFO Flush bit is cleared by
58230 + * the core.
58231 + * - 0x0 : Non Periodic TxFIFO Flush
58232 + * - 0x1 : Periodic TxFIFO #1 Flush in device mode
58233 + * or Periodic TxFIFO in host mode
58234 + * - 0x2 : Periodic TxFIFO #2 Flush in device mode.
58235 + * - ...
58236 + * - 0xF : Periodic TxFIFO #15 Flush in device mode
58237 + * - 0x10: Flush all the Transmit NonPeriodic and
58238 + * Transmit Periodic FIFOs in the core
58239 + */
58240 + unsigned txfnum:5;
58241 + /** Reserved */
58242 + unsigned reserved11_29:19;
58243 + /** DMA Request Signal. Indicated DMA request is in
58244 + * probress. Used for debug purpose. */
58245 + unsigned dmareq:1;
58246 + /** AHB Master Idle. Indicates the AHB Master State
58247 + * Machine is in IDLE condition. */
58248 + unsigned ahbidle:1;
58249 + } b;
58250 +} grstctl_t;
58251 +
58252 +/**
58253 + * This union represents the bit fields of the Core Interrupt Mask
58254 + * Register (GINTMSK). Set/clear the bits using the bit fields then
58255 + * write the <i>d32</i> value to the register.
58256 + */
58257 +typedef union gintmsk_data {
58258 + /** raw register data */
58259 + uint32_t d32;
58260 + /** register bits */
58261 + struct {
58262 + unsigned reserved0:1;
58263 + unsigned modemismatch:1;
58264 + unsigned otgintr:1;
58265 + unsigned sofintr:1;
58266 + unsigned rxstsqlvl:1;
58267 + unsigned nptxfempty:1;
58268 + unsigned ginnakeff:1;
58269 + unsigned goutnakeff:1;
58270 + unsigned ulpickint:1;
58271 + unsigned i2cintr:1;
58272 + unsigned erlysuspend:1;
58273 + unsigned usbsuspend:1;
58274 + unsigned usbreset:1;
58275 + unsigned enumdone:1;
58276 + unsigned isooutdrop:1;
58277 + unsigned eopframe:1;
58278 + unsigned restoredone:1;
58279 + unsigned epmismatch:1;
58280 + unsigned inepintr:1;
58281 + unsigned outepintr:1;
58282 + unsigned incomplisoin:1;
58283 + unsigned incomplisoout:1;
58284 + unsigned fetsusp:1;
58285 + unsigned resetdet:1;
58286 + unsigned portintr:1;
58287 + unsigned hcintr:1;
58288 + unsigned ptxfempty:1;
58289 + unsigned lpmtranrcvd:1;
58290 + unsigned conidstschng:1;
58291 + unsigned disconnect:1;
58292 + unsigned sessreqintr:1;
58293 + unsigned wkupintr:1;
58294 + } b;
58295 +} gintmsk_data_t;
58296 +/**
58297 + * This union represents the bit fields of the Core Interrupt Register
58298 + * (GINTSTS). Set/clear the bits using the bit fields then write the
58299 + * <i>d32</i> value to the register.
58300 + */
58301 +typedef union gintsts_data {
58302 + /** raw register data */
58303 + uint32_t d32;
58304 +#define DWC_SOF_INTR_MASK 0x0008
58305 + /** register bits */
58306 + struct {
58307 +#define DWC_HOST_MODE 1
58308 + unsigned curmode:1;
58309 + unsigned modemismatch:1;
58310 + unsigned otgintr:1;
58311 + unsigned sofintr:1;
58312 + unsigned rxstsqlvl:1;
58313 + unsigned nptxfempty:1;
58314 + unsigned ginnakeff:1;
58315 + unsigned goutnakeff:1;
58316 + unsigned ulpickint:1;
58317 + unsigned i2cintr:1;
58318 + unsigned erlysuspend:1;
58319 + unsigned usbsuspend:1;
58320 + unsigned usbreset:1;
58321 + unsigned enumdone:1;
58322 + unsigned isooutdrop:1;
58323 + unsigned eopframe:1;
58324 + unsigned restoredone:1;
58325 + unsigned epmismatch:1;
58326 + unsigned inepint:1;
58327 + unsigned outepintr:1;
58328 + unsigned incomplisoin:1;
58329 + unsigned incomplisoout:1;
58330 + unsigned fetsusp:1;
58331 + unsigned resetdet:1;
58332 + unsigned portintr:1;
58333 + unsigned hcintr:1;
58334 + unsigned ptxfempty:1;
58335 + unsigned lpmtranrcvd:1;
58336 + unsigned conidstschng:1;
58337 + unsigned disconnect:1;
58338 + unsigned sessreqintr:1;
58339 + unsigned wkupintr:1;
58340 + } b;
58341 +} gintsts_data_t;
58342 +
58343 +/**
58344 + * This union represents the bit fields in the Device Receive Status Read and
58345 + * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
58346 + * element then read out the bits using the <i>b</i>it elements.
58347 + */
58348 +typedef union device_grxsts_data {
58349 + /** raw register data */
58350 + uint32_t d32;
58351 + /** register bits */
58352 + struct {
58353 + unsigned epnum:4;
58354 + unsigned bcnt:11;
58355 + unsigned dpid:2;
58356 +
58357 +#define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet
58358 +#define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete
58359 +
58360 +#define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK
58361 +#define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete
58362 +#define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet
58363 + unsigned pktsts:4;
58364 + unsigned fn:4;
58365 + unsigned reserved25_31:7;
58366 + } b;
58367 +} device_grxsts_data_t;
58368 +
58369 +/**
58370 + * This union represents the bit fields in the Host Receive Status Read and
58371 + * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
58372 + * element then read out the bits using the <i>b</i>it elements.
58373 + */
58374 +typedef union host_grxsts_data {
58375 + /** raw register data */
58376 + uint32_t d32;
58377 + /** register bits */
58378 + struct {
58379 + unsigned chnum:4;
58380 + unsigned bcnt:11;
58381 + unsigned dpid:2;
58382 +
58383 + unsigned pktsts:4;
58384 +#define DWC_GRXSTS_PKTSTS_IN 0x2
58385 +#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3
58386 +#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5
58387 +#define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7
58388 +
58389 + unsigned reserved21_31:11;
58390 + } b;
58391 +} host_grxsts_data_t;
58392 +
58393 +/**
58394 + * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ,
58395 + * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the <i>d32</i> element
58396 + * then read out the bits using the <i>b</i>it elements.
58397 + */
58398 +typedef union fifosize_data {
58399 + /** raw register data */
58400 + uint32_t d32;
58401 + /** register bits */
58402 + struct {
58403 + unsigned startaddr:16;
58404 + unsigned depth:16;
58405 + } b;
58406 +} fifosize_data_t;
58407 +
58408 +/**
58409 + * This union represents the bit fields in the Non-Periodic Transmit
58410 + * FIFO/Queue Status Register (GNPTXSTS). Read the register into the
58411 + * <i>d32</i> element then read out the bits using the <i>b</i>it
58412 + * elements.
58413 + */
58414 +typedef union gnptxsts_data {
58415 + /** raw register data */
58416 + uint32_t d32;
58417 + /** register bits */
58418 + struct {
58419 + unsigned nptxfspcavail:16;
58420 + unsigned nptxqspcavail:8;
58421 + /** Top of the Non-Periodic Transmit Request Queue
58422 + * - bit 24 - Terminate (Last entry for the selected
58423 + * channel/EP)
58424 + * - bits 26:25 - Token Type
58425 + * - 2'b00 - IN/OUT
58426 + * - 2'b01 - Zero Length OUT
58427 + * - 2'b10 - PING/Complete Split
58428 + * - 2'b11 - Channel Halt
58429 + * - bits 30:27 - Channel/EP Number
58430 + */
58431 + unsigned nptxqtop_terminate:1;
58432 + unsigned nptxqtop_token:2;
58433 + unsigned nptxqtop_chnep:4;
58434 + unsigned reserved:1;
58435 + } b;
58436 +} gnptxsts_data_t;
58437 +
58438 +/**
58439 + * This union represents the bit fields in the Transmit
58440 + * FIFO Status Register (DTXFSTS). Read the register into the
58441 + * <i>d32</i> element then read out the bits using the <i>b</i>it
58442 + * elements.
58443 + */
58444 +typedef union dtxfsts_data {
58445 + /** raw register data */
58446 + uint32_t d32;
58447 + /** register bits */
58448 + struct {
58449 + unsigned txfspcavail:16;
58450 + unsigned reserved:16;
58451 + } b;
58452 +} dtxfsts_data_t;
58453 +
58454 +/**
58455 + * This union represents the bit fields in the I2C Control Register
58456 + * (I2CCTL). Read the register into the <i>d32</i> element then read out the
58457 + * bits using the <i>b</i>it elements.
58458 + */
58459 +typedef union gi2cctl_data {
58460 + /** raw register data */
58461 + uint32_t d32;
58462 + /** register bits */
58463 + struct {
58464 + unsigned rwdata:8;
58465 + unsigned regaddr:8;
58466 + unsigned addr:7;
58467 + unsigned i2cen:1;
58468 + unsigned ack:1;
58469 + unsigned i2csuspctl:1;
58470 + unsigned i2cdevaddr:2;
58471 + unsigned i2cdatse0:1;
58472 + unsigned reserved:1;
58473 + unsigned rw:1;
58474 + unsigned bsydne:1;
58475 + } b;
58476 +} gi2cctl_data_t;
58477 +
58478 +/**
58479 + * This union represents the bit fields in the PHY Vendor Control Register
58480 + * (GPVNDCTL). Read the register into the <i>d32</i> element then read out the
58481 + * bits using the <i>b</i>it elements.
58482 + */
58483 +typedef union gpvndctl_data {
58484 + /** raw register data */
58485 + uint32_t d32;
58486 + /** register bits */
58487 + struct {
58488 + unsigned regdata:8;
58489 + unsigned vctrl:8;
58490 + unsigned regaddr16_21:6;
58491 + unsigned regwr:1;
58492 + unsigned reserved23_24:2;
58493 + unsigned newregreq:1;
58494 + unsigned vstsbsy:1;
58495 + unsigned vstsdone:1;
58496 + unsigned reserved28_30:3;
58497 + unsigned disulpidrvr:1;
58498 + } b;
58499 +} gpvndctl_data_t;
58500 +
58501 +/**
58502 + * This union represents the bit fields in the General Purpose
58503 + * Input/Output Register (GGPIO).
58504 + * Read the register into the <i>d32</i> element then read out the
58505 + * bits using the <i>b</i>it elements.
58506 + */
58507 +typedef union ggpio_data {
58508 + /** raw register data */
58509 + uint32_t d32;
58510 + /** register bits */
58511 + struct {
58512 + unsigned gpi:16;
58513 + unsigned gpo:16;
58514 + } b;
58515 +} ggpio_data_t;
58516 +
58517 +/**
58518 + * This union represents the bit fields in the User ID Register
58519 + * (GUID). Read the register into the <i>d32</i> element then read out the
58520 + * bits using the <i>b</i>it elements.
58521 + */
58522 +typedef union guid_data {
58523 + /** raw register data */
58524 + uint32_t d32;
58525 + /** register bits */
58526 + struct {
58527 + unsigned rwdata:32;
58528 + } b;
58529 +} guid_data_t;
58530 +
58531 +/**
58532 + * This union represents the bit fields in the Synopsys ID Register
58533 + * (GSNPSID). Read the register into the <i>d32</i> element then read out the
58534 + * bits using the <i>b</i>it elements.
58535 + */
58536 +typedef union gsnpsid_data {
58537 + /** raw register data */
58538 + uint32_t d32;
58539 + /** register bits */
58540 + struct {
58541 + unsigned rwdata:32;
58542 + } b;
58543 +} gsnpsid_data_t;
58544 +
58545 +/**
58546 + * This union represents the bit fields in the User HW Config1
58547 + * Register. Read the register into the <i>d32</i> element then read
58548 + * out the bits using the <i>b</i>it elements.
58549 + */
58550 +typedef union hwcfg1_data {
58551 + /** raw register data */
58552 + uint32_t d32;
58553 + /** register bits */
58554 + struct {
58555 + unsigned ep_dir0:2;
58556 + unsigned ep_dir1:2;
58557 + unsigned ep_dir2:2;
58558 + unsigned ep_dir3:2;
58559 + unsigned ep_dir4:2;
58560 + unsigned ep_dir5:2;
58561 + unsigned ep_dir6:2;
58562 + unsigned ep_dir7:2;
58563 + unsigned ep_dir8:2;
58564 + unsigned ep_dir9:2;
58565 + unsigned ep_dir10:2;
58566 + unsigned ep_dir11:2;
58567 + unsigned ep_dir12:2;
58568 + unsigned ep_dir13:2;
58569 + unsigned ep_dir14:2;
58570 + unsigned ep_dir15:2;
58571 + } b;
58572 +} hwcfg1_data_t;
58573 +
58574 +/**
58575 + * This union represents the bit fields in the User HW Config2
58576 + * Register. Read the register into the <i>d32</i> element then read
58577 + * out the bits using the <i>b</i>it elements.
58578 + */
58579 +typedef union hwcfg2_data {
58580 + /** raw register data */
58581 + uint32_t d32;
58582 + /** register bits */
58583 + struct {
58584 + /* GHWCFG2 */
58585 + unsigned op_mode:3;
58586 +#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
58587 +#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
58588 +#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
58589 +#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
58590 +#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
58591 +#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
58592 +#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
58593 +
58594 + unsigned architecture:2;
58595 + unsigned point2point:1;
58596 + unsigned hs_phy_type:2;
58597 +#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
58598 +#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
58599 +#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
58600 +#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
58601 +
58602 + unsigned fs_phy_type:2;
58603 + unsigned num_dev_ep:4;
58604 + unsigned num_host_chan:4;
58605 + unsigned perio_ep_supported:1;
58606 + unsigned dynamic_fifo:1;
58607 + unsigned multi_proc_int:1;
58608 + unsigned reserved21:1;
58609 + unsigned nonperio_tx_q_depth:2;
58610 + unsigned host_perio_tx_q_depth:2;
58611 + unsigned dev_token_q_depth:5;
58612 + unsigned otg_enable_ic_usb:1;
58613 + } b;
58614 +} hwcfg2_data_t;
58615 +
58616 +/**
58617 + * This union represents the bit fields in the User HW Config3
58618 + * Register. Read the register into the <i>d32</i> element then read
58619 + * out the bits using the <i>b</i>it elements.
58620 + */
58621 +typedef union hwcfg3_data {
58622 + /** raw register data */
58623 + uint32_t d32;
58624 + /** register bits */
58625 + struct {
58626 + /* GHWCFG3 */
58627 + unsigned xfer_size_cntr_width:4;
58628 + unsigned packet_size_cntr_width:3;
58629 + unsigned otg_func:1;
58630 + unsigned i2c:1;
58631 + unsigned vendor_ctrl_if:1;
58632 + unsigned optional_features:1;
58633 + unsigned synch_reset_type:1;
58634 + unsigned adp_supp:1;
58635 + unsigned otg_enable_hsic:1;
58636 + unsigned bc_support:1;
58637 + unsigned otg_lpm_en:1;
58638 + unsigned dfifo_depth:16;
58639 + } b;
58640 +} hwcfg3_data_t;
58641 +
58642 +/**
58643 + * This union represents the bit fields in the User HW Config4
58644 + * Register. Read the register into the <i>d32</i> element then read
58645 + * out the bits using the <i>b</i>it elements.
58646 + */
58647 +typedef union hwcfg4_data {
58648 + /** raw register data */
58649 + uint32_t d32;
58650 + /** register bits */
58651 + struct {
58652 + unsigned num_dev_perio_in_ep:4;
58653 + unsigned power_optimiz:1;
58654 + unsigned min_ahb_freq:1;
58655 + unsigned hiber:1;
58656 + unsigned xhiber:1;
58657 + unsigned reserved:6;
58658 + unsigned utmi_phy_data_width:2;
58659 + unsigned num_dev_mode_ctrl_ep:4;
58660 + unsigned iddig_filt_en:1;
58661 + unsigned vbus_valid_filt_en:1;
58662 + unsigned a_valid_filt_en:1;
58663 + unsigned b_valid_filt_en:1;
58664 + unsigned session_end_filt_en:1;
58665 + unsigned ded_fifo_en:1;
58666 + unsigned num_in_eps:4;
58667 + unsigned desc_dma:1;
58668 + unsigned desc_dma_dyn:1;
58669 + } b;
58670 +} hwcfg4_data_t;
58671 +
58672 +/**
58673 + * This union represents the bit fields of the Core LPM Configuration
58674 + * Register (GLPMCFG). Set the bits using bit fields then write
58675 + * the <i>d32</i> value to the register.
58676 + */
58677 +typedef union glpmctl_data {
58678 + /** raw register data */
58679 + uint32_t d32;
58680 + /** register bits */
58681 + struct {
58682 + /** LPM-Capable (LPMCap) (Device and Host)
58683 + * The application uses this bit to control
58684 + * the DWC_otg core LPM capabilities.
58685 + */
58686 + unsigned lpm_cap_en:1;
58687 + /** LPM response programmed by application (AppL1Res) (Device)
58688 + * Handshake response to LPM token pre-programmed
58689 + * by device application software.
58690 + */
58691 + unsigned appl_resp:1;
58692 + /** Host Initiated Resume Duration (HIRD) (Device and Host)
58693 + * In Host mode this field indicates the value of HIRD
58694 + * to be sent in an LPM transaction.
58695 + * In Device mode this field is updated with the
58696 + * Received LPM Token HIRD bmAttribute
58697 + * when an ACK/NYET/STALL response is sent
58698 + * to an LPM transaction.
58699 + */
58700 + unsigned hird:4;
58701 + /** RemoteWakeEnable (bRemoteWake) (Device and Host)
58702 + * In Host mode this bit indicates the value of remote
58703 + * wake up to be sent in wIndex field of LPM transaction.
58704 + * In Device mode this field is updated with the
58705 + * Received LPM Token bRemoteWake bmAttribute
58706 + * when an ACK/NYET/STALL response is sent
58707 + * to an LPM transaction.
58708 + */
58709 + unsigned rem_wkup_en:1;
58710 + /** Enable utmi_sleep_n (EnblSlpM) (Device and Host)
58711 + * The application uses this bit to control
58712 + * the utmi_sleep_n assertion to the PHY when in L1 state.
58713 + */
58714 + unsigned en_utmi_sleep:1;
58715 + /** HIRD Threshold (HIRD_Thres) (Device and Host)
58716 + */
58717 + unsigned hird_thres:5;
58718 + /** LPM Response (CoreL1Res) (Device and Host)
58719 + * In Host mode this bit contains handsake response to
58720 + * LPM transaction.
58721 + * In Device mode the response of the core to
58722 + * LPM transaction received is reflected in these two bits.
58723 + - 0x0 : ERROR (No handshake response)
58724 + - 0x1 : STALL
58725 + - 0x2 : NYET
58726 + - 0x3 : ACK
58727 + */
58728 + unsigned lpm_resp:2;
58729 + /** Port Sleep Status (SlpSts) (Device and Host)
58730 + * This bit is set as long as a Sleep condition
58731 + * is present on the USB bus.
58732 + */
58733 + unsigned prt_sleep_sts:1;
58734 + /** Sleep State Resume OK (L1ResumeOK) (Device and Host)
58735 + * Indicates that the application or host
58736 + * can start resume from Sleep state.
58737 + */
58738 + unsigned sleep_state_resumeok:1;
58739 + /** LPM channel Index (LPM_Chnl_Indx) (Host)
58740 + * The channel number on which the LPM transaction
58741 + * has to be applied while sending
58742 + * an LPM transaction to the local device.
58743 + */
58744 + unsigned lpm_chan_index:4;
58745 + /** LPM Retry Count (LPM_Retry_Cnt) (Host)
58746 + * Number host retries that would be performed
58747 + * if the device response was not valid response.
58748 + */
58749 + unsigned retry_count:3;
58750 + /** Send LPM Transaction (SndLPM) (Host)
58751 + * When set by application software,
58752 + * an LPM transaction containing two tokens
58753 + * is sent.
58754 + */
58755 + unsigned send_lpm:1;
58756 + /** LPM Retry status (LPM_RetryCnt_Sts) (Host)
58757 + * Number of LPM Host Retries still remaining
58758 + * to be transmitted for the current LPM sequence
58759 + */
58760 + unsigned retry_count_sts:3;
58761 + unsigned reserved28_29:2;
58762 + /** In host mode once this bit is set, the host
58763 + * configures to drive the HSIC Idle state on the bus.
58764 + * It then waits for the device to initiate the Connect sequence.
58765 + * In device mode once this bit is set, the device waits for
58766 + * the HSIC Idle line state on the bus. Upon receving the Idle
58767 + * line state, it initiates the HSIC Connect sequence.
58768 + */
58769 + unsigned hsic_connect:1;
58770 + /** This bit overrides and functionally inverts
58771 + * the if_select_hsic input port signal.
58772 + */
58773 + unsigned inv_sel_hsic:1;
58774 + } b;
58775 +} glpmcfg_data_t;
58776 +
58777 +/**
58778 + * This union represents the bit fields of the Core ADP Timer, Control and
58779 + * Status Register (ADPTIMCTLSTS). Set the bits using bit fields then write
58780 + * the <i>d32</i> value to the register.
58781 + */
58782 +typedef union adpctl_data {
58783 + /** raw register data */
58784 + uint32_t d32;
58785 + /** register bits */
58786 + struct {
58787 + /** Probe Discharge (PRB_DSCHG)
58788 + * These bits set the times for TADP_DSCHG.
58789 + * These bits are defined as follows:
58790 + * 2'b00 - 4 msec
58791 + * 2'b01 - 8 msec
58792 + * 2'b10 - 16 msec
58793 + * 2'b11 - 32 msec
58794 + */
58795 + unsigned prb_dschg:2;
58796 + /** Probe Delta (PRB_DELTA)
58797 + * These bits set the resolution for RTIM value.
58798 + * The bits are defined in units of 32 kHz clock cycles as follows:
58799 + * 2'b00 - 1 cycles
58800 + * 2'b01 - 2 cycles
58801 + * 2'b10 - 3 cycles
58802 + * 2'b11 - 4 cycles
58803 + * For example if this value is chosen to 2'b01, it means that RTIM
58804 + * increments for every 3(three) 32Khz clock cycles.
58805 + */
58806 + unsigned prb_delta:2;
58807 + /** Probe Period (PRB_PER)
58808 + * These bits sets the TADP_PRD as shown in Figure 4 as follows:
58809 + * 2'b00 - 0.625 to 0.925 sec (typical 0.775 sec)
58810 + * 2'b01 - 1.25 to 1.85 sec (typical 1.55 sec)
58811 + * 2'b10 - 1.9 to 2.6 sec (typical 2.275 sec)
58812 + * 2'b11 - Reserved
58813 + */
58814 + unsigned prb_per:2;
58815 + /** These bits capture the latest time it took for VBUS to ramp from
58816 + * VADP_SINK to VADP_PRB.
58817 + * 0x000 - 1 cycles
58818 + * 0x001 - 2 cycles
58819 + * 0x002 - 3 cycles
58820 + * etc
58821 + * 0x7FF - 2048 cycles
58822 + * A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec.
58823 + */
58824 + unsigned rtim:11;
58825 + /** Enable Probe (EnaPrb)
58826 + * When programmed to 1'b1, the core performs a probe operation.
58827 + * This bit is valid only if OTG_Ver = 1'b1.
58828 + */
58829 + unsigned enaprb:1;
58830 + /** Enable Sense (EnaSns)
58831 + * When programmed to 1'b1, the core performs a Sense operation.
58832 + * This bit is valid only if OTG_Ver = 1'b1.
58833 + */
58834 + unsigned enasns:1;
58835 + /** ADP Reset (ADPRes)
58836 + * When set, ADP controller is reset.
58837 + * This bit is valid only if OTG_Ver = 1'b1.
58838 + */
58839 + unsigned adpres:1;
58840 + /** ADP Enable (ADPEn)
58841 + * When set, the core performs either ADP probing or sensing
58842 + * based on EnaPrb or EnaSns.
58843 + * This bit is valid only if OTG_Ver = 1'b1.
58844 + */
58845 + unsigned adpen:1;
58846 + /** ADP Probe Interrupt (ADP_PRB_INT)
58847 + * When this bit is set, it means that the VBUS
58848 + * voltage is greater than VADP_PRB or VADP_PRB is reached.
58849 + * This bit is valid only if OTG_Ver = 1'b1.
58850 + */
58851 + unsigned adp_prb_int:1;
58852 + /**
58853 + * ADP Sense Interrupt (ADP_SNS_INT)
58854 + * When this bit is set, it means that the VBUS voltage is greater than
58855 + * VADP_SNS value or VADP_SNS is reached.
58856 + * This bit is valid only if OTG_Ver = 1'b1.
58857 + */
58858 + unsigned adp_sns_int:1;
58859 + /** ADP Tomeout Interrupt (ADP_TMOUT_INT)
58860 + * This bit is relevant only for an ADP probe.
58861 + * When this bit is set, it means that the ramp time has
58862 + * completed ie ADPCTL.RTIM has reached its terminal value
58863 + * of 0x7FF. This is a debug feature that allows software
58864 + * to read the ramp time after each cycle.
58865 + * This bit is valid only if OTG_Ver = 1'b1.
58866 + */
58867 + unsigned adp_tmout_int:1;
58868 + /** ADP Probe Interrupt Mask (ADP_PRB_INT_MSK)
58869 + * When this bit is set, it unmasks the interrupt due to ADP_PRB_INT.
58870 + * This bit is valid only if OTG_Ver = 1'b1.
58871 + */
58872 + unsigned adp_prb_int_msk:1;
58873 + /** ADP Sense Interrupt Mask (ADP_SNS_INT_MSK)
58874 + * When this bit is set, it unmasks the interrupt due to ADP_SNS_INT.
58875 + * This bit is valid only if OTG_Ver = 1'b1.
58876 + */
58877 + unsigned adp_sns_int_msk:1;
58878 + /** ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK)
58879 + * When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT.
58880 + * This bit is valid only if OTG_Ver = 1'b1.
58881 + */
58882 + unsigned adp_tmout_int_msk:1;
58883 + /** Access Request
58884 + * 2'b00 - Read/Write Valid (updated by the core)
58885 + * 2'b01 - Read
58886 + * 2'b00 - Write
58887 + * 2'b00 - Reserved
58888 + */
58889 + unsigned ar:2;
58890 + /** Reserved */
58891 + unsigned reserved29_31:3;
58892 + } b;
58893 +} adpctl_data_t;
58894 +
58895 +////////////////////////////////////////////
58896 +// Device Registers
58897 +/**
58898 + * Device Global Registers. <i>Offsets 800h-BFFh</i>
58899 + *
58900 + * The following structures define the size and relative field offsets
58901 + * for the Device Mode Registers.
58902 + *
58903 + * <i>These registers are visible only in Device mode and must not be
58904 + * accessed in Host mode, as the results are unknown.</i>
58905 + */
58906 +typedef struct dwc_otg_dev_global_regs {
58907 + /** Device Configuration Register. <i>Offset 800h</i> */
58908 + volatile uint32_t dcfg;
58909 + /** Device Control Register. <i>Offset: 804h</i> */
58910 + volatile uint32_t dctl;
58911 + /** Device Status Register (Read Only). <i>Offset: 808h</i> */
58912 + volatile uint32_t dsts;
58913 + /** Reserved. <i>Offset: 80Ch</i> */
58914 + uint32_t unused;
58915 + /** Device IN Endpoint Common Interrupt Mask
58916 + * Register. <i>Offset: 810h</i> */
58917 + volatile uint32_t diepmsk;
58918 + /** Device OUT Endpoint Common Interrupt Mask
58919 + * Register. <i>Offset: 814h</i> */
58920 + volatile uint32_t doepmsk;
58921 + /** Device All Endpoints Interrupt Register. <i>Offset: 818h</i> */
58922 + volatile uint32_t daint;
58923 + /** Device All Endpoints Interrupt Mask Register. <i>Offset:
58924 + * 81Ch</i> */
58925 + volatile uint32_t daintmsk;
58926 + /** Device IN Token Queue Read Register-1 (Read Only).
58927 + * <i>Offset: 820h</i> */
58928 + volatile uint32_t dtknqr1;
58929 + /** Device IN Token Queue Read Register-2 (Read Only).
58930 + * <i>Offset: 824h</i> */
58931 + volatile uint32_t dtknqr2;
58932 + /** Device VBUS discharge Register. <i>Offset: 828h</i> */
58933 + volatile uint32_t dvbusdis;
58934 + /** Device VBUS Pulse Register. <i>Offset: 82Ch</i> */
58935 + volatile uint32_t dvbuspulse;
58936 + /** Device IN Token Queue Read Register-3 (Read Only). /
58937 + * Device Thresholding control register (Read/Write)
58938 + * <i>Offset: 830h</i> */
58939 + volatile uint32_t dtknqr3_dthrctl;
58940 + /** Device IN Token Queue Read Register-4 (Read Only). /
58941 + * Device IN EPs empty Inr. Mask Register (Read/Write)
58942 + * <i>Offset: 834h</i> */
58943 + volatile uint32_t dtknqr4_fifoemptymsk;
58944 + /** Device Each Endpoint Interrupt Register (Read Only). /
58945 + * <i>Offset: 838h</i> */
58946 + volatile uint32_t deachint;
58947 + /** Device Each Endpoint Interrupt mask Register (Read/Write). /
58948 + * <i>Offset: 83Ch</i> */
58949 + volatile uint32_t deachintmsk;
58950 + /** Device Each In Endpoint Interrupt mask Register (Read/Write). /
58951 + * <i>Offset: 840h</i> */
58952 + volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS];
58953 + /** Device Each Out Endpoint Interrupt mask Register (Read/Write). /
58954 + * <i>Offset: 880h</i> */
58955 + volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS];
58956 +} dwc_otg_device_global_regs_t;
58957 +
58958 +/**
58959 + * This union represents the bit fields in the Device Configuration
58960 + * Register. Read the register into the <i>d32</i> member then
58961 + * set/clear the bits using the <i>b</i>it elements. Write the
58962 + * <i>d32</i> member to the dcfg register.
58963 + */
58964 +typedef union dcfg_data {
58965 + /** raw register data */
58966 + uint32_t d32;
58967 + /** register bits */
58968 + struct {
58969 + /** Device Speed */
58970 + unsigned devspd:2;
58971 + /** Non Zero Length Status OUT Handshake */
58972 + unsigned nzstsouthshk:1;
58973 +#define DWC_DCFG_SEND_STALL 1
58974 +
58975 + unsigned ena32khzs:1;
58976 + /** Device Addresses */
58977 + unsigned devaddr:7;
58978 + /** Periodic Frame Interval */
58979 + unsigned perfrint:2;
58980 +#define DWC_DCFG_FRAME_INTERVAL_80 0
58981 +#define DWC_DCFG_FRAME_INTERVAL_85 1
58982 +#define DWC_DCFG_FRAME_INTERVAL_90 2
58983 +#define DWC_DCFG_FRAME_INTERVAL_95 3
58984 +
58985 + /** Enable Device OUT NAK for bulk in DDMA mode */
58986 + unsigned endevoutnak:1;
58987 +
58988 + unsigned reserved14_17:4;
58989 + /** In Endpoint Mis-match count */
58990 + unsigned epmscnt:5;
58991 + /** Enable Descriptor DMA in Device mode */
58992 + unsigned descdma:1;
58993 + unsigned perschintvl:2;
58994 + unsigned resvalid:6;
58995 + } b;
58996 +} dcfg_data_t;
58997 +
58998 +/**
58999 + * This union represents the bit fields in the Device Control
59000 + * Register. Read the register into the <i>d32</i> member then
59001 + * set/clear the bits using the <i>b</i>it elements.
59002 + */
59003 +typedef union dctl_data {
59004 + /** raw register data */
59005 + uint32_t d32;
59006 + /** register bits */
59007 + struct {
59008 + /** Remote Wakeup */
59009 + unsigned rmtwkupsig:1;
59010 + /** Soft Disconnect */
59011 + unsigned sftdiscon:1;
59012 + /** Global Non-Periodic IN NAK Status */
59013 + unsigned gnpinnaksts:1;
59014 + /** Global OUT NAK Status */
59015 + unsigned goutnaksts:1;
59016 + /** Test Control */
59017 + unsigned tstctl:3;
59018 + /** Set Global Non-Periodic IN NAK */
59019 + unsigned sgnpinnak:1;
59020 + /** Clear Global Non-Periodic IN NAK */
59021 + unsigned cgnpinnak:1;
59022 + /** Set Global OUT NAK */
59023 + unsigned sgoutnak:1;
59024 + /** Clear Global OUT NAK */
59025 + unsigned cgoutnak:1;
59026 + /** Power-On Programming Done */
59027 + unsigned pwronprgdone:1;
59028 + /** Reserved */
59029 + unsigned reserved:1;
59030 + /** Global Multi Count */
59031 + unsigned gmc:2;
59032 + /** Ignore Frame Number for ISOC EPs */
59033 + unsigned ifrmnum:1;
59034 + /** NAK on Babble */
59035 + unsigned nakonbble:1;
59036 + /** Enable Continue on BNA */
59037 + unsigned encontonbna:1;
59038 +
59039 + unsigned reserved18_31:14;
59040 + } b;
59041 +} dctl_data_t;
59042 +
59043 +/**
59044 + * This union represents the bit fields in the Device Status
59045 + * Register. Read the register into the <i>d32</i> member then
59046 + * set/clear the bits using the <i>b</i>it elements.
59047 + */
59048 +typedef union dsts_data {
59049 + /** raw register data */
59050 + uint32_t d32;
59051 + /** register bits */
59052 + struct {
59053 + /** Suspend Status */
59054 + unsigned suspsts:1;
59055 + /** Enumerated Speed */
59056 + unsigned enumspd:2;
59057 +#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
59058 +#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
59059 +#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2
59060 +#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3
59061 + /** Erratic Error */
59062 + unsigned errticerr:1;
59063 + unsigned reserved4_7:4;
59064 + /** Frame or Microframe Number of the received SOF */
59065 + unsigned soffn:14;
59066 + unsigned reserved22_31:10;
59067 + } b;
59068 +} dsts_data_t;
59069 +
59070 +/**
59071 + * This union represents the bit fields in the Device IN EP Interrupt
59072 + * Register and the Device IN EP Common Mask Register.
59073 + *
59074 + * - Read the register into the <i>d32</i> member then set/clear the
59075 + * bits using the <i>b</i>it elements.
59076 + */
59077 +typedef union diepint_data {
59078 + /** raw register data */
59079 + uint32_t d32;
59080 + /** register bits */
59081 + struct {
59082 + /** Transfer complete mask */
59083 + unsigned xfercompl:1;
59084 + /** Endpoint disable mask */
59085 + unsigned epdisabled:1;
59086 + /** AHB Error mask */
59087 + unsigned ahberr:1;
59088 + /** TimeOUT Handshake mask (non-ISOC EPs) */
59089 + unsigned timeout:1;
59090 + /** IN Token received with TxF Empty mask */
59091 + unsigned intktxfemp:1;
59092 + /** IN Token Received with EP mismatch mask */
59093 + unsigned intknepmis:1;
59094 + /** IN Endpoint NAK Effective mask */
59095 + unsigned inepnakeff:1;
59096 + /** Reserved */
59097 + unsigned emptyintr:1;
59098 +
59099 + unsigned txfifoundrn:1;
59100 +
59101 + /** BNA Interrupt mask */
59102 + unsigned bna:1;
59103 +
59104 + unsigned reserved10_12:3;
59105 + /** BNA Interrupt mask */
59106 + unsigned nak:1;
59107 +
59108 + unsigned reserved14_31:18;
59109 + } b;
59110 +} diepint_data_t;
59111 +
59112 +/**
59113 + * This union represents the bit fields in the Device IN EP
59114 + * Common/Dedicated Interrupt Mask Register.
59115 + */
59116 +typedef union diepint_data diepmsk_data_t;
59117 +
59118 +/**
59119 + * This union represents the bit fields in the Device OUT EP Interrupt
59120 + * Registerand Device OUT EP Common Interrupt Mask Register.
59121 + *
59122 + * - Read the register into the <i>d32</i> member then set/clear the
59123 + * bits using the <i>b</i>it elements.
59124 + */
59125 +typedef union doepint_data {
59126 + /** raw register data */
59127 + uint32_t d32;
59128 + /** register bits */
59129 + struct {
59130 + /** Transfer complete */
59131 + unsigned xfercompl:1;
59132 + /** Endpoint disable */
59133 + unsigned epdisabled:1;
59134 + /** AHB Error */
59135 + unsigned ahberr:1;
59136 + /** Setup Phase Done (contorl EPs) */
59137 + unsigned setup:1;
59138 + /** OUT Token Received when Endpoint Disabled */
59139 + unsigned outtknepdis:1;
59140 +
59141 + unsigned stsphsercvd:1;
59142 + /** Back-to-Back SETUP Packets Received */
59143 + unsigned back2backsetup:1;
59144 +
59145 + unsigned reserved7:1;
59146 + /** OUT packet Error */
59147 + unsigned outpkterr:1;
59148 + /** BNA Interrupt */
59149 + unsigned bna:1;
59150 +
59151 + unsigned reserved10:1;
59152 + /** Packet Drop Status */
59153 + unsigned pktdrpsts:1;
59154 + /** Babble Interrupt */
59155 + unsigned babble:1;
59156 + /** NAK Interrupt */
59157 + unsigned nak:1;
59158 + /** NYET Interrupt */
59159 + unsigned nyet:1;
59160 + /** Bit indicating setup packet received */
59161 + unsigned sr:1;
59162 +
59163 + unsigned reserved16_31:16;
59164 + } b;
59165 +} doepint_data_t;
59166 +
59167 +/**
59168 + * This union represents the bit fields in the Device OUT EP
59169 + * Common/Dedicated Interrupt Mask Register.
59170 + */
59171 +typedef union doepint_data doepmsk_data_t;
59172 +
59173 +/**
59174 + * This union represents the bit fields in the Device All EP Interrupt
59175 + * and Mask Registers.
59176 + * - Read the register into the <i>d32</i> member then set/clear the
59177 + * bits using the <i>b</i>it elements.
59178 + */
59179 +typedef union daint_data {
59180 + /** raw register data */
59181 + uint32_t d32;
59182 + /** register bits */
59183 + struct {
59184 + /** IN Endpoint bits */
59185 + unsigned in:16;
59186 + /** OUT Endpoint bits */
59187 + unsigned out:16;
59188 + } ep;
59189 + struct {
59190 + /** IN Endpoint bits */
59191 + unsigned inep0:1;
59192 + unsigned inep1:1;
59193 + unsigned inep2:1;
59194 + unsigned inep3:1;
59195 + unsigned inep4:1;
59196 + unsigned inep5:1;
59197 + unsigned inep6:1;
59198 + unsigned inep7:1;
59199 + unsigned inep8:1;
59200 + unsigned inep9:1;
59201 + unsigned inep10:1;
59202 + unsigned inep11:1;
59203 + unsigned inep12:1;
59204 + unsigned inep13:1;
59205 + unsigned inep14:1;
59206 + unsigned inep15:1;
59207 + /** OUT Endpoint bits */
59208 + unsigned outep0:1;
59209 + unsigned outep1:1;
59210 + unsigned outep2:1;
59211 + unsigned outep3:1;
59212 + unsigned outep4:1;
59213 + unsigned outep5:1;
59214 + unsigned outep6:1;
59215 + unsigned outep7:1;
59216 + unsigned outep8:1;
59217 + unsigned outep9:1;
59218 + unsigned outep10:1;
59219 + unsigned outep11:1;
59220 + unsigned outep12:1;
59221 + unsigned outep13:1;
59222 + unsigned outep14:1;
59223 + unsigned outep15:1;
59224 + } b;
59225 +} daint_data_t;
59226 +
59227 +/**
59228 + * This union represents the bit fields in the Device IN Token Queue
59229 + * Read Registers.
59230 + * - Read the register into the <i>d32</i> member.
59231 + * - READ-ONLY Register
59232 + */
59233 +typedef union dtknq1_data {
59234 + /** raw register data */
59235 + uint32_t d32;
59236 + /** register bits */
59237 + struct {
59238 + /** In Token Queue Write Pointer */
59239 + unsigned intknwptr:5;
59240 + /** Reserved */
59241 + unsigned reserved05_06:2;
59242 + /** write pointer has wrapped. */
59243 + unsigned wrap_bit:1;
59244 + /** EP Numbers of IN Tokens 0 ... 4 */
59245 + unsigned epnums0_5:24;
59246 + } b;
59247 +} dtknq1_data_t;
59248 +
59249 +/**
59250 + * This union represents Threshold control Register
59251 + * - Read and write the register into the <i>d32</i> member.
59252 + * - READ-WRITABLE Register
59253 + */
59254 +typedef union dthrctl_data {
59255 + /** raw register data */
59256 + uint32_t d32;
59257 + /** register bits */
59258 + struct {
59259 + /** non ISO Tx Thr. Enable */
59260 + unsigned non_iso_thr_en:1;
59261 + /** ISO Tx Thr. Enable */
59262 + unsigned iso_thr_en:1;
59263 + /** Tx Thr. Length */
59264 + unsigned tx_thr_len:9;
59265 + /** AHB Threshold ratio */
59266 + unsigned ahb_thr_ratio:2;
59267 + /** Reserved */
59268 + unsigned reserved13_15:3;
59269 + /** Rx Thr. Enable */
59270 + unsigned rx_thr_en:1;
59271 + /** Rx Thr. Length */
59272 + unsigned rx_thr_len:9;
59273 + unsigned reserved26:1;
59274 + /** Arbiter Parking Enable*/
59275 + unsigned arbprken:1;
59276 + /** Reserved */
59277 + unsigned reserved28_31:4;
59278 + } b;
59279 +} dthrctl_data_t;
59280 +
59281 +/**
59282 + * Device Logical IN Endpoint-Specific Registers. <i>Offsets
59283 + * 900h-AFCh</i>
59284 + *
59285 + * There will be one set of endpoint registers per logical endpoint
59286 + * implemented.
59287 + *
59288 + * <i>These registers are visible only in Device mode and must not be
59289 + * accessed in Host mode, as the results are unknown.</i>
59290 + */
59291 +typedef struct dwc_otg_dev_in_ep_regs {
59292 + /** Device IN Endpoint Control Register. <i>Offset:900h +
59293 + * (ep_num * 20h) + 00h</i> */
59294 + volatile uint32_t diepctl;
59295 + /** Reserved. <i>Offset:900h + (ep_num * 20h) + 04h</i> */
59296 + uint32_t reserved04;
59297 + /** Device IN Endpoint Interrupt Register. <i>Offset:900h +
59298 + * (ep_num * 20h) + 08h</i> */
59299 + volatile uint32_t diepint;
59300 + /** Reserved. <i>Offset:900h + (ep_num * 20h) + 0Ch</i> */
59301 + uint32_t reserved0C;
59302 + /** Device IN Endpoint Transfer Size
59303 + * Register. <i>Offset:900h + (ep_num * 20h) + 10h</i> */
59304 + volatile uint32_t dieptsiz;
59305 + /** Device IN Endpoint DMA Address Register. <i>Offset:900h +
59306 + * (ep_num * 20h) + 14h</i> */
59307 + volatile uint32_t diepdma;
59308 + /** Device IN Endpoint Transmit FIFO Status Register. <i>Offset:900h +
59309 + * (ep_num * 20h) + 18h</i> */
59310 + volatile uint32_t dtxfsts;
59311 + /** Device IN Endpoint DMA Buffer Register. <i>Offset:900h +
59312 + * (ep_num * 20h) + 1Ch</i> */
59313 + volatile uint32_t diepdmab;
59314 +} dwc_otg_dev_in_ep_regs_t;
59315 +
59316 +/**
59317 + * Device Logical OUT Endpoint-Specific Registers. <i>Offsets:
59318 + * B00h-CFCh</i>
59319 + *
59320 + * There will be one set of endpoint registers per logical endpoint
59321 + * implemented.
59322 + *
59323 + * <i>These registers are visible only in Device mode and must not be
59324 + * accessed in Host mode, as the results are unknown.</i>
59325 + */
59326 +typedef struct dwc_otg_dev_out_ep_regs {
59327 + /** Device OUT Endpoint Control Register. <i>Offset:B00h +
59328 + * (ep_num * 20h) + 00h</i> */
59329 + volatile uint32_t doepctl;
59330 + /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 04h</i> */
59331 + uint32_t reserved04;
59332 + /** Device OUT Endpoint Interrupt Register. <i>Offset:B00h +
59333 + * (ep_num * 20h) + 08h</i> */
59334 + volatile uint32_t doepint;
59335 + /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 0Ch</i> */
59336 + uint32_t reserved0C;
59337 + /** Device OUT Endpoint Transfer Size Register. <i>Offset:
59338 + * B00h + (ep_num * 20h) + 10h</i> */
59339 + volatile uint32_t doeptsiz;
59340 + /** Device OUT Endpoint DMA Address Register. <i>Offset:B00h
59341 + * + (ep_num * 20h) + 14h</i> */
59342 + volatile uint32_t doepdma;
59343 + /** Reserved. <i>Offset:B00h + * (ep_num * 20h) + 18h</i> */
59344 + uint32_t unused;
59345 + /** Device OUT Endpoint DMA Buffer Register. <i>Offset:B00h
59346 + * + (ep_num * 20h) + 1Ch</i> */
59347 + uint32_t doepdmab;
59348 +} dwc_otg_dev_out_ep_regs_t;
59349 +
59350 +/**
59351 + * This union represents the bit fields in the Device EP Control
59352 + * Register. Read the register into the <i>d32</i> member then
59353 + * set/clear the bits using the <i>b</i>it elements.
59354 + */
59355 +typedef union depctl_data {
59356 + /** raw register data */
59357 + uint32_t d32;
59358 + /** register bits */
59359 + struct {
59360 + /** Maximum Packet Size
59361 + * IN/OUT EPn
59362 + * IN/OUT EP0 - 2 bits
59363 + * 2'b00: 64 Bytes
59364 + * 2'b01: 32
59365 + * 2'b10: 16
59366 + * 2'b11: 8 */
59367 + unsigned mps:11;
59368 +#define DWC_DEP0CTL_MPS_64 0
59369 +#define DWC_DEP0CTL_MPS_32 1
59370 +#define DWC_DEP0CTL_MPS_16 2
59371 +#define DWC_DEP0CTL_MPS_8 3
59372 +
59373 + /** Next Endpoint
59374 + * IN EPn/IN EP0
59375 + * OUT EPn/OUT EP0 - reserved */
59376 + unsigned nextep:4;
59377 +
59378 + /** USB Active Endpoint */
59379 + unsigned usbactep:1;
59380 +
59381 + /** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
59382 + * This field contains the PID of the packet going to
59383 + * be received or transmitted on this endpoint. The
59384 + * application should program the PID of the first
59385 + * packet going to be received or transmitted on this
59386 + * endpoint , after the endpoint is
59387 + * activated. Application use the SetD1PID and
59388 + * SetD0PID fields of this register to program either
59389 + * D0 or D1 PID.
59390 + *
59391 + * The encoding for this field is
59392 + * - 0: D0
59393 + * - 1: D1
59394 + */
59395 + unsigned dpid:1;
59396 +
59397 + /** NAK Status */
59398 + unsigned naksts:1;
59399 +
59400 + /** Endpoint Type
59401 + * 2'b00: Control
59402 + * 2'b01: Isochronous
59403 + * 2'b10: Bulk
59404 + * 2'b11: Interrupt */
59405 + unsigned eptype:2;
59406 +
59407 + /** Snoop Mode
59408 + * OUT EPn/OUT EP0
59409 + * IN EPn/IN EP0 - reserved */
59410 + unsigned snp:1;
59411 +
59412 + /** Stall Handshake */
59413 + unsigned stall:1;
59414 +
59415 + /** Tx Fifo Number
59416 + * IN EPn/IN EP0
59417 + * OUT EPn/OUT EP0 - reserved */
59418 + unsigned txfnum:4;
59419 +
59420 + /** Clear NAK */
59421 + unsigned cnak:1;
59422 + /** Set NAK */
59423 + unsigned snak:1;
59424 + /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
59425 + * Writing to this field sets the Endpoint DPID (DPID)
59426 + * field in this register to DATA0. Set Even
59427 + * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
59428 + * Writing to this field sets the Even/Odd
59429 + * (micro)frame (EO_FrNum) field to even (micro)
59430 + * frame.
59431 + */
59432 + unsigned setd0pid:1;
59433 + /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
59434 + * Writing to this field sets the Endpoint DPID (DPID)
59435 + * field in this register to DATA1 Set Odd
59436 + * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
59437 + * Writing to this field sets the Even/Odd
59438 + * (micro)frame (EO_FrNum) field to odd (micro) frame.
59439 + */
59440 + unsigned setd1pid:1;
59441 +
59442 + /** Endpoint Disable */
59443 + unsigned epdis:1;
59444 + /** Endpoint Enable */
59445 + unsigned epena:1;
59446 + } b;
59447 +} depctl_data_t;
59448 +
59449 +/**
59450 + * This union represents the bit fields in the Device EP Transfer
59451 + * Size Register. Read the register into the <i>d32</i> member then
59452 + * set/clear the bits using the <i>b</i>it elements.
59453 + */
59454 +typedef union deptsiz_data {
59455 + /** raw register data */
59456 + uint32_t d32;
59457 + /** register bits */
59458 + struct {
59459 + /** Transfer size */
59460 + unsigned xfersize:19;
59461 +/** Max packet count for EP (pow(2,10)-1) */
59462 +#define MAX_PKT_CNT 1023
59463 + /** Packet Count */
59464 + unsigned pktcnt:10;
59465 + /** Multi Count - Periodic IN endpoints */
59466 + unsigned mc:2;
59467 + unsigned reserved:1;
59468 + } b;
59469 +} deptsiz_data_t;
59470 +
59471 +/**
59472 + * This union represents the bit fields in the Device EP 0 Transfer
59473 + * Size Register. Read the register into the <i>d32</i> member then
59474 + * set/clear the bits using the <i>b</i>it elements.
59475 + */
59476 +typedef union deptsiz0_data {
59477 + /** raw register data */
59478 + uint32_t d32;
59479 + /** register bits */
59480 + struct {
59481 + /** Transfer size */
59482 + unsigned xfersize:7;
59483 + /** Reserved */
59484 + unsigned reserved7_18:12;
59485 + /** Packet Count */
59486 + unsigned pktcnt:2;
59487 + /** Reserved */
59488 + unsigned reserved21_28:8;
59489 + /**Setup Packet Count (DOEPTSIZ0 Only) */
59490 + unsigned supcnt:2;
59491 + unsigned reserved31;
59492 + } b;
59493 +} deptsiz0_data_t;
59494 +
59495 +/////////////////////////////////////////////////
59496 +// DMA Descriptor Specific Structures
59497 +//
59498 +
59499 +/** Buffer status definitions */
59500 +
59501 +#define BS_HOST_READY 0x0
59502 +#define BS_DMA_BUSY 0x1
59503 +#define BS_DMA_DONE 0x2
59504 +#define BS_HOST_BUSY 0x3
59505 +
59506 +/** Receive/Transmit status definitions */
59507 +
59508 +#define RTS_SUCCESS 0x0
59509 +#define RTS_BUFFLUSH 0x1
59510 +#define RTS_RESERVED 0x2
59511 +#define RTS_BUFERR 0x3
59512 +
59513 +/**
59514 + * This union represents the bit fields in the DMA Descriptor
59515 + * status quadlet. Read the quadlet into the <i>d32</i> member then
59516 + * set/clear the bits using the <i>b</i>it, <i>b_iso_out</i> and
59517 + * <i>b_iso_in</i> elements.
59518 + */
59519 +typedef union dev_dma_desc_sts {
59520 + /** raw register data */
59521 + uint32_t d32;
59522 + /** quadlet bits */
59523 + struct {
59524 + /** Received number of bytes */
59525 + unsigned bytes:16;
59526 + /** NAK bit - only for OUT EPs */
59527 + unsigned nak:1;
59528 + unsigned reserved17_22:6;
59529 + /** Multiple Transfer - only for OUT EPs */
59530 + unsigned mtrf:1;
59531 + /** Setup Packet received - only for OUT EPs */
59532 + unsigned sr:1;
59533 + /** Interrupt On Complete */
59534 + unsigned ioc:1;
59535 + /** Short Packet */
59536 + unsigned sp:1;
59537 + /** Last */
59538 + unsigned l:1;
59539 + /** Receive Status */
59540 + unsigned sts:2;
59541 + /** Buffer Status */
59542 + unsigned bs:2;
59543 + } b;
59544 +
59545 +//#ifdef DWC_EN_ISOC
59546 + /** iso out quadlet bits */
59547 + struct {
59548 + /** Received number of bytes */
59549 + unsigned rxbytes:11;
59550 +
59551 + unsigned reserved11:1;
59552 + /** Frame Number */
59553 + unsigned framenum:11;
59554 + /** Received ISO Data PID */
59555 + unsigned pid:2;
59556 + /** Interrupt On Complete */
59557 + unsigned ioc:1;
59558 + /** Short Packet */
59559 + unsigned sp:1;
59560 + /** Last */
59561 + unsigned l:1;
59562 + /** Receive Status */
59563 + unsigned rxsts:2;
59564 + /** Buffer Status */
59565 + unsigned bs:2;
59566 + } b_iso_out;
59567 +
59568 + /** iso in quadlet bits */
59569 + struct {
59570 + /** Transmited number of bytes */
59571 + unsigned txbytes:12;
59572 + /** Frame Number */
59573 + unsigned framenum:11;
59574 + /** Transmited ISO Data PID */
59575 + unsigned pid:2;
59576 + /** Interrupt On Complete */
59577 + unsigned ioc:1;
59578 + /** Short Packet */
59579 + unsigned sp:1;
59580 + /** Last */
59581 + unsigned l:1;
59582 + /** Transmit Status */
59583 + unsigned txsts:2;
59584 + /** Buffer Status */
59585 + unsigned bs:2;
59586 + } b_iso_in;
59587 +//#endif /* DWC_EN_ISOC */
59588 +} dev_dma_desc_sts_t;
59589 +
59590 +/**
59591 + * DMA Descriptor structure
59592 + *
59593 + * DMA Descriptor structure contains two quadlets:
59594 + * Status quadlet and Data buffer pointer.
59595 + */
59596 +typedef struct dwc_otg_dev_dma_desc {
59597 + /** DMA Descriptor status quadlet */
59598 + dev_dma_desc_sts_t status;
59599 + /** DMA Descriptor data buffer pointer */
59600 + uint32_t buf;
59601 +} dwc_otg_dev_dma_desc_t;
59602 +
59603 +/**
59604 + * The dwc_otg_dev_if structure contains information needed to manage
59605 + * the DWC_otg controller acting in device mode. It represents the
59606 + * programming view of the device-specific aspects of the controller.
59607 + */
59608 +typedef struct dwc_otg_dev_if {
59609 + /** Pointer to device Global registers.
59610 + * Device Global Registers starting at offset 800h
59611 + */
59612 + dwc_otg_device_global_regs_t *dev_global_regs;
59613 +#define DWC_DEV_GLOBAL_REG_OFFSET 0x800
59614 +
59615 + /**
59616 + * Device Logical IN Endpoint-Specific Registers 900h-AFCh
59617 + */
59618 + dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS];
59619 +#define DWC_DEV_IN_EP_REG_OFFSET 0x900
59620 +#define DWC_EP_REG_OFFSET 0x20
59621 +
59622 + /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */
59623 + dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];
59624 +#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00
59625 +
59626 + /* Device configuration information */
59627 + uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */
59628 + uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */
59629 + uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/
59630 +
59631 + /** Size of periodic FIFOs (Bytes) */
59632 + uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS];
59633 +
59634 + /** Size of Tx FIFOs (Bytes) */
59635 + uint16_t tx_fifo_size[MAX_TX_FIFOS];
59636 +
59637 + /** Thresholding enable flags and length varaiables **/
59638 + uint16_t rx_thr_en;
59639 + uint16_t iso_tx_thr_en;
59640 + uint16_t non_iso_tx_thr_en;
59641 +
59642 + uint16_t rx_thr_length;
59643 + uint16_t tx_thr_length;
59644 +
59645 + /**
59646 + * Pointers to the DMA Descriptors for EP0 Control
59647 + * transfers (virtual and physical)
59648 + */
59649 +
59650 + /** 2 descriptors for SETUP packets */
59651 + dwc_dma_t dma_setup_desc_addr[2];
59652 + dwc_otg_dev_dma_desc_t *setup_desc_addr[2];
59653 +
59654 + /** Pointer to Descriptor with latest SETUP packet */
59655 + dwc_otg_dev_dma_desc_t *psetup;
59656 +
59657 + /** Index of current SETUP handler descriptor */
59658 + uint32_t setup_desc_index;
59659 +
59660 + /** Descriptor for Data In or Status In phases */
59661 + dwc_dma_t dma_in_desc_addr;
59662 + dwc_otg_dev_dma_desc_t *in_desc_addr;
59663 +
59664 + /** Descriptor for Data Out or Status Out phases */
59665 + dwc_dma_t dma_out_desc_addr;
59666 + dwc_otg_dev_dma_desc_t *out_desc_addr;
59667 +
59668 + /** Setup Packet Detected - if set clear NAK when queueing */
59669 + uint32_t spd;
59670 + /** Isoc ep pointer on which incomplete happens */
59671 + void *isoc_ep;
59672 +
59673 +} dwc_otg_dev_if_t;
59674 +
59675 +/////////////////////////////////////////////////
59676 +// Host Mode Register Structures
59677 +//
59678 +/**
59679 + * The Host Global Registers structure defines the size and relative
59680 + * field offsets for the Host Mode Global Registers. Host Global
59681 + * Registers offsets 400h-7FFh.
59682 +*/
59683 +typedef struct dwc_otg_host_global_regs {
59684 + /** Host Configuration Register. <i>Offset: 400h</i> */
59685 + volatile uint32_t hcfg;
59686 + /** Host Frame Interval Register. <i>Offset: 404h</i> */
59687 + volatile uint32_t hfir;
59688 + /** Host Frame Number / Frame Remaining Register. <i>Offset: 408h</i> */
59689 + volatile uint32_t hfnum;
59690 + /** Reserved. <i>Offset: 40Ch</i> */
59691 + uint32_t reserved40C;
59692 + /** Host Periodic Transmit FIFO/ Queue Status Register. <i>Offset: 410h</i> */
59693 + volatile uint32_t hptxsts;
59694 + /** Host All Channels Interrupt Register. <i>Offset: 414h</i> */
59695 + volatile uint32_t haint;
59696 + /** Host All Channels Interrupt Mask Register. <i>Offset: 418h</i> */
59697 + volatile uint32_t haintmsk;
59698 + /** Host Frame List Base Address Register . <i>Offset: 41Ch</i> */
59699 + volatile uint32_t hflbaddr;
59700 +} dwc_otg_host_global_regs_t;
59701 +
59702 +/**
59703 + * This union represents the bit fields in the Host Configuration Register.
59704 + * Read the register into the <i>d32</i> member then set/clear the bits using
59705 + * the <i>b</i>it elements. Write the <i>d32</i> member to the hcfg register.
59706 + */
59707 +typedef union hcfg_data {
59708 + /** raw register data */
59709 + uint32_t d32;
59710 +
59711 + /** register bits */
59712 + struct {
59713 + /** FS/LS Phy Clock Select */
59714 + unsigned fslspclksel:2;
59715 +#define DWC_HCFG_30_60_MHZ 0
59716 +#define DWC_HCFG_48_MHZ 1
59717 +#define DWC_HCFG_6_MHZ 2
59718 +
59719 + /** FS/LS Only Support */
59720 + unsigned fslssupp:1;
59721 + unsigned reserved3_6:4;
59722 + /** Enable 32-KHz Suspend Mode */
59723 + unsigned ena32khzs:1;
59724 + /** Resume Validation Periiod */
59725 + unsigned resvalid:8;
59726 + unsigned reserved16_22:7;
59727 + /** Enable Scatter/gather DMA in Host mode */
59728 + unsigned descdma:1;
59729 + /** Frame List Entries */
59730 + unsigned frlisten:2;
59731 + /** Enable Periodic Scheduling */
59732 + unsigned perschedena:1;
59733 + unsigned reserved27_30:4;
59734 + unsigned modechtimen:1;
59735 + } b;
59736 +} hcfg_data_t;
59737 +
59738 +/**
59739 + * This union represents the bit fields in the Host Frame Remaing/Number
59740 + * Register.
59741 + */
59742 +typedef union hfir_data {
59743 + /** raw register data */
59744 + uint32_t d32;
59745 +
59746 + /** register bits */
59747 + struct {
59748 + unsigned frint:16;
59749 + unsigned hfirrldctrl:1;
59750 + unsigned reserved:15;
59751 + } b;
59752 +} hfir_data_t;
59753 +
59754 +/**
59755 + * This union represents the bit fields in the Host Frame Remaing/Number
59756 + * Register.
59757 + */
59758 +typedef union hfnum_data {
59759 + /** raw register data */
59760 + uint32_t d32;
59761 +
59762 + /** register bits */
59763 + struct {
59764 + unsigned frnum:16;
59765 +#define DWC_HFNUM_MAX_FRNUM 0x3FFF
59766 + unsigned frrem:16;
59767 + } b;
59768 +} hfnum_data_t;
59769 +
59770 +typedef union hptxsts_data {
59771 + /** raw register data */
59772 + uint32_t d32;
59773 +
59774 + /** register bits */
59775 + struct {
59776 + unsigned ptxfspcavail:16;
59777 + unsigned ptxqspcavail:8;
59778 + /** Top of the Periodic Transmit Request Queue
59779 + * - bit 24 - Terminate (last entry for the selected channel)
59780 + * - bits 26:25 - Token Type
59781 + * - 2'b00 - Zero length
59782 + * - 2'b01 - Ping
59783 + * - 2'b10 - Disable
59784 + * - bits 30:27 - Channel Number
59785 + * - bit 31 - Odd/even microframe
59786 + */
59787 + unsigned ptxqtop_terminate:1;
59788 + unsigned ptxqtop_token:2;
59789 + unsigned ptxqtop_chnum:4;
59790 + unsigned ptxqtop_odd:1;
59791 + } b;
59792 +} hptxsts_data_t;
59793 +
59794 +/**
59795 + * This union represents the bit fields in the Host Port Control and Status
59796 + * Register. Read the register into the <i>d32</i> member then set/clear the
59797 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
59798 + * hprt0 register.
59799 + */
59800 +typedef union hprt0_data {
59801 + /** raw register data */
59802 + uint32_t d32;
59803 + /** register bits */
59804 + struct {
59805 + unsigned prtconnsts:1;
59806 + unsigned prtconndet:1;
59807 + unsigned prtena:1;
59808 + unsigned prtenchng:1;
59809 + unsigned prtovrcurract:1;
59810 + unsigned prtovrcurrchng:1;
59811 + unsigned prtres:1;
59812 + unsigned prtsusp:1;
59813 + unsigned prtrst:1;
59814 + unsigned reserved9:1;
59815 + unsigned prtlnsts:2;
59816 + unsigned prtpwr:1;
59817 + unsigned prttstctl:4;
59818 + unsigned prtspd:2;
59819 +#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0
59820 +#define DWC_HPRT0_PRTSPD_FULL_SPEED 1
59821 +#define DWC_HPRT0_PRTSPD_LOW_SPEED 2
59822 + unsigned reserved19_31:13;
59823 + } b;
59824 +} hprt0_data_t;
59825 +
59826 +/**
59827 + * This union represents the bit fields in the Host All Interrupt
59828 + * Register.
59829 + */
59830 +typedef union haint_data {
59831 + /** raw register data */
59832 + uint32_t d32;
59833 + /** register bits */
59834 + struct {
59835 + unsigned ch0:1;
59836 + unsigned ch1:1;
59837 + unsigned ch2:1;
59838 + unsigned ch3:1;
59839 + unsigned ch4:1;
59840 + unsigned ch5:1;
59841 + unsigned ch6:1;
59842 + unsigned ch7:1;
59843 + unsigned ch8:1;
59844 + unsigned ch9:1;
59845 + unsigned ch10:1;
59846 + unsigned ch11:1;
59847 + unsigned ch12:1;
59848 + unsigned ch13:1;
59849 + unsigned ch14:1;
59850 + unsigned ch15:1;
59851 + unsigned reserved:16;
59852 + } b;
59853 +
59854 + struct {
59855 + unsigned chint:16;
59856 + unsigned reserved:16;
59857 + } b2;
59858 +} haint_data_t;
59859 +
59860 +/**
59861 + * This union represents the bit fields in the Host All Interrupt
59862 + * Register.
59863 + */
59864 +typedef union haintmsk_data {
59865 + /** raw register data */
59866 + uint32_t d32;
59867 + /** register bits */
59868 + struct {
59869 + unsigned ch0:1;
59870 + unsigned ch1:1;
59871 + unsigned ch2:1;
59872 + unsigned ch3:1;
59873 + unsigned ch4:1;
59874 + unsigned ch5:1;
59875 + unsigned ch6:1;
59876 + unsigned ch7:1;
59877 + unsigned ch8:1;
59878 + unsigned ch9:1;
59879 + unsigned ch10:1;
59880 + unsigned ch11:1;
59881 + unsigned ch12:1;
59882 + unsigned ch13:1;
59883 + unsigned ch14:1;
59884 + unsigned ch15:1;
59885 + unsigned reserved:16;
59886 + } b;
59887 +
59888 + struct {
59889 + unsigned chint:16;
59890 + unsigned reserved:16;
59891 + } b2;
59892 +} haintmsk_data_t;
59893 +
59894 +/**
59895 + * Host Channel Specific Registers. <i>500h-5FCh</i>
59896 + */
59897 +typedef struct dwc_otg_hc_regs {
59898 + /** Host Channel 0 Characteristic Register. <i>Offset: 500h + (chan_num * 20h) + 00h</i> */
59899 + volatile uint32_t hcchar;
59900 + /** Host Channel 0 Split Control Register. <i>Offset: 500h + (chan_num * 20h) + 04h</i> */
59901 + volatile uint32_t hcsplt;
59902 + /** Host Channel 0 Interrupt Register. <i>Offset: 500h + (chan_num * 20h) + 08h</i> */
59903 + volatile uint32_t hcint;
59904 + /** Host Channel 0 Interrupt Mask Register. <i>Offset: 500h + (chan_num * 20h) + 0Ch</i> */
59905 + volatile uint32_t hcintmsk;
59906 + /** Host Channel 0 Transfer Size Register. <i>Offset: 500h + (chan_num * 20h) + 10h</i> */
59907 + volatile uint32_t hctsiz;
59908 + /** Host Channel 0 DMA Address Register. <i>Offset: 500h + (chan_num * 20h) + 14h</i> */
59909 + volatile uint32_t hcdma;
59910 + volatile uint32_t reserved;
59911 + /** Host Channel 0 DMA Buffer Address Register. <i>Offset: 500h + (chan_num * 20h) + 1Ch</i> */
59912 + volatile uint32_t hcdmab;
59913 +} dwc_otg_hc_regs_t;
59914 +
59915 +/**
59916 + * This union represents the bit fields in the Host Channel Characteristics
59917 + * Register. Read the register into the <i>d32</i> member then set/clear the
59918 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
59919 + * hcchar register.
59920 + */
59921 +typedef union hcchar_data {
59922 + /** raw register data */
59923 + uint32_t d32;
59924 +
59925 + /** register bits */
59926 + struct {
59927 + /** Maximum packet size in bytes */
59928 + unsigned mps:11;
59929 +
59930 + /** Endpoint number */
59931 + unsigned epnum:4;
59932 +
59933 + /** 0: OUT, 1: IN */
59934 + unsigned epdir:1;
59935 +
59936 + unsigned reserved:1;
59937 +
59938 + /** 0: Full/high speed device, 1: Low speed device */
59939 + unsigned lspddev:1;
59940 +
59941 + /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */
59942 + unsigned eptype:2;
59943 +
59944 + /** Packets per frame for periodic transfers. 0 is reserved. */
59945 + unsigned multicnt:2;
59946 +
59947 + /** Device address */
59948 + unsigned devaddr:7;
59949 +
59950 + /**
59951 + * Frame to transmit periodic transaction.
59952 + * 0: even, 1: odd
59953 + */
59954 + unsigned oddfrm:1;
59955 +
59956 + /** Channel disable */
59957 + unsigned chdis:1;
59958 +
59959 + /** Channel enable */
59960 + unsigned chen:1;
59961 + } b;
59962 +} hcchar_data_t;
59963 +
59964 +typedef union hcsplt_data {
59965 + /** raw register data */
59966 + uint32_t d32;
59967 +
59968 + /** register bits */
59969 + struct {
59970 + /** Port Address */
59971 + unsigned prtaddr:7;
59972 +
59973 + /** Hub Address */
59974 + unsigned hubaddr:7;
59975 +
59976 + /** Transaction Position */
59977 + unsigned xactpos:2;
59978 +#define DWC_HCSPLIT_XACTPOS_MID 0
59979 +#define DWC_HCSPLIT_XACTPOS_END 1
59980 +#define DWC_HCSPLIT_XACTPOS_BEGIN 2
59981 +#define DWC_HCSPLIT_XACTPOS_ALL 3
59982 +
59983 + /** Do Complete Split */
59984 + unsigned compsplt:1;
59985 +
59986 + /** Reserved */
59987 + unsigned reserved:14;
59988 +
59989 + /** Split Enble */
59990 + unsigned spltena:1;
59991 + } b;
59992 +} hcsplt_data_t;
59993 +
59994 +/**
59995 + * This union represents the bit fields in the Host All Interrupt
59996 + * Register.
59997 + */
59998 +typedef union hcint_data {
59999 + /** raw register data */
60000 + uint32_t d32;
60001 + /** register bits */
60002 + struct {
60003 + /** Transfer Complete */
60004 + unsigned xfercomp:1;
60005 + /** Channel Halted */
60006 + unsigned chhltd:1;
60007 + /** AHB Error */
60008 + unsigned ahberr:1;
60009 + /** STALL Response Received */
60010 + unsigned stall:1;
60011 + /** NAK Response Received */
60012 + unsigned nak:1;
60013 + /** ACK Response Received */
60014 + unsigned ack:1;
60015 + /** NYET Response Received */
60016 + unsigned nyet:1;
60017 + /** Transaction Err */
60018 + unsigned xacterr:1;
60019 + /** Babble Error */
60020 + unsigned bblerr:1;
60021 + /** Frame Overrun */
60022 + unsigned frmovrun:1;
60023 + /** Data Toggle Error */
60024 + unsigned datatglerr:1;
60025 + /** Buffer Not Available (only for DDMA mode) */
60026 + unsigned bna:1;
60027 + /** Exessive transaction error (only for DDMA mode) */
60028 + unsigned xcs_xact:1;
60029 + /** Frame List Rollover interrupt */
60030 + unsigned frm_list_roll:1;
60031 + /** Reserved */
60032 + unsigned reserved14_31:18;
60033 + } b;
60034 +} hcint_data_t;
60035 +
60036 +/**
60037 + * This union represents the bit fields in the Host Channel Interrupt Mask
60038 + * Register. Read the register into the <i>d32</i> member then set/clear the
60039 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
60040 + * hcintmsk register.
60041 + */
60042 +typedef union hcintmsk_data {
60043 + /** raw register data */
60044 + uint32_t d32;
60045 +
60046 + /** register bits */
60047 + struct {
60048 + unsigned xfercompl:1;
60049 + unsigned chhltd:1;
60050 + unsigned ahberr:1;
60051 + unsigned stall:1;
60052 + unsigned nak:1;
60053 + unsigned ack:1;
60054 + unsigned nyet:1;
60055 + unsigned xacterr:1;
60056 + unsigned bblerr:1;
60057 + unsigned frmovrun:1;
60058 + unsigned datatglerr:1;
60059 + unsigned bna:1;
60060 + unsigned xcs_xact:1;
60061 + unsigned frm_list_roll:1;
60062 + unsigned reserved14_31:18;
60063 + } b;
60064 +} hcintmsk_data_t;
60065 +
60066 +/**
60067 + * This union represents the bit fields in the Host Channel Transfer Size
60068 + * Register. Read the register into the <i>d32</i> member then set/clear the
60069 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
60070 + * hcchar register.
60071 + */
60072 +
60073 +typedef union hctsiz_data {
60074 + /** raw register data */
60075 + uint32_t d32;
60076 +
60077 + /** register bits */
60078 + struct {
60079 + /** Total transfer size in bytes */
60080 + unsigned xfersize:19;
60081 +
60082 + /** Data packets to transfer */
60083 + unsigned pktcnt:10;
60084 +
60085 + /**
60086 + * Packet ID for next data packet
60087 + * 0: DATA0
60088 + * 1: DATA2
60089 + * 2: DATA1
60090 + * 3: MDATA (non-Control), SETUP (Control)
60091 + */
60092 + unsigned pid:2;
60093 +#define DWC_HCTSIZ_DATA0 0
60094 +#define DWC_HCTSIZ_DATA1 2
60095 +#define DWC_HCTSIZ_DATA2 1
60096 +#define DWC_HCTSIZ_MDATA 3
60097 +#define DWC_HCTSIZ_SETUP 3
60098 +
60099 + /** Do PING protocol when 1 */
60100 + unsigned dopng:1;
60101 + } b;
60102 +
60103 + /** register bits */
60104 + struct {
60105 + /** Scheduling information */
60106 + unsigned schinfo:8;
60107 +
60108 + /** Number of transfer descriptors.
60109 + * Max value:
60110 + * 64 in general,
60111 + * 256 only for HS isochronous endpoint.
60112 + */
60113 + unsigned ntd:8;
60114 +
60115 + /** Data packets to transfer */
60116 + unsigned reserved16_28:13;
60117 +
60118 + /**
60119 + * Packet ID for next data packet
60120 + * 0: DATA0
60121 + * 1: DATA2
60122 + * 2: DATA1
60123 + * 3: MDATA (non-Control)
60124 + */
60125 + unsigned pid:2;
60126 +
60127 + /** Do PING protocol when 1 */
60128 + unsigned dopng:1;
60129 + } b_ddma;
60130 +} hctsiz_data_t;
60131 +
60132 +/**
60133 + * This union represents the bit fields in the Host DMA Address
60134 + * Register used in Descriptor DMA mode.
60135 + */
60136 +typedef union hcdma_data {
60137 + /** raw register data */
60138 + uint32_t d32;
60139 + /** register bits */
60140 + struct {
60141 + unsigned reserved0_2:3;
60142 + /** Current Transfer Descriptor. Not used for ISOC */
60143 + unsigned ctd:8;
60144 + /** Start Address of Descriptor List */
60145 + unsigned dma_addr:21;
60146 + } b;
60147 +} hcdma_data_t;
60148 +
60149 +/**
60150 + * This union represents the bit fields in the DMA Descriptor
60151 + * status quadlet for host mode. Read the quadlet into the <i>d32</i> member then
60152 + * set/clear the bits using the <i>b</i>it elements.
60153 + */
60154 +typedef union host_dma_desc_sts {
60155 + /** raw register data */
60156 + uint32_t d32;
60157 + /** quadlet bits */
60158 +
60159 + /* for non-isochronous */
60160 + struct {
60161 + /** Number of bytes */
60162 + unsigned n_bytes:17;
60163 + /** QTD offset to jump when Short Packet received - only for IN EPs */
60164 + unsigned qtd_offset:6;
60165 + /**
60166 + * Set to request the core to jump to alternate QTD if
60167 + * Short Packet received - only for IN EPs
60168 + */
60169 + unsigned a_qtd:1;
60170 + /**
60171 + * Setup Packet bit. When set indicates that buffer contains
60172 + * setup packet.
60173 + */
60174 + unsigned sup:1;
60175 + /** Interrupt On Complete */
60176 + unsigned ioc:1;
60177 + /** End of List */
60178 + unsigned eol:1;
60179 + unsigned reserved27:1;
60180 + /** Rx/Tx Status */
60181 + unsigned sts:2;
60182 +#define DMA_DESC_STS_PKTERR 1
60183 + unsigned reserved30:1;
60184 + /** Active Bit */
60185 + unsigned a:1;
60186 + } b;
60187 + /* for isochronous */
60188 + struct {
60189 + /** Number of bytes */
60190 + unsigned n_bytes:12;
60191 + unsigned reserved12_24:13;
60192 + /** Interrupt On Complete */
60193 + unsigned ioc:1;
60194 + unsigned reserved26_27:2;
60195 + /** Rx/Tx Status */
60196 + unsigned sts:2;
60197 + unsigned reserved30:1;
60198 + /** Active Bit */
60199 + unsigned a:1;
60200 + } b_isoc;
60201 +} host_dma_desc_sts_t;
60202 +
60203 +#define MAX_DMA_DESC_SIZE 131071
60204 +#define MAX_DMA_DESC_NUM_GENERIC 64
60205 +#define MAX_DMA_DESC_NUM_HS_ISOC 256
60206 +#define MAX_FRLIST_EN_NUM 64
60207 +/**
60208 + * Host-mode DMA Descriptor structure
60209 + *
60210 + * DMA Descriptor structure contains two quadlets:
60211 + * Status quadlet and Data buffer pointer.
60212 + */
60213 +typedef struct dwc_otg_host_dma_desc {
60214 + /** DMA Descriptor status quadlet */
60215 + host_dma_desc_sts_t status;
60216 + /** DMA Descriptor data buffer pointer */
60217 + uint32_t buf;
60218 +} dwc_otg_host_dma_desc_t;
60219 +
60220 +/** OTG Host Interface Structure.
60221 + *
60222 + * The OTG Host Interface Structure structure contains information
60223 + * needed to manage the DWC_otg controller acting in host mode. It
60224 + * represents the programming view of the host-specific aspects of the
60225 + * controller.
60226 + */
60227 +typedef struct dwc_otg_host_if {
60228 + /** Host Global Registers starting at offset 400h.*/
60229 + dwc_otg_host_global_regs_t *host_global_regs;
60230 +#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400
60231 +
60232 + /** Host Port 0 Control and Status Register */
60233 + volatile uint32_t *hprt0;
60234 +#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440
60235 +
60236 + /** Host Channel Specific Registers at offsets 500h-5FCh. */
60237 + dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS];
60238 +#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500
60239 +#define DWC_OTG_CHAN_REGS_OFFSET 0x20
60240 +
60241 + /* Host configuration information */
60242 + /** Number of Host Channels (range: 1-16) */
60243 + uint8_t num_host_channels;
60244 + /** Periodic EPs supported (0: no, 1: yes) */
60245 + uint8_t perio_eps_supported;
60246 + /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */
60247 + uint16_t perio_tx_fifo_size;
60248 +
60249 +} dwc_otg_host_if_t;
60250 +
60251 +/**
60252 + * This union represents the bit fields in the Power and Clock Gating Control
60253 + * Register. Read the register into the <i>d32</i> member then set/clear the
60254 + * bits using the <i>b</i>it elements.
60255 + */
60256 +typedef union pcgcctl_data {
60257 + /** raw register data */
60258 + uint32_t d32;
60259 +
60260 + /** register bits */
60261 + struct {
60262 + /** Stop Pclk */
60263 + unsigned stoppclk:1;
60264 + /** Gate Hclk */
60265 + unsigned gatehclk:1;
60266 + /** Power Clamp */
60267 + unsigned pwrclmp:1;
60268 + /** Reset Power Down Modules */
60269 + unsigned rstpdwnmodule:1;
60270 + /** Reserved */
60271 + unsigned reserved:1;
60272 + /** Enable Sleep Clock Gating (Enbl_L1Gating) */
60273 + unsigned enbl_sleep_gating:1;
60274 + /** PHY In Sleep (PhySleep) */
60275 + unsigned phy_in_sleep:1;
60276 + /** Deep Sleep*/
60277 + unsigned deep_sleep:1;
60278 + unsigned resetaftsusp:1;
60279 + unsigned restoremode:1;
60280 + unsigned enbl_extnd_hiber:1;
60281 + unsigned extnd_hiber_pwrclmp:1;
60282 + unsigned extnd_hiber_switch:1;
60283 + unsigned ess_reg_restored:1;
60284 + unsigned prt_clk_sel:2;
60285 + unsigned port_power:1;
60286 + unsigned max_xcvrselect:2;
60287 + unsigned max_termsel:1;
60288 + unsigned mac_dev_addr:7;
60289 + unsigned p2hd_dev_enum_spd:2;
60290 + unsigned p2hd_prt_spd:2;
60291 + unsigned if_dev_mode:1;
60292 + } b;
60293 +} pcgcctl_data_t;
60294 +
60295 +/**
60296 + * This union represents the bit fields in the Global Data FIFO Software
60297 + * Configuration Register. Read the register into the <i>d32</i> member then
60298 + * set/clear the bits using the <i>b</i>it elements.
60299 + */
60300 +typedef union gdfifocfg_data {
60301 + /* raw register data */
60302 + uint32_t d32;
60303 + /** register bits */
60304 + struct {
60305 + /** OTG Data FIFO depth */
60306 + unsigned gdfifocfg:16;
60307 + /** Start address of EP info controller */
60308 + unsigned epinfobase:16;
60309 + } b;
60310 +} gdfifocfg_data_t;
60311 +
60312 +/**
60313 + * This union represents the bit fields in the Global Power Down Register
60314 + * Register. Read the register into the <i>d32</i> member then set/clear the
60315 + * bits using the <i>b</i>it elements.
60316 + */
60317 +typedef union gpwrdn_data {
60318 + /* raw register data */
60319 + uint32_t d32;
60320 +
60321 + /** register bits */
60322 + struct {
60323 + /** PMU Interrupt Select */
60324 + unsigned pmuintsel:1;
60325 + /** PMU Active */
60326 + unsigned pmuactv:1;
60327 + /** Restore */
60328 + unsigned restore:1;
60329 + /** Power Down Clamp */
60330 + unsigned pwrdnclmp:1;
60331 + /** Power Down Reset */
60332 + unsigned pwrdnrstn:1;
60333 + /** Power Down Switch */
60334 + unsigned pwrdnswtch:1;
60335 + /** Disable VBUS */
60336 + unsigned dis_vbus:1;
60337 + /** Line State Change */
60338 + unsigned lnstschng:1;
60339 + /** Line state change mask */
60340 + unsigned lnstchng_msk:1;
60341 + /** Reset Detected */
60342 + unsigned rst_det:1;
60343 + /** Reset Detect mask */
60344 + unsigned rst_det_msk:1;
60345 + /** Disconnect Detected */
60346 + unsigned disconn_det:1;
60347 + /** Disconnect Detect mask */
60348 + unsigned disconn_det_msk:1;
60349 + /** Connect Detected*/
60350 + unsigned connect_det:1;
60351 + /** Connect Detected Mask*/
60352 + unsigned connect_det_msk:1;
60353 + /** SRP Detected */
60354 + unsigned srp_det:1;
60355 + /** SRP Detect mask */
60356 + unsigned srp_det_msk:1;
60357 + /** Status Change Interrupt */
60358 + unsigned sts_chngint:1;
60359 + /** Status Change Interrupt Mask */
60360 + unsigned sts_chngint_msk:1;
60361 + /** Line State */
60362 + unsigned linestate:2;
60363 + /** Indicates current mode(status of IDDIG signal) */
60364 + unsigned idsts:1;
60365 + /** B Session Valid signal status*/
60366 + unsigned bsessvld:1;
60367 + /** ADP Event Detected */
60368 + unsigned adp_int:1;
60369 + /** Multi Valued ID pin */
60370 + unsigned mult_val_id_bc:5;
60371 + /** Reserved 24_31 */
60372 + unsigned reserved29_31:3;
60373 + } b;
60374 +} gpwrdn_data_t;
60375 +
60376 +#endif
60377 --- /dev/null
60378 +++ b/drivers/usb/host/dwc_otg/test/Makefile
60379 @@ -0,0 +1,16 @@
60380 +
60381 +PERL=/usr/bin/perl
60382 +PL_TESTS=test_sysfs.pl test_mod_param.pl
60383 +
60384 +.PHONY : test
60385 +test : perl_tests
60386 +
60387 +perl_tests :
60388 + @echo
60389 + @echo Running perl tests
60390 + @for test in $(PL_TESTS); do \
60391 + if $(PERL) ./$$test ; then \
60392 + echo "=======> $$test, PASSED" ; \
60393 + else echo "=======> $$test, FAILED" ; \
60394 + fi \
60395 + done
60396 --- /dev/null
60397 +++ b/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm
60398 @@ -0,0 +1,337 @@
60399 +package dwc_otg_test;
60400 +
60401 +use strict;
60402 +use Exporter ();
60403 +
60404 +use vars qw(@ISA @EXPORT
60405 +$sysfsdir $paramdir $errors $params
60406 +);
60407 +
60408 +@ISA = qw(Exporter);
60409 +
60410 +#
60411 +# Globals
60412 +#
60413 +$sysfsdir = "/sys/devices/lm0";
60414 +$paramdir = "/sys/module/dwc_otg";
60415 +$errors = 0;
60416 +
60417 +$params = [
60418 + {
60419 + NAME => "otg_cap",
60420 + DEFAULT => 0,
60421 + ENUM => [],
60422 + LOW => 0,
60423 + HIGH => 2
60424 + },
60425 + {
60426 + NAME => "dma_enable",
60427 + DEFAULT => 0,
60428 + ENUM => [],
60429 + LOW => 0,
60430 + HIGH => 1
60431 + },
60432 + {
60433 + NAME => "dma_burst_size",
60434 + DEFAULT => 32,
60435 + ENUM => [1, 4, 8, 16, 32, 64, 128, 256],
60436 + LOW => 1,
60437 + HIGH => 256
60438 + },
60439 + {
60440 + NAME => "host_speed",
60441 + DEFAULT => 0,
60442 + ENUM => [],
60443 + LOW => 0,
60444 + HIGH => 1
60445 + },
60446 + {
60447 + NAME => "host_support_fs_ls_low_power",
60448 + DEFAULT => 0,
60449 + ENUM => [],
60450 + LOW => 0,
60451 + HIGH => 1
60452 + },
60453 + {
60454 + NAME => "host_ls_low_power_phy_clk",
60455 + DEFAULT => 0,
60456 + ENUM => [],
60457 + LOW => 0,
60458 + HIGH => 1
60459 + },
60460 + {
60461 + NAME => "dev_speed",
60462 + DEFAULT => 0,
60463 + ENUM => [],
60464 + LOW => 0,
60465 + HIGH => 1
60466 + },
60467 + {
60468 + NAME => "enable_dynamic_fifo",
60469 + DEFAULT => 1,
60470 + ENUM => [],
60471 + LOW => 0,
60472 + HIGH => 1
60473 + },
60474 + {
60475 + NAME => "data_fifo_size",
60476 + DEFAULT => 8192,
60477 + ENUM => [],
60478 + LOW => 32,
60479 + HIGH => 32768
60480 + },
60481 + {
60482 + NAME => "dev_rx_fifo_size",
60483 + DEFAULT => 1064,
60484 + ENUM => [],
60485 + LOW => 16,
60486 + HIGH => 32768
60487 + },
60488 + {
60489 + NAME => "dev_nperio_tx_fifo_size",
60490 + DEFAULT => 1024,
60491 + ENUM => [],
60492 + LOW => 16,
60493 + HIGH => 32768
60494 + },
60495 + {
60496 + NAME => "dev_perio_tx_fifo_size_1",
60497 + DEFAULT => 256,
60498 + ENUM => [],
60499 + LOW => 4,
60500 + HIGH => 768
60501 + },
60502 + {
60503 + NAME => "dev_perio_tx_fifo_size_2",
60504 + DEFAULT => 256,
60505 + ENUM => [],
60506 + LOW => 4,
60507 + HIGH => 768
60508 + },
60509 + {
60510 + NAME => "dev_perio_tx_fifo_size_3",
60511 + DEFAULT => 256,
60512 + ENUM => [],
60513 + LOW => 4,
60514 + HIGH => 768
60515 + },
60516 + {
60517 + NAME => "dev_perio_tx_fifo_size_4",
60518 + DEFAULT => 256,
60519 + ENUM => [],
60520 + LOW => 4,
60521 + HIGH => 768
60522 + },
60523 + {
60524 + NAME => "dev_perio_tx_fifo_size_5",
60525 + DEFAULT => 256,
60526 + ENUM => [],
60527 + LOW => 4,
60528 + HIGH => 768
60529 + },
60530 + {
60531 + NAME => "dev_perio_tx_fifo_size_6",
60532 + DEFAULT => 256,
60533 + ENUM => [],
60534 + LOW => 4,
60535 + HIGH => 768
60536 + },
60537 + {
60538 + NAME => "dev_perio_tx_fifo_size_7",
60539 + DEFAULT => 256,
60540 + ENUM => [],
60541 + LOW => 4,
60542 + HIGH => 768
60543 + },
60544 + {
60545 + NAME => "dev_perio_tx_fifo_size_8",
60546 + DEFAULT => 256,
60547 + ENUM => [],
60548 + LOW => 4,
60549 + HIGH => 768
60550 + },
60551 + {
60552 + NAME => "dev_perio_tx_fifo_size_9",
60553 + DEFAULT => 256,
60554 + ENUM => [],
60555 + LOW => 4,
60556 + HIGH => 768
60557 + },
60558 + {
60559 + NAME => "dev_perio_tx_fifo_size_10",
60560 + DEFAULT => 256,
60561 + ENUM => [],
60562 + LOW => 4,
60563 + HIGH => 768
60564 + },
60565 + {
60566 + NAME => "dev_perio_tx_fifo_size_11",
60567 + DEFAULT => 256,
60568 + ENUM => [],
60569 + LOW => 4,
60570 + HIGH => 768
60571 + },
60572 + {
60573 + NAME => "dev_perio_tx_fifo_size_12",
60574 + DEFAULT => 256,
60575 + ENUM => [],
60576 + LOW => 4,
60577 + HIGH => 768
60578 + },
60579 + {
60580 + NAME => "dev_perio_tx_fifo_size_13",
60581 + DEFAULT => 256,
60582 + ENUM => [],
60583 + LOW => 4,
60584 + HIGH => 768
60585 + },
60586 + {
60587 + NAME => "dev_perio_tx_fifo_size_14",
60588 + DEFAULT => 256,
60589 + ENUM => [],
60590 + LOW => 4,
60591 + HIGH => 768
60592 + },
60593 + {
60594 + NAME => "dev_perio_tx_fifo_size_15",
60595 + DEFAULT => 256,
60596 + ENUM => [],
60597 + LOW => 4,
60598 + HIGH => 768
60599 + },
60600 + {
60601 + NAME => "host_rx_fifo_size",
60602 + DEFAULT => 1024,
60603 + ENUM => [],
60604 + LOW => 16,
60605 + HIGH => 32768
60606 + },
60607 + {
60608 + NAME => "host_nperio_tx_fifo_size",
60609 + DEFAULT => 1024,
60610 + ENUM => [],
60611 + LOW => 16,
60612 + HIGH => 32768
60613 + },
60614 + {
60615 + NAME => "host_perio_tx_fifo_size",
60616 + DEFAULT => 1024,
60617 + ENUM => [],
60618 + LOW => 16,
60619 + HIGH => 32768
60620 + },
60621 + {
60622 + NAME => "max_transfer_size",
60623 + DEFAULT => 65535,
60624 + ENUM => [],
60625 + LOW => 2047,
60626 + HIGH => 65535
60627 + },
60628 + {
60629 + NAME => "max_packet_count",
60630 + DEFAULT => 511,
60631 + ENUM => [],
60632 + LOW => 15,
60633 + HIGH => 511
60634 + },
60635 + {
60636 + NAME => "host_channels",
60637 + DEFAULT => 12,
60638 + ENUM => [],
60639 + LOW => 1,
60640 + HIGH => 16
60641 + },
60642 + {
60643 + NAME => "dev_endpoints",
60644 + DEFAULT => 6,
60645 + ENUM => [],
60646 + LOW => 1,
60647 + HIGH => 15
60648 + },
60649 + {
60650 + NAME => "phy_type",
60651 + DEFAULT => 1,
60652 + ENUM => [],
60653 + LOW => 0,
60654 + HIGH => 2
60655 + },
60656 + {
60657 + NAME => "phy_utmi_width",
60658 + DEFAULT => 16,
60659 + ENUM => [8, 16],
60660 + LOW => 8,
60661 + HIGH => 16
60662 + },
60663 + {
60664 + NAME => "phy_ulpi_ddr",
60665 + DEFAULT => 0,
60666 + ENUM => [],
60667 + LOW => 0,
60668 + HIGH => 1
60669 + },
60670 + ];
60671 +
60672 +
60673 +#
60674 +#
60675 +sub check_arch {
60676 + $_ = `uname -m`;
60677 + chomp;
60678 + unless (m/armv4tl/) {
60679 + warn "# \n# Can't execute on $_. Run on integrator platform.\n# \n";
60680 + return 0;
60681 + }
60682 + return 1;
60683 +}
60684 +
60685 +#
60686 +#
60687 +sub load_module {
60688 + my $params = shift;
60689 + print "\nRemoving Module\n";
60690 + system "rmmod dwc_otg";
60691 + print "Loading Module\n";
60692 + if ($params ne "") {
60693 + print "Module Parameters: $params\n";
60694 + }
60695 + if (system("modprobe dwc_otg $params")) {
60696 + warn "Unable to load module\n";
60697 + return 0;
60698 + }
60699 + return 1;
60700 +}
60701 +
60702 +#
60703 +#
60704 +sub test_status {
60705 + my $arg = shift;
60706 +
60707 + print "\n";
60708 +
60709 + if (defined $arg) {
60710 + warn "WARNING: $arg\n";
60711 + }
60712 +
60713 + if ($errors > 0) {
60714 + warn "TEST FAILED with $errors errors\n";
60715 + return 0;
60716 + } else {
60717 + print "TEST PASSED\n";
60718 + return 0 if (defined $arg);
60719 + }
60720 + return 1;
60721 +}
60722 +
60723 +#
60724 +#
60725 +@EXPORT = qw(
60726 +$sysfsdir
60727 +$paramdir
60728 +$params
60729 +$errors
60730 +check_arch
60731 +load_module
60732 +test_status
60733 +);
60734 +
60735 +1;
60736 --- /dev/null
60737 +++ b/drivers/usb/host/dwc_otg/test/test_mod_param.pl
60738 @@ -0,0 +1,133 @@
60739 +#!/usr/bin/perl -w
60740 +#
60741 +# Run this program on the integrator.
60742 +#
60743 +# - Tests module parameter default values.
60744 +# - Tests setting of valid module parameter values via modprobe.
60745 +# - Tests invalid module parameter values.
60746 +# -----------------------------------------------------------------------------
60747 +use strict;
60748 +use dwc_otg_test;
60749 +
60750 +check_arch() or die;
60751 +
60752 +#
60753 +#
60754 +sub test {
60755 + my ($param,$expected) = @_;
60756 + my $value = get($param);
60757 +
60758 + if ($value == $expected) {
60759 + print "$param = $value, okay\n";
60760 + }
60761 +
60762 + else {
60763 + warn "ERROR: value of $param != $expected, $value\n";
60764 + $errors ++;
60765 + }
60766 +}
60767 +
60768 +#
60769 +#
60770 +sub get {
60771 + my $param = shift;
60772 + my $tmp = `cat $paramdir/$param`;
60773 + chomp $tmp;
60774 + return $tmp;
60775 +}
60776 +
60777 +#
60778 +#
60779 +sub test_main {
60780 +
60781 + print "\nTesting Module Parameters\n";
60782 +
60783 + load_module("") or die;
60784 +
60785 + # Test initial values
60786 + print "\nTesting Default Values\n";
60787 + foreach (@{$params}) {
60788 + test ($_->{NAME}, $_->{DEFAULT});
60789 + }
60790 +
60791 + # Test low value
60792 + print "\nTesting Low Value\n";
60793 + my $cmd_params = "";
60794 + foreach (@{$params}) {
60795 + $cmd_params = $cmd_params . "$_->{NAME}=$_->{LOW} ";
60796 + }
60797 + load_module($cmd_params) or die;
60798 +
60799 + foreach (@{$params}) {
60800 + test ($_->{NAME}, $_->{LOW});
60801 + }
60802 +
60803 + # Test high value
60804 + print "\nTesting High Value\n";
60805 + $cmd_params = "";
60806 + foreach (@{$params}) {
60807 + $cmd_params = $cmd_params . "$_->{NAME}=$_->{HIGH} ";
60808 + }
60809 + load_module($cmd_params) or die;
60810 +
60811 + foreach (@{$params}) {
60812 + test ($_->{NAME}, $_->{HIGH});
60813 + }
60814 +
60815 + # Test Enum
60816 + print "\nTesting Enumerated\n";
60817 + foreach (@{$params}) {
60818 + if (defined $_->{ENUM}) {
60819 + my $value;
60820 + foreach $value (@{$_->{ENUM}}) {
60821 + $cmd_params = "$_->{NAME}=$value";
60822 + load_module($cmd_params) or die;
60823 + test ($_->{NAME}, $value);
60824 + }
60825 + }
60826 + }
60827 +
60828 + # Test Invalid Values
60829 + print "\nTesting Invalid Values\n";
60830 + $cmd_params = "";
60831 + foreach (@{$params}) {
60832 + $cmd_params = $cmd_params . sprintf "$_->{NAME}=%d ", $_->{LOW}-1;
60833 + }
60834 + load_module($cmd_params) or die;
60835 +
60836 + foreach (@{$params}) {
60837 + test ($_->{NAME}, $_->{DEFAULT});
60838 + }
60839 +
60840 + $cmd_params = "";
60841 + foreach (@{$params}) {
60842 + $cmd_params = $cmd_params . sprintf "$_->{NAME}=%d ", $_->{HIGH}+1;
60843 + }
60844 + load_module($cmd_params) or die;
60845 +
60846 + foreach (@{$params}) {
60847 + test ($_->{NAME}, $_->{DEFAULT});
60848 + }
60849 +
60850 + print "\nTesting Enumerated\n";
60851 + foreach (@{$params}) {
60852 + if (defined $_->{ENUM}) {
60853 + my $value;
60854 + foreach $value (@{$_->{ENUM}}) {
60855 + $value = $value + 1;
60856 + $cmd_params = "$_->{NAME}=$value";
60857 + load_module($cmd_params) or die;
60858 + test ($_->{NAME}, $_->{DEFAULT});
60859 + $value = $value - 2;
60860 + $cmd_params = "$_->{NAME}=$value";
60861 + load_module($cmd_params) or die;
60862 + test ($_->{NAME}, $_->{DEFAULT});
60863 + }
60864 + }
60865 + }
60866 +
60867 + test_status() or die;
60868 +}
60869 +
60870 +test_main();
60871 +0;
60872 --- /dev/null
60873 +++ b/drivers/usb/host/dwc_otg/test/test_sysfs.pl
60874 @@ -0,0 +1,193 @@
60875 +#!/usr/bin/perl -w
60876 +#
60877 +# Run this program on the integrator
60878 +# - Tests select sysfs attributes.
60879 +# - Todo ... test more attributes, hnp/srp, buspower/bussuspend, etc.
60880 +# -----------------------------------------------------------------------------
60881 +use strict;
60882 +use dwc_otg_test;
60883 +
60884 +check_arch() or die;
60885 +
60886 +#
60887 +#
60888 +sub test {
60889 + my ($attr,$expected) = @_;
60890 + my $string = get($attr);
60891 +
60892 + if ($string eq $expected) {
60893 + printf("$attr = $string, okay\n");
60894 + }
60895 + else {
60896 + warn "ERROR: value of $attr != $expected, $string\n";
60897 + $errors ++;
60898 + }
60899 +}
60900 +
60901 +#
60902 +#
60903 +sub set {
60904 + my ($reg, $value) = @_;
60905 + system "echo $value > $sysfsdir/$reg";
60906 +}
60907 +
60908 +#
60909 +#
60910 +sub get {
60911 + my $attr = shift;
60912 + my $string = `cat $sysfsdir/$attr`;
60913 + chomp $string;
60914 + if ($string =~ m/\s\=\s/) {
60915 + my $tmp;
60916 + ($tmp, $string) = split /\s=\s/, $string;
60917 + }
60918 + return $string;
60919 +}
60920 +
60921 +#
60922 +#
60923 +sub test_main {
60924 + print("\nTesting Sysfs Attributes\n");
60925 +
60926 + load_module("") or die;
60927 +
60928 + # Test initial values of regoffset/regvalue/guid/gsnpsid
60929 + print("\nTesting Default Values\n");
60930 +
60931 + test("regoffset", "0xffffffff");
60932 + test("regvalue", "invalid offset");
60933 + test("guid", "0x12345678"); # this will fail if it has been changed
60934 + test("gsnpsid", "0x4f54200a");
60935 +
60936 + # Test operation of regoffset/regvalue
60937 + print("\nTesting regoffset\n");
60938 + set('regoffset', '5a5a5a5a');
60939 + test("regoffset", "0xffffffff");
60940 +
60941 + set('regoffset', '0');
60942 + test("regoffset", "0x00000000");
60943 +
60944 + set('regoffset', '40000');
60945 + test("regoffset", "0x00000000");
60946 +
60947 + set('regoffset', '3ffff');
60948 + test("regoffset", "0x0003ffff");
60949 +
60950 + set('regoffset', '1');
60951 + test("regoffset", "0x00000001");
60952 +
60953 + print("\nTesting regvalue\n");
60954 + set('regoffset', '3c');
60955 + test("regvalue", "0x12345678");
60956 + set('regvalue', '5a5a5a5a');
60957 + test("regvalue", "0x5a5a5a5a");
60958 + set('regvalue','a5a5a5a5');
60959 + test("regvalue", "0xa5a5a5a5");
60960 + set('guid','12345678');
60961 +
60962 + # Test HNP Capable
60963 + print("\nTesting HNP Capable bit\n");
60964 + set('hnpcapable', '1');
60965 + test("hnpcapable", "0x1");
60966 + set('hnpcapable','0');
60967 + test("hnpcapable", "0x0");
60968 +
60969 + set('regoffset','0c');
60970 +
60971 + my $old = get('gusbcfg');
60972 + print("setting hnpcapable\n");
60973 + set('hnpcapable', '1');
60974 + test("hnpcapable", "0x1");
60975 + test('gusbcfg', sprintf "0x%08x", (oct ($old) | (1<<9)));
60976 + test('regvalue', sprintf "0x%08x", (oct ($old) | (1<<9)));
60977 +
60978 + $old = get('gusbcfg');
60979 + print("clearing hnpcapable\n");
60980 + set('hnpcapable', '0');
60981 + test("hnpcapable", "0x0");
60982 + test ('gusbcfg', sprintf "0x%08x", oct ($old) & (~(1<<9)));
60983 + test ('regvalue', sprintf "0x%08x", oct ($old) & (~(1<<9)));
60984 +
60985 + # Test SRP Capable
60986 + print("\nTesting SRP Capable bit\n");
60987 + set('srpcapable', '1');
60988 + test("srpcapable", "0x1");
60989 + set('srpcapable','0');
60990 + test("srpcapable", "0x0");
60991 +
60992 + set('regoffset','0c');
60993 +
60994 + $old = get('gusbcfg');
60995 + print("setting srpcapable\n");
60996 + set('srpcapable', '1');
60997 + test("srpcapable", "0x1");
60998 + test('gusbcfg', sprintf "0x%08x", (oct ($old) | (1<<8)));
60999 + test('regvalue', sprintf "0x%08x", (oct ($old) | (1<<8)));
61000 +
61001 + $old = get('gusbcfg');
61002 + print("clearing srpcapable\n");
61003 + set('srpcapable', '0');
61004 + test("srpcapable", "0x0");
61005 + test('gusbcfg', sprintf "0x%08x", oct ($old) & (~(1<<8)));
61006 + test('regvalue', sprintf "0x%08x", oct ($old) & (~(1<<8)));
61007 +
61008 + # Test GGPIO
61009 + print("\nTesting GGPIO\n");
61010 + set('ggpio','5a5a5a5a');
61011 + test('ggpio','0x5a5a0000');
61012 + set('ggpio','a5a5a5a5');
61013 + test('ggpio','0xa5a50000');
61014 + set('ggpio','11110000');
61015 + test('ggpio','0x11110000');
61016 + set('ggpio','00001111');
61017 + test('ggpio','0x00000000');
61018 +
61019 + # Test DEVSPEED
61020 + print("\nTesting DEVSPEED\n");
61021 + set('regoffset','800');
61022 + $old = get('regvalue');
61023 + set('devspeed','0');
61024 + test('devspeed','0x0');
61025 + test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3)));
61026 + set('devspeed','1');
61027 + test('devspeed','0x1');
61028 + test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 1));
61029 + set('devspeed','2');
61030 + test('devspeed','0x2');
61031 + test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 2));
61032 + set('devspeed','3');
61033 + test('devspeed','0x3');
61034 + test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 3));
61035 + set('devspeed','4');
61036 + test('devspeed','0x0');
61037 + test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3)));
61038 + set('devspeed','5');
61039 + test('devspeed','0x1');
61040 + test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 1));
61041 +
61042 +
61043 + # mode Returns the current mode:0 for device mode1 for host mode Read
61044 + # hnp Initiate the Host Negotiation Protocol. Read returns the status. Read/Write
61045 + # srp Initiate the Session Request Protocol. Read returns the status. Read/Write
61046 + # buspower Get or Set the Power State of the bus (0 - Off or 1 - On) Read/Write
61047 + # bussuspend Suspend the USB bus. Read/Write
61048 + # busconnected Get the connection status of the bus Read
61049 +
61050 + # gotgctl Get or set the Core Control Status Register. Read/Write
61051 + ## gusbcfg Get or set the Core USB Configuration Register Read/Write
61052 + # grxfsiz Get or set the Receive FIFO Size Register Read/Write
61053 + # gnptxfsiz Get or set the non-periodic Transmit Size Register Read/Write
61054 + # gpvndctl Get or set the PHY Vendor Control Register Read/Write
61055 + ## ggpio Get the value in the lower 16-bits of the General Purpose IO Register or Set the upper 16 bits. Read/Write
61056 + ## guid Get or set the value of the User ID Register Read/Write
61057 + ## gsnpsid Get the value of the Synopsys ID Regester Read
61058 + ## devspeed Get or set the device speed setting in the DCFG register Read/Write
61059 + # enumspeed Gets the device enumeration Speed. Read
61060 + # hptxfsiz Get the value of the Host Periodic Transmit FIFO Read
61061 + # hprt0 Get or Set the value in the Host Port Control and Status Register Read/Write
61062 +
61063 + test_status("TEST NYI") or die;
61064 +}
61065 +
61066 +test_main();
61067 +0;
OpenWrt Source Repository