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brcm2708: update 4.1 patches
[openwrt/openwrt.git] / target / linux / brcm2708 / patches-4.1 / 0007-dmaengine-Add-support-for-BCM2708.patch
1 From 04a4ceef489437512b4d40071e049950d56fbb27 Mon Sep 17 00:00:00 2001
2 From: Florian Meier <florian.meier@koalo.de>
3 Date: Fri, 22 Nov 2013 14:22:53 +0100
4 Subject: [PATCH 007/171] dmaengine: Add support for BCM2708
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
8
9 Add support for DMA controller of BCM2708 as used in the Raspberry Pi.
10 Currently it only supports cyclic DMA.
11
12 Signed-off-by: Florian Meier <florian.meier@koalo.de>
13
14 dmaengine: expand functionality by supporting scatter/gather transfers sdhci-bcm2708 and dma.c: fix for LITE channels
15
16 DMA: fix cyclic LITE length overflow bug
17
18 dmaengine: bcm2708: Remove chancnt affectations
19
20 Mirror bcm2835-dma.c commit 9eba5536a7434c69d8c185d4bd1c70734d92287d:
21 chancnt is already filled by dma_async_device_register, which uses the channel
22 list to know how much channels there is.
23
24 Since it's already filled, we can safely remove it from the drivers' probe
25 function.
26
27 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
28
29 dmaengine: bcm2708: overwrite dreq only if it is not set
30
31 dreq is set when the DMA channel is fetched from Device Tree.
32 slave_id is set using dmaengine_slave_config().
33 Only overwrite dreq with slave_id if it is not set.
34
35 dreq/slave_id in the cyclic DMA case is not touched, because I don't
36 have hardware to test with.
37
38 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
39
40 dmaengine: bcm2708: do device registration in the board file
41
42 Don't register the device in the driver. Do it in the board file.
43
44 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
45
46 dmaengine: bcm2708: don't restrict DT support to ARCH_BCM2835
47
48 Both ARCH_BCM2835 and ARCH_BCM270x are built with OF now.
49 Add Device Tree support to the non ARCH_BCM2835 case.
50 Use the same driver name regardless of architecture.
51
52 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
53
54 BCM270x_DT: add bcm2835-dma entry
55
56 Add Device Tree entry for bcm2835-dma.
57 The entry doesn't contain any resources since they are handled
58 by the arch/arm/mach-bcm270x/dma.c driver.
59 In non-DT mode, don't add the device in the board file.
60
61 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
62
63 bcm2708-dmaengine: Add debug options
64
65 BCM270x: Add memory and irq resources to dmaengine device and DT
66
67 Prepare for merging of the legacy DMA API arch driver dma.c
68 with bcm2708-dmaengine by adding memory and irq resources both
69 to platform file device and Device Tree node.
70 Don't use BCM_DMAMAN_DRIVER_NAME so we don't have to include mach/dma.h
71
72 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
73
74 dmaengine: bcm2708: Merge with arch dma.c driver and disable dma.c
75
76 Merge the legacy DMA API driver with bcm2708-dmaengine.
77 This is done so we can use bcm2708_fb on ARCH_BCM2835 (mailbox
78 driver is also needed).
79
80 Changes to the dma.c code:
81 - Use BIT() macro.
82 - Cutdown some comments to one line.
83 - Add mutex to vc_dmaman and use this, since the dev lock is locked
84 during probing of the engine part.
85 - Add global g_dmaman variable since drvdata is used by the engine part.
86 - Restructure for readability:
87 vc_dmaman_chan_alloc()
88 vc_dmaman_chan_free()
89 bcm_dma_chan_free()
90 - Restructure bcm_dma_chan_alloc() to simplify error handling.
91 - Use device irq resources instead of hardcoded bcm_dma_irqs table.
92 - Remove dev_dmaman_register() and code it directly.
93 - Remove dev_dmaman_deregister() and code it directly.
94 - Simplify bcm_dmaman_probe() using devm_* functions.
95 - Get dmachans from DT if available.
96 - Keep 'dma.dmachans' module argument name for backwards compatibility.
97
98 Make it available on ARCH_BCM2835 as well.
99
100 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
101
102 dmaengine: bcm2708: set residue_granularity field
103
104 bcm2708-dmaengine supports residue reporting at burst level
105 but didn't report this via the residue_granularity field.
106
107 Without this field set properly we get playback issues with I2S cards.
108 ---
109 arch/arm/mach-bcm2708/bcm2708.c | 68 ++
110 arch/arm/mach-bcm2709/bcm2709.c | 68 ++
111 drivers/dma/Kconfig | 13 +-
112 drivers/dma/Makefile | 1 +
113 drivers/dma/bcm2708-dmaengine.c | 1298 +++++++++++++++++++++++++++++
114 include/linux/platform_data/dma-bcm2708.h | 127 +++
115 6 files changed, 1574 insertions(+), 1 deletion(-)
116 create mode 100644 drivers/dma/bcm2708-dmaengine.c
117 create mode 100644 include/linux/platform_data/dma-bcm2708.h
118
119 --- a/arch/arm/mach-bcm2708/bcm2708.c
120 +++ b/arch/arm/mach-bcm2708/bcm2708.c
121 @@ -234,6 +234,73 @@ static struct amba_device *amba_devs[] _
122 &uart0_device,
123 };
124
125 +static struct resource bcm2708_dmaengine_resources[] = {
126 + {
127 + .start = DMA_BASE,
128 + .end = DMA_BASE + SZ_4K - 1,
129 + .flags = IORESOURCE_MEM,
130 + }, {
131 + .start = IRQ_DMA0,
132 + .end = IRQ_DMA0,
133 + .flags = IORESOURCE_IRQ,
134 + }, {
135 + .start = IRQ_DMA1,
136 + .end = IRQ_DMA1,
137 + .flags = IORESOURCE_IRQ,
138 + }, {
139 + .start = IRQ_DMA2,
140 + .end = IRQ_DMA2,
141 + .flags = IORESOURCE_IRQ,
142 + }, {
143 + .start = IRQ_DMA3,
144 + .end = IRQ_DMA3,
145 + .flags = IORESOURCE_IRQ,
146 + }, {
147 + .start = IRQ_DMA4,
148 + .end = IRQ_DMA4,
149 + .flags = IORESOURCE_IRQ,
150 + }, {
151 + .start = IRQ_DMA5,
152 + .end = IRQ_DMA5,
153 + .flags = IORESOURCE_IRQ,
154 + }, {
155 + .start = IRQ_DMA6,
156 + .end = IRQ_DMA6,
157 + .flags = IORESOURCE_IRQ,
158 + }, {
159 + .start = IRQ_DMA7,
160 + .end = IRQ_DMA7,
161 + .flags = IORESOURCE_IRQ,
162 + }, {
163 + .start = IRQ_DMA8,
164 + .end = IRQ_DMA8,
165 + .flags = IORESOURCE_IRQ,
166 + }, {
167 + .start = IRQ_DMA9,
168 + .end = IRQ_DMA9,
169 + .flags = IORESOURCE_IRQ,
170 + }, {
171 + .start = IRQ_DMA10,
172 + .end = IRQ_DMA10,
173 + .flags = IORESOURCE_IRQ,
174 + }, {
175 + .start = IRQ_DMA11,
176 + .end = IRQ_DMA11,
177 + .flags = IORESOURCE_IRQ,
178 + }, {
179 + .start = IRQ_DMA12,
180 + .end = IRQ_DMA12,
181 + .flags = IORESOURCE_IRQ,
182 + }
183 +};
184 +
185 +static struct platform_device bcm2708_dmaengine_device = {
186 + .name = "bcm2708-dmaengine",
187 + .id = -1,
188 + .resource = bcm2708_dmaengine_resources,
189 + .num_resources = ARRAY_SIZE(bcm2708_dmaengine_resources),
190 +};
191 +
192 static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
193
194 static struct platform_device bcm2708_fb_device = {
195 @@ -463,6 +530,7 @@ void __init bcm2708_init(void)
196 bcm2708_init_clocks();
197 bcm2708_dt_init();
198
199 + bcm_register_device_dt(&bcm2708_dmaengine_device);
200 bcm_register_device(&bcm2708_vcio_device);
201 #ifdef CONFIG_BCM2708_GPIO
202 bcm_register_device_dt(&bcm2708_gpio_device);
203 --- a/arch/arm/mach-bcm2709/bcm2709.c
204 +++ b/arch/arm/mach-bcm2709/bcm2709.c
205 @@ -244,6 +244,73 @@ static struct amba_device *amba_devs[] _
206 &uart0_device,
207 };
208
209 +static struct resource bcm2708_dmaengine_resources[] = {
210 + {
211 + .start = DMA_BASE,
212 + .end = DMA_BASE + SZ_4K - 1,
213 + .flags = IORESOURCE_MEM,
214 + }, {
215 + .start = IRQ_DMA0,
216 + .end = IRQ_DMA0,
217 + .flags = IORESOURCE_IRQ,
218 + }, {
219 + .start = IRQ_DMA1,
220 + .end = IRQ_DMA1,
221 + .flags = IORESOURCE_IRQ,
222 + }, {
223 + .start = IRQ_DMA2,
224 + .end = IRQ_DMA2,
225 + .flags = IORESOURCE_IRQ,
226 + }, {
227 + .start = IRQ_DMA3,
228 + .end = IRQ_DMA3,
229 + .flags = IORESOURCE_IRQ,
230 + }, {
231 + .start = IRQ_DMA4,
232 + .end = IRQ_DMA4,
233 + .flags = IORESOURCE_IRQ,
234 + }, {
235 + .start = IRQ_DMA5,
236 + .end = IRQ_DMA5,
237 + .flags = IORESOURCE_IRQ,
238 + }, {
239 + .start = IRQ_DMA6,
240 + .end = IRQ_DMA6,
241 + .flags = IORESOURCE_IRQ,
242 + }, {
243 + .start = IRQ_DMA7,
244 + .end = IRQ_DMA7,
245 + .flags = IORESOURCE_IRQ,
246 + }, {
247 + .start = IRQ_DMA8,
248 + .end = IRQ_DMA8,
249 + .flags = IORESOURCE_IRQ,
250 + }, {
251 + .start = IRQ_DMA9,
252 + .end = IRQ_DMA9,
253 + .flags = IORESOURCE_IRQ,
254 + }, {
255 + .start = IRQ_DMA10,
256 + .end = IRQ_DMA10,
257 + .flags = IORESOURCE_IRQ,
258 + }, {
259 + .start = IRQ_DMA11,
260 + .end = IRQ_DMA11,
261 + .flags = IORESOURCE_IRQ,
262 + }, {
263 + .start = IRQ_DMA12,
264 + .end = IRQ_DMA12,
265 + .flags = IORESOURCE_IRQ,
266 + }
267 +};
268 +
269 +static struct platform_device bcm2708_dmaengine_device = {
270 + .name = "bcm2708-dmaengine",
271 + .id = -1,
272 + .resource = bcm2708_dmaengine_resources,
273 + .num_resources = ARRAY_SIZE(bcm2708_dmaengine_resources),
274 +};
275 +
276 static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
277
278 static struct platform_device bcm2708_fb_device = {
279 @@ -483,6 +550,7 @@ void __init bcm2709_init(void)
280 bcm2709_init_clocks();
281 bcm2709_dt_init();
282
283 + bcm_register_device_dt(&bcm2708_dmaengine_device);
284 bcm_register_device(&bcm2708_vcio_device);
285 #ifdef CONFIG_BCM2708_GPIO
286 bcm_register_device_dt(&bcm2708_gpio_device);
287 --- a/drivers/dma/Kconfig
288 +++ b/drivers/dma/Kconfig
289 @@ -337,6 +337,17 @@ config DMA_BCM2835
290 select DMA_ENGINE
291 select DMA_VIRTUAL_CHANNELS
292
293 +config DMA_BCM2708
294 + tristate "BCM2708 DMA engine support"
295 + depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835
296 + select DMA_ENGINE
297 + select DMA_VIRTUAL_CHANNELS
298 +
299 +config DMA_BCM2708_LEGACY
300 + bool "BCM2708 DMA legacy API support"
301 + depends on DMA_BCM2708
302 + default y
303 +
304 config TI_CPPI41
305 tristate "AM33xx CPPI41 DMA support"
306 depends on ARCH_OMAP
307 @@ -385,7 +396,7 @@ config MOXART_DMA
308 select DMA_VIRTUAL_CHANNELS
309 help
310 Enable support for the MOXA ART SoC DMA controller.
311 -
312 +
313 config FSL_EDMA
314 tristate "Freescale eDMA engine support"
315 depends on OF
316 --- a/drivers/dma/Makefile
317 +++ b/drivers/dma/Makefile
318 @@ -39,6 +39,7 @@ obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
319 obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
320 obj-$(CONFIG_DMA_OMAP) += omap-dma.o
321 obj-$(CONFIG_DMA_BCM2835) += bcm2835-dma.o
322 +obj-$(CONFIG_DMA_BCM2708) += bcm2708-dmaengine.o
323 obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
324 obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o
325 obj-$(CONFIG_DMA_JZ4780) += dma-jz4780.o
326 --- /dev/null
327 +++ b/drivers/dma/bcm2708-dmaengine.c
328 @@ -0,0 +1,1298 @@
329 +/*
330 + * BCM2835 DMA engine support
331 + *
332 + * This driver supports cyclic and scatter/gather DMA transfers.
333 + *
334 + * Author: Florian Meier <florian.meier@koalo.de>
335 + * Gellert Weisz <gellert@raspberrypi.org>
336 + * Copyright 2013-2014
337 + *
338 + * Based on
339 + * OMAP DMAengine support by Russell King
340 + *
341 + * BCM2708 DMA Driver
342 + * Copyright (C) 2010 Broadcom
343 + *
344 + * Raspberry Pi PCM I2S ALSA Driver
345 + * Copyright (c) by Phil Poole 2013
346 + *
347 + * MARVELL MMP Peripheral DMA Driver
348 + * Copyright 2012 Marvell International Ltd.
349 + *
350 + * This program is free software; you can redistribute it and/or modify
351 + * it under the terms of the GNU General Public License as published by
352 + * the Free Software Foundation; either version 2 of the License, or
353 + * (at your option) any later version.
354 + *
355 + * This program is distributed in the hope that it will be useful,
356 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
357 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
358 + * GNU General Public License for more details.
359 + */
360 +
361 +#include <linux/dmaengine.h>
362 +#include <linux/dma-mapping.h>
363 +#include <linux/err.h>
364 +#include <linux/init.h>
365 +#include <linux/interrupt.h>
366 +#include <linux/list.h>
367 +#include <linux/module.h>
368 +#include <linux/platform_data/dma-bcm2708.h>
369 +#include <linux/platform_device.h>
370 +#include <linux/slab.h>
371 +#include <linux/io.h>
372 +#include <linux/spinlock.h>
373 +#include <linux/of.h>
374 +#include <linux/of_dma.h>
375 +
376 +#include "virt-dma.h"
377 +
378 +static unsigned dma_debug;
379 +
380 +/*
381 + * Legacy DMA API
382 + */
383 +
384 +#ifdef CONFIG_DMA_BCM2708_LEGACY
385 +
386 +#define CACHE_LINE_MASK 31
387 +#define DEFAULT_DMACHAN_BITMAP 0x10 /* channel 4 only */
388 +
389 +/* valid only for channels 0 - 14, 15 has its own base address */
390 +#define BCM2708_DMA_CHAN(n) ((n) << 8) /* base address */
391 +#define BCM2708_DMA_CHANIO(dma_base, n) \
392 + ((void __iomem *)((char *)(dma_base) + BCM2708_DMA_CHAN(n)))
393 +
394 +struct vc_dmaman {
395 + void __iomem *dma_base;
396 + u32 chan_available; /* bitmap of available channels */
397 + u32 has_feature[BCM_DMA_FEATURE_COUNT]; /* bitmap of feature presence */
398 + struct mutex lock;
399 +};
400 +
401 +static struct device *dmaman_dev; /* we assume there's only one! */
402 +static struct vc_dmaman *g_dmaman; /* DMA manager */
403 +static int dmachans = -1; /* module parameter */
404 +
405 +/* DMA Auxiliary Functions */
406 +
407 +/* A DMA buffer on an arbitrary boundary may separate a cache line into a
408 + section inside the DMA buffer and another section outside it.
409 + Even if we flush DMA buffers from the cache there is always the chance that
410 + during a DMA someone will access the part of a cache line that is outside
411 + the DMA buffer - which will then bring in unwelcome data.
412 + Without being able to dictate our own buffer pools we must insist that
413 + DMA buffers consist of a whole number of cache lines.
414 +*/
415 +extern int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len)
416 +{
417 + int i;
418 +
419 + for (i = 0; i < sg_len; i++) {
420 + if (sg_ptr[i].offset & CACHE_LINE_MASK ||
421 + sg_ptr[i].length & CACHE_LINE_MASK)
422 + return 0;
423 + }
424 +
425 + return 1;
426 +}
427 +EXPORT_SYMBOL_GPL(bcm_sg_suitable_for_dma);
428 +
429 +extern void bcm_dma_start(void __iomem *dma_chan_base,
430 + dma_addr_t control_block)
431 +{
432 + dsb(); /* ARM data synchronization (push) operation */
433 +
434 + writel(control_block, dma_chan_base + BCM2708_DMA_ADDR);
435 + writel(BCM2708_DMA_ACTIVE, dma_chan_base + BCM2708_DMA_CS);
436 +}
437 +EXPORT_SYMBOL_GPL(bcm_dma_start);
438 +
439 +extern void bcm_dma_wait_idle(void __iomem *dma_chan_base)
440 +{
441 + dsb();
442 +
443 + /* ugly busy wait only option for now */
444 + while (readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE)
445 + cpu_relax();
446 +}
447 +EXPORT_SYMBOL_GPL(bcm_dma_wait_idle);
448 +
449 +extern bool bcm_dma_is_busy(void __iomem *dma_chan_base)
450 +{
451 + dsb();
452 +
453 + return readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE;
454 +}
455 +EXPORT_SYMBOL_GPL(bcm_dma_is_busy);
456 +
457 +/* Complete an ongoing DMA (assuming its results are to be ignored)
458 + Does nothing if there is no DMA in progress.
459 + This routine waits for the current AXI transfer to complete before
460 + terminating the current DMA. If the current transfer is hung on a DREQ used
461 + by an uncooperative peripheral the AXI transfer may never complete. In this
462 + case the routine times out and return a non-zero error code.
463 + Use of this routine doesn't guarantee that the ongoing or aborted DMA
464 + does not produce an interrupt.
465 +*/
466 +extern int bcm_dma_abort(void __iomem *dma_chan_base)
467 +{
468 + unsigned long int cs;
469 + int rc = 0;
470 +
471 + cs = readl(dma_chan_base + BCM2708_DMA_CS);
472 +
473 + if (BCM2708_DMA_ACTIVE & cs) {
474 + long int timeout = 10000;
475 +
476 + /* write 0 to the active bit - pause the DMA */
477 + writel(0, dma_chan_base + BCM2708_DMA_CS);
478 +
479 + /* wait for any current AXI transfer to complete */
480 + while (0 != (cs & BCM2708_DMA_ISPAUSED) && --timeout >= 0)
481 + cs = readl(dma_chan_base + BCM2708_DMA_CS);
482 +
483 + if (0 != (cs & BCM2708_DMA_ISPAUSED)) {
484 + /* we'll un-pause when we set of our next DMA */
485 + rc = -ETIMEDOUT;
486 +
487 + } else if (BCM2708_DMA_ACTIVE & cs) {
488 + /* terminate the control block chain */
489 + writel(0, dma_chan_base + BCM2708_DMA_NEXTCB);
490 +
491 + /* abort the whole DMA */
492 + writel(BCM2708_DMA_ABORT | BCM2708_DMA_ACTIVE,
493 + dma_chan_base + BCM2708_DMA_CS);
494 + }
495 + }
496 +
497 + return rc;
498 +}
499 +EXPORT_SYMBOL_GPL(bcm_dma_abort);
500 +
501 + /* DMA Manager Device Methods */
502 +
503 +static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base,
504 + u32 chans_available)
505 +{
506 + dmaman->dma_base = dma_base;
507 + dmaman->chan_available = chans_available;
508 + dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c; /* 2 & 3 */
509 + dmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01; /* 0 */
510 + dmaman->has_feature[BCM_DMA_FEATURE_NORMAL_ORD] = 0xfe; /* 1 to 7 */
511 + dmaman->has_feature[BCM_DMA_FEATURE_LITE_ORD] = 0x7f00; /* 8 to 14 */
512 +}
513 +
514 +static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman,
515 + unsigned preferred_feature_set)
516 +{
517 + u32 chans;
518 + int chan = 0;
519 + int feature;
520 +
521 + chans = dmaman->chan_available;
522 + for (feature = 0; feature < BCM_DMA_FEATURE_COUNT; feature++)
523 + /* select the subset of available channels with the desired
524 + feature so long as some of the candidate channels have that
525 + feature */
526 + if ((preferred_feature_set & (1 << feature)) &&
527 + (chans & dmaman->has_feature[feature]))
528 + chans &= dmaman->has_feature[feature];
529 +
530 + if (!chans)
531 + return -ENOENT;
532 +
533 + /* return the ordinal of the first channel in the bitmap */
534 + while (chans != 0 && (chans & 1) == 0) {
535 + chans >>= 1;
536 + chan++;
537 + }
538 + /* claim the channel */
539 + dmaman->chan_available &= ~(1 << chan);
540 +
541 + return chan;
542 +}
543 +
544 +static int vc_dmaman_chan_free(struct vc_dmaman *dmaman, int chan)
545 +{
546 + if (chan < 0)
547 + return -EINVAL;
548 +
549 + if ((1 << chan) & dmaman->chan_available)
550 + return -EIDRM;
551 +
552 + dmaman->chan_available |= (1 << chan);
553 +
554 + return 0;
555 +}
556 +
557 +/* DMA Manager Monitor */
558 +
559 +extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
560 + void __iomem **out_dma_base, int *out_dma_irq)
561 +{
562 + struct vc_dmaman *dmaman = g_dmaman;
563 + struct platform_device *pdev = to_platform_device(dmaman_dev);
564 + struct resource *r;
565 + int chan;
566 +
567 + if (!dmaman_dev)
568 + return -ENODEV;
569 +
570 + mutex_lock(&dmaman->lock);
571 + chan = vc_dmaman_chan_alloc(dmaman, preferred_feature_set);
572 + if (chan < 0)
573 + goto out;
574 +
575 + r = platform_get_resource(pdev, IORESOURCE_IRQ, (unsigned int)chan);
576 + if (!r) {
577 + dev_err(dmaman_dev, "failed to get irq for DMA channel %d\n",
578 + chan);
579 + vc_dmaman_chan_free(dmaman, chan);
580 + chan = -ENOENT;
581 + goto out;
582 + }
583 +
584 + *out_dma_base = BCM2708_DMA_CHANIO(dmaman->dma_base, chan);
585 + *out_dma_irq = r->start;
586 + dev_dbg(dmaman_dev,
587 + "Legacy API allocated channel=%d, base=%p, irq=%i\n",
588 + chan, *out_dma_base, *out_dma_irq);
589 +
590 +out:
591 + mutex_unlock(&dmaman->lock);
592 +
593 + return chan;
594 +}
595 +EXPORT_SYMBOL_GPL(bcm_dma_chan_alloc);
596 +
597 +extern int bcm_dma_chan_free(int channel)
598 +{
599 + struct vc_dmaman *dmaman = g_dmaman;
600 + int rc;
601 +
602 + if (!dmaman_dev)
603 + return -ENODEV;
604 +
605 + mutex_lock(&dmaman->lock);
606 + rc = vc_dmaman_chan_free(dmaman, channel);
607 + mutex_unlock(&dmaman->lock);
608 +
609 + return rc;
610 +}
611 +EXPORT_SYMBOL_GPL(bcm_dma_chan_free);
612 +
613 +static int bcm_dmaman_probe(struct platform_device *pdev)
614 +{
615 + struct device *dev = &pdev->dev;
616 + struct vc_dmaman *dmaman;
617 + struct resource *r;
618 + void __iomem *dma_base;
619 + uint32_t val;
620 +
621 + if (!of_property_read_u32(dev->of_node,
622 + "brcm,dma-channel-mask", &val))
623 + dmachans = val;
624 + else if (dmachans == -1)
625 + dmachans = DEFAULT_DMACHAN_BITMAP;
626 +
627 + dmaman = devm_kzalloc(dev, sizeof(*dmaman), GFP_KERNEL);
628 + if (!dmaman)
629 + return -ENOMEM;
630 +
631 + mutex_init(&dmaman->lock);
632 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
633 + dma_base = devm_ioremap_resource(dev, r);
634 + if (IS_ERR(dma_base))
635 + return PTR_ERR(dma_base);
636 +
637 + vc_dmaman_init(dmaman, dma_base, dmachans);
638 + g_dmaman = dmaman;
639 + dmaman_dev = dev;
640 +
641 + dev_info(dev, "DMA legacy API manager at %p, dmachans=0x%x\n",
642 + dma_base, dmachans);
643 +
644 + return 0;
645 +}
646 +
647 +static int bcm_dmaman_remove(struct platform_device *pdev)
648 +{
649 + dmaman_dev = NULL;
650 +
651 + return 0;
652 +}
653 +
654 +#else /* CONFIG_DMA_BCM2708_LEGACY */
655 +
656 +static int bcm_dmaman_remove(struct platform_device *pdev)
657 +{
658 + return 0;
659 +}
660 +
661 +#endif /* CONFIG_DMA_BCM2708_LEGACY */
662 +
663 +/*
664 + * DMA engine
665 + */
666 +
667 +struct bcm2835_dmadev {
668 + struct dma_device ddev;
669 + spinlock_t lock;
670 + void __iomem *base;
671 + struct device_dma_parameters dma_parms;
672 +};
673 +
674 +struct bcm2835_dma_cb {
675 + uint32_t info;
676 + uint32_t src;
677 + uint32_t dst;
678 + uint32_t length;
679 + uint32_t stride;
680 + uint32_t next;
681 + uint32_t pad[2];
682 +};
683 +
684 +struct bcm2835_chan {
685 + struct virt_dma_chan vc;
686 + struct list_head node;
687 +
688 + struct dma_slave_config cfg;
689 + bool cyclic;
690 +
691 + int ch;
692 + struct bcm2835_desc *desc;
693 +
694 + void __iomem *chan_base;
695 + int irq_number;
696 +
697 + unsigned int dreq;
698 +};
699 +
700 +struct bcm2835_desc {
701 + struct virt_dma_desc vd;
702 + enum dma_transfer_direction dir;
703 +
704 + unsigned int control_block_size;
705 + struct bcm2835_dma_cb *control_block_base;
706 + dma_addr_t control_block_base_phys;
707 +
708 + unsigned int frames;
709 + size_t size;
710 +};
711 +
712 +#define BCM2835_DMA_CS 0x00
713 +#define BCM2835_DMA_ADDR 0x04
714 +#define BCM2835_DMA_SOURCE_AD 0x0c
715 +#define BCM2835_DMA_DEST_AD 0x10
716 +#define BCM2835_DMA_NEXTCB 0x1C
717 +
718 +/* DMA CS Control and Status bits */
719 +#define BCM2835_DMA_ACTIVE BIT(0)
720 +#define BCM2835_DMA_INT BIT(2)
721 +#define BCM2835_DMA_ISPAUSED BIT(4) /* Pause requested or not active */
722 +#define BCM2835_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */
723 +#define BCM2835_DMA_ERR BIT(8)
724 +#define BCM2835_DMA_ABORT BIT(30) /* Stop current CB, go to next, WO */
725 +#define BCM2835_DMA_RESET BIT(31) /* WO, self clearing */
726 +
727 +#define BCM2835_DMA_INT_EN BIT(0)
728 +#define BCM2835_DMA_WAIT_RESP BIT(3)
729 +#define BCM2835_DMA_D_INC BIT(4)
730 +#define BCM2835_DMA_D_WIDTH BIT(5)
731 +#define BCM2835_DMA_D_DREQ BIT(6)
732 +#define BCM2835_DMA_S_INC BIT(8)
733 +#define BCM2835_DMA_S_WIDTH BIT(9)
734 +#define BCM2835_DMA_S_DREQ BIT(10)
735 +
736 +#define BCM2835_DMA_PER_MAP(x) ((x) << 16)
737 +#define BCM2835_DMA_WAITS(x) (((x)&0x1f) << 21)
738 +
739 +#define SDHCI_BCM_DMA_WAITS 0 /* delays slowing DMA transfers: 0-31 */
740 +
741 +#define BCM2835_DMA_DATA_TYPE_S8 1
742 +#define BCM2835_DMA_DATA_TYPE_S16 2
743 +#define BCM2835_DMA_DATA_TYPE_S32 4
744 +#define BCM2835_DMA_DATA_TYPE_S128 16
745 +
746 +#define BCM2835_DMA_BULK_MASK BIT(0)
747 +#define BCM2835_DMA_FIQ_MASK (BIT(2) | BIT(3))
748 +
749 +
750 +/* Valid only for channels 0 - 14, 15 has its own base address */
751 +#define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */
752 +#define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n))
753 +
754 +#define MAX_LITE_TRANSFER 32768
755 +#define MAX_NORMAL_TRANSFER 1073741824
756 +
757 +static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d)
758 +{
759 + return container_of(d, struct bcm2835_dmadev, ddev);
760 +}
761 +
762 +static inline struct bcm2835_chan *to_bcm2835_dma_chan(struct dma_chan *c)
763 +{
764 + return container_of(c, struct bcm2835_chan, vc.chan);
765 +}
766 +
767 +static inline struct bcm2835_desc *to_bcm2835_dma_desc(
768 + struct dma_async_tx_descriptor *t)
769 +{
770 + return container_of(t, struct bcm2835_desc, vd.tx);
771 +}
772 +
773 +static void dma_dumpregs(struct bcm2835_chan *c)
774 +{
775 + pr_debug("-------------DMA DUMPREGS-------------\n");
776 + pr_debug("CS= %u\n",
777 + readl(c->chan_base + BCM2835_DMA_CS));
778 + pr_debug("ADDR= %u\n",
779 + readl(c->chan_base + BCM2835_DMA_ADDR));
780 + pr_debug("SOURCE_ADDR= %u\n",
781 + readl(c->chan_base + BCM2835_DMA_SOURCE_AD));
782 + pr_debug("DEST_AD= %u\n",
783 + readl(c->chan_base + BCM2835_DMA_DEST_AD));
784 + pr_debug("NEXTCB= %u\n",
785 + readl(c->chan_base + BCM2835_DMA_NEXTCB));
786 + pr_debug("--------------------------------------\n");
787 +}
788 +
789 +static void bcm2835_dma_desc_free(struct virt_dma_desc *vd)
790 +{
791 + struct bcm2835_desc *desc = container_of(vd, struct bcm2835_desc, vd);
792 + dma_free_coherent(desc->vd.tx.chan->device->dev,
793 + desc->control_block_size,
794 + desc->control_block_base,
795 + desc->control_block_base_phys);
796 + kfree(desc);
797 +}
798 +
799 +static int bcm2835_dma_abort(void __iomem *chan_base)
800 +{
801 + unsigned long cs;
802 + long int timeout = 10000;
803 +
804 + cs = readl(chan_base + BCM2835_DMA_CS);
805 + if (!(cs & BCM2835_DMA_ACTIVE))
806 + return 0;
807 +
808 + /* Write 0 to the active bit - Pause the DMA */
809 + writel(0, chan_base + BCM2835_DMA_CS);
810 +
811 + /* Wait for any current AXI transfer to complete */
812 + while ((cs & BCM2835_DMA_ISPAUSED) && --timeout) {
813 + cpu_relax();
814 + cs = readl(chan_base + BCM2835_DMA_CS);
815 + }
816 +
817 + /* We'll un-pause when we set of our next DMA */
818 + if (!timeout)
819 + return -ETIMEDOUT;
820 +
821 + if (!(cs & BCM2835_DMA_ACTIVE))
822 + return 0;
823 +
824 + /* Terminate the control block chain */
825 + writel(0, chan_base + BCM2835_DMA_NEXTCB);
826 +
827 + /* Abort the whole DMA */
828 + writel(BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE,
829 + chan_base + BCM2835_DMA_CS);
830 +
831 + return 0;
832 +}
833 +
834 +
835 +static void bcm2835_dma_start_desc(struct bcm2835_chan *c)
836 +{
837 + struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
838 + struct bcm2835_desc *d;
839 +
840 + if (!vd) {
841 + c->desc = NULL;
842 + return;
843 + }
844 +
845 + list_del(&vd->node);
846 +
847 + c->desc = d = to_bcm2835_dma_desc(&vd->tx);
848 +
849 + writel(d->control_block_base_phys, c->chan_base + BCM2835_DMA_ADDR);
850 + writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS);
851 +
852 +}
853 +
854 +static irqreturn_t bcm2835_dma_callback(int irq, void *data)
855 +{
856 + struct bcm2835_chan *c = data;
857 + struct bcm2835_desc *d;
858 + unsigned long flags;
859 +
860 + spin_lock_irqsave(&c->vc.lock, flags);
861 +
862 + /* Acknowledge interrupt */
863 + writel(BCM2835_DMA_INT, c->chan_base + BCM2835_DMA_CS);
864 +
865 + d = c->desc;
866 +
867 + if (d) {
868 + if (c->cyclic) {
869 + vchan_cyclic_callback(&d->vd);
870 +
871 + /* Keep the DMA engine running */
872 + writel(BCM2835_DMA_ACTIVE,
873 + c->chan_base + BCM2835_DMA_CS);
874 +
875 + } else {
876 + vchan_cookie_complete(&c->desc->vd);
877 + bcm2835_dma_start_desc(c);
878 + }
879 + }
880 +
881 + spin_unlock_irqrestore(&c->vc.lock, flags);
882 +
883 + return IRQ_HANDLED;
884 +}
885 +
886 +static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan)
887 +{
888 + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
889 + int ret;
890 +
891 + dev_dbg(c->vc.chan.device->dev,
892 + "Allocating DMA channel %d\n", c->ch);
893 +
894 + ret = request_irq(c->irq_number,
895 + bcm2835_dma_callback, 0, "DMA IRQ", c);
896 +
897 + return ret;
898 +}
899 +
900 +static void bcm2835_dma_free_chan_resources(struct dma_chan *chan)
901 +{
902 + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
903 +
904 + vchan_free_chan_resources(&c->vc);
905 + free_irq(c->irq_number, c);
906 +
907 + dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch);
908 +}
909 +
910 +static size_t bcm2835_dma_desc_size(struct bcm2835_desc *d)
911 +{
912 + return d->size;
913 +}
914 +
915 +static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr)
916 +{
917 + unsigned int i;
918 + size_t size;
919 +
920 + for (size = i = 0; i < d->frames; i++) {
921 + struct bcm2835_dma_cb *control_block =
922 + &d->control_block_base[i];
923 + size_t this_size = control_block->length;
924 + dma_addr_t dma;
925 +
926 + if (d->dir == DMA_DEV_TO_MEM)
927 + dma = control_block->dst;
928 + else
929 + dma = control_block->src;
930 +
931 + if (size)
932 + size += this_size;
933 + else if (addr >= dma && addr < dma + this_size)
934 + size += dma + this_size - addr;
935 + }
936 +
937 + return size;
938 +}
939 +
940 +static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan,
941 + dma_cookie_t cookie, struct dma_tx_state *txstate)
942 +{
943 + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
944 + struct bcm2835_desc *d;
945 + struct virt_dma_desc *vd;
946 + enum dma_status ret;
947 + unsigned long flags;
948 + dma_addr_t pos;
949 +
950 + ret = dma_cookie_status(chan, cookie, txstate);
951 + if (ret == DMA_COMPLETE || !txstate)
952 + return ret;
953 +
954 + spin_lock_irqsave(&c->vc.lock, flags);
955 + vd = vchan_find_desc(&c->vc, cookie);
956 + if (vd) {
957 + txstate->residue =
958 + bcm2835_dma_desc_size(to_bcm2835_dma_desc(&vd->tx));
959 + } else if (c->desc && c->desc->vd.tx.cookie == cookie) {
960 + d = c->desc;
961 +
962 + if (d->dir == DMA_MEM_TO_DEV)
963 + pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD);
964 + else if (d->dir == DMA_DEV_TO_MEM)
965 + pos = readl(c->chan_base + BCM2835_DMA_DEST_AD);
966 + else
967 + pos = 0;
968 +
969 + txstate->residue = bcm2835_dma_desc_size_pos(d, pos);
970 + } else {
971 + txstate->residue = 0;
972 + }
973 +
974 + spin_unlock_irqrestore(&c->vc.lock, flags);
975 +
976 + return ret;
977 +}
978 +
979 +static void bcm2835_dma_issue_pending(struct dma_chan *chan)
980 +{
981 + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
982 + unsigned long flags;
983 +
984 + spin_lock_irqsave(&c->vc.lock, flags);
985 + if (vchan_issue_pending(&c->vc) && !c->desc)
986 + bcm2835_dma_start_desc(c);
987 +
988 + spin_unlock_irqrestore(&c->vc.lock, flags);
989 +}
990 +
991 +static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
992 + struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
993 + size_t period_len, enum dma_transfer_direction direction,
994 + unsigned long flags)
995 +{
996 + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
997 + enum dma_slave_buswidth dev_width;
998 + struct bcm2835_desc *d;
999 + dma_addr_t dev_addr;
1000 + unsigned int es, sync_type;
1001 + unsigned int frame, max_size;
1002 +
1003 + /* Grab configuration */
1004 + if (!is_slave_direction(direction)) {
1005 + dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
1006 + return NULL;
1007 + }
1008 +
1009 + if (direction == DMA_DEV_TO_MEM) {
1010 + dev_addr = c->cfg.src_addr;
1011 + dev_width = c->cfg.src_addr_width;
1012 + sync_type = BCM2835_DMA_S_DREQ;
1013 + } else {
1014 + dev_addr = c->cfg.dst_addr;
1015 + dev_width = c->cfg.dst_addr_width;
1016 + sync_type = BCM2835_DMA_D_DREQ;
1017 + }
1018 +
1019 + /* Bus width translates to the element size (ES) */
1020 + switch (dev_width) {
1021 + case DMA_SLAVE_BUSWIDTH_4_BYTES:
1022 + es = BCM2835_DMA_DATA_TYPE_S32;
1023 + break;
1024 + default:
1025 + return NULL;
1026 + }
1027 +
1028 + /* Now allocate and setup the descriptor. */
1029 + d = kzalloc(sizeof(*d), GFP_NOWAIT);
1030 + if (!d)
1031 + return NULL;
1032 +
1033 + d->dir = direction;
1034 +
1035 + if (c->ch >= 8) /* we have a LITE channel */
1036 + max_size = MAX_LITE_TRANSFER;
1037 + else
1038 + max_size = MAX_NORMAL_TRANSFER;
1039 + period_len = min(period_len, max_size);
1040 +
1041 + d->frames = (buf_len-1) / period_len + 1;
1042 +
1043 + /* Allocate memory for control blocks */
1044 + d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb);
1045 + d->control_block_base = dma_zalloc_coherent(chan->device->dev,
1046 + d->control_block_size, &d->control_block_base_phys,
1047 + GFP_NOWAIT);
1048 +
1049 + if (!d->control_block_base) {
1050 + kfree(d);
1051 + return NULL;
1052 + }
1053 +
1054 + /*
1055 + * Iterate over all frames, create a control block
1056 + * for each frame and link them together.
1057 + */
1058 + for (frame = 0; frame < d->frames; frame++) {
1059 + struct bcm2835_dma_cb *control_block =
1060 + &d->control_block_base[frame];
1061 +
1062 + /* Setup adresses */
1063 + if (d->dir == DMA_DEV_TO_MEM) {
1064 + control_block->info = BCM2835_DMA_D_INC;
1065 + control_block->src = dev_addr;
1066 + control_block->dst = buf_addr + frame * period_len;
1067 + } else {
1068 + control_block->info = BCM2835_DMA_S_INC;
1069 + control_block->src = buf_addr + frame * period_len;
1070 + control_block->dst = dev_addr;
1071 + }
1072 +
1073 + /* Enable interrupt */
1074 + control_block->info |= BCM2835_DMA_INT_EN;
1075 +
1076 + /* Setup synchronization */
1077 + if (sync_type != 0)
1078 + control_block->info |= sync_type;
1079 +
1080 + /* Setup DREQ channel */
1081 + if (c->cfg.slave_id != 0)
1082 + control_block->info |=
1083 + BCM2835_DMA_PER_MAP(c->cfg.slave_id);
1084 +
1085 + /* Length of a frame */
1086 + if (frame != d->frames-1)
1087 + control_block->length = period_len;
1088 + else
1089 + control_block->length = buf_len - (d->frames - 1) * period_len;
1090 +
1091 + d->size += control_block->length;
1092 +
1093 + /*
1094 + * Next block is the next frame.
1095 + * This function is called on cyclic DMA transfers.
1096 + * Therefore, wrap around at number of frames.
1097 + */
1098 + control_block->next = d->control_block_base_phys +
1099 + sizeof(struct bcm2835_dma_cb)
1100 + * ((frame + 1) % d->frames);
1101 + }
1102 +
1103 + c->cyclic = true;
1104 +
1105 + return vchan_tx_prep(&c->vc, &d->vd, flags);
1106 +}
1107 +
1108 +
1109 +static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg(
1110 + struct dma_chan *chan, struct scatterlist *sgl,
1111 + unsigned int sg_len, enum dma_transfer_direction direction,
1112 + unsigned long flags, void *context)
1113 +{
1114 + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
1115 + enum dma_slave_buswidth dev_width;
1116 + struct bcm2835_desc *d;
1117 + dma_addr_t dev_addr;
1118 + struct scatterlist *sgent;
1119 + unsigned int es, sync_type;
1120 + unsigned int i, j, splitct, max_size;
1121 +
1122 + if (!is_slave_direction(direction)) {
1123 + dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
1124 + return NULL;
1125 + }
1126 +
1127 + if (direction == DMA_DEV_TO_MEM) {
1128 + dev_addr = c->cfg.src_addr;
1129 + dev_width = c->cfg.src_addr_width;
1130 + sync_type = BCM2835_DMA_S_DREQ;
1131 + } else {
1132 + dev_addr = c->cfg.dst_addr;
1133 + dev_width = c->cfg.dst_addr_width;
1134 + sync_type = BCM2835_DMA_D_DREQ;
1135 + }
1136 +
1137 + /* Bus width translates to the element size (ES) */
1138 + switch (dev_width) {
1139 + case DMA_SLAVE_BUSWIDTH_4_BYTES:
1140 + es = BCM2835_DMA_DATA_TYPE_S32;
1141 + break;
1142 + default:
1143 + return NULL;
1144 + }
1145 +
1146 + /* Now allocate and setup the descriptor. */
1147 + d = kzalloc(sizeof(*d), GFP_NOWAIT);
1148 + if (!d)
1149 + return NULL;
1150 +
1151 + d->dir = direction;
1152 +
1153 + if (c->ch >= 8) /* we have a LITE channel */
1154 + max_size = MAX_LITE_TRANSFER;
1155 + else
1156 + max_size = MAX_NORMAL_TRANSFER;
1157 +
1158 + /* We store the length of the SG list in d->frames
1159 + taking care to account for splitting up transfers
1160 + too large for a LITE channel */
1161 +
1162 + d->frames = 0;
1163 + for_each_sg(sgl, sgent, sg_len, i) {
1164 + uint32_t len = sg_dma_len(sgent);
1165 + d->frames += 1 + len / max_size;
1166 + }
1167 +
1168 + /* Allocate memory for control blocks */
1169 + d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb);
1170 + d->control_block_base = dma_zalloc_coherent(chan->device->dev,
1171 + d->control_block_size, &d->control_block_base_phys,
1172 + GFP_NOWAIT);
1173 +
1174 + if (!d->control_block_base) {
1175 + kfree(d);
1176 + return NULL;
1177 + }
1178 +
1179 + /*
1180 + * Iterate over all SG entries, create a control block
1181 + * for each frame and link them together.
1182 + */
1183 +
1184 + /* we count the number of times an SG entry had to be splitct
1185 + as a result of using a LITE channel */
1186 + splitct = 0;
1187 +
1188 + for_each_sg(sgl, sgent, sg_len, i) {
1189 + dma_addr_t addr = sg_dma_address(sgent);
1190 + uint32_t len = sg_dma_len(sgent);
1191 +
1192 + for (j = 0; j < len; j += max_size) {
1193 + struct bcm2835_dma_cb *control_block =
1194 + &d->control_block_base[i+splitct];
1195 +
1196 + /* Setup adresses */
1197 + if (d->dir == DMA_DEV_TO_MEM) {
1198 + control_block->info = BCM2835_DMA_D_INC |
1199 + BCM2835_DMA_D_WIDTH | BCM2835_DMA_S_DREQ;
1200 + control_block->src = dev_addr;
1201 + control_block->dst = addr + (dma_addr_t)j;
1202 + } else {
1203 + control_block->info = BCM2835_DMA_S_INC |
1204 + BCM2835_DMA_S_WIDTH | BCM2835_DMA_D_DREQ;
1205 + control_block->src = addr + (dma_addr_t)j;
1206 + control_block->dst = dev_addr;
1207 + }
1208 +
1209 + /* Common part */
1210 + u32 waits = SDHCI_BCM_DMA_WAITS;
1211 + if ((dma_debug >> 0) & 0x1f)
1212 + waits = (dma_debug >> 0) & 0x1f;
1213 + control_block->info |= BCM2835_DMA_WAITS(waits);
1214 + control_block->info |= BCM2835_DMA_WAIT_RESP;
1215 +
1216 + /* Enable */
1217 + if (i == sg_len-1 && len-j <= max_size)
1218 + control_block->info |= BCM2835_DMA_INT_EN;
1219 +
1220 + /* Setup synchronization */
1221 + if (sync_type != 0)
1222 + control_block->info |= sync_type;
1223 +
1224 + /* Setup DREQ channel */
1225 + if (c->dreq != 0)
1226 + control_block->info |=
1227 + BCM2835_DMA_PER_MAP(c->dreq);
1228 +
1229 + /* Length of a frame */
1230 + control_block->length = min(len-j, max_size);
1231 + d->size += control_block->length;
1232 +
1233 + /*
1234 + * Next block is the next frame.
1235 + */
1236 + if (i < sg_len-1 || len-j > max_size) {
1237 + /* next block is the next frame. */
1238 + control_block->next = d->control_block_base_phys +
1239 + sizeof(struct bcm2835_dma_cb) * (i + splitct + 1);
1240 + } else {
1241 + /* next block is empty. */
1242 + control_block->next = 0;
1243 + }
1244 +
1245 + if (len-j > max_size)
1246 + splitct++;
1247 + }
1248 + }
1249 +
1250 + c->cyclic = false;
1251 +
1252 + return vchan_tx_prep(&c->vc, &d->vd, flags);
1253 +}
1254 +
1255 +static int bcm2835_dma_slave_config(struct dma_chan *chan,
1256 + struct dma_slave_config *cfg)
1257 +{
1258 + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
1259 + if ((cfg->direction == DMA_DEV_TO_MEM &&
1260 + cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
1261 + (cfg->direction == DMA_MEM_TO_DEV &&
1262 + cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
1263 + !is_slave_direction(cfg->direction)) {
1264 + return -EINVAL;
1265 + }
1266 +
1267 + c->cfg = *cfg;
1268 + if (!c->dreq)
1269 + c->dreq = cfg->slave_id;
1270 +
1271 + return 0;
1272 +}
1273 +
1274 +static int bcm2835_dma_terminate_all(struct dma_chan *chan)
1275 +{
1276 + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
1277 + struct bcm2835_dmadev *d = to_bcm2835_dma_dev(c->vc.chan.device);
1278 + unsigned long flags;
1279 + int timeout = 10000;
1280 + LIST_HEAD(head);
1281 +
1282 + spin_lock_irqsave(&c->vc.lock, flags);
1283 +
1284 + /* Prevent this channel being scheduled */
1285 + spin_lock(&d->lock);
1286 + list_del_init(&c->node);
1287 + spin_unlock(&d->lock);
1288 +
1289 + /*
1290 + * Stop DMA activity: we assume the callback will not be called
1291 + * after bcm_dma_abort() returns (even if it does, it will see
1292 + * c->desc is NULL and exit.)
1293 + */
1294 + if (c->desc) {
1295 + c->desc = NULL;
1296 + bcm2835_dma_abort(c->chan_base);
1297 +
1298 + /* Wait for stopping */
1299 + while (--timeout) {
1300 + if (!(readl(c->chan_base + BCM2835_DMA_CS) &
1301 + BCM2835_DMA_ACTIVE))
1302 + break;
1303 +
1304 + cpu_relax();
1305 + }
1306 +
1307 + if (!timeout)
1308 + dev_err(d->ddev.dev, "DMA transfer could not be terminated\n");
1309 + }
1310 +
1311 + vchan_get_all_descriptors(&c->vc, &head);
1312 + spin_unlock_irqrestore(&c->vc.lock, flags);
1313 + vchan_dma_desc_free_list(&c->vc, &head);
1314 +
1315 + return 0;
1316 +}
1317 +
1318 +#ifndef CONFIG_DMA_BCM2708_LEGACY
1319 +static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id, int irq)
1320 +{
1321 + struct bcm2835_chan *c;
1322 +
1323 + c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL);
1324 + if (!c)
1325 + return -ENOMEM;
1326 +
1327 + c->vc.desc_free = bcm2835_dma_desc_free;
1328 + vchan_init(&c->vc, &d->ddev);
1329 + INIT_LIST_HEAD(&c->node);
1330 +
1331 + c->chan_base = BCM2835_DMA_CHANIO(d->base, chan_id);
1332 + c->ch = chan_id;
1333 + c->irq_number = irq;
1334 +
1335 + return 0;
1336 +}
1337 +#endif
1338 +
1339 +static int bcm2708_dma_chan_init(struct bcm2835_dmadev *d,
1340 + void __iomem *chan_base, int chan_id, int irq)
1341 +{
1342 + struct bcm2835_chan *c;
1343 +
1344 + c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL);
1345 + if (!c)
1346 + return -ENOMEM;
1347 +
1348 + c->vc.desc_free = bcm2835_dma_desc_free;
1349 + vchan_init(&c->vc, &d->ddev);
1350 + INIT_LIST_HEAD(&c->node);
1351 +
1352 + c->chan_base = chan_base;
1353 + c->ch = chan_id;
1354 + c->irq_number = irq;
1355 +
1356 + return 0;
1357 +}
1358 +
1359 +
1360 +static void bcm2835_dma_free(struct bcm2835_dmadev *od)
1361 +{
1362 + struct bcm2835_chan *c, *next;
1363 +
1364 + list_for_each_entry_safe(c, next, &od->ddev.channels,
1365 + vc.chan.device_node) {
1366 + list_del(&c->vc.chan.device_node);
1367 + tasklet_kill(&c->vc.task);
1368 + }
1369 +}
1370 +
1371 +static const struct of_device_id bcm2835_dma_of_match[] = {
1372 + { .compatible = "brcm,bcm2835-dma", },
1373 + {},
1374 +};
1375 +MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match);
1376 +
1377 +static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *spec,
1378 + struct of_dma *ofdma)
1379 +{
1380 + struct bcm2835_dmadev *d = ofdma->of_dma_data;
1381 + struct dma_chan *chan;
1382 +
1383 + chan = dma_get_any_slave_channel(&d->ddev);
1384 + if (!chan)
1385 + return NULL;
1386 +
1387 + /* Set DREQ from param */
1388 + to_bcm2835_dma_chan(chan)->dreq = spec->args[0];
1389 +
1390 + return chan;
1391 +}
1392 +
1393 +static int bcm2835_dma_probe(struct platform_device *pdev)
1394 +{
1395 + struct bcm2835_dmadev *od;
1396 +#ifndef CONFIG_DMA_BCM2708_LEGACY
1397 + struct resource *res;
1398 + void __iomem *base;
1399 + uint32_t chans_available;
1400 +#endif
1401 + int rc;
1402 + int i;
1403 + int irq;
1404 +
1405 +
1406 + if (!pdev->dev.dma_mask)
1407 + pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
1408 +
1409 +#ifdef CONFIG_DMA_BCM2708_LEGACY
1410 +
1411 + rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1412 + if (rc)
1413 + return rc;
1414 + dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1415 +
1416 +
1417 + od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
1418 + if (!od)
1419 + return -ENOMEM;
1420 +
1421 + rc = bcm_dmaman_probe(pdev);
1422 + if (rc)
1423 + return rc;
1424 +
1425 + pdev->dev.dma_parms = &od->dma_parms;
1426 + dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
1427 +
1428 +
1429 + dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
1430 + dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask);
1431 + dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
1432 + od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources;
1433 + od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources;
1434 + od->ddev.device_tx_status = bcm2835_dma_tx_status;
1435 + od->ddev.device_issue_pending = bcm2835_dma_issue_pending;
1436 + od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic;
1437 + od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg;
1438 + od->ddev.device_terminate_all = bcm2835_dma_terminate_all;
1439 + od->ddev.device_config = bcm2835_dma_slave_config;
1440 + od->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1441 + od->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1442 + od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1443 + od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1444 + od->ddev.dev = &pdev->dev;
1445 + INIT_LIST_HEAD(&od->ddev.channels);
1446 + spin_lock_init(&od->lock);
1447 +
1448 + platform_set_drvdata(pdev, od);
1449 +
1450 + for (i = 0; i < 5; i++) {
1451 + void __iomem *chan_base;
1452 + int chan_id;
1453 +
1454 + chan_id = bcm_dma_chan_alloc(BCM_DMA_FEATURE_LITE,
1455 + &chan_base,
1456 + &irq);
1457 +
1458 + if (chan_id < 0)
1459 + break;
1460 +
1461 + rc = bcm2708_dma_chan_init(od, chan_base, chan_id, irq);
1462 + if (rc)
1463 + goto err_no_dma;
1464 + }
1465 +
1466 + if (pdev->dev.of_node) {
1467 + rc = of_dma_controller_register(pdev->dev.of_node,
1468 + bcm2835_dma_xlate, od);
1469 + if (rc) {
1470 + dev_err(&pdev->dev,
1471 + "Failed to register DMA controller\n");
1472 + goto err_no_dma;
1473 + }
1474 + }
1475 +
1476 +#else
1477 + rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1478 + if (rc)
1479 + return rc;
1480 +
1481 +
1482 + od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
1483 + if (!od)
1484 + return -ENOMEM;
1485 +
1486 + pdev->dev.dma_parms = &od->dma_parms;
1487 + dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
1488 +
1489 +
1490 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1491 + base = devm_ioremap_resource(&pdev->dev, res);
1492 + if (IS_ERR(base))
1493 + return PTR_ERR(base);
1494 +
1495 + od->base = base;
1496 +
1497 +
1498 + dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
1499 + dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask);
1500 + dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
1501 + od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources;
1502 + od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources;
1503 + od->ddev.device_tx_status = bcm2835_dma_tx_status;
1504 + od->ddev.device_issue_pending = bcm2835_dma_issue_pending;
1505 + od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic;
1506 + od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg;
1507 + od->ddev.device_terminate_all = bcm2835_dma_terminate_all;
1508 + od->ddev.device_config = bcm2835_dma_slave_config;
1509 + od->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1510 + od->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1511 + od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1512 + od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1513 + od->ddev.dev = &pdev->dev;
1514 + INIT_LIST_HEAD(&od->ddev.channels);
1515 + spin_lock_init(&od->lock);
1516 +
1517 + platform_set_drvdata(pdev, od);
1518 +
1519 +
1520 + /* Request DMA channel mask from device tree */
1521 + if (of_property_read_u32(pdev->dev.of_node,
1522 + "brcm,dma-channel-mask",
1523 + &chans_available)) {
1524 + dev_err(&pdev->dev, "Failed to get channel mask\n");
1525 + rc = -EINVAL;
1526 + goto err_no_dma;
1527 + }
1528 +
1529 +
1530 + /*
1531 + * Do not use the FIQ and BULK channels,
1532 + * because they are used by the GPU.
1533 + */
1534 + chans_available &= ~(BCM2835_DMA_FIQ_MASK | BCM2835_DMA_BULK_MASK);
1535 +
1536 +
1537 + for (i = 0; i < pdev->num_resources; i++) {
1538 + irq = platform_get_irq(pdev, i);
1539 + if (irq < 0)
1540 + break;
1541 +
1542 + if (chans_available & (1 << i)) {
1543 + rc = bcm2835_dma_chan_init(od, i, irq);
1544 + if (rc)
1545 + goto err_no_dma;
1546 + }
1547 + }
1548 +
1549 + dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i);
1550 +
1551 + /* Device-tree DMA controller registration */
1552 + rc = of_dma_controller_register(pdev->dev.of_node,
1553 + bcm2835_dma_xlate, od);
1554 + if (rc) {
1555 + dev_err(&pdev->dev, "Failed to register DMA controller\n");
1556 + goto err_no_dma;
1557 + }
1558 +#endif
1559 +
1560 + rc = dma_async_device_register(&od->ddev);
1561 + if (rc) {
1562 + dev_err(&pdev->dev,
1563 + "Failed to register slave DMA engine device: %d\n", rc);
1564 + goto err_no_dma;
1565 + }
1566 +
1567 + dev_info(&pdev->dev, "Load BCM2835 DMA engine driver\n");
1568 + dev_info(&pdev->dev, "dma_debug:%x\n", dma_debug);
1569 +
1570 + return 0;
1571 +
1572 +err_no_dma:
1573 + bcm2835_dma_free(od);
1574 + return rc;
1575 +}
1576 +
1577 +static int bcm2835_dma_remove(struct platform_device *pdev)
1578 +{
1579 + struct bcm2835_dmadev *od = platform_get_drvdata(pdev);
1580 +
1581 + dma_async_device_unregister(&od->ddev);
1582 + bcm2835_dma_free(od);
1583 + bcm_dmaman_remove(pdev);
1584 +
1585 + return 0;
1586 +}
1587 +
1588 +static struct platform_driver bcm2835_dma_driver = {
1589 + .probe = bcm2835_dma_probe,
1590 + .remove = bcm2835_dma_remove,
1591 + .driver = {
1592 + .name = "bcm2708-dmaengine",
1593 + .owner = THIS_MODULE,
1594 + .of_match_table = of_match_ptr(bcm2835_dma_of_match),
1595 + },
1596 +};
1597 +
1598 +static int bcm2835_init(void)
1599 +{
1600 + return platform_driver_register(&bcm2835_dma_driver);
1601 +}
1602 +
1603 +static void bcm2835_exit(void)
1604 +{
1605 + platform_driver_unregister(&bcm2835_dma_driver);
1606 +}
1607 +
1608 +/*
1609 + * Load after serial driver (arch_initcall) so we see the messages if it fails,
1610 + * but before drivers (module_init) that need a DMA channel.
1611 + */
1612 +subsys_initcall(bcm2835_init);
1613 +module_exit(bcm2835_exit);
1614 +
1615 +module_param(dma_debug, uint, 0644);
1616 +#ifdef CONFIG_DMA_BCM2708_LEGACY
1617 +/* Keep backward compatibility: dma.dmachans= */
1618 +#undef MODULE_PARAM_PREFIX
1619 +#define MODULE_PARAM_PREFIX "dma."
1620 +module_param(dmachans, int, 0644);
1621 +#endif
1622 +MODULE_ALIAS("platform:bcm2835-dma");
1623 +MODULE_DESCRIPTION("BCM2835 DMA engine driver");
1624 +MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
1625 +MODULE_AUTHOR("Gellert Weisz <gellert@raspberrypi.org>");
1626 +MODULE_LICENSE("GPL v2");
1627 --- /dev/null
1628 +++ b/include/linux/platform_data/dma-bcm2708.h
1629 @@ -0,0 +1,127 @@
1630 +/*
1631 + * Copyright (C) 2010 Broadcom
1632 + *
1633 + * This program is free software; you can redistribute it and/or modify
1634 + * it under the terms of the GNU General Public License version 2 as
1635 + * published by the Free Software Foundation.
1636 + */
1637 +
1638 +#ifndef _PLAT_BCM2708_DMA_H
1639 +#define _PLAT_BCM2708_DMA_H
1640 +
1641 +/* DMA CS Control and Status bits */
1642 +#define BCM2708_DMA_ACTIVE BIT(0)
1643 +#define BCM2708_DMA_INT BIT(2)
1644 +#define BCM2708_DMA_ISPAUSED BIT(4) /* Pause requested or not active */
1645 +#define BCM2708_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */
1646 +#define BCM2708_DMA_ERR BIT(8)
1647 +#define BCM2708_DMA_ABORT BIT(30) /* stop current CB, go to next, WO */
1648 +#define BCM2708_DMA_RESET BIT(31) /* WO, self clearing */
1649 +
1650 +/* DMA control block "info" field bits */
1651 +#define BCM2708_DMA_INT_EN BIT(0)
1652 +#define BCM2708_DMA_TDMODE BIT(1)
1653 +#define BCM2708_DMA_WAIT_RESP BIT(3)
1654 +#define BCM2708_DMA_D_INC BIT(4)
1655 +#define BCM2708_DMA_D_WIDTH BIT(5)
1656 +#define BCM2708_DMA_D_DREQ BIT(6)
1657 +#define BCM2708_DMA_S_INC BIT(8)
1658 +#define BCM2708_DMA_S_WIDTH BIT(9)
1659 +#define BCM2708_DMA_S_DREQ BIT(10)
1660 +
1661 +#define BCM2708_DMA_BURST(x) (((x) & 0xf) << 12)
1662 +#define BCM2708_DMA_PER_MAP(x) ((x) << 16)
1663 +#define BCM2708_DMA_WAITS(x) (((x) & 0x1f) << 21)
1664 +
1665 +#define BCM2708_DMA_DREQ_EMMC 11
1666 +#define BCM2708_DMA_DREQ_SDHOST 13
1667 +
1668 +#define BCM2708_DMA_CS 0x00 /* Control and Status */
1669 +#define BCM2708_DMA_ADDR 0x04
1670 +/* the current control block appears in the following registers - read only */
1671 +#define BCM2708_DMA_INFO 0x08
1672 +#define BCM2708_DMA_SOURCE_AD 0x0c
1673 +#define BCM2708_DMA_DEST_AD 0x10
1674 +#define BCM2708_DMA_NEXTCB 0x1C
1675 +#define BCM2708_DMA_DEBUG 0x20
1676 +
1677 +#define BCM2708_DMA4_CS (BCM2708_DMA_CHAN(4) + BCM2708_DMA_CS)
1678 +#define BCM2708_DMA4_ADDR (BCM2708_DMA_CHAN(4) + BCM2708_DMA_ADDR)
1679 +
1680 +#define BCM2708_DMA_TDMODE_LEN(w, h) ((h) << 16 | (w))
1681 +
1682 +/* When listing features we can ask for when allocating DMA channels give
1683 + those with higher priority smaller ordinal numbers */
1684 +#define BCM_DMA_FEATURE_FAST_ORD 0
1685 +#define BCM_DMA_FEATURE_BULK_ORD 1
1686 +#define BCM_DMA_FEATURE_NORMAL_ORD 2
1687 +#define BCM_DMA_FEATURE_LITE_ORD 3
1688 +#define BCM_DMA_FEATURE_FAST BIT(BCM_DMA_FEATURE_FAST_ORD)
1689 +#define BCM_DMA_FEATURE_BULK BIT(BCM_DMA_FEATURE_BULK_ORD)
1690 +#define BCM_DMA_FEATURE_NORMAL BIT(BCM_DMA_FEATURE_NORMAL_ORD)
1691 +#define BCM_DMA_FEATURE_LITE BIT(BCM_DMA_FEATURE_LITE_ORD)
1692 +#define BCM_DMA_FEATURE_COUNT 4
1693 +
1694 +struct bcm2708_dma_cb {
1695 + unsigned long info;
1696 + unsigned long src;
1697 + unsigned long dst;
1698 + unsigned long length;
1699 + unsigned long stride;
1700 + unsigned long next;
1701 + unsigned long pad[2];
1702 +};
1703 +
1704 +struct scatterlist;
1705 +
1706 +#ifdef CONFIG_DMA_BCM2708_LEGACY
1707 +
1708 +int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len);
1709 +void bcm_dma_start(void __iomem *dma_chan_base, dma_addr_t control_block);
1710 +void bcm_dma_wait_idle(void __iomem *dma_chan_base);
1711 +bool bcm_dma_is_busy(void __iomem *dma_chan_base);
1712 +int bcm_dma_abort(void __iomem *dma_chan_base);
1713 +
1714 +/* return channel no or -ve error */
1715 +int bcm_dma_chan_alloc(unsigned preferred_feature_set,
1716 + void __iomem **out_dma_base, int *out_dma_irq);
1717 +int bcm_dma_chan_free(int channel);
1718 +
1719 +#else /* CONFIG_DMA_BCM2708_LEGACY */
1720 +
1721 +static inline int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr,
1722 + int sg_len)
1723 +{
1724 + return 0;
1725 +}
1726 +
1727 +static inline void bcm_dma_start(void __iomem *dma_chan_base,
1728 + dma_addr_t control_block) { }
1729 +
1730 +static inline void bcm_dma_wait_idle(void __iomem *dma_chan_base) { }
1731 +
1732 +static inline bool bcm_dma_is_busy(void __iomem *dma_chan_base)
1733 +{
1734 + return false;
1735 +}
1736 +
1737 +static inline int bcm_dma_abort(void __iomem *dma_chan_base)
1738 +{
1739 + return -EINVAL;
1740 +}
1741 +
1742 +static inline int bcm_dma_chan_alloc(unsigned preferred_feature_set,
1743 + void __iomem **out_dma_base,
1744 + int *out_dma_irq)
1745 +{
1746 + return -EINVAL;
1747 +}
1748 +
1749 +static inline int bcm_dma_chan_free(int channel)
1750 +{
1751 + return -EINVAL;
1752 +}
1753 +
1754 +#endif /* CONFIG_DMA_BCM2708_LEGACY */
1755 +
1756 +#endif /* _PLAT_BCM2708_DMA_H */
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