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[openwrt/openwrt.git] / target / linux / brcm2708 / patches-4.1 / 0034-ASoC-Add-support-for-BCM2708.patch
1 From 6fb867c30ac9a24482bcccd69c146d526c8e89ec Mon Sep 17 00:00:00 2001
2 From: Florian Meier <florian.meier@koalo.de>
3 Date: Fri, 22 Nov 2013 14:33:38 +0100
4 Subject: [PATCH 034/148] ASoC: Add support for BCM2708
5
6 This driver adds support for digital audio (I2S)
7 for the BCM2708 SoC that is used by the
8 Raspberry Pi. External audio codecs can be
9 connected to the Raspberry Pi via P5 header.
10
11 It relies on cyclic DMA engine support for BCM2708.
12
13 Signed-off-by: Florian Meier <florian.meier@koalo.de>
14
15 ASoC: BCM2708: Add 24 bit support
16
17 This adds 24 bit support to the I2S driver of the BCM2708.
18 Besides enabling the 24 bit flags, it includes two bug fixes:
19
20 MMAP is not supported. Claiming this leads to strange issues
21 when the format of driver and file do not match.
22
23 The datasheet states that the width extension bit should be set
24 for widths greater than 24, but greater or equal would be correct.
25 This follows from the definition of the width field.
26
27 Signed-off-by: Florian Meier <florian.meier@koalo.de>
28
29 bcm2708-i2s: Update bclk_ratio to more correct values
30
31 Move GPIO setup to hw_params.
32
33 This is used to stop the I2S driver from breaking
34 the GPIO setup for other uses of the PCM interface
35
36 Configure GPIOs for I2S based on revision/card settings
37
38 With RPi model B+, assignment of the I2S GPIO pins has changed.
39 This patch uses the board revision to auto-detect the GPIOs used
40 for I2S. It also allows sound card drivers to set the GPIOs that
41 should be used. This is especially important with the Compute
42 Module.
43
44 bcm2708-i2s: Avoid leak from iomap when accessing gpio
45
46 bcm2708: Eliminate i2s debugfs directory error
47
48 Qualify the two regmap ranges uses by bcm2708-i2s ('-i2s' and '-clk')
49 to avoid the name clash when registering debugfs entries.
50 ---
51 sound/soc/bcm/Kconfig | 11 +
52 sound/soc/bcm/Makefile | 4 +
53 sound/soc/bcm/bcm2708-i2s.c | 1009 +++++++++++++++++++++++++++++++++++++++++++
54 sound/soc/bcm/bcm2708-i2s.h | 35 ++
55 4 files changed, 1059 insertions(+)
56 create mode 100644 sound/soc/bcm/bcm2708-i2s.c
57 create mode 100644 sound/soc/bcm/bcm2708-i2s.h
58
59 --- a/sound/soc/bcm/Kconfig
60 +++ b/sound/soc/bcm/Kconfig
61 @@ -7,3 +7,14 @@ config SND_BCM2835_SOC_I2S
62 Say Y or M if you want to add support for codecs attached to
63 the BCM2835 I2S interface. You will also need
64 to select the audio interfaces to support below.
65 +
66 +config SND_BCM2708_SOC_I2S
67 + tristate "SoC Audio support for the Broadcom BCM2708 I2S module"
68 + depends on MACH_BCM2708 || MACH_BCM2709
69 + select REGMAP_MMIO
70 + select SND_SOC_DMAENGINE_PCM
71 + select SND_SOC_GENERIC_DMAENGINE_PCM
72 + help
73 + Say Y or M if you want to add support for codecs attached to
74 + the BCM2708 I2S interface. You will also need
75 + to select the audio interfaces to support below.
76 --- a/sound/soc/bcm/Makefile
77 +++ b/sound/soc/bcm/Makefile
78 @@ -3,3 +3,7 @@ snd-soc-bcm2835-i2s-objs := bcm2835-i2s.
79
80 obj-$(CONFIG_SND_BCM2835_SOC_I2S) += snd-soc-bcm2835-i2s.o
81
82 +# BCM2708 Platform Support
83 +snd-soc-bcm2708-i2s-objs := bcm2708-i2s.o
84 +
85 +obj-$(CONFIG_SND_BCM2708_SOC_I2S) += snd-soc-bcm2708-i2s.o
86 --- /dev/null
87 +++ b/sound/soc/bcm/bcm2708-i2s.c
88 @@ -0,0 +1,1009 @@
89 +/*
90 + * ALSA SoC I2S Audio Layer for Broadcom BCM2708 SoC
91 + *
92 + * Author: Florian Meier <florian.meier@koalo.de>
93 + * Copyright 2013
94 + *
95 + * Based on
96 + * Raspberry Pi PCM I2S ALSA Driver
97 + * Copyright (c) by Phil Poole 2013
98 + *
99 + * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
100 + * Vladimir Barinov, <vbarinov@embeddedalley.com>
101 + * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
102 + *
103 + * OMAP ALSA SoC DAI driver using McBSP port
104 + * Copyright (C) 2008 Nokia Corporation
105 + * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
106 + * Peter Ujfalusi <peter.ujfalusi@ti.com>
107 + *
108 + * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
109 + * Author: Timur Tabi <timur@freescale.com>
110 + * Copyright 2007-2010 Freescale Semiconductor, Inc.
111 + *
112 + * This program is free software; you can redistribute it and/or
113 + * modify it under the terms of the GNU General Public License
114 + * version 2 as published by the Free Software Foundation.
115 + *
116 + * This program is distributed in the hope that it will be useful, but
117 + * WITHOUT ANY WARRANTY; without even the implied warranty of
118 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
119 + * General Public License for more details.
120 + */
121 +
122 +#include "bcm2708-i2s.h"
123 +
124 +#include <linux/init.h>
125 +#include <linux/module.h>
126 +#include <linux/device.h>
127 +#include <linux/slab.h>
128 +#include <linux/delay.h>
129 +#include <linux/io.h>
130 +#include <linux/clk.h>
131 +#include <mach/gpio.h>
132 +
133 +#include <sound/core.h>
134 +#include <sound/pcm.h>
135 +#include <sound/pcm_params.h>
136 +#include <sound/initval.h>
137 +#include <sound/soc.h>
138 +#include <sound/dmaengine_pcm.h>
139 +
140 +#include <asm/system_info.h>
141 +
142 +/* Clock registers */
143 +#define BCM2708_CLK_PCMCTL_REG 0x00
144 +#define BCM2708_CLK_PCMDIV_REG 0x04
145 +
146 +/* Clock register settings */
147 +#define BCM2708_CLK_PASSWD (0x5a000000)
148 +#define BCM2708_CLK_PASSWD_MASK (0xff000000)
149 +#define BCM2708_CLK_MASH(v) ((v) << 9)
150 +#define BCM2708_CLK_FLIP BIT(8)
151 +#define BCM2708_CLK_BUSY BIT(7)
152 +#define BCM2708_CLK_KILL BIT(5)
153 +#define BCM2708_CLK_ENAB BIT(4)
154 +#define BCM2708_CLK_SRC(v) (v)
155 +
156 +#define BCM2708_CLK_SHIFT (12)
157 +#define BCM2708_CLK_DIVI(v) ((v) << BCM2708_CLK_SHIFT)
158 +#define BCM2708_CLK_DIVF(v) (v)
159 +#define BCM2708_CLK_DIVF_MASK (0xFFF)
160 +
161 +enum {
162 + BCM2708_CLK_MASH_0 = 0,
163 + BCM2708_CLK_MASH_1,
164 + BCM2708_CLK_MASH_2,
165 + BCM2708_CLK_MASH_3,
166 +};
167 +
168 +enum {
169 + BCM2708_CLK_SRC_GND = 0,
170 + BCM2708_CLK_SRC_OSC,
171 + BCM2708_CLK_SRC_DBG0,
172 + BCM2708_CLK_SRC_DBG1,
173 + BCM2708_CLK_SRC_PLLA,
174 + BCM2708_CLK_SRC_PLLC,
175 + BCM2708_CLK_SRC_PLLD,
176 + BCM2708_CLK_SRC_HDMI,
177 +};
178 +
179 +/* Most clocks are not useable (freq = 0) */
180 +static const unsigned int bcm2708_clk_freq[BCM2708_CLK_SRC_HDMI+1] = {
181 + [BCM2708_CLK_SRC_GND] = 0,
182 + [BCM2708_CLK_SRC_OSC] = 19200000,
183 + [BCM2708_CLK_SRC_DBG0] = 0,
184 + [BCM2708_CLK_SRC_DBG1] = 0,
185 + [BCM2708_CLK_SRC_PLLA] = 0,
186 + [BCM2708_CLK_SRC_PLLC] = 0,
187 + [BCM2708_CLK_SRC_PLLD] = 500000000,
188 + [BCM2708_CLK_SRC_HDMI] = 0,
189 +};
190 +
191 +/* I2S registers */
192 +#define BCM2708_I2S_CS_A_REG 0x00
193 +#define BCM2708_I2S_FIFO_A_REG 0x04
194 +#define BCM2708_I2S_MODE_A_REG 0x08
195 +#define BCM2708_I2S_RXC_A_REG 0x0c
196 +#define BCM2708_I2S_TXC_A_REG 0x10
197 +#define BCM2708_I2S_DREQ_A_REG 0x14
198 +#define BCM2708_I2S_INTEN_A_REG 0x18
199 +#define BCM2708_I2S_INTSTC_A_REG 0x1c
200 +#define BCM2708_I2S_GRAY_REG 0x20
201 +
202 +/* I2S register settings */
203 +#define BCM2708_I2S_STBY BIT(25)
204 +#define BCM2708_I2S_SYNC BIT(24)
205 +#define BCM2708_I2S_RXSEX BIT(23)
206 +#define BCM2708_I2S_RXF BIT(22)
207 +#define BCM2708_I2S_TXE BIT(21)
208 +#define BCM2708_I2S_RXD BIT(20)
209 +#define BCM2708_I2S_TXD BIT(19)
210 +#define BCM2708_I2S_RXR BIT(18)
211 +#define BCM2708_I2S_TXW BIT(17)
212 +#define BCM2708_I2S_CS_RXERR BIT(16)
213 +#define BCM2708_I2S_CS_TXERR BIT(15)
214 +#define BCM2708_I2S_RXSYNC BIT(14)
215 +#define BCM2708_I2S_TXSYNC BIT(13)
216 +#define BCM2708_I2S_DMAEN BIT(9)
217 +#define BCM2708_I2S_RXTHR(v) ((v) << 7)
218 +#define BCM2708_I2S_TXTHR(v) ((v) << 5)
219 +#define BCM2708_I2S_RXCLR BIT(4)
220 +#define BCM2708_I2S_TXCLR BIT(3)
221 +#define BCM2708_I2S_TXON BIT(2)
222 +#define BCM2708_I2S_RXON BIT(1)
223 +#define BCM2708_I2S_EN (1)
224 +
225 +#define BCM2708_I2S_CLKDIS BIT(28)
226 +#define BCM2708_I2S_PDMN BIT(27)
227 +#define BCM2708_I2S_PDME BIT(26)
228 +#define BCM2708_I2S_FRXP BIT(25)
229 +#define BCM2708_I2S_FTXP BIT(24)
230 +#define BCM2708_I2S_CLKM BIT(23)
231 +#define BCM2708_I2S_CLKI BIT(22)
232 +#define BCM2708_I2S_FSM BIT(21)
233 +#define BCM2708_I2S_FSI BIT(20)
234 +#define BCM2708_I2S_FLEN(v) ((v) << 10)
235 +#define BCM2708_I2S_FSLEN(v) (v)
236 +
237 +#define BCM2708_I2S_CHWEX BIT(15)
238 +#define BCM2708_I2S_CHEN BIT(14)
239 +#define BCM2708_I2S_CHPOS(v) ((v) << 4)
240 +#define BCM2708_I2S_CHWID(v) (v)
241 +#define BCM2708_I2S_CH1(v) ((v) << 16)
242 +#define BCM2708_I2S_CH2(v) (v)
243 +
244 +#define BCM2708_I2S_TX_PANIC(v) ((v) << 24)
245 +#define BCM2708_I2S_RX_PANIC(v) ((v) << 16)
246 +#define BCM2708_I2S_TX(v) ((v) << 8)
247 +#define BCM2708_I2S_RX(v) (v)
248 +
249 +#define BCM2708_I2S_INT_RXERR BIT(3)
250 +#define BCM2708_I2S_INT_TXERR BIT(2)
251 +#define BCM2708_I2S_INT_RXR BIT(1)
252 +#define BCM2708_I2S_INT_TXW BIT(0)
253 +
254 +/* I2S DMA interface */
255 +#define BCM2708_I2S_FIFO_PHYSICAL_ADDR 0x7E203004
256 +#define BCM2708_DMA_DREQ_PCM_TX 2
257 +#define BCM2708_DMA_DREQ_PCM_RX 3
258 +
259 +/* I2S pin configuration */
260 +static int bcm2708_i2s_gpio=BCM2708_I2S_GPIO_AUTO;
261 +
262 +/* General device struct */
263 +struct bcm2708_i2s_dev {
264 + struct device *dev;
265 + struct snd_dmaengine_dai_dma_data dma_data[2];
266 + unsigned int fmt;
267 + unsigned int bclk_ratio;
268 +
269 + struct regmap *i2s_regmap;
270 + struct regmap *clk_regmap;
271 +};
272 +
273 +void bcm2708_i2s_set_gpio(int gpio) {
274 + bcm2708_i2s_gpio=gpio;
275 +}
276 +EXPORT_SYMBOL(bcm2708_i2s_set_gpio);
277 +
278 +
279 +static void bcm2708_i2s_start_clock(struct bcm2708_i2s_dev *dev)
280 +{
281 + /* Start the clock if in master mode */
282 + unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
283 +
284 + switch (master) {
285 + case SND_SOC_DAIFMT_CBS_CFS:
286 + case SND_SOC_DAIFMT_CBS_CFM:
287 + regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
288 + BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB,
289 + BCM2708_CLK_PASSWD | BCM2708_CLK_ENAB);
290 + break;
291 + default:
292 + break;
293 + }
294 +}
295 +
296 +static void bcm2708_i2s_stop_clock(struct bcm2708_i2s_dev *dev)
297 +{
298 + uint32_t clkreg;
299 + int timeout = 1000;
300 +
301 + /* Stop clock */
302 + regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
303 + BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB,
304 + BCM2708_CLK_PASSWD);
305 +
306 + /* Wait for the BUSY flag going down */
307 + while (--timeout) {
308 + regmap_read(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, &clkreg);
309 + if (!(clkreg & BCM2708_CLK_BUSY))
310 + break;
311 + }
312 +
313 + if (!timeout) {
314 + /* KILL the clock */
315 + dev_err(dev->dev, "I2S clock didn't stop. Kill the clock!\n");
316 + regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
317 + BCM2708_CLK_KILL | BCM2708_CLK_PASSWD_MASK,
318 + BCM2708_CLK_KILL | BCM2708_CLK_PASSWD);
319 + }
320 +}
321 +
322 +static void bcm2708_i2s_clear_fifos(struct bcm2708_i2s_dev *dev,
323 + bool tx, bool rx)
324 +{
325 + int timeout = 1000;
326 + uint32_t syncval;
327 + uint32_t csreg;
328 + uint32_t i2s_active_state;
329 + uint32_t clkreg;
330 + uint32_t clk_active_state;
331 + uint32_t off;
332 + uint32_t clr;
333 +
334 + off = tx ? BCM2708_I2S_TXON : 0;
335 + off |= rx ? BCM2708_I2S_RXON : 0;
336 +
337 + clr = tx ? BCM2708_I2S_TXCLR : 0;
338 + clr |= rx ? BCM2708_I2S_RXCLR : 0;
339 +
340 + /* Backup the current state */
341 + regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg);
342 + i2s_active_state = csreg & (BCM2708_I2S_RXON | BCM2708_I2S_TXON);
343 +
344 + regmap_read(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, &clkreg);
345 + clk_active_state = clkreg & BCM2708_CLK_ENAB;
346 +
347 + /* Start clock if not running */
348 + if (!clk_active_state) {
349 + regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
350 + BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB,
351 + BCM2708_CLK_PASSWD | BCM2708_CLK_ENAB);
352 + }
353 +
354 + /* Stop I2S module */
355 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, off, 0);
356 +
357 + /*
358 + * Clear the FIFOs
359 + * Requires at least 2 PCM clock cycles to take effect
360 + */
361 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, clr, clr);
362 +
363 + /* Wait for 2 PCM clock cycles */
364 +
365 + /*
366 + * Toggle the SYNC flag. After 2 PCM clock cycles it can be read back
367 + * FIXME: This does not seem to work for slave mode!
368 + */
369 + regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &syncval);
370 + syncval &= BCM2708_I2S_SYNC;
371 +
372 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
373 + BCM2708_I2S_SYNC, ~syncval);
374 +
375 + /* Wait for the SYNC flag changing it's state */
376 + while (--timeout) {
377 + regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg);
378 + if ((csreg & BCM2708_I2S_SYNC) != syncval)
379 + break;
380 + }
381 +
382 + if (!timeout)
383 + dev_err(dev->dev, "I2S SYNC error!\n");
384 +
385 + /* Stop clock if it was not running before */
386 + if (!clk_active_state)
387 + bcm2708_i2s_stop_clock(dev);
388 +
389 + /* Restore I2S state */
390 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
391 + BCM2708_I2S_RXON | BCM2708_I2S_TXON, i2s_active_state);
392 +}
393 +
394 +static int bcm2708_i2s_set_dai_fmt(struct snd_soc_dai *dai,
395 + unsigned int fmt)
396 +{
397 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
398 + dev->fmt = fmt;
399 + return 0;
400 +}
401 +
402 +static int bcm2708_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai,
403 + unsigned int ratio)
404 +{
405 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
406 + dev->bclk_ratio = ratio;
407 + return 0;
408 +}
409 +
410 +
411 +static int bcm2708_i2s_set_function(unsigned offset, int function)
412 +{
413 + #define GPIOFSEL(x) (0x00+(x)*4)
414 + void __iomem *gpio = __io_address(GPIO_BASE);
415 + unsigned alt = function <= 3 ? function + 4: function == 4 ? 3 : 2;
416 + unsigned gpiodir;
417 + unsigned gpio_bank = offset / 10;
418 + unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3;
419 +
420 + if (offset >= BCM2708_NR_GPIOS)
421 + return -EINVAL;
422 +
423 + gpiodir = readl(gpio + GPIOFSEL(gpio_bank));
424 + gpiodir &= ~(7 << gpio_field_offset);
425 + gpiodir |= alt << gpio_field_offset;
426 + writel(gpiodir, gpio + GPIOFSEL(gpio_bank));
427 + return 0;
428 +}
429 +
430 +static void bcm2708_i2s_setup_gpio(void)
431 +{
432 + /*
433 + * This is the common way to handle the GPIO pins for
434 + * the Raspberry Pi.
435 + * TODO Better way would be to handle
436 + * this in the device tree!
437 + */
438 + int pin,pinconfig,startpin,alt;
439 +
440 + /* SPI is on different GPIOs on different boards */
441 + /* for Raspberry Pi B+, this is pin GPIO18-21, for original on 28-31 */
442 + if (bcm2708_i2s_gpio==BCM2708_I2S_GPIO_AUTO) {
443 + if ((system_rev & 0xffffff) >= 0x10) {
444 + /* Model B+ */
445 + pinconfig=BCM2708_I2S_GPIO_PIN18;
446 + } else {
447 + /* original */
448 + pinconfig=BCM2708_I2S_GPIO_PIN28;
449 + }
450 + } else {
451 + pinconfig=bcm2708_i2s_gpio;
452 + }
453 +
454 + if (pinconfig==BCM2708_I2S_GPIO_PIN18) {
455 + startpin=18;
456 + alt=BCM2708_I2S_GPIO_PIN18_ALT;
457 + } else if (pinconfig==BCM2708_I2S_GPIO_PIN28) {
458 + startpin=28;
459 + alt=BCM2708_I2S_GPIO_PIN28_ALT;
460 + } else {
461 + printk(KERN_INFO "Can't configure I2S GPIOs, unknown pin mode for I2S: %i\n",pinconfig);
462 + return;
463 + }
464 +
465 + /* configure I2S pins to correct ALT mode */
466 + for (pin = startpin; pin <= startpin+3; pin++) {
467 + bcm2708_i2s_set_function(pin, alt);
468 + }
469 +}
470 +
471 +static int bcm2708_i2s_hw_params(struct snd_pcm_substream *substream,
472 + struct snd_pcm_hw_params *params,
473 + struct snd_soc_dai *dai)
474 +{
475 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
476 +
477 + unsigned int sampling_rate = params_rate(params);
478 + unsigned int data_length, data_delay, bclk_ratio;
479 + unsigned int ch1pos, ch2pos, mode, format;
480 + unsigned int mash = BCM2708_CLK_MASH_1;
481 + unsigned int divi, divf, target_frequency;
482 + int clk_src = -1;
483 + unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
484 + bool bit_master = (master == SND_SOC_DAIFMT_CBS_CFS
485 + || master == SND_SOC_DAIFMT_CBS_CFM);
486 +
487 + bool frame_master = (master == SND_SOC_DAIFMT_CBS_CFS
488 + || master == SND_SOC_DAIFMT_CBM_CFS);
489 + uint32_t csreg;
490 +
491 + /*
492 + * If a stream is already enabled,
493 + * the registers are already set properly.
494 + */
495 + regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg);
496 +
497 + if (csreg & (BCM2708_I2S_TXON | BCM2708_I2S_RXON))
498 + return 0;
499 +
500 +
501 + bcm2708_i2s_setup_gpio();
502 +
503 + /*
504 + * Adjust the data length according to the format.
505 + * We prefill the half frame length with an integer
506 + * divider of 2400 as explained at the clock settings.
507 + * Maybe it is overwritten there, if the Integer mode
508 + * does not apply.
509 + */
510 + switch (params_format(params)) {
511 + case SNDRV_PCM_FORMAT_S16_LE:
512 + data_length = 16;
513 + bclk_ratio = 50;
514 + break;
515 + case SNDRV_PCM_FORMAT_S24_LE:
516 + data_length = 24;
517 + bclk_ratio = 50;
518 + break;
519 + case SNDRV_PCM_FORMAT_S32_LE:
520 + data_length = 32;
521 + bclk_ratio = 100;
522 + break;
523 + default:
524 + return -EINVAL;
525 + }
526 +
527 + /* If bclk_ratio already set, use that one. */
528 + if (dev->bclk_ratio)
529 + bclk_ratio = dev->bclk_ratio;
530 +
531 + /*
532 + * Clock Settings
533 + *
534 + * The target frequency of the bit clock is
535 + * sampling rate * frame length
536 + *
537 + * Integer mode:
538 + * Sampling rates that are multiples of 8000 kHz
539 + * can be driven by the oscillator of 19.2 MHz
540 + * with an integer divider as long as the frame length
541 + * is an integer divider of 19200000/8000=2400 as set up above.
542 + * This is no longer possible if the sampling rate
543 + * is too high (e.g. 192 kHz), because the oscillator is too slow.
544 + *
545 + * MASH mode:
546 + * For all other sampling rates, it is not possible to
547 + * have an integer divider. Approximate the clock
548 + * with the MASH module that induces a slight frequency
549 + * variance. To minimize that it is best to have the fastest
550 + * clock here. That is PLLD with 500 MHz.
551 + */
552 + target_frequency = sampling_rate * bclk_ratio;
553 + clk_src = BCM2708_CLK_SRC_OSC;
554 + mash = BCM2708_CLK_MASH_0;
555 +
556 + if (bcm2708_clk_freq[clk_src] % target_frequency == 0
557 + && bit_master && frame_master) {
558 + divi = bcm2708_clk_freq[clk_src] / target_frequency;
559 + divf = 0;
560 + } else {
561 + uint64_t dividend;
562 +
563 + if (!dev->bclk_ratio) {
564 + /*
565 + * Overwrite bclk_ratio, because the
566 + * above trick is not needed or can
567 + * not be used.
568 + */
569 + bclk_ratio = 2 * data_length;
570 + }
571 +
572 + target_frequency = sampling_rate * bclk_ratio;
573 +
574 + clk_src = BCM2708_CLK_SRC_PLLD;
575 + mash = BCM2708_CLK_MASH_1;
576 +
577 + dividend = bcm2708_clk_freq[clk_src];
578 + dividend <<= BCM2708_CLK_SHIFT;
579 + do_div(dividend, target_frequency);
580 + divi = dividend >> BCM2708_CLK_SHIFT;
581 + divf = dividend & BCM2708_CLK_DIVF_MASK;
582 + }
583 +
584 + /* Clock should only be set up here if CPU is clock master */
585 + if (((dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBS_CFS) ||
586 + ((dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBS_CFM)) {
587 + /* Set clock divider */
588 + regmap_write(dev->clk_regmap, BCM2708_CLK_PCMDIV_REG, BCM2708_CLK_PASSWD
589 + | BCM2708_CLK_DIVI(divi)
590 + | BCM2708_CLK_DIVF(divf));
591 +
592 + /* Setup clock, but don't start it yet */
593 + regmap_write(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, BCM2708_CLK_PASSWD
594 + | BCM2708_CLK_MASH(mash)
595 + | BCM2708_CLK_SRC(clk_src));
596 + }
597 +
598 + /* Setup the frame format */
599 + format = BCM2708_I2S_CHEN;
600 +
601 + if (data_length >= 24)
602 + format |= BCM2708_I2S_CHWEX;
603 +
604 + format |= BCM2708_I2S_CHWID((data_length-8)&0xf);
605 +
606 + switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
607 + case SND_SOC_DAIFMT_I2S:
608 + data_delay = 1;
609 + break;
610 + default:
611 + /*
612 + * TODO
613 + * Others are possible but are not implemented at the moment.
614 + */
615 + dev_err(dev->dev, "%s:bad format\n", __func__);
616 + return -EINVAL;
617 + }
618 +
619 + ch1pos = data_delay;
620 + ch2pos = bclk_ratio / 2 + data_delay;
621 +
622 + switch (params_channels(params)) {
623 + case 2:
624 + format = BCM2708_I2S_CH1(format) | BCM2708_I2S_CH2(format);
625 + format |= BCM2708_I2S_CH1(BCM2708_I2S_CHPOS(ch1pos));
626 + format |= BCM2708_I2S_CH2(BCM2708_I2S_CHPOS(ch2pos));
627 + break;
628 + default:
629 + return -EINVAL;
630 + }
631 +
632 + /*
633 + * Set format for both streams.
634 + * We cannot set another frame length
635 + * (and therefore word length) anyway,
636 + * so the format will be the same.
637 + */
638 + regmap_write(dev->i2s_regmap, BCM2708_I2S_RXC_A_REG, format);
639 + regmap_write(dev->i2s_regmap, BCM2708_I2S_TXC_A_REG, format);
640 +
641 + /* Setup the I2S mode */
642 + mode = 0;
643 +
644 + if (data_length <= 16) {
645 + /*
646 + * Use frame packed mode (2 channels per 32 bit word)
647 + * We cannot set another frame length in the second stream
648 + * (and therefore word length) anyway,
649 + * so the format will be the same.
650 + */
651 + mode |= BCM2708_I2S_FTXP | BCM2708_I2S_FRXP;
652 + }
653 +
654 + mode |= BCM2708_I2S_FLEN(bclk_ratio - 1);
655 + mode |= BCM2708_I2S_FSLEN(bclk_ratio / 2);
656 +
657 + /* Master or slave? */
658 + switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
659 + case SND_SOC_DAIFMT_CBS_CFS:
660 + /* CPU is master */
661 + break;
662 + case SND_SOC_DAIFMT_CBM_CFS:
663 + /*
664 + * CODEC is bit clock master
665 + * CPU is frame master
666 + */
667 + mode |= BCM2708_I2S_CLKM;
668 + break;
669 + case SND_SOC_DAIFMT_CBS_CFM:
670 + /*
671 + * CODEC is frame master
672 + * CPU is bit clock master
673 + */
674 + mode |= BCM2708_I2S_FSM;
675 + break;
676 + case SND_SOC_DAIFMT_CBM_CFM:
677 + /* CODEC is master */
678 + mode |= BCM2708_I2S_CLKM;
679 + mode |= BCM2708_I2S_FSM;
680 + break;
681 + default:
682 + dev_err(dev->dev, "%s:bad master\n", __func__);
683 + return -EINVAL;
684 + }
685 +
686 + /*
687 + * Invert clocks?
688 + *
689 + * The BCM approach seems to be inverted to the classical I2S approach.
690 + */
691 + switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) {
692 + case SND_SOC_DAIFMT_NB_NF:
693 + /* None. Therefore, both for BCM */
694 + mode |= BCM2708_I2S_CLKI;
695 + mode |= BCM2708_I2S_FSI;
696 + break;
697 + case SND_SOC_DAIFMT_IB_IF:
698 + /* Both. Therefore, none for BCM */
699 + break;
700 + case SND_SOC_DAIFMT_NB_IF:
701 + /*
702 + * Invert only frame sync. Therefore,
703 + * invert only bit clock for BCM
704 + */
705 + mode |= BCM2708_I2S_CLKI;
706 + break;
707 + case SND_SOC_DAIFMT_IB_NF:
708 + /*
709 + * Invert only bit clock. Therefore,
710 + * invert only frame sync for BCM
711 + */
712 + mode |= BCM2708_I2S_FSI;
713 + break;
714 + default:
715 + return -EINVAL;
716 + }
717 +
718 + regmap_write(dev->i2s_regmap, BCM2708_I2S_MODE_A_REG, mode);
719 +
720 + /* Setup the DMA parameters */
721 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
722 + BCM2708_I2S_RXTHR(1)
723 + | BCM2708_I2S_TXTHR(1)
724 + | BCM2708_I2S_DMAEN, 0xffffffff);
725 +
726 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_DREQ_A_REG,
727 + BCM2708_I2S_TX_PANIC(0x10)
728 + | BCM2708_I2S_RX_PANIC(0x30)
729 + | BCM2708_I2S_TX(0x30)
730 + | BCM2708_I2S_RX(0x20), 0xffffffff);
731 +
732 + /* Clear FIFOs */
733 + bcm2708_i2s_clear_fifos(dev, true, true);
734 +
735 + return 0;
736 +}
737 +
738 +static int bcm2708_i2s_prepare(struct snd_pcm_substream *substream,
739 + struct snd_soc_dai *dai)
740 +{
741 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
742 + uint32_t cs_reg;
743 +
744 + bcm2708_i2s_start_clock(dev);
745 +
746 + /*
747 + * Clear both FIFOs if the one that should be started
748 + * is not empty at the moment. This should only happen
749 + * after overrun. Otherwise, hw_params would have cleared
750 + * the FIFO.
751 + */
752 + regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &cs_reg);
753 +
754 + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK
755 + && !(cs_reg & BCM2708_I2S_TXE))
756 + bcm2708_i2s_clear_fifos(dev, true, false);
757 + else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE
758 + && (cs_reg & BCM2708_I2S_RXD))
759 + bcm2708_i2s_clear_fifos(dev, false, true);
760 +
761 + return 0;
762 +}
763 +
764 +static void bcm2708_i2s_stop(struct bcm2708_i2s_dev *dev,
765 + struct snd_pcm_substream *substream,
766 + struct snd_soc_dai *dai)
767 +{
768 + uint32_t mask;
769 +
770 + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
771 + mask = BCM2708_I2S_RXON;
772 + else
773 + mask = BCM2708_I2S_TXON;
774 +
775 + regmap_update_bits(dev->i2s_regmap,
776 + BCM2708_I2S_CS_A_REG, mask, 0);
777 +
778 + /* Stop also the clock when not SND_SOC_DAIFMT_CONT */
779 + if (!dai->active && !(dev->fmt & SND_SOC_DAIFMT_CONT))
780 + bcm2708_i2s_stop_clock(dev);
781 +}
782 +
783 +static int bcm2708_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
784 + struct snd_soc_dai *dai)
785 +{
786 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
787 + uint32_t mask;
788 +
789 + switch (cmd) {
790 + case SNDRV_PCM_TRIGGER_START:
791 + case SNDRV_PCM_TRIGGER_RESUME:
792 + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
793 + bcm2708_i2s_start_clock(dev);
794 +
795 + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
796 + mask = BCM2708_I2S_RXON;
797 + else
798 + mask = BCM2708_I2S_TXON;
799 +
800 + regmap_update_bits(dev->i2s_regmap,
801 + BCM2708_I2S_CS_A_REG, mask, mask);
802 + break;
803 +
804 + case SNDRV_PCM_TRIGGER_STOP:
805 + case SNDRV_PCM_TRIGGER_SUSPEND:
806 + case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
807 + bcm2708_i2s_stop(dev, substream, dai);
808 + break;
809 + default:
810 + return -EINVAL;
811 + }
812 +
813 + return 0;
814 +}
815 +
816 +static int bcm2708_i2s_startup(struct snd_pcm_substream *substream,
817 + struct snd_soc_dai *dai)
818 +{
819 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
820 +
821 + if (dai->active)
822 + return 0;
823 +
824 + /* Should this still be running stop it */
825 + bcm2708_i2s_stop_clock(dev);
826 +
827 + /* Enable PCM block */
828 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
829 + BCM2708_I2S_EN, BCM2708_I2S_EN);
830 +
831 + /*
832 + * Disable STBY.
833 + * Requires at least 4 PCM clock cycles to take effect.
834 + */
835 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
836 + BCM2708_I2S_STBY, BCM2708_I2S_STBY);
837 +
838 + return 0;
839 +}
840 +
841 +static void bcm2708_i2s_shutdown(struct snd_pcm_substream *substream,
842 + struct snd_soc_dai *dai)
843 +{
844 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
845 +
846 + bcm2708_i2s_stop(dev, substream, dai);
847 +
848 + /* If both streams are stopped, disable module and clock */
849 + if (dai->active)
850 + return;
851 +
852 + /* Disable the module */
853 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
854 + BCM2708_I2S_EN, 0);
855 +
856 + /*
857 + * Stopping clock is necessary, because stop does
858 + * not stop the clock when SND_SOC_DAIFMT_CONT
859 + */
860 + bcm2708_i2s_stop_clock(dev);
861 +}
862 +
863 +static const struct snd_soc_dai_ops bcm2708_i2s_dai_ops = {
864 + .startup = bcm2708_i2s_startup,
865 + .shutdown = bcm2708_i2s_shutdown,
866 + .prepare = bcm2708_i2s_prepare,
867 + .trigger = bcm2708_i2s_trigger,
868 + .hw_params = bcm2708_i2s_hw_params,
869 + .set_fmt = bcm2708_i2s_set_dai_fmt,
870 + .set_bclk_ratio = bcm2708_i2s_set_dai_bclk_ratio
871 +};
872 +
873 +static int bcm2708_i2s_dai_probe(struct snd_soc_dai *dai)
874 +{
875 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
876 +
877 + dai->playback_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
878 + dai->capture_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE];
879 +
880 + return 0;
881 +}
882 +
883 +static struct snd_soc_dai_driver bcm2708_i2s_dai = {
884 + .name = "bcm2708-i2s",
885 + .probe = bcm2708_i2s_dai_probe,
886 + .playback = {
887 + .channels_min = 2,
888 + .channels_max = 2,
889 + .rates = SNDRV_PCM_RATE_8000_192000,
890 + .formats = SNDRV_PCM_FMTBIT_S16_LE
891 + | SNDRV_PCM_FMTBIT_S24_LE
892 + | SNDRV_PCM_FMTBIT_S32_LE
893 + },
894 + .capture = {
895 + .channels_min = 2,
896 + .channels_max = 2,
897 + .rates = SNDRV_PCM_RATE_8000_192000,
898 + .formats = SNDRV_PCM_FMTBIT_S16_LE
899 + | SNDRV_PCM_FMTBIT_S24_LE
900 + | SNDRV_PCM_FMTBIT_S32_LE
901 + },
902 + .ops = &bcm2708_i2s_dai_ops,
903 + .symmetric_rates = 1
904 +};
905 +
906 +static bool bcm2708_i2s_volatile_reg(struct device *dev, unsigned int reg)
907 +{
908 + switch (reg) {
909 + case BCM2708_I2S_CS_A_REG:
910 + case BCM2708_I2S_FIFO_A_REG:
911 + case BCM2708_I2S_INTSTC_A_REG:
912 + case BCM2708_I2S_GRAY_REG:
913 + return true;
914 + default:
915 + return false;
916 + };
917 +}
918 +
919 +static bool bcm2708_i2s_precious_reg(struct device *dev, unsigned int reg)
920 +{
921 + switch (reg) {
922 + case BCM2708_I2S_FIFO_A_REG:
923 + return true;
924 + default:
925 + return false;
926 + };
927 +}
928 +
929 +static bool bcm2708_clk_volatile_reg(struct device *dev, unsigned int reg)
930 +{
931 + switch (reg) {
932 + case BCM2708_CLK_PCMCTL_REG:
933 + return true;
934 + default:
935 + return false;
936 + };
937 +}
938 +
939 +static const struct regmap_config bcm2708_regmap_config[] = {
940 + {
941 + .reg_bits = 32,
942 + .reg_stride = 4,
943 + .val_bits = 32,
944 + .max_register = BCM2708_I2S_GRAY_REG,
945 + .precious_reg = bcm2708_i2s_precious_reg,
946 + .volatile_reg = bcm2708_i2s_volatile_reg,
947 + .cache_type = REGCACHE_RBTREE,
948 + .name = "i2s",
949 + },
950 + {
951 + .reg_bits = 32,
952 + .reg_stride = 4,
953 + .val_bits = 32,
954 + .max_register = BCM2708_CLK_PCMDIV_REG,
955 + .volatile_reg = bcm2708_clk_volatile_reg,
956 + .cache_type = REGCACHE_RBTREE,
957 + .name = "clk",
958 + },
959 +};
960 +
961 +static const struct snd_soc_component_driver bcm2708_i2s_component = {
962 + .name = "bcm2708-i2s-comp",
963 +};
964 +
965 +static const struct snd_pcm_hardware bcm2708_pcm_hardware = {
966 + .info = SNDRV_PCM_INFO_INTERLEAVED |
967 + SNDRV_PCM_INFO_JOINT_DUPLEX,
968 + .formats = SNDRV_PCM_FMTBIT_S16_LE |
969 + SNDRV_PCM_FMTBIT_S24_LE |
970 + SNDRV_PCM_FMTBIT_S32_LE,
971 + .period_bytes_min = 32,
972 + .period_bytes_max = 64 * PAGE_SIZE,
973 + .periods_min = 2,
974 + .periods_max = 255,
975 + .buffer_bytes_max = 128 * PAGE_SIZE,
976 +};
977 +
978 +static const struct snd_dmaengine_pcm_config bcm2708_dmaengine_pcm_config = {
979 + .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
980 + .pcm_hardware = &bcm2708_pcm_hardware,
981 + .prealloc_buffer_size = 256 * PAGE_SIZE,
982 +};
983 +
984 +
985 +static int bcm2708_i2s_probe(struct platform_device *pdev)
986 +{
987 + struct bcm2708_i2s_dev *dev;
988 + int i;
989 + int ret;
990 + struct regmap *regmap[2];
991 + struct resource *mem[2];
992 +
993 + /* Request both ioareas */
994 + for (i = 0; i <= 1; i++) {
995 + void __iomem *base;
996 +
997 + mem[i] = platform_get_resource(pdev, IORESOURCE_MEM, i);
998 + base = devm_ioremap_resource(&pdev->dev, mem[i]);
999 + if (IS_ERR(base))
1000 + return PTR_ERR(base);
1001 +
1002 + regmap[i] = devm_regmap_init_mmio(&pdev->dev, base,
1003 + &bcm2708_regmap_config[i]);
1004 + if (IS_ERR(regmap[i])) {
1005 + dev_err(&pdev->dev, "I2S probe: regmap init failed\n");
1006 + return PTR_ERR(regmap[i]);
1007 + }
1008 + }
1009 +
1010 + dev = devm_kzalloc(&pdev->dev, sizeof(*dev),
1011 + GFP_KERNEL);
1012 + if (IS_ERR(dev))
1013 + return PTR_ERR(dev);
1014 +
1015 + dev->i2s_regmap = regmap[0];
1016 + dev->clk_regmap = regmap[1];
1017 +
1018 + /* Set the DMA address */
1019 + dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr =
1020 + (dma_addr_t)BCM2708_I2S_FIFO_PHYSICAL_ADDR;
1021 +
1022 + dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr =
1023 + (dma_addr_t)BCM2708_I2S_FIFO_PHYSICAL_ADDR;
1024 +
1025 + /* Set the DREQ */
1026 + dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].slave_id =
1027 + BCM2708_DMA_DREQ_PCM_TX;
1028 + dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].slave_id =
1029 + BCM2708_DMA_DREQ_PCM_RX;
1030 +
1031 + /* Set the bus width */
1032 + dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr_width =
1033 + DMA_SLAVE_BUSWIDTH_4_BYTES;
1034 + dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr_width =
1035 + DMA_SLAVE_BUSWIDTH_4_BYTES;
1036 +
1037 + /* Set burst */
1038 + dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].maxburst = 2;
1039 + dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].maxburst = 2;
1040 +
1041 + /* BCLK ratio - use default */
1042 + dev->bclk_ratio = 0;
1043 +
1044 + /* Store the pdev */
1045 + dev->dev = &pdev->dev;
1046 + dev_set_drvdata(&pdev->dev, dev);
1047 +
1048 + ret = snd_soc_register_component(&pdev->dev,
1049 + &bcm2708_i2s_component, &bcm2708_i2s_dai, 1);
1050 +
1051 + if (ret) {
1052 + dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
1053 + ret = -ENOMEM;
1054 + return ret;
1055 + }
1056 +
1057 + ret = snd_dmaengine_pcm_register(&pdev->dev,
1058 + &bcm2708_dmaengine_pcm_config,
1059 + SND_DMAENGINE_PCM_FLAG_COMPAT);
1060 + if (ret) {
1061 + dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
1062 + snd_soc_unregister_component(&pdev->dev);
1063 + return ret;
1064 + }
1065 +
1066 + return 0;
1067 +}
1068 +
1069 +static int bcm2708_i2s_remove(struct platform_device *pdev)
1070 +{
1071 + snd_dmaengine_pcm_unregister(&pdev->dev);
1072 + snd_soc_unregister_component(&pdev->dev);
1073 + return 0;
1074 +}
1075 +
1076 +static const struct of_device_id bcm2708_i2s_of_match[] = {
1077 + { .compatible = "brcm,bcm2708-i2s", },
1078 + {},
1079 +};
1080 +MODULE_DEVICE_TABLE(of, bcm2708_i2s_of_match);
1081 +
1082 +static struct platform_driver bcm2708_i2s_driver = {
1083 + .probe = bcm2708_i2s_probe,
1084 + .remove = bcm2708_i2s_remove,
1085 + .driver = {
1086 + .name = "bcm2708-i2s",
1087 + .owner = THIS_MODULE,
1088 + .of_match_table = bcm2708_i2s_of_match,
1089 + },
1090 +};
1091 +
1092 +module_platform_driver(bcm2708_i2s_driver);
1093 +
1094 +MODULE_ALIAS("platform:bcm2708-i2s");
1095 +MODULE_DESCRIPTION("BCM2708 I2S interface");
1096 +MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
1097 +MODULE_LICENSE("GPL v2");
1098 --- /dev/null
1099 +++ b/sound/soc/bcm/bcm2708-i2s.h
1100 @@ -0,0 +1,35 @@
1101 +/*
1102 + * I2S configuration for sound cards.
1103 + *
1104 + * Copyright (c) 2014 Daniel Matuschek <daniel@hifiberry.com>
1105 + *
1106 + * This program is free software; you can redistribute it and/or modify
1107 + * it under the terms of the GNU General Public License as published by
1108 + * the Free Software Foundation; either version 2 of the License, or
1109 + * (at your option) any later version.
1110 + *
1111 + * This program is distributed in the hope that it will be useful,
1112 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1113 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1114 + * GNU General Public License for more details.
1115 + *
1116 + * You should have received a copy of the GNU General Public License
1117 + * along with this program; if not, write to the Free Software
1118 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1119 + */
1120 +
1121 +#ifndef BCM2708_I2S_H
1122 +#define BCM2708_I2S_H
1123 +
1124 +/* I2S pin assignment */
1125 +#define BCM2708_I2S_GPIO_AUTO 0
1126 +#define BCM2708_I2S_GPIO_PIN18 1
1127 +#define BCM2708_I2S_GPIO_PIN28 2
1128 +
1129 +/* Alt mode to enable I2S */
1130 +#define BCM2708_I2S_GPIO_PIN18_ALT 0
1131 +#define BCM2708_I2S_GPIO_PIN28_ALT 2
1132 +
1133 +extern void bcm2708_i2s_set_gpio(int gpio);
1134 +
1135 +#endif
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