target/linux/brcm2708/patches-4.4/0016-bcm2835-i2s-setup-clock-only-if-CPU-is-clock-master.patch

   1 From 63e23a08bd0bcf782f870bacaf82404e36a6a1bd Mon Sep 17 00:00:00 2001
   2 From: Matthias Reichl <hias@horus.com>
   3 Date: Sun, 11 Oct 2015 15:25:51 +0200
   4 Subject: [PATCH] bcm2835-i2s: setup clock only if CPU is clock master
   5
   6 Code ported from bcm2708-i2s driver in Raspberry Pi tree.
   7
   8 RPi commit c14827ecdaa36607f6110f9ce8df96e698672191 ("bcm2708: Allow
   9 option card devices to be configured via DT")
  10
  11 Original work by Zoltan Szenczi, committed to RPi tree by
  12 Phil Elwell.
  13
  14 Signed-off-by: Matthias Reichl <hias@horus.com>
  15 ---
  16  sound/soc/bcm/bcm2835-i2s.c | 28 +++++++++++++++++++---------
  17  1 file changed, 19 insertions(+), 9 deletions(-)
  18
  19 --- a/sound/soc/bcm/bcm2835-i2s.c
  20 +++ b/sound/soc/bcm/bcm2835-i2s.c
  21 @@ -411,15 +411,25 @@ static int bcm2835_i2s_hw_params(struct
  22                 divf = dividend & BCM2835_CLK_DIVF_MASK;
  23         }
  24
  25 -       /* Set clock divider */
  26 -       regmap_write(dev->clk_regmap, BCM2835_CLK_PCMDIV_REG, BCM2835_CLK_PASSWD
  27 -                       | BCM2835_CLK_DIVI(divi)
  28 -                       | BCM2835_CLK_DIVF(divf));
  29 +       /* Clock should only be set up here if CPU is clock master */
  30 +       switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  31 +       case SND_SOC_DAIFMT_CBS_CFS:
  32 +       case SND_SOC_DAIFMT_CBS_CFM:
  33 +               /* Set clock divider */
  34 +               regmap_write(dev->clk_regmap, BCM2835_CLK_PCMDIV_REG,
  35 +                                 BCM2835_CLK_PASSWD
  36 +                               | BCM2835_CLK_DIVI(divi)
  37 +                               | BCM2835_CLK_DIVF(divf));
  38
  39 -       /* Setup clock, but don't start it yet */
  40 -       regmap_write(dev->clk_regmap, BCM2835_CLK_PCMCTL_REG, BCM2835_CLK_PASSWD
  41 -                       | BCM2835_CLK_MASH(mash)
  42 -                       | BCM2835_CLK_SRC(clk_src));
  43 +               /* Setup clock, but don't start it yet */
  44 +               regmap_write(dev->clk_regmap, BCM2835_CLK_PCMCTL_REG,
  45 +                                 BCM2835_CLK_PASSWD
  46 +                               | BCM2835_CLK_MASH(mash)
  47 +                               | BCM2835_CLK_SRC(clk_src));
  48 +               break;
  49 +       default:
  50 +               break;
  51 +       }
  52
  53         /* Setup the frame format */
  54         format = BCM2835_I2S_CHEN;