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brcm2708: update linux 4.4 patches to latest version
[openwrt/openwrt.git] / target / linux / brcm2708 / patches-4.4 / 0033-Adding-bcm2835-sdhost-driver-and-an-overlay-to-enabl.patch
1 From 0c9b7e17d022e45363737d67da590524416f8e3d Mon Sep 17 00:00:00 2001
2 From: Phil Elwell <phil@raspberrypi.org>
3 Date: Wed, 25 Mar 2015 17:49:47 +0000
4 Subject: [PATCH] Adding bcm2835-sdhost driver, and an overlay to enable it
5
6 BCM2835 has two SD card interfaces. This driver uses the other one.
7
8 bcm2835-sdhost: Error handling fix, and code clarification
9
10 bcm2835-sdhost: Adding overclocking option
11
12 Allow a different clock speed to be substitued for a requested 50MHz.
13 This option is exposed using the "overclock_50" DT parameter.
14 Note that the sdhost interface is restricted to integer divisions of
15 core_freq, and the highest sensible option for a core_freq of 250MHz
16 is 84 (250/3 = 83.3MHz), the next being 125 (250/2) which is much too
17 high.
18
19 Use at your own risk.
20
21 bcm2835-sdhost: Round up the overclock, so 62 works for 62.5Mhz
22
23 Also only warn once for each overclock setting.
24
25 bcm2835-sdhost: Improve error handling and recovery
26
27 1) Expose the hw_reset method to the MMC framework, removing many
28 internal calls by the driver.
29
30 2) Reduce overclock setting on error.
31
32 3) Increase timeout to cope with high capacity cards.
33
34 4) Add properties and parameters to control pio_limit and debug.
35
36 5) Reduce messages at probe time.
37
38 bcm2835-sdhost: Further improve overclock back-off
39
40 bcm2835-sdhost: Clear HBLC for PIO mode
41
42 Also update pio_limit default in overlay README.
43
44 bcm2835-sdhost: Add the ERASE capability
45
46 See: https://github.com/raspberrypi/linux/issues/1076
47
48 bcm2835-sdhost: Ignore CRC7 for MMC CMD1
49
50 It seems that the sdhost interface returns CRC7 errors for CMD1,
51 which is the MMC-specific SEND_OP_COND. Returning these errors to
52 the MMC layer causes a downward spiral, but ignoring them seems
53 to be harmless.
54
55 bcm2835-mmc/sdhost: Remove ARCH_BCM2835 differences
56
57 The bcm2835-mmc driver (and -sdhost driver that copied from it)
58 contains code to handle SDIO interrupts in a threaded interrupt
59 handler rather than waking the MMC framework thread. The change
60 follows a patch from Russell King that adds the facility as the
61 preferred way of working.
62
63 However, the new code path is only present in ARCH_BCM2835
64 builds, which I have taken to be a way of testing the waters
65 rather than making the change across the board; I can't see
66 any technical reason why it wouldn't be enabled for MACH_BCM270X
67 builds. So this patch standardises on the ARCH_BCM2835 code,
68 removing the old code paths.
69
70 bcm2835-sdhost: Don't log timeout errors unless debug=1
71
72 The MMC card-discovery process generates timeouts. This is
73 expected behaviour, so reporting it to the user serves no purpose.
74 Suppress the reporting of timeout errors unless the debug flag
75 is on.
76 ---
77 drivers/mmc/host/Kconfig | 10 +
78 drivers/mmc/host/Makefile | 1 +
79 drivers/mmc/host/bcm2835-sdhost.c | 1907 +++++++++++++++++++++++++++++++++++++
80 3 files changed, 1918 insertions(+)
81 create mode 100644 drivers/mmc/host/bcm2835-sdhost.c
82
83 --- a/drivers/mmc/host/Kconfig
84 +++ b/drivers/mmc/host/Kconfig
85 @@ -33,6 +33,16 @@ config MMC_BCM2835_PIO_DMA_BARRIER
86
87 If unsure, say 2 here.
88
89 +config MMC_BCM2835_SDHOST
90 + tristate "Support for the SDHost controller on BCM2708/9"
91 + depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835
92 + help
93 + This selects the SDHost controller on BCM2835/6.
94 +
95 + If you have a controller with this interface, say Y or M here.
96 +
97 + If unsure, say N.
98 +
99 config MMC_ARMMMCI
100 tristate "ARM AMBA Multimedia Card Interface support"
101 depends on ARM_AMBA
102 --- a/drivers/mmc/host/Makefile
103 +++ b/drivers/mmc/host/Makefile
104 @@ -18,6 +18,7 @@ obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c
105 obj-$(CONFIG_MMC_SDHCI_SIRF) += sdhci-sirf.o
106 obj-$(CONFIG_MMC_SDHCI_F_SDH30) += sdhci_f_sdh30.o
107 obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o
108 +obj-$(CONFIG_MMC_BCM2835_SDHOST) += bcm2835-sdhost.o
109 obj-$(CONFIG_MMC_BCM2835) += bcm2835-mmc.o
110 obj-$(CONFIG_MMC_WBSD) += wbsd.o
111 obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
112 --- /dev/null
113 +++ b/drivers/mmc/host/bcm2835-sdhost.c
114 @@ -0,0 +1,1907 @@
115 +/*
116 + * BCM2835 SD host driver.
117 + *
118 + * Author: Phil Elwell <phil@raspberrypi.org>
119 + * Copyright 2015
120 + *
121 + * Based on
122 + * mmc-bcm2835.c by Gellert Weisz
123 + * which is, in turn, based on
124 + * sdhci-bcm2708.c by Broadcom
125 + * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
126 + * sdhci.c and sdhci-pci.c by Pierre Ossman
127 + *
128 + * This program is free software; you can redistribute it and/or modify it
129 + * under the terms and conditions of the GNU General Public License,
130 + * version 2, as published by the Free Software Foundation.
131 + *
132 + * This program is distributed in the hope it will be useful, but WITHOUT
133 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
134 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
135 + * more details.
136 + *
137 + * You should have received a copy of the GNU General Public License
138 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
139 + */
140 +
141 +#define SAFE_READ_THRESHOLD 4
142 +#define SAFE_WRITE_THRESHOLD 4
143 +#define ALLOW_DMA 1
144 +#define ALLOW_CMD23 0
145 +#define ALLOW_FAST 1
146 +#define USE_BLOCK_IRQ 1
147 +
148 +#include <linux/delay.h>
149 +#include <linux/module.h>
150 +#include <linux/io.h>
151 +#include <linux/mmc/mmc.h>
152 +#include <linux/mmc/host.h>
153 +#include <linux/mmc/sd.h>
154 +#include <linux/scatterlist.h>
155 +#include <linux/of_address.h>
156 +#include <linux/of_irq.h>
157 +#include <linux/clk.h>
158 +#include <linux/platform_device.h>
159 +#include <linux/err.h>
160 +#include <linux/blkdev.h>
161 +#include <linux/dmaengine.h>
162 +#include <linux/dma-mapping.h>
163 +#include <linux/of_dma.h>
164 +#include <linux/time.h>
165 +
166 +#define DRIVER_NAME "sdhost-bcm2835"
167 +
168 +#define SDCMD 0x00 /* Command to SD card - 16 R/W */
169 +#define SDARG 0x04 /* Argument to SD card - 32 R/W */
170 +#define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
171 +#define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */
172 +#define SDRSP0 0x10 /* SD card response (31:0) - 32 R */
173 +#define SDRSP1 0x14 /* SD card response (63:32) - 32 R */
174 +#define SDRSP2 0x18 /* SD card response (95:64) - 32 R */
175 +#define SDRSP3 0x1c /* SD card response (127:96) - 32 R */
176 +#define SDHSTS 0x20 /* SD host status - 11 R */
177 +#define SDVDD 0x30 /* SD card power control - 1 R/W */
178 +#define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */
179 +#define SDHCFG 0x38 /* Host configuration - 2 R/W */
180 +#define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */
181 +#define SDDATA 0x40 /* Data to/from SD card - 32 R/W */
182 +#define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */
183 +
184 +#define SDCMD_NEW_FLAG 0x8000
185 +#define SDCMD_FAIL_FLAG 0x4000
186 +#define SDCMD_BUSYWAIT 0x800
187 +#define SDCMD_NO_RESPONSE 0x400
188 +#define SDCMD_LONG_RESPONSE 0x200
189 +#define SDCMD_WRITE_CMD 0x80
190 +#define SDCMD_READ_CMD 0x40
191 +#define SDCMD_CMD_MASK 0x3f
192 +
193 +#define SDCDIV_MAX_CDIV 0x7ff
194 +
195 +#define SDHSTS_BUSY_IRPT 0x400
196 +#define SDHSTS_BLOCK_IRPT 0x200
197 +#define SDHSTS_SDIO_IRPT 0x100
198 +#define SDHSTS_REW_TIME_OUT 0x80
199 +#define SDHSTS_CMD_TIME_OUT 0x40
200 +#define SDHSTS_CRC16_ERROR 0x20
201 +#define SDHSTS_CRC7_ERROR 0x10
202 +#define SDHSTS_FIFO_ERROR 0x08
203 +/* Reserved */
204 +/* Reserved */
205 +#define SDHSTS_DATA_FLAG 0x01
206 +
207 +#define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR|SDHSTS_CRC16_ERROR|SDHSTS_REW_TIME_OUT|SDHSTS_FIFO_ERROR)
208 +#define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT|SDHSTS_TRANSFER_ERROR_MASK)
209 +
210 +#define SDHCFG_BUSY_IRPT_EN (1<<10)
211 +#define SDHCFG_BLOCK_IRPT_EN (1<<8)
212 +#define SDHCFG_SDIO_IRPT_EN (1<<5)
213 +#define SDHCFG_DATA_IRPT_EN (1<<4)
214 +#define SDHCFG_SLOW_CARD (1<<3)
215 +#define SDHCFG_WIDE_EXT_BUS (1<<2)
216 +#define SDHCFG_WIDE_INT_BUS (1<<1)
217 +#define SDHCFG_REL_CMD_LINE (1<<0)
218 +
219 +#define SDEDM_FORCE_DATA_MODE (1<<19)
220 +#define SDEDM_CLOCK_PULSE (1<<20)
221 +#define SDEDM_BYPASS (1<<21)
222 +
223 +#define SDEDM_WRITE_THRESHOLD_SHIFT 9
224 +#define SDEDM_READ_THRESHOLD_SHIFT 14
225 +#define SDEDM_THRESHOLD_MASK 0x1f
226 +
227 +#define MHZ 1000000
228 +
229 +
230 +struct bcm2835_host {
231 + spinlock_t lock;
232 +
233 + void __iomem *ioaddr;
234 + u32 bus_addr;
235 +
236 + struct mmc_host *mmc;
237 +
238 + u32 pio_timeout; /* In jiffies */
239 +
240 + int clock; /* Current clock speed */
241 +
242 + bool slow_card; /* Force 11-bit divisor */
243 +
244 + unsigned int max_clk; /* Max possible freq */
245 +
246 + struct tasklet_struct finish_tasklet; /* Tasklet structures */
247 +
248 + struct timer_list timer; /* Timer for timeouts */
249 +
250 + struct timer_list pio_timer; /* PIO error detection timer */
251 +
252 + struct sg_mapping_iter sg_miter; /* SG state for PIO */
253 + unsigned int blocks; /* remaining PIO blocks */
254 +
255 + int irq; /* Device IRQ */
256 +
257 +
258 + /* cached registers */
259 + u32 hcfg;
260 + u32 cdiv;
261 +
262 + struct mmc_request *mrq; /* Current request */
263 + struct mmc_command *cmd; /* Current command */
264 + struct mmc_data *data; /* Current data request */
265 + unsigned int data_complete:1; /* Data finished before cmd */
266 +
267 + unsigned int flush_fifo:1; /* Drain the fifo when finishing */
268 +
269 + unsigned int use_busy:1; /* Wait for busy interrupt */
270 +
271 + unsigned int debug:1; /* Enable debug output */
272 +
273 + u32 thread_isr;
274 +
275 + /*DMA part*/
276 + struct dma_chan *dma_chan_rx; /* DMA channel for reads */
277 + struct dma_chan *dma_chan_tx; /* DMA channel for writes */
278 +
279 + bool allow_dma;
280 + bool have_dma;
281 + bool use_dma;
282 + /*end of DMA part*/
283 +
284 + int max_delay; /* maximum length of time spent waiting */
285 + struct timeval stop_time; /* when the last stop was issued */
286 + u32 delay_after_stop; /* minimum time between stop and subsequent data transfer */
287 + u32 overclock_50; /* frequency to use when 50MHz is requested (in MHz) */
288 + u32 overclock; /* Current frequency if overclocked, else zero */
289 + u32 pio_limit; /* Maximum block count for PIO (0 = always DMA) */
290 +};
291 +
292 +
293 +static inline void bcm2835_sdhost_write(struct bcm2835_host *host, u32 val, int reg)
294 +{
295 + writel(val, host->ioaddr + reg);
296 +}
297 +
298 +static inline u32 bcm2835_sdhost_read(struct bcm2835_host *host, int reg)
299 +{
300 + return readl(host->ioaddr + reg);
301 +}
302 +
303 +static inline u32 bcm2835_sdhost_read_relaxed(struct bcm2835_host *host, int reg)
304 +{
305 + return readl_relaxed(host->ioaddr + reg);
306 +}
307 +
308 +static void bcm2835_sdhost_dumpcmd(struct bcm2835_host *host,
309 + struct mmc_command *cmd,
310 + const char *label)
311 +{
312 + if (cmd)
313 + pr_info("%s:%c%s op %d arg 0x%x flags 0x%x - resp %08x %08x %08x %08x, err %d\n",
314 + mmc_hostname(host->mmc),
315 + (cmd == host->cmd) ? '>' : ' ',
316 + label, cmd->opcode, cmd->arg, cmd->flags,
317 + cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3],
318 + cmd->error);
319 +}
320 +
321 +static void bcm2835_sdhost_dumpregs(struct bcm2835_host *host)
322 +{
323 + bcm2835_sdhost_dumpcmd(host, host->mrq->sbc, "sbc");
324 + bcm2835_sdhost_dumpcmd(host, host->mrq->cmd, "cmd");
325 + if (host->mrq->data)
326 + pr_err("%s: data blocks %x blksz %x - err %d\n",
327 + mmc_hostname(host->mmc),
328 + host->mrq->data->blocks,
329 + host->mrq->data->blksz,
330 + host->mrq->data->error);
331 + bcm2835_sdhost_dumpcmd(host, host->mrq->stop, "stop");
332 +
333 + pr_info("%s: =========== REGISTER DUMP ===========\n",
334 + mmc_hostname(host->mmc));
335 +
336 + pr_info("%s: SDCMD 0x%08x\n",
337 + mmc_hostname(host->mmc),
338 + bcm2835_sdhost_read(host, SDCMD));
339 + pr_info("%s: SDARG 0x%08x\n",
340 + mmc_hostname(host->mmc),
341 + bcm2835_sdhost_read(host, SDARG));
342 + pr_info("%s: SDTOUT 0x%08x\n",
343 + mmc_hostname(host->mmc),
344 + bcm2835_sdhost_read(host, SDTOUT));
345 + pr_info("%s: SDCDIV 0x%08x\n",
346 + mmc_hostname(host->mmc),
347 + bcm2835_sdhost_read(host, SDCDIV));
348 + pr_info("%s: SDRSP0 0x%08x\n",
349 + mmc_hostname(host->mmc),
350 + bcm2835_sdhost_read(host, SDRSP0));
351 + pr_info("%s: SDRSP1 0x%08x\n",
352 + mmc_hostname(host->mmc),
353 + bcm2835_sdhost_read(host, SDRSP1));
354 + pr_info("%s: SDRSP2 0x%08x\n",
355 + mmc_hostname(host->mmc),
356 + bcm2835_sdhost_read(host, SDRSP2));
357 + pr_info("%s: SDRSP3 0x%08x\n",
358 + mmc_hostname(host->mmc),
359 + bcm2835_sdhost_read(host, SDRSP3));
360 + pr_info("%s: SDHSTS 0x%08x\n",
361 + mmc_hostname(host->mmc),
362 + bcm2835_sdhost_read(host, SDHSTS));
363 + pr_info("%s: SDVDD 0x%08x\n",
364 + mmc_hostname(host->mmc),
365 + bcm2835_sdhost_read(host, SDVDD));
366 + pr_info("%s: SDEDM 0x%08x\n",
367 + mmc_hostname(host->mmc),
368 + bcm2835_sdhost_read(host, SDEDM));
369 + pr_info("%s: SDHCFG 0x%08x\n",
370 + mmc_hostname(host->mmc),
371 + bcm2835_sdhost_read(host, SDHCFG));
372 + pr_info("%s: SDHBCT 0x%08x\n",
373 + mmc_hostname(host->mmc),
374 + bcm2835_sdhost_read(host, SDHBCT));
375 + pr_info("%s: SDHBLC 0x%08x\n",
376 + mmc_hostname(host->mmc),
377 + bcm2835_sdhost_read(host, SDHBLC));
378 +
379 + pr_info("%s: ===========================================\n",
380 + mmc_hostname(host->mmc));
381 +}
382 +
383 +
384 +static void bcm2835_sdhost_set_power(struct bcm2835_host *host, bool on)
385 +{
386 + bcm2835_sdhost_write(host, on ? 1 : 0, SDVDD);
387 +}
388 +
389 +
390 +static void bcm2835_sdhost_reset_internal(struct bcm2835_host *host)
391 +{
392 + u32 temp;
393 +
394 + bcm2835_sdhost_set_power(host, false);
395 +
396 + bcm2835_sdhost_write(host, 0, SDCMD);
397 + bcm2835_sdhost_write(host, 0, SDARG);
398 + bcm2835_sdhost_write(host, 0xf00000, SDTOUT);
399 + bcm2835_sdhost_write(host, 0, SDCDIV);
400 + bcm2835_sdhost_write(host, 0x7f8, SDHSTS); /* Write 1s to clear */
401 + bcm2835_sdhost_write(host, 0, SDHCFG);
402 + bcm2835_sdhost_write(host, 0, SDHBCT);
403 + bcm2835_sdhost_write(host, 0, SDHBLC);
404 +
405 + /* Limit fifo usage due to silicon bug */
406 + temp = bcm2835_sdhost_read(host, SDEDM);
407 + temp &= ~((SDEDM_THRESHOLD_MASK<<SDEDM_READ_THRESHOLD_SHIFT) |
408 + (SDEDM_THRESHOLD_MASK<<SDEDM_WRITE_THRESHOLD_SHIFT));
409 + temp |= (SAFE_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) |
410 + (SAFE_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT);
411 + bcm2835_sdhost_write(host, temp, SDEDM);
412 + mdelay(10);
413 + bcm2835_sdhost_set_power(host, true);
414 + mdelay(10);
415 + host->clock = 0;
416 + bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
417 + bcm2835_sdhost_write(host, host->cdiv, SDCDIV);
418 + mmiowb();
419 +}
420 +
421 +
422 +static void bcm2835_sdhost_reset(struct mmc_host *mmc)
423 +{
424 + struct bcm2835_host *host = mmc_priv(mmc);
425 + unsigned long flags;
426 + if (host->debug)
427 + pr_info("%s: reset\n", mmc_hostname(mmc));
428 + spin_lock_irqsave(&host->lock, flags);
429 +
430 + bcm2835_sdhost_reset_internal(host);
431 +
432 + spin_unlock_irqrestore(&host->lock, flags);
433 +}
434 +
435 +static void bcm2835_sdhost_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
436 +
437 +static void bcm2835_sdhost_init(struct bcm2835_host *host, int soft)
438 +{
439 + pr_debug("bcm2835_sdhost_init(%d)\n", soft);
440 +
441 + /* Set interrupt enables */
442 + host->hcfg = SDHCFG_BUSY_IRPT_EN;
443 +
444 + bcm2835_sdhost_reset_internal(host);
445 +
446 + if (soft) {
447 + /* force clock reconfiguration */
448 + host->clock = 0;
449 + bcm2835_sdhost_set_ios(host->mmc, &host->mmc->ios);
450 + }
451 +}
452 +
453 +static bool bcm2835_sdhost_is_write_complete(struct bcm2835_host *host)
454 +{
455 + bool write_complete = ((bcm2835_sdhost_read(host, SDEDM) & 0xf) == 1);
456 +
457 + if (!write_complete) {
458 + /* Request an IRQ for the last block */
459 + host->hcfg |= SDHCFG_BLOCK_IRPT_EN;
460 + bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
461 + if ((bcm2835_sdhost_read(host, SDEDM) & 0xf) == 1) {
462 + /* The write has now completed. Disable the interrupt
463 + and clear the status flag */
464 + host->hcfg &= ~SDHCFG_BLOCK_IRPT_EN;
465 + bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
466 + bcm2835_sdhost_write(host, SDHSTS_BLOCK_IRPT, SDHSTS);
467 + write_complete = true;
468 + }
469 + }
470 +
471 + return write_complete;
472 +}
473 +
474 +static void bcm2835_sdhost_wait_write_complete(struct bcm2835_host *host)
475 +{
476 + int timediff;
477 +#ifdef DEBUG
478 + static struct timeval start_time;
479 + static int max_stall_time = 0;
480 + static int total_stall_time = 0;
481 + struct timeval before, after;
482 +
483 + do_gettimeofday(&before);
484 + if (max_stall_time == 0)
485 + start_time = before;
486 +#endif
487 +
488 + timediff = 0;
489 +
490 + while (1) {
491 + u32 edm = bcm2835_sdhost_read(host, SDEDM);
492 + if ((edm & 0xf) == 1)
493 + break;
494 + timediff++;
495 + if (timediff > 5000000) {
496 +#ifdef DEBUG
497 + do_gettimeofday(&after);
498 + timediff = (after.tv_sec - before.tv_sec)*1000000 +
499 + (after.tv_usec - before.tv_usec);
500 +
501 + pr_err(" wait_write_complete - still waiting after %dus\n",
502 + timediff);
503 +#else
504 + pr_err(" wait_write_complete - still waiting after %d retries\n",
505 + timediff);
506 +#endif
507 + bcm2835_sdhost_dumpregs(host);
508 + host->data->error = -ETIMEDOUT;
509 + return;
510 + }
511 + }
512 +
513 +#ifdef DEBUG
514 + do_gettimeofday(&after);
515 + timediff = (after.tv_sec - before.tv_sec)*1000000 + (after.tv_usec - before.tv_usec);
516 +
517 + total_stall_time += timediff;
518 + if (timediff > max_stall_time)
519 + max_stall_time = timediff;
520 +
521 + if ((after.tv_sec - start_time.tv_sec) > 10) {
522 + pr_debug(" wait_write_complete - max wait %dus, total %dus\n",
523 + max_stall_time, total_stall_time);
524 + start_time = after;
525 + max_stall_time = 0;
526 + total_stall_time = 0;
527 + }
528 +#endif
529 +}
530 +
531 +static void bcm2835_sdhost_finish_data(struct bcm2835_host *host);
532 +
533 +static void bcm2835_sdhost_dma_complete(void *param)
534 +{
535 + struct bcm2835_host *host = param;
536 + struct dma_chan *dma_chan;
537 + unsigned long flags;
538 + u32 dir_data;
539 +
540 + spin_lock_irqsave(&host->lock, flags);
541 +
542 + if (host->data) {
543 + bool write_complete;
544 + if (USE_BLOCK_IRQ)
545 + write_complete = bcm2835_sdhost_is_write_complete(host);
546 + else {
547 + bcm2835_sdhost_wait_write_complete(host);
548 + write_complete = true;
549 + }
550 + pr_debug("dma_complete() - write_complete=%d\n",
551 + write_complete);
552 +
553 + if (write_complete || (host->data->flags & MMC_DATA_READ))
554 + {
555 + if (write_complete) {
556 + dma_chan = host->dma_chan_tx;
557 + dir_data = DMA_TO_DEVICE;
558 + } else {
559 + dma_chan = host->dma_chan_rx;
560 + dir_data = DMA_FROM_DEVICE;
561 + }
562 +
563 + dma_unmap_sg(dma_chan->device->dev,
564 + host->data->sg, host->data->sg_len,
565 + dir_data);
566 +
567 + bcm2835_sdhost_finish_data(host);
568 + }
569 + }
570 +
571 + spin_unlock_irqrestore(&host->lock, flags);
572 +}
573 +
574 +static bool data_transfer_wait(struct bcm2835_host *host)
575 +{
576 + unsigned long timeout = 1000000;
577 + while (timeout)
578 + {
579 + u32 sdhsts = bcm2835_sdhost_read(host, SDHSTS);
580 + if (sdhsts & SDHSTS_DATA_FLAG) {
581 + bcm2835_sdhost_write(host, SDHSTS_DATA_FLAG, SDHSTS);
582 + break;
583 + }
584 + timeout--;
585 + }
586 + if (timeout == 0) {
587 + pr_err("%s: Data %s timeout\n",
588 + mmc_hostname(host->mmc),
589 + (host->data->flags & MMC_DATA_READ) ? "read" : "write");
590 + bcm2835_sdhost_dumpregs(host);
591 + host->data->error = -ETIMEDOUT;
592 + return false;
593 + }
594 + return true;
595 +}
596 +
597 +static void bcm2835_sdhost_read_block_pio(struct bcm2835_host *host)
598 +{
599 + unsigned long flags;
600 + size_t blksize, len;
601 + u32 *buf;
602 +
603 + blksize = host->data->blksz;
604 +
605 + local_irq_save(flags);
606 +
607 + while (blksize) {
608 + if (!sg_miter_next(&host->sg_miter))
609 + BUG();
610 +
611 + len = min(host->sg_miter.length, blksize);
612 + BUG_ON(len % 4);
613 +
614 + blksize -= len;
615 + host->sg_miter.consumed = len;
616 +
617 + buf = (u32 *)host->sg_miter.addr;
618 +
619 + while (len) {
620 + if (!data_transfer_wait(host))
621 + break;
622 +
623 + *(buf++) = bcm2835_sdhost_read(host, SDDATA);
624 + len -= 4;
625 + }
626 +
627 + if (host->data->error)
628 + break;
629 + }
630 +
631 + sg_miter_stop(&host->sg_miter);
632 +
633 + local_irq_restore(flags);
634 +}
635 +
636 +static void bcm2835_sdhost_write_block_pio(struct bcm2835_host *host)
637 +{
638 + unsigned long flags;
639 + size_t blksize, len;
640 + u32 *buf;
641 +
642 + blksize = host->data->blksz;
643 +
644 + local_irq_save(flags);
645 +
646 + while (blksize) {
647 + if (!sg_miter_next(&host->sg_miter))
648 + BUG();
649 +
650 + len = min(host->sg_miter.length, blksize);
651 + BUG_ON(len % 4);
652 +
653 + blksize -= len;
654 + host->sg_miter.consumed = len;
655 +
656 + buf = host->sg_miter.addr;
657 +
658 + while (len) {
659 + if (!data_transfer_wait(host))
660 + break;
661 +
662 + bcm2835_sdhost_write(host, *(buf++), SDDATA);
663 + len -= 4;
664 + }
665 +
666 + if (host->data->error)
667 + break;
668 + }
669 +
670 + sg_miter_stop(&host->sg_miter);
671 +
672 + local_irq_restore(flags);
673 +}
674 +
675 +
676 +static void bcm2835_sdhost_transfer_pio(struct bcm2835_host *host)
677 +{
678 + u32 sdhsts;
679 + bool is_read;
680 + BUG_ON(!host->data);
681 +
682 + is_read = (host->data->flags & MMC_DATA_READ) != 0;
683 + if (is_read)
684 + bcm2835_sdhost_read_block_pio(host);
685 + else
686 + bcm2835_sdhost_write_block_pio(host);
687 +
688 + sdhsts = bcm2835_sdhost_read(host, SDHSTS);
689 + if (sdhsts & (SDHSTS_CRC16_ERROR |
690 + SDHSTS_CRC7_ERROR |
691 + SDHSTS_FIFO_ERROR)) {
692 + pr_err("%s: %s transfer error - HSTS %x\n",
693 + mmc_hostname(host->mmc),
694 + is_read ? "read" : "write",
695 + sdhsts);
696 + host->data->error = -EILSEQ;
697 + } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT |
698 + SDHSTS_REW_TIME_OUT))) {
699 + pr_err("%s: %s timeout error - HSTS %x\n",
700 + mmc_hostname(host->mmc),
701 + is_read ? "read" : "write",
702 + sdhsts);
703 + host->data->error = -ETIMEDOUT;
704 + } else if (!is_read && !host->data->error) {
705 + /* Start a timer in case a transfer error occurs because
706 + there is no error interrupt */
707 + mod_timer(&host->pio_timer, jiffies + host->pio_timeout);
708 + }
709 +}
710 +
711 +
712 +static void bcm2835_sdhost_transfer_dma(struct bcm2835_host *host)
713 +{
714 + u32 len, dir_data, dir_slave;
715 + struct dma_async_tx_descriptor *desc = NULL;
716 + struct dma_chan *dma_chan;
717 +
718 + pr_debug("bcm2835_sdhost_transfer_dma()\n");
719 +
720 + WARN_ON(!host->data);
721 +
722 + if (!host->data)
723 + return;
724 +
725 + if (host->data->flags & MMC_DATA_READ) {
726 + dma_chan = host->dma_chan_rx;
727 + dir_data = DMA_FROM_DEVICE;
728 + dir_slave = DMA_DEV_TO_MEM;
729 + } else {
730 + dma_chan = host->dma_chan_tx;
731 + dir_data = DMA_TO_DEVICE;
732 + dir_slave = DMA_MEM_TO_DEV;
733 + }
734 +
735 + BUG_ON(!dma_chan->device);
736 + BUG_ON(!dma_chan->device->dev);
737 + BUG_ON(!host->data->sg);
738 +
739 + len = dma_map_sg(dma_chan->device->dev, host->data->sg,
740 + host->data->sg_len, dir_data);
741 + if (len > 0) {
742 + desc = dmaengine_prep_slave_sg(dma_chan, host->data->sg,
743 + len, dir_slave,
744 + DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
745 + } else {
746 + dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n");
747 + }
748 + if (desc) {
749 + desc->callback = bcm2835_sdhost_dma_complete;
750 + desc->callback_param = host;
751 + dmaengine_submit(desc);
752 + dma_async_issue_pending(dma_chan);
753 + }
754 +
755 +}
756 +
757 +
758 +static void bcm2835_sdhost_set_transfer_irqs(struct bcm2835_host *host)
759 +{
760 + u32 all_irqs = SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN |
761 + SDHCFG_BUSY_IRPT_EN;
762 + if (host->use_dma)
763 + host->hcfg = (host->hcfg & ~all_irqs) |
764 + SDHCFG_BUSY_IRPT_EN;
765 + else
766 + host->hcfg = (host->hcfg & ~all_irqs) |
767 + SDHCFG_DATA_IRPT_EN |
768 + SDHCFG_BUSY_IRPT_EN;
769 +
770 + bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
771 +}
772 +
773 +
774 +static void bcm2835_sdhost_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd)
775 +{
776 + struct mmc_data *data = cmd->data;
777 +
778 + WARN_ON(host->data);
779 +
780 + if (!data)
781 + return;
782 +
783 + /* Sanity checks */
784 + BUG_ON(data->blksz * data->blocks > 524288);
785 + BUG_ON(data->blksz > host->mmc->max_blk_size);
786 + BUG_ON(data->blocks > 65535);
787 +
788 + host->data = data;
789 + host->data_complete = 0;
790 + host->flush_fifo = 0;
791 + host->data->bytes_xfered = 0;
792 +
793 + host->use_dma = host->have_dma && (data->blocks > host->pio_limit);
794 + if (!host->use_dma) {
795 + int flags;
796 +
797 + flags = SG_MITER_ATOMIC;
798 + if (data->flags & MMC_DATA_READ)
799 + flags |= SG_MITER_TO_SG;
800 + else
801 + flags |= SG_MITER_FROM_SG;
802 + sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
803 + host->blocks = data->blocks;
804 + }
805 +
806 + bcm2835_sdhost_set_transfer_irqs(host);
807 +
808 + bcm2835_sdhost_write(host, data->blksz, SDHBCT);
809 + bcm2835_sdhost_write(host, host->use_dma ? data->blocks : 0, SDHBLC);
810 +
811 + BUG_ON(!host->data);
812 +}
813 +
814 +
815 +void bcm2835_sdhost_send_command(struct bcm2835_host *host, struct mmc_command *cmd)
816 +{
817 + u32 sdcmd, sdhsts;
818 + unsigned long timeout;
819 + int delay;
820 +
821 + WARN_ON(host->cmd);
822 +
823 + if (cmd->data)
824 + pr_debug("%s: send_command %d 0x%x "
825 + "(flags 0x%x) - %s %d*%d\n",
826 + mmc_hostname(host->mmc),
827 + cmd->opcode, cmd->arg, cmd->flags,
828 + (cmd->data->flags & MMC_DATA_READ) ?
829 + "read" : "write", cmd->data->blocks,
830 + cmd->data->blksz);
831 + else
832 + pr_debug("%s: send_command %d 0x%x (flags 0x%x)\n",
833 + mmc_hostname(host->mmc),
834 + cmd->opcode, cmd->arg, cmd->flags);
835 +
836 + /* Wait max 100 ms */
837 + timeout = 10000;
838 +
839 + while (bcm2835_sdhost_read(host, SDCMD) & SDCMD_NEW_FLAG) {
840 + if (timeout == 0) {
841 + pr_err("%s: previous command never completed.\n",
842 + mmc_hostname(host->mmc));
843 + bcm2835_sdhost_dumpregs(host);
844 + cmd->error = -EIO;
845 + tasklet_schedule(&host->finish_tasklet);
846 + return;
847 + }
848 + timeout--;
849 + udelay(10);
850 + }
851 +
852 + delay = (10000 - timeout)/100;
853 + if (delay > host->max_delay) {
854 + host->max_delay = delay;
855 + pr_warning("%s: controller hung for %d ms\n",
856 + mmc_hostname(host->mmc),
857 + host->max_delay);
858 + }
859 +
860 + timeout = jiffies;
861 + if (!cmd->data && cmd->busy_timeout > 9000)
862 + timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
863 + else
864 + timeout += 10 * HZ;
865 + mod_timer(&host->timer, timeout);
866 +
867 + host->cmd = cmd;
868 +
869 + /* Clear any error flags */
870 + sdhsts = bcm2835_sdhost_read(host, SDHSTS);
871 + if (sdhsts & SDHSTS_ERROR_MASK)
872 + bcm2835_sdhost_write(host, sdhsts, SDHSTS);
873 +
874 + bcm2835_sdhost_prepare_data(host, cmd);
875 +
876 + bcm2835_sdhost_write(host, cmd->arg, SDARG);
877 +
878 + if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
879 + pr_err("%s: unsupported response type!\n",
880 + mmc_hostname(host->mmc));
881 + cmd->error = -EINVAL;
882 + tasklet_schedule(&host->finish_tasklet);
883 + return;
884 + }
885 +
886 + sdcmd = cmd->opcode & SDCMD_CMD_MASK;
887 +
888 + if (!(cmd->flags & MMC_RSP_PRESENT))
889 + sdcmd |= SDCMD_NO_RESPONSE;
890 + else {
891 + if (cmd->flags & MMC_RSP_136)
892 + sdcmd |= SDCMD_LONG_RESPONSE;
893 + if (cmd->flags & MMC_RSP_BUSY) {
894 + sdcmd |= SDCMD_BUSYWAIT;
895 + host->use_busy = 1;
896 + }
897 + }
898 +
899 + if (cmd->data) {
900 + if (host->delay_after_stop) {
901 + struct timeval now;
902 + int time_since_stop;
903 + do_gettimeofday(&now);
904 + time_since_stop = (now.tv_sec - host->stop_time.tv_sec);
905 + if (time_since_stop < 2) {
906 + /* Possibly less than one second */
907 + time_since_stop = time_since_stop * 1000000 +
908 + (now.tv_usec - host->stop_time.tv_usec);
909 + if (time_since_stop < host->delay_after_stop)
910 + udelay(host->delay_after_stop -
911 + time_since_stop);
912 + }
913 + }
914 +
915 + if (cmd->data->flags & MMC_DATA_WRITE)
916 + sdcmd |= SDCMD_WRITE_CMD;
917 + if (cmd->data->flags & MMC_DATA_READ)
918 + sdcmd |= SDCMD_READ_CMD;
919 + }
920 +
921 + bcm2835_sdhost_write(host, sdcmd | SDCMD_NEW_FLAG, SDCMD);
922 +}
923 +
924 +
925 +static void bcm2835_sdhost_finish_command(struct bcm2835_host *host);
926 +static void bcm2835_sdhost_transfer_complete(struct bcm2835_host *host);
927 +
928 +static void bcm2835_sdhost_finish_data(struct bcm2835_host *host)
929 +{
930 + struct mmc_data *data;
931 +
932 + data = host->data;
933 + BUG_ON(!data);
934 +
935 + pr_debug("finish_data(error %d, stop %d, sbc %d)\n",
936 + data->error, data->stop ? 1 : 0,
937 + host->mrq->sbc ? 1 : 0);
938 +
939 + host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN);
940 + bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
941 +
942 + if (data->error) {
943 + data->bytes_xfered = 0;
944 + } else
945 + data->bytes_xfered = data->blksz * data->blocks;
946 +
947 + host->data_complete = 1;
948 +
949 + if (host->cmd) {
950 + /*
951 + * Data managed to finish before the
952 + * command completed. Make sure we do
953 + * things in the proper order.
954 + */
955 + pr_debug("Finished early - HSTS %x\n",
956 + bcm2835_sdhost_read(host, SDHSTS));
957 + }
958 + else
959 + bcm2835_sdhost_transfer_complete(host);
960 +}
961 +
962 +
963 +static void bcm2835_sdhost_transfer_complete(struct bcm2835_host *host)
964 +{
965 + struct mmc_data *data;
966 +
967 + BUG_ON(host->cmd);
968 + BUG_ON(!host->data);
969 + BUG_ON(!host->data_complete);
970 +
971 + data = host->data;
972 + host->data = NULL;
973 +
974 + pr_debug("transfer_complete(error %d, stop %d)\n",
975 + data->error, data->stop ? 1 : 0);
976 +
977 + /*
978 + * Need to send CMD12 if -
979 + * a) open-ended multiblock transfer (no CMD23)
980 + * b) error in multiblock transfer
981 + */
982 + if (data->stop &&
983 + (data->error ||
984 + !host->mrq->sbc)) {
985 + host->flush_fifo = 1;
986 + bcm2835_sdhost_send_command(host, data->stop);
987 + if (host->delay_after_stop)
988 + do_gettimeofday(&host->stop_time);
989 + if (!host->use_busy)
990 + bcm2835_sdhost_finish_command(host);
991 + } else {
992 + tasklet_schedule(&host->finish_tasklet);
993 + }
994 +}
995 +
996 +static void bcm2835_sdhost_finish_command(struct bcm2835_host *host)
997 +{
998 + u32 sdcmd;
999 + unsigned long timeout;
1000 +#ifdef DEBUG
1001 + struct timeval before, after;
1002 + int timediff = 0;
1003 +#endif
1004 +
1005 + pr_debug("finish_command(%x)\n", bcm2835_sdhost_read(host, SDCMD));
1006 +
1007 + BUG_ON(!host->cmd || !host->mrq);
1008 +
1009 +#ifdef DEBUG
1010 + do_gettimeofday(&before);
1011 +#endif
1012 + /* Wait max 100 ms */
1013 + timeout = 10000;
1014 + for (sdcmd = bcm2835_sdhost_read(host, SDCMD);
1015 + (sdcmd & SDCMD_NEW_FLAG) && timeout;
1016 + timeout--) {
1017 + if (host->flush_fifo) {
1018 + while (bcm2835_sdhost_read(host, SDHSTS) &
1019 + SDHSTS_DATA_FLAG)
1020 + (void)bcm2835_sdhost_read(host, SDDATA);
1021 + }
1022 + udelay(10);
1023 + sdcmd = bcm2835_sdhost_read(host, SDCMD);
1024 + }
1025 +#ifdef DEBUG
1026 + do_gettimeofday(&after);
1027 + timediff = (after.tv_sec - before.tv_sec)*1000000 +
1028 + (after.tv_usec - before.tv_usec);
1029 +
1030 + pr_debug(" finish_command - waited %dus\n", timediff);
1031 +#endif
1032 +
1033 + if (timeout == 0) {
1034 + pr_err("%s: command never completed.\n",
1035 + mmc_hostname(host->mmc));
1036 + bcm2835_sdhost_dumpregs(host);
1037 + host->cmd->error = -EIO;
1038 + tasklet_schedule(&host->finish_tasklet);
1039 + return;
1040 + }
1041 +
1042 + if (host->flush_fifo) {
1043 + for (timeout = 100;
1044 + (bcm2835_sdhost_read(host, SDHSTS) & SDHSTS_DATA_FLAG) && timeout;
1045 + timeout--) {
1046 + (void)bcm2835_sdhost_read(host, SDDATA);
1047 + }
1048 + host->flush_fifo = 0;
1049 + if (timeout == 0) {
1050 + pr_err("%s: FIFO never drained.\n",
1051 + mmc_hostname(host->mmc));
1052 + bcm2835_sdhost_dumpregs(host);
1053 + host->cmd->error = -EIO;
1054 + tasklet_schedule(&host->finish_tasklet);
1055 + return;
1056 + }
1057 + }
1058 +
1059 + /* Check for errors */
1060 + if (sdcmd & SDCMD_FAIL_FLAG)
1061 + {
1062 + u32 sdhsts = bcm2835_sdhost_read(host, SDHSTS);
1063 +
1064 + if (host->debug)
1065 + pr_info("%s: error detected - CMD %x, HSTS %03x, EDM %x\n",
1066 + mmc_hostname(host->mmc), sdcmd, sdhsts,
1067 + bcm2835_sdhost_read(host, SDEDM));
1068 +
1069 + if ((sdhsts & SDHSTS_CRC7_ERROR) &&
1070 + (host->cmd->opcode == 1)) {
1071 + if (host->debug)
1072 + pr_info("%s: ignoring CRC7 error for CMD1\n",
1073 + mmc_hostname(host->mmc));
1074 + } else {
1075 + if (sdhsts & SDHSTS_CMD_TIME_OUT) {
1076 + if (host->debug)
1077 + pr_err("%s: command %d timeout\n",
1078 + mmc_hostname(host->mmc),
1079 + host->cmd->opcode);
1080 + host->cmd->error = -ETIMEDOUT;
1081 + } else {
1082 + pr_err("%s: unexpected command %d error\n",
1083 + mmc_hostname(host->mmc),
1084 + host->cmd->opcode);
1085 + bcm2835_sdhost_dumpregs(host);
1086 + host->cmd->error = -EIO;
1087 + }
1088 + tasklet_schedule(&host->finish_tasklet);
1089 + return;
1090 + }
1091 + }
1092 +
1093 + if (host->cmd->flags & MMC_RSP_PRESENT) {
1094 + if (host->cmd->flags & MMC_RSP_136) {
1095 + int i;
1096 + for (i = 0; i < 4; i++)
1097 + host->cmd->resp[3 - i] = bcm2835_sdhost_read(host, SDRSP0 + i*4);
1098 + pr_debug("%s: finish_command %08x %08x %08x %08x\n",
1099 + mmc_hostname(host->mmc),
1100 + host->cmd->resp[0], host->cmd->resp[1], host->cmd->resp[2], host->cmd->resp[3]);
1101 + } else {
1102 + host->cmd->resp[0] = bcm2835_sdhost_read(host, SDRSP0);
1103 + pr_debug("%s: finish_command %08x\n",
1104 + mmc_hostname(host->mmc),
1105 + host->cmd->resp[0]);
1106 + }
1107 + }
1108 +
1109 + host->cmd->error = 0;
1110 +
1111 + if (host->cmd == host->mrq->sbc) {
1112 + /* Finished CMD23, now send actual command. */
1113 + host->cmd = NULL;
1114 + bcm2835_sdhost_send_command(host, host->mrq->cmd);
1115 +
1116 + if (host->cmd->data && host->use_dma)
1117 + /* DMA transfer starts now, PIO starts after irq */
1118 + bcm2835_sdhost_transfer_dma(host);
1119 +
1120 + if (!host->use_busy)
1121 + bcm2835_sdhost_finish_command(host);
1122 + } else if (host->cmd == host->mrq->stop)
1123 + /* Finished CMD12 */
1124 + tasklet_schedule(&host->finish_tasklet);
1125 + else {
1126 + /* Processed actual command. */
1127 + host->cmd = NULL;
1128 + if (!host->data)
1129 + tasklet_schedule(&host->finish_tasklet);
1130 + else if (host->data_complete)
1131 + bcm2835_sdhost_transfer_complete(host);
1132 + }
1133 +}
1134 +
1135 +static void bcm2835_sdhost_timeout(unsigned long data)
1136 +{
1137 + struct bcm2835_host *host;
1138 + unsigned long flags;
1139 +
1140 + host = (struct bcm2835_host *)data;
1141 +
1142 + spin_lock_irqsave(&host->lock, flags);
1143 +
1144 + if (host->mrq) {
1145 + pr_err("%s: timeout waiting for hardware interrupt.\n",
1146 + mmc_hostname(host->mmc));
1147 + bcm2835_sdhost_dumpregs(host);
1148 +
1149 + if (host->data) {
1150 + host->data->error = -ETIMEDOUT;
1151 + bcm2835_sdhost_finish_data(host);
1152 + } else {
1153 + if (host->cmd)
1154 + host->cmd->error = -ETIMEDOUT;
1155 + else
1156 + host->mrq->cmd->error = -ETIMEDOUT;
1157 +
1158 + pr_debug("timeout_timer tasklet_schedule\n");
1159 + tasklet_schedule(&host->finish_tasklet);
1160 + }
1161 + }
1162 +
1163 + mmiowb();
1164 + spin_unlock_irqrestore(&host->lock, flags);
1165 +}
1166 +
1167 +static void bcm2835_sdhost_pio_timeout(unsigned long data)
1168 +{
1169 + struct bcm2835_host *host;
1170 + unsigned long flags;
1171 +
1172 + host = (struct bcm2835_host *)data;
1173 +
1174 + spin_lock_irqsave(&host->lock, flags);
1175 +
1176 + if (host->data) {
1177 + u32 sdhsts = bcm2835_sdhost_read(host, SDHSTS);
1178 +
1179 + if (sdhsts & SDHSTS_REW_TIME_OUT) {
1180 + pr_err("%s: transfer timeout\n",
1181 + mmc_hostname(host->mmc));
1182 + if (host->debug)
1183 + bcm2835_sdhost_dumpregs(host);
1184 + } else {
1185 + pr_err("%s: unexpected transfer timeout\n",
1186 + mmc_hostname(host->mmc));
1187 + bcm2835_sdhost_dumpregs(host);
1188 + }
1189 +
1190 + bcm2835_sdhost_write(host, SDHSTS_TRANSFER_ERROR_MASK,
1191 + SDHSTS);
1192 +
1193 + host->data->error = -ETIMEDOUT;
1194 +
1195 + bcm2835_sdhost_finish_data(host);
1196 + }
1197 +
1198 + mmiowb();
1199 + spin_unlock_irqrestore(&host->lock, flags);
1200 +}
1201 +
1202 +static void bcm2835_sdhost_enable_sdio_irq_nolock(struct bcm2835_host *host, int enable)
1203 +{
1204 + if (enable)
1205 + host->hcfg |= SDHCFG_SDIO_IRPT_EN;
1206 + else
1207 + host->hcfg &= ~SDHCFG_SDIO_IRPT_EN;
1208 + bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
1209 + mmiowb();
1210 +}
1211 +
1212 +static void bcm2835_sdhost_enable_sdio_irq(struct mmc_host *mmc, int enable)
1213 +{
1214 + struct bcm2835_host *host = mmc_priv(mmc);
1215 + unsigned long flags;
1216 +
1217 + pr_debug("%s: enable_sdio_irq(%d)\n", mmc_hostname(mmc), enable);
1218 + spin_lock_irqsave(&host->lock, flags);
1219 + bcm2835_sdhost_enable_sdio_irq_nolock(host, enable);
1220 + spin_unlock_irqrestore(&host->lock, flags);
1221 +}
1222 +
1223 +static u32 bcm2835_sdhost_busy_irq(struct bcm2835_host *host, u32 intmask)
1224 +{
1225 + const u32 handled = (SDHSTS_REW_TIME_OUT | SDHSTS_CMD_TIME_OUT |
1226 + SDHSTS_CRC16_ERROR | SDHSTS_CRC7_ERROR |
1227 + SDHSTS_FIFO_ERROR);
1228 +
1229 + if (!host->cmd) {
1230 + pr_err("%s: got command busy interrupt 0x%08x even "
1231 + "though no command operation was in progress.\n",
1232 + mmc_hostname(host->mmc), (unsigned)intmask);
1233 + bcm2835_sdhost_dumpregs(host);
1234 + return 0;
1235 + }
1236 +
1237 + if (!host->use_busy) {
1238 + pr_err("%s: got command busy interrupt 0x%08x even "
1239 + "though not expecting one.\n",
1240 + mmc_hostname(host->mmc), (unsigned)intmask);
1241 + bcm2835_sdhost_dumpregs(host);
1242 + return 0;
1243 + }
1244 + host->use_busy = 0;
1245 +
1246 + if (intmask & SDHSTS_ERROR_MASK)
1247 + {
1248 + pr_err("sdhost_busy_irq: intmask %x, data %p\n", intmask, host->mrq->data);
1249 + if (intmask & SDHSTS_CRC7_ERROR)
1250 + host->cmd->error = -EILSEQ;
1251 + else if (intmask & (SDHSTS_CRC16_ERROR |
1252 + SDHSTS_FIFO_ERROR)) {
1253 + if (host->mrq->data)
1254 + host->mrq->data->error = -EILSEQ;
1255 + else
1256 + host->cmd->error = -EILSEQ;
1257 + } else if (intmask & SDHSTS_REW_TIME_OUT) {
1258 + if (host->mrq->data)
1259 + host->mrq->data->error = -ETIMEDOUT;
1260 + else
1261 + host->cmd->error = -ETIMEDOUT;
1262 + } else if (intmask & SDHSTS_CMD_TIME_OUT)
1263 + host->cmd->error = -ETIMEDOUT;
1264 +
1265 + bcm2835_sdhost_dumpregs(host);
1266 + tasklet_schedule(&host->finish_tasklet);
1267 + }
1268 + else
1269 + bcm2835_sdhost_finish_command(host);
1270 +
1271 + return handled;
1272 +}
1273 +
1274 +static u32 bcm2835_sdhost_data_irq(struct bcm2835_host *host, u32 intmask)
1275 +{
1276 + const u32 handled = (SDHSTS_REW_TIME_OUT |
1277 + SDHSTS_CRC16_ERROR |
1278 + SDHSTS_FIFO_ERROR);
1279 +
1280 + /* There are no dedicated data/space available interrupt
1281 + status bits, so it is necessary to use the single shared
1282 + data/space available FIFO status bits. It is therefore not
1283 + an error to get here when there is no data transfer in
1284 + progress. */
1285 + if (!host->data)
1286 + return 0;
1287 +
1288 + if (intmask & (SDHSTS_CRC16_ERROR |
1289 + SDHSTS_FIFO_ERROR |
1290 + SDHSTS_REW_TIME_OUT)) {
1291 + if (intmask & (SDHSTS_CRC16_ERROR |
1292 + SDHSTS_FIFO_ERROR))
1293 + host->data->error = -EILSEQ;
1294 + else
1295 + host->data->error = -ETIMEDOUT;
1296 +
1297 + bcm2835_sdhost_dumpregs(host);
1298 + tasklet_schedule(&host->finish_tasklet);
1299 + return handled;
1300 + }
1301 +
1302 + /* Use the block interrupt for writes after the first block */
1303 + if (host->data->flags & MMC_DATA_WRITE) {
1304 + host->hcfg &= ~(SDHCFG_DATA_IRPT_EN);
1305 + host->hcfg |= SDHCFG_BLOCK_IRPT_EN;
1306 + bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
1307 + if (host->data->error)
1308 + bcm2835_sdhost_finish_data(host);
1309 + else
1310 + bcm2835_sdhost_transfer_pio(host);
1311 + } else {
1312 + if (!host->data->error) {
1313 + bcm2835_sdhost_transfer_pio(host);
1314 + host->blocks--;
1315 + }
1316 + if ((host->blocks == 0) || host->data->error)
1317 + bcm2835_sdhost_finish_data(host);
1318 + }
1319 +
1320 + return handled;
1321 +}
1322 +
1323 +static u32 bcm2835_sdhost_block_irq(struct bcm2835_host *host, u32 intmask)
1324 +{
1325 + struct dma_chan *dma_chan;
1326 + u32 dir_data;
1327 + const u32 handled = (SDHSTS_REW_TIME_OUT |
1328 + SDHSTS_CRC16_ERROR |
1329 + SDHSTS_FIFO_ERROR);
1330 +
1331 + if (!host->data) {
1332 + pr_err("%s: got block interrupt 0x%08x even "
1333 + "though no data operation was in progress.\n",
1334 + mmc_hostname(host->mmc), (unsigned)intmask);
1335 + bcm2835_sdhost_dumpregs(host);
1336 + return handled;
1337 + }
1338 +
1339 + if (intmask & (SDHSTS_CRC16_ERROR |
1340 + SDHSTS_FIFO_ERROR |
1341 + SDHSTS_REW_TIME_OUT)) {
1342 + if (intmask & (SDHSTS_CRC16_ERROR |
1343 + SDHSTS_FIFO_ERROR))
1344 + host->data->error = -EILSEQ;
1345 + else
1346 + host->data->error = -ETIMEDOUT;
1347 +
1348 + if (host->debug)
1349 + bcm2835_sdhost_dumpregs(host);
1350 + tasklet_schedule(&host->finish_tasklet);
1351 + return handled;
1352 + }
1353 +
1354 + if (!host->use_dma) {
1355 + BUG_ON(!host->blocks);
1356 + host->blocks--;
1357 + if ((host->blocks == 0) || host->data->error) {
1358 + /* Cancel the timer */
1359 + del_timer(&host->pio_timer);
1360 +
1361 + bcm2835_sdhost_finish_data(host);
1362 + } else {
1363 + bcm2835_sdhost_transfer_pio(host);
1364 +
1365 + /* Reset the timer */
1366 + mod_timer(&host->pio_timer,
1367 + jiffies + host->pio_timeout);
1368 + }
1369 + } else if (host->data->flags & MMC_DATA_WRITE) {
1370 + dma_chan = host->dma_chan_tx;
1371 + dir_data = DMA_TO_DEVICE;
1372 + dma_unmap_sg(dma_chan->device->dev,
1373 + host->data->sg, host->data->sg_len,
1374 + dir_data);
1375 +
1376 + bcm2835_sdhost_finish_data(host);
1377 + }
1378 +
1379 + return handled;
1380 +}
1381 +
1382 +
1383 +static irqreturn_t bcm2835_sdhost_irq(int irq, void *dev_id)
1384 +{
1385 + irqreturn_t result = IRQ_NONE;
1386 + struct bcm2835_host *host = dev_id;
1387 + u32 unexpected = 0, early = 0;
1388 + int loops = 0;
1389 +
1390 + spin_lock(&host->lock);
1391 +
1392 + for (loops = 0; loops < 1; loops++) {
1393 + u32 intmask, handled;
1394 +
1395 + intmask = bcm2835_sdhost_read(host, SDHSTS);
1396 + handled = intmask & (SDHSTS_BUSY_IRPT |
1397 + SDHSTS_BLOCK_IRPT |
1398 + SDHSTS_SDIO_IRPT |
1399 + SDHSTS_DATA_FLAG);
1400 + if ((handled == SDHSTS_DATA_FLAG) &&
1401 + (loops == 0) && !host->data) {
1402 + pr_err("%s: sdhost_irq data interrupt 0x%08x even "
1403 + "though no data operation was in progress.\n",
1404 + mmc_hostname(host->mmc),
1405 + (unsigned)intmask);
1406 +
1407 + bcm2835_sdhost_dumpregs(host);
1408 + }
1409 +
1410 + if (!handled)
1411 + break;
1412 +
1413 + if (loops)
1414 + early |= handled;
1415 +
1416 + result = IRQ_HANDLED;
1417 +
1418 + /* Clear all interrupts and notifications */
1419 + bcm2835_sdhost_write(host, intmask, SDHSTS);
1420 +
1421 + if (intmask & SDHSTS_BUSY_IRPT)
1422 + handled |= bcm2835_sdhost_busy_irq(host, intmask);
1423 +
1424 + /* There is no true data interrupt status bit, so it is
1425 + necessary to qualify the data flag with the interrupt
1426 + enable bit */
1427 + if ((intmask & SDHSTS_DATA_FLAG) &&
1428 + (host->hcfg & SDHCFG_DATA_IRPT_EN))
1429 + handled |= bcm2835_sdhost_data_irq(host, intmask);
1430 +
1431 + if (intmask & SDHSTS_BLOCK_IRPT)
1432 + handled |= bcm2835_sdhost_block_irq(host, intmask);
1433 +
1434 + if (intmask & SDHSTS_SDIO_IRPT) {
1435 + bcm2835_sdhost_enable_sdio_irq_nolock(host, false);
1436 + host->thread_isr |= SDHSTS_SDIO_IRPT;
1437 + result = IRQ_WAKE_THREAD;
1438 + }
1439 +
1440 + unexpected |= (intmask & ~handled);
1441 + }
1442 +
1443 + mmiowb();
1444 +
1445 + spin_unlock(&host->lock);
1446 +
1447 + if (early)
1448 + pr_debug("%s: early %x (loops %d)\n",
1449 + mmc_hostname(host->mmc), early, loops);
1450 +
1451 + if (unexpected) {
1452 + pr_err("%s: unexpected interrupt 0x%08x.\n",
1453 + mmc_hostname(host->mmc), unexpected);
1454 + bcm2835_sdhost_dumpregs(host);
1455 + }
1456 +
1457 + return result;
1458 +}
1459 +
1460 +static irqreturn_t bcm2835_sdhost_thread_irq(int irq, void *dev_id)
1461 +{
1462 + struct bcm2835_host *host = dev_id;
1463 + unsigned long flags;
1464 + u32 isr;
1465 +
1466 + spin_lock_irqsave(&host->lock, flags);
1467 + isr = host->thread_isr;
1468 + host->thread_isr = 0;
1469 + spin_unlock_irqrestore(&host->lock, flags);
1470 +
1471 + if (isr & SDHSTS_SDIO_IRPT) {
1472 + sdio_run_irqs(host->mmc);
1473 +
1474 +/* Is this necessary? Why re-enable an interrupt which is enabled?
1475 + spin_lock_irqsave(&host->lock, flags);
1476 + if (host->flags & SDHSTS_SDIO_IRPT_ENABLED)
1477 + bcm2835_sdhost_enable_sdio_irq_nolock(host, true);
1478 + spin_unlock_irqrestore(&host->lock, flags);
1479 +*/
1480 + }
1481 +
1482 + return isr ? IRQ_HANDLED : IRQ_NONE;
1483 +}
1484 +
1485 +
1486 +
1487 +void bcm2835_sdhost_set_clock(struct bcm2835_host *host, unsigned int clock)
1488 +{
1489 + int div = 0; /* Initialized for compiler warning */
1490 + unsigned int input_clock = clock;
1491 +
1492 + if (host->debug)
1493 + pr_info("%s: set_clock(%d)\n", mmc_hostname(host->mmc), clock);
1494 +
1495 + if ((host->overclock_50 > 50) &&
1496 + (clock == 50*MHZ)) {
1497 + clock = host->overclock_50 * MHZ + (MHZ - 1);
1498 + }
1499 +
1500 + /* The SDCDIV register has 11 bits, and holds (div - 2).
1501 + But in data mode the max is 50MHz wihout a minimum, and only the
1502 + bottom 3 bits are used. Since the switch over is automatic (unless
1503 + we have marked the card as slow...), chosen values have to make
1504 + sense in both modes.
1505 + Ident mode must be 100-400KHz, so can range check the requested
1506 + clock. CMD15 must be used to return to data mode, so this can be
1507 + monitored.
1508 +
1509 + clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz
1510 + 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz
1511 +
1512 + 623->400KHz/27.8MHz
1513 + reset value (507)->491159/50MHz
1514 +
1515 + BUT, the 3-bit clock divisor in data mode is too small if the
1516 + core clock is higher than 250MHz, so instead use the SLOW_CARD
1517 + configuration bit to force the use of the ident clock divisor
1518 + at all times.
1519 + */
1520 +
1521 + host->mmc->actual_clock = 0;
1522 +
1523 + if (clock < 100000) {
1524 + /* Can't stop the clock, but make it as slow as possible
1525 + * to show willing
1526 + */
1527 + host->cdiv = SDCDIV_MAX_CDIV;
1528 + bcm2835_sdhost_write(host, host->cdiv, SDCDIV);
1529 + return;
1530 + }
1531 +
1532 + div = host->max_clk / clock;
1533 + if (div < 2)
1534 + div = 2;
1535 + if ((host->max_clk / div) > clock)
1536 + div++;
1537 + div -= 2;
1538 +
1539 + if (div > SDCDIV_MAX_CDIV)
1540 + div = SDCDIV_MAX_CDIV;
1541 +
1542 + clock = host->max_clk / (div + 2);
1543 + host->mmc->actual_clock = clock;
1544 +
1545 + if (clock > input_clock) {
1546 + /* Save the closest value, to make it easier
1547 + to reduce in the event of error */
1548 + host->overclock_50 = (clock/MHZ);
1549 +
1550 + if (clock != host->overclock) {
1551 + pr_warn("%s: overclocking to %dHz\n",
1552 + mmc_hostname(host->mmc), clock);
1553 + host->overclock = clock;
1554 + }
1555 + }
1556 + else if (host->overclock)
1557 + {
1558 + host->overclock = 0;
1559 + if (clock == 50 * MHZ)
1560 + pr_warn("%s: cancelling overclock\n",
1561 + mmc_hostname(host->mmc));
1562 + }
1563 +
1564 + host->cdiv = div;
1565 + bcm2835_sdhost_write(host, host->cdiv, SDCDIV);
1566 +
1567 + /* Set the timeout to 500ms */
1568 + bcm2835_sdhost_write(host, host->mmc->actual_clock/2, SDTOUT);
1569 +
1570 + if (host->debug)
1571 + pr_info("%s: clock=%d -> max_clk=%d, cdiv=%x (actual clock %d)\n",
1572 + mmc_hostname(host->mmc), input_clock,
1573 + host->max_clk, host->cdiv, host->mmc->actual_clock);
1574 +}
1575 +
1576 +static void bcm2835_sdhost_request(struct mmc_host *mmc, struct mmc_request *mrq)
1577 +{
1578 + struct bcm2835_host *host;
1579 + unsigned long flags;
1580 +
1581 + host = mmc_priv(mmc);
1582 +
1583 + if (host->debug) {
1584 + struct mmc_command *cmd = mrq->cmd;
1585 + BUG_ON(!cmd);
1586 + if (cmd->data)
1587 + pr_info("%s: cmd %d 0x%x (flags 0x%x) - %s %d*%d\n",
1588 + mmc_hostname(mmc),
1589 + cmd->opcode, cmd->arg, cmd->flags,
1590 + (cmd->data->flags & MMC_DATA_READ) ?
1591 + "read" : "write", cmd->data->blocks,
1592 + cmd->data->blksz);
1593 + else
1594 + pr_info("%s: cmd %d 0x%x (flags 0x%x)\n",
1595 + mmc_hostname(mmc),
1596 + cmd->opcode, cmd->arg, cmd->flags);
1597 + }
1598 +
1599 + /* Reset the error statuses in case this is a retry */
1600 + if (mrq->cmd)
1601 + mrq->cmd->error = 0;
1602 + if (mrq->data)
1603 + mrq->data->error = 0;
1604 + if (mrq->stop)
1605 + mrq->stop->error = 0;
1606 +
1607 + if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
1608 + pr_err("%s: unsupported block size (%d bytes)\n",
1609 + mmc_hostname(mmc), mrq->data->blksz);
1610 + mrq->cmd->error = -EINVAL;
1611 + mmc_request_done(mmc, mrq);
1612 + return;
1613 + }
1614 +
1615 + spin_lock_irqsave(&host->lock, flags);
1616 +
1617 + WARN_ON(host->mrq != NULL);
1618 +
1619 + host->mrq = mrq;
1620 +
1621 + if (mrq->sbc)
1622 + bcm2835_sdhost_send_command(host, mrq->sbc);
1623 + else
1624 + bcm2835_sdhost_send_command(host, mrq->cmd);
1625 +
1626 + mmiowb();
1627 + spin_unlock_irqrestore(&host->lock, flags);
1628 +
1629 + if (!mrq->sbc && mrq->cmd->data && host->use_dma)
1630 + /* DMA transfer starts now, PIO starts after irq */
1631 + bcm2835_sdhost_transfer_dma(host);
1632 +
1633 + if (!host->use_busy)
1634 + bcm2835_sdhost_finish_command(host);
1635 +}
1636 +
1637 +
1638 +static void bcm2835_sdhost_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1639 +{
1640 +
1641 + struct bcm2835_host *host = mmc_priv(mmc);
1642 + unsigned long flags;
1643 +
1644 + if (host->debug)
1645 + pr_info("%s: ios clock %d, pwr %d, bus_width %d, "
1646 + "timing %d, vdd %d, drv_type %d\n",
1647 + mmc_hostname(mmc),
1648 + ios->clock, ios->power_mode, ios->bus_width,
1649 + ios->timing, ios->signal_voltage, ios->drv_type);
1650 +
1651 + spin_lock_irqsave(&host->lock, flags);
1652 +
1653 + if (!ios->clock || ios->clock != host->clock) {
1654 + bcm2835_sdhost_set_clock(host, ios->clock);
1655 + host->clock = ios->clock;
1656 + }
1657 +
1658 + /* set bus width */
1659 + host->hcfg &= ~SDHCFG_WIDE_EXT_BUS;
1660 + if (ios->bus_width == MMC_BUS_WIDTH_4)
1661 + host->hcfg |= SDHCFG_WIDE_EXT_BUS;
1662 +
1663 + host->hcfg |= SDHCFG_WIDE_INT_BUS;
1664 +
1665 + /* Disable clever clock switching, to cope with fast core clocks */
1666 + host->hcfg |= SDHCFG_SLOW_CARD;
1667 +
1668 + bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
1669 +
1670 + mmiowb();
1671 +
1672 + spin_unlock_irqrestore(&host->lock, flags);
1673 +}
1674 +
1675 +static int bcm2835_sdhost_multi_io_quirk(struct mmc_card *card,
1676 + unsigned int direction,
1677 + u32 blk_pos, int blk_size)
1678 +{
1679 + /* There is a bug in the host controller hardware that makes
1680 + reading the final sector of the card as part of a multiple read
1681 + problematic. Detect that case and shorten the read accordingly.
1682 + */
1683 + /* csd.capacity is in weird units - convert to sectors */
1684 + u32 card_sectors = (card->csd.capacity << (card->csd.read_blkbits - 9));
1685 +
1686 + if ((direction == MMC_DATA_READ) &&
1687 + ((blk_pos + blk_size) == card_sectors))
1688 + blk_size--;
1689 +
1690 + return blk_size;
1691 +}
1692 +
1693 +
1694 +static struct mmc_host_ops bcm2835_sdhost_ops = {
1695 + .request = bcm2835_sdhost_request,
1696 + .set_ios = bcm2835_sdhost_set_ios,
1697 + .enable_sdio_irq = bcm2835_sdhost_enable_sdio_irq,
1698 + .hw_reset = bcm2835_sdhost_reset,
1699 + .multi_io_quirk = bcm2835_sdhost_multi_io_quirk,
1700 +};
1701 +
1702 +
1703 +static void bcm2835_sdhost_tasklet_finish(unsigned long param)
1704 +{
1705 + struct bcm2835_host *host;
1706 + unsigned long flags;
1707 + struct mmc_request *mrq;
1708 +
1709 + host = (struct bcm2835_host *)param;
1710 +
1711 + spin_lock_irqsave(&host->lock, flags);
1712 +
1713 + /*
1714 + * If this tasklet gets rescheduled while running, it will
1715 + * be run again afterwards but without any active request.
1716 + */
1717 + if (!host->mrq) {
1718 + spin_unlock_irqrestore(&host->lock, flags);
1719 + return;
1720 + }
1721 +
1722 + del_timer(&host->timer);
1723 +
1724 + mrq = host->mrq;
1725 +
1726 + /* Drop the overclock after any data corruption, or after any
1727 + error overclocked */
1728 + if (host->overclock) {
1729 + if ((mrq->cmd && mrq->cmd->error) ||
1730 + (mrq->data && mrq->data->error) ||
1731 + (mrq->stop && mrq->stop->error)) {
1732 + host->overclock_50--;
1733 + pr_warn("%s: reducing overclock due to errors\n",
1734 + mmc_hostname(host->mmc));
1735 + bcm2835_sdhost_set_clock(host,50*MHZ);
1736 + mrq->cmd->error = -EILSEQ;
1737 + mrq->cmd->retries = 1;
1738 + }
1739 + }
1740 +
1741 + host->mrq = NULL;
1742 + host->cmd = NULL;
1743 + host->data = NULL;
1744 +
1745 + mmiowb();
1746 +
1747 + spin_unlock_irqrestore(&host->lock, flags);
1748 + mmc_request_done(host->mmc, mrq);
1749 +}
1750 +
1751 +
1752 +
1753 +int bcm2835_sdhost_add_host(struct bcm2835_host *host)
1754 +{
1755 + struct mmc_host *mmc;
1756 + struct dma_slave_config cfg;
1757 + char pio_limit_string[20];
1758 + int ret;
1759 +
1760 + mmc = host->mmc;
1761 +
1762 + bcm2835_sdhost_reset_internal(host);
1763 +
1764 + mmc->f_max = host->max_clk;
1765 + mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV;
1766 +
1767 + mmc->max_busy_timeout = (~(unsigned int)0)/(mmc->f_max/1000);
1768 +
1769 + pr_debug("f_max %d, f_min %d, max_busy_timeout %d\n",
1770 + mmc->f_max, mmc->f_min, mmc->max_busy_timeout);
1771 +
1772 + /* host controller capabilities */
1773 + mmc->caps |= /* MMC_CAP_SDIO_IRQ |*/ MMC_CAP_4_BIT_DATA |
1774 + MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
1775 + MMC_CAP_NEEDS_POLL | MMC_CAP_HW_RESET | MMC_CAP_ERASE |
1776 + (ALLOW_CMD23 * MMC_CAP_CMD23);
1777 +
1778 + spin_lock_init(&host->lock);
1779 +
1780 + if (host->allow_dma) {
1781 + if (IS_ERR_OR_NULL(host->dma_chan_tx) ||
1782 + IS_ERR_OR_NULL(host->dma_chan_rx)) {
1783 + pr_err("%s: unable to initialise DMA channels. "
1784 + "Falling back to PIO\n",
1785 + mmc_hostname(mmc));
1786 + host->have_dma = false;
1787 + } else {
1788 + host->have_dma = true;
1789 +
1790 + cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1791 + cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1792 + cfg.slave_id = 13; /* DREQ channel */
1793 +
1794 + cfg.direction = DMA_MEM_TO_DEV;
1795 + cfg.src_addr = 0;
1796 + cfg.dst_addr = host->bus_addr + SDDATA;
1797 + ret = dmaengine_slave_config(host->dma_chan_tx, &cfg);
1798 +
1799 + cfg.direction = DMA_DEV_TO_MEM;
1800 + cfg.src_addr = host->bus_addr + SDDATA;
1801 + cfg.dst_addr = 0;
1802 + ret = dmaengine_slave_config(host->dma_chan_rx, &cfg);
1803 + }
1804 + } else {
1805 + host->have_dma = false;
1806 + }
1807 +
1808 + mmc->max_segs = 128;
1809 + mmc->max_req_size = 524288;
1810 + mmc->max_seg_size = mmc->max_req_size;
1811 + mmc->max_blk_size = 512;
1812 + mmc->max_blk_count = 65535;
1813 +
1814 + /* report supported voltage ranges */
1815 + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1816 +
1817 + tasklet_init(&host->finish_tasklet,
1818 + bcm2835_sdhost_tasklet_finish, (unsigned long)host);
1819 +
1820 + setup_timer(&host->timer, bcm2835_sdhost_timeout,
1821 + (unsigned long)host);
1822 +
1823 + setup_timer(&host->pio_timer, bcm2835_sdhost_pio_timeout,
1824 + (unsigned long)host);
1825 +
1826 + bcm2835_sdhost_init(host, 0);
1827 + ret = request_threaded_irq(host->irq, bcm2835_sdhost_irq,
1828 + bcm2835_sdhost_thread_irq,
1829 + IRQF_SHARED, mmc_hostname(mmc), host);
1830 + if (ret) {
1831 + pr_err("%s: failed to request IRQ %d: %d\n",
1832 + mmc_hostname(mmc), host->irq, ret);
1833 + goto untasklet;
1834 + }
1835 +
1836 + mmiowb();
1837 + mmc_add_host(mmc);
1838 +
1839 + pio_limit_string[0] = '\0';
1840 + if (host->have_dma && (host->pio_limit > 0))
1841 + sprintf(pio_limit_string, " (>%d)", host->pio_limit);
1842 + pr_info("%s: %s loaded - DMA %s%s\n",
1843 + mmc_hostname(mmc), DRIVER_NAME,
1844 + host->have_dma ? "enabled" : "disabled",
1845 + pio_limit_string);
1846 +
1847 + return 0;
1848 +
1849 +untasklet:
1850 + tasklet_kill(&host->finish_tasklet);
1851 +
1852 + return ret;
1853 +}
1854 +
1855 +static int bcm2835_sdhost_probe(struct platform_device *pdev)
1856 +{
1857 + struct device *dev = &pdev->dev;
1858 + struct device_node *node = dev->of_node;
1859 + struct clk *clk;
1860 + struct resource *iomem;
1861 + struct bcm2835_host *host;
1862 + struct mmc_host *mmc;
1863 + const __be32 *addr;
1864 + int ret;
1865 +
1866 + pr_debug("bcm2835_sdhost_probe\n");
1867 + mmc = mmc_alloc_host(sizeof(*host), dev);
1868 + if (!mmc)
1869 + return -ENOMEM;
1870 +
1871 + mmc->ops = &bcm2835_sdhost_ops;
1872 + host = mmc_priv(mmc);
1873 + host->mmc = mmc;
1874 + host->pio_timeout = msecs_to_jiffies(500);
1875 + host->max_delay = 1; /* Warn if over 1ms */
1876 + spin_lock_init(&host->lock);
1877 +
1878 + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1879 + host->ioaddr = devm_ioremap_resource(dev, iomem);
1880 + if (IS_ERR(host->ioaddr)) {
1881 + ret = PTR_ERR(host->ioaddr);
1882 + goto err;
1883 + }
1884 +
1885 + addr = of_get_address(node, 0, NULL, NULL);
1886 + if (!addr) {
1887 + dev_err(dev, "could not get DMA-register address\n");
1888 + return -ENODEV;
1889 + }
1890 + host->bus_addr = be32_to_cpup(addr);
1891 + pr_debug(" - ioaddr %lx, iomem->start %lx, bus_addr %lx\n",
1892 + (unsigned long)host->ioaddr,
1893 + (unsigned long)iomem->start,
1894 + (unsigned long)host->bus_addr);
1895 +
1896 + host->allow_dma = ALLOW_DMA;
1897 +
1898 + if (node) {
1899 + /* Read any custom properties */
1900 + of_property_read_u32(node,
1901 + "brcm,delay-after-stop",
1902 + &host->delay_after_stop);
1903 + of_property_read_u32(node,
1904 + "brcm,overclock-50",
1905 + &host->overclock_50);
1906 + of_property_read_u32(node,
1907 + "brcm,pio-limit",
1908 + &host->pio_limit);
1909 + host->allow_dma = ALLOW_DMA &&
1910 + !of_property_read_bool(node, "brcm,force-pio");
1911 + host->debug = of_property_read_bool(node, "brcm,debug");
1912 + }
1913 +
1914 + if (host->allow_dma) {
1915 + if (node) {
1916 + host->dma_chan_tx =
1917 + dma_request_slave_channel(dev, "tx");
1918 + host->dma_chan_rx =
1919 + dma_request_slave_channel(dev, "rx");
1920 + } else {
1921 + dma_cap_mask_t mask;
1922 +
1923 + dma_cap_zero(mask);
1924 + /* we don't care about the channel, any would work */
1925 + dma_cap_set(DMA_SLAVE, mask);
1926 + host->dma_chan_tx =
1927 + dma_request_channel(mask, NULL, NULL);
1928 + host->dma_chan_rx =
1929 + dma_request_channel(mask, NULL, NULL);
1930 + }
1931 + }
1932 +
1933 + clk = devm_clk_get(dev, NULL);
1934 + if (IS_ERR(clk)) {
1935 + dev_err(dev, "could not get clk\n");
1936 + ret = PTR_ERR(clk);
1937 + goto err;
1938 + }
1939 +
1940 + host->max_clk = clk_get_rate(clk);
1941 +
1942 + host->irq = platform_get_irq(pdev, 0);
1943 + if (host->irq <= 0) {
1944 + dev_err(dev, "get IRQ failed\n");
1945 + ret = -EINVAL;
1946 + goto err;
1947 + }
1948 +
1949 + pr_debug(" - max_clk %lx, irq %d\n",
1950 + (unsigned long)host->max_clk,
1951 + (int)host->irq);
1952 +
1953 + if (node)
1954 + mmc_of_parse(mmc);
1955 + else
1956 + mmc->caps |= MMC_CAP_4_BIT_DATA;
1957 +
1958 + ret = bcm2835_sdhost_add_host(host);
1959 + if (ret)
1960 + goto err;
1961 +
1962 + platform_set_drvdata(pdev, host);
1963 +
1964 + pr_debug("bcm2835_sdhost_probe -> OK\n");
1965 +
1966 + return 0;
1967 +
1968 +err:
1969 + pr_debug("bcm2835_sdhost_probe -> err %d\n", ret);
1970 + mmc_free_host(mmc);
1971 +
1972 + return ret;
1973 +}
1974 +
1975 +static int bcm2835_sdhost_remove(struct platform_device *pdev)
1976 +{
1977 + struct bcm2835_host *host = platform_get_drvdata(pdev);
1978 +
1979 + pr_debug("bcm2835_sdhost_remove\n");
1980 +
1981 + mmc_remove_host(host->mmc);
1982 +
1983 + bcm2835_sdhost_set_power(host, false);
1984 +
1985 + free_irq(host->irq, host);
1986 +
1987 + del_timer_sync(&host->timer);
1988 +
1989 + tasklet_kill(&host->finish_tasklet);
1990 +
1991 + mmc_free_host(host->mmc);
1992 + platform_set_drvdata(pdev, NULL);
1993 +
1994 + pr_debug("bcm2835_sdhost_remove - OK\n");
1995 + return 0;
1996 +}
1997 +
1998 +
1999 +static const struct of_device_id bcm2835_sdhost_match[] = {
2000 + { .compatible = "brcm,bcm2835-sdhost" },
2001 + { }
2002 +};
2003 +MODULE_DEVICE_TABLE(of, bcm2835_sdhost_match);
2004 +
2005 +
2006 +
2007 +static struct platform_driver bcm2835_sdhost_driver = {
2008 + .probe = bcm2835_sdhost_probe,
2009 + .remove = bcm2835_sdhost_remove,
2010 + .driver = {
2011 + .name = DRIVER_NAME,
2012 + .owner = THIS_MODULE,
2013 + .of_match_table = bcm2835_sdhost_match,
2014 + },
2015 +};
2016 +module_platform_driver(bcm2835_sdhost_driver);
2017 +
2018 +MODULE_ALIAS("platform:sdhost-bcm2835");
2019 +MODULE_DESCRIPTION("BCM2835 SDHost driver");
2020 +MODULE_LICENSE("GPL v2");
2021 +MODULE_AUTHOR("Phil Elwell");
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