target/linux/brcm2708/patches-4.4/0255-clk-bcm2835-added-missing-clock-register-definitions.patch

   1 From 324fca092b17a2affebeb89a35f53b6512ded4d0 Mon Sep 17 00:00:00 2001
   2 From: Martin Sperl <kernel@martin.sperl.org>
   3 Date: Tue, 22 Dec 2015 20:13:08 +0000
   4 Subject: [PATCH] clk: bcm2835: added missing clock register definitions
   5
   6 Added missing CTRL and DIV clock register definitions for:
   7 PCM, SLIM, TCNT, TEC, TD0, TD1
   8
   9 Register information taken from:
  10 https://rawgit.com/msperl/rpi-registers/master/rpi-registers.html#CM
  11 which extracted the information from the header files shared by
  12 Broadcom/rpi foundation in this file:
  13 http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz
  14
  15 Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
  16 Reviewed-by: Eric Anholt <eric@anholt.net>
  17 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  18 (cherry picked from commit 2103a2156119b30f5924af2a1094227954be4617)
  19 ---
  20  drivers/clk/bcm/clk-bcm2835.c | 13 +++++++++++++
  21  1 file changed, 13 insertions(+)
  22
  23 --- a/drivers/clk/bcm/clk-bcm2835.c
  24 +++ b/drivers/clk/bcm/clk-bcm2835.c
  25 @@ -88,10 +88,23 @@
  26  #define CM_HSMDIV              0x08c
  27  #define CM_OTPCTL              0x090
  28  #define CM_OTPDIV              0x094
  29 +#define CM_PCMCTL              0x098
  30 +#define CM_PCMDIV              0x09c
  31  #define CM_PWMCTL              0x0a0
  32  #define CM_PWMDIV              0x0a4
  33 +#define CM_SLIMCTL             0x0a8
  34 +#define CM_SLIMDIV             0x0ac
  35  #define CM_SMICTL              0x0b0
  36  #define CM_SMIDIV              0x0b4
  37 +/* no definition for 0x0b8  and 0x0bc */
  38 +#define CM_TCNTCTL             0x0c0
  39 +#define CM_TCNTDIV             0x0c4
  40 +#define CM_TECCTL              0x0c8
  41 +#define CM_TECDIV              0x0cc
  42 +#define CM_TD0CTL              0x0d0
  43 +#define CM_TD0DIV              0x0d4
  44 +#define CM_TD1CTL              0x0d8
  45 +#define CM_TD1DIV              0x0dc
  46  #define CM_TSENSCTL            0x0e0
  47  #define CM_TSENSDIV            0x0e4
  48  #define CM_TIMERCTL            0x0e8