target/linux/brcm2708/patches-4.4/0256-clk-bcm2835-pll_off-should-only-update-CM_PLL_ANARST.patch

   1 From 2083f21dc65df8ce4fd887acd815551058b23e3e Mon Sep 17 00:00:00 2001
   2 From: Martin Sperl <kernel@martin.sperl.org>
   3 Date: Mon, 29 Feb 2016 11:39:17 +0000
   4 Subject: [PATCH 256/304] clk: bcm2835: pll_off should only update
   5  CM_PLL_ANARST
   6
   7 bcm2835_pll_off is currently assigning CM_PLL_ANARST to the control
   8 register, which may lose the other bits that are currently set by the
   9 clock dividers.
  10
  11 It also now locks during the read/modify/write cycle of both
  12 registers.
  13
  14 Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the
  15 audio domain clocks")
  16
  17 Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
  18 Signed-off-by: Eric Anholt <eric@anholt.net>
  19 Reviewed-by: Eric Anholt <eric@anholt.net>
  20 (cherry picked from commit 6727f086cfe4ddcc651eb2bf4301abfcf619be06)
  21 ---
  22  drivers/clk/bcm/clk-bcm2835.c | 10 ++++++++--
  23  1 file changed, 8 insertions(+), 2 deletions(-)
  24
  25 --- a/drivers/clk/bcm/clk-bcm2835.c
  26 +++ b/drivers/clk/bcm/clk-bcm2835.c
  27 @@ -913,8 +913,14 @@ static void bcm2835_pll_off(struct clk_h
  28         struct bcm2835_cprman *cprman = pll->cprman;
  29         const struct bcm2835_pll_data *data = pll->data;
  30
  31 -       cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST);
  32 -       cprman_write(cprman, data->a2w_ctrl_reg, A2W_PLL_CTRL_PWRDN);
  33 +       spin_lock(&cprman->regs_lock);
  34 +       cprman_write(cprman, data->cm_ctrl_reg,
  35 +                    cprman_read(cprman, data->cm_ctrl_reg) |
  36 +                    CM_PLL_ANARST);
  37 +       cprman_write(cprman, data->a2w_ctrl_reg,
  38 +                    cprman_read(cprman, data->a2w_ctrl_reg) |
  39 +                    A2W_PLL_CTRL_PWRDN);
  40 +       spin_unlock(&cprman->regs_lock);
  41  }
  42
  43  static int bcm2835_pll_on(struct clk_hw *hw)