target/linux/brcm2708/patches-4.4/0336-drm-vc4-Add-support-for-gamma-ramps.patch

   1 From ad9de9ffedcbcc35c4fe13cddabda66abc98e3ef Mon Sep 17 00:00:00 2001
   2 From: Eric Anholt <eric@anholt.net>
   3 Date: Thu, 31 Mar 2016 18:38:20 -0700
   4 Subject: [PATCH 336/423] drm/vc4: Add support for gamma ramps.
   5
   6 We could possibly save a bit of power by not requesting gamma
   7 conversion when the ramp happens to be 1:1, but at least if all the
   8 CRTCs are off the SRAM will be disabled.
   9
  10 This should fix brightness sliders in a lot of fullscreen games.
  11
  12 Signed-off-by: Eric Anholt <eric@anholt.net>
  13 (cherry picked from commit e582b6c7e7f9d0b1e30e8017e4082d3a9ede3310)
  14 ---
  15  drivers/gpu/drm/vc4/vc4_crtc.c | 58 ++++++++++++++++++++++++++++++++++++++++++
  16  drivers/gpu/drm/vc4/vc4_regs.h |  6 +++++
  17  2 files changed, 64 insertions(+)
  18
  19 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
  20 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
  21 @@ -49,6 +49,10 @@ struct vc4_crtc {
  22         /* Which HVS channel we're using for our CRTC. */
  23         int channel;
  24
  25 +       u8 lut_r[256];
  26 +       u8 lut_g[256];
  27 +       u8 lut_b[256];
  28 +
  29         struct drm_pending_vblank_event *event;
  30  };
  31
  32 @@ -147,6 +151,46 @@ static void vc4_crtc_destroy(struct drm_
  33         drm_crtc_cleanup(crtc);
  34  }
  35
  36 +static void
  37 +vc4_crtc_lut_load(struct drm_crtc *crtc)
  38 +{
  39 +       struct drm_device *dev = crtc->dev;
  40 +       struct vc4_dev *vc4 = to_vc4_dev(dev);
  41 +       struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  42 +       u32 i;
  43 +
  44 +       /* The LUT memory is laid out with each HVS channel in order,
  45 +        * each of which takes 256 writes for R, 256 for G, then 256
  46 +        * for B.
  47 +        */
  48 +       HVS_WRITE(SCALER_GAMADDR,
  49 +                 SCALER_GAMADDR_AUTOINC |
  50 +                 (vc4_crtc->channel * 3 * crtc->gamma_size));
  51 +
  52 +       for (i = 0; i < crtc->gamma_size; i++)
  53 +               HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
  54 +       for (i = 0; i < crtc->gamma_size; i++)
  55 +               HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
  56 +       for (i = 0; i < crtc->gamma_size; i++)
  57 +               HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
  58 +}
  59 +
  60 +static void
  61 +vc4_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
  62 +                  uint32_t start, uint32_t size)
  63 +{
  64 +       struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  65 +       u32 i;
  66 +
  67 +       for (i = start; i < start + size; i++) {
  68 +               vc4_crtc->lut_r[i] = r[i] >> 8;
  69 +               vc4_crtc->lut_g[i] = g[i] >> 8;
  70 +               vc4_crtc->lut_b[i] = b[i] >> 8;
  71 +       }
  72 +
  73 +       vc4_crtc_lut_load(crtc);
  74 +}
  75 +
  76  static u32 vc4_get_fifo_full_level(u32 format)
  77  {
  78         static const u32 fifo_len_bytes = 64;
  79 @@ -260,8 +304,14 @@ static void vc4_crtc_mode_set_nofb(struc
  80
  81         HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
  82                   SCALER_DISPBKGND_AUTOHS |
  83 +                 SCALER_DISPBKGND_GAMMA |
  84                   (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
  85
  86 +       /* Reload the LUT, since the SRAMs would have been disabled if
  87 +        * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
  88 +        */
  89 +       vc4_crtc_lut_load(crtc);
  90 +
  91         if (debug_dump_regs) {
  92                 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
  93                 vc4_crtc_dump_regs(vc4_crtc);
  94 @@ -613,6 +663,7 @@ static const struct drm_crtc_funcs vc4_c
  95         .reset = drm_atomic_helper_crtc_reset,
  96         .atomic_duplicate_state = vc4_crtc_duplicate_state,
  97         .atomic_destroy_state = vc4_crtc_destroy_state,
  98 +       .gamma_set = vc4_crtc_gamma_set,
  99  };
 100
 101  static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
 102 @@ -731,6 +782,7 @@ static int vc4_crtc_bind(struct device *
 103         primary_plane->crtc = crtc;
 104         vc4->crtc[drm_crtc_index(crtc)] = vc4_crtc;
 105         vc4_crtc->channel = vc4_crtc->data->hvs_channel;
 106 +       drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
 107
 108         /* Set up some arbitrary number of planes.  We're not limited
 109          * by a set number of physical registers, just the space in
 110 @@ -771,6 +823,12 @@ static int vc4_crtc_bind(struct device *
 111
 112         vc4_set_crtc_possible_masks(drm, crtc);
 113
 114 +       for (i = 0; i < crtc->gamma_size; i++) {
 115 +               vc4_crtc->lut_r[i] = i;
 116 +               vc4_crtc->lut_g[i] = i;
 117 +               vc4_crtc->lut_b[i] = i;
 118 +       }
 119 +
 120         platform_set_drvdata(pdev, vc4_crtc);
 121
 122         return 0;
 123 --- a/drivers/gpu/drm/vc4/vc4_regs.h
 124 +++ b/drivers/gpu/drm/vc4/vc4_regs.h
 125 @@ -390,6 +390,12 @@
 126  #define SCALER_DISPBASE2                        0x0000006c
 127  #define SCALER_DISPALPHA2                       0x00000070
 128  #define SCALER_GAMADDR                          0x00000078
 129 +# define SCALER_GAMADDR_AUTOINC                        BIT(31)
 130 +/* Enables all gamma ramp SRAMs, not just those of CRTCs with gamma
 131 + * enabled.
 132 + */
 133 +# define SCALER_GAMADDR_SRAMENB                        BIT(30)
 134 +
 135  #define SCALER_GAMDATA                          0x000000e0
 136  #define SCALER_DLIST_START                      0x00002000
 137  #define SCALER_DLIST_SIZE                       0x00004000