target/linux/brcm2708/patches-4.4/0432-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-divi.patch

   1 From bf239659e82c137de23c322fa852b24a0acd3156 Mon Sep 17 00:00:00 2001
   2 From: Eric Anholt <eric@anholt.net>
   3 Date: Thu, 31 Mar 2016 12:51:04 -0700
   4 Subject: [PATCH] clk: bcm2835: Don't rate change PLLs on behalf of dividers.
   5
   6 Our core PLLs are intended to be configured once and left alone.  With
   7 the flag set, asking to set the PLLD_DSI1 clock rate would change PLLD
   8 just to get closer to the requested DSI clock, thus changing PLLD_PER,
   9 the UART and ethernet PHY clock rates downstream of it, and breaking
  10 ethernet.
  11
  12 Signed-off-by: Eric Anholt <eric@anholt.net>
  13 ---
  14  drivers/clk/bcm/clk-bcm2835.c | 2 +-
  15  1 file changed, 1 insertion(+), 1 deletion(-)
  16
  17 --- a/drivers/clk/bcm/clk-bcm2835.c
  18 +++ b/drivers/clk/bcm/clk-bcm2835.c
  19 @@ -1215,7 +1215,7 @@ bcm2835_register_pll_divider(struct bcm2
  20         init.num_parents = 1;
  21         init.name = divider_name;
  22         init.ops = &bcm2835_pll_divider_clk_ops;
  23 -       init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED;
  24 +       init.flags = CLK_IGNORE_UNUSED;
  25
  26         divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);
  27         if (!divider)