kernel: bump kernel 4.4 to 4.4.129 for 17.01
[openwrt/openwrt.git] / target / linux / brcm2708 / patches-4.4 / 0434-clk-bcm2835-Add-an-enum-for-the-DSI1-pixel-clock.patch
1 From 105aa2411add3d0d8bb815109e4a6fb6c778a1d2 Mon Sep 17 00:00:00 2001
2 From: Eric Anholt <eric@anholt.net>
3 Date: Thu, 14 Apr 2016 19:00:33 -0700
4 Subject: [PATCH] clk: bcm2835: Add an enum for the DSI1 pixel clock.
5
6 Signed-off-by: Eric Anholt <eric@anholt.net>
7 ---
8 drivers/clk/bcm/clk-bcm2835.c | 39 +++++++++++++++++++++++++++++++++++--
9 include/dt-bindings/clock/bcm2835.h | 1 +
10 2 files changed, 38 insertions(+), 2 deletions(-)
11
12 --- a/drivers/clk/bcm/clk-bcm2835.c
13 +++ b/drivers/clk/bcm/clk-bcm2835.c
14 @@ -942,6 +942,9 @@ static long bcm2835_clock_rate_from_divi
15 const struct bcm2835_clock_data *data = clock->data;
16 u64 temp;
17
18 + if (data->int_bits == 0 && data->frac_bits == 0)
19 + return parent_rate;
20 +
21 /*
22 * The divisor is a 12.12 fixed point field, but only some of
23 * the bits are populated in any given clock.
24 @@ -965,7 +968,12 @@ static unsigned long bcm2835_clock_get_r
25 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
26 struct bcm2835_cprman *cprman = clock->cprman;
27 const struct bcm2835_clock_data *data = clock->data;
28 - u32 div = cprman_read(cprman, data->div_reg);
29 + u32 div;
30 +
31 + if (data->int_bits == 0 && data->frac_bits == 0)
32 + return parent_rate;
33 +
34 + div = cprman_read(cprman, data->div_reg);
35
36 return bcm2835_clock_rate_from_divisor(clock, parent_rate, div);
37 }
38 @@ -1411,6 +1419,28 @@ static const char *const bcm2835_clock_v
39 __VA_ARGS__)
40
41 /*
42 + * DSI1 parent clocks. The DSI1 byte clock comes from the DSI1 PHY,
43 + * which in turn sources from plld_dsi1.
44 + */
45 +static const char *const bcm2835_clock_dsi1_parents[] = {
46 + "gnd",
47 + "xosc",
48 + "testdebug0",
49 + "testdebug1",
50 + "dsi1_ddr",
51 + "dsi1_ddr_inv",
52 + "dsi1_ddr2",
53 + "dsi1_ddr2_inv",
54 + "dsi1_byte",
55 + "dsi1_byte_inv",
56 +};
57 +
58 +#define REGISTER_DSI1_CLK(...) REGISTER_CLK( \
59 + .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents), \
60 + .parents = bcm2835_clock_dsi1_parents, \
61 + __VA_ARGS__)
62 +
63 +/*
64 * the real definition of all the pll, pll_dividers and clocks
65 * these make use of the above REGISTER_* macros
66 */
67 @@ -1855,7 +1885,12 @@ static const struct bcm2835_clk_desc clk
68 .div_reg = CM_DSI1EDIV,
69 .int_bits = 4,
70 .frac_bits = 8),
71 -
72 + [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK(
73 + .name = "dsi1p",
74 + .ctl_reg = CM_DSI1PCTL,
75 + .div_reg = CM_DSI1PDIV,
76 + .int_bits = 0,
77 + .frac_bits = 0),
78 /* the gates */
79
80 /*
81 --- a/include/dt-bindings/clock/bcm2835.h
82 +++ b/include/dt-bindings/clock/bcm2835.h
83 @@ -64,3 +64,4 @@
84 #define BCM2835_CLOCK_CAM1 46
85 #define BCM2835_CLOCK_DSI0E 47
86 #define BCM2835_CLOCK_DSI1E 48
87 +#define BCM2835_CLOCK_DSI1P 49