target/linux/brcm2708/patches-4.9/950-0171-drm-vc4-Set-up-SCALER_DISPCTRL-at-boot.patch

   1 From e79b86a0c5ccd0e8c16e31b2d494d43e997253d1 Mon Sep 17 00:00:00 2001
   2 From: Eric Anholt <eric@anholt.net>
   3 Date: Thu, 15 Sep 2016 15:25:23 +0100
   4 Subject: [PATCH] drm/vc4: Set up SCALER_DISPCTRL at boot.
   5
   6 We want the HVS on, obviously, and we also want DSP3 (PV1's source) to
   7 be muxed from HVS channel 2 like we expect in vc4_crtc.c.  The
   8 firmware wasn't setting the DSP3 mux up when both the LCD and HDMI
   9 were disabled.
  10
  11 Signed-off-by: Eric Anholt <eric@anholt.net>
  12 ---
  13  drivers/gpu/drm/vc4/vc4_hvs.c  | 14 ++++++++++++++
  14  drivers/gpu/drm/vc4/vc4_regs.h |  3 +++
  15  2 files changed, 17 insertions(+)
  16
  17 --- a/drivers/gpu/drm/vc4/vc4_hvs.c
  18 +++ b/drivers/gpu/drm/vc4/vc4_hvs.c
  19 @@ -170,6 +170,7 @@ static int vc4_hvs_bind(struct device *d
  20         struct vc4_dev *vc4 = drm->dev_private;
  21         struct vc4_hvs *hvs = NULL;
  22         int ret;
  23 +       u32 dispctrl;
  24
  25         hvs = devm_kzalloc(&pdev->dev, sizeof(*hvs), GFP_KERNEL);
  26         if (!hvs)
  27 @@ -211,6 +212,19 @@ static int vc4_hvs_bind(struct device *d
  28                 return ret;
  29
  30         vc4->hvs = hvs;
  31 +
  32 +       dispctrl = HVS_READ(SCALER_DISPCTRL);
  33 +
  34 +       dispctrl |= SCALER_DISPCTRL_ENABLE;
  35 +
  36 +       /* Set DSP3 (PV1) to use HVS channel 2, which would otherwise
  37 +        * be unused.
  38 +        */
  39 +       dispctrl &= ~SCALER_DISPCTRL_DSP3_MUX_MASK;
  40 +       dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
  41 +
  42 +       HVS_WRITE(SCALER_DISPCTRL, dispctrl);
  43 +
  44         return 0;
  45  }
  46
  47 --- a/drivers/gpu/drm/vc4/vc4_regs.h
  48 +++ b/drivers/gpu/drm/vc4/vc4_regs.h
  49 @@ -244,6 +244,9 @@
  50  # define SCALER_DISPCTRL_ENABLE                        BIT(31)
  51  # define SCALER_DISPCTRL_DSP2EISLUR            BIT(15)
  52  # define SCALER_DISPCTRL_DSP1EISLUR            BIT(14)
  53 +# define SCALER_DISPCTRL_DSP3_MUX_MASK         VC4_MASK(19, 18)
  54 +# define SCALER_DISPCTRL_DSP3_MUX_SHIFT                18
  55 +
  56  /* Enables Display 0 short line and underrun contribution to
  57   * SCALER_DISPSTAT_IRQDISP0.  Note that short frame contributions are
  58   * always enabled.