de25019506b0ddc34d3b492445589935cf0688cc
[openwrt/openwrt.git] / target / linux / brcm47xx / patches-2.6.32 / 700-ssb-gigabit-ethernet-driver.patch
1 --- a/drivers/net/tg3.c
2 +++ b/drivers/net/tg3.c
3 @@ -41,6 +41,7 @@
4 #include <linux/prefetch.h>
5 #include <linux/dma-mapping.h>
6 #include <linux/firmware.h>
7 +#include <linux/ssb/ssb_driver_gige.h>
8
9 #include <net/checksum.h>
10 #include <net/ip.h>
11 @@ -457,8 +458,9 @@ static void _tw32_flush(struct tg3 *tp,
12 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
13 {
14 tp->write32_mbox(tp, off, val);
15 - if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
16 - !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
17 + if ((tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) ||
18 + (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
19 + !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)))
20 tp->read32_mbox(tp, off);
21 }
22
23 @@ -468,7 +470,7 @@ static void tg3_write32_tx_mbox(struct t
24 writel(val, mbox);
25 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
26 writel(val, mbox);
27 - if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
28 + if ((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) || (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES))
29 readl(mbox);
30 }
31
32 @@ -768,7 +770,7 @@ static void tg3_switch_clocks(struct tg3
33
34 #define PHY_BUSY_LOOPS 5000
35
36 -static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
37 +static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 *val)
38 {
39 u32 frame_val;
40 unsigned int loops;
41 @@ -817,7 +819,12 @@ static int tg3_readphy(struct tg3 *tp, i
42 return ret;
43 }
44
45 -static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
46 +static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
47 +{
48 + return __tg3_readphy(tp, PHY_ADDR, reg, val);
49 +}
50 +
51 +static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 val)
52 {
53 u32 frame_val;
54 unsigned int loops;
55 @@ -866,6 +873,11 @@ static int tg3_writephy(struct tg3 *tp,
56 return ret;
57 }
58
59 +static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
60 +{
61 + return __tg3_writephy(tp, PHY_ADDR, reg, val);
62 +}
63 +
64 static int tg3_bmcr_reset(struct tg3 *tp)
65 {
66 u32 phy_control;
67 @@ -2337,6 +2349,9 @@ static int tg3_nvram_read(struct tg3 *tp
68 {
69 int ret;
70
71 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
72 + return -ENODEV;
73 +
74 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
75 return tg3_nvram_read_using_eeprom(tp, offset, val);
76
77 @@ -2668,8 +2683,10 @@ static int tg3_set_power_state(struct tg
78 tg3_frob_aux_power(tp);
79
80 /* Workaround for unstable PLL clock */
81 - if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
82 - (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
83 + if ((tp->phy_id & PHY_ID_MASK) != PHY_ID_BCM5750_2 &&
84 + /* !!! FIXME !!! */
85 + ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
86 + (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
87 u32 val = tr32(0x7d00);
88
89 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
90 @@ -3161,6 +3178,14 @@ relink:
91
92 tg3_phy_copper_begin(tp);
93
94 + if (tp->tg3_flags3 & TG3_FLG3_ROBOSWITCH) {
95 + current_link_up = 1;
96 + current_speed = SPEED_1000; //FIXME
97 + current_duplex = DUPLEX_FULL;
98 + tp->link_config.active_speed = current_speed;
99 + tp->link_config.active_duplex = current_duplex;
100 + }
101 +
102 tg3_readphy(tp, MII_BMSR, &tmp);
103 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
104 (tmp & BMSR_LSTATUS))
105 @@ -6264,6 +6289,11 @@ static int tg3_poll_fw(struct tg3 *tp)
106 int i;
107 u32 val;
108
109 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
110 + /* We don't use firmware. */
111 + return 0;
112 + }
113 +
114 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
115 /* Wait up to 20ms for init done. */
116 for (i = 0; i < 200; i++) {
117 @@ -6541,6 +6571,14 @@ static int tg3_chip_reset(struct tg3 *tp
118 tw32(0x5000, 0x400);
119 }
120
121 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
122 + /* BCM4785: In order to avoid repercussions from using potentially
123 + * defective internal ROM, stop the Rx RISC CPU, which is not
124 + * required. */
125 + tg3_stop_fw(tp);
126 + tg3_halt_cpu(tp, RX_CPU_BASE);
127 + }
128 +
129 tw32(GRC_MODE, tp->grc_mode);
130
131 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
132 @@ -6695,9 +6733,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
133 return -ENODEV;
134 }
135
136 - /* Clear firmware's nvram arbitration. */
137 - if (tp->tg3_flags & TG3_FLAG_NVRAM)
138 - tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
139 + if (!(tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)) {
140 + /* Clear firmware's nvram arbitration. */
141 + if (tp->tg3_flags & TG3_FLAG_NVRAM)
142 + tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
143 + }
144 +
145 return 0;
146 }
147
148 @@ -6760,6 +6801,11 @@ static int tg3_load_5701_a0_firmware_fix
149 const __be32 *fw_data;
150 int err, i;
151
152 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
153 + /* We don't use firmware. */
154 + return 0;
155 + }
156 +
157 fw_data = (void *)tp->fw->data;
158
159 /* Firmware blob starts with version numbers, followed by
160 @@ -6819,6 +6865,11 @@ static int tg3_load_tso_firmware(struct
161 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
162 int err, i;
163
164 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
165 + /* We don't use firmware. */
166 + return 0;
167 + }
168 +
169 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
170 return 0;
171
172 @@ -7906,6 +7957,11 @@ static void tg3_timer(unsigned long __op
173
174 spin_lock(&tp->lock);
175
176 + if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
177 + /* BCM4785: Flush posted writes from GbE to host memory. */
178 + tr32(HOSTCC_MODE);
179 + }
180 +
181 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
182 /* All of this garbage is because when using non-tagged
183 * IRQ status the mailbox/status_block protocol the chip
184 @@ -9791,6 +9847,11 @@ static int tg3_test_nvram(struct tg3 *tp
185 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
186 return 0;
187
188 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
189 + /* We don't have NVRAM. */
190 + return 0;
191 + }
192 +
193 if (tg3_nvram_read(tp, 0, &magic) != 0)
194 return -EIO;
195
196 @@ -10585,7 +10646,7 @@ static int tg3_ioctl(struct net_device *
197 return -EAGAIN;
198
199 spin_lock_bh(&tp->lock);
200 - err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
201 + err = __tg3_readphy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
202 spin_unlock_bh(&tp->lock);
203
204 data->val_out = mii_regval;
205 @@ -10601,7 +10662,7 @@ static int tg3_ioctl(struct net_device *
206 return -EAGAIN;
207
208 spin_lock_bh(&tp->lock);
209 - err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
210 + err = __tg3_writephy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
211 spin_unlock_bh(&tp->lock);
212
213 return err;
214 @@ -11246,6 +11307,12 @@ static void __devinit tg3_get_5717_nvram
215 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
216 static void __devinit tg3_nvram_init(struct tg3 *tp)
217 {
218 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
219 + /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
220 + tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
221 + return;
222 + }
223 +
224 tw32_f(GRC_EEPROM_ADDR,
225 (EEPROM_ADDR_FSM_RESET |
226 (EEPROM_DEFAULT_CLOCK_PERIOD <<
227 @@ -11506,6 +11573,9 @@ static int tg3_nvram_write_block(struct
228 {
229 int ret;
230
231 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
232 + return -ENODEV;
233 +
234 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
235 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
236 ~GRC_LCLCTRL_GPIO_OUTPUT1);
237 @@ -12788,6 +12858,11 @@ static int __devinit tg3_get_invariants(
238 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
239 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
240
241 + if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
242 + tp->write32_tx_mbox = tg3_write_flush_reg32;
243 + tp->write32_rx_mbox = tg3_write_flush_reg32;
244 + }
245 +
246 /* Get eeprom hw config before calling tg3_set_power_state().
247 * In particular, the TG3_FLG2_IS_NIC flag must be
248 * determined before calling tg3_set_power_state() so that
249 @@ -13177,6 +13252,10 @@ static int __devinit tg3_get_device_addr
250 }
251
252 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
253 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
254 + ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
255 + }
256 + if (!is_valid_ether_addr(&dev->dev_addr[0])) {
257 #ifdef CONFIG_SPARC
258 if (!tg3_get_default_macaddr_sparc(tp))
259 return 0;
260 @@ -13669,6 +13748,7 @@ static char * __devinit tg3_phy_string(s
261 case PHY_ID_BCM5704: return "5704";
262 case PHY_ID_BCM5705: return "5705";
263 case PHY_ID_BCM5750: return "5750";
264 + case PHY_ID_BCM5750_2: return "5750-2";
265 case PHY_ID_BCM5752: return "5752";
266 case PHY_ID_BCM5714: return "5714";
267 case PHY_ID_BCM5780: return "5780";
268 @@ -13880,6 +13960,13 @@ static int __devinit tg3_init_one(struct
269 tp->msg_enable = tg3_debug;
270 else
271 tp->msg_enable = TG3_DEF_MSG_ENABLE;
272 + if (pdev_is_ssb_gige_core(pdev)) {
273 + tp->tg3_flags3 |= TG3_FLG3_IS_SSB_CORE;
274 + if (ssb_gige_must_flush_posted_writes(pdev))
275 + tp->tg3_flags3 |= TG3_FLG3_FLUSH_POSTED_WRITES;
276 + if (ssb_gige_have_roboswitch(pdev))
277 + tp->tg3_flags3 |= TG3_FLG3_ROBOSWITCH;
278 + }
279
280 /* The word/byte swap controls here control register access byte
281 * swapping. DMA data byte swapping is controlled in the GRC_MODE
282 --- a/drivers/net/tg3.h
283 +++ b/drivers/net/tg3.h
284 @@ -1939,6 +1939,9 @@
285 #define NIC_SRAM_RGMII_STD_IBND_DISABLE 0x00000004
286 #define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008
287 #define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010
288 +#define TG3_FLG3_IS_SSB_CORE 0x00000800
289 +#define TG3_FLG3_FLUSH_POSTED_WRITES 0x00001000
290 +#define TG3_FLG3_ROBOSWITCH 0x00002000
291
292 #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
293
294 @@ -2821,6 +2824,7 @@ struct tg3 {
295 #define PHY_ID_BCM5714 0x60008340
296 #define PHY_ID_BCM5780 0x60008350
297 #define PHY_ID_BCM5755 0xbc050cc0
298 +#define PHY_ID_BCM5750_2 0xbc050cd0
299 #define PHY_ID_BCM5787 0xbc050ce0
300 #define PHY_ID_BCM5756 0xbc050ed0
301 #define PHY_ID_BCM5784 0xbc050fa0
302 @@ -2865,7 +2869,7 @@ struct tg3 {
303 (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
304 (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
305 (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
306 - (X) == PHY_ID_BCM8002)
307 + (X) == PHY_ID_BCM8002 || (X) == PHY_ID_BCM5750_2)
308
309 struct tg3_hw_stats *hw_stats;
310 dma_addr_t stats_mapping;