f396ca745a27f59d3769d6c4497bd0a24383ef66
[openwrt/openwrt.git] / target / linux / brcm47xx / patches-2.6.33 / 220-bcm5354.patch
1 --- a/drivers/ssb/driver_chipcommon.c
2 +++ b/drivers/ssb/driver_chipcommon.c
3 @@ -258,6 +258,8 @@ void ssb_chipco_resume(struct ssb_chipco
4 void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
5 u32 *plltype, u32 *n, u32 *m)
6 {
7 + if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
8 + return;
9 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
10 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
11 switch (*plltype) {
12 @@ -281,6 +283,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
13 void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
14 u32 *plltype, u32 *n, u32 *m)
15 {
16 + if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
17 + return;
18 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
19 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
20 switch (*plltype) {
21 --- a/drivers/ssb/driver_mipscore.c
22 +++ b/drivers/ssb/driver_mipscore.c
23 @@ -217,6 +217,8 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
24
25 if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {
26 rate = 200000000;
27 + } else if (bus->chip_id == 0x5354) {
28 + rate = 240000000;
29 } else {
30 rate = ssb_calc_clock_rate(pll_type, n, m);
31 }
32 --- a/drivers/ssb/main.c
33 +++ b/drivers/ssb/main.c
34 @@ -1069,6 +1069,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
35
36 if (bus->chip_id == 0x5365) {
37 rate = 100000000;
38 + } else if (bus->chip_id == 0x5354) {
39 + rate = 120000000;
40 } else {
41 rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
42 if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */