c8c3158c1004bc3c5c66a2ea38469738803d5efc
[openwrt/openwrt.git] / target / linux / brcm47xx / patches-3.6 / 400-arch-bcm47xx.patch
1 --- a/arch/mips/bcm47xx/nvram.c
2 +++ b/arch/mips/bcm47xx/nvram.c
3 @@ -198,3 +198,30 @@ int bcm47xx_nvram_getenv(char *name, cha
4 return -ENOENT;
5 }
6 EXPORT_SYMBOL(bcm47xx_nvram_getenv);
7 +
8 +char *nvram_get(const char *name)
9 +{
10 + char *var, *value, *end, *eq;
11 +
12 + if (!name)
13 + return NULL;
14 +
15 + if (!nvram_buf[0])
16 + nvram_init();
17 +
18 + /* Look for name=value and return value */
19 + var = &nvram_buf[sizeof(struct nvram_header)];
20 + end = nvram_buf + sizeof(nvram_buf) - 2;
21 + end[0] = end[1] = '\0';
22 + for (; *var; var = value + strlen(value) + 1) {
23 + eq = strchr(var, '=');
24 + if (!eq)
25 + break;
26 + value = eq + 1;
27 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
28 + return value;
29 + }
30 +
31 + return NULL;
32 +}
33 +EXPORT_SYMBOL(nvram_get);
34 --- a/arch/mips/bcm47xx/Makefile
35 +++ b/arch/mips/bcm47xx/Makefile
36 @@ -4,4 +4,5 @@
37 #
38
39 obj-y += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o
40 +obj-y += gpio.o
41 obj-$(CONFIG_BCM47XX_SSB) += wgt634u.o
42 --- /dev/null
43 +++ b/arch/mips/bcm47xx/gpio.c
44 @@ -0,0 +1,119 @@
45 +/*
46 + * This file is subject to the terms and conditions of the GNU General Public
47 + * License. See the file "COPYING" in the main directory of this archive
48 + * for more details.
49 + *
50 + * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
51 + * Copyright (C) 2012 Hauke Mehrtens <hauke@hauke-m.de>
52 + *
53 + * Parts of this file are based on Atheros AR71XX/AR724X/AR913X GPIO
54 + */
55 +
56 +#include <linux/export.h>
57 +#include <linux/gpio.h>
58 +#include <linux/ssb/ssb_embedded.h>
59 +#include <linux/bcma/bcma.h>
60 +
61 +#include <bcm47xx.h>
62 +
63 +/* low level BCM47xx gpio api */
64 +u32 bcm47xx_gpio_in(u32 mask)
65 +{
66 + switch (bcm47xx_bus_type) {
67 +#ifdef CONFIG_BCM47XX_SSB
68 + case BCM47XX_BUS_TYPE_SSB:
69 + return ssb_gpio_in(&bcm47xx_bus.ssb, mask);
70 +#endif
71 +#ifdef CONFIG_BCM47XX_BCMA
72 + case BCM47XX_BUS_TYPE_BCMA:
73 + return bcma_chipco_gpio_in(&bcm47xx_bus.bcma.bus.drv_cc, mask);
74 +#endif
75 + }
76 + return -EINVAL;
77 +}
78 +EXPORT_SYMBOL(bcm47xx_gpio_in);
79 +
80 +u32 bcm47xx_gpio_out(u32 mask, u32 value)
81 +{
82 + switch (bcm47xx_bus_type) {
83 +#ifdef CONFIG_BCM47XX_SSB
84 + case BCM47XX_BUS_TYPE_SSB:
85 + return ssb_gpio_out(&bcm47xx_bus.ssb, mask, value);
86 +#endif
87 +#ifdef CONFIG_BCM47XX_BCMA
88 + case BCM47XX_BUS_TYPE_BCMA:
89 + return bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, mask,
90 + value);
91 +#endif
92 + }
93 + return -EINVAL;
94 +}
95 +EXPORT_SYMBOL(bcm47xx_gpio_out);
96 +
97 +u32 bcm47xx_gpio_outen(u32 mask, u32 value)
98 +{
99 + switch (bcm47xx_bus_type) {
100 +#ifdef CONFIG_BCM47XX_SSB
101 + case BCM47XX_BUS_TYPE_SSB:
102 + return ssb_gpio_outen(&bcm47xx_bus.ssb, mask, value);
103 +#endif
104 +#ifdef CONFIG_BCM47XX_BCMA
105 + case BCM47XX_BUS_TYPE_BCMA:
106 + return bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc,
107 + mask, value);
108 +#endif
109 + }
110 + return -EINVAL;
111 +}
112 +EXPORT_SYMBOL(bcm47xx_gpio_outen);
113 +
114 +u32 bcm47xx_gpio_control(u32 mask, u32 value)
115 +{
116 + switch (bcm47xx_bus_type) {
117 +#ifdef CONFIG_BCM47XX_SSB
118 + case BCM47XX_BUS_TYPE_SSB:
119 + return ssb_gpio_control(&bcm47xx_bus.ssb, mask, value);
120 +#endif
121 +#ifdef CONFIG_BCM47XX_BCMA
122 + case BCM47XX_BUS_TYPE_BCMA:
123 + return bcma_chipco_gpio_control(&bcm47xx_bus.bcma.bus.drv_cc,
124 + mask, value);
125 +#endif
126 + }
127 + return -EINVAL;
128 +}
129 +EXPORT_SYMBOL(bcm47xx_gpio_control);
130 +
131 +u32 bcm47xx_gpio_intmask(u32 mask, u32 value)
132 +{
133 + switch (bcm47xx_bus_type) {
134 +#ifdef CONFIG_BCM47XX_SSB
135 + case BCM47XX_BUS_TYPE_SSB:
136 + return ssb_gpio_intmask(&bcm47xx_bus.ssb, mask, value);
137 +#endif
138 +#ifdef CONFIG_BCM47XX_BCMA
139 + case BCM47XX_BUS_TYPE_BCMA:
140 + return bcma_chipco_gpio_intmask(&bcm47xx_bus.bcma.bus.drv_cc,
141 + mask, value);
142 +#endif
143 + }
144 + return -EINVAL;
145 +}
146 +EXPORT_SYMBOL(bcm47xx_gpio_intmask);
147 +
148 +u32 bcm47xx_gpio_polarity(u32 mask, u32 value)
149 +{
150 + switch (bcm47xx_bus_type) {
151 +#ifdef CONFIG_BCM47XX_SSB
152 + case BCM47XX_BUS_TYPE_SSB:
153 + return ssb_gpio_polarity(&bcm47xx_bus.ssb, mask, value);
154 +#endif
155 +#ifdef CONFIG_BCM47XX_BCMA
156 + case BCM47XX_BUS_TYPE_BCMA:
157 + return bcma_chipco_gpio_polarity(&bcm47xx_bus.bcma.bus.drv_cc,
158 + mask, value);
159 +#endif
160 + }
161 + return -EINVAL;
162 +}
163 +EXPORT_SYMBOL(bcm47xx_gpio_polarity);
164 --- a/arch/mips/include/asm/mach-bcm47xx/gpio.h
165 +++ b/arch/mips/include/asm/mach-bcm47xx/gpio.h
166 @@ -14,4 +14,11 @@ static inline int irq_to_gpio(unsigned i
167 return -EINVAL;
168 }
169
170 +u32 bcm47xx_gpio_in(u32 mask);
171 +u32 bcm47xx_gpio_out(u32 mask, u32 value);
172 +u32 bcm47xx_gpio_outen(u32 mask, u32 value);
173 +u32 bcm47xx_gpio_control(u32 mask, u32 value);
174 +u32 bcm47xx_gpio_intmask(u32 mask, u32 value);
175 +u32 bcm47xx_gpio_polarity(u32 mask, u32 value);
176 +
177 #endif