36d39fa892bd39c5eb086feabdf26abdfea5842f
[openwrt/openwrt.git] / target / linux / brcm47xx / patches-4.9 / 159-cpu_fixes.patch
1 --- a/arch/mips/include/asm/r4kcache.h
2 +++ b/arch/mips/include/asm/r4kcache.h
3 @@ -25,6 +25,38 @@
4 extern void (*r4k_blast_dcache)(void);
5 extern void (*r4k_blast_icache)(void);
6
7 +#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2)
8 +#include <asm/paccess.h>
9 +#include <linux/ssb/ssb.h>
10 +#define BCM4710_DUMMY_RREG() bcm4710_dummy_rreg()
11 +
12 +static inline unsigned long bcm4710_dummy_rreg(void)
13 +{
14 + return *(volatile unsigned long *)(KSEG1ADDR(SSB_ENUM_BASE));
15 +}
16 +
17 +#define BCM4710_FILL_TLB(addr) bcm4710_fill_tlb((void *)(addr))
18 +
19 +static inline unsigned long bcm4710_fill_tlb(void *addr)
20 +{
21 + return *(unsigned long *)addr;
22 +}
23 +
24 +#define BCM4710_PROTECTED_FILL_TLB(addr) bcm4710_protected_fill_tlb((void *)(addr))
25 +
26 +static inline void bcm4710_protected_fill_tlb(void *addr)
27 +{
28 + unsigned long x;
29 + get_dbe(x, (unsigned long *)addr);;
30 +}
31 +
32 +#else
33 +#define BCM4710_DUMMY_RREG()
34 +
35 +#define BCM4710_FILL_TLB(addr)
36 +#define BCM4710_PROTECTED_FILL_TLB(addr)
37 +#endif
38 +
39 /*
40 * This macro return a properly sign-extended address suitable as base address
41 * for indexed cache operations. Two issues here:
42 @@ -98,6 +130,7 @@ static inline void flush_icache_line_ind
43 static inline void flush_dcache_line_indexed(unsigned long addr)
44 {
45 __dflush_prologue
46 + BCM4710_DUMMY_RREG();
47 cache_op(Index_Writeback_Inv_D, addr);
48 __dflush_epilogue
49 }
50 @@ -125,6 +158,7 @@ static inline void flush_icache_line(uns
51 static inline void flush_dcache_line(unsigned long addr)
52 {
53 __dflush_prologue
54 + BCM4710_DUMMY_RREG();
55 cache_op(Hit_Writeback_Inv_D, addr);
56 __dflush_epilogue
57 }
58 @@ -132,6 +166,7 @@ static inline void flush_dcache_line(uns
59 static inline void invalidate_dcache_line(unsigned long addr)
60 {
61 __dflush_prologue
62 + BCM4710_DUMMY_RREG();
63 cache_op(Hit_Invalidate_D, addr);
64 __dflush_epilogue
65 }
66 @@ -187,6 +222,7 @@ static inline void protected_flush_icach
67 #ifdef CONFIG_EVA
68 protected_cachee_op(Hit_Invalidate_I, addr);
69 #else
70 + BCM4710_DUMMY_RREG();
71 protected_cache_op(Hit_Invalidate_I, addr);
72 #endif
73 break;
74 @@ -201,6 +237,7 @@ static inline void protected_flush_icach
75 */
76 static inline void protected_writeback_dcache_line(unsigned long addr)
77 {
78 + BCM4710_DUMMY_RREG();
79 #ifdef CONFIG_EVA
80 protected_cachee_op(Hit_Writeback_Inv_D, addr);
81 #else
82 @@ -558,8 +595,51 @@ static inline void invalidate_tcache_pag
83 : "r" (base), \
84 "i" (op));
85
86 +static inline void blast_dcache(void)
87 +{
88 + unsigned long start = KSEG0;
89 + unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
90 + unsigned long end = (start + dcache_size);
91 +
92 + do {
93 + BCM4710_DUMMY_RREG();
94 + cache_op(Index_Writeback_Inv_D, start);
95 + start += current_cpu_data.dcache.linesz;
96 + } while(start < end);
97 +}
98 +
99 +static inline void blast_dcache_page(unsigned long page)
100 +{
101 + unsigned long start = page;
102 + unsigned long end = start + PAGE_SIZE;
103 +
104 + BCM4710_FILL_TLB(start);
105 + do {
106 + BCM4710_DUMMY_RREG();
107 + cache_op(Hit_Writeback_Inv_D, start);
108 + start += current_cpu_data.dcache.linesz;
109 + } while(start < end);
110 +}
111 +
112 +static inline void blast_dcache_page_indexed(unsigned long page)
113 +{
114 + unsigned long start = page;
115 + unsigned long end = start + PAGE_SIZE;
116 + unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
117 + unsigned long ws_end = current_cpu_data.dcache.ways <<
118 + current_cpu_data.dcache.waybit;
119 + unsigned long ws, addr;
120 + for (ws = 0; ws < ws_end; ws += ws_inc) {
121 + start = page + ws;
122 + for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
123 + BCM4710_DUMMY_RREG();
124 + cache_op(Index_Writeback_Inv_D, addr);
125 + }
126 + }
127 +}
128 +
129 /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
130 -#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra) \
131 +#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra, war) \
132 static inline void extra##blast_##pfx##cache##lsize(void) \
133 { \
134 unsigned long start = INDEX_BASE; \
135 @@ -571,6 +651,7 @@ static inline void extra##blast_##pfx##c
136 \
137 __##pfx##flush_prologue \
138 \
139 + war \
140 for (ws = 0; ws < ws_end; ws += ws_inc) \
141 for (addr = start; addr < end; addr += lsize * 32) \
142 cache##lsize##_unroll32(addr|ws, indexop); \
143 @@ -585,6 +666,7 @@ static inline void extra##blast_##pfx##c
144 \
145 __##pfx##flush_prologue \
146 \
147 + war \
148 do { \
149 cache##lsize##_unroll32(start, hitop); \
150 start += lsize * 32; \
151 @@ -603,6 +685,8 @@ static inline void extra##blast_##pfx##c
152 current_cpu_data.desc.waybit; \
153 unsigned long ws, addr; \
154 \
155 + war \
156 + \
157 __##pfx##flush_prologue \
158 \
159 for (ws = 0; ws < ws_end; ws += ws_inc) \
160 @@ -612,26 +696,26 @@ static inline void extra##blast_##pfx##c
161 __##pfx##flush_epilogue \
162 }
163
164 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
165 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, )
166 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
167 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
168 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, )
169 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_)
170 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
171 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
172 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
173 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
174 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
175 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
176 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
177 -
178 -__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
179 -__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
180 -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
181 -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
182 -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
183 -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
184 +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, , )
185 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, , BCM4710_FILL_TLB(start);)
186 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, , )
187 +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, , )
188 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, , BCM4710_FILL_TLB(start);)
189 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_, BCM4710_FILL_TLB(start);)
190 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, , )
191 +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, , )
192 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, , BCM4710_FILL_TLB(start);)
193 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, , )
194 +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, , )
195 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, , )
196 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, , )
197 +
198 +__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, , )
199 +__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, , )
200 +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, , )
201 +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, , )
202 +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, , )
203 +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, , )
204
205 #define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
206 static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
207 @@ -660,17 +744,19 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde
208 __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
209
210 /* build blast_xxx_range, protected_blast_xxx_range */
211 -#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \
212 +#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra, war, war2) \
213 static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
214 unsigned long end) \
215 { \
216 unsigned long lsize = cpu_##desc##_line_size(); \
217 unsigned long addr = start & ~(lsize - 1); \
218 unsigned long aend = (end - 1) & ~(lsize - 1); \
219 + war \
220 \
221 __##pfx##flush_prologue \
222 \
223 while (1) { \
224 + war2 \
225 prot##cache_op(hitop, addr); \
226 if (addr == aend) \
227 break; \
228 @@ -682,8 +768,8 @@ static inline void prot##extra##blast_##
229
230 #ifndef CONFIG_EVA
231
232 -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
233 -__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
234 +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, , BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
235 +__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, , , )
236
237 #else
238
239 @@ -720,14 +806,14 @@ __BUILD_PROT_BLAST_CACHE_RANGE(d, dcache
240 __BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I)
241
242 #endif
243 -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
244 +__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, , , )
245 __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
246 - protected_, loongson2_)
247 -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
248 -__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , )
249 -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
250 + protected_, loongson2_, , )
251 +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , , BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
252 +__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , , , )
253 +__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , , , )
254 /* blast_inv_dcache_range */
255 -__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
256 -__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
257 +__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , , , BCM4710_DUMMY_RREG();)
258 +__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , , , )
259
260 #endif /* _ASM_R4KCACHE_H */
261 --- a/arch/mips/include/asm/stackframe.h
262 +++ b/arch/mips/include/asm/stackframe.h
263 @@ -365,6 +365,10 @@
264 .macro RESTORE_SP_AND_RET
265 LONG_L sp, PT_R29(sp)
266 .set arch=r4000
267 +#ifdef CONFIG_BCM47XX
268 + nop
269 + nop
270 +#endif
271 eret
272 .set mips0
273 .endm
274 --- a/arch/mips/kernel/genex.S
275 +++ b/arch/mips/kernel/genex.S
276 @@ -21,6 +21,19 @@
277 #include <asm/war.h>
278 #include <asm/thread_info.h>
279
280 +#ifdef CONFIG_BCM47XX
281 +# ifdef eret
282 +# undef eret
283 +# endif
284 +# define eret \
285 + .set push; \
286 + .set noreorder; \
287 + nop; \
288 + nop; \
289 + eret; \
290 + .set pop;
291 +#endif
292 +
293 __INIT
294
295 /*
296 @@ -32,6 +45,9 @@
297 NESTED(except_vec3_generic, 0, sp)
298 .set push
299 .set noat
300 +#ifdef CONFIG_BCM47XX
301 + nop
302 +#endif
303 #if R5432_CP0_INTERRUPT_WAR
304 mfc0 k0, CP0_INDEX
305 #endif
306 @@ -55,6 +71,9 @@ NESTED(except_vec3_r4000, 0, sp)
307 .set push
308 .set arch=r4000
309 .set noat
310 +#ifdef CONFIG_BCM47XX
311 + nop
312 +#endif
313 mfc0 k1, CP0_CAUSE
314 li k0, 31<<2
315 andi k1, k1, 0x7c
316 --- a/arch/mips/mm/c-r4k.c
317 +++ b/arch/mips/mm/c-r4k.c
318 @@ -39,6 +39,9 @@
319 #include <asm/dma-coherence.h>
320 #include <asm/mips-cm.h>
321
322 +/* For enabling BCM4710 cache workarounds */
323 +static int bcm4710 = 0;
324 +
325 /*
326 * Bits describing what cache ops an SMP callback function may perform.
327 *
328 @@ -190,6 +193,9 @@ static void r4k_blast_dcache_user_page_s
329 {
330 unsigned long dc_lsize = cpu_dcache_line_size();
331
332 + if (bcm4710)
333 + r4k_blast_dcache_page = blast_dcache_page;
334 + else
335 if (dc_lsize == 0)
336 r4k_blast_dcache_user_page = (void *)cache_noop;
337 else if (dc_lsize == 16)
338 @@ -208,6 +214,9 @@ static void r4k_blast_dcache_page_indexe
339 {
340 unsigned long dc_lsize = cpu_dcache_line_size();
341
342 + if (bcm4710)
343 + r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
344 + else
345 if (dc_lsize == 0)
346 r4k_blast_dcache_page_indexed = (void *)cache_noop;
347 else if (dc_lsize == 16)
348 @@ -227,6 +236,9 @@ static void r4k_blast_dcache_setup(void)
349 {
350 unsigned long dc_lsize = cpu_dcache_line_size();
351
352 + if (bcm4710)
353 + r4k_blast_dcache = blast_dcache;
354 + else
355 if (dc_lsize == 0)
356 r4k_blast_dcache = (void *)cache_noop;
357 else if (dc_lsize == 16)
358 @@ -952,6 +964,8 @@ static void local_r4k_flush_cache_sigtra
359 }
360
361 R4600_HIT_CACHEOP_WAR_IMPL;
362 + BCM4710_PROTECTED_FILL_TLB(addr);
363 + BCM4710_PROTECTED_FILL_TLB(addr + 4);
364 if (!cpu_has_ic_fills_f_dc) {
365 if (dc_lsize)
366 vaddr ? flush_dcache_line(addr & ~(dc_lsize - 1))
367 @@ -1840,6 +1854,17 @@ static void coherency_setup(void)
368 * silly idea of putting something else there ...
369 */
370 switch (current_cpu_type()) {
371 + case CPU_BMIPS3300:
372 + {
373 + u32 cm;
374 + cm = read_c0_diag();
375 + /* Enable icache */
376 + cm |= (1 << 31);
377 + /* Enable dcache */
378 + cm |= (1 << 30);
379 + write_c0_diag(cm);
380 + }
381 + break;
382 case CPU_R4000PC:
383 case CPU_R4000SC:
384 case CPU_R4000MC:
385 @@ -1886,6 +1911,15 @@ void r4k_cache_init(void)
386 extern void build_copy_page(void);
387 struct cpuinfo_mips *c = &current_cpu_data;
388
389 + /* Check if special workarounds are required */
390 +#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2)
391 + if (current_cpu_data.cputype == CPU_BMIPS32 && (current_cpu_data.processor_id & 0xff) == 0) {
392 + printk("Enabling BCM4710A0 cache workarounds.\n");
393 + bcm4710 = 1;
394 + } else
395 +#endif
396 + bcm4710 = 0;
397 +
398 probe_pcache();
399 probe_vcache();
400 setup_scache();
401 @@ -1963,7 +1997,15 @@ void r4k_cache_init(void)
402 */
403 local_r4k___flush_cache_all(NULL);
404
405 +#ifdef CONFIG_BCM47XX
406 + {
407 + static void (*_coherency_setup)(void);
408 + _coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
409 + _coherency_setup();
410 + }
411 +#else
412 coherency_setup();
413 +#endif
414 board_cache_error_setup = r4k_cache_error_setup;
415
416 /*
417 --- a/arch/mips/mm/tlbex.c
418 +++ b/arch/mips/mm/tlbex.c
419 @@ -968,6 +968,9 @@ build_get_pgde32(u32 **p, unsigned int t
420 uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
421 uasm_i_addu(p, ptr, tmp, ptr);
422 #else
423 +#ifdef CONFIG_BCM47XX
424 + uasm_i_nop(p);
425 +#endif
426 UASM_i_LA_mostly(p, ptr, pgdc);
427 #endif
428 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
429 @@ -1310,6 +1313,9 @@ static void build_r4000_tlb_refill_handl
430 #ifdef CONFIG_64BIT
431 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
432 #else
433 +# ifdef CONFIG_BCM47XX
434 + uasm_i_nop(&p);
435 +# endif
436 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
437 #endif
438
439 @@ -1321,6 +1327,9 @@ static void build_r4000_tlb_refill_handl
440 build_update_entries(&p, K0, K1);
441 build_tlb_write_entry(&p, &l, &r, tlb_random);
442 uasm_l_leave(&l, p);
443 +#ifdef CONFIG_BCM47XX
444 + uasm_i_nop(&p);
445 +#endif
446 uasm_i_eret(&p); /* return from trap */
447 }
448 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
449 @@ -2003,6 +2012,9 @@ build_r4000_tlbchange_handler_head(u32 *
450 #ifdef CONFIG_64BIT
451 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
452 #else
453 +# ifdef CONFIG_BCM47XX
454 + uasm_i_nop(p);
455 +# endif
456 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
457 #endif
458
459 @@ -2049,6 +2061,9 @@ build_r4000_tlbchange_handler_tail(u32 *
460 build_tlb_write_entry(p, l, r, tlb_indexed);
461 uasm_l_leave(l, *p);
462 build_restore_work_registers(p);
463 +#ifdef CONFIG_BCM47XX
464 + uasm_i_nop(p);
465 +#endif
466 uasm_i_eret(p); /* return from trap */
467
468 #ifdef CONFIG_64BIT