target/linux/brcm63xx/patches-3.14/334-MIPS-BCM63XX-detect-BCM6368-variants.patch

   1 From 825cc67e56b5e624a05f6850a86d91508b786848 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jogo@openwrt.org>
   3 Date: Sat, 7 Dec 2013 14:36:56 +0100
   4 Subject: [PATCH 24/44] MIPS: BCM63XX: detect BCM6368 variants
   5
   6 The DSL-less BCM6368 variant BCM6367 uses a different chip id. Apart
   7 from missing DSL, there is no difference to BCM6368, so treat it such.
   8
   9 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  10 ---
  11  arch/mips/bcm63xx/cpu.c                          | 4 ++++
  12  arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 3 +++
  13  2 files changed, 7 insertions(+)
  14
  15 --- a/arch/mips/bcm63xx/cpu.c
  16 +++ b/arch/mips/bcm63xx/cpu.c
  17 @@ -394,8 +394,12 @@ void __init bcm63xx_cpu_init(void)
  18
  19                 break;
  20         case BCM6368_CPU_ID:
  21 +       case BCM6369_CPU_ID:
  22                 bcm63xx_regs_base = bcm6368_regs_base;
  23                 bcm63xx_irqs = bcm6368_irqs;
  24 +
  25 +               /* BCM6369 is a BCM6368 without xDSL, so treat it the same */
  26 +               bcm63xx_cpu_id = BCM6368_CPU_ID;
  27                 break;
  28         default:
  29                 panic("unsupported broadcom CPU %x", bcm63xx_cpu_id);
  30 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
  31 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
  32 @@ -20,6 +20,7 @@
  33  #define BCM6361_CPU_ID         0x6361
  34  #define BCM6362_CPU_ID         0x6362
  35  #define BCM6368_CPU_ID         0x6368
  36 +#define BCM6369_CPU_ID         0x6369
  37
  38  void __init bcm63xx_cpu_init(void);
  39  u32 bcm63xx_get_cpu_variant(void);
  40 @@ -106,6 +107,8 @@ static inline u16 __pure bcm63xx_get_cpu
  41         (bcm63xx_get_cpu_variant() == BCM6362_CPU_ID)
  42  #define BCMCPU_VARIANT_IS_6368() \
  43         (bcm63xx_get_cpu_variant() == BCM6368_CPU_ID)
  44 +#define BCMCPU_VARIANT_IS_6369() \
  45 +       (bcm63xx_get_cpu_variant() == BCM6369_CPU_ID)
  46
  47  /*
  48   * While registers sets are (mostly) the same across 63xx CPU, base