target/linux/brcm63xx/patches-3.18/321-irqchip-add-support-for-bcm6345-style-external-inter.patch

   1 From 6896b5f0538a7a7cfb7fac2d9ed3c6841c72ed40 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jogo@openwrt.org>
   3 Date: Sun, 30 Nov 2014 14:54:27 +0100
   4 Subject: [PATCH 18/20] irqchip: add support for bcm6345-style external
   5  interrupt controller
   6
   7 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
   8 ---
   9  .../interrupt-controller/brcm,bcm6345-ext-intc.txt |   24 ++
  10  drivers/irqchip/Kconfig                            |    4 +
  11  drivers/irqchip/Makefile                           |    1 +
  12  drivers/irqchip/irq-bcm6345-ext.c                  |  296 ++++++++++++++++++++
  13  include/linux/irqchip/irq-bcm6345-ext-intc.h       |   14 +
  14  5 files changed, 339 insertions(+)
  15  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt
  16  create mode 100644 drivers/irqchip/irq-bcm6345-ext.c
  17  create mode 100644 include/linux/irqchip/irq-bcm6345-ext-intc.h
  18
  19 --- /dev/null
  20 +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt
  21 @@ -0,0 +1,24 @@
  22 +Broadcom BCM6345-style external interrupt controller
  23 +
  24 +Required properties:
  25 +
  26 +- compatible: should be "brcm,bcm6345-l2-intc" or "brcm,bcm6345-l2-intc"
  27 +- reg: specifies the base physical addresses and size of the registers.
  28 +- interrupt-controller: identifies the node as an interrupt controller
  29 +- #interrupt-cells: specifies the number of cells needed to encode an interrupt
  30 +  source, should be 2
  31 +- interrupt-parent: specifies the phandle to the parent interrupt controller
  32 +  this one is cascaded from
  33 +- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
  34 +  node, valid values depend on the type of parent interrupt controller
  35 +
  36 +Example:
  37 +
  38 +ext_intc: interrupt-controller@10000018 {
  39 +       compatible = "brcm,bcm6345-l2-intc";
  40 +       interrupt-parent = <&periph_intc>;
  41 +       #interrupt-cells = <2>;
  42 +       reg = <0x10000018 0x4>;
  43 +       interrupt-controller;
  44 +       interrupts = <24>, <25>, <26>, <27>;
  45 +};
  46 --- a/drivers/irqchip/Kconfig
  47 +++ b/drivers/irqchip/Kconfig
  48 @@ -54,6 +54,10 @@ config BRCMSTB_L2_IRQ
  49         select GENERIC_IRQ_CHIP
  50         select IRQ_DOMAIN
  51
  52 +config BCM6345_EXT_IRQ
  53 +       bool
  54 +       select IRQ_DOMAIN
  55 +
  56  config BCM6345_L2_IRQ
  57         bool
  58         select IRQ_DOMAIN
  59 --- a/drivers/irqchip/Makefile
  60 +++ b/drivers/irqchip/Makefile
  61 @@ -7,6 +7,7 @@ obj-$(CONFIG_ARCH_MMP)                  += irq-mmp.o
  62  obj-$(CONFIG_ARCH_MVEBU)               += irq-armada-370-xp.o
  63  obj-$(CONFIG_ARCH_MXS)                 += irq-mxs.o
  64  obj-$(CONFIG_ARCH_S3C24XX)             += irq-s3c24xx.o
  65 +obj-$(CONFIG_BCM6345_EXT_IRQ)          += irq-bcm6345-ext.o
  66  obj-$(CONFIG_BCM6345_L2_IRQ)           += irq-bcm6345-l2.o
  67  obj-$(CONFIG_DW_APB_ICTL)              += irq-dw-apb-ictl.o
  68  obj-$(CONFIG_METAG)                    += irq-metag-ext.o
  69 --- /dev/null
  70 +++ b/drivers/irqchip/irq-bcm6345-ext.c
  71 @@ -0,0 +1,296 @@
  72 +/*
  73 + * This file is subject to the terms and conditions of the GNU General Public
  74 + * License.  See the file "COPYING" in the main directory of this archive
  75 + * for more details.
  76 + *
  77 + * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>
  78 +i */
  79 +
  80 +#include <linux/ioport.h>
  81 +#include <linux/irq.h>
  82 +#include <linux/irqchip/chained_irq.h>
  83 +#include <linux/irqchip/irq-bcm6345-ext-intc.h>
  84 +#include <linux/kernel.h>
  85 +#include <linux/of.h>
  86 +#include <linux/of_irq.h>
  87 +#include <linux/of_address.h>
  88 +#include <linux/slab.h>
  89 +#include <linux/spinlock.h>
  90 +
  91 +#include "irqchip.h"
  92 +
  93 +#ifdef CONFIG_BCM63XX
  94 +#include <asm/mach-bcm63xx/bcm63xx_irq.h>
  95 +
  96 +#define VIRQ_BASE              IRQ_EXTERNAL_BASE
  97 +#else
  98 +#define VIRQ_BASE              0
  99 +#endif
 100 +
 101 +#define MAX_IRQS               4
 102 +
 103 +#define EXTIRQ_CFG_SENSE       0
 104 +#define EXTIRQ_CFG_STAT                1
 105 +#define EXTIRQ_CFG_CLEAR       2
 106 +#define EXTIRQ_CFG_MASK                3
 107 +#define EXTIRQ_CFG_BOTHEDGE    4
 108 +#define EXTIRQ_CFG_LEVELSENSE  5
 109 +
 110 +struct intc_data {
 111 +       struct irq_chip chip;
 112 +       struct irq_domain *domain;
 113 +       spinlock_t lock;
 114 +
 115 +       int parent_irq[MAX_IRQS];
 116 +       void __iomem *reg;
 117 +       int shift;
 118 +};
 119 +
 120 +static void bcm6345_ext_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
 121 +{
 122 +       struct intc_data *data = irq_desc_get_handler_data(desc);
 123 +       struct irq_chip *chip = irq_desc_get_chip(desc);
 124 +       unsigned int idx;
 125 +
 126 +       chained_irq_enter(chip, desc);
 127 +
 128 +       for (idx = 0; idx < MAX_IRQS; idx++) {
 129 +               if (data->parent_irq[idx] != irq)
 130 +                       continue;
 131 +
 132 +               generic_handle_irq(irq_find_mapping(data->domain, idx));
 133 +       }
 134 +
 135 +       chained_irq_exit(chip, desc);
 136 +}
 137 +
 138 +static void bcm6345_ext_intc_irq_ack(struct irq_data *data)
 139 +{
 140 +       struct intc_data *priv = data->domain->host_data;
 141 +       irq_hw_number_t hwirq = irqd_to_hwirq(data);
 142 +       u32 reg;
 143 +
 144 +       raw_spin_lock(priv->lock);
 145 +       reg = __raw_readl(priv->reg);
 146 +       reg |= hwirq << (EXTIRQ_CFG_CLEAR * priv->shift);
 147 +       __raw_writel(reg, priv->reg);
 148 +       raw_spin_unlock(priv->lock);
 149 +}
 150 +
 151 +static void bcm6345_ext_intc_irq_mask(struct irq_data *data)
 152 +{
 153 +       struct intc_data *priv = data->domain->host_data;
 154 +       irq_hw_number_t hwirq = irqd_to_hwirq(data);
 155 +       u32 reg;
 156 +
 157 +       raw_spin_lock(priv->lock);
 158 +       reg = __raw_readl(priv->reg);
 159 +       reg &= ~(hwirq << (EXTIRQ_CFG_MASK * priv->shift));
 160 +       __raw_writel(reg, priv->reg);
 161 +       raw_spin_unlock(priv->lock);
 162 +}
 163 +
 164 +static void bcm6345_ext_intc_irq_unmask(struct irq_data *data)
 165 +{
 166 +       struct intc_data *priv = data->domain->host_data;
 167 +       irq_hw_number_t hwirq = irqd_to_hwirq(data);
 168 +       u32 reg;
 169 +
 170 +       raw_spin_lock(priv->lock);
 171 +       reg = __raw_readl(priv->reg);
 172 +       reg |= hwirq << (EXTIRQ_CFG_MASK * priv->shift);
 173 +       __raw_writel(reg, priv->reg);
 174 +       raw_spin_unlock(priv->lock);
 175 +}
 176 +
 177 +static int bcm6345_ext_intc_set_type(struct irq_data *data,
 178 +                                    unsigned int flow_type)
 179 +{
 180 +       struct intc_data *priv = data->domain->host_data;
 181 +       irq_hw_number_t hwirq = irqd_to_hwirq(data);
 182 +       bool levelsense = 0, sense = 0, bothedge = 0;
 183 +       u32 reg;
 184 +
 185 +       flow_type &= IRQ_TYPE_SENSE_MASK;
 186 +
 187 +       if (flow_type == IRQ_TYPE_NONE)
 188 +               flow_type = IRQ_TYPE_LEVEL_LOW;
 189 +
 190 +       switch (flow_type) {
 191 +       case IRQ_TYPE_EDGE_BOTH:
 192 +               bothedge = 1;
 193 +               break;
 194 +
 195 +       case IRQ_TYPE_EDGE_RISING:
 196 +               break;
 197 +
 198 +       case IRQ_TYPE_EDGE_FALLING:
 199 +               sense = 1;
 200 +               break;
 201 +
 202 +       case IRQ_TYPE_LEVEL_HIGH:
 203 +               levelsense = 1;
 204 +               sense = 1;
 205 +               break;
 206 +
 207 +       case IRQ_TYPE_LEVEL_LOW:
 208 +               levelsense = 1;
 209 +               break;
 210 +
 211 +       default:
 212 +               pr_err("bogus flow type combination given!\n");
 213 +               return -EINVAL;
 214 +       }
 215 +
 216 +       raw_spin_lock(priv->lock);
 217 +       reg = __raw_readl(priv->reg);
 218 +
 219 +       if (levelsense)
 220 +               reg |= hwirq << (EXTIRQ_CFG_LEVELSENSE * priv->shift);
 221 +       else
 222 +               reg &= ~(hwirq << (EXTIRQ_CFG_LEVELSENSE * priv->shift));
 223 +       if (sense)
 224 +               reg |= hwirq << (EXTIRQ_CFG_SENSE * priv->shift);
 225 +       else
 226 +               reg &= ~(hwirq << (EXTIRQ_CFG_SENSE * priv->shift));
 227 +       if (bothedge)
 228 +               reg |= hwirq << (EXTIRQ_CFG_BOTHEDGE * priv->shift);
 229 +       else
 230 +               reg &= ~(hwirq << (EXTIRQ_CFG_BOTHEDGE * priv->shift));
 231 +
 232 +       __raw_writel(reg, priv->reg);
 233 +       raw_spin_unlock(priv->lock);
 234 +
 235 +       irqd_set_trigger_type(data, flow_type);
 236 +       if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 237 +               __irq_set_handler_locked(data->irq, handle_level_irq);
 238 +       else
 239 +               __irq_set_handler_locked(data->irq, handle_edge_irq);
 240 +
 241 +       return 0;
 242 +}
 243 +
 244 +static int bcm6345_ext_intc_map(struct irq_domain *d, unsigned int irq,
 245 +                         irq_hw_number_t hw)
 246 +{
 247 +       struct intc_data *priv = d->host_data;
 248 +
 249 +       irq_set_chip_and_handler(irq, &priv->chip, handle_level_irq);
 250 +
 251 +       return 0;
 252 +}
 253 +
 254 +
 255 +static const struct irq_domain_ops bcm6345_ext_domain_ops = {
 256 +       .xlate = irq_domain_xlate_twocell,
 257 +       .map = bcm6345_ext_intc_map,
 258 +};
 259 +
 260 +static int __init __bcm6345_ext_intc_init(struct device_node *node,
 261 +                                         int num_irqs, int *irqs,
 262 +                                         void __iomem *reg, int shift)
 263 +{
 264 +       struct intc_data *data;
 265 +       unsigned int i;
 266 +       int start = VIRQ_BASE;
 267 +
 268 +       data = kzalloc(sizeof(*data), GFP_KERNEL);
 269 +       if (!data)
 270 +               return -ENOMEM;
 271 +
 272 +       for (i = 0; i < num_irqs; i++) {
 273 +               data->parent_irq[i] = irqs[i];
 274 +
 275 +               irq_set_handler_data(irqs[i], data);
 276 +               irq_set_chained_handler(irqs[i], bcm6345_ext_intc_irq_handle);
 277 +       }
 278 +
 279 +       data->reg = reg;
 280 +
 281 +       data->chip.name = "bcm6345-ext-intc";
 282 +       data->chip.irq_ack = bcm6345_ext_intc_irq_ack;
 283 +       data->chip.irq_mask = bcm6345_ext_intc_irq_mask;
 284 +       data->chip.irq_unmask = bcm6345_ext_intc_irq_unmask;
 285 +       data->chip.irq_set_type = bcm6345_ext_intc_set_type;
 286 +
 287 +       /*
 288 +        * If we have less than 4 irqs, this is the second controller on
 289 +        * bcm63xx. So increase the VIRQ start to not overlap with the first
 290 +        * one, but only do so if we actually use a non-zero start.
 291 +        *
 292 +        * This can be removed when bcm63xx has no legacy users anymore.
 293 +        */
 294 +       if (start && num_irqs < 4)
 295 +               start += 4;
 296 +
 297 +       data->domain = irq_domain_add_simple(node, num_irqs, start,
 298 +                                            &bcm6345_ext_domain_ops, data);
 299 +       if (!data->domain) {
 300 +               kfree(data);
 301 +               return -ENOMEM;
 302 +       }
 303 +
 304 +       return 0;
 305 +}
 306 +
 307 +void __init bcm6345_ext_intc_init(int num_irqs, int *irqs, void __iomem *reg,
 308 +                                 int shift)
 309 +{
 310 +       __bcm6345_ext_intc_init(NULL, num_irqs, irqs, reg, shift);
 311 +}
 312 +
 313 +#ifdef CONFIG_OF
 314 +static int __init bcm63xx_ext_intc_of_init(struct device_node *node,
 315 +                                          struct device_node *parent,
 316 +                                          int shift)
 317 +{
 318 +       int num_irqs, ret = -EINVAL;
 319 +       unsigned i;
 320 +       void __iomem *base;
 321 +       int irqs[MAX_IRQS] = { 0 };
 322 +
 323 +       num_irqs = of_irq_count(node);
 324 +
 325 +       if (!num_irqs || num_irqs > MAX_IRQS)
 326 +               return -EINVAL;
 327 +
 328 +       for (i = 0; i < num_irqs; i++) {
 329 +               irqs[i] = irq_of_parse_and_map(node, i);
 330 +               if (!irqs[i]) {
 331 +                       ret = -ENOMEM;
 332 +                       goto out_unmap;
 333 +               }
 334 +       }
 335 +
 336 +       base = of_iomap(node, 0);
 337 +       if (!base)
 338 +               goto out_unmap;
 339 +
 340 +       ret = __bcm6345_ext_intc_init(node, num_irqs, irqs, base, shift);
 341 +       if (!ret)
 342 +               return 0;
 343 +out_unmap:
 344 +       iounmap(base);
 345 +
 346 +       for (i = 0; i < num_irqs; i++)
 347 +               irq_dispose_mapping(irqs[i]);
 348 +
 349 +       return ret;
 350 +}
 351 +
 352 +static int __init bcm6345_ext_intc_of_init(struct device_node *node,
 353 +                                          struct device_node *parent)
 354 +{
 355 +       return bcm63xx_ext_intc_of_init(node, parent, 4);
 356 +}
 357 +static int __init bcm6348_ext_intc_of_init(struct device_node *node,
 358 +                                          struct device_node *parent)
 359 +{
 360 +       return bcm63xx_ext_intc_of_init(node, parent, 5);
 361 +}
 362 +
 363 +IRQCHIP_DECLARE(bcm6345_ext_intc, "brcm,bcm6345-ext-intc",
 364 +               bcm6345_ext_intc_of_init);
 365 +IRQCHIP_DECLARE(bcm6348_ext_intc, "brcm,bcm6348-ext-intc",
 366 +               bcm6348_ext_intc_of_init);
 367 +#endif
 368 --- /dev/null
 369 +++ b/include/linux/irqchip/irq-bcm6345-ext-intc.h
 370 @@ -0,0 +1,14 @@
 371 +/*
 372 + * This file is subject to the terms and conditions of the GNU General Public
 373 + * License.  See the file "COPYING" in the main directory of this archive
 374 + * for more details.
 375 + *
 376 + * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>
 377 + */
 378 +
 379 +#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_INTC_H
 380 +#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_INTC_H
 381 +
 382 +void bcm6345_ext_intc_init(int n_irqs, int *irqs, void __iomem *reg, int shift);
 383 +
 384 +#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_INTC_H */