target/linux/brcm63xx/patches-3.3/103-MIPS-BCM63XX-add-TRNG-peripheral-definitions.patch

   1 From 913c171ebfe0d589bdf6efb8fd607258c96ea54a Mon Sep 17 00:00:00 2001
   2 From: Florian Fainelli <florian@openwrt.org>
   3 Date: Wed, 25 Jan 2012 17:39:58 +0100
   4 Subject: [PATCH 16/63] MIPS: BCM63XX: add TRNG peripheral definitions
   5
   6 Signed-off-by: Florian Fainelli <florian@openwrt.org>
   7 ---
   8  arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |    9 +++++++++
   9  arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   14 ++++++++++++++
  10  2 files changed, 23 insertions(+), 0 deletions(-)
  11
  12 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
  13 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
  14 @@ -129,6 +129,7 @@ enum bcm63xx_regs_set {
  15         RSET_PCMDMA,
  16         RSET_PCMDMAC,
  17         RSET_PCMDMAS,
  18 +       RSET_TRNG
  19  };
  20
  21  #define RSET_DSL_LMEM_SIZE             (64 * 1024 * 4)
  22 @@ -152,6 +153,7 @@ enum bcm63xx_regs_set {
  23  #define RSET_XTMDMA_SIZE               256
  24  #define RSET_XTMDMAC_SIZE(chans)       (16 * (chans))
  25  #define RSET_XTMDMAS_SIZE(chans)       (16 * (chans))
  26 +#define RSET_TRNG_SIZE                 20
  27
  28  /*
  29   * 6338 register sets base address
  30 @@ -195,6 +197,7 @@ enum bcm63xx_regs_set {
  31  #define BCM_6338_PCMDMA_BASE           (0xdeadbeef)
  32  #define BCM_6338_PCMDMAC_BASE          (0xdeadbeef)
  33  #define BCM_6338_PCMDMAS_BASE          (0xdeadbeef)
  34 +#define BCM_6338_TRNG_BASE             (0xdeadbeef)
  35
  36  /*
  37   * 6345 register sets base address
  38 @@ -238,6 +241,7 @@ enum bcm63xx_regs_set {
  39  #define BCM_6345_PCMDMA_BASE           (0xdeadbeef)
  40  #define BCM_6345_PCMDMAC_BASE          (0xdeadbeef)
  41  #define BCM_6345_PCMDMAS_BASE          (0xdeadbeef)
  42 +#define BCM_6345_TRNG_BASE             (0xdeadbeef)
  43
  44  /*
  45   * 6348 register sets base address
  46 @@ -278,6 +282,7 @@ enum bcm63xx_regs_set {
  47  #define BCM_6348_PCMDMA_BASE           (0xdeadbeef)
  48  #define BCM_6348_PCMDMAC_BASE          (0xdeadbeef)
  49  #define BCM_6348_PCMDMAS_BASE          (0xdeadbeef)
  50 +#define BCM_6348_TRNG_BASE             (0xdeadbeef)
  51
  52  /*
  53   * 6358 register sets base address
  54 @@ -318,6 +323,7 @@ enum bcm63xx_regs_set {
  55  #define BCM_6358_PCMDMA_BASE           (0xfffe1800)
  56  #define BCM_6358_PCMDMAC_BASE          (0xfffe1900)
  57  #define BCM_6358_PCMDMAS_BASE          (0xfffe1a00)
  58 +#define BCM_6358_TRNG_BASE             (0xdeadbeef)
  59
  60
  61  /*
  62 @@ -359,6 +365,7 @@ enum bcm63xx_regs_set {
  63  #define BCM_6368_PCMDMA_BASE           (0xb0005800)
  64  #define BCM_6368_PCMDMAC_BASE          (0xb0005a00)
  65  #define BCM_6368_PCMDMAS_BASE          (0xb0005c00)
  66 +#define BCM_6368_TRNG_BASE             (0xb0004180)
  67
  68
  69  extern const unsigned long *bcm63xx_regs_base;
  70 @@ -404,6 +411,7 @@ extern const unsigned long *bcm63xx_regs
  71         __GEN_RSET_BASE(__cpu, PCMDMA)                                  \
  72         __GEN_RSET_BASE(__cpu, PCMDMAC)                                 \
  73         __GEN_RSET_BASE(__cpu, PCMDMAS)                                 \
  74 +       __GEN_RSET_BASE(__cpu, TRNG)                                    \
  75         }
  76
  77  #define __GEN_CPU_REGS_TABLE(__cpu)                                    \
  78 @@ -442,6 +450,7 @@ extern const unsigned long *bcm63xx_regs
  79         [RSET_PCMDMA]           = BCM_## __cpu ##_PCMDMA_BASE,          \
  80         [RSET_PCMDMAC]          = BCM_## __cpu ##_PCMDMAC_BASE,         \
  81         [RSET_PCMDMAS]          = BCM_## __cpu ##_PCMDMAS_BASE,         \
  82 +       [RSET_TRNG]             = BCM_## __cpu ##_TRNG_BASE,            \
  83
  84
  85  static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
  86 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
  87 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
  88 @@ -1099,4 +1099,18 @@
  89  #define SPI_SSOFFTIME_SHIFT            3
  90  #define SPI_BYTE_SWAP                  0x80
  91
  92 +/*************************************************************************
  93 + * _REG relative to RSET_TRNG
  94 + *************************************************************************/
  95 +
  96 +#define TRNG_CTRL                      0x00
  97 +#define TRNG_EN                                (1 << 0)
  98 +
  99 +#define TRNG_STAT                      0x04
 100 +#define TRNG_AVAIL_MASK                        (0xff000000)
 101 +
 102 +#define TRNG_DATA                      0x08
 103 +#define TRNG_THRES                     0x0c
 104 +#define TRNG_MASK                      0x10
 105 +
 106  #endif /* BCM63XX_REGS_H_ */