target/linux/brcm63xx/patches-4.1/342-MIPS-BCM63XX-split-PCIe-reset-signals.patch

   1 From 4bdfacdeaf3c988c4f3256c88118893eac640b03 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jogo@openwrt.org>
   3 Date: Sun, 8 Dec 2013 14:17:50 +0100
   4 Subject: [PATCH 52/53] MIPS: BCM63XX: split PCIE reset signals
   5
   6 ---
   7  arch/mips/bcm63xx/reset.c                          | 39 ++++++++++++++--------
   8  arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h |  2 ++
   9  arch/mips/pci/pci-bcm63xx.c                        |  7 ++++
  10  3 files changed, 34 insertions(+), 14 deletions(-)
  11
  12 --- a/arch/mips/bcm63xx/reset.c
  13 +++ b/arch/mips/bcm63xx/reset.c
  14 @@ -28,7 +28,9 @@
  15         [BCM63XX_RESET_PCM]             = BCM## __cpu ##_RESET_PCM,     \
  16         [BCM63XX_RESET_MPI]             = BCM## __cpu ##_RESET_MPI,     \
  17         [BCM63XX_RESET_PCIE]            = BCM## __cpu ##_RESET_PCIE,    \
  18 -       [BCM63XX_RESET_PCIE_EXT]        = BCM## __cpu ##_RESET_PCIE_EXT,
  19 +       [BCM63XX_RESET_PCIE_EXT]        = BCM## __cpu ##_RESET_PCIE_EXT, \
  20 +       [BCM63XX_RESET_PCIE_CORE]       = BCM## __cpu ##_RESET_PCIE_CORE, \
  21 +       [BCM63XX_RESET_PCIE_HARD]       = BCM## __cpu ##_RESET_PCIE_HARD,
  22
  23  #define BCM3368_RESET_SPI      SOFTRESET_3368_SPI_MASK
  24  #define BCM3368_RESET_ENET     SOFTRESET_3368_ENET_MASK
  25 @@ -42,6 +44,8 @@
  26  #define BCM3368_RESET_MPI      SOFTRESET_3368_MPI_MASK
  27  #define BCM3368_RESET_PCIE     0
  28  #define BCM3368_RESET_PCIE_EXT 0
  29 +#define BCM3368_RESET_PCIE_CORE        0
  30 +#define BCM3368_RESET_PCIE_HARD        0
  31
  32
  33  #define BCM6318_RESET_SPI      SOFTRESET_6318_SPI_MASK
  34 @@ -54,11 +58,10 @@
  35  #define BCM6318_RESET_ENETSW   SOFTRESET_6318_ENETSW_MASK
  36  #define BCM6318_RESET_PCM      0
  37  #define BCM6318_RESET_MPI      0
  38 -#define BCM6318_RESET_PCIE     \
  39 -                               (SOFTRESET_6318_PCIE_MASK |             \
  40 -                                SOFTRESET_6318_PCIE_CORE_MASK |        \
  41 -                                SOFTRESET_6318_PCIE_HARD_MASK)
  42 +#define BCM6318_RESET_PCIE     SOFTRESET_6318_PCIE_MASK
  43  #define BCM6318_RESET_PCIE_EXT SOFTRESET_6318_PCIE_EXT_MASK
  44 +#define BCM6318_RESET_PCIE_CORE        SOFTRESET_6318_PCIE_CORE_MASK
  45 +#define BCM6318_RESET_PCIE_HARD        SOFTRESET_6318_PCIE_HARD_MASK
  46
  47  #define BCM6328_RESET_SPI      SOFTRESET_6328_SPI_MASK
  48  #define BCM6328_RESET_ENET     0
  49 @@ -70,11 +73,10 @@
  50  #define BCM6328_RESET_ENETSW   SOFTRESET_6328_ENETSW_MASK
  51  #define BCM6328_RESET_PCM      SOFTRESET_6328_PCM_MASK
  52  #define BCM6328_RESET_MPI      0
  53 -#define BCM6328_RESET_PCIE     \
  54 -                               (SOFTRESET_6328_PCIE_MASK |             \
  55 -                                SOFTRESET_6328_PCIE_CORE_MASK |        \
  56 -                                SOFTRESET_6328_PCIE_HARD_MASK)
  57 +#define BCM6328_RESET_PCIE     SOFTRESET_6328_PCIE_MASK
  58  #define BCM6328_RESET_PCIE_EXT SOFTRESET_6328_PCIE_EXT_MASK
  59 +#define BCM6328_RESET_PCIE_CORE        SOFTRESET_6328_PCIE_CORE_MASK
  60 +#define BCM6328_RESET_PCIE_HARD        SOFTRESET_6328_PCIE_HARD_MASK
  61
  62  #define BCM6338_RESET_SPI      SOFTRESET_6338_SPI_MASK
  63  #define BCM6338_RESET_ENET     SOFTRESET_6338_ENET_MASK
  64 @@ -88,6 +90,8 @@
  65  #define BCM6338_RESET_MPI      0
  66  #define BCM6338_RESET_PCIE     0
  67  #define BCM6338_RESET_PCIE_EXT 0
  68 +#define BCM6338_RESET_PCIE_CORE        0
  69 +#define BCM6338_RESET_PCIE_HARD        0
  70
  71  #define BCM6348_RESET_SPI      SOFTRESET_6348_SPI_MASK
  72  #define BCM6348_RESET_ENET     SOFTRESET_6348_ENET_MASK
  73 @@ -101,6 +105,8 @@
  74  #define BCM6348_RESET_MPI      0
  75  #define BCM6348_RESET_PCIE     0
  76  #define BCM6348_RESET_PCIE_EXT 0
  77 +#define BCM6348_RESET_PCIE_CORE        0
  78 +#define BCM6348_RESET_PCIE_HARD        0
  79
  80  #define BCM6358_RESET_SPI      SOFTRESET_6358_SPI_MASK
  81  #define BCM6358_RESET_ENET     SOFTRESET_6358_ENET_MASK
  82 @@ -114,6 +120,8 @@
  83  #define BCM6358_RESET_MPI      SOFTRESET_6358_MPI_MASK
  84  #define BCM6358_RESET_PCIE     0
  85  #define BCM6358_RESET_PCIE_EXT 0
  86 +#define BCM6358_RESET_PCIE_CORE        0
  87 +#define BCM6358_RESET_PCIE_HARD        0
  88
  89  #define BCM6362_RESET_SPI      SOFTRESET_6362_SPI_MASK
  90  #define BCM6362_RESET_ENET     0
  91 @@ -125,9 +133,10 @@
  92  #define BCM6362_RESET_ENETSW   SOFTRESET_6362_ENETSW_MASK
  93  #define BCM6362_RESET_PCM      SOFTRESET_6362_PCM_MASK
  94  #define BCM6362_RESET_MPI      0
  95 -#define BCM6362_RESET_PCIE      (SOFTRESET_6362_PCIE_MASK | \
  96 -                                SOFTRESET_6362_PCIE_CORE_MASK)
  97 +#define BCM6362_RESET_PCIE      SOFTRESET_6362_PCIE_MASK
  98  #define BCM6362_RESET_PCIE_EXT SOFTRESET_6362_PCIE_EXT_MASK
  99 +#define BCM6362_RESET_PCIE_CORE        SOFTRESET_6362_PCIE_CORE_MASK
 100 +#define BCM6362_RESET_PCIE_HARD        0
 101
 102  #define BCM6368_RESET_SPI      SOFTRESET_6368_SPI_MASK
 103  #define BCM6368_RESET_ENET     0
 104 @@ -141,6 +150,8 @@
 105  #define BCM6368_RESET_MPI      SOFTRESET_6368_MPI_MASK
 106  #define BCM6368_RESET_PCIE     0
 107  #define BCM6368_RESET_PCIE_EXT 0
 108 +#define BCM6368_RESET_PCIE_CORE        0
 109 +#define BCM6368_RESET_PCIE_HARD        0
 110
 111  #define BCM63268_RESET_SPI     SOFTRESET_63268_SPI_MASK
 112  #define BCM63268_RESET_ENET    0
 113 @@ -152,10 +163,10 @@
 114  #define BCM63268_RESET_ENETSW  SOFTRESET_63268_ENETSW_MASK
 115  #define BCM63268_RESET_PCM     SOFTRESET_63268_PCM_MASK
 116  #define BCM63268_RESET_MPI     0
 117 -#define BCM63268_RESET_PCIE    (SOFTRESET_63268_PCIE_MASK | \
 118 -                                SOFTRESET_63268_PCIE_CORE_MASK | \
 119 -                                SOFTRESET_63268_PCIE_HARD_MASK)
 120 +#define BCM63268_RESET_PCIE    SOFTRESET_63268_PCIE_MASK
 121  #define BCM63268_RESET_PCIE_EXT        SOFTRESET_63268_PCIE_EXT_MASK
 122 +#define BCM63268_RESET_PCIE_CORE       SOFTRESET_63268_PCIE_CORE_MASK
 123 +#define BCM63268_RESET_PCIE_HARD       SOFTRESET_63268_PCIE_HARD_MASK
 124
 125  /*
 126   * core reset bits
 127 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h
 128 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h
 129 @@ -14,6 +14,8 @@ enum bcm63xx_core_reset {
 130         BCM63XX_RESET_MPI,
 131         BCM63XX_RESET_PCIE,
 132         BCM63XX_RESET_PCIE_EXT,
 133 +       BCM63XX_RESET_PCIE_CORE,
 134 +       BCM63XX_RESET_PCIE_HARD,
 135  };
 136
 137  void bcm63xx_core_set_reset(enum bcm63xx_core_reset, int reset);
 138 --- a/arch/mips/pci/pci-bcm63xx.c
 139 +++ b/arch/mips/pci/pci-bcm63xx.c
 140 @@ -135,9 +135,16 @@ static void __init bcm63xx_reset_pcie(vo
 141
 142         /* reset the PCIe core */
 143         bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);
 144 +       bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 1);
 145         bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1);
 146 +       if (BCMCPU_IS_6328() || BCMCPU_IS_63268()) {
 147 +               bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 1);
 148 +               mdelay(10);
 149 +               bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 0);
 150 +       }
 151         mdelay(10);
 152
 153 +       bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 0);
 154         bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0);
 155         mdelay(10);
 156