target/linux/brcm63xx/patches-4.1/345-MIPS-BCM63XX-fixup-mapped-SPI-flash-access-on-boot.patch

   1 From 1cacd0f7b0d35f8e3d3f8a69ecb3b5e436d6b9e8 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jogo@openwrt.org>
   3 Date: Sun, 22 Dec 2013 13:25:25 +0100
   4 Subject: [PATCH 52/56] MIPS: BCM63XX: fixup mapped SPI flash access on boot
   5
   6 Some bootloaders leave the flash access in an invalid state with dual
   7 read enabled; fix it by disabling it and falling back to simple fast
   8 reads.
   9
  10 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  11 ---
  12  arch/mips/bcm63xx/dev-flash.c | 51 ++++++++++++++++++++++++++++++++++++
  13  1 file changed, 51 insertions(+)
  14
  15 --- a/arch/mips/bcm63xx/dev-flash.c
  16 +++ b/arch/mips/bcm63xx/dev-flash.c
  17 @@ -16,6 +16,7 @@
  18  #include <linux/mtd/mtd.h>
  19  #include <linux/mtd/partitions.h>
  20  #include <linux/mtd/physmap.h>
  21 +#include <linux/mtd/spi-nor.h>
  22
  23  #include <bcm63xx_cpu.h>
  24  #include <bcm63xx_dev_flash.h>
  25 @@ -110,9 +111,59 @@ static int __init bcm63xx_detect_flash_t
  26         }
  27  }
  28
  29 +#define HSSPI_FLASH_CTRL_REG           0x14
  30 +#define FLASH_CTRL_READ_OPCODE_MASK    0xff
  31 +#define FLASH_CTRL_ADDR_BYTES_MASK     (0x3 << 8)
  32 +#define FLASH_CTRL_ADDR_BYTES_2                (0 << 8)
  33 +#define FLASH_CTRL_ADDR_BYTES_3                (1 << 8)
  34 +#define FLASH_CTRL_ADDR_BYTES_4                (2 << 8)
  35 +#define FLASH_CTRL_DUMMY_BYTES_SHIFT   10
  36 +#define FLASH_CTRL_DUMMY_BYTES_MASK    (0x3 << FLASH_CTRL_DUMMY_BYTES_SHIFT)
  37 +#define FLASH_CTRL_MB_EN               (1 << 23)
  38 +
  39  void __init bcm63xx_flash_detect(void)
  40  {
  41         flash_type = bcm63xx_detect_flash_type();
  42 +
  43 +       /* ensure flash mapping has sane values */
  44 +       if (flash_type == BCM63XX_FLASH_TYPE_SERIAL &&
  45 +           (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() ||
  46 +            BCMCPU_IS_63268())) {
  47 +               u32 val = bcm_rset_readl(RSET_HSSPI, HSSPI_FLASH_CTRL_REG);
  48 +
  49 +               if (val & FLASH_CTRL_MB_EN) {
  50 +                       /* cfe might configure non working dual-io mode */
  51 +                       val &= ~FLASH_CTRL_MB_EN;
  52 +                       val &= ~FLASH_CTRL_READ_OPCODE_MASK;
  53 +                       val &= ~FLASH_CTRL_DUMMY_BYTES_MASK;
  54 +                       val |= 1 << FLASH_CTRL_DUMMY_BYTES_SHIFT;
  55 +
  56 +                       switch (val & FLASH_CTRL_ADDR_BYTES_MASK) {
  57 +                       case FLASH_CTRL_ADDR_BYTES_3:
  58 +                               val |= SPINOR_OP_READ_FAST;
  59 +                               break;
  60 +                       case FLASH_CTRL_ADDR_BYTES_4:
  61 +                               val |= SPINOR_OP_READ4_FAST;
  62 +                               break;
  63 +                       case FLASH_CTRL_ADDR_BYTES_2:
  64 +                       default:
  65 +                               pr_warn("unsupported address byte mode (%x), not fixing up\n",
  66 +                                       val & FLASH_CTRL_ADDR_BYTES_MASK);
  67 +                               return;
  68 +                       }
  69 +               } else {
  70 +                       /* ensure dummy bytes is set to 1 for _FAST reads */
  71 +                       u8 cmd = val & FLASH_CTRL_READ_OPCODE_MASK;
  72 +
  73 +                       if (cmd != SPINOR_OP_READ_FAST && cmd != SPINOR_OP_READ4_FAST)
  74 +                               return;
  75 +
  76 +                       val &= ~FLASH_CTRL_DUMMY_BYTES_MASK;
  77 +                       val |= 1 << FLASH_CTRL_DUMMY_BYTES_SHIFT;
  78 +               }
  79 +
  80 +               bcm_rset_writel(RSET_HSSPI, val, HSSPI_FLASH_CTRL_REG);
  81 +       }
  82  }
  83
  84  int __init bcm63xx_flash_register(void)