target/linux/brcm63xx/patches-4.9/320-irqchip-add-support-for-bcm6345-style-periphery-irq-.patch

   1 From 301744ecbeece89ab3a9d6beef7802fa22598f00 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jogo@openwrt.org>
   3 Date: Sun, 30 Nov 2014 14:53:12 +0100
   4 Subject: [PATCH 1/5] irqchip: add support for bcm6345-style periphery irq
   5  controller
   6
   7 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
   8 ---
   9  .../brcm,bcm6345-periph-intc.txt                   |   50 +++
  10  drivers/irqchip/Kconfig                            |    4 +
  11  drivers/irqchip/Makefile                           |    1 +
  12  drivers/irqchip/irq-bcm6345-periph.c               |  339 ++++++++++++++++++++
  13  include/linux/irqchip/irq-bcm6345-periph.h         |   16 +
  14  5 files changed, 410 insertions(+)
  15  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-periph-intc.txt
  16  create mode 100644 drivers/irqchip/irq-bcm6345-periph.c
  17  create mode 100644 include/linux/irqchip/irq-bcm6345-periph.h
  18
  19 --- /dev/null
  20 +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-periph-intc.txt
  21 @@ -0,0 +1,50 @@
  22 +Broadcom BCM6345 Level 1 periphery interrupt controller
  23 +
  24 +This block is a  interrupt controller that is typically connected directly
  25 +to one of the HW INT lines on each CPU.  Every BCM63XX xDSL chip since
  26 +BCM6345 has contained this hardware.
  27 +
  28 +Key elements of the hardware design include:
  29 +
  30 +- 32, 64, or 128 incoming level IRQ lines
  31 +
  32 +- All onchip peripherals are wired directly to an L2 input
  33 +
  34 +- A separate instance of the register set for each CPU, allowing individual
  35 +  peripheral IRQs to be routed to any CPU
  36 +
  37 +- No atomic mask/unmask operations
  38 +
  39 +- No polarity/level/edge settings
  40 +
  41 +- No FIFO or priority encoder logic; software is expected to read all
  42 +  1-4 status words to determine which IRQs are pending
  43 +
  44 +Required properties:
  45 +
  46 +- compatible: Should be "brcm,bcm6345-periph-intc".
  47 +- reg: Specifies the base physical address and size of the registers.
  48 +  Multiple register addresses may be specified, and must match the amount of
  49 +  parent interrupts.
  50 +- interrupt-controller: Identifies the node as an interrupt controller.
  51 +- #interrupt-cells: Specifies the number of cells needed to encode an interrupt
  52 +  source, should be 1.
  53 +- interrupt-parent: Specifies the phandle to the parent interrupt controller
  54 +  this one is cascaded from.
  55 +- interrupts: Specifies the interrupt line(s) in the interrupt-parent controller
  56 +  node, valid values depend on the type of parent interrupt controller.
  57 +  Multiple lines are used to route interrupts to different cpus, with the first
  58 +  assumed to be for the boot CPU.
  59 +
  60 +Example:
  61 +
  62 +periph_intc: interrupt-controller@f0406800 {
  63 +       compatible = "brcm,bcm6345-periph-intc";
  64 +       reg = <0x10000020 0x10>, <0x10000030 0x10>;
  65 +
  66 +       interrupt-controller;
  67 +       #interrupt-cells = <1>;
  68 +
  69 +       interrupt-parent = <&cpu_intc>;
  70 +       interrupts = <2>, <3>;
  71 +};
  72 --- a/drivers/irqchip/Kconfig
  73 +++ b/drivers/irqchip/Kconfig
  74 @@ -110,6 +110,10 @@ config BRCMSTB_L2_IRQ
  75         select GENERIC_IRQ_CHIP
  76         select IRQ_DOMAIN
  77
  78 +config BCM6345_PERIPH_IRQ
  79 +       bool
  80 +       select IRQ_DOMAIN
  81 +
  82  config DW_APB_ICTL
  83         bool
  84         select GENERIC_IRQ_CHIP
  85 --- a/drivers/irqchip/Makefile
  86 +++ b/drivers/irqchip/Makefile
  87 @@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_MMP)                        += irq-mmp.o
  88  obj-$(CONFIG_IRQ_MXS)                  += irq-mxs.o
  89  obj-$(CONFIG_ARCH_TEGRA)               += irq-tegra.o
  90  obj-$(CONFIG_ARCH_S3C24XX)             += irq-s3c24xx.o
  91 +obj-$(CONFIG_BCM6345_PERIPH_IRQ)       += irq-bcm6345-periph.o
  92  obj-$(CONFIG_DW_APB_ICTL)              += irq-dw-apb-ictl.o
  93  obj-$(CONFIG_METAG)                    += irq-metag-ext.o
  94  obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)   += irq-metag.o
  95 --- /dev/null
  96 +++ b/drivers/irqchip/irq-bcm6345-periph.c
  97 @@ -0,0 +1,339 @@
  98 +/*
  99 + * This file is subject to the terms and conditions of the GNU General Public
 100 + * License.  See the file "COPYING" in the main directory of this archive
 101 + * for more details.
 102 + *
 103 + * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>
 104 + */
 105 +
 106 +#include <linux/ioport.h>
 107 +#include <linux/irq.h>
 108 +#include <linux/irqchip.h>
 109 +#include <linux/irqchip/chained_irq.h>
 110 +#include <linux/irqchip/irq-bcm6345-periph.h>
 111 +#include <linux/kernel.h>
 112 +#include <linux/of.h>
 113 +#include <linux/of_irq.h>
 114 +#include <linux/of_address.h>
 115 +#include <linux/slab.h>
 116 +#include <linux/spinlock.h>
 117 +
 118 +#ifdef CONFIG_BCM63XX
 119 +#include <asm/mach-bcm63xx/bcm63xx_irq.h>
 120 +
 121 +#define VIRQ_BASE      IRQ_INTERNAL_BASE
 122 +#else
 123 +#define VIRQ_BASE      0
 124 +#endif
 125 +
 126 +#define MAX_WORDS      4
 127 +#define MAX_PARENT_IRQS        2
 128 +#define IRQS_PER_WORD  32
 129 +
 130 +struct intc_block {
 131 +       int parent_irq;
 132 +       void __iomem *base;
 133 +       void __iomem *en_reg[MAX_WORDS];
 134 +       void __iomem *status_reg[MAX_WORDS];
 135 +       u32 mask_cache[MAX_WORDS];
 136 +};
 137 +
 138 +struct intc_data {
 139 +       struct irq_chip chip;
 140 +       struct intc_block block[MAX_PARENT_IRQS];
 141 +
 142 +       int num_words;
 143 +
 144 +       struct irq_domain *domain;
 145 +       raw_spinlock_t lock;
 146 +};
 147 +
 148 +static void bcm6345_periph_irq_handle(struct irq_desc *desc)
 149 +{
 150 +       struct intc_data *data = irq_desc_get_handler_data(desc);
 151 +       struct irq_chip *chip = irq_desc_get_chip(desc);
 152 +       struct intc_block *block;
 153 +       unsigned int irq = irq_desc_get_irq(desc);
 154 +       unsigned int idx;
 155 +
 156 +       chained_irq_enter(chip, desc);
 157 +
 158 +       for (idx = 0; idx < MAX_PARENT_IRQS; idx++)
 159 +               if (irq == data->block[idx].parent_irq)
 160 +                       block = &data->block[idx];
 161 +
 162 +       for (idx = 0; idx < data->num_words; idx++) {
 163 +               int base = idx * IRQS_PER_WORD;
 164 +               unsigned long pending;
 165 +               int hw_irq;
 166 +
 167 +               raw_spin_lock(&data->lock);
 168 +               pending = __raw_readl(block->en_reg[idx]) &
 169 +                         __raw_readl(block->status_reg[idx]);
 170 +               raw_spin_unlock(&data->lock);
 171 +
 172 +               for_each_set_bit(hw_irq, &pending, IRQS_PER_WORD) {
 173 +                       int virq;
 174 +
 175 +                       virq  = irq_find_mapping(data->domain, base + hw_irq);
 176 +                       generic_handle_irq(virq);
 177 +               }
 178 +       }
 179 +
 180 +       chained_irq_exit(chip, desc);
 181 +}
 182 +
 183 +static void __bcm6345_periph_enable(struct intc_block *block, int reg, int bit,
 184 +                                   bool enable)
 185 +{
 186 +       u32 val;
 187 +
 188 +       val = __raw_readl(block->en_reg[reg]);
 189 +       if (enable)
 190 +               val |= BIT(bit);
 191 +       else
 192 +               val &= ~BIT(bit);
 193 +       __raw_writel(val, block->en_reg[reg]);
 194 +}
 195 +
 196 +static void bcm6345_periph_irq_mask(struct irq_data *data)
 197 +{
 198 +       unsigned int i, reg, bit;
 199 +       struct intc_data *priv = data->domain->host_data;
 200 +       irq_hw_number_t hwirq = irqd_to_hwirq(data);
 201 +
 202 +       reg = hwirq / IRQS_PER_WORD;
 203 +       bit = hwirq % IRQS_PER_WORD;
 204 +
 205 +       raw_spin_lock(&priv->lock);
 206 +       for (i = 0; i < MAX_PARENT_IRQS; i++) {
 207 +               struct intc_block *block = &priv->block[i];
 208 +
 209 +               if (!block->parent_irq)
 210 +                       break;
 211 +
 212 +               __bcm6345_periph_enable(block, reg, bit, false);
 213 +       }
 214 +       raw_spin_unlock(&priv->lock);
 215 +}
 216 +
 217 +static void bcm6345_periph_irq_unmask(struct irq_data *data)
 218 +{
 219 +       struct intc_data *priv = data->domain->host_data;
 220 +       irq_hw_number_t hwirq = irqd_to_hwirq(data);
 221 +       unsigned int i, reg, bit;
 222 +
 223 +       reg = hwirq / IRQS_PER_WORD;
 224 +       bit = hwirq % IRQS_PER_WORD;
 225 +
 226 +       raw_spin_lock(&priv->lock);
 227 +       for (i = 0; i < MAX_PARENT_IRQS; i++) {
 228 +               struct intc_block *block = &priv->block[i];
 229 +
 230 +               if (!block->parent_irq)
 231 +                       break;
 232 +
 233 +               if (block->mask_cache[reg] & BIT(bit))
 234 +                       __bcm6345_periph_enable(block, reg, bit, true);
 235 +               else
 236 +                       __bcm6345_periph_enable(block, reg, bit, false);
 237 +       }
 238 +       raw_spin_unlock(&priv->lock);
 239 +}
 240 +
 241 +#ifdef CONFIG_SMP
 242 +static int bcm6345_periph_set_affinity(struct irq_data *data,
 243 +                                      const struct cpumask *mask, bool force)
 244 +{
 245 +       irq_hw_number_t hwirq = irqd_to_hwirq(data);
 246 +       struct intc_data *priv = data->domain->host_data;
 247 +       unsigned int i, reg, bit;
 248 +       unsigned long flags;
 249 +       bool enabled;
 250 +       int cpu;
 251 +
 252 +       reg = hwirq / IRQS_PER_WORD;
 253 +       bit = hwirq % IRQS_PER_WORD;
 254 +
 255 +       /* we could route to more than one cpu, but performance
 256 +          suffers, so fix it to one.
 257 +        */
 258 +       cpu = cpumask_any_and(mask, cpu_online_mask);
 259 +       if (cpu >= nr_cpu_ids)
 260 +               return -EINVAL;
 261 +
 262 +       if (cpu >= MAX_PARENT_IRQS)
 263 +               return -EINVAL;
 264 +
 265 +       if (!priv->block[cpu].parent_irq)
 266 +               return -EINVAL;
 267 +
 268 +       raw_spin_lock_irqsave(&priv->lock, flags);
 269 +       enabled = !irqd_irq_masked(data);
 270 +       for (i = 0; i < MAX_PARENT_IRQS; i++) {
 271 +               struct intc_block *block = &priv->block[i];
 272 +
 273 +               if (!block->parent_irq)
 274 +                       break;
 275 +
 276 +               if (i == cpu) {
 277 +                       block->mask_cache[reg] |= BIT(bit);
 278 +                       __bcm6345_periph_enable(block, reg, bit, enabled);
 279 +               } else {
 280 +                       block->mask_cache[reg] &= ~BIT(bit);
 281 +                       __bcm6345_periph_enable(block, reg, bit, false);
 282 +               }
 283 +       }
 284 +       raw_spin_unlock_irqrestore(&priv->lock, flags);
 285 +
 286 +       return 0;
 287 +}
 288 +#endif
 289 +
 290 +static int bcm6345_periph_map(struct irq_domain *d, unsigned int irq,
 291 +                             irq_hw_number_t hw)
 292 +{
 293 +       struct intc_data *priv = d->host_data;
 294 +
 295 +       irq_set_chip_and_handler(irq, &priv->chip, handle_level_irq);
 296 +
 297 +       return 0;
 298 +}
 299 +
 300 +static const struct irq_domain_ops bcm6345_periph_domain_ops = {
 301 +       .xlate = irq_domain_xlate_onecell,
 302 +       .map = bcm6345_periph_map,
 303 +};
 304 +
 305 +static int __init __bcm6345_periph_intc_init(struct device_node *node,
 306 +                                            int num_blocks, int *irq,
 307 +                                            void __iomem **base, int num_words)
 308 +{
 309 +       struct intc_data *data;
 310 +       unsigned int i, w, status_offset;
 311 +
 312 +       data = kzalloc(sizeof(*data), GFP_KERNEL);
 313 +       if (!data)
 314 +               return -ENOMEM;
 315 +
 316 +       raw_spin_lock_init(&data->lock);
 317 +
 318 +       status_offset = num_words * sizeof(u32);
 319 +
 320 +       for (i = 0; i < num_blocks; i++) {
 321 +               struct intc_block *block = &data->block[i];
 322 +
 323 +               block->parent_irq = irq[i];
 324 +               block->base = base[i];
 325 +
 326 +               for (w = 0; w < num_words; w++) {
 327 +                       int word_offset = sizeof(u32) * ((num_words - w) - 1);
 328 +
 329 +                       block->en_reg[w] = base[i] + word_offset;
 330 +                       block->status_reg[w] = base[i] + status_offset;
 331 +                       block->status_reg[w] += word_offset;
 332 +
 333 +                       /* route all interrupts to line 0 by default */
 334 +                       if (i == 0)
 335 +                               block->mask_cache[w] = 0xffffffff;
 336 +               }
 337 +
 338 +               irq_set_handler_data(block->parent_irq, data);
 339 +               irq_set_chained_handler(block->parent_irq,
 340 +                                       bcm6345_periph_irq_handle);
 341 +       }
 342 +
 343 +       data->num_words = num_words;
 344 +
 345 +       data->chip.name = "bcm6345-periph-intc";
 346 +       data->chip.irq_mask = bcm6345_periph_irq_mask;
 347 +       data->chip.irq_unmask = bcm6345_periph_irq_unmask;
 348 +
 349 +#ifdef CONFIG_SMP
 350 +       if (num_blocks > 1)
 351 +               data->chip.irq_set_affinity = bcm6345_periph_set_affinity;
 352 +#endif
 353 +
 354 +       data->domain = irq_domain_add_simple(node, IRQS_PER_WORD * num_words,
 355 +                                            VIRQ_BASE,
 356 +                                            &bcm6345_periph_domain_ops, data);
 357 +       if (!data->domain) {
 358 +               kfree(data);
 359 +               return -EINVAL;
 360 +       }
 361 +
 362 +       return 0;
 363 +}
 364 +
 365 +void __init bcm6345_periph_intc_init(int num_blocks, int *irq,
 366 +                                    void __iomem **base, int num_words)
 367 +{
 368 +       __bcm6345_periph_intc_init(NULL, num_blocks, irq, base, num_words);
 369 +}
 370 +
 371 +#ifdef CONFIG_OF
 372 +static int __init bcm6345_periph_of_init(struct device_node *node,
 373 +                                        struct device_node *parent)
 374 +{
 375 +       struct resource res;
 376 +       int num_irqs, ret = -EINVAL;
 377 +       int irqs[MAX_PARENT_IRQS] = { 0 };
 378 +       void __iomem *bases[MAX_PARENT_IRQS] = { NULL };
 379 +       int words = 0;
 380 +       int i;
 381 +
 382 +       num_irqs = of_irq_count(node);
 383 +
 384 +       if (num_irqs < 1 || num_irqs > MAX_PARENT_IRQS)
 385 +               return -EINVAL;
 386 +
 387 +       for (i = 0; i < num_irqs; i++) {
 388 +               resource_size_t size;
 389 +
 390 +               irqs[i] = irq_of_parse_and_map(node, i);
 391 +               if (!irqs[i])
 392 +                       goto out_unmap;
 393 +
 394 +               if (of_address_to_resource(node, i, &res))
 395 +                       goto out_unmap;
 396 +
 397 +               size = resource_size(&res);
 398 +               switch (size) {
 399 +               case 8:
 400 +               case 16:
 401 +               case 32:
 402 +                       size = size / 8;
 403 +                       break;
 404 +               default:
 405 +                       goto out_unmap;
 406 +               }
 407 +
 408 +               if (words && words != size) {
 409 +                       ret = -EINVAL;
 410 +                       goto out_unmap;
 411 +               }
 412 +               words = size;
 413 +
 414 +               bases[i] = of_iomap(node, i);
 415 +               if (!bases[i]) {
 416 +                       ret = -ENOMEM;
 417 +                       goto out_unmap;
 418 +               }
 419 +       }
 420 +
 421 +       ret = __bcm6345_periph_intc_init(node, num_irqs, irqs, bases, words);
 422 +       if (!ret)
 423 +               return 0;
 424 +
 425 +out_unmap:
 426 +       for (i = 0; i < num_irqs; i++) {
 427 +               iounmap(bases[i]);
 428 +               irq_dispose_mapping(irqs[i]);
 429 +       }
 430 +
 431 +       return ret;
 432 +}
 433 +
 434 +IRQCHIP_DECLARE(bcm6345_periph_intc, "brcm,bcm6345-l1-intc",
 435 +               bcm6345_periph_of_init);
 436 +#endif
 437 --- /dev/null
 438 +++ b/include/linux/irqchip/irq-bcm6345-periph.h
 439 @@ -0,0 +1,16 @@
 440 +/*
 441 + * This file is subject to the terms and conditions of the GNU General Public
 442 + * License.  See the file "COPYING" in the main directory of this archive
 443 + * for more details.
 444 + *
 445 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
 446 + * Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr>
 447 + */
 448 +
 449 +#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H
 450 +#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H
 451 +
 452 +void bcm6345_periph_intc_init(int num_blocks, int *irq, void __iomem **base,
 453 +                             int num_words);
 454 +
 455 +#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H */