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cns3xxx: clean up patches
[openwrt/openwrt.git] / target / linux / cns3xxx / files / arch / arm / mach-cns3xxx / laguna.c
1 /*
2 * Gateworks Corporation Laguna Platform
3 *
4 * Copyright 2000 Deep Blue Solutions Ltd
5 * Copyright 2008 ARM Limited
6 * Copyright 2008 Cavium Networks
7 * Scott Shu
8 * Copyright 2010 MontaVista Software, LLC.
9 * Anton Vorontsov <avorontsov@mvista.com>
10 * Copyright 2011 Gateworks Corporation
11 * Chris Lang <clang@gateworks.com>
12 * Copyright 2012-2013 Gateworks Corporation
13 * Tim Harvey <tharvey@gateworks.com>
14 *
15 * This file is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License, Version 2, as
17 * published by the Free Software Foundation.
18 */
19
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/compiler.h>
23 #include <linux/io.h>
24 #include <linux/irq.h>
25 #include <linux/gpio.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/serial_core.h>
28 #include <linux/serial_8250.h>
29 #include <linux/platform_device.h>
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/physmap.h>
32 #include <linux/mtd/partitions.h>
33 #include <linux/leds.h>
34 #include <linux/i2c.h>
35 #include <linux/platform_data/at24.h>
36 #include <linux/platform_data/pca953x.h>
37 #include <linux/spi/spi.h>
38 #include <linux/spi/flash.h>
39 #include <linux/if_ether.h>
40 #include <linux/pps-gpio.h>
41 #include <linux/usb/ehci_pdriver.h>
42 #include <linux/usb/ohci_pdriver.h>
43 #include <linux/clk-provider.h>
44 #include <linux/clkdev.h>
45 #include <linux/platform_data/cns3xxx.h>
46 #include <asm/setup.h>
47 #include <asm/mach-types.h>
48 #include <asm/mach/arch.h>
49 #include <asm/mach/map.h>
50 #include <asm/mach/time.h>
51 #include <mach/gpio.h>
52 #include "core.h"
53 #include "devices.h"
54 #include "cns3xxx.h"
55 #include "pm.h"
56
57 #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
58
59 // Config 1 Bitmap
60 #define ETH0_LOAD BIT(0)
61 #define ETH1_LOAD BIT(1)
62 #define ETH2_LOAD BIT(2)
63 #define SATA0_LOAD BIT(3)
64 #define SATA1_LOAD BIT(4)
65 #define PCM_LOAD BIT(5)
66 #define I2S_LOAD BIT(6)
67 #define SPI0_LOAD BIT(7)
68 #define SPI1_LOAD BIT(8)
69 #define PCIE0_LOAD BIT(9)
70 #define PCIE1_LOAD BIT(10)
71 #define USB0_LOAD BIT(11)
72 #define USB1_LOAD BIT(12)
73 #define USB1_ROUTE BIT(13)
74 #define SD_LOAD BIT(14)
75 #define UART0_LOAD BIT(15)
76 #define UART1_LOAD BIT(16)
77 #define UART2_LOAD BIT(17)
78 #define MPCI0_LOAD BIT(18)
79 #define MPCI1_LOAD BIT(19)
80 #define MPCI2_LOAD BIT(20)
81 #define MPCI3_LOAD BIT(21)
82 #define FP_BUT_LOAD BIT(22)
83 #define FP_BUT_HEADER_LOAD BIT(23)
84 #define FP_LED_LOAD BIT(24)
85 #define FP_LED_HEADER_LOAD BIT(25)
86 #define FP_TAMPER_LOAD BIT(26)
87 #define HEADER_33V_LOAD BIT(27)
88 #define SATA_POWER_LOAD BIT(28)
89 #define FP_POWER_LOAD BIT(29)
90 #define GPIO_HEADER_LOAD BIT(30)
91 #define GSP_BAT_LOAD BIT(31)
92
93 // Config 2 Bitmap
94 #define FAN_LOAD BIT(0)
95 #define SPI_FLASH_LOAD BIT(1)
96 #define NOR_FLASH_LOAD BIT(2)
97 #define GPS_LOAD BIT(3)
98 #define SUPPLY_5V_LOAD BIT(6)
99 #define SUPPLY_33V_LOAD BIT(7)
100
101 struct laguna_board_info {
102 char model[16];
103 u32 config_bitmap;
104 u32 config2_bitmap;
105 u8 nor_flash_size;
106 u8 spi_flash_size;
107 };
108
109 static struct laguna_board_info laguna_info __initdata;
110
111 /*
112 * NOR Flash
113 */
114 static struct mtd_partition laguna_nor_partitions[] = {
115 {
116 .name = "uboot",
117 .size = SZ_256K,
118 .offset = 0,
119 .mask_flags = MTD_WRITEABLE,
120 }, {
121 .name = "params",
122 .size = SZ_128K,
123 .offset = SZ_256K,
124 }, {
125 .name = "firmware",
126 .offset = SZ_256K + SZ_128K,
127 },
128 };
129
130 static struct physmap_flash_data laguna_nor_pdata = {
131 .width = 2,
132 .parts = laguna_nor_partitions,
133 .nr_parts = ARRAY_SIZE(laguna_nor_partitions),
134 };
135
136 static struct resource laguna_nor_res = {
137 .start = CNS3XXX_FLASH_BASE,
138 .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
139 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
140 };
141
142 static struct platform_device laguna_nor_pdev = {
143 .name = "physmap-flash",
144 .id = 0,
145 .resource = &laguna_nor_res,
146 .num_resources = 1,
147 .dev = {
148 .platform_data = &laguna_nor_pdata,
149 },
150 };
151
152 /*
153 * SPI
154 */
155 static struct mtd_partition laguna_spi_partitions[] = {
156 {
157 .name = "uboot",
158 .size = SZ_256K,
159 .offset = 0,
160 .mask_flags = MTD_WRITEABLE,
161 }, {
162 .name = "params",
163 .size = SZ_256K,
164 .offset = SZ_256K,
165 }, {
166 .name = "firmware",
167 .offset = SZ_512K,
168 },
169 };
170
171 static struct flash_platform_data laguna_spi_pdata = {
172 .parts = laguna_spi_partitions,
173 .nr_parts = ARRAY_SIZE(laguna_spi_partitions),
174 };
175
176 static struct spi_board_info __initdata laguna_spi_devices[] = {
177 {
178 .modalias = "m25p80",
179 .platform_data = &laguna_spi_pdata,
180 .max_speed_hz = 50000000,
181 .bus_num = 1,
182 .chip_select = 0,
183 },
184 };
185
186 static struct resource laguna_spi_resource = {
187 .start = CNS3XXX_SSP_BASE + 0x40,
188 .end = CNS3XXX_SSP_BASE + 0x6f,
189 .flags = IORESOURCE_MEM,
190 };
191
192 static struct platform_device laguna_spi_controller = {
193 .name = "cns3xxx_spi",
194 .resource = &laguna_spi_resource,
195 .num_resources = 1,
196 };
197
198 /*
199 * LED's
200 */
201 static struct gpio_led laguna_gpio_leds[] = {
202 {
203 .name = "user1", /* Green Led */
204 .gpio = 115,
205 .active_low = 1,
206 },{
207 .name = "user2", /* Red Led */
208 .gpio = 114,
209 .active_low = 1,
210 },{
211 .name = "pwr1", /* Green Led */
212 .gpio = 116,
213 .active_low = 1,
214 },{
215 .name = "pwr2", /* Yellow Led */
216 .gpio = 117,
217 .active_low = 1,
218 },{
219 .name = "txd1", /* Green Led */
220 .gpio = 118,
221 .active_low = 1,
222 },{
223 .name = "txd2", /* Yellow Led */
224 .gpio = 119,
225 .active_low = 1,
226 },{
227 .name = "rxd1", /* Green Led */
228 .gpio = 120,
229 .active_low = 1,
230 },{
231 .name = "rxd2", /* Yellow Led */
232 .gpio = 121,
233 .active_low = 1,
234 },{
235 .name = "ser1", /* Green Led */
236 .gpio = 122,
237 .active_low = 1,
238 },{
239 .name = "ser2", /* Yellow Led */
240 .gpio = 123,
241 .active_low = 1,
242 },{
243 .name = "enet1", /* Green Led */
244 .gpio = 124,
245 .active_low = 1,
246 },{
247 .name = "enet2", /* Yellow Led */
248 .gpio = 125,
249 .active_low = 1,
250 },{
251 .name = "sig1_1", /* Green Led */
252 .gpio = 126,
253 .active_low = 1,
254 },{
255 .name = "sig1_2", /* Yellow Led */
256 .gpio = 127,
257 .active_low = 1,
258 },{
259 .name = "sig2_1", /* Green Led */
260 .gpio = 128,
261 .active_low = 1,
262 },{
263 .name = "sig2_2", /* Yellow Led */
264 .gpio = 129,
265 .active_low = 1,
266 },{
267 .name = "sig3_1", /* Green Led */
268 .gpio = 130,
269 .active_low = 1,
270 },{
271 .name = "sig3_2", /* Yellow Led */
272 .gpio = 131,
273 .active_low = 1,
274 },{
275 .name = "net1", /*Green Led */
276 .gpio = 109,
277 .active_low = 1,
278 },{
279 .name = "net2", /* Red Led */
280 .gpio = 110,
281 .active_low = 1,
282 },{
283 .name = "mod1", /* Green Led */
284 .gpio = 111,
285 .active_low = 1,
286 },{
287 .name = "mod2", /* Red Led */
288 .gpio = 112,
289 .active_low = 1,
290 },
291 };
292
293 static struct gpio_led_platform_data laguna_gpio_leds_data = {
294 .num_leds = 22,
295 .leds = laguna_gpio_leds,
296 };
297
298 static struct platform_device laguna_gpio_leds_device = {
299 .name = "leds-gpio",
300 .id = PLATFORM_DEVID_NONE,
301 .dev.platform_data = &laguna_gpio_leds_data,
302 };
303
304 /*
305 * Ethernet
306 */
307 static struct cns3xxx_plat_info laguna_net_data = {
308 .ports = 0,
309 .phy = {
310 0,
311 1,
312 2,
313 },
314 };
315
316 static struct resource laguna_net_resource[] = {
317 {
318 .name = "eth0_mem",
319 .start = CNS3XXX_SWITCH_BASE,
320 .end = CNS3XXX_SWITCH_BASE + SZ_4K - 1,
321 .flags = IORESOURCE_MEM
322 }, {
323 .name = "eth_rx",
324 .start = IRQ_CNS3XXX_SW_R0RXC,
325 .end = IRQ_CNS3XXX_SW_R0RXC,
326 .flags = IORESOURCE_IRQ
327 }, {
328 .name = "eth_stat",
329 .start = IRQ_CNS3XXX_SW_STATUS,
330 .end = IRQ_CNS3XXX_SW_STATUS,
331 .flags = IORESOURCE_IRQ
332 }
333 };
334
335 static u64 laguna_net_dmamask = DMA_BIT_MASK(32);
336 static struct platform_device laguna_net_device = {
337 .name = "cns3xxx_eth",
338 .id = 0,
339 .resource = laguna_net_resource,
340 .num_resources = ARRAY_SIZE(laguna_net_resource),
341 .dev = {
342 .dma_mask = &laguna_net_dmamask,
343 .coherent_dma_mask = DMA_BIT_MASK(32),
344 .platform_data = &laguna_net_data,
345 }
346 };
347
348 /*
349 * UART
350 */
351 static void __init laguna_early_serial_setup(void)
352 {
353 #ifdef CONFIG_SERIAL_8250_CONSOLE
354 static struct uart_port laguna_serial_port = {
355 .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
356 .mapbase = CNS3XXX_UART0_BASE,
357 .irq = IRQ_CNS3XXX_UART0,
358 .iotype = UPIO_MEM,
359 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
360 .regshift = 2,
361 .uartclk = 24000000,
362 .line = 0,
363 .type = PORT_16550A,
364 .fifosize = 16,
365 };
366
367 early_serial_setup(&laguna_serial_port);
368 #endif
369 }
370
371 static struct resource laguna_uart_resources[] = {
372 {
373 .start = CNS3XXX_UART0_BASE,
374 .end = CNS3XXX_UART0_BASE + SZ_4K - 1,
375 .flags = IORESOURCE_MEM
376 },{
377 .start = CNS3XXX_UART1_BASE,
378 .end = CNS3XXX_UART1_BASE + SZ_4K - 1,
379 .flags = IORESOURCE_MEM
380 },{
381 .start = CNS3XXX_UART2_BASE,
382 .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
383 .flags = IORESOURCE_MEM
384 },
385 };
386
387 static struct plat_serial8250_port laguna_uart_data[] = {
388 {
389 .mapbase = (CNS3XXX_UART0_BASE),
390 .irq = IRQ_CNS3XXX_UART0,
391 .iotype = UPIO_MEM,
392 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP,
393 .regshift = 2,
394 .uartclk = 24000000,
395 .type = PORT_16550A,
396 },{
397 .mapbase = (CNS3XXX_UART1_BASE),
398 .irq = IRQ_CNS3XXX_UART1,
399 .iotype = UPIO_MEM,
400 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP,
401 .regshift = 2,
402 .uartclk = 24000000,
403 .type = PORT_16550A,
404 },{
405 .mapbase = (CNS3XXX_UART2_BASE),
406 .irq = IRQ_CNS3XXX_UART2,
407 .iotype = UPIO_MEM,
408 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP,
409 .regshift = 2,
410 .uartclk = 24000000,
411 .type = PORT_16550A,
412 },
413 { },
414 };
415
416 static struct platform_device laguna_uart = {
417 .name = "serial8250",
418 .id = PLAT8250_DEV_PLATFORM,
419 .dev.platform_data = laguna_uart_data,
420 .num_resources = 3,
421 .resource = laguna_uart_resources
422 };
423
424 /*
425 * USB
426 */
427 static struct resource cns3xxx_usb_ehci_resources[] = {
428 [0] = {
429 .start = CNS3XXX_USB_BASE,
430 .end = CNS3XXX_USB_BASE + SZ_16M - 1,
431 .flags = IORESOURCE_MEM,
432 },
433 [1] = {
434 .start = IRQ_CNS3XXX_USB_EHCI,
435 .flags = IORESOURCE_IRQ,
436 },
437 };
438
439 static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
440
441 static int csn3xxx_usb_power_on(struct platform_device *pdev)
442 {
443 /*
444 * EHCI and OHCI share the same clock and power,
445 * resetting twice would cause the 1st controller been reset.
446 * Therefore only do power up at the first up device, and
447 * power down at the last down device.
448 *
449 * Set USB AHB INCR length to 16
450 */
451 if (atomic_inc_return(&usb_pwr_ref) == 1) {
452 cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
453 cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
454 cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
455 __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
456 MISC_CHIP_CONFIG_REG);
457 }
458
459 return 0;
460 }
461
462 static void csn3xxx_usb_power_off(struct platform_device *pdev)
463 {
464 /*
465 * EHCI and OHCI share the same clock and power,
466 * resetting twice would cause the 1st controller been reset.
467 * Therefore only do power up at the first up device, and
468 * power down at the last down device.
469 */
470 if (atomic_dec_return(&usb_pwr_ref) == 0)
471 cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
472 }
473
474 static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
475 .power_on = csn3xxx_usb_power_on,
476 .power_off = csn3xxx_usb_power_off,
477 };
478
479 static struct platform_device cns3xxx_usb_ehci_device = {
480 .name = "ehci-platform",
481 .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
482 .resource = cns3xxx_usb_ehci_resources,
483 .dev = {
484 .dma_mask = &cns3xxx_usb_ehci_dma_mask,
485 .coherent_dma_mask = DMA_BIT_MASK(32),
486 .platform_data = &cns3xxx_usb_ehci_pdata,
487 },
488 };
489
490 static struct resource cns3xxx_usb_ohci_resources[] = {
491 [0] = {
492 .start = CNS3XXX_USB_OHCI_BASE,
493 .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
494 .flags = IORESOURCE_MEM,
495 },
496 [1] = {
497 .start = IRQ_CNS3XXX_USB_OHCI,
498 .flags = IORESOURCE_IRQ,
499 },
500 };
501
502 static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
503
504 static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
505 .num_ports = 1,
506 .power_on = csn3xxx_usb_power_on,
507 .power_off = csn3xxx_usb_power_off,
508 };
509
510 static struct platform_device cns3xxx_usb_ohci_device = {
511 .name = "ohci-platform",
512 .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
513 .resource = cns3xxx_usb_ohci_resources,
514 .dev = {
515 .dma_mask = &cns3xxx_usb_ohci_dma_mask,
516 .coherent_dma_mask = DMA_BIT_MASK(32),
517 .platform_data = &cns3xxx_usb_ohci_pdata,
518 },
519 };
520
521 static struct resource cns3xxx_usb_otg_resources[] = {
522 [0] = {
523 .start = CNS3XXX_USBOTG_BASE,
524 .end = CNS3XXX_USBOTG_BASE + SZ_16M - 1,
525 .flags = IORESOURCE_MEM,
526 },
527 [1] = {
528 .start = IRQ_CNS3XXX_USB_OTG,
529 .flags = IORESOURCE_IRQ,
530 },
531 };
532
533 static u64 cns3xxx_usb_otg_dma_mask = DMA_BIT_MASK(32);
534
535 static struct platform_device cns3xxx_usb_otg_device = {
536 .name = "dwc2",
537 .num_resources = ARRAY_SIZE(cns3xxx_usb_otg_resources),
538 .resource = cns3xxx_usb_otg_resources,
539 .dev = {
540 .dma_mask = &cns3xxx_usb_otg_dma_mask,
541 .coherent_dma_mask = DMA_BIT_MASK(32),
542 },
543 };
544
545 /*
546 * I2C
547 */
548 static struct resource laguna_i2c_resource[] = {
549 {
550 .start = CNS3XXX_SSP_BASE + 0x20,
551 .end = CNS3XXX_SSP_BASE + 0x3f,
552 .flags = IORESOURCE_MEM,
553 },{
554 .start = IRQ_CNS3XXX_I2C,
555 .flags = IORESOURCE_IRQ,
556 },
557 };
558
559 static struct platform_device laguna_i2c_controller = {
560 .name = "cns3xxx-i2c",
561 .num_resources = 2,
562 .resource = laguna_i2c_resource,
563 };
564
565 static struct nvmem_device *at24_nvmem;
566
567 static void at24_setup(struct nvmem_device *mem_acc, void *context)
568 {
569 char buf[16];
570
571 at24_nvmem = mem_acc;
572
573 /* Read MAC addresses */
574 if (nvmem_device_read(at24_nvmem, 0x100, 6, buf) == 6)
575 memcpy(&laguna_net_data.hwaddr[0], buf, ETH_ALEN);
576 if (nvmem_device_read(at24_nvmem, 0x106, 6, buf) == 6)
577 memcpy(&laguna_net_data.hwaddr[1], buf, ETH_ALEN);
578 if (nvmem_device_read(at24_nvmem, 0x10C, 6, buf) == 6)
579 memcpy(&laguna_net_data.hwaddr[2], buf, ETH_ALEN);
580 if (nvmem_device_read(at24_nvmem, 0x112, 6, buf) == 6)
581 memcpy(&laguna_net_data.hwaddr[3], buf, ETH_ALEN);
582
583 /* Read out Model Information */
584 if (nvmem_device_read(at24_nvmem, 0x130, 16, buf) == 16)
585 memcpy(&laguna_info.model, buf, 16);
586 if (nvmem_device_read(at24_nvmem, 0x140, 1, buf) == 1)
587 memcpy(&laguna_info.nor_flash_size, buf, 1);
588 if (nvmem_device_read(at24_nvmem, 0x141, 1, buf) == 1)
589 memcpy(&laguna_info.spi_flash_size, buf, 1);
590 if (nvmem_device_read(at24_nvmem, 0x142, 4, buf) == 4)
591 memcpy(&laguna_info.config_bitmap, buf, 4);
592 if (nvmem_device_read(at24_nvmem, 0x146, 4, buf) == 4)
593 memcpy(&laguna_info.config2_bitmap, buf, 4);
594 };
595
596 static struct at24_platform_data laguna_eeprom_info = {
597 .byte_len = 1024,
598 .page_size = 16,
599 .flags = AT24_FLAG_READONLY,
600 .setup = at24_setup,
601 };
602
603 static struct pca953x_platform_data laguna_pca_data = {
604 .gpio_base = 100,
605 .irq_base = -1,
606 };
607
608 static struct pca953x_platform_data laguna_pca2_data = {
609 .gpio_base = 116,
610 .irq_base = -1,
611 };
612
613 static struct i2c_board_info __initdata laguna_i2c_devices[] = {
614 {
615 I2C_BOARD_INFO("pca9555", 0x23),
616 .platform_data = &laguna_pca_data,
617 },{
618 I2C_BOARD_INFO("pca9555", 0x27),
619 .platform_data = &laguna_pca2_data,
620 },{
621 I2C_BOARD_INFO("gsp", 0x29),
622 },{
623 I2C_BOARD_INFO ("24c08",0x50),
624 .platform_data = &laguna_eeprom_info,
625 },{
626 I2C_BOARD_INFO("ds1672", 0x68),
627 },
628 };
629
630 /*
631 * Watchdog
632 */
633
634 static struct resource laguna_watchdog_resources[] = {
635 [0] = {
636 .start = CNS3XXX_TC11MP_TWD_BASE + 0x100, // CPU0 watchdog
637 .end = CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1,
638 .flags = IORESOURCE_MEM,
639 },
640 };
641
642 static struct platform_device laguna_watchdog = {
643 .name = "mpcore_wdt",
644 .id = PLATFORM_DEVID_NONE,
645 .num_resources = ARRAY_SIZE(laguna_watchdog_resources),
646 .resource = laguna_watchdog_resources,
647 };
648
649 /*
650 * GPS PPS
651 */
652 static struct pps_gpio_platform_data laguna_pps_data = {
653 .gpio_pin = 0,
654 .gpio_label = "GPS_PPS",
655 .assert_falling_edge = 0,
656 .capture_clear = 0,
657 };
658
659 static struct platform_device laguna_pps_device = {
660 .name = "pps-gpio",
661 .id = PLATFORM_DEVID_NONE,
662 .dev.platform_data = &laguna_pps_data,
663 };
664
665 /*
666 * GPIO
667 */
668
669 static struct gpio laguna_gpio_gw2391[] = {
670 { 0, GPIOF_IN , "*GPS_PPS" },
671 { 1, GPIOF_IN , "*GSC_IRQ#" },
672 { 2, GPIOF_IN , "*USB_FAULT#" },
673 { 5, GPIOF_OUT_INIT_LOW , "*USB0_PCI_SEL" },
674 { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
675 { 7, GPIOF_OUT_INIT_LOW , "*USB1_PCI_SEL" },
676 { 8, GPIOF_OUT_INIT_HIGH, "*PERST#" },
677 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN#" },
678 { 100, GPIOF_IN , "*USER_PB#" },
679 { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
680 { 108, GPIOF_IN , "DIO0" },
681 { 109, GPIOF_IN , "DIO1" },
682 { 110, GPIOF_IN , "DIO2" },
683 { 111, GPIOF_IN , "DIO3" },
684 { 112, GPIOF_IN , "DIO4" },
685 };
686
687 static struct gpio laguna_gpio_gw2388[] = {
688 { 0, GPIOF_IN , "*GPS_PPS" },
689 { 1, GPIOF_IN , "*GSC_IRQ#" },
690 { 3, GPIOF_IN , "*USB_FAULT#" },
691 { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
692 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
693 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
694 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
695 { 100, GPIOF_OUT_INIT_HIGH, "*USER_PB#" },
696 { 108, GPIOF_IN , "DIO0" },
697 { 109, GPIOF_IN , "DIO1" },
698 { 110, GPIOF_IN , "DIO2" },
699 { 111, GPIOF_IN , "DIO3" },
700 { 112, GPIOF_IN , "DIO4" },
701 };
702
703 static struct gpio laguna_gpio_gw2387[] = {
704 { 0, GPIOF_IN , "*GPS_PPS" },
705 { 1, GPIOF_IN , "*GSC_IRQ#" },
706 { 2, GPIOF_IN , "*USB_FAULT#" },
707 { 5, GPIOF_OUT_INIT_LOW , "*USB_PCI_SEL" },
708 { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
709 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
710 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
711 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
712 { 100, GPIOF_IN , "*USER_PB#" },
713 { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
714 { 108, GPIOF_IN , "DIO0" },
715 { 109, GPIOF_IN , "DIO1" },
716 { 110, GPIOF_IN , "DIO2" },
717 { 111, GPIOF_IN , "DIO3" },
718 { 112, GPIOF_IN , "DIO4" },
719 { 113, GPIOF_IN , "DIO5" },
720 };
721
722 static struct gpio laguna_gpio_gw2386[] = {
723 { 0, GPIOF_IN , "*GPS_PPS" },
724 { 2, GPIOF_IN , "*USB_FAULT#" },
725 { 6, GPIOF_OUT_INIT_LOW , "*USB_PCI_SEL" },
726 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
727 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
728 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
729 { 108, GPIOF_IN , "DIO0" },
730 { 109, GPIOF_IN , "DIO1" },
731 { 110, GPIOF_IN , "DIO2" },
732 { 111, GPIOF_IN , "DIO3" },
733 { 112, GPIOF_IN , "DIO4" },
734 { 113, GPIOF_IN , "DIO5" },
735 };
736
737 static struct gpio laguna_gpio_gw2385[] = {
738 { 0, GPIOF_IN , "*GSC_IRQ#" },
739 { 1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" },
740 { 2, GPIOF_IN , "*USB_HST_FAULT#" },
741 { 5, GPIOF_IN , "*USB_OTG_FAULT#" },
742 { 6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" },
743 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
744 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
745 { 9, GPIOF_OUT_INIT_LOW , "*SER_EN" },
746 { 10, GPIOF_IN, "*USER_PB#" },
747 { 11, GPIOF_OUT_INIT_HIGH, "*PERST#" },
748 { 100, GPIOF_IN , "*USER_PB#" },
749 { 103, GPIOF_OUT_INIT_HIGH, "V5_EN" },
750 };
751
752 static struct gpio laguna_gpio_gw2384[] = {
753 { 0, GPIOF_IN , "*GSC_IRQ#" },
754 { 1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" },
755 { 2, GPIOF_IN , "*USB_HST_FAULT#" },
756 { 5, GPIOF_IN , "*USB_OTG_FAULT#" },
757 { 6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" },
758 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
759 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
760 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
761 { 12, GPIOF_OUT_INIT_LOW , "J10_DIOLED0" },
762 { 13, GPIOF_OUT_INIT_HIGH, "*I2CMUX_RST#" },
763 { 14, GPIOF_OUT_INIT_LOW , "J10_DIOLED1" },
764 { 15, GPIOF_OUT_INIT_LOW , "J10_DIOLED2" },
765 { 100, GPIOF_IN , "*USER_PB#" },
766 { 103, GPIOF_OUT_INIT_HIGH, "V5_EN" },
767 { 108, GPIOF_IN , "J9_DIOGSC0" },
768 };
769
770 static struct gpio laguna_gpio_gw2383[] = {
771 { 0, GPIOF_IN , "*GPS_PPS" },
772 { 1, GPIOF_IN , "*GSC_IRQ#" },
773 { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
774 { 3, GPIOF_IN , "GPIO0" },
775 { 8, GPIOF_IN , "GPIO1" },
776 { 100, GPIOF_IN , "DIO0" },
777 { 101, GPIOF_IN , "DIO1" },
778 { 108, GPIOF_IN , "*USER_PB#" },
779 };
780
781 static struct gpio laguna_gpio_gw2382[] = {
782 { 0, GPIOF_IN , "*GPS_PPS" },
783 { 1, GPIOF_IN , "*GSC_IRQ#" },
784 { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
785 { 3, GPIOF_IN , "GPIO0" },
786 { 4, GPIOF_IN , "GPIO1" },
787 { 9, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
788 { 10, GPIOF_OUT_INIT_HIGH, "*USB_PCI_SEL#" },
789 { 100, GPIOF_IN , "DIO0" },
790 { 101, GPIOF_IN , "DIO1" },
791 { 108, GPIOF_IN , "*USER_PB#" },
792 };
793
794 static struct gpio laguna_gpio_gw2380[] = {
795 { 0, GPIOF_IN , "*GPS_PPS" },
796 { 1, GPIOF_IN , "*GSC_IRQ#" },
797 { 3, GPIOF_IN , "GPIO0" },
798 { 8, GPIOF_IN , "GPIO1" },
799 { 100, GPIOF_IN , "DIO0" },
800 { 101, GPIOF_IN , "DIO1" },
801 { 102, GPIOF_IN , "DIO2" },
802 { 103, GPIOF_IN , "DIO3" },
803 { 108, GPIOF_IN , "*USER_PB#" },
804 };
805
806 /*
807 * Initialization
808 */
809 static void __init laguna_init(void)
810 {
811 struct clk *clk;
812 u32 __iomem *reg;
813
814 clk = clk_register_fixed_rate(NULL, "cpu", NULL,
815 CLK_IGNORE_UNUSED,
816 cns3xxx_cpu_clock() * (1000000 / 8));
817 clk_register_clkdev(clk, "cpu", NULL);
818
819 platform_device_register(&laguna_watchdog);
820
821 platform_device_register(&laguna_i2c_controller);
822
823 /* Set I2C 0-3 drive strength to 21 mA */
824 reg = MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B;
825 *reg |= 0x300;
826
827 /* Enable SCL/SDA for I2C */
828 reg = MISC_GPIOB_PIN_ENABLE_REG;
829 *reg |= BIT(12) | BIT(13);
830
831 /* Enable MMC/SD pins */
832 *reg |= BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11);
833
834 cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
835 cns3xxx_pwr_power_up(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
836 cns3xxx_pwr_soft_rst(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
837
838 cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SPI_PCM_I2C));
839 cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SPI_PCM_I2C));
840
841 i2c_register_board_info(0, ARRAY_AND_SIZE(laguna_i2c_devices));
842
843 pm_power_off = cns3xxx_power_off;
844 }
845
846 static struct map_desc laguna_io_desc[] __initdata = {
847 {
848 .virtual = CNS3XXX_UART0_BASE_VIRT,
849 .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
850 .length = SZ_4K,
851 .type = MT_DEVICE,
852 },
853 };
854
855 static void __init laguna_map_io(void)
856 {
857 cns3xxx_map_io();
858 iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
859 laguna_early_serial_setup();
860 }
861
862 static int laguna_register_gpio(struct gpio *array, size_t num)
863 {
864 int i, err, ret;
865
866 ret = 0;
867 for (i = 0; i < num; i++, array++) {
868 const char *label = array->label;
869 if (label[0] == '*')
870 label++;
871 err = gpio_request_one(array->gpio, array->flags, label);
872 if (err)
873 ret = err;
874 else {
875 err = gpio_export(array->gpio, array->label[0] != '*');
876 }
877 }
878 return ret;
879 }
880
881 /* allow disabling of external isolated PCIe IRQs */
882 static int cns3xxx_pciextirq = 1;
883 static int __init cns3xxx_pciextirq_disable(char *s)
884 {
885 cns3xxx_pciextirq = 0;
886 return 1;
887 }
888 __setup("noextirq", cns3xxx_pciextirq_disable);
889
890 static int __init laguna_pcie_init_irq(void)
891 {
892 u32 __iomem *mem = (void __iomem *)(CNS3XXX_GPIOB_BASE_VIRT + 0x0004);
893 u32 reg = (__raw_readl(mem) >> 26) & 0xf;
894 int irqs[] = {
895 IRQ_CNS3XXX_EXTERNAL_PIN0,
896 IRQ_CNS3XXX_EXTERNAL_PIN1,
897 IRQ_CNS3XXX_EXTERNAL_PIN2,
898 154,
899 };
900
901 if (!machine_is_gw2388())
902 return 0;
903
904 /* Verify GPIOB[26:29] == 0001b indicating support for ext irqs */
905 if (cns3xxx_pciextirq && reg != 1)
906 cns3xxx_pciextirq = 0;
907
908 if (cns3xxx_pciextirq) {
909 printk("laguna: using isolated PCI interrupts:"
910 " irq%d/irq%d/irq%d/irq%d\n",
911 irqs[0], irqs[1], irqs[2], irqs[3]);
912 cns3xxx_pcie_set_irqs(0, irqs);
913 } else {
914 printk("laguna: using shared PCI interrupts: irq%d\n",
915 IRQ_CNS3XXX_PCIE0_DEVICE);
916 }
917
918 return 0;
919 }
920 subsys_initcall(laguna_pcie_init_irq);
921
922 static int __init laguna_model_setup(void)
923 {
924 u32 __iomem *mem;
925 u32 reg;
926
927 if (!machine_is_gw2388())
928 return 0;
929
930 printk("Running on Gateworks Laguna %s\n", laguna_info.model);
931 cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
932 NR_IRQS_CNS3XXX);
933
934 /*
935 * If pcie external interrupts are supported and desired
936 * configure IRQ types and configure pin function.
937 * Note that cns3xxx_pciextirq is enabled by default, but can be
938 * unset via the 'noextirq' kernel param or by laguna_pcie_init() if
939 * the baseboard model does not support this hardware feature.
940 */
941 if (cns3xxx_pciextirq) {
942 mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0018);
943 reg = __raw_readl(mem);
944 /* GPIO26 is gpio, EXT_INT[0:2] not gpio func */
945 reg &= ~0x3c000000;
946 reg |= 0x38000000;
947 __raw_writel(reg, mem);
948
949 cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
950 IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
951
952 irq_set_irq_type(154, IRQ_TYPE_LEVEL_LOW);
953 irq_set_irq_type(93, IRQ_TYPE_LEVEL_HIGH);
954 irq_set_irq_type(94, IRQ_TYPE_LEVEL_HIGH);
955 irq_set_irq_type(95, IRQ_TYPE_LEVEL_HIGH);
956 } else {
957 cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
958 IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
959 }
960
961 if (strncmp(laguna_info.model, "GW", 2) == 0) {
962 if (laguna_info.config_bitmap & ETH0_LOAD)
963 laguna_net_data.ports |= BIT(0);
964 if (laguna_info.config_bitmap & ETH1_LOAD)
965 laguna_net_data.ports |= BIT(1);
966 if (laguna_info.config_bitmap & ETH2_LOAD)
967 laguna_net_data.ports |= BIT(2);
968 if (laguna_net_data.ports)
969 platform_device_register(&laguna_net_device);
970
971 if ((laguna_info.config_bitmap & SATA0_LOAD) ||
972 (laguna_info.config_bitmap & SATA1_LOAD))
973 cns3xxx_ahci_init();
974
975 if (laguna_info.config_bitmap & (USB0_LOAD)) {
976 cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
977
978 /* DRVVBUS pins share with GPIOA */
979 mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0014);
980 reg = __raw_readl(mem);
981 reg |= 0x8;
982 __raw_writel(reg, mem);
983
984 /* Enable OTG */
985 mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0808);
986 reg = __raw_readl(mem);
987 reg &= ~(1 << 10);
988 __raw_writel(reg, mem);
989
990 platform_device_register(&cns3xxx_usb_otg_device);
991 }
992
993 if (laguna_info.config_bitmap & (USB1_LOAD)) {
994 platform_device_register(&cns3xxx_usb_ehci_device);
995 platform_device_register(&cns3xxx_usb_ohci_device);
996 }
997
998 if (laguna_info.config_bitmap & (SD_LOAD))
999 cns3xxx_sdhci_init();
1000
1001 if (laguna_info.config_bitmap & (UART0_LOAD))
1002 laguna_uart.num_resources = 1;
1003 if (laguna_info.config_bitmap & (UART1_LOAD))
1004 laguna_uart.num_resources = 2;
1005 if (laguna_info.config_bitmap & (UART2_LOAD))
1006 laguna_uart.num_resources = 3;
1007 platform_device_register(&laguna_uart);
1008
1009 if (laguna_info.config2_bitmap & (NOR_FLASH_LOAD)) {
1010 laguna_nor_partitions[2].size =
1011 (SZ_4M << laguna_info.nor_flash_size) -
1012 laguna_nor_partitions[2].offset;
1013 laguna_nor_res.end = CNS3XXX_FLASH_BASE +
1014 laguna_nor_partitions[2].offset +
1015 laguna_nor_partitions[2].size - 1;
1016 platform_device_register(&laguna_nor_pdev);
1017 }
1018
1019 if (laguna_info.config2_bitmap & (SPI_FLASH_LOAD)) {
1020 laguna_spi_partitions[2].size =
1021 (SZ_2M << laguna_info.spi_flash_size) -
1022 laguna_spi_partitions[2].offset;
1023 spi_register_board_info(ARRAY_AND_SIZE(laguna_spi_devices));
1024 }
1025
1026 if ((laguna_info.config_bitmap & SPI0_LOAD) ||
1027 (laguna_info.config_bitmap & SPI1_LOAD))
1028 platform_device_register(&laguna_spi_controller);
1029
1030 if (laguna_info.config2_bitmap & GPS_LOAD)
1031 platform_device_register(&laguna_pps_device);
1032
1033 /*
1034 * Do any model specific setup not known by the bitmap by matching
1035 * the first 6 characters of the model name
1036 */
1037
1038 if ( (strncmp(laguna_info.model, "GW2388", 6) == 0)
1039 || (strncmp(laguna_info.model, "GW2389", 6) == 0) )
1040 {
1041 // configure GPIO's
1042 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2388));
1043 // configure LED's
1044 laguna_gpio_leds_data.num_leds = 2;
1045 } else if (strncmp(laguna_info.model, "GW2387", 6) == 0) {
1046 // configure GPIO's
1047 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2387));
1048 // configure LED's
1049 laguna_gpio_leds_data.num_leds = 2;
1050 } else if (strncmp(laguna_info.model, "GW2386", 6) == 0) {
1051 // configure GPIO's
1052 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2386));
1053 // configure LED's
1054 laguna_gpio_leds_data.num_leds = 2;
1055 } else if (strncmp(laguna_info.model, "GW2385", 6) == 0) {
1056 // configure GPIO's
1057 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2385));
1058 // configure LED's
1059 laguna_gpio_leds[0].gpio = 115;
1060 laguna_gpio_leds[1].gpio = 12;
1061 laguna_gpio_leds[1].name = "red";
1062 laguna_gpio_leds[1].active_low = 0,
1063 laguna_gpio_leds[2].gpio = 14;
1064 laguna_gpio_leds[2].name = "green";
1065 laguna_gpio_leds[2].active_low = 0,
1066 laguna_gpio_leds[3].gpio = 15;
1067 laguna_gpio_leds[3].name = "blue";
1068 laguna_gpio_leds[3].active_low = 0,
1069 laguna_gpio_leds_data.num_leds = 4;
1070 } else if ( (strncmp(laguna_info.model, "GW2384", 6) == 0)
1071 || (strncmp(laguna_info.model, "GW2394", 6) == 0) )
1072 {
1073 // configure GPIO's
1074 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2384));
1075 // configure LED's
1076 laguna_gpio_leds_data.num_leds = 1;
1077 } else if (strncmp(laguna_info.model, "GW2383", 6) == 0) {
1078 // configure GPIO's
1079 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2383));
1080 // configure LED's
1081 laguna_gpio_leds[0].gpio = 107;
1082 laguna_gpio_leds_data.num_leds = 1;
1083 } else if (strncmp(laguna_info.model, "GW2382", 6) == 0) {
1084 // configure GPIO's
1085 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2382));
1086 // configure LED's
1087 laguna_gpio_leds[0].gpio = 107;
1088 laguna_gpio_leds_data.num_leds = 1;
1089 } else if (strncmp(laguna_info.model, "GW2380", 6) == 0) {
1090 // configure GPIO's
1091 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2380));
1092 // configure LED's
1093 laguna_gpio_leds[0].gpio = 107;
1094 laguna_gpio_leds[1].gpio = 106;
1095 laguna_gpio_leds_data.num_leds = 2;
1096 } else if ( (strncmp(laguna_info.model, "GW2391", 6) == 0)
1097 || (strncmp(laguna_info.model, "GW2393", 6) == 0) )
1098 {
1099 // configure GPIO's
1100 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2391));
1101 // configure LED's
1102 laguna_gpio_leds_data.num_leds = 2;
1103 }
1104 platform_device_register(&laguna_gpio_leds_device);
1105 } else {
1106 // Do some defaults here, not sure what yet
1107 }
1108 return 0;
1109 }
1110 late_initcall(laguna_model_setup);
1111
1112 MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
1113 .smp = smp_ops(cns3xxx_smp_ops),
1114 .atag_offset = 0x100,
1115 .map_io = laguna_map_io,
1116 .init_irq = cns3xxx_init_irq,
1117 .init_time = cns3xxx_timer_init,
1118 .init_machine = laguna_init,
1119 .init_late = cns3xxx_pcie_init_late,
1120 .restart = cns3xxx_restart,
1121 MACHINE_END
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