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cns3xxx: add missing dma mask for ethernet device
[openwrt/openwrt.git] / target / linux / cns3xxx / files / arch / arm / mach-cns3xxx / laguna.c
1 /*
2 * Gateworks Corporation Laguna Platform
3 *
4 * Copyright 2000 Deep Blue Solutions Ltd
5 * Copyright 2008 ARM Limited
6 * Copyright 2008 Cavium Networks
7 * Scott Shu
8 * Copyright 2010 MontaVista Software, LLC.
9 * Anton Vorontsov <avorontsov@mvista.com>
10 * Copyright 2011 Gateworks Corporation
11 * Chris Lang <clang@gateworks.com>
12 * Copyright 2012-2013 Gateworks Corporation
13 * Tim Harvey <tharvey@gateworks.com>
14 *
15 * This file is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License, Version 2, as
17 * published by the Free Software Foundation.
18 */
19
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/compiler.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/serial_core.h>
27 #include <linux/serial_8250.h>
28 #include <linux/platform_device.h>
29 #include <linux/mtd/mtd.h>
30 #include <linux/mtd/physmap.h>
31 #include <linux/mtd/partitions.h>
32 #include <linux/leds.h>
33 #include <linux/i2c.h>
34 #include <linux/platform_data/at24.h>
35 #include <linux/platform_data/pca953x.h>
36 #include <linux/spi/spi.h>
37 #include <linux/spi/flash.h>
38 #include <linux/if_ether.h>
39 #include <linux/pps-gpio.h>
40 #include <linux/usb/ehci_pdriver.h>
41 #include <linux/usb/ohci_pdriver.h>
42 #include <linux/clk-provider.h>
43 #include <linux/clkdev.h>
44 #include <linux/platform_data/cns3xxx.h>
45 #include <asm/setup.h>
46 #include <asm/mach-types.h>
47 #include <asm/mach/arch.h>
48 #include <asm/mach/map.h>
49 #include <asm/mach/time.h>
50 #include <mach/gpio.h>
51 #include "core.h"
52 #include "devices.h"
53 #include "cns3xxx.h"
54 #include "pm.h"
55
56 #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
57
58 // Config 1 Bitmap
59 #define ETH0_LOAD BIT(0)
60 #define ETH1_LOAD BIT(1)
61 #define ETH2_LOAD BIT(2)
62 #define SATA0_LOAD BIT(3)
63 #define SATA1_LOAD BIT(4)
64 #define PCM_LOAD BIT(5)
65 #define I2S_LOAD BIT(6)
66 #define SPI0_LOAD BIT(7)
67 #define SPI1_LOAD BIT(8)
68 #define PCIE0_LOAD BIT(9)
69 #define PCIE1_LOAD BIT(10)
70 #define USB0_LOAD BIT(11)
71 #define USB1_LOAD BIT(12)
72 #define USB1_ROUTE BIT(13)
73 #define SD_LOAD BIT(14)
74 #define UART0_LOAD BIT(15)
75 #define UART1_LOAD BIT(16)
76 #define UART2_LOAD BIT(17)
77 #define MPCI0_LOAD BIT(18)
78 #define MPCI1_LOAD BIT(19)
79 #define MPCI2_LOAD BIT(20)
80 #define MPCI3_LOAD BIT(21)
81 #define FP_BUT_LOAD BIT(22)
82 #define FP_BUT_HEADER_LOAD BIT(23)
83 #define FP_LED_LOAD BIT(24)
84 #define FP_LED_HEADER_LOAD BIT(25)
85 #define FP_TAMPER_LOAD BIT(26)
86 #define HEADER_33V_LOAD BIT(27)
87 #define SATA_POWER_LOAD BIT(28)
88 #define FP_POWER_LOAD BIT(29)
89 #define GPIO_HEADER_LOAD BIT(30)
90 #define GSP_BAT_LOAD BIT(31)
91
92 // Config 2 Bitmap
93 #define FAN_LOAD BIT(0)
94 #define SPI_FLASH_LOAD BIT(1)
95 #define NOR_FLASH_LOAD BIT(2)
96 #define GPS_LOAD BIT(3)
97 #define SUPPLY_5V_LOAD BIT(6)
98 #define SUPPLY_33V_LOAD BIT(7)
99
100 struct laguna_board_info {
101 char model[16];
102 u32 config_bitmap;
103 u32 config2_bitmap;
104 u8 nor_flash_size;
105 u8 spi_flash_size;
106 };
107
108 static struct laguna_board_info laguna_info __initdata;
109
110 /*
111 * NOR Flash
112 */
113 static struct mtd_partition laguna_nor_partitions[] = {
114 {
115 .name = "uboot",
116 .size = SZ_256K,
117 .offset = 0,
118 .mask_flags = MTD_WRITEABLE,
119 }, {
120 .name = "params",
121 .size = SZ_128K,
122 .offset = SZ_256K,
123 }, {
124 .name = "kernel",
125 .size = SZ_2M,
126 .offset = SZ_256K + SZ_128K,
127 }, {
128 .name = "rootfs",
129 .size = SZ_16M - SZ_256K - SZ_128K - SZ_2M,
130 .offset = SZ_256K + SZ_128K + SZ_2M,
131 },
132 };
133
134 static struct physmap_flash_data laguna_nor_pdata = {
135 .width = 2,
136 .parts = laguna_nor_partitions,
137 .nr_parts = ARRAY_SIZE(laguna_nor_partitions),
138 };
139
140 static struct resource laguna_nor_res = {
141 .start = CNS3XXX_FLASH_BASE,
142 .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
143 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
144 };
145
146 static struct platform_device laguna_nor_pdev = {
147 .name = "physmap-flash",
148 .id = 0,
149 .resource = &laguna_nor_res,
150 .num_resources = 1,
151 .dev = {
152 .platform_data = &laguna_nor_pdata,
153 },
154 };
155
156 /*
157 * SPI
158 */
159 static struct mtd_partition laguna_spi_partitions[] = {
160 {
161 .name = "uboot",
162 .size = SZ_256K,
163 .offset = 0,
164 .mask_flags = MTD_WRITEABLE,
165 }, {
166 .name = "params",
167 .size = SZ_256K,
168 .offset = SZ_256K,
169 }, {
170 .name = "kernel",
171 .size = SZ_1M + SZ_512K,
172 .offset = SZ_512K,
173 }, {
174 .name = "rootfs",
175 .size = SZ_16M - SZ_2M,
176 .offset = SZ_2M,
177 },
178 };
179
180 static struct flash_platform_data laguna_spi_pdata = {
181 .parts = laguna_spi_partitions,
182 .nr_parts = ARRAY_SIZE(laguna_spi_partitions),
183 };
184
185 static struct spi_board_info __initdata laguna_spi_devices[] = {
186 {
187 .modalias = "m25p80",
188 .platform_data = &laguna_spi_pdata,
189 .max_speed_hz = 50000000,
190 .bus_num = 1,
191 .chip_select = 0,
192 },
193 };
194
195 static struct resource laguna_spi_resource = {
196 .start = CNS3XXX_SSP_BASE + 0x40,
197 .end = CNS3XXX_SSP_BASE + 0x6f,
198 .flags = IORESOURCE_MEM,
199 };
200
201 static struct platform_device laguna_spi_controller = {
202 .name = "cns3xxx_spi",
203 .resource = &laguna_spi_resource,
204 .num_resources = 1,
205 };
206
207 /*
208 * LED's
209 */
210 static struct gpio_led laguna_gpio_leds[] = {
211 {
212 .name = "user1", /* Green Led */
213 .gpio = 115,
214 .active_low = 1,
215 },{
216 .name = "user2", /* Red Led */
217 .gpio = 114,
218 .active_low = 1,
219 },{
220 .name = "pwr1", /* Green Led */
221 .gpio = 116,
222 .active_low = 1,
223 },{
224 .name = "pwr2", /* Yellow Led */
225 .gpio = 117,
226 .active_low = 1,
227 },{
228 .name = "txd1", /* Green Led */
229 .gpio = 118,
230 .active_low = 1,
231 },{
232 .name = "txd2", /* Yellow Led */
233 .gpio = 119,
234 .active_low = 1,
235 },{
236 .name = "rxd1", /* Green Led */
237 .gpio = 120,
238 .active_low = 1,
239 },{
240 .name = "rxd2", /* Yellow Led */
241 .gpio = 121,
242 .active_low = 1,
243 },{
244 .name = "ser1", /* Green Led */
245 .gpio = 122,
246 .active_low = 1,
247 },{
248 .name = "ser2", /* Yellow Led */
249 .gpio = 123,
250 .active_low = 1,
251 },{
252 .name = "enet1", /* Green Led */
253 .gpio = 124,
254 .active_low = 1,
255 },{
256 .name = "enet2", /* Yellow Led */
257 .gpio = 125,
258 .active_low = 1,
259 },{
260 .name = "sig1_1", /* Green Led */
261 .gpio = 126,
262 .active_low = 1,
263 },{
264 .name = "sig1_2", /* Yellow Led */
265 .gpio = 127,
266 .active_low = 1,
267 },{
268 .name = "sig2_1", /* Green Led */
269 .gpio = 128,
270 .active_low = 1,
271 },{
272 .name = "sig2_2", /* Yellow Led */
273 .gpio = 129,
274 .active_low = 1,
275 },{
276 .name = "sig3_1", /* Green Led */
277 .gpio = 130,
278 .active_low = 1,
279 },{
280 .name = "sig3_2", /* Yellow Led */
281 .gpio = 131,
282 .active_low = 1,
283 },{
284 .name = "net1", /*Green Led */
285 .gpio = 109,
286 .active_low = 1,
287 },{
288 .name = "net2", /* Red Led */
289 .gpio = 110,
290 .active_low = 1,
291 },{
292 .name = "mod1", /* Green Led */
293 .gpio = 111,
294 .active_low = 1,
295 },{
296 .name = "mod2", /* Red Led */
297 .gpio = 112,
298 .active_low = 1,
299 },
300 };
301
302 static struct gpio_led_platform_data laguna_gpio_leds_data = {
303 .num_leds = 22,
304 .leds = laguna_gpio_leds,
305 };
306
307 static struct platform_device laguna_gpio_leds_device = {
308 .name = "leds-gpio",
309 .id = -1,
310 .dev.platform_data = &laguna_gpio_leds_data,
311 };
312
313 /*
314 * Ethernet
315 */
316 static struct cns3xxx_plat_info laguna_net_data = {
317 .ports = 0,
318 .phy = {
319 0,
320 1,
321 2,
322 },
323 };
324
325 static struct resource laguna_net_resource[] = {
326 {
327 .name = "eth0_mem",
328 .start = CNS3XXX_SWITCH_BASE,
329 .end = CNS3XXX_SWITCH_BASE + SZ_4K - 1,
330 .flags = IORESOURCE_MEM
331 }, {
332 .name = "eth_rx",
333 .start = IRQ_CNS3XXX_SW_R0RXC,
334 .end = IRQ_CNS3XXX_SW_R0RXC,
335 .flags = IORESOURCE_IRQ
336 }, {
337 .name = "eth_stat",
338 .start = IRQ_CNS3XXX_SW_STATUS,
339 .end = IRQ_CNS3XXX_SW_STATUS,
340 .flags = IORESOURCE_IRQ
341 }
342 };
343
344 static u64 laguna_net_dmamask = DMA_BIT_MASK(32);
345 static struct platform_device laguna_net_device = {
346 .name = "cns3xxx_eth",
347 .id = 0,
348 .resource = laguna_net_resource,
349 .num_resources = ARRAY_SIZE(laguna_net_resource),
350 .dev = {
351 .dma_mask = &laguna_net_dmamask,
352 .coherent_dma_mask = DMA_BIT_MASK(32),
353 .platform_data = &laguna_net_data,
354 }
355 };
356
357 /*
358 * UART
359 */
360 static void __init laguna_early_serial_setup(void)
361 {
362 #ifdef CONFIG_SERIAL_8250_CONSOLE
363 static struct uart_port laguna_serial_port = {
364 .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
365 .mapbase = CNS3XXX_UART0_BASE,
366 .irq = IRQ_CNS3XXX_UART0,
367 .iotype = UPIO_MEM,
368 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
369 .regshift = 2,
370 .uartclk = 24000000,
371 .line = 0,
372 .type = PORT_16550A,
373 .fifosize = 16,
374 };
375
376 early_serial_setup(&laguna_serial_port);
377 #endif
378 }
379
380 static struct resource laguna_uart_resources[] = {
381 {
382 .start = CNS3XXX_UART0_BASE,
383 .end = CNS3XXX_UART0_BASE + SZ_4K - 1,
384 .flags = IORESOURCE_MEM
385 },{
386 .start = CNS3XXX_UART2_BASE,
387 .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
388 .flags = IORESOURCE_MEM
389 },{
390 .start = CNS3XXX_UART2_BASE,
391 .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
392 .flags = IORESOURCE_MEM
393 },
394 };
395
396 static struct plat_serial8250_port laguna_uart_data[] = {
397 {
398 .mapbase = (CNS3XXX_UART0_BASE),
399 .irq = IRQ_CNS3XXX_UART0,
400 .iotype = UPIO_MEM,
401 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP,
402 .regshift = 2,
403 .uartclk = 24000000,
404 .type = PORT_16550A,
405 },{
406 .mapbase = (CNS3XXX_UART1_BASE),
407 .irq = IRQ_CNS3XXX_UART1,
408 .iotype = UPIO_MEM,
409 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP,
410 .regshift = 2,
411 .uartclk = 24000000,
412 .type = PORT_16550A,
413 },{
414 .mapbase = (CNS3XXX_UART2_BASE),
415 .irq = IRQ_CNS3XXX_UART2,
416 .iotype = UPIO_MEM,
417 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP,
418 .regshift = 2,
419 .uartclk = 24000000,
420 .type = PORT_16550A,
421 },
422 { },
423 };
424
425 static struct platform_device laguna_uart = {
426 .name = "serial8250",
427 .id = PLAT8250_DEV_PLATFORM,
428 .dev.platform_data = laguna_uart_data,
429 .num_resources = 3,
430 .resource = laguna_uart_resources
431 };
432
433 /*
434 * USB
435 */
436 static struct resource cns3xxx_usb_ehci_resources[] = {
437 [0] = {
438 .start = CNS3XXX_USB_BASE,
439 .end = CNS3XXX_USB_BASE + SZ_16M - 1,
440 .flags = IORESOURCE_MEM,
441 },
442 [1] = {
443 .start = IRQ_CNS3XXX_USB_EHCI,
444 .flags = IORESOURCE_IRQ,
445 },
446 };
447
448 static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
449
450 static int csn3xxx_usb_power_on(struct platform_device *pdev)
451 {
452 /*
453 * EHCI and OHCI share the same clock and power,
454 * resetting twice would cause the 1st controller been reset.
455 * Therefore only do power up at the first up device, and
456 * power down at the last down device.
457 *
458 * Set USB AHB INCR length to 16
459 */
460 if (atomic_inc_return(&usb_pwr_ref) == 1) {
461 cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
462 cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
463 cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
464 __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
465 MISC_CHIP_CONFIG_REG);
466 }
467
468 return 0;
469 }
470
471 static void csn3xxx_usb_power_off(struct platform_device *pdev)
472 {
473 /*
474 * EHCI and OHCI share the same clock and power,
475 * resetting twice would cause the 1st controller been reset.
476 * Therefore only do power up at the first up device, and
477 * power down at the last down device.
478 */
479 if (atomic_dec_return(&usb_pwr_ref) == 0)
480 cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
481 }
482
483 static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
484 .power_on = csn3xxx_usb_power_on,
485 .power_off = csn3xxx_usb_power_off,
486 };
487
488 static struct platform_device cns3xxx_usb_ehci_device = {
489 .name = "ehci-platform",
490 .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
491 .resource = cns3xxx_usb_ehci_resources,
492 .dev = {
493 .dma_mask = &cns3xxx_usb_ehci_dma_mask,
494 .coherent_dma_mask = DMA_BIT_MASK(32),
495 .platform_data = &cns3xxx_usb_ehci_pdata,
496 },
497 };
498
499 static struct resource cns3xxx_usb_ohci_resources[] = {
500 [0] = {
501 .start = CNS3XXX_USB_OHCI_BASE,
502 .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
503 .flags = IORESOURCE_MEM,
504 },
505 [1] = {
506 .start = IRQ_CNS3XXX_USB_OHCI,
507 .flags = IORESOURCE_IRQ,
508 },
509 };
510
511 static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
512
513 static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
514 .num_ports = 1,
515 .power_on = csn3xxx_usb_power_on,
516 .power_off = csn3xxx_usb_power_off,
517 };
518
519 static struct platform_device cns3xxx_usb_ohci_device = {
520 .name = "ohci-platform",
521 .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
522 .resource = cns3xxx_usb_ohci_resources,
523 .dev = {
524 .dma_mask = &cns3xxx_usb_ohci_dma_mask,
525 .coherent_dma_mask = DMA_BIT_MASK(32),
526 .platform_data = &cns3xxx_usb_ohci_pdata,
527 },
528 };
529
530 static struct resource cns3xxx_usb_otg_resources[] = {
531 [0] = {
532 .start = CNS3XXX_USBOTG_BASE,
533 .end = CNS3XXX_USBOTG_BASE + SZ_16M - 1,
534 .flags = IORESOURCE_MEM,
535 },
536 [1] = {
537 .start = IRQ_CNS3XXX_USB_OTG,
538 .flags = IORESOURCE_IRQ,
539 },
540 };
541
542 static u64 cns3xxx_usb_otg_dma_mask = DMA_BIT_MASK(32);
543
544 static struct platform_device cns3xxx_usb_otg_device = {
545 .name = "dwc2",
546 .num_resources = ARRAY_SIZE(cns3xxx_usb_otg_resources),
547 .resource = cns3xxx_usb_otg_resources,
548 .dev = {
549 .dma_mask = &cns3xxx_usb_otg_dma_mask,
550 .coherent_dma_mask = DMA_BIT_MASK(32),
551 },
552 };
553
554 /*
555 * I2C
556 */
557 static struct resource laguna_i2c_resource[] = {
558 {
559 .start = CNS3XXX_SSP_BASE + 0x20,
560 .end = CNS3XXX_SSP_BASE + 0x3f,
561 .flags = IORESOURCE_MEM,
562 },{
563 .start = IRQ_CNS3XXX_I2C,
564 .flags = IORESOURCE_IRQ,
565 },
566 };
567
568 static struct platform_device laguna_i2c_controller = {
569 .name = "cns3xxx-i2c",
570 .num_resources = 2,
571 .resource = laguna_i2c_resource,
572 };
573
574 static struct memory_accessor *at24_mem_acc;
575
576 static void at24_setup(struct memory_accessor *mem_acc, void *context)
577 {
578 char buf[16];
579
580 at24_mem_acc = mem_acc;
581
582 /* Read MAC addresses */
583 if (at24_mem_acc->read(at24_mem_acc, buf, 0x100, 6) == 6)
584 memcpy(&laguna_net_data.hwaddr[0], buf, ETH_ALEN);
585 if (at24_mem_acc->read(at24_mem_acc, buf, 0x106, 6) == 6)
586 memcpy(&laguna_net_data.hwaddr[1], buf, ETH_ALEN);
587 if (at24_mem_acc->read(at24_mem_acc, buf, 0x10C, 6) == 6)
588 memcpy(&laguna_net_data.hwaddr[2], buf, ETH_ALEN);
589 if (at24_mem_acc->read(at24_mem_acc, buf, 0x112, 6) == 6)
590 memcpy(&laguna_net_data.hwaddr[3], buf, ETH_ALEN);
591
592 /* Read out Model Information */
593 if (at24_mem_acc->read(at24_mem_acc, buf, 0x130, 16) == 16)
594 memcpy(&laguna_info.model, buf, 16);
595 if (at24_mem_acc->read(at24_mem_acc, buf, 0x140, 1) == 1)
596 memcpy(&laguna_info.nor_flash_size, buf, 1);
597 if (at24_mem_acc->read(at24_mem_acc, buf, 0x141, 1) == 1)
598 memcpy(&laguna_info.spi_flash_size, buf, 1);
599 if (at24_mem_acc->read(at24_mem_acc, buf, 0x142, 4) == 4)
600 memcpy(&laguna_info.config_bitmap, buf, 4);
601 if (at24_mem_acc->read(at24_mem_acc, buf, 0x146, 4) == 4)
602 memcpy(&laguna_info.config2_bitmap, buf, 4);
603 };
604
605 static struct at24_platform_data laguna_eeprom_info = {
606 .byte_len = 1024,
607 .page_size = 16,
608 .flags = AT24_FLAG_READONLY,
609 .setup = at24_setup,
610 };
611
612 static struct pca953x_platform_data laguna_pca_data = {
613 .gpio_base = 100,
614 .irq_base = -1,
615 };
616
617 static struct pca953x_platform_data laguna_pca2_data = {
618 .gpio_base = 116,
619 .irq_base = -1,
620 };
621
622 static struct i2c_board_info __initdata laguna_i2c_devices[] = {
623 {
624 I2C_BOARD_INFO("pca9555", 0x23),
625 .platform_data = &laguna_pca_data,
626 },{
627 I2C_BOARD_INFO("pca9555", 0x27),
628 .platform_data = &laguna_pca2_data,
629 },{
630 I2C_BOARD_INFO("gsp", 0x29),
631 },{
632 I2C_BOARD_INFO ("24c08",0x50),
633 .platform_data = &laguna_eeprom_info,
634 },{
635 I2C_BOARD_INFO("ds1672", 0x68),
636 },
637 };
638
639 /*
640 * Watchdog
641 */
642
643 static struct resource laguna_watchdog_resources[] = {
644 [0] = {
645 .start = CNS3XXX_TC11MP_TWD_BASE + 0x100, // CPU0 watchdog
646 .end = CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1,
647 .flags = IORESOURCE_MEM,
648 },
649 };
650
651 static struct platform_device laguna_watchdog = {
652 .name = "mpcore_wdt",
653 .id = -1,
654 .num_resources = ARRAY_SIZE(laguna_watchdog_resources),
655 .resource = laguna_watchdog_resources,
656 };
657
658 /*
659 * GPS PPS
660 */
661 static struct pps_gpio_platform_data laguna_pps_data = {
662 .gpio_pin = 0,
663 .gpio_label = "GPS_PPS",
664 .assert_falling_edge = 0,
665 .capture_clear = 0,
666 };
667
668 static struct platform_device laguna_pps_device = {
669 .name = "pps-gpio",
670 .id = -1,
671 .dev.platform_data = &laguna_pps_data,
672 };
673
674 /*
675 * GPIO
676 */
677
678 static struct gpio laguna_gpio_gw2391[] = {
679 { 0, GPIOF_IN , "*GPS_PPS" },
680 { 1, GPIOF_IN , "*GSC_IRQ#" },
681 { 2, GPIOF_IN , "*USB_FAULT#" },
682 { 5, GPIOF_OUT_INIT_LOW , "*USB0_PCI_SEL" },
683 { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
684 { 7, GPIOF_OUT_INIT_LOW , "*USB1_PCI_SEL" },
685 { 8, GPIOF_OUT_INIT_HIGH, "*PERST#" },
686 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN#" },
687 { 100, GPIOF_IN , "*USER_PB#" },
688 { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
689 { 108, GPIOF_IN , "DIO0" },
690 { 109, GPIOF_IN , "DIO1" },
691 { 110, GPIOF_IN , "DIO2" },
692 { 111, GPIOF_IN , "DIO3" },
693 { 112, GPIOF_IN , "DIO4" },
694 };
695
696 static struct gpio laguna_gpio_gw2388[] = {
697 { 0, GPIOF_IN , "*GPS_PPS" },
698 { 1, GPIOF_IN , "*GSC_IRQ#" },
699 { 3, GPIOF_IN , "*USB_FAULT#" },
700 { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
701 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
702 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
703 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
704 { 100, GPIOF_OUT_INIT_HIGH, "*USER_PB#" },
705 { 108, GPIOF_IN , "DIO0" },
706 { 109, GPIOF_IN , "DIO1" },
707 { 110, GPIOF_IN , "DIO2" },
708 { 111, GPIOF_IN , "DIO3" },
709 { 112, GPIOF_IN , "DIO4" },
710 };
711
712 static struct gpio laguna_gpio_gw2387[] = {
713 { 0, GPIOF_IN , "*GPS_PPS" },
714 { 1, GPIOF_IN , "*GSC_IRQ#" },
715 { 2, GPIOF_IN , "*USB_FAULT#" },
716 { 5, GPIOF_OUT_INIT_LOW , "*USB_PCI_SEL" },
717 { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
718 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
719 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
720 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
721 { 100, GPIOF_IN , "*USER_PB#" },
722 { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
723 { 108, GPIOF_IN , "DIO0" },
724 { 109, GPIOF_IN , "DIO1" },
725 { 110, GPIOF_IN , "DIO2" },
726 { 111, GPIOF_IN , "DIO3" },
727 { 112, GPIOF_IN , "DIO4" },
728 { 113, GPIOF_IN , "DIO5" },
729 };
730
731 static struct gpio laguna_gpio_gw2385[] = {
732 { 0, GPIOF_IN , "*GSC_IRQ#" },
733 { 1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" },
734 { 2, GPIOF_IN , "*USB_HST_FAULT#" },
735 { 5, GPIOF_IN , "*USB_OTG_FAULT#" },
736 { 6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" },
737 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
738 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
739 { 9, GPIOF_OUT_INIT_LOW , "*SER_EN" },
740 { 10, GPIOF_IN, "*USER_PB#" },
741 { 11, GPIOF_OUT_INIT_HIGH, "*PERST#" },
742 { 100, GPIOF_IN , "*USER_PB#" },
743 { 103, GPIOF_OUT_INIT_HIGH, "V5_EN" },
744 };
745
746 static struct gpio laguna_gpio_gw2384[] = {
747 { 0, GPIOF_IN , "*GSC_IRQ#" },
748 { 1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" },
749 { 2, GPIOF_IN , "*USB_HST_FAULT#" },
750 { 5, GPIOF_IN , "*USB_OTG_FAULT#" },
751 { 6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" },
752 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
753 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
754 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
755 { 12, GPIOF_OUT_INIT_LOW , "J10_DIOLED0" },
756 { 13, GPIOF_OUT_INIT_HIGH, "*I2CMUX_RST#" },
757 { 14, GPIOF_OUT_INIT_LOW , "J10_DIOLED1" },
758 { 15, GPIOF_OUT_INIT_LOW , "J10_DIOLED2" },
759 { 100, GPIOF_IN , "*USER_PB#" },
760 { 103, GPIOF_OUT_INIT_HIGH, "V5_EN" },
761 { 108, GPIOF_IN , "J9_DIOGSC0" },
762 };
763
764 static struct gpio laguna_gpio_gw2383[] = {
765 { 0, GPIOF_IN , "*GPS_PPS" },
766 { 1, GPIOF_IN , "*GSC_IRQ#" },
767 { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
768 { 3, GPIOF_IN , "GPIO0" },
769 { 8, GPIOF_IN , "GPIO1" },
770 { 100, GPIOF_IN , "DIO0" },
771 { 101, GPIOF_IN , "DIO1" },
772 { 108, GPIOF_IN , "*USER_PB#" },
773 };
774
775 static struct gpio laguna_gpio_gw2382[] = {
776 { 0, GPIOF_IN , "*GPS_PPS" },
777 { 1, GPIOF_IN , "*GSC_IRQ#" },
778 { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
779 { 3, GPIOF_IN , "GPIO0" },
780 { 4, GPIOF_IN , "GPIO1" },
781 { 9, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
782 { 10, GPIOF_OUT_INIT_HIGH, "*USB_PCI_SEL#" },
783 { 100, GPIOF_IN , "DIO0" },
784 { 101, GPIOF_IN , "DIO1" },
785 { 108, GPIOF_IN , "*USER_PB#" },
786 };
787
788 static struct gpio laguna_gpio_gw2380[] = {
789 { 0, GPIOF_IN , "*GPS_PPS" },
790 { 1, GPIOF_IN , "*GSC_IRQ#" },
791 { 3, GPIOF_IN , "GPIO0" },
792 { 8, GPIOF_IN , "GPIO1" },
793 { 100, GPIOF_IN , "DIO0" },
794 { 101, GPIOF_IN , "DIO1" },
795 { 102, GPIOF_IN , "DIO2" },
796 { 103, GPIOF_IN , "DIO3" },
797 { 108, GPIOF_IN , "*USER_PB#" },
798 };
799
800 /*
801 * Initialization
802 */
803 static void __init laguna_init(void)
804 {
805 struct clk *clk;
806 u32 __iomem *reg;
807
808 clk = clk_register_fixed_rate(NULL, "cpu", NULL,
809 CLK_IS_ROOT | CLK_IGNORE_UNUSED,
810 cns3xxx_cpu_clock() * (1000000 / 8));
811 clk_register_clkdev(clk, "cpu", NULL);
812
813 platform_device_register(&laguna_watchdog);
814
815 platform_device_register(&laguna_i2c_controller);
816
817 /* Set ext_int 0-3 drive strength to 21 mA */
818 reg = MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B;
819 *reg |= 0x300;
820
821 /* Enable SCL/SDA for I2C */
822 reg = MISC_GPIOB_PIN_ENABLE_REG;
823 *reg |= BIT(12) | BIT(13);
824
825 /* Enable MMC/SD pins */
826 *reg |= BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11);
827
828 cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
829 cns3xxx_pwr_power_up(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
830 cns3xxx_pwr_soft_rst(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
831
832 cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SPI_PCM_I2C));
833 cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SPI_PCM_I2C));
834
835 i2c_register_board_info(0, ARRAY_AND_SIZE(laguna_i2c_devices));
836
837 pm_power_off = cns3xxx_power_off;
838 }
839
840 static struct map_desc laguna_io_desc[] __initdata = {
841 {
842 .virtual = CNS3XXX_UART0_BASE_VIRT,
843 .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
844 .length = SZ_4K,
845 .type = MT_DEVICE,
846 },
847 };
848
849 static void __init laguna_map_io(void)
850 {
851 cns3xxx_map_io();
852 cns3xxx_pcie_iotable_init();
853 iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
854 laguna_early_serial_setup();
855 }
856
857 static int laguna_register_gpio(struct gpio *array, size_t num)
858 {
859 int i, err, ret;
860
861 ret = 0;
862 for (i = 0; i < num; i++, array++) {
863 const char *label = array->label;
864 if (label[0] == '*')
865 label++;
866 err = gpio_request_one(array->gpio, array->flags, label);
867 if (err)
868 ret = err;
869 else {
870 err = gpio_export(array->gpio, array->label[0] != '*');
871 }
872 }
873 return ret;
874 }
875
876 static int __init laguna_pcie_init(void)
877 {
878 if (!machine_is_gw2388())
879 return 0;
880
881 return cns3xxx_pcie_init();
882 }
883 subsys_initcall(laguna_pcie_init);
884
885 static int __init laguna_model_setup(void)
886 {
887 u32 __iomem *mem;
888 u32 reg;
889
890 if (!machine_is_gw2388())
891 return 0;
892
893 printk("Running on Gateworks Laguna %s\n", laguna_info.model);
894 cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
895 NR_IRQS_CNS3XXX);
896 cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
897 NR_IRQS_CNS3XXX + 32);
898
899 if (strncmp(laguna_info.model, "GW", 2) == 0) {
900 if (laguna_info.config_bitmap & ETH0_LOAD)
901 laguna_net_data.ports |= BIT(0);
902 if (laguna_info.config_bitmap & ETH1_LOAD)
903 laguna_net_data.ports |= BIT(1);
904 if (laguna_info.config_bitmap & ETH2_LOAD)
905 laguna_net_data.ports |= BIT(2);
906 if (laguna_net_data.ports)
907 platform_device_register(&laguna_net_device);
908
909 if ((laguna_info.config_bitmap & SATA0_LOAD) ||
910 (laguna_info.config_bitmap & SATA1_LOAD))
911 cns3xxx_ahci_init();
912
913 if (laguna_info.config_bitmap & (USB0_LOAD)) {
914 cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
915
916 /* DRVVBUS pins share with GPIOA */
917 mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0014);
918 reg = __raw_readl(mem);
919 reg |= 0x8;
920 __raw_writel(reg, mem);
921
922 /* Enable OTG */
923 mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0808);
924 reg = __raw_readl(mem);
925 reg &= ~(1 << 10);
926 __raw_writel(reg, mem);
927
928 platform_device_register(&cns3xxx_usb_otg_device);
929 }
930
931 if (laguna_info.config_bitmap & (USB1_LOAD)) {
932 platform_device_register(&cns3xxx_usb_ehci_device);
933 platform_device_register(&cns3xxx_usb_ohci_device);
934 }
935
936 if (laguna_info.config_bitmap & (SD_LOAD))
937 cns3xxx_sdhci_init();
938
939 if (laguna_info.config_bitmap & (UART0_LOAD))
940 laguna_uart.num_resources = 1;
941 if (laguna_info.config_bitmap & (UART1_LOAD))
942 laguna_uart.num_resources = 2;
943 if (laguna_info.config_bitmap & (UART2_LOAD))
944 laguna_uart.num_resources = 3;
945 platform_device_register(&laguna_uart);
946
947 if (laguna_info.config2_bitmap & (NOR_FLASH_LOAD)) {
948 switch (laguna_info.nor_flash_size) {
949 case 1:
950 laguna_nor_partitions[3].size = SZ_8M - SZ_256K - SZ_128K - SZ_2M;
951 laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_8M - 1;
952 break;
953 case 2:
954 laguna_nor_partitions[3].size = SZ_16M - SZ_256K - SZ_128K - SZ_2M;
955 laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_16M - 1;
956 break;
957 case 3:
958 laguna_nor_partitions[3].size = SZ_32M - SZ_256K - SZ_128K - SZ_2M;
959 laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_32M - 1;
960 break;
961 case 4:
962 laguna_nor_partitions[3].size = SZ_64M - SZ_256K - SZ_128K - SZ_2M;
963 laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_64M - 1;
964 break;
965 case 5:
966 laguna_nor_partitions[3].size = SZ_128M - SZ_256K - SZ_128K - SZ_2M;
967 laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_128M - 1;
968 break;
969 }
970 platform_device_register(&laguna_nor_pdev);
971 }
972
973 if (laguna_info.config2_bitmap & (SPI_FLASH_LOAD)) {
974 switch (laguna_info.spi_flash_size) {
975 case 1:
976 laguna_spi_partitions[3].size = SZ_4M - SZ_2M;
977 break;
978 case 2:
979 laguna_spi_partitions[3].size = SZ_8M - SZ_2M;
980 break;
981 case 3:
982 laguna_spi_partitions[3].size = SZ_16M - SZ_2M;
983 break;
984 case 4:
985 laguna_spi_partitions[3].size = SZ_32M - SZ_2M;
986 break;
987 case 5:
988 laguna_spi_partitions[3].size = SZ_64M - SZ_2M;
989 break;
990 }
991 spi_register_board_info(ARRAY_AND_SIZE(laguna_spi_devices));
992 }
993
994 if ((laguna_info.config_bitmap & SPI0_LOAD) ||
995 (laguna_info.config_bitmap & SPI1_LOAD))
996 platform_device_register(&laguna_spi_controller);
997
998 if (laguna_info.config2_bitmap & GPS_LOAD)
999 platform_device_register(&laguna_pps_device);
1000
1001 /*
1002 * Do any model specific setup not known by the bitmap by matching
1003 * the first 6 characters of the model name
1004 */
1005
1006 if ( (strncmp(laguna_info.model, "GW2388", 6) == 0)
1007 || (strncmp(laguna_info.model, "GW2389", 6) == 0) )
1008 {
1009 // configure GPIO's
1010 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2388));
1011 // configure LED's
1012 laguna_gpio_leds_data.num_leds = 2;
1013 } else if (strncmp(laguna_info.model, "GW2387", 6) == 0) {
1014 // configure GPIO's
1015 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2387));
1016 // configure LED's
1017 laguna_gpio_leds_data.num_leds = 2;
1018 } else if (strncmp(laguna_info.model, "GW2385", 6) == 0) {
1019 // configure GPIO's
1020 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2385));
1021 // configure LED's
1022 laguna_gpio_leds[0].gpio = 115;
1023 laguna_gpio_leds[1].gpio = 12;
1024 laguna_gpio_leds[1].name = "red";
1025 laguna_gpio_leds[1].active_low = 0,
1026 laguna_gpio_leds[2].gpio = 14;
1027 laguna_gpio_leds[2].name = "green";
1028 laguna_gpio_leds[2].active_low = 0,
1029 laguna_gpio_leds[3].gpio = 15;
1030 laguna_gpio_leds[3].name = "blue";
1031 laguna_gpio_leds[3].active_low = 0,
1032 laguna_gpio_leds_data.num_leds = 4;
1033 } else if (strncmp(laguna_info.model, "GW2384", 6) == 0) {
1034 // configure GPIO's
1035 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2384));
1036 // configure LED's
1037 laguna_gpio_leds_data.num_leds = 1;
1038 } else if (strncmp(laguna_info.model, "GW2383", 6) == 0) {
1039 // configure GPIO's
1040 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2383));
1041 // configure LED's
1042 laguna_gpio_leds[0].gpio = 107;
1043 laguna_gpio_leds_data.num_leds = 1;
1044 } else if (strncmp(laguna_info.model, "GW2382", 6) == 0) {
1045 // configure GPIO's
1046 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2382));
1047 // configure LED's
1048 laguna_gpio_leds[0].gpio = 107;
1049 laguna_gpio_leds_data.num_leds = 1;
1050 } else if (strncmp(laguna_info.model, "GW2380", 6) == 0) {
1051 // configure GPIO's
1052 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2380));
1053 // configure LED's
1054 laguna_gpio_leds[0].gpio = 107;
1055 laguna_gpio_leds[1].gpio = 106;
1056 laguna_gpio_leds_data.num_leds = 2;
1057 } else if (strncmp(laguna_info.model, "GW2391", 6) == 0) {
1058 // configure GPIO's
1059 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2391));
1060 // configure LED's
1061 laguna_gpio_leds_data.num_leds = 2;
1062 }
1063 platform_device_register(&laguna_gpio_leds_device);
1064 } else {
1065 // Do some defaults here, not sure what yet
1066 }
1067 return 0;
1068 }
1069 late_initcall(laguna_model_setup);
1070
1071 MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
1072 .smp = smp_ops(cns3xxx_smp_ops),
1073 .atag_offset = 0x100,
1074 .map_io = laguna_map_io,
1075 .init_irq = cns3xxx_init_irq,
1076 .init_time = cns3xxx_timer_init,
1077 .init_machine = laguna_init,
1078 .restart = cns3xxx_restart,
1079 MACHINE_END
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