target/linux/cns3xxx/patches-3.3/470-gpio_irq.patch

   1 --- a/arch/arm/mach-cns3xxx/Makefile
   2 +++ b/arch/arm/mach-cns3xxx/Makefile
   3 @@ -1,4 +1,4 @@
   4 -obj-$(CONFIG_ARCH_CNS3XXX)             += core.o pm.o devices.o
   5 +obj-$(CONFIG_ARCH_CNS3XXX)             += core.o gpio.o pm.o devices.o
   6  obj-$(CONFIG_PCI)                      += pcie.o
   7  obj-$(CONFIG_MACH_CNS3420VB)           += cns3420vb.o
   8  obj-$(CONFIG_MACH_GW2388)              += laguna.o
   9 --- a/arch/arm/mach-cns3xxx/cns3420vb.c
  10 +++ b/arch/arm/mach-cns3xxx/cns3420vb.c
  11 @@ -198,6 +198,10 @@ static void __init cns3420_init(void)
  12
  13         cns3xxx_ahci_init();
  14         cns3xxx_sdhci_init();
  15 +       cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
  16 +               NR_IRQS_CNS3XXX);
  17 +       cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
  18 +               NR_IRQS_CNS3XXX + 32);
  19
  20         pm_power_off = cns3xxx_power_off;
  21  }
  22 --- a/arch/arm/mach-cns3xxx/core.c
  23 +++ b/arch/arm/mach-cns3xxx/core.c
  24 @@ -21,7 +21,6 @@
  25  #include <asm/hardware/gic.h>
  26  #include <asm/smp_twd.h>
  27  #include <asm/hardware/cache-l2x0.h>
  28 -#include <asm/gpio.h>
  29  #include <mach/cns3xxx.h>
  30  #include "core.h"
  31
  32 @@ -83,73 +82,12 @@ static struct map_desc cns3xxx_io_desc[]
  33         },
  34  };
  35
  36 -static inline void gpio_line_config(u8 line, u32 direction)
  37 -{
  38 -       u32 reg;
  39 -       if (direction) {
  40 -               if (line < 32) {
  41 -                       reg = __raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
  42 -                       reg |= (1 << line);
  43 -                       __raw_writel(reg, CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
  44 -               } else {
  45 -                       reg = __raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
  46 -                       reg |= (1 << (line - 32));
  47 -                       __raw_writel(reg, CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
  48 -               }
  49 -       } else {
  50 -               if (line < 32) {
  51 -                       reg = __raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
  52 -                       reg &= ~(1 << line);
  53 -                       __raw_writel(reg, CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
  54 -               } else {
  55 -                       reg = __raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
  56 -                       reg &= ~(1 << (line - 32));
  57 -                       __raw_writel(reg, CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
  58 -               }
  59 -       }
  60 -}
  61 -
  62 -static int cns3xxx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
  63 -{
  64 -       gpio_line_config(gpio, CNS3XXX_GPIO_IN);
  65 -       return 0;
  66 -}
  67 -
  68 -static int cns3xxx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int level)
  69 -{
  70 -       gpio_line_set(gpio, level);
  71 -       gpio_line_config(gpio, CNS3XXX_GPIO_OUT);
  72 -       return 0;
  73 -}
  74 -
  75 -static int cns3xxx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
  76 -{
  77 -       return gpio_get_value(gpio);
  78 -}
  79 -
  80 -static void cns3xxx_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
  81 -{
  82 -       gpio_set_value(gpio, value);
  83 -}
  84 -
  85 -static struct gpio_chip cns3xxx_gpio_chip = {
  86 -       .label                  = "CNS3XXX_GPIO_CHIP",
  87 -       .direction_input        = cns3xxx_gpio_direction_input,
  88 -       .direction_output       = cns3xxx_gpio_direction_output,
  89 -       .get                    = cns3xxx_gpio_get_value,
  90 -       .set                    = cns3xxx_gpio_set_value,
  91 -       .base                   = 0,
  92 -       .ngpio                  = 64,
  93 -};
  94 -
  95  void __init cns3xxx_common_init(void)
  96  {
  97  #ifdef CONFIG_LOCAL_TIMERS
  98         twd_base = (void __iomem *) CNS3XXX_TC11MP_TWD_BASE_VIRT;
  99  #endif
 100         iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
 101 -
 102 -       gpiochip_add(&cns3xxx_gpio_chip);
 103  }
 104
 105  /* used by entry-macro.S */
 106 --- a/arch/arm/Kconfig
 107 +++ b/arch/arm/Kconfig
 108 @@ -366,7 +366,8 @@ config ARCH_CLPS711X
 109  config ARCH_CNS3XXX
 110         bool "Cavium Networks CNS3XXX family"
 111         select CPU_V6K
 112 -       select ARCH_WANT_OPTIONAL_GPIOLIB
 113 +       select ARCH_REQUIRE_GPIOLIB
 114 +       select GENERIC_IRQ_CHIP
 115         select GENERIC_CLOCKEVENTS
 116         select ARM_GIC
 117         select CLKDEV_LOOKUP
 118 --- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
 119 +++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
 120 @@ -627,7 +627,7 @@ int cns3xxx_cpu_clock(void);
 121
 122  #if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_CNS3XXX)
 123  #undef NR_IRQS
 124 -#define NR_IRQS                                NR_IRQS_CNS3XXX
 125 +#define NR_IRQS                                (NR_IRQS_CNS3XXX + 64)
 126  #endif
 127
 128  #endif /* __MACH_BOARD_CNS3XXX_H */