cns3xxx: add preliminary 4.9 support
[openwrt/openwrt.git] / target / linux / cns3xxx / patches-4.9 / 095-gpio_support.patch
1 --- a/arch/arm/mach-cns3xxx/cns3420vb.c
2 +++ b/arch/arm/mach-cns3xxx/cns3420vb.c
3 @@ -245,6 +245,10 @@ static void __init cns3420_init(void)
4
5 cns3xxx_ahci_init();
6 cns3xxx_sdhci_init();
7 + cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
8 + NR_IRQS_CNS3XXX);
9 + cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
10 + NR_IRQS_CNS3XXX + 32);
11
12 pm_power_off = cns3xxx_power_off;
13 }
14 --- a/arch/arm/mach-cns3xxx/Kconfig
15 +++ b/arch/arm/mach-cns3xxx/Kconfig
16 @@ -2,6 +2,8 @@ menuconfig ARCH_CNS3XXX
17 bool "Cavium Networks CNS3XXX family"
18 depends on ARCH_MULTI_V6
19 select ARM_GIC
20 + select ARCH_REQUIRE_GPIOLIB
21 + select GENERIC_IRQ_CHIP
22 select HAVE_ARM_SCU if SMP
23 select HAVE_ARM_TWD
24 select HAVE_SMP
25 --- a/arch/arm/mach-cns3xxx/Makefile
26 +++ b/arch/arm/mach-cns3xxx/Makefile
27 @@ -1,7 +1,7 @@
28 ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
29
30 obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o
31 -cns3xxx-y += core.o pm.o
32 +cns3xxx-y += core.o pm.o gpio.o
33 cns3xxx-$(CONFIG_ATAGS) += devices.o
34 cns3xxx-$(CONFIG_PCI) += pcie.o
35 cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
36 --- a/arch/arm/mach-cns3xxx/cns3xxx.h
37 +++ b/arch/arm/mach-cns3xxx/cns3xxx.h
38 @@ -68,8 +68,10 @@
39 #define SMC_PCELL_ID_3_OFFSET 0xFFC
40
41 #define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */
42 +#define CNS3XXX_GPIOA_BASE_VIRT 0xFB006000
43
44 #define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */
45 +#define CNS3XXX_GPIOB_BASE_VIRT 0xFB007000
46
47 #define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */
48
49 --- a/arch/arm/mach-cns3xxx/core.c
50 +++ b/arch/arm/mach-cns3xxx/core.c
51 @@ -50,6 +50,16 @@ static struct map_desc cns3xxx_io_desc[]
52 .pfn = __phys_to_pfn(CNS3XXX_PM_BASE),
53 .length = SZ_4K,
54 .type = MT_DEVICE,
55 + }, {
56 + .virtual = CNS3XXX_GPIOA_BASE_VIRT,
57 + .pfn = __phys_to_pfn(CNS3XXX_GPIOA_BASE),
58 + .length = SZ_4K,
59 + .type = MT_DEVICE,
60 + }, {
61 + .virtual = CNS3XXX_GPIOB_BASE_VIRT,
62 + .pfn = __phys_to_pfn(CNS3XXX_GPIOB_BASE),
63 + .length = SZ_4K,
64 + .type = MT_DEVICE,
65 #ifdef CONFIG_PCI
66 }, {
67 .virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT,