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add preliminary coldfire v4e support
[openwrt/openwrt.git] / target / linux / coldfire / patches / 001-cf.patch
1 --- /dev/null
2 +++ b/arch/m68k/coldfire/cache.c
3 @@ -0,0 +1,43 @@
4 +/*
5 + * linux/arch/m68k/coldfire/cache.c
6 + *
7 + * Matt Waddel Matt.Waddel@freescale.com
8 + * Kurt Mahan kmahan@freescale.com
9 + * Copyright Freescale Semiconductor, Inc. 2007
10 + *
11 + * This program is free software; you can redistribute it and/or modify
12 + * it under the terms of the GNU General Public License as published by
13 + * the Free Software Foundation; either version 2 of the License, or
14 + * (at your option) any later version.
15 + */
16 +
17 +#include <linux/interrupt.h>
18 +#include <asm/cfcache.h>
19 +#include <asm/coldfire.h>
20 +#include <asm/system.h>
21 +
22 +/* Cache Control Reg shadow reg */
23 +unsigned long shadow_cacr;
24 +
25 +/**
26 + * cacr_set - Set the Cache Control Register
27 + * @x Value to set
28 + */
29 +void cacr_set(unsigned long x)
30 +{
31 + shadow_cacr = x;
32 +
33 + __asm__ __volatile__ ("movec %0, %%cacr"
34 + : /* no outputs */
35 + : "r" (shadow_cacr));
36 +}
37 +
38 +/**
39 + * cacr_get - Get the current value of the Cache Control Register
40 + *
41 + * @return CACR value
42 + */
43 +unsigned long cacr_get(void)
44 +{
45 + return shadow_cacr;
46 +}
47 --- /dev/null
48 +++ b/arch/m68k/coldfire/config.c
49 @@ -0,0 +1,483 @@
50 +/*
51 + * linux/arch/m68k/coldfire/config.c
52 + *
53 + * Kurt Mahan kmahan@freescale.com
54 + * Matt Waddel Matt.Waddel@freescale.com
55 + * Copyright Freescale Semiconductor, Inc. 2007, 2008
56 + *
57 + * This program is free software; you can redistribute it and/or modify
58 + * it under the terms of the GNU General Public License as published by
59 + * the Free Software Foundation; either version 2 of the License, or
60 + * (at your option) any later version.
61 + */
62 +
63 +#include <linux/module.h>
64 +#include <linux/init.h>
65 +#include <linux/string.h>
66 +#include <linux/kernel.h>
67 +#include <linux/console.h>
68 +#include <linux/bootmem.h>
69 +#include <linux/mm.h>
70 +#include <asm/bootinfo.h>
71 +#include <asm/machdep.h>
72 +#include <asm/coldfire.h>
73 +#include <asm/cfcache.h>
74 +#include <asm/cacheflush.h>
75 +#include <asm/io.h>
76 +#include <asm/cfmmu.h>
77 +#include <asm/setup.h>
78 +#include <asm/irq.h>
79 +#include <asm/traps.h>
80 +#include <asm/movs.h>
81 +#include <asm/movs.h>
82 +#include <asm/page.h>
83 +#include <asm/pgalloc.h>
84 +
85 +#include <asm/mcfsim.h>
86 +
87 +#if defined(CONFIG_M5445X)
88 +#define UBOOT_EXTRA_CLOCKS
89 +#elif defined(CONFIG_M547X_8X)
90 +#define UBOOT_PCI
91 +#endif
92 +#include <asm/bootinfo.h>
93 +
94 +#ifdef CONFIG_M5445X
95 +#include <asm/mcf5445x_intc.h>
96 +#include <asm/mcf5445x_sdramc.h>
97 +#include <asm/mcf5445x_fbcs.h>
98 +#include <asm/mcf5445x_dtim.h>
99 +#include <asm/mcf5445x_xbs.h>
100 +#endif
101 +
102 +#ifdef CONFIG_M547X_8X
103 +#include <asm/m5485gpt.h>
104 +#endif
105 +
106 +extern int get_irq_list(struct seq_file *p, void *v);
107 +extern char _text, _end;
108 +extern char _etext, _edata, __init_begin, __init_end;
109 +extern struct console mcfrs_console;
110 +extern char m68k_command_line[CL_SIZE];
111 +extern unsigned long availmem;
112 +
113 +static int irq_enable[NR_IRQS];
114 +unsigned long num_pages;
115 +
116 +/* ethernet mac addresses from uboot */
117 +unsigned char uboot_enet0[6];
118 +unsigned char uboot_enet1[6];
119 +
120 +void coldfire_sort_memrec(void)
121 +{
122 + int i, j;
123 +
124 + /* Sort the m68k_memory records by address */
125 + for (i = 0; i < m68k_num_memory; ++i) {
126 + for (j = i + 1; j < m68k_num_memory; ++j) {
127 + if (m68k_memory[i].addr > m68k_memory[j].addr) {
128 + struct mem_info tmp;
129 + tmp = m68k_memory[i];
130 + m68k_memory[i] = m68k_memory[j];
131 + m68k_memory[j] = tmp;
132 + }
133 + }
134 + }
135 + /* Trim off discontiguous bits */
136 + for (i = 1; i < m68k_num_memory; ++i) {
137 + if ((m68k_memory[i-1].addr + m68k_memory[i-1].size) !=
138 + m68k_memory[i].addr) {
139 + printk(KERN_DEBUG "m68k_parse_bootinfo: addr gap between \
140 + 0x%lx & 0x%lx\n",
141 + m68k_memory[i-1].addr+m68k_memory[i-1].size,
142 + m68k_memory[i].addr);
143 + m68k_num_memory = i;
144 + break;
145 + }
146 + }
147 +}
148 +
149 +/*
150 + * UBoot Handler
151 + */
152 +int __init uboot_commandline(char *bootargs)
153 +{
154 + int len = 0, cmd_line_len;
155 + static struct uboot_record uboot_info;
156 + u32 offset = PAGE_OFFSET_RAW - PHYS_OFFSET;
157 +
158 + extern unsigned long uboot_info_stk;
159 +
160 + /* validate address */
161 + if ((uboot_info_stk < PAGE_OFFSET_RAW) ||
162 + (uboot_info_stk >= (PAGE_OFFSET_RAW + CONFIG_SDRAM_SIZE)))
163 + return 0;
164 +
165 + /* Add offset to get post-remapped kernel memory location */
166 + uboot_info.bdi = (struct bd_info *)((*(u32 *)(uboot_info_stk)) + offset);
167 + uboot_info.initrd_start = (*(u32 *)(uboot_info_stk+4)) + offset;
168 + uboot_info.initrd_end = (*(u32 *)(uboot_info_stk+8)) + offset;
169 + uboot_info.cmd_line_start = (*(u32 *)(uboot_info_stk+12)) + offset;
170 + uboot_info.cmd_line_stop = (*(u32 *)(uboot_info_stk+16)) + offset;
171 +
172 + /* copy over mac addresses */
173 + memcpy(uboot_enet0, uboot_info.bdi->bi_enet0addr, 6);
174 + memcpy(uboot_enet1, uboot_info.bdi->bi_enet1addr, 6);
175 +
176 + /* copy command line */
177 + cmd_line_len = uboot_info.cmd_line_stop - uboot_info.cmd_line_start;
178 + if ((cmd_line_len > 0) && (cmd_line_len < CL_SIZE-1))
179 + len = (int)strncpy(bootargs, (char *)uboot_info.cmd_line_start,\
180 + cmd_line_len);
181 +
182 + return len;
183 +}
184 +
185 +/*
186 + * This routine does things not done in the bootloader.
187 + */
188 +#if defined(CONFIG_M54451)
189 +#define DEFAULT_COMMAND_LINE "debug root=/dev/nfs rw nfsroot=172.27.155.1:/tftpboot/redstripe/rootfs/ ip=172.27.155.51:172.27.155.1"
190 +#elif defined(CONFIG_M54455)
191 +#define MTD_DEFAULT_COMMAND_LINE "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
192 +#define DEFAULT_COMMAND_LINE "debug root=/dev/nfs rw nfsroot=172.27.155.1:/tftpboot/redstripe/rootfs/ ip=172.27.155.55:172.27.155.1"
193 +#elif defined(CONFIG_M547X_8X)
194 +#define DEFAULT_COMMAND_LINE "debug root=/dev/nfs rw nfsroot=172.27.155.1:/tftpboot/rigo/rootfs/ ip=172.27.155.75:172.27.155.1"
195 +#endif
196 +asmlinkage void __init cf_early_init(void)
197 +{
198 + struct bi_record *record = (struct bi_record *) &_end;
199 +
200 + extern char _end;
201 +
202 +#if defined(CONFIG_M5445X)
203 + SET_VBR((void *)MCF_RAMBAR1);
204 +#elif defined(CONFIG_M547X_8X)
205 + SET_VBR((void *)MCF_RAMBAR0);
206 +#endif
207 +
208 + /* Mask all interrupts */
209 +#if defined(CONFIG_M5445X)
210 + MCF_INTC0_IMRL = 0xFFFFFFFF;
211 + MCF_INTC0_IMRH = 0xFFFFFFFF;
212 + MCF_INTC1_IMRL = 0xFFFFFFFF;
213 + MCF_INTC1_IMRH = 0xFFFFFFFF;
214 +#elif defined(CONFIG_M547X_8X)
215 + MCF_IMRL = 0xFFFFFFFF;
216 + MCF_IMRH = 0xFFFFFFFF;
217 +#endif
218 +
219 +#if defined(CONFIG_M5445X)
220 +#if defined(CONFIG_NOR_FLASH_BASE)
221 + MCF_FBCS_CSAR(1) = CONFIG_NOR_FLASH_BASE;
222 +#else
223 + MCF_FBCS_CSAR(1) = 0x00000000;
224 +#endif
225 +
226 +#if CONFIG_SDRAM_SIZE > (256*1024*1024)
227 + /* Init optional SDRAM chip select */
228 + MCF_SDRAMC_SDCS(1) = (256*1024*1024) | 0x1B;
229 +#endif
230 +#endif /* CONFIG_M5445X */
231 +
232 +#if defined(CONFIG_M5445X)
233 + /* Setup SDRAM crossbar(XBS) priorities */
234 + MCF_XBS_PRS2 = (MCF_XBS_PRS_M0(MCF_XBS_PRI_2) |
235 + MCF_XBS_PRS_M1(MCF_XBS_PRI_3) |
236 + MCF_XBS_PRS_M2(MCF_XBS_PRI_4) |
237 + MCF_XBS_PRS_M3(MCF_XBS_PRI_5) |
238 + MCF_XBS_PRS_M5(MCF_XBS_PRI_6) |
239 + MCF_XBS_PRS_M6(MCF_XBS_PRI_1) |
240 + MCF_XBS_PRS_M7(MCF_XBS_PRI_7));
241 +#endif
242 +
243 + m68k_machtype = MACH_CFMMU;
244 + m68k_fputype = FPU_CFV4E;
245 + m68k_mmutype = MMU_CFV4E;
246 + m68k_cputype = CPU_CFV4E;
247 +
248 + m68k_num_memory = 0;
249 + m68k_memory[m68k_num_memory].addr = CONFIG_SDRAM_BASE;
250 + m68k_memory[m68k_num_memory++].size = CONFIG_SDRAM_SIZE;
251 +
252 + if (!uboot_commandline(m68k_command_line)) {
253 +#if defined(CONFIG_BOOTPARAM)
254 + strncpy(m68k_command_line, CONFIG_BOOTPARAM_STRING, CL_SIZE-1);
255 +#else
256 + strcpy(m68k_command_line, DEFAULT_COMMAND_LINE);
257 +#endif
258 + }
259 +
260 +#if defined(CONFIG_BLK_DEV_INITRD)
261 + /* add initrd image */
262 + record = (struct bi_record *) ((void *)record + record->size);
263 + record->tag = BI_RAMDISK;
264 + record->size = sizeof(record->tag) + sizeof(record->size)
265 + + sizeof(record->data[0]) + sizeof(record->data[1]);
266 +#endif
267 +
268 + /* Mark end of tags. */
269 + record = (struct bi_record *) ((void *) record + record->size);
270 + record->tag = 0;
271 + record->data[0] = 0;
272 + record->data[1] = 0;
273 + record->size = sizeof(record->tag) + sizeof(record->size)
274 + + sizeof(record->data[0]) + sizeof(record->data[1]);
275 +
276 + /* Invalidate caches via CACR */
277 + flush_bcache();
278 + cacr_set(CACHE_DISABLE_MODE);
279 +
280 + /* Turn on caches via CACR, enable EUSP */
281 + cacr_set(CACHE_INITIAL_MODE);
282 +
283 +}
284 +
285 +#if defined(CONFIG_M5445X)
286 +void settimericr(unsigned int timer, unsigned int level)
287 +{
288 + volatile unsigned char *icrp;
289 + unsigned int icr;
290 + unsigned char irq;
291 +
292 + if (timer <= 2) {
293 + switch (timer) {
294 + case 2: irq = 33; icr = MCFSIM_ICR_TIMER2; break;
295 + default: irq = 32; icr = MCFSIM_ICR_TIMER1; break;
296 + }
297 +
298 + icrp = (volatile unsigned char *) (icr);
299 + *icrp = level;
300 + coldfire_enable_irq0(irq);
301 + }
302 +}
303 +#endif
304 +
305 +/* Assembler routines */
306 +asmlinkage void buserr(void);
307 +asmlinkage void trap(void);
308 +asmlinkage void system_call(void);
309 +asmlinkage void inthandler(void);
310 +
311 +void __init coldfire_trap_init(void)
312 +{
313 + int i = 0;
314 + e_vector *vectors;
315 +
316 +#if defined(CONFIG_M5445X)
317 + vectors = (e_vector *)MCF_RAMBAR1;
318 +#elif defined(CONFIG_M547X_8X)
319 + vectors = (e_vector *)MCF_RAMBAR0;
320 +#endif
321 + /*
322 + * There is a common trap handler and common interrupt
323 + * handler that handle almost every vector. We treat
324 + * the system call and bus error special, they get their
325 + * own first level handlers.
326 + */
327 + for (i = 3; (i <= 23); i++)
328 + vectors[i] = trap;
329 + for (i = 33; (i <= 63); i++)
330 + vectors[i] = trap;
331 + for (i = 24; (i <= 31); i++)
332 + vectors[i] = inthandler;
333 + for (i = 64; (i < 255); i++)
334 + vectors[i] = inthandler;
335 +
336 + vectors[255] = 0;
337 + vectors[2] = buserr;
338 + vectors[32] = system_call;
339 +}
340 +
341 +#if defined(CONFIG_M5445X)
342 +
343 +void coldfire_tick(void)
344 +{
345 + /* Reset the ColdFire timer */
346 + __raw_writeb(MCF_DTIM_DTER_CAP | MCF_DTIM_DTER_REF, MCF_DTIM0_DTER);
347 +}
348 +
349 +void __init coldfire_sched_init(irq_handler_t handler)
350 +{
351 + unsigned int mcf_timerlevel = 5;
352 + unsigned int mcf_timervector = 64+32;
353 +
354 + __raw_writew(MCF_DTIM_DTMR_RST_RST, MCF_DTIM0_DTMR);
355 + __raw_writel(((MCF_BUSCLK / 16) / HZ), MCF_DTIM0_DTRR);
356 + __raw_writew(MCF_DTIM_DTMR_ORRI | MCF_DTIM_DTMR_CLK_DIV16 |
357 + MCF_DTIM_DTMR_FRR | MCF_DTIM_DTMR_RST_EN, \
358 + MCF_DTIM0_DTMR);
359 +
360 + request_irq(mcf_timervector, handler, IRQF_DISABLED, \
361 + "timer", (void *)MCF_DTIM0_DTMR);
362 +
363 + settimericr(1, mcf_timerlevel);
364 +}
365 +
366 +int timerirqpending(int timer)
367 +{
368 + unsigned int imr = 0;
369 +
370 + switch (timer) {
371 + case 1: imr = 0x1; break;
372 + case 2: imr = 0x2; break;
373 + default: break;
374 + }
375 +
376 + return (getiprh() & imr);
377 +}
378 +
379 +unsigned long coldfire_gettimeoffset(void)
380 +{
381 + volatile unsigned long trr, tcn, offset;
382 +
383 + tcn = __raw_readw(MCF_DTIM0_DTCN);
384 + trr = __raw_readl(MCF_DTIM0_DTRR);
385 + offset = (tcn * (1000000 / HZ)) / trr;
386 +
387 + /* Check if we just wrapped the counters and maybe missed a tick */
388 + if ((offset < (1000000 / HZ / 2)) && timerirqpending(1))
389 + offset += 1000000 / HZ;
390 + return offset;
391 +}
392 +
393 +#elif defined(CONFIG_M547X_8X)
394 +
395 +void coldfire_tick(void)
396 +{
397 + /* Reset the ColdFire timer */
398 + MCF_SSR(0) = MCF_SSR_ST;
399 +}
400 +
401 +void __init coldfire_sched_init(irq_handler_t handler)
402 +{
403 + int irq = ISC_SLTn(0);
404 +
405 + MCF_SCR(0) = 0;
406 + MCF_ICR(irq) = ILP_SLT0;
407 + request_irq(64 + irq, handler, IRQF_DISABLED, "ColdFire Timer 0", NULL);
408 + MCF_SLTCNT(0) = MCF_BUSCLK / HZ;
409 + MCF_SCR(0) |= MCF_SCR_TEN | MCF_SCR_IEN | MCF_SCR_RUN;
410 +}
411 +
412 +unsigned long coldfire_gettimeoffset(void)
413 +{
414 + volatile unsigned long trr, tcn, offset;
415 + trr = MCF_SLTCNT(0);
416 + tcn = MCF_SCNT(0);
417 +
418 + offset = (trr - tcn) * ((1000000 >> 3) / HZ) / (trr >> 3);
419 + if (MCF_SSR(0) & MCF_SSR_ST)
420 + offset += 1000000 / HZ;
421 +
422 + return offset;
423 +}
424 +
425 +#endif
426 +
427 +void coldfire_reboot(void)
428 +{
429 +#if defined(CONFIG_M5445X)
430 + /* disable interrupts and do a software reset */
431 + asm("movew #0x2700, %%sr\n\t"
432 + "moveb #0x80, %%d0\n\t"
433 + "moveb %%d0, 0xfc0a0000\n\t"
434 + : : : "%d0");
435 +#elif defined(CONFIG_M547X_8X)
436 + /* disable interrupts and enable the watchdog */
437 + printk(KERN_INFO "Rebooting\n");
438 + asm("movew #0x2700, %sr\n");
439 + MCF_GPT_GMS0 = MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4);
440 +#endif
441 +}
442 +
443 +static void coldfire_get_model(char *model)
444 +{
445 + sprintf(model, "Version 4 ColdFire");
446 +}
447 +
448 +static void __init
449 +coldfire_bootmem_alloc(unsigned long memory_start, unsigned long memory_end)
450 +{
451 + unsigned long base_pfn;
452 +
453 + /* compute total pages in system */
454 + num_pages = PAGE_ALIGN(memory_end - PAGE_OFFSET) >> PAGE_SHIFT;
455 +
456 + /* align start/end to page boundries */
457 + memory_start = PAGE_ALIGN(memory_start);
458 + memory_end = memory_end & PAGE_MASK;
459 +
460 + /* page numbers */
461 + base_pfn = __pa(PAGE_OFFSET) >> PAGE_SHIFT;
462 + min_low_pfn = __pa(memory_start) >> PAGE_SHIFT;
463 + max_low_pfn = __pa(memory_end) >> PAGE_SHIFT;
464 +
465 + high_memory = (void *)memory_end;
466 + availmem = memory_start;
467 +
468 + /* setup bootmem data */
469 + m68k_setup_node(0);
470 + availmem += init_bootmem_node(NODE_DATA(0), min_low_pfn,
471 + base_pfn, max_low_pfn);
472 + availmem = PAGE_ALIGN(availmem);
473 + free_bootmem(__pa(availmem), memory_end - (availmem));
474 +}
475 +
476 +void __init config_coldfire(void)
477 +{
478 + unsigned long endmem, startmem;
479 + int i;
480 +
481 + /*
482 + * Calculate endmem from m68k_memory, assume all are contiguous
483 + */
484 + startmem = ((((int) &_end) + (PAGE_SIZE - 1)) & PAGE_MASK);
485 + endmem = PAGE_OFFSET;
486 + for (i = 0; i < m68k_num_memory; ++i)
487 + endmem += m68k_memory[i].size;
488 +
489 + printk(KERN_INFO "starting up linux startmem 0x%lx, endmem 0x%lx, \
490 + size %luMB\n", startmem, endmem, (endmem - startmem) >> 20);
491 +
492 + memset(irq_enable, 0, sizeof(irq_enable));
493 +
494 + /*
495 + * Setup coldfire mach-specific handlers
496 + */
497 + mach_max_dma_address = 0xffffffff;
498 + mach_sched_init = coldfire_sched_init;
499 + mach_tick = coldfire_tick;
500 + mach_gettimeoffset = coldfire_gettimeoffset;
501 + mach_reset = coldfire_reboot;
502 +/* mach_hwclk = coldfire_hwclk; to be done */
503 + mach_get_model = coldfire_get_model;
504 +
505 + coldfire_bootmem_alloc(startmem, endmem-1);
506 +
507 + /*
508 + * initrd setup
509 + */
510 +/* #ifdef CONFIG_BLK_DEV_INITRD
511 + if (m68k_ramdisk.size) {
512 + reserve_bootmem (__pa(m68k_ramdisk.addr), m68k_ramdisk.size);
513 + initrd_start = (unsigned long) m68k_ramdisk.addr;
514 + initrd_end = initrd_start + m68k_ramdisk.size;
515 + printk (KERN_DEBUG "initrd: %08lx - %08lx\n", initrd_start,
516 + initrd_end);
517 + }
518 +#endif */
519 +
520 +#if defined(CONFIG_DUMMY_CONSOLE) || defined(CONFIG_FRAMEBUFFER_CONSOLE)
521 + conswitchp = &dummy_con;
522 +#endif
523 +
524 +#if defined(CONFIG_SERIAL_COLDFIRE)
525 + /*
526 + * This causes trouble when it is re-registered later.
527 + * Currently this is fixed by conditionally commenting
528 + * out the register_console in mcf_serial.c
529 + */
530 + register_console(&mcfrs_console);
531 +#endif
532 +}
533 --- /dev/null
534 +++ b/arch/m68k/coldfire/entry.S
535 @@ -0,0 +1,711 @@
536 +/*
537 + * arch/m68k/coldfire/entry.S
538 + *
539 + * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
540 + * Copyright (C) 1998 D. Jeff Dionne <jeff@lineo.ca>,
541 + * Kenneth Albanowski <kjahds@kjahds.com>,
542 + * Copyright (C) 2000 Lineo Inc. (www.lineo.com)
543 + * Copyright (C) 2004-2006 Macq Electronique SA. (www.macqel.com)
544 + * Matt Waddel Matt.Waddel@freescale.com
545 + * Kurt Mahan kmahan@freescale.com
546 + * Copyright Freescale Semiconductor, Inc. 2007
547 + *
548 + * Modify irq status in buserr -- (c) Copyright 2008, SYSTEM electronic Gmbh
549 + *
550 + * Based on:
551 + *
552 + * arch/m68knommu/platform/5307/entry.S &
553 + * arch/m68k/kernel/entry.S
554 + *
555 + * Copyright (C) 1991, 1992 Linus Torvalds
556 + *
557 + * This file is subject to the terms and conditions of the GNU General Public
558 + * License. See the file README.legal in the main directory of this archive
559 + * for more details.
560 + *
561 + * Linux/m68k support by Hamish Macdonald
562 + *
563 + * ColdFire support by Greg Ungerer (gerg@snapgear.com)
564 + * 5307 fixes by David W. Miller
565 + * linux 2.4 support David McCullough <davidm@snapgear.com>
566 + * Bug, speed and maintainability fixes by Philippe De Muyter <phdm@macqel.be>
567 + * Ported to mmu Coldfire by Matt Waddel
568 + */
569 +
570 +#include <linux/sys.h>
571 +#include <linux/linkage.h>
572 +#include <asm/cf_entry.h>
573 +#include <asm/errno.h>
574 +#include <asm/setup.h>
575 +#include <asm/segment.h>
576 +#include <asm/traps.h>
577 +#include <asm/unistd.h>
578 +
579 +/*
580 + * TASK_INFO:
581 + *
582 + * - TINFO_PREEMPT (struct thread_info / preempt_count)
583 + * Used to keep track of preemptability
584 + * - TINFO_FLAGS (struct thread_info / flags - include/asm-m68k/thread_info.h)
585 + * Various bit flags that are checked for scheduling/tracing
586 + * Bits 0-7 are checked every exception exit
587 + * 8-15 are checked every syscall exit
588 + *
589 + * TIF_SIGPENDING 6
590 + * TIF_NEED_RESCHED 7
591 + * TIF_DELAYED_TRACE 14
592 + * TIF_SYSCALL_TRACE 15
593 + * TIF_MEMDIE 16 (never checked here)
594 + */
595 +
596 +.bss
597 +
598 +sw_ksp:
599 +.long 0
600 +
601 +sw_usp:
602 +.long 0
603 +
604 +.text
605 +
606 +.globl system_call
607 +.globl buserr
608 +.globl trap
609 +.globl resume
610 +.globl ret_from_exception
611 +.globl ret_from_signal
612 +.globl sys_call_table
613 +.globl ret_from_interrupt
614 +.globl inthandler
615 +
616 +ENTRY(buserr)
617 +#ifdef CONFIG_COLDFIRE_FOO
618 + movew #0x2700,%sr /* lock interrupts */
619 +#endif
620 + SAVE_ALL_INT
621 +#ifdef CONFIG_COLDFIRE_FOO
622 + movew PT_SR(%sp),%d3 /* get original %sr */
623 + oril #0x2000,%d3 /* set supervisor mode in it */
624 + movew %d3,%sr /* recover irq state */
625 +#endif
626 + GET_CURRENT(%d0)
627 + movel %sp,%sp@- /* stack frame pointer argument */
628 + jsr buserr_c
629 + addql #4,%sp
630 + jra .Lret_from_exception
631 +
632 +ENTRY(trap)
633 + SAVE_ALL_INT
634 + GET_CURRENT(%d0)
635 + movel %sp,%sp@- /* stack frame pointer argument */
636 + jsr trap_c
637 + addql #4,%sp
638 + jra .Lret_from_exception
639 +
640 + /* After a fork we jump here directly from resume,
641 + %d1 contains the previous task schedule_tail */
642 +ENTRY(ret_from_fork)
643 + movel %d1,%sp@-
644 + jsr schedule_tail
645 + addql #4,%sp
646 + jra .Lret_from_exception
647 +
648 +do_trace_entry:
649 + movel #-ENOSYS,%d1 /* needed for strace */
650 + movel %d1,%sp@(PT_D0)
651 + subql #4,%sp
652 + SAVE_SWITCH_STACK
653 + jbsr syscall_trace
654 + RESTORE_SWITCH_STACK
655 + addql #4,%sp
656 + movel %sp@(PT_ORIG_D0),%d0
657 + cmpl #NR_syscalls,%d0
658 + jcs syscall
659 +badsys:
660 + movel #-ENOSYS,%d1
661 + movel %d1,%sp@(PT_D0)
662 + jra ret_from_exception
663 +
664 +do_trace_exit:
665 + subql #4,%sp
666 + SAVE_SWITCH_STACK
667 + jbsr syscall_trace
668 + RESTORE_SWITCH_STACK
669 + addql #4,%sp
670 + jra .Lret_from_exception
671 +
672 +ENTRY(ret_from_signal)
673 + RESTORE_SWITCH_STACK
674 + addql #4,%sp
675 + jra .Lret_from_exception
676 +
677 +ENTRY(system_call)
678 + SAVE_ALL_SYS
679 +
680 + GET_CURRENT(%d1)
681 + /* save top of frame */
682 + movel %sp,%curptr@(TASK_THREAD+THREAD_ESP0)
683 +
684 + /* syscall trace */
685 + tstb %curptr@(TASK_INFO+TINFO_FLAGS+2)
686 + jmi do_trace_entry /* SYSCALL_TRACE is set */
687 + cmpl #NR_syscalls,%d0
688 + jcc badsys
689 +syscall:
690 + movel #sys_call_table,%a0
691 + asll #2,%d0
692 + addl %d0,%a0
693 + movel %a0@,%a0
694 + jsr %a0@
695 + movel %d0,%sp@(PT_D0) /* save the return value */
696 +ret_from_syscall:
697 + movew %curptr@(TASK_INFO+TINFO_FLAGS+2),%d0
698 + jne syscall_exit_work /* flags set so process */
699 +1: RESTORE_ALL
700 +
701 +syscall_exit_work:
702 + btst #5,%sp@(PT_SR) /* check if returning to kernel */
703 + bnes 1b /* if so, skip resched, signals */
704 +
705 + btstl #15,%d0 /* check if SYSCALL_TRACE */
706 + jne do_trace_exit
707 + btstl #14,%d0 /* check if DELAYED_TRACE */
708 + jne do_delayed_trace
709 + btstl #6,%d0 /* check if SIGPENDING */
710 + jne do_signal_return
711 + pea resume_userspace
712 + jra schedule
713 +
714 +ENTRY(ret_from_exception)
715 +.Lret_from_exception:
716 + btst #5,%sp@(PT_SR) /* check if returning to kernel */
717 + bnes 1f /* if so, skip resched, signals */
718 + movel %d0,%sp@- /* Only allow interrupts when we are */
719 + move %sr,%d0 /* last one on the kernel stack, */
720 + andl #ALLOWINT,%d0 /* otherwise stack overflow can occur */
721 + move %d0,%sr /* during heavy interrupt load. */
722 + movel %sp@+,%d0
723 +
724 +resume_userspace:
725 + moveb %curptr@(TASK_INFO+TINFO_FLAGS+3),%d0
726 + jne exit_work /* SIGPENDING and/or NEED_RESCHED set */
727 +1: RESTORE_ALL
728 +
729 +exit_work:
730 + /* save top of frame */
731 + movel %sp,%curptr@(TASK_THREAD+THREAD_ESP0)
732 + btstl #6,%d0 /* check for SIGPENDING in flags */
733 + jne do_signal_return
734 + pea resume_userspace
735 + jra schedule
736 +
737 +do_signal_return:
738 + subql #4,%sp /* dummy return address */
739 + SAVE_SWITCH_STACK
740 + pea %sp@(SWITCH_STACK_SIZE)
741 + clrl %sp@-
742 + bsrl do_signal
743 + addql #8,%sp
744 + RESTORE_SWITCH_STACK
745 + addql #4,%sp
746 + jbra resume_userspace
747 +
748 +do_delayed_trace:
749 + bclr #7,%sp@(PT_SR) /* clear trace bit in SR */
750 + pea 1 /* send SIGTRAP */
751 + movel %curptr,%sp@-
752 + pea LSIGTRAP
753 + jbsr send_sig
754 + addql #8,%sp
755 + addql #4,%sp
756 + jbra resume_userspace
757 +
758 +/*
759 + * This is the interrupt handler (for all hardware interrupt
760 + * sources). It figures out the vector number and calls the appropriate
761 + * interrupt service routine directly.
762 + */
763 +ENTRY(inthandler)
764 + SAVE_ALL_INT
765 + GET_CURRENT(%d0)
766 + addql #1,%curptr@(TASK_INFO+TINFO_PREEMPT)
767 + /* put exception # in d0 */
768 + movel %sp@(PT_VECTOR),%d0
769 + swap %d0 /* extract bits 25:18 */
770 + lsrl #2,%d0
771 + andl #0x0ff,%d0
772 +
773 + movel %sp,%sp@-
774 + movel %d0,%sp@- /* put vector # on stack */
775 +auto_irqhandler_fixup = . + 2
776 + jbsr process_int /* process the IRQ */
777 + addql #8,%sp /* pop parameters off stack */
778 +
779 +ENTRY(ret_from_interrupt)
780 +ret_from_interrupt:
781 +
782 + subql #1,%curptr@(TASK_INFO+TINFO_PREEMPT)
783 + jeq ret_from_last_interrupt
784 +2: RESTORE_ALL
785 +
786 + ALIGN
787 +ret_from_last_interrupt:
788 + moveb %sp@(PT_SR),%d0
789 + andl #(~ALLOWINT>>8)&0xff,%d0
790 + jne 2b
791 +
792 + /* check if we need to do software interrupts */
793 + tstl irq_stat+CPUSTAT_SOFTIRQ_PENDING
794 + jeq .Lret_from_exception
795 + pea ret_from_exception
796 + jra do_softirq
797 +
798 +ENTRY(user_inthandler)
799 + SAVE_ALL_INT
800 + GET_CURRENT(%d0)
801 + addql #1,%curptr@(TASK_INFO+TINFO_PREEMPT)
802 + /* put exception # in d0 */
803 + movel %sp@(PT_VECTOR),%d0
804 +user_irqvec_fixup = . + 2
805 + swap %d0 /* extract bits 25:18 */
806 + lsrl #2,%d0
807 + andl #0x0ff,%d0
808 +
809 + movel %sp,%sp@-
810 + movel %d0,%sp@- /* put vector # on stack */
811 +user_irqhandler_fixup = . + 2
812 + jbsr process_int /* process the IRQ */
813 + addql #8,%sp /* pop parameters off stack */
814 +
815 + subql #1,%curptr@(TASK_INFO+TINFO_PREEMPT)
816 + jeq ret_from_last_interrupt
817 + RESTORE_ALL
818 +
819 +/* Handler for uninitialized and spurious interrupts */
820 +
821 +ENTRY(bad_inthandler)
822 + SAVE_ALL_INT
823 + GET_CURRENT(%d0)
824 + addql #1,%curptr@(TASK_INFO+TINFO_PREEMPT)
825 +
826 + movel %sp,%sp@-
827 + jsr handle_badint
828 + addql #4,%sp
829 +
830 + subql #1,%curptr@(TASK_INFO+TINFO_PREEMPT)
831 + jeq ret_from_last_interrupt
832 + RESTORE_ALL
833 +
834 +ENTRY(sys_fork)
835 + SAVE_SWITCH_STACK
836 + pea %sp@(SWITCH_STACK_SIZE)
837 + jbsr m68k_fork
838 + addql #4,%sp
839 + RESTORE_SWITCH_STACK
840 + rts
841 +
842 +ENTRY(sys_clone)
843 + SAVE_SWITCH_STACK
844 + pea %sp@(SWITCH_STACK_SIZE)
845 + jbsr m68k_clone
846 + addql #4,%sp
847 + RESTORE_SWITCH_STACK
848 + rts
849 +
850 +ENTRY(sys_vfork)
851 + SAVE_SWITCH_STACK
852 + pea %sp@(SWITCH_STACK_SIZE)
853 + jbsr m68k_vfork
854 + addql #4,%sp
855 + RESTORE_SWITCH_STACK
856 + rts
857 +
858 +ENTRY(sys_sigsuspend)
859 + SAVE_SWITCH_STACK
860 + pea %sp@(SWITCH_STACK_SIZE)
861 + jbsr do_sigsuspend
862 + addql #4,%sp
863 + RESTORE_SWITCH_STACK
864 + rts
865 +
866 +ENTRY(sys_rt_sigsuspend)
867 + SAVE_SWITCH_STACK
868 + pea %sp@(SWITCH_STACK_SIZE)
869 + jbsr do_rt_sigsuspend
870 + addql #4,%sp
871 + RESTORE_SWITCH_STACK
872 + rts
873 +
874 +ENTRY(sys_sigreturn)
875 + SAVE_SWITCH_STACK
876 + jbsr do_sigreturn
877 + RESTORE_SWITCH_STACK
878 + rts
879 +
880 +ENTRY(sys_rt_sigreturn)
881 + SAVE_SWITCH_STACK
882 + jbsr do_rt_sigreturn
883 + RESTORE_SWITCH_STACK
884 + rts
885 +
886 +resume:
887 + /*
888 + * Beware - when entering resume, prev (the current task) is
889 + * in a0, next (the new task) is in a1,so don't change these
890 + * registers until their contents are no longer needed.
891 + */
892 +
893 + /* save sr */
894 + movew %sr,%d0
895 + movew %d0,%a0@(TASK_THREAD+THREAD_SR)
896 +
897 + /* save usp */
898 + /* Save USP via %a1 (which is saved/restored from %d0) */
899 + movel %a1,%d0
900 + movel %usp,%a1
901 + movel %a1,%a0@(TASK_THREAD+THREAD_USP)
902 + movel %d0,%a1
903 +
904 + /* save non-scratch registers on stack */
905 + SAVE_SWITCH_STACK
906 +
907 + /* save current kernel stack pointer */
908 + movel %sp,%a0@(TASK_THREAD+THREAD_KSP)
909 +
910 + /* Return previous task in %d1 */
911 + movel %curptr,%d1
912 +
913 + /* switch to new task (a1 contains new task) */
914 + movel %a1,%curptr
915 +
916 + /* restore the kernel stack pointer */
917 + movel %a1@(TASK_THREAD+THREAD_KSP),%sp
918 +
919 + /* restore non-scratch registers */
920 + RESTORE_SWITCH_STACK
921 +
922 + /* restore user stack pointer */
923 + movel %a1@(TASK_THREAD+THREAD_USP),%a0
924 + movel %a0,%usp
925 +
926 + /* restore status register */
927 + movew %a1@(TASK_THREAD+THREAD_SR),%d0
928 + movew %d0,%sr
929 +
930 + rts
931 +
932 +.data
933 +ALIGN
934 +sys_call_table:
935 + .long sys_ni_syscall /* 0 - old "setup()" system call*/
936 + .long sys_exit
937 + .long sys_fork
938 + .long sys_read
939 + .long sys_write
940 + .long sys_open /* 5 */
941 + .long sys_close
942 + .long sys_waitpid
943 + .long sys_creat
944 + .long sys_link
945 + .long sys_unlink /* 10 */
946 + .long sys_execve
947 + .long sys_chdir
948 + .long sys_time
949 + .long sys_mknod
950 + .long sys_chmod /* 15 */
951 + .long sys_chown16
952 + .long sys_ni_syscall /* old break syscall holder */
953 + .long sys_stat
954 + .long sys_lseek
955 + .long sys_getpid /* 20 */
956 + .long sys_mount
957 + .long sys_oldumount
958 + .long sys_setuid16
959 + .long sys_getuid16
960 + .long sys_stime /* 25 */
961 + .long sys_ptrace
962 + .long sys_alarm
963 + .long sys_fstat
964 + .long sys_pause
965 + .long sys_utime /* 30 */
966 + .long sys_ni_syscall /* old stty syscall holder */
967 + .long sys_ni_syscall /* old gtty syscall holder */
968 + .long sys_access
969 + .long sys_nice
970 + .long sys_ni_syscall /* 35 */ /* old ftime syscall holder */
971 + .long sys_sync
972 + .long sys_kill
973 + .long sys_rename
974 + .long sys_mkdir
975 + .long sys_rmdir /* 40 */
976 + .long sys_dup
977 + .long sys_pipe
978 + .long sys_times
979 + .long sys_ni_syscall /* old prof syscall holder */
980 + .long sys_brk /* 45 */
981 + .long sys_setgid16
982 + .long sys_getgid16
983 + .long sys_signal
984 + .long sys_geteuid16
985 + .long sys_getegid16 /* 50 */
986 + .long sys_acct
987 + .long sys_umount /* recycled never used phys() */
988 + .long sys_ni_syscall /* old lock syscall holder */
989 + .long sys_ioctl
990 + .long sys_fcntl /* 55 */
991 + .long sys_ni_syscall /* old mpx syscall holder */
992 + .long sys_setpgid
993 + .long sys_ni_syscall /* old ulimit syscall holder */
994 + .long sys_ni_syscall
995 + .long sys_umask /* 60 */
996 + .long sys_chroot
997 + .long sys_ustat
998 + .long sys_dup2
999 + .long sys_getppid
1000 + .long sys_getpgrp /* 65 */
1001 + .long sys_setsid
1002 + .long sys_sigaction
1003 + .long sys_sgetmask
1004 + .long sys_ssetmask
1005 + .long sys_setreuid16 /* 70 */
1006 + .long sys_setregid16
1007 + .long sys_sigsuspend
1008 + .long sys_sigpending
1009 + .long sys_sethostname
1010 + .long sys_setrlimit /* 75 */
1011 + .long sys_old_getrlimit
1012 + .long sys_getrusage
1013 + .long sys_gettimeofday
1014 + .long sys_settimeofday
1015 + .long sys_getgroups16 /* 80 */
1016 + .long sys_setgroups16
1017 + .long old_select
1018 + .long sys_symlink
1019 + .long sys_lstat
1020 + .long sys_readlink /* 85 */
1021 + .long sys_uselib
1022 + .long sys_swapon
1023 + .long sys_reboot
1024 + .long old_readdir
1025 + .long old_mmap /* 90 */
1026 + .long sys_munmap
1027 + .long sys_truncate
1028 + .long sys_ftruncate
1029 + .long sys_fchmod
1030 + .long sys_fchown16 /* 95 */
1031 + .long sys_getpriority
1032 + .long sys_setpriority
1033 + .long sys_ni_syscall /* old profil syscall holder */
1034 + .long sys_statfs
1035 + .long sys_fstatfs /* 100 */
1036 + .long sys_ni_syscall /* ioperm for i386 */
1037 + .long sys_socketcall
1038 + .long sys_syslog
1039 + .long sys_setitimer
1040 + .long sys_getitimer /* 105 */
1041 + .long sys_newstat
1042 + .long sys_newlstat
1043 + .long sys_newfstat
1044 + .long sys_ni_syscall
1045 + .long sys_ni_syscall /* 110 */ /* iopl for i386 */
1046 + .long sys_vhangup
1047 + .long sys_ni_syscall /* obsolete idle() syscall */
1048 + .long sys_ni_syscall /* vm86old for i386 */
1049 + .long sys_wait4
1050 + .long sys_swapoff /* 115 */
1051 + .long sys_sysinfo
1052 + .long sys_ipc
1053 + .long sys_fsync
1054 + .long sys_sigreturn
1055 + .long sys_clone /* 120 */
1056 + .long sys_setdomainname
1057 + .long sys_newuname
1058 + .long sys_cacheflush /* modify_ldt for i386 */
1059 + .long sys_adjtimex
1060 + .long sys_mprotect /* 125 */
1061 + .long sys_sigprocmask
1062 + .long sys_ni_syscall /* old "create_module" */
1063 + .long sys_init_module
1064 + .long sys_delete_module
1065 + .long sys_ni_syscall /* 130 - old "get_kernel_syms" */
1066 + .long sys_quotactl
1067 + .long sys_getpgid
1068 + .long sys_fchdir
1069 + .long sys_bdflush
1070 + .long sys_sysfs /* 135 */
1071 + .long sys_personality
1072 + .long sys_ni_syscall /* for afs_syscall */
1073 + .long sys_setfsuid16
1074 + .long sys_setfsgid16
1075 + .long sys_llseek /* 140 */
1076 + .long sys_getdents
1077 + .long sys_select
1078 + .long sys_flock
1079 + .long sys_msync
1080 + .long sys_readv /* 145 */
1081 + .long sys_writev
1082 + .long sys_getsid
1083 + .long sys_fdatasync
1084 + .long sys_sysctl
1085 + .long sys_mlock /* 150 */
1086 + .long sys_munlock
1087 + .long sys_mlockall
1088 + .long sys_munlockall
1089 + .long sys_sched_setparam
1090 + .long sys_sched_getparam /* 155 */
1091 + .long sys_sched_setscheduler
1092 + .long sys_sched_getscheduler
1093 + .long sys_sched_yield
1094 + .long sys_sched_get_priority_max
1095 + .long sys_sched_get_priority_min /* 160 */
1096 + .long sys_sched_rr_get_interval
1097 + .long sys_nanosleep
1098 + .long sys_mremap
1099 + .long sys_setresuid16
1100 + .long sys_getresuid16 /* 165 */
1101 + .long sys_getpagesize
1102 + .long sys_ni_syscall /* old sys_query_module */
1103 + .long sys_poll
1104 + .long sys_nfsservctl
1105 + .long sys_setresgid16 /* 170 */
1106 + .long sys_getresgid16
1107 + .long sys_prctl
1108 + .long sys_rt_sigreturn
1109 + .long sys_rt_sigaction
1110 + .long sys_rt_sigprocmask /* 175 */
1111 + .long sys_rt_sigpending
1112 + .long sys_rt_sigtimedwait
1113 + .long sys_rt_sigqueueinfo
1114 + .long sys_rt_sigsuspend
1115 + .long sys_pread64 /* 180 */
1116 + .long sys_pwrite64
1117 + .long sys_lchown16;
1118 + .long sys_getcwd
1119 + .long sys_capget
1120 + .long sys_capset /* 185 */
1121 + .long sys_sigaltstack
1122 + .long sys_sendfile
1123 + .long sys_ni_syscall /* streams1 */
1124 + .long sys_ni_syscall /* streams2 */
1125 + .long sys_vfork /* 190 */
1126 + .long sys_getrlimit
1127 + .long sys_mmap2
1128 + .long sys_truncate64
1129 + .long sys_ftruncate64
1130 + .long sys_stat64 /* 195 */
1131 + .long sys_lstat64
1132 + .long sys_fstat64
1133 + .long sys_chown
1134 + .long sys_getuid
1135 + .long sys_getgid /* 200 */
1136 + .long sys_geteuid
1137 + .long sys_getegid
1138 + .long sys_setreuid
1139 + .long sys_setregid
1140 + .long sys_getgroups /* 205 */
1141 + .long sys_setgroups
1142 + .long sys_fchown
1143 + .long sys_setresuid
1144 + .long sys_getresuid
1145 + .long sys_setresgid /* 210 */
1146 + .long sys_getresgid
1147 + .long sys_lchown
1148 + .long sys_setuid
1149 + .long sys_setgid
1150 + .long sys_setfsuid /* 215 */
1151 + .long sys_setfsgid
1152 + .long sys_pivot_root
1153 + .long sys_ni_syscall
1154 + .long sys_ni_syscall
1155 + .long sys_getdents64 /* 220 */
1156 + .long sys_gettid
1157 + .long sys_tkill
1158 + .long sys_setxattr
1159 + .long sys_lsetxattr
1160 + .long sys_fsetxattr /* 225 */
1161 + .long sys_getxattr
1162 + .long sys_lgetxattr
1163 + .long sys_fgetxattr
1164 + .long sys_listxattr
1165 + .long sys_llistxattr /* 230 */
1166 + .long sys_flistxattr
1167 + .long sys_removexattr
1168 + .long sys_lremovexattr
1169 + .long sys_fremovexattr
1170 + .long sys_futex /* 235 */
1171 + .long sys_sendfile64
1172 + .long sys_mincore
1173 + .long sys_madvise
1174 + .long sys_fcntl64
1175 + .long sys_readahead /* 240 */
1176 + .long sys_io_setup
1177 + .long sys_io_destroy
1178 + .long sys_io_getevents
1179 + .long sys_io_submit
1180 + .long sys_io_cancel /* 245 */
1181 + .long sys_fadvise64
1182 + .long sys_exit_group
1183 + .long sys_lookup_dcookie
1184 + .long sys_epoll_create
1185 + .long sys_epoll_ctl /* 250 */
1186 + .long sys_epoll_wait
1187 + .long sys_remap_file_pages
1188 + .long sys_set_tid_address
1189 + .long sys_timer_create
1190 + .long sys_timer_settime /* 255 */
1191 + .long sys_timer_gettime
1192 + .long sys_timer_getoverrun
1193 + .long sys_timer_delete
1194 + .long sys_clock_settime
1195 + .long sys_clock_gettime /* 260 */
1196 + .long sys_clock_getres
1197 + .long sys_clock_nanosleep
1198 + .long sys_statfs64
1199 + .long sys_fstatfs64
1200 + .long sys_tgkill /* 265 */
1201 + .long sys_utimes
1202 + .long sys_fadvise64_64
1203 + .long sys_mbind
1204 + .long sys_get_mempolicy
1205 + .long sys_set_mempolicy /* 270 */
1206 + .long sys_mq_open
1207 + .long sys_mq_unlink
1208 + .long sys_mq_timedsend
1209 + .long sys_mq_timedreceive
1210 + .long sys_mq_notify /* 275 */
1211 + .long sys_mq_getsetattr
1212 + .long sys_waitid
1213 + .long sys_ni_syscall /* for sys_vserver */
1214 + .long sys_add_key
1215 + .long sys_request_key /* 280 */
1216 + .long sys_keyctl
1217 + .long sys_ioprio_set
1218 + .long sys_ioprio_get
1219 + .long sys_inotify_init
1220 + .long sys_inotify_add_watch /* 285 */
1221 + .long sys_inotify_rm_watch
1222 + .long sys_migrate_pages
1223 + .long sys_openat
1224 + .long sys_mkdirat
1225 + .long sys_mknodat /* 290 */
1226 + .long sys_fchownat
1227 + .long sys_futimesat
1228 + .long sys_fstatat64
1229 + .long sys_unlinkat
1230 + .long sys_renameat /* 295 */
1231 + .long sys_linkat
1232 + .long sys_symlinkat
1233 + .long sys_readlinkat
1234 + .long sys_fchmodat
1235 + .long sys_faccessat /* 300 */
1236 + .long sys_ni_syscall /* Reserved for pselect6 */
1237 + .long sys_ni_syscall /* Reserved for ppoll */
1238 + .long sys_unshare
1239 + .long sys_set_robust_list
1240 + .long sys_get_robust_list /* 305 */
1241 + .long sys_splice
1242 + .long sys_sync_file_range
1243 + .long sys_tee
1244 + .long sys_vmsplice
1245 + .long sys_move_pages /* 310 */
1246 +
1247 --- /dev/null
1248 +++ b/arch/m68k/coldfire/head.S
1249 @@ -0,0 +1,661 @@
1250 +/*
1251 + * head.S is the MMU enabled ColdFire specific initial boot code
1252 + *
1253 + * Ported to ColdFire by
1254 + * Matt Waddel Matt.Waddel@freescale.com
1255 + * Kurt Mahan kmahan@freescale.com
1256 + * Copyright Freescale Semiconductor, Inc. 2007, 2008
1257 + * Phys kernel mapping Copyright Daniel Krueger, SYSTEC electornic GmbH 2008
1258 + *
1259 + * This program is free software; you can redistribute it and/or modify
1260 + * it under the terms of the GNU General Public License as published by
1261 + * the Free Software Foundation; either version 2 of the License, or
1262 + * (at your option) any later version.
1263 + *
1264 + * Parts of this code came from arch/m68k/kernel/head.S
1265 + */
1266 +#include <linux/linkage.h>
1267 +#include <linux/init.h>
1268 +#include <asm/bootinfo.h>
1269 +#include <asm/setup.h>
1270 +#include <asm/entry.h>
1271 +#include <asm/pgtable.h>
1272 +#include <asm/page.h>
1273 +#include <asm/coldfire.h>
1274 +#include <asm/mcfuart.h>
1275 +#include <asm/cfcache.h>
1276 +
1277 +#define DEBUG
1278 +
1279 +.globl kernel_pg_dir
1280 +.globl availmem
1281 +.globl set_context
1282 +.globl set_fpga
1283 +
1284 +#ifdef DEBUG
1285 +/* When debugging use readable names for labels */
1286 +#ifdef __STDC__
1287 +#define L(name) .head.S.##name
1288 +#else
1289 +#define L(name) .head.S./**/name
1290 +#endif
1291 +#else
1292 +#ifdef __STDC__
1293 +#define L(name) .L##name
1294 +#else
1295 +#define L(name) .L/**/name
1296 +#endif
1297 +#endif
1298 +
1299 +/* The __INITDATA stuff is a no-op when ftrace or kgdb are turned on */
1300 +#ifndef __INITDATA
1301 +#define __INITDATA .data
1302 +#define __FINIT .previous
1303 +#endif
1304 +
1305 +#if CONFIG_SDRAM_BASE != PAGE_OFFSET
1306 +/*
1307 + * Kernel mapped to virtual ram address.
1308 + *
1309 + * M5445x:
1310 + * Data[0]: 0xF0000000 -> 0xFFFFFFFF System regs
1311 + * Data[1]: 0xA0000000 -> 0xAFFFFFFF PCI
1312 + * Code[0]: Not Mapped
1313 + * Code[1]: Not Mapped
1314 + *
1315 + * M547x/M548x
1316 + * Data[0]: 0xF0000000 -> 0xFFFFFFFF System regs
1317 + * Data[1]: Not Mapped
1318 + * Code[0]: Not Mapped
1319 + * Code[1]: Not Mapped
1320 + */
1321 +#if defined(CONFIG_M5445X)
1322 +#define ACR0_DEFAULT #0xF00FA048 /* System regs */
1323 +#define ACR1_DEFAULT #0xA00FA048 /* PCI */
1324 +#define ACR2_DEFAULT #0x00000000 /* Not Mapped */
1325 +#define ACR3_DEFAULT #0x00000000 /* Not Mapped */
1326 +#elif defined(CONFIG_M547X_8X)
1327 +#define ACR0_DEFAULT #0xF00FA048 /* System Regs */
1328 +#define ACR1_DEFAULT #0x00000000 /* Not Mapped */
1329 +#define ACR2_DEFAULT #0x00000000 /* Not Mapped */
1330 +#define ACR3_DEFAULT #0x00000000 /* Not Mapped */
1331 +#endif
1332 +
1333 +#else /* CONFIG_SDRAM_BASE = PAGE_OFFSET */
1334 +/*
1335 + * Kernel mapped to physical ram address.
1336 + *
1337 + * M5445x:
1338 + * Data[0]: 0xF0000000 -> 0xFFFFFFFF System regs
1339 + * Data[1]: 0x40000000 -> 0x4FFFFFFF SDRAM - uncached
1340 + * Code[0]: Not Mapped
1341 + * Code[1]: 0x40000000 -> 0x4FFFFFFF SDRAM - cached
1342 + *
1343 + * M547x/M548x
1344 + * Data[0]: 0xF0000000 -> 0xFFFFFFFF System regs
1345 + * Data[1]: 0x00000000 -> 0x0FFFFFFF SDRAM - uncached
1346 + * Code[0]: Not Mapped
1347 + * Code[1]: 0x00000000 -> 0x0FFFFFFF SDRAM - cached
1348 + */
1349 +#if defined(CONFIG_M5445X)
1350 +#define ACR0_DEFAULT #0xF00FA048 /* System Regs */
1351 +#define ACR1_DEFAULT #0x400FA048 /* SDRAM uncached */
1352 +#define ACR2_DEFAULT #0x00000000 /* Not mapped */
1353 +#define ACR3_DEFAULT #0x400FA008 /* SDRAM cached */
1354 +#elif defined(CONFIG_M547X_8X)
1355 +#define ACR0_DEFAULT #0xF00FA048 /* System Regs */
1356 +#define ACR1_DEFAULT #0x000FA048 /* SDRAM uncached */
1357 +#define ACR2_DEFAULT #0x00000000 /* Not mapped */
1358 +#define ACR3_DEFAULT #0x000FA008 /* SDRAM cached */
1359 +#endif
1360 +#endif
1361 +
1362 +/* Several macros to make the writing of subroutines easier:
1363 + * - func_start marks the beginning of the routine which setups the frame
1364 + * register and saves the registers, it also defines another macro
1365 + * to automatically restore the registers again.
1366 + * - func_return marks the end of the routine and simply calls the prepared
1367 + * macro to restore registers and jump back to the caller.
1368 + * - func_define generates another macro to automatically put arguments
1369 + * onto the stack call the subroutine and cleanup the stack again.
1370 + */
1371 +
1372 +.macro load_symbol_address symbol,register
1373 + movel #\symbol,\register
1374 +.endm
1375 +
1376 +.macro func_start name,saveregs,savesize,stack=0
1377 +L(\name):
1378 + linkw %a6,#-\stack
1379 + subal #(\savesize),%sp
1380 + moveml \saveregs,%sp@
1381 +.set stackstart,-\stack
1382 +
1383 +.macro func_return_\name
1384 + moveml %sp@,\saveregs
1385 + addal #(\savesize),%sp
1386 + unlk %a6
1387 + rts
1388 +.endm
1389 +.endm
1390 +
1391 +.macro func_return name
1392 + func_return_\name
1393 +.endm
1394 +
1395 +.macro func_call name
1396 + jbsr L(\name)
1397 +.endm
1398 +
1399 +.macro move_stack nr,arg1,arg2,arg3,arg4
1400 +.if \nr
1401 + move_stack "(\nr-1)",\arg2,\arg3,\arg4
1402 + movel \arg1,%sp@-
1403 +.endif
1404 +.endm
1405 +
1406 +.macro func_define name,nr=0
1407 +.macro \name arg1,arg2,arg3,arg4
1408 + move_stack \nr,\arg1,\arg2,\arg3,\arg4
1409 + func_call \name
1410 +.if \nr
1411 + lea %sp@(\nr*4),%sp
1412 +.endif
1413 +.endm
1414 +.endm
1415 +
1416 +func_define serial_putc,1
1417 +
1418 +.macro putc ch
1419 + pea \ch
1420 + func_call serial_putc
1421 + addql #4,%sp
1422 +.endm
1423 +
1424 +.macro dputc ch
1425 +#ifdef DEBUG
1426 + putc \ch
1427 +#endif
1428 +.endm
1429 +
1430 +func_define putn,1
1431 +
1432 +.macro dputn nr
1433 +#ifdef DEBUG
1434 + putn \nr
1435 +#endif
1436 +.endm
1437 +
1438 +#if CONFIG_SDRAM_BASE != PAGE_OFFSET
1439 +/*
1440 + mmu_map - creates a new TLB entry
1441 +
1442 + virt_addr Must be on proper boundary
1443 + phys_addr Must be on proper boundary
1444 + itlb MMUOR_ITLB if instruction TLB or 0
1445 + asid address space ID
1446 + shared_global MMUTR_SG if shared between different ASIDs or 0
1447 + size_code MMUDR_SZ1M 1 MB
1448 + MMUDR_SZ4K 4 KB
1449 + MMUDR_SZ8K 8 KB
1450 + MMUDR_SZ16M 16 MB
1451 + cache_mode MMUDR_INC instruction non-cacheable
1452 + MMUDR_IC instruction cacheable
1453 + MMUDR_DWT data writethrough
1454 + MMUDR_DCB data copyback
1455 + MMUDR_DNCP data non-cacheable, precise
1456 + MMUDR_DNCIP data non-cacheable, imprecise
1457 + super_prot MMUDR_SP if user mode generates exception or 0
1458 + readable MMUDR_R if permits read access (data TLB) or 0
1459 + writable MMUDR_W if permits write access (data TLB) or 0
1460 + executable MMUDR_X if permits execute access (instruction TLB) or 0
1461 + locked MMUDR_LK prevents TLB entry from being replaced or 0
1462 + temp_data_reg a data register to use for temporary values
1463 +*/
1464 +.macro mmu_map virt_addr,phys_addr,itlb,asid,shared_global,size_code,cache_mode,super_prot,readable,writable,executable,locked,temp_data_reg
1465 + /* Set up search of TLB. */
1466 + movel #(\virt_addr+1), \temp_data_reg
1467 + movel \temp_data_reg, MMUAR
1468 + /* Search. */
1469 + movel #(MMUOR_STLB + MMUOR_ADR +\itlb), \temp_data_reg
1470 + movew \temp_data_reg, (MMUOR)
1471 + /* Set up tag value. */
1472 + movel #(\virt_addr + \asid + \shared_global + MMUTR_V), \temp_data_reg
1473 + movel \temp_data_reg, MMUTR
1474 + /* Set up data value. */
1475 + movel #(\phys_addr + \size_code + \cache_mode + \super_prot + \readable + \writable + \executable + \locked), \temp_data_reg
1476 + movel \temp_data_reg, MMUDR
1477 + /* Save it. */
1478 + movel #(MMUOR_ACC + MMUOR_UAA + \itlb), \temp_data_reg
1479 + movew \temp_data_reg, (MMUOR)
1480 +.endm /* mmu_map */
1481 +
1482 +.macro mmu_unmap virt_addr,itlb,temp_data_reg
1483 + /* Set up search of TLB. */
1484 + movel #(\virt_addr+1), \temp_data_reg
1485 + movel \temp_data_reg, MMUAR
1486 + /* Search. */
1487 + movel #(MMUOR_STLB + MMUOR_ADR +\itlb), \temp_data_reg
1488 + movew \temp_data_reg, (MMUOR)
1489 + /* Test for hit. */
1490 + movel MMUSR,\temp_data_reg
1491 + btst #MMUSR_HITN,\temp_data_reg
1492 + beq 1f
1493 + /* Read the TLB. */
1494 + movel #(MMUOR_RW + MMUOR_ACC +\itlb), \temp_data_reg
1495 + movew \temp_data_reg, (MMUOR)
1496 + movel MMUSR,\temp_data_reg
1497 + /* Set up tag value. */
1498 + movel #0, \temp_data_reg
1499 + movel \temp_data_reg, MMUTR
1500 + /* Set up data value. */
1501 + movel #0, \temp_data_reg
1502 + movel \temp_data_reg, MMUDR
1503 + /* Save it. */
1504 + movel #(MMUOR_ACC + MMUOR_UAA + \itlb), \temp_data_reg
1505 + movew \temp_data_reg, (MMUOR)
1506 +1:
1507 +.endm /* mmu_unmap */
1508 +#endif /* CONFIG_SDRAM_BASE != PAGE_OFFSET */
1509 +
1510 +/* .text */
1511 +.section ".text.head","ax"
1512 +ENTRY(_stext)
1513 +/* Version numbers of the bootinfo interface -- if we later pass info
1514 + * from boot ROM we might want to put something real here.
1515 + *
1516 + * The area from _stext to _start will later be used as kernel pointer table
1517 + */
1518 + bras 1f /* Jump over bootinfo version numbers */
1519 +
1520 + .long BOOTINFOV_MAGIC
1521 + .long 0
1522 +#if CONFIG_SDRAM_BASE != PAGE_OFFSET
1523 +1: jmp __start-(0xc0000000-CONFIG_SDRAM_BASE)
1524 +#else
1525 +1: jmp __start
1526 +#endif
1527 +
1528 +.equ kernel_pg_dir,_stext
1529 +.equ .,_stext+0x1000
1530 +
1531 +ENTRY(_start)
1532 + jra __start
1533 +__INIT
1534 +ENTRY(__start)
1535 +/* Save the location of u-boot info - cmd line, bd_info, etc. */
1536 + movel %a7,%a4 /* Don't use %a4 before cf_early_init */
1537 + addl #0x00000004,%a4 /* offset past top */
1538 + addl #(PAGE_OFFSET-CONFIG_SDRAM_BASE),%a4 /* high mem offset */
1539 +
1540 +/* Setup initial stack pointer */
1541 + movel #CONFIG_SDRAM_BASE+0x1000,%sp
1542 +
1543 +/* Setup usp */
1544 + subl %a0,%a0
1545 + movel %a0,%usp
1546 +
1547 +#if defined(CONFIG_M5445X)
1548 + movel #0x80000000, %d0
1549 + movec %d0, %rambar1
1550 +#elif defined(CONFIG_M547X_8X)
1551 + movel #MCF_MBAR, %d0
1552 + movec %d0, %mbar
1553 + move.l #(MCF_RAMBAR0 + 0x21), %d0
1554 + movec %d0, %rambar0
1555 + move.l #(MCF_RAMBAR1 + 0x21), %d0
1556 + movec %d0, %rambar1
1557 +#endif
1558 +
1559 + movew #0x2700,%sr
1560 +
1561 +/* reset cache */
1562 + movel #(CF_CACR_ICINVA + CF_CACR_DCINVA),%d0
1563 + movecl %d0,%cacr
1564 +
1565 + movel #(MMU_BASE+1),%d0
1566 + movecl %d0,%mmubar
1567 + movel #MMUOR_CA,%a0 /* Clear tlb entries */
1568 + movew %a0,(MMUOR)
1569 + movel #(MMUOR_CA + MMUOR_ITLB),%a0 /* Use ITLB for searches */
1570 + movew %a0,(MMUOR)
1571 + movel #0,%a0 /* Clear Addr Space User ID */
1572 + movecl %a0,%asid
1573 +
1574 +/* setup ACRs */
1575 + movel ACR0_DEFAULT, %d0 /* ACR0 (DATA) setup */
1576 + movec %d0, %acr0
1577 + nop
1578 + movel ACR1_DEFAULT, %d0 /* ACR1 (DATA) setup */
1579 + movec %d0, %acr1
1580 + nop
1581 + movel ACR2_DEFAULT, %d0 /* ACR2 (CODE) setup */
1582 + movec %d0, %acr2
1583 + nop
1584 + movel ACR3_DEFAULT, %d0 /* ACR3 (CODE) setup */
1585 + movec %d0, %acr3
1586 + nop
1587 +
1588 + /* If you change the memory size to another value make a matching
1589 + change in paging_init(cf-mmu.c) to zones_size[]. */
1590 +
1591 +#if CONFIG_SDRAM_BASE != PAGE_OFFSET
1592 +#if defined(CONFIG_M5445X)
1593 + /* Map 256MB as code */
1594 + mmu_map (PAGE_OFFSET+0*0x1000000), (PHYS_OFFSET+0*0x1000000), \
1595 + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
1596 + 0, 0, MMUDR_X, MMUDR_LK, %d0
1597 + mmu_map (PAGE_OFFSET+1*0x1000000), (PHYS_OFFSET+1*0x1000000), \
1598 + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
1599 + 0, 0, MMUDR_X, MMUDR_LK, %d0
1600 + mmu_map (PAGE_OFFSET+2*0x1000000), (PHYS_OFFSET+2*0x1000000), \
1601 + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
1602 + 0, 0, MMUDR_X, MMUDR_LK, %d0
1603 + mmu_map (PAGE_OFFSET+3*0x1000000), (PHYS_OFFSET+3*0x1000000), \
1604 + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
1605 + 0, 0, MMUDR_X, MMUDR_LK, %d0
1606 + mmu_map (PAGE_OFFSET+4*0x1000000), (PHYS_OFFSET+4*0x1000000), \
1607 + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
1608 + 0, 0, MMUDR_X, MMUDR_LK, %d0
1609 + mmu_map (PAGE_OFFSET+5*0x1000000), (PHYS_OFFSET+5*0x1000000), \
1610 + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
1611 + 0, 0, MMUDR_X, MMUDR_LK, %d0
1612 + mmu_map (PAGE_OFFSET+6*0x1000000), (PHYS_OFFSET+6*0x1000000), \
1613 + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
1614 + 0, 0, MMUDR_X, MMUDR_LK, %d0
1615 + mmu_map (PAGE_OFFSET+7*0x1000000), (PHYS_OFFSET+7*0x1000000), \
1616 + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
1617 + 0, 0, MMUDR_X, MMUDR_LK, %d0
1618 + mmu_map (PAGE_OFFSET+8*0x1000000), (PHYS_OFFSET+8*0x1000000), \
1619 + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
1620 + 0, 0, MMUDR_X, MMUDR_LK, %d0
1621 + mmu_map (PAGE_OFFSET+9*0x1000000), (PHYS_OFFSET+9*0x1000000), \
1622 + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
1623 + 0, 0, MMUDR_X, MMUDR_LK, %d0
1624 + mmu_map (PAGE_OFFSET+10*0x1000000), (PHYS_OFFSET+10*0x1000000), \
1625 + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
1626 + 0, 0, MMUDR_X, MMUDR_LK, %d0
1627 + mmu_map (PAGE_OFFSET+11*0x1000000), (PHYS_OFFSET+11*0x1000000), \
1628 + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
1629 + 0, 0, MMUDR_X, MMUDR_LK, %d0
1630 + mmu_map (PAGE_OFFSET+12*0x1000000), (PHYS_OFFSET+12*0x1000000), \
1631 + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
1632 + 0, 0, MMUDR_X, MMUDR_LK, %d0
1633 + mmu_map (PAGE_OFFSET+13*0x1000000), (PHYS_OFFSET+13*0x1000000), \
1634 + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
1635 + 0, 0, MMUDR_X, MMUDR_LK, %d0
1636 + mmu_map (PAGE_OFFSET+14*0x1000000), (PHYS_OFFSET+14*0x1000000), \
1637 + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
1638 + 0, 0, MMUDR_X, MMUDR_LK, %d0
1639 + mmu_map (PAGE_OFFSET+15*0x1000000), (PHYS_OFFSET+15*0x1000000), \
1640 + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
1641 + 0, 0, MMUDR_X, MMUDR_LK, %d0
1642 +
1643 + /* Map 256MB as data also */
1644 + mmu_map (PAGE_OFFSET+0*0x1000000), (PHYS_OFFSET+0*0x1000000), 0, 0, \
1645 + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
1646 + 0, MMUDR_LK, %d0
1647 + mmu_map (PAGE_OFFSET+1*0x1000000), (PHYS_OFFSET+1*0x1000000), 0, 0, \
1648 + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
1649 + 0, MMUDR_LK, %d0
1650 + mmu_map (PAGE_OFFSET+2*0x1000000), (PHYS_OFFSET+2*0x1000000), 0, 0, \
1651 + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
1652 + 0, MMUDR_LK, %d0
1653 + mmu_map (PAGE_OFFSET+3*0x1000000), (PHYS_OFFSET+3*0x1000000), 0, 0, \
1654 + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
1655 + 0, MMUDR_LK, %d0
1656 + mmu_map (PAGE_OFFSET+4*0x1000000), (PHYS_OFFSET+4*0x1000000), 0, 0, \
1657 + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
1658 + 0, MMUDR_LK, %d0
1659 + mmu_map (PAGE_OFFSET+5*0x1000000), (PHYS_OFFSET+5*0x1000000), 0, 0, \
1660 + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
1661 + 0, MMUDR_LK, %d0
1662 + mmu_map (PAGE_OFFSET+6*0x1000000), (PHYS_OFFSET+6*0x1000000), 0, 0, \
1663 + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
1664 + 0, MMUDR_LK, %d0
1665 + mmu_map (PAGE_OFFSET+7*0x1000000), (PHYS_OFFSET+7*0x1000000), 0, 0, \
1666 + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
1667 + 0, MMUDR_LK, %d0
1668 + mmu_map (PAGE_OFFSET+8*0x1000000), (PHYS_OFFSET+8*0x1000000), 0, 0, \
1669 + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
1670 + 0, MMUDR_LK, %d0
1671 + mmu_map (PAGE_OFFSET+9*0x1000000), (PHYS_OFFSET+9*0x1000000), 0, 0, \
1672 + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
1673 + 0, MMUDR_LK, %d0
1674 + mmu_map (PAGE_OFFSET+10*0x1000000), (PHYS_OFFSET+10*0x1000000), 0, 0, \
1675 + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
1676 + 0, MMUDR_LK, %d0
1677 + mmu_map (PAGE_OFFSET+11*0x1000000), (PHYS_OFFSET+11*0x1000000), 0, 0, \
1678 + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
1679 + 0, MMUDR_LK, %d0
1680 + mmu_map (PAGE_OFFSET+12*0x1000000), (PHYS_OFFSET+12*0x1000000), 0, 0, \
1681 + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
1682 + 0, MMUDR_LK, %d0
1683 + mmu_map (PAGE_OFFSET+13*0x1000000), (PHYS_OFFSET+13*0x1000000), 0, 0, \
1684 + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
1685 + 0, MMUDR_LK, %d0
1686 + mmu_map (PAGE_OFFSET+14*0x1000000), (PHYS_OFFSET+14*0x1000000), 0, 0, \
1687 + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
1688 + 0, MMUDR_LK, %d0
1689 + mmu_map (PAGE_OFFSET+15*0x1000000), (PHYS_OFFSET+15*0x1000000), 0, 0, \
1690 + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
1691 + 0, MMUDR_LK, %d0
1692 +
1693 + /* Map ATA registers -- sacrifice a data TLB due to the hw design */
1694 + mmu_map (0x90000000), (0x90000000), 0, 0, \
1695 + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
1696 + 0, MMUDR_LK, %d0
1697 +
1698 +#elif defined(CONFIG_M547X_8X)
1699 +
1700 + /* Map first 8 MB as code */
1701 + mmu_map (PAGE_OFFSET+0*1024*1024), (0*1024*1024), MMUOR_ITLB, 0, \
1702 + MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \
1703 + MMUDR_LK, %d0
1704 + mmu_map (PAGE_OFFSET+1*1024*1024), (1*1024*1024), MMUOR_ITLB, 0, \
1705 + MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \
1706 + MMUDR_LK, %d0
1707 + mmu_map (PAGE_OFFSET+2*1024*1024), (2*1024*1024), MMUOR_ITLB, 0, \
1708 + MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \
1709 + MMUDR_LK, %d0
1710 + mmu_map (PAGE_OFFSET+3*1024*1024), (3*1024*1024), MMUOR_ITLB, 0, \
1711 + MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \
1712 + MMUDR_LK, %d0
1713 + mmu_map (PAGE_OFFSET+4*1024*1024), (4*1024*1024), MMUOR_ITLB, 0, \
1714 + MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \
1715 + MMUDR_LK, %d0
1716 + mmu_map (PAGE_OFFSET+5*1024*1024), (5*1024*1024), MMUOR_ITLB, 0, \
1717 + MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \
1718 + MMUDR_LK, %d0
1719 + mmu_map (PAGE_OFFSET+6*1024*1024), (6*1024*1024), MMUOR_ITLB, 0, \
1720 + MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \
1721 + MMUDR_LK, %d0
1722 + mmu_map (PAGE_OFFSET+7*1024*1024), (7*1024*1024), MMUOR_ITLB, 0, \
1723 + MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \
1724 + MMUDR_LK, %d0
1725 +
1726 + /* Map first 8 MB as data */
1727 + mmu_map (PAGE_OFFSET+0*1024*1024), (0*1024*1024), 0, 0, \
1728 + MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
1729 + MMUDR_W, 0, MMUDR_LK, %d0
1730 + mmu_map (PAGE_OFFSET+1*1024*1024), (1*1024*1024), 0, 0, \
1731 + MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
1732 + MMUDR_W, 0, MMUDR_LK, %d0
1733 + mmu_map (PAGE_OFFSET+2*1024*1024), (2*1024*1024), 0, 0, \
1734 + MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
1735 + MMUDR_W, 0, MMUDR_LK, %d0
1736 + mmu_map (PAGE_OFFSET+3*1024*1024), (3*1024*1024), 0, 0, \
1737 + MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
1738 + MMUDR_W, 0, MMUDR_LK, %d0
1739 + mmu_map (PAGE_OFFSET+4*1024*1024), (4*1024*1024), 0, 0, \
1740 + MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
1741 + MMUDR_W, 0, MMUDR_LK, %d0
1742 + mmu_map (PAGE_OFFSET+5*1024*1024), (5*1024*1024), 0, 0, \
1743 + MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
1744 + MMUDR_W, 0, MMUDR_LK, %d0
1745 + mmu_map (PAGE_OFFSET+6*1024*1024), (6*1024*1024), 0, 0, \
1746 + MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
1747 + MMUDR_W, 0, MMUDR_LK, %d0
1748 + mmu_map (PAGE_OFFSET+7*1024*1024), (7*1024*1024), 0, 0, \
1749 + MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
1750 + MMUDR_W, 0, MMUDR_LK, %d0
1751 +#endif
1752 + /*
1753 + * Do unity mapping to enable the MMU. Map first chunk of memory
1754 + * in place as code/data. The TLBs will be deleted after the MMU is
1755 + * enabled and we are executing in high memory.
1756 + */
1757 +
1758 +#if defined(CONFIG_M5445X)
1759 + /* Map first 16 MB as code */
1760 + mmu_map (PHYS_OFFSET+0*0x1000000), (PHYS_OFFSET+0*0x1000000), \
1761 + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_INC, MMUDR_SP, 0, \
1762 + 0, MMUDR_X, 0, %d0
1763 + /* Map first 16 MB as data too */
1764 + mmu_map (PHYS_OFFSET+0*0x1000000), (PHYS_OFFSET+0*0x1000000), 0, 0, \
1765 + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
1766 + 0, 0, %d0
1767 +#elif defined(CONFIG_M547X_8X)
1768 + /* Map first 4 MB as code */
1769 + mmu_map (0*1024*1024), (0*1024*1024), MMUOR_ITLB, 0, \
1770 + MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, \
1771 + MMUDR_X, 0, %d0
1772 + mmu_map (1*1024*1024), (1*1024*1024), MMUOR_ITLB, 0, \
1773 + MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, \
1774 + MMUDR_X, 0, %d0
1775 + mmu_map (2*1024*1024), (2*1024*1024), MMUOR_ITLB, 0, \
1776 + MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, \
1777 + MMUDR_X, 0, %d0
1778 + mmu_map (3*1024*1024), (3*1024*1024), MMUOR_ITLB, 0, \
1779 + MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, \
1780 + MMUDR_X, 0, %d0
1781 +
1782 + /* Map first 4 MB as data too */
1783 + mmu_map (0*1024*1024), (0*1024*1024), 0, 0, \
1784 + MMUTR_SG, MMUDR_SZ1M, MMUDR_DCB, MMUDR_SP, MMUDR_R, \
1785 + MMUDR_W, 0, 0, %d0
1786 + mmu_map (1*1024*1024), (1*1024*1024), 0, 0, \
1787 + MMUTR_SG, MMUDR_SZ1M, MMUDR_DCB, MMUDR_SP, MMUDR_R, \
1788 + MMUDR_W, 0, 0, %d0
1789 + mmu_map (2*1024*1024), (2*1024*1024), 0, 0, \
1790 + MMUTR_SG, MMUDR_SZ1M, MMUDR_DCB, MMUDR_SP, MMUDR_R, \
1791 + MMUDR_W, 0, 0, %d0
1792 + mmu_map (3*1024*1024), (3*1024*1024), 0, 0, \
1793 + MMUTR_SG, MMUDR_SZ1M, MMUDR_DCB, MMUDR_SP, MMUDR_R, \
1794 + MMUDR_W, 0, 0, %d0
1795 +#endif
1796 +#endif /* CONFIG_SDRAM_BASE != PAGE_OFFSET */
1797 +
1798 + /* Turn on MMU */
1799 + movel #(MMUCR_EN),%a0
1800 + movel %a0,MMUCR
1801 + nop /* This synchs the pipeline after a write to MMUCR */
1802 +
1803 + movel #__running_high,%a0 /* Get around PC-relative addressing. */
1804 + jmp %a0@
1805 +
1806 +ENTRY(__running_high)
1807 + load_symbol_address _stext,%sp
1808 + movel L(memory_start),%a0
1809 + movel %a0,availmem
1810 + load_symbol_address L(phys_kernel_start),%a0
1811 + load_symbol_address _stext,%a1
1812 + subl #_stext,%a1
1813 + addl #PAGE_OFFSET,%a1
1814 + movel %a1,%a0@
1815 +
1816 +/* zero bss */
1817 + lea _sbss,%a0
1818 + lea _ebss,%a1
1819 + clrl %d0
1820 +_loop_bss:
1821 + movel %d0,(%a0)+
1822 + cmpl %a0,%a1
1823 + bne _loop_bss
1824 +
1825 + /* Unmap unity mappings */
1826 +#if CONFIG_SDRAM_BASE != PAGE_OFFSET
1827 +#if defined(CONFIG_M5445X)
1828 + mmu_unmap (PHYS_OFFSET+0*0x1000000), MMUOR_ITLB, %d0
1829 + mmu_unmap (PHYS_OFFSET+0*0x1000000), 0, %d0
1830 +#elif defined(CONFIG_M547X_8X)
1831 + mmu_unmap (PHYS_OFFSET+0*0x1000000), MMUOR_ITLB, %d0
1832 + mmu_unmap (PHYS_OFFSET+1*0x1000000), MMUOR_ITLB, %d0
1833 + mmu_unmap (PHYS_OFFSET+2*0x1000000), MMUOR_ITLB, %d0
1834 + mmu_unmap (PHYS_OFFSET+3*0x1000000), MMUOR_ITLB, %d0
1835 + mmu_unmap (PHYS_OFFSET+0*0x1000000), 0, %d0
1836 + mmu_unmap (PHYS_OFFSET+1*0x1000000), 0, %d0
1837 + mmu_unmap (PHYS_OFFSET+2*0x1000000), 0, %d0
1838 + mmu_unmap (PHYS_OFFSET+3*0x1000000), 0, %d0
1839 +#endif
1840 +#endif /* CONFIG_SDRAM_BASE != PAGE_OFFSET */
1841 +
1842 +/* Setup initial stack pointer */
1843 + lea init_task,%a2
1844 + lea init_thread_union+THREAD_SIZE,%sp
1845 + subl %a6,%a6 /* clear a6 for gdb */
1846 +
1847 +#ifdef CONFIG_MCF_USER_HALT
1848 +/* Setup debug control reg to allow halts from user space */
1849 + lea wdbg_uhe,%a0
1850 + wdebug (%a0)
1851 +#endif
1852 +
1853 + movel %a4,uboot_info_stk /* save uboot info to variable */
1854 + jsr cf_early_init
1855 + jmp start_kernel
1856 +
1857 +.section ".text.head","ax"
1858 +set_context:
1859 +func_start set_context,%d0,(1*4)
1860 + movel 12(%sp),%d0
1861 + movec %d0,%asid
1862 +func_return set_context
1863 +
1864 +#ifdef CONFIG_M5445X
1865 +/*
1866 + * set_fpga(addr,val) on the M5445X
1867 + *
1868 + * Map in 0x00000000 -> 0x0fffffff and then do the write.
1869 + */
1870 +set_fpga:
1871 +#if 0
1872 + movew %sr,%d1
1873 + movew #0x2700,%sr
1874 + movel ACR0_FPGA, %d0
1875 + movec %d0, %acr0
1876 + nop
1877 + moveal 4(%sp),%a0
1878 + movel 8(%sp),%a0@
1879 + movel ACR0_DEFAULT, %d0
1880 + movec %d0, %acr0
1881 + nop
1882 + movew %d1,%sr
1883 +#endif
1884 + rts
1885 +#endif
1886 +
1887 + .data
1888 + .align 4
1889 +
1890 +availmem:
1891 + .long 0
1892 +L(phys_kernel_start):
1893 + .long PAGE_OFFSET
1894 +L(kernel_end):
1895 + .long 0
1896 +L(memory_start):
1897 + .long PAGE_OFFSET_RAW
1898 +
1899 +#ifdef CONFIG_MCF_USER_HALT
1900 +/*
1901 + * Enable User Halt Enable in the debug control register.
1902 + */
1903 +wdbg_uhe:
1904 + .word 0x2c80 /* DR0 */
1905 + .word 0x00b0 /* 31:16 */
1906 + .word 0x0400 /* 15:0 -- enable UHE */
1907 + .word 0x0000 /* unused */
1908 +#endif
1909 +
1910 +
1911 --- /dev/null
1912 +++ b/arch/m68k/coldfire/ints.c
1913 @@ -0,0 +1,463 @@
1914 +/*
1915 + * linux/arch/m68k/coldfire/ints.c -- General interrupt handling code
1916 + *
1917 + * Copyright (C) 1999-2002 Greg Ungerer (gerg@snapgear.com)
1918 + * Copyright (C) 1998 D. Jeff Dionne <jeff@lineo.ca>,
1919 + * Kenneth Albanowski <kjahds@kjahds.com>,
1920 + * Copyright (C) 2000 Lineo Inc. (www.lineo.com)
1921 + *
1922 + * Copyright Freescale Semiconductor, Inc. 2007, 2008
1923 + * Kurt Mahan kmahan@freescale.com
1924 + * Matt Waddel Matt.Waddel@freescale.com
1925 + *
1926 + * Based on:
1927 + * linux/arch/m68k/kernel/ints.c &
1928 + * linux/arch/m68knommu/5307/ints.c
1929 + *
1930 + * This file is subject to the terms and conditions of the GNU General Public
1931 + * License. See the file COPYING in the main directory of this archive
1932 + * for more details.
1933 + */
1934 +
1935 +#include <linux/module.h>
1936 +#include <linux/types.h>
1937 +#include <linux/init.h>
1938 +#include <linux/sched.h>
1939 +#include <linux/kernel_stat.h>
1940 +#include <linux/errno.h>
1941 +#include <linux/seq_file.h>
1942 +#include <linux/interrupt.h>
1943 +
1944 +#include <asm/system.h>
1945 +#include <asm/irq.h>
1946 +#include <asm/traps.h>
1947 +#include <asm/page.h>
1948 +#include <asm/machdep.h>
1949 +#include <asm/irq_regs.h>
1950 +
1951 +#include <asm/mcfsim.h>
1952 +
1953 +/*
1954 + * IRQ Handler lists.
1955 + */
1956 +static struct irq_node *irq_list[SYS_IRQS];
1957 +static struct irq_controller *irq_controller[SYS_IRQS];
1958 +static int irq_depth[SYS_IRQS];
1959 +
1960 +/*
1961 + * IRQ Controller
1962 + */
1963 +#if defined(CONFIG_M5445X)
1964 +void m5445x_irq_enable(unsigned int irq);
1965 +void m5445x_irq_disable(unsigned int irq);
1966 +static struct irq_controller m5445x_irq_controller = {
1967 + .name = "M5445X",
1968 + .lock = SPIN_LOCK_UNLOCKED,
1969 + .enable = m5445x_irq_enable,
1970 + .disable = m5445x_irq_disable,
1971 +};
1972 +#elif defined(CONFIG_M547X_8X)
1973 +void m547x_8x_irq_enable(unsigned int irq);
1974 +void m547x_8x_irq_disable(unsigned int irq);
1975 +static struct irq_controller m547x_8x_irq_controller = {
1976 + .name = "M547X_8X",
1977 + .lock = SPIN_LOCK_UNLOCKED,
1978 + .enable = m547x_8x_irq_enable,
1979 + .disable = m547x_8x_irq_disable,
1980 +};
1981 +#else
1982 +# error No IRQ controller defined
1983 +#endif
1984 +
1985 +#define POOL_SIZE SYS_IRQS
1986 +static struct irq_node pool[POOL_SIZE];
1987 +static struct irq_node *get_irq_node(void);
1988 +
1989 +/* The number of spurious interrupts */
1990 +unsigned int num_spurious;
1991 +asmlinkage void handle_badint(struct pt_regs *regs);
1992 +
1993 +/*
1994 + * void init_IRQ(void)
1995 + *
1996 + * This function should be called during kernel startup to initialize
1997 + * the IRQ handling routines.
1998 + */
1999 +void __init init_IRQ(void)
2000 +{
2001 + int i;
2002 +
2003 +#if defined(CONFIG_M5445X)
2004 + for (i = 0; i < SYS_IRQS; i++)
2005 + irq_controller[i] = &m5445x_irq_controller;
2006 +#elif defined(CONFIG_M547X_8X)
2007 + for (i = 0; i < SYS_IRQS; i++)
2008 + irq_controller[i] = &m547x_8x_irq_controller;
2009 +#endif
2010 +}
2011 +
2012 +/*
2013 + * process_int(unsigned long vec, struct pt_regs *fp)
2014 + *
2015 + * Process an interrupt. Called from entry.S.
2016 + */
2017 +asmlinkage void process_int(unsigned long vec, struct pt_regs *fp)
2018 +{
2019 + struct pt_regs *old_regs;
2020 + struct irq_node *node;
2021 + old_regs = set_irq_regs(fp);
2022 + kstat_cpu(0).irqs[vec]++;
2023 +
2024 + node = irq_list[vec];
2025 + if (!node)
2026 + handle_badint(fp);
2027 + else {
2028 + do {
2029 + node->handler(vec, node->dev_id);
2030 + node = node->next;
2031 + } while (node);
2032 + }
2033 +
2034 + set_irq_regs(old_regs);
2035 +}
2036 +
2037 +/*
2038 + * show_interrupts( struct seq_file *p, void *v)
2039 + *
2040 + * Called to show all the current interrupt information.
2041 + */
2042 +int show_interrupts(struct seq_file *p, void *v)
2043 +{
2044 + struct irq_controller *contr;
2045 + struct irq_node *node;
2046 + int i = *(loff_t *) v;
2047 +
2048 + if ((i < NR_IRQS) && (irq_list[i])) {
2049 + contr = irq_controller[i];
2050 + node = irq_list[i];
2051 + seq_printf(p, "%-8s %3u: %10u %s", contr->name, i,
2052 + kstat_cpu(0).irqs[i], node->devname);
2053 + while ((node = node->next))
2054 + seq_printf(p, ", %s", node->devname);
2055 +
2056 + seq_printf(p, "\n");
2057 + }
2058 +
2059 + return 0;
2060 +}
2061 +
2062 +/*
2063 + * get_irq_node(void)
2064 + *
2065 + * Get an irq node from the pool.
2066 + */
2067 +struct irq_node *get_irq_node(void)
2068 +{
2069 + struct irq_node *p = pool;
2070 + int i;
2071 +
2072 + for (i = 0; i < POOL_SIZE; i++, p++) {
2073 + if (!p->handler) {
2074 + memset(p, 0, sizeof(struct irq_node));
2075 + return p;
2076 + }
2077 + }
2078 + printk(KERN_INFO "%s(%s:%d): No more irq nodes, I suggest you \
2079 + increase POOL_SIZE", __FUNCTION__, __FILE__, __LINE__);
2080 + return NULL;
2081 +}
2082 +
2083 +void init_irq_proc(void)
2084 +{
2085 + /* Insert /proc/irq driver here */
2086 +}
2087 +
2088 +int setup_irq(unsigned int irq, struct irq_node *node)
2089 +{
2090 + struct irq_controller *contr;
2091 + struct irq_node **prev;
2092 + unsigned long flags;
2093 +
2094 + if (irq >= NR_IRQS || !irq_controller[irq]) {
2095 + printk("%s: Incorrect IRQ %d from %s\n",
2096 + __FUNCTION__, irq, node->devname);
2097 + return -ENXIO;
2098 + }
2099 +
2100 + contr = irq_controller[irq];
2101 + spin_lock_irqsave(&contr->lock, flags);
2102 +
2103 + prev = irq_list + irq;
2104 + if (*prev) {
2105 + /* Can't share interrupts unless both agree to */
2106 + if (!((*prev)->flags & node->flags & IRQF_SHARED)) {
2107 + spin_unlock_irqrestore(&contr->lock, flags);
2108 + printk(KERN_INFO "%s: -BUSY-Incorrect IRQ %d \n",
2109 + __FUNCTION__, irq);
2110 + return -EBUSY;
2111 + }
2112 + while (*prev)
2113 + prev = &(*prev)->next;
2114 + }
2115 +
2116 + if (!irq_list[irq]) {
2117 + if (contr->startup)
2118 + contr->startup(irq);
2119 + else
2120 + contr->enable(irq);
2121 + }
2122 + node->next = NULL;
2123 + *prev = node;
2124 +
2125 + spin_unlock_irqrestore(&contr->lock, flags);
2126 +
2127 + return 0;
2128 +}
2129 +
2130 +int request_irq(unsigned int irq,
2131 + irq_handler_t handler,
2132 + unsigned long flags, const char *devname, void *dev_id)
2133 +{
2134 + struct irq_node *node = get_irq_node();
2135 + int res;
2136 +
2137 + if (!node) {
2138 + printk(KERN_INFO "%s:get_irq_node error %x\n",
2139 + __FUNCTION__,(unsigned int) node);
2140 + return -ENOMEM;
2141 + }
2142 + node->handler = handler;
2143 + node->flags = flags;
2144 + node->dev_id = dev_id;
2145 + node->devname = devname;
2146 +
2147 + res = setup_irq(irq, node);
2148 + if (res)
2149 + node->handler = NULL;
2150 +
2151 + return res;
2152 +}
2153 +EXPORT_SYMBOL(request_irq);
2154 +
2155 +void free_irq(unsigned int irq, void *dev_id)
2156 +{
2157 + struct irq_controller *contr;
2158 + struct irq_node **p, *node;
2159 + unsigned long flags;
2160 +
2161 + if (irq >= NR_IRQS || !irq_controller[irq]) {
2162 + printk(KERN_DEBUG "%s: Incorrect IRQ %d\n", __FUNCTION__, irq);
2163 + return;
2164 + }
2165 +
2166 + contr = irq_controller[irq];
2167 + spin_lock_irqsave(&contr->lock, flags);
2168 +
2169 + p = irq_list + irq;
2170 + while ((node = *p)) {
2171 + if (node->dev_id == dev_id)
2172 + break;
2173 + p = &node->next;
2174 + }
2175 +
2176 + if (node) {
2177 + *p = node->next;
2178 + node->handler = NULL;
2179 + } else
2180 + printk(KERN_DEBUG "%s: Removing probably wrong IRQ %d\n",
2181 + __FUNCTION__, irq);
2182 +
2183 + if (!irq_list[irq]) {
2184 + if (contr->shutdown)
2185 + contr->shutdown(irq);
2186 + else
2187 + contr->disable(irq);
2188 + }
2189 +
2190 + spin_unlock_irqrestore(&contr->lock, flags);
2191 +}
2192 +EXPORT_SYMBOL(free_irq);
2193 +
2194 +void enable_irq(unsigned int irq)
2195 +{
2196 + struct irq_controller *contr;
2197 + unsigned long flags;
2198 +
2199 + if (irq >= NR_IRQS || !irq_controller[irq]) {
2200 + printk(KERN_DEBUG "%s: Incorrect IRQ %d\n", __FUNCTION__, irq);
2201 + return;
2202 + }
2203 +
2204 + contr = irq_controller[irq];
2205 + spin_lock_irqsave(&contr->lock, flags);
2206 + if (irq_depth[irq]) {
2207 + if (!--irq_depth[irq]) {
2208 + if (contr->enable)
2209 + contr->enable(irq);
2210 + }
2211 + } else
2212 + WARN_ON(1);
2213 + spin_unlock_irqrestore(&contr->lock, flags);
2214 +}
2215 +EXPORT_SYMBOL(enable_irq);
2216 +
2217 +void disable_irq(unsigned int irq)
2218 +{
2219 + struct irq_controller *contr;
2220 + unsigned long flags;
2221 +
2222 + if (irq >= NR_IRQS || !irq_controller[irq]) {
2223 + printk(KERN_DEBUG "%s: Incorrect IRQ %d\n", __FUNCTION__, irq);
2224 + return;
2225 + }
2226 +
2227 + contr = irq_controller[irq];
2228 + spin_lock_irqsave(&contr->lock, flags);
2229 + if (!irq_depth[irq]++) {
2230 + if (contr->disable)
2231 + contr->disable(irq);
2232 + }
2233 + spin_unlock_irqrestore(&contr->lock, flags);
2234 +}
2235 +EXPORT_SYMBOL(disable_irq);
2236 +
2237 +void disable_irq_nosync(unsigned int irq) __attribute__((alias("disable_irq")));
2238 +EXPORT_SYMBOL(disable_irq_nosync);
2239 +
2240 +
2241 +unsigned long probe_irq_on(void)
2242 +{
2243 + return 0;
2244 +}
2245 +EXPORT_SYMBOL(probe_irq_on);
2246 +
2247 +int probe_irq_off(unsigned long irqs)
2248 +{
2249 + return 0;
2250 +}
2251 +EXPORT_SYMBOL(probe_irq_off);
2252 +
2253 +asmlinkage void handle_badint(struct pt_regs *regs)
2254 +{
2255 + kstat_cpu(0).irqs[0]++;
2256 + num_spurious++;
2257 + printk(KERN_DEBUG "unexpected interrupt from %u\n", regs->vector);
2258 +}
2259 +EXPORT_SYMBOL(handle_badint);
2260 +
2261 +#ifdef CONFIG_M5445X
2262 +/*
2263 + * M5445X Implementation
2264 + */
2265 +void m5445x_irq_enable(unsigned int irq)
2266 +{
2267 + /* enable the interrupt hardware */
2268 + if (irq < 64)
2269 + return;
2270 +
2271 + /* adjust past non-hardware ints */
2272 + irq -= 64;
2273 +
2274 + /* check for eport */
2275 + if ((irq > 0) && (irq < 8)) {
2276 + /* enable eport */
2277 + MCF_EPORT_EPPAR &= ~(3 << (irq*2)); /* level */
2278 + MCF_EPORT_EPDDR &= ~(1 << irq); /* input */
2279 + MCF_EPORT_EPIER |= 1 << irq; /* irq enabled */
2280 + }
2281 +
2282 + if (irq < 64) {
2283 + /* controller 0 */
2284 + MCF_INTC0_ICR(irq) = 0x02;
2285 + MCF_INTC0_CIMR = irq;
2286 + } else {
2287 + /* controller 1 */
2288 + irq -= 64;
2289 + MCF_INTC1_ICR(irq) = 0x02;
2290 + MCF_INTC1_CIMR = irq;
2291 + }
2292 +}
2293 +
2294 +void m5445x_irq_disable(unsigned int irq)
2295 +{
2296 + /* disable the interrupt hardware */
2297 + if (irq < 64)
2298 + return;
2299 +
2300 + /* adjust past non-hardware ints */
2301 + irq -= 64;
2302 +
2303 + /* check for eport */
2304 + if ((irq > 0) && (irq < 8)) {
2305 + /* disable eport */
2306 + MCF_EPORT_EPIER &= ~(1 << irq);
2307 + }
2308 +
2309 + if (irq < 64) {
2310 + /* controller 0 */
2311 + MCF_INTC0_ICR(irq) = 0x00;
2312 + MCF_INTC0_SIMR = irq;
2313 + } else {
2314 + /* controller 1 */
2315 + irq -= 64;
2316 + MCF_INTC1_ICR(irq) = 0x00;
2317 + MCF_INTC1_SIMR = irq;
2318 + }
2319 +}
2320 +#elif defined(CONFIG_M547X_8X)
2321 +/*
2322 + * M547X_8X Implementation
2323 + */
2324 +void m547x_8x_irq_enable(unsigned int irq)
2325 +{
2326 + /* enable the interrupt hardware */
2327 + if (irq < 64)
2328 + return;
2329 +
2330 + /* adjust past non-hardware ints */
2331 + irq -= 64;
2332 +
2333 +/* JKM -- re-add EPORT later */
2334 +#if 0
2335 + /* check for eport */
2336 + if ((irq > 0) && (irq < 8)) {
2337 + /* enable eport */
2338 + MCF_EPORT_EPPAR &= ~(3 << (irq*2)); /* level */
2339 + MCF_EPORT_EPDDR &= ~(1 << irq); /* input */
2340 + MCF_EPORT_EPIER |= 1 << irq; /* irq enabled */
2341 + }
2342 +#endif
2343 +
2344 + if (irq < 32) {
2345 + /* *grumble* don't set low bit of IMRL */
2346 + MCF_IMRL &= (~(1 << irq) & 0xfffffffe);
2347 + }
2348 + else {
2349 + MCF_IMRH &= ~(1 << (irq - 32));
2350 + }
2351 +}
2352 +
2353 +void m547x_8x_irq_disable(unsigned int irq)
2354 +{
2355 + /* disable the interrupt hardware */
2356 + if (irq < 64)
2357 + return;
2358 +
2359 + /* adjust past non-hardware ints */
2360 + irq -= 64;
2361 +
2362 +/* JKM -- re-add EPORT later */
2363 +#if 0
2364 + /* check for eport */
2365 + if ((irq > 0) && (irq < 8)) {
2366 + /* disable eport */
2367 + MCF_EPORT_EPIER &= ~(1 << irq);
2368 + }
2369 +#endif
2370 +
2371 + if (irq < 32)
2372 + MCF_IMRL |= (1 << irq);
2373 + else
2374 + MCF_IMRH |= (1 << (irq - 32));
2375 +}
2376 +#endif
2377 --- /dev/null
2378 +++ b/arch/m68k/coldfire/iomap.c
2379 @@ -0,0 +1,56 @@
2380 +/*
2381 + * arch/m68k/coldfire/iomap.c
2382 + *
2383 + * Generic coldfire iomap interface
2384 + *
2385 + * Based on the sh64 iomap.c by Paul Mundt.
2386 + *
2387 + * This file is subject to the terms and conditions of the GNU General Public
2388 + * License. See the file "COPYING" in the main directory of this archive
2389 + * for more details.
2390 + */
2391 +#include <linux/pci.h>
2392 +#include <asm/io.h>
2393 +
2394 +#if 0
2395 +void __iomem *__attribute__ ((weak))
2396 +ioport_map(unsigned long port, unsigned int len)
2397 +{
2398 + return (void __iomem *)port;
2399 +}
2400 +EXPORT_SYMBOL(pci_iomap);
2401 +
2402 +void ioport_unmap(void __iomem *addr)
2403 +{
2404 + /* Nothing .. */
2405 +}
2406 +EXPORT_SYMBOL(pci_iounmap);
2407 +
2408 +void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max)
2409 +{
2410 + unsigned long start = pci_resource_start(dev, bar);
2411 + unsigned long len = pci_resource_len(dev, bar);
2412 + unsigned long flags = pci_resource_flags(dev, bar);
2413 +printk(KERN_INFO "PCI_IOMAP: BAR=%d START=0x%lx LEN=0x%lx FLAGS=0x%lx\n",
2414 + bar, start, len, flags);
2415 +
2416 + if (!len)
2417 + return NULL;
2418 + if (max && len > max)
2419 + len = max;
2420 + if (flags & IORESOURCE_IO)
2421 + return ioport_map(start, len);
2422 + if (flags & IORESOURCE_MEM)
2423 + return (void __iomem *)start;
2424 +
2425 + /* What? */
2426 + return NULL;
2427 +}
2428 +EXPORT_SYMBOL(ioport_map);
2429 +
2430 +void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
2431 +{
2432 + /* Nothing .. */
2433 +}
2434 +EXPORT_SYMBOL(ioport_unmap);
2435 +#endif
2436 --- /dev/null
2437 +++ b/arch/m68k/coldfire/m547x_8x-devices.c
2438 @@ -0,0 +1,163 @@
2439 +/*
2440 + * arch/m68k/coldfire/m547x_8x-devices.c
2441 + *
2442 + * Coldfire M547x/M548x Platform Device Configuration
2443 + *
2444 + * Copyright (c) 2008 Freescale Semiconductor, Inc.
2445 + * Kurt Mahan <kmahan@freescale.com>
2446 + */
2447 +#include <linux/module.h>
2448 +#include <linux/kernel.h>
2449 +#include <linux/init.h>
2450 +#include <linux/platform_device.h>
2451 +#include <linux/fsl_devices.h>
2452 +#include <linux/spi/spi.h>
2453 +
2454 +#include <asm/coldfire.h>
2455 +#include <asm/mcfsim.h>
2456 +#include <asm/mcfqspi.h>
2457 +
2458 +
2459 +#ifdef CONFIG_SPI
2460 +/*
2461 + *
2462 + * DSPI
2463 + *
2464 + */
2465 +
2466 +/* number of supported SPI selects */
2467 +#define SPI_NUM_CHIPSELECTS 8
2468 +
2469 +void coldfire_spi_cs_control(u8 cs, u8 command)
2470 +{
2471 + /* nothing special required */
2472 +}
2473 +
2474 +#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
2475 +static struct coldfire_spi_chip spidev_chip_info = {
2476 + .bits_per_word = 8,
2477 +};
2478 +#endif
2479 +
2480 +static struct spi_board_info spi_board_info[] = {
2481 +#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
2482 + {
2483 + .modalias = "spidev",
2484 + .max_speed_hz = 16000000, /* max clk (SCK) speed in HZ */
2485 + .bus_num = 1,
2486 + .chip_select = 0, /* CS0 */
2487 + .controller_data = &spidev_chip_info,
2488 + }
2489 +#endif
2490 +};
2491 +
2492 +static int spi_irq_list[] = {
2493 + /* IRQ, ICR Offset, ICR Val,Mask */
2494 + 64 + ISC_DSPI_OVRFW, ISC_DSPI_OVRFW, 0x18, 0,
2495 + 64 + ISC_DSPI_RFOF, ISC_DSPI_RFOF, 0x18, 0,
2496 + 64 + ISC_DSPI_RFDF, ISC_DSPI_RFDF, 0x18, 0,
2497 + 64 + ISC_DSPI_TFUF, ISC_DSPI_TFUF, 0x18, 0,
2498 + 64 + ISC_DSPI_TCF, ISC_DSPI_TCF, 0x18, 0,
2499 + 64 + ISC_DSPI_TFFF, ISC_DSPI_TFFF, 0x18, 0,
2500 + 64 + ISC_DSPI_EOQF, ISC_DSPI_EOQF, 0x18, 0,
2501 + 0,0,0,0,
2502 +};
2503 +
2504 +static struct coldfire_spi_master coldfire_master_info = {
2505 + .bus_num = 1,
2506 + .num_chipselect = SPI_NUM_CHIPSELECTS,
2507 + .irq_list = spi_irq_list,
2508 + .irq_source = 0, /* not used */
2509 + .irq_vector = 0, /* not used */
2510 + .irq_mask = 0, /* not used */
2511 + .irq_lp = 0, /* not used */
2512 + .par_val = 0, /* not used */
2513 + .cs_control = coldfire_spi_cs_control,
2514 +};
2515 +
2516 +static struct resource coldfire_spi_resources[] = {
2517 + [0] = {
2518 + .name = "spi-par",
2519 + .start = MCF_MBAR + 0x00000a50, /* PAR_DSPI */
2520 + .end = MCF_MBAR + 0x00000a50, /* PAR_DSPI */
2521 + .flags = IORESOURCE_MEM
2522 + },
2523 +
2524 + [1] = {
2525 + .name = "spi-module",
2526 + .start = MCF_MBAR + 0x00008a00, /* DSPI MCR Base */
2527 + .end = MCF_MBAR + 0x00008ab8, /* DSPI mem map end */
2528 + .flags = IORESOURCE_MEM
2529 + },
2530 +
2531 + [2] = {
2532 + .name = "spi-int-level",
2533 + .start = MCF_MBAR + 0x740, /* ICR start */
2534 + .end = MCF_MBAR + 0x740 + ISC_DSPI_EOQF, /* ICR end */
2535 + .flags = IORESOURCE_MEM
2536 + },
2537 +
2538 + [3] = {
2539 + .name = "spi-int-mask",
2540 + .start = MCF_MBAR + 0x70c, /* IMRL */
2541 + .end = MCF_MBAR + 0x70c, /* IMRL */
2542 + .flags = IORESOURCE_MEM
2543 + }
2544 +};
2545 +
2546 +static struct platform_device coldfire_spi = {
2547 + .name = "spi_coldfire",
2548 + .id = -1,
2549 + .resource = coldfire_spi_resources,
2550 + .num_resources = ARRAY_SIZE(coldfire_spi_resources),
2551 + .dev = {
2552 + .platform_data = &coldfire_master_info,
2553 + }
2554 +};
2555 +
2556 +/**
2557 + * m547x_8x_spi_init - Initialize SPI
2558 + */
2559 +static int __init m547x_8x_spi_init(void)
2560 +{
2561 + int retval;
2562 +
2563 + /* initialize the DSPI PAR */
2564 + MCF_GPIO_PAR_DSPI = (MCF_GPIO_PAR_DSPI_PAR_CS5 |
2565 + MCF_GPIO_PAR_DSPI_PAR_CS3_DSPICS |
2566 + MCF_GPIO_PAR_DSPI_PAR_CS2_DSPICS |
2567 + MCF_GPIO_PAR_DSPI_PAR_CS0_DSPICS |
2568 + MCF_GPIO_PAR_DSPI_PAR_SCK_SCK |
2569 + MCF_GPIO_PAR_DSPI_PAR_SIN_SIN |
2570 + MCF_GPIO_PAR_DSPI_PAR_SOUT_SOUT);
2571 +
2572 + /* register device */
2573 + retval = platform_device_register(&coldfire_spi);
2574 + if (retval < 0) {
2575 + goto out;
2576 + }
2577 +
2578 + /* register board info */
2579 + if (ARRAY_SIZE(spi_board_info))
2580 + retval = spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
2581 +
2582 +out:
2583 + return retval;
2584 +}
2585 +#endif
2586 +
2587 +
2588 +/**
2589 + * m547x_8x_init_devices - Initialize M547X_8X devices
2590 + *
2591 + * Returns 0 on success.
2592 + */
2593 +static int __init m547x_8x_init_devices(void)
2594 +{
2595 +#ifdef CONFIG_SPI
2596 + m547x_8x_spi_init();
2597 +#endif
2598 +
2599 + return 0;
2600 +}
2601 +arch_initcall(m547x_8x_init_devices);
2602 --- /dev/null
2603 +++ b/arch/m68k/coldfire/m547x_8x-dma.c
2604 @@ -0,0 +1,516 @@
2605 +/*
2606 + * arch/m68k/coldfire/m547x_8x-dma.c
2607 + *
2608 + * Coldfire M547x/M548x DMA
2609 + *
2610 + * Copyright (c) 2008 Freescale Semiconductor, Inc.
2611 + * Kurt Mahan <kmahan@freescale.com>
2612 + *
2613 + * This code is based on patches from the Freescale M547x_8x BSP
2614 + * release mcf547x_8x-20070107-ltib.iso
2615 + *
2616 + * This program is free software; you can redistribute it and/or modify
2617 + * it under the terms of the GNU General Public License as published by
2618 + * the Free Software Foundation; either version 2 of the License, or
2619 + * (at your option) any later version.
2620 + *
2621 + * This program is distributed in the hope that it will be useful,
2622 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2623 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2624 + * GNU General Public License for more details.
2625 + *
2626 + * You should have received a copy of the GNU General Public License
2627 + * along with this program; if not, write to the Free Software
2628 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
2629 + */
2630 +#include <linux/kernel.h>
2631 +#include <linux/sched.h>
2632 +#include <linux/mm.h>
2633 +#include <linux/init.h>
2634 +#include <linux/interrupt.h>
2635 +#include <asm/io.h>
2636 +#include <asm/irq.h>
2637 +#include <asm/dma.h>
2638 +#include <asm/coldfire.h>
2639 +#include <asm/m5485sram.h>
2640 +#include <asm/mcfsim.h>
2641 +
2642 +/*
2643 + * This global keeps track of which initiators have been
2644 + * used of the available assignments. Initiators 0-15 are
2645 + * hardwired. Initiators 16-31 are multiplexed and controlled
2646 + * via the Initiatior Mux Control Registe (IMCR). The
2647 + * assigned requestor is stored with the associated initiator
2648 + * number.
2649 + */
2650 +static int used_reqs[32] = {
2651 + DMA_ALWAYS, DMA_DSPI_RX, DMA_DSPI_TX, DMA_DREQ0,
2652 + DMA_PSC0_RX, DMA_PSC0_TX, DMA_USBEP0, DMA_USBEP1,
2653 + DMA_USBEP2, DMA_USBEP3, DMA_PCI_TX, DMA_PCI_RX,
2654 + DMA_PSC1_RX, DMA_PSC1_TX, DMA_I2C_RX, DMA_I2C_TX,
2655 + 0, 0, 0, 0,
2656 + 0, 0, 0, 0,
2657 + 0, 0, 0, 0,
2658 + 0, 0, 0, 0
2659 +};
2660 +
2661 +/*
2662 + * This global keeps track of which channels have been assigned
2663 + * to tasks. This methology assumes that no single initiator
2664 + * will be tied to more than one task/channel
2665 + */
2666 +static char used_channel[16] = {
2667 + -1, -1, -1, -1, -1, -1, -1, -1,
2668 + -1, -1, -1, -1, -1, -1, -1, -1
2669 +};
2670 +
2671 +unsigned int connected_channel[16] = {
2672 + 0, 0, 0, 0, 0, 0, 0, 0,
2673 + 0, 0, 0, 0, 0, 0, 0, 0
2674 +};
2675 +
2676 +/**
2677 + * dma_set_initiator - enable initiator
2678 + * @initiator: initiator identifier
2679 + *
2680 + * Returns 0 of successful, non-zero otherwise
2681 + *
2682 + * Attempt to enable the provided Initiator in the Initiator
2683 + * Mux Control Register.
2684 + */
2685 +int dma_set_initiator(int initiator)
2686 +{
2687 + switch (initiator) {
2688 + case DMA_ALWAYS:
2689 + case DMA_DSPI_RX:
2690 + case DMA_DSPI_TX:
2691 + case DMA_DREQ0:
2692 + case DMA_PSC0_RX:
2693 + case DMA_PSC0_TX:
2694 + case DMA_USBEP0:
2695 + case DMA_USBEP1:
2696 + case DMA_USBEP2:
2697 + case DMA_USBEP3:
2698 + case DMA_PCI_TX:
2699 + case DMA_PCI_RX:
2700 + case DMA_PSC1_RX:
2701 + case DMA_PSC1_TX:
2702 + case DMA_I2C_RX:
2703 + case DMA_I2C_TX:
2704 + /*
2705 + * These initiators are always active
2706 + */
2707 + break;
2708 +
2709 + case DMA_FEC0_RX:
2710 + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC16(3))
2711 + | MCF_DMA_IMCR_SRC16_FEC0RX;
2712 + used_reqs[16] = DMA_FEC0_RX;
2713 + break;
2714 +
2715 + case DMA_FEC0_TX:
2716 + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC17(3))
2717 + | MCF_DMA_IMCR_SRC17_FEC0TX;
2718 + used_reqs[17] = DMA_FEC0_TX;
2719 + break;
2720 +
2721 + case DMA_FEC1_RX:
2722 + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC20(3))
2723 + | MCF_DMA_IMCR_SRC20_FEC1RX;
2724 + used_reqs[20] = DMA_FEC1_RX;
2725 + break;
2726 +
2727 + case DMA_FEC1_TX:
2728 + if (used_reqs[21] == 0) {
2729 + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC21(3))
2730 + | MCF_DMA_IMCR_SRC21_FEC1TX;
2731 + used_reqs[21] = DMA_FEC1_TX;
2732 + } else if (used_reqs[25] == 0) {
2733 + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC25(3))
2734 + | MCF_DMA_IMCR_SRC25_FEC1TX;
2735 + used_reqs[25] = DMA_FEC1_TX;
2736 + } else if (used_reqs[31] == 0) {
2737 + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC31(3))
2738 + | MCF_DMA_IMCR_SRC31_FEC1TX;
2739 + used_reqs[31] = DMA_FEC1_TX;
2740 + } else /* No empty slots */
2741 + return 1;
2742 + break;
2743 +
2744 + case DMA_DREQ1:
2745 + if (used_reqs[29] == 0) {
2746 + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC29(3))
2747 + | MCF_DMA_IMCR_SRC29_DREQ1;
2748 + used_reqs[29] = DMA_DREQ1;
2749 + } else if (used_reqs[21] == 0) {
2750 + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC21(3))
2751 + | MCF_DMA_IMCR_SRC21_DREQ1;
2752 + used_reqs[21] = DMA_DREQ1;
2753 + } else /* No empty slots */
2754 + return 1;
2755 + break;
2756 +
2757 + case DMA_CTM0:
2758 + if (used_reqs[24] == 0) {
2759 + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC24(3))
2760 + | MCF_DMA_IMCR_SRC24_CTM0;
2761 + used_reqs[24] = DMA_CTM0;
2762 + } else /* No empty slots */
2763 + return 1;
2764 + break;
2765 +
2766 + case DMA_CTM1:
2767 + if (used_reqs[25] == 0) {
2768 + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC25(3))
2769 + | MCF_DMA_IMCR_SRC25_CTM1;
2770 + used_reqs[25] = DMA_CTM1;
2771 + } else /* No empty slots */
2772 + return 1;
2773 + break;
2774 +
2775 + case DMA_CTM2:
2776 + if (used_reqs[26] == 0) {
2777 + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC26(3))
2778 + | MCF_DMA_IMCR_SRC26_CTM2;
2779 + used_reqs[26] = DMA_CTM2;
2780 + } else /* No empty slots */
2781 + return 1;
2782 + break;
2783 +
2784 + case DMA_CTM3:
2785 + if (used_reqs[27] == 0) {
2786 + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC27(3))
2787 + | MCF_DMA_IMCR_SRC27_CTM3;
2788 + used_reqs[27] = DMA_CTM3;
2789 + } else /* No empty slots */
2790 + return 1;
2791 + break;
2792 +
2793 + case DMA_CTM4:
2794 + if (used_reqs[28] == 0) {
2795 + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC28(3))
2796 + | MCF_DMA_IMCR_SRC28_CTM4;
2797 + used_reqs[28] = DMA_CTM4;
2798 + } else /* No empty slots */
2799 + return 1;
2800 + break;
2801 +
2802 + case DMA_CTM5:
2803 + if (used_reqs[29] == 0) {
2804 + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC29(3))
2805 + | MCF_DMA_IMCR_SRC29_CTM5;
2806 + used_reqs[29] = DMA_CTM5;
2807 + } else /* No empty slots */
2808 + return 1;
2809 + break;
2810 +
2811 + case DMA_CTM6:
2812 + if (used_reqs[30] == 0) {
2813 + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC30(3))
2814 + | MCF_DMA_IMCR_SRC30_CTM6;
2815 + used_reqs[30] = DMA_CTM6;
2816 + } else /* No empty slots */
2817 + return 1;
2818 + break;
2819 +
2820 + case DMA_CTM7:
2821 + if (used_reqs[31] == 0) {
2822 + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC31(3))
2823 + | MCF_DMA_IMCR_SRC31_CTM7;
2824 + used_reqs[31] = DMA_CTM7;
2825 + } else /* No empty slots */
2826 + return 1;
2827 + break;
2828 +
2829 + case DMA_USBEP4:
2830 + if (used_reqs[26] == 0) {
2831 + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC26(3))
2832 + | MCF_DMA_IMCR_SRC26_USBEP4;
2833 + used_reqs[26] = DMA_USBEP4;
2834 + } else /* No empty slots */
2835 + return 1;
2836 + break;
2837 +
2838 + case DMA_USBEP5:
2839 + if (used_reqs[27] == 0) {
2840 + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC27(3))
2841 + | MCF_DMA_IMCR_SRC27_USBEP5;
2842 + used_reqs[27] = DMA_USBEP5;
2843 + } else /* No empty slots */
2844 + return 1;
2845 + break;
2846 +
2847 + case DMA_USBEP6:
2848 + if (used_reqs[28] == 0) {
2849 + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC28(3))
2850 + | MCF_DMA_IMCR_SRC28_USBEP6;
2851 + used_reqs[28] = DMA_USBEP6;
2852 + } else /* No empty slots */
2853 + return 1;
2854 + break;
2855 +
2856 + case DMA_PSC2_RX:
2857 + if (used_reqs[28] == 0) {
2858 + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC28(3))
2859 + | MCF_DMA_IMCR_SRC28_PSC2RX;
2860 + used_reqs[28] = DMA_PSC2_RX;
2861 + } else /* No empty slots */
2862 + return 1;
2863 + break;
2864 +
2865 + case DMA_PSC2_TX:
2866 + if (used_reqs[29] == 0) {
2867 + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC29(3))
2868 + | MCF_DMA_IMCR_SRC29_PSC2TX;
2869 + used_reqs[29] = DMA_PSC2_TX;
2870 + } else /* No empty slots */
2871 + return 1;
2872 + break;
2873 +
2874 + case DMA_PSC3_RX:
2875 + if (used_reqs[30] == 0) {
2876 + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC30(3))
2877 + | MCF_DMA_IMCR_SRC30_PSC3RX;
2878 + used_reqs[30] = DMA_PSC3_RX;
2879 + } else /* No empty slots */
2880 + return 1;
2881 + break;
2882 +
2883 + case DMA_PSC3_TX:
2884 + if (used_reqs[31] == 0) {
2885 + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC31(3))
2886 + | MCF_DMA_IMCR_SRC31_PSC3TX;
2887 + used_reqs[31] = DMA_PSC3_TX;
2888 + } else /* No empty slots */
2889 + return 1;
2890 + break;
2891 +
2892 + default:
2893 + return 1;
2894 + }
2895 + return 0;
2896 +}
2897 +
2898 +/**
2899 + * dma_get_initiator - get the initiator for the given requestor
2900 + * @requestor: initiator identifier
2901 + *
2902 + * Returns initiator number (0-31) if assigned or just 0
2903 + */
2904 +unsigned int dma_get_initiator(int requestor)
2905 +{
2906 + u32 i;
2907 +
2908 + for (i = 0; i < sizeof(used_reqs); ++i) {
2909 + if (used_reqs[i] == requestor)
2910 + return i;
2911 + }
2912 + return 0;
2913 +}
2914 +
2915 +/**
2916 + * dma_remove_initiator - remove the given initiator from active list
2917 + * @requestor: requestor to remove
2918 + */
2919 +void dma_remove_initiator(int requestor)
2920 +{
2921 + u32 i;
2922 +
2923 + for (i = 0; i < sizeof(used_reqs); ++i) {
2924 + if (used_reqs[i] == requestor) {
2925 + used_reqs[i] = -1;
2926 + break;
2927 + }
2928 + }
2929 +}
2930 +
2931 +/**
2932 + * dma_set_channel_fec: find available channel for fec and mark
2933 + * @requestor: initiator/requestor identifier
2934 + *
2935 + * Returns first avaialble channel (0-5) or -1 if all occupied
2936 + */
2937 +int dma_set_channel_fec(int requestor)
2938 +{
2939 + u32 i, t;
2940 +
2941 +#ifdef CONFIG_FEC_548x_ENABLE_FEC2
2942 + t = 4;
2943 +#else
2944 + t = 2;
2945 +#endif
2946 +
2947 + for (i = 0; i < t ; ++i) {
2948 + if (used_channel[i] == -1) {
2949 + used_channel[i] = requestor;
2950 + return i;
2951 + }
2952 + }
2953 + /* All channels taken */
2954 + return -1;
2955 +}
2956 +
2957 +/**
2958 + * dma_set_channel - find an available channel and mark as used
2959 + * @requestor: initiator/requestor identifier
2960 + *
2961 + * Returns first available channel (6-15) or -1 if all occupied
2962 + */
2963 +int dma_set_channel(int requestor)
2964 +{
2965 + u32 i;
2966 +#ifdef CONFIG_NET_FEC2
2967 + i = 4;
2968 +#else
2969 + i = 2;
2970 +#endif
2971 +
2972 + for (; i < 16; ++i)
2973 + if (used_channel[i] == -1) {
2974 + used_channel[i] = requestor;
2975 + return i;
2976 + }
2977 +
2978 + /* All channels taken */
2979 + return -1;
2980 +}
2981 +
2982 +/**
2983 + * dma_get_channel - get the channel being initiated by the requestor
2984 + * @requestor: initiator/requestor identifier
2985 + *
2986 + * Returns Initiator for requestor or -1 if not found
2987 + */
2988 +int dma_get_channel(int requestor)
2989 +{
2990 + u32 i;
2991 +
2992 + for (i = 0; i < sizeof(used_channel); ++i) {
2993 + if (used_channel[i] == requestor)
2994 + return i;
2995 + }
2996 + return -1;
2997 +}
2998 +
2999 +/**
3000 + * dma_connect - connect a channel with reference on data
3001 + * @channel: channel number
3002 + * @address: reference address of data
3003 + *
3004 + * Returns 0 if success or -1 if invalid channel
3005 + */
3006 +int dma_connect(int channel, int address)
3007 +{
3008 + if ((channel < 16) && (channel >= 0)) {
3009 + connected_channel[channel] = address;
3010 + return 0;
3011 + }
3012 + return -1;
3013 +}
3014 +
3015 +/**
3016 + * dma_disconnect - disconnect a channel
3017 + * @channel: channel number
3018 + *
3019 + * Returns 0 if success or -1 if invalid channel
3020 + */
3021 +int dma_disconnect(int channel)
3022 +{
3023 + if ((channel < 16) && (channel >= 0)) {
3024 + connected_channel[channel] = 0;
3025 + return 0;
3026 + }
3027 + return -1;
3028 +}
3029 +
3030 +/**
3031 + * dma_remove_channel - remove channel from the active list
3032 + * @requestor: initiator/requestor identifier
3033 + */
3034 +void dma_remove_channel(int requestor)
3035 +{
3036 + u32 i;
3037 +
3038 + for (i = 0; i < sizeof(used_channel); ++i) {
3039 + if (used_channel[i] == requestor) {
3040 + used_channel[i] = -1;
3041 + break;
3042 + }
3043 + }
3044 +}
3045 +
3046 +/**
3047 + * dma_interrupt_handler - dma interrupt handler
3048 + * @irq: interrupt number
3049 + * @dev_id: data
3050 + *
3051 + * Returns IRQ_HANDLED
3052 + */
3053 +irqreturn_t dma_interrupt_handler(int irq, void *dev_id)
3054 +{
3055 + u32 i, interrupts;
3056 +
3057 + /*
3058 + * Determine which interrupt(s) triggered by AND'ing the
3059 + * pending interrupts with those that aren't masked.
3060 + */
3061 + interrupts = MCF_DMA_DIPR;
3062 + MCF_DMA_DIPR = interrupts;
3063 +
3064 + for (i = 0; i < 16; ++i, interrupts >>= 1) {
3065 + if (interrupts & 0x1)
3066 + if (connected_channel[i] != 0)
3067 + ((void (*)(void)) (connected_channel[i])) ();
3068 + }
3069 +
3070 + return IRQ_HANDLED;
3071 +}
3072 +
3073 +/**
3074 + * dma_remove_channel_by_number - clear dma channel
3075 + * @channel: channel number to clear
3076 + */
3077 +void dma_remove_channel_by_number(int channel)
3078 +{
3079 + if ((channel < sizeof(used_channel)) && (channel >= 0))
3080 + used_channel[channel] = -1;
3081 +}
3082 +
3083 +/**
3084 + * dma_init - initialize the dma subsystem
3085 + *
3086 + * Returns 0 if success non-zero if failure
3087 + *
3088 + * Handles the DMA initialization during device setup.
3089 + */
3090 +int __devinit dma_init()
3091 +{
3092 + int result;
3093 + char *dma_version_str;
3094 +
3095 + MCD_getVersion(&dma_version_str);
3096 + printk(KERN_INFO "m547x_8x DMA: Initialize %s\n", dma_version_str);
3097 +
3098 + /* attempt to setup dma interrupt handler */
3099 + if (request_irq(64 + ISC_DMA, dma_interrupt_handler, IRQF_DISABLED,
3100 + "MCD-DMA", NULL)) {
3101 + printk(KERN_ERR "MCD-DMA: Cannot allocate the DMA IRQ(48)\n");
3102 + return 1;
3103 + }
3104 +
3105 + MCF_DMA_DIMR = 0;
3106 + MCF_DMA_DIPR = 0xFFFFFFFF;
3107 +
3108 + MCF_ICR(ISC_DMA) = ILP_DMA;
3109 +
3110 + result = MCD_initDma((dmaRegs *) (MCF_MBAR + 0x8000),
3111 + (void *) SYS_SRAM_DMA_START, MCD_RELOC_TASKS);
3112 + if (result != MCD_OK) {
3113 + printk(KERN_ERR "MCD-DMA: Cannot perform DMA initialization\n");
3114 + free_irq(64 + ISC_DMA, NULL);
3115 + return 1;
3116 + }
3117 +
3118 + return 0;
3119 +}
3120 +device_initcall(dma_init);
3121 --- /dev/null
3122 +++ b/arch/m68k/coldfire/Makefile
3123 @@ -0,0 +1,20 @@
3124 +#
3125 +# Makefile for Linux arch/m68k/coldfire source directory
3126 +#
3127 +
3128 +obj-y:= entry.o config.o cache.o signal.o muldi3.o traps.o ints.o
3129 +ifdef CONFIG_M5445X
3130 +ifneq ($(strip $(CONFIG_USB) $(CONFIG_USB_GADGET_MCF5445X)),)
3131 + obj-y += usb.o usb/
3132 +endif
3133 +endif
3134 +
3135 +ifdef CONFIG_M547X_8X
3136 +obj-$(CONFIG_PCI) += mcf548x-pci.o
3137 +else
3138 +obj-$(CONFIG_PCI) += pci.o mcf5445x-pci.o iomap.o
3139 +endif
3140 +obj-$(CONFIG_M5445X) += mcf5445x-devices.o
3141 +obj-$(CONFIG_M547X_8X) += m547x_8x-devices.o
3142 +obj-$(CONFIG_M547X_8X) += mcf548x-devices.o
3143 +obj-$(CONFIG_MCD_DMA) += m547x_8x-dma.o
3144 --- /dev/null
3145 +++ b/arch/m68k/coldfire/mcf5445x-devices.c
3146 @@ -0,0 +1,136 @@
3147 +/*
3148 + * arch/m68k/coldfire/mcf5445x-devices.c
3149 + *
3150 + * Coldfire M5445x Platform Device Configuration
3151 + *
3152 + * Based on the Freescale MXC devices.c
3153 + *
3154 + * Copyright (c) 2007 Freescale Semiconductor, Inc.
3155 + * Kurt Mahan <kmahan@freescale.com>
3156 + */
3157 +#include <linux/module.h>
3158 +#include <linux/kernel.h>
3159 +#include <linux/init.h>
3160 +#include <linux/platform_device.h>
3161 +#include <linux/fsl_devices.h>
3162 +
3163 +#include <asm/coldfire.h>
3164 +#include <asm/mcfsim.h>
3165 +
3166 +/* ATA Interrupt */
3167 +#define IRQ_ATA (64 + 64 + 54)
3168 +
3169 +/* ATA Base */
3170 +#define BASE_IO_ATA 0x90000000
3171 +
3172 +#define ATA_IER MCF_REG08(BASE_IO_ATA+0x2c) /* int enable reg */
3173 +#define ATA_ICR MCF_REG08(BASE_IO_ATA+0x30) /* int clear reg */
3174 +
3175 +/*
3176 + * On-chip PATA
3177 + */
3178 +#if defined(CONFIG_PATA_FSL) || defined(CONFIG_PATA_FSL_MODULE)
3179 +static int ata_init(struct platform_device *pdev)
3180 +{
3181 + /* clear ints */
3182 + ATA_IER = 0x00;
3183 + ATA_ICR = 0xff;
3184 +
3185 + /* setup shared pins */
3186 + MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC & MCF_GPIO_PAR_FEC_FEC1_MASK) |
3187 + MCF_GPIO_PAR_FEC_FEC1_ATA;
3188 +
3189 + MCF_GPIO_PAR_FECI2C = (MCF_GPIO_PAR_FECI2C &
3190 + (MCF_GPIO_PAR_FECI2C_MDC1_MASK &
3191 + MCF_GPIO_PAR_FECI2C_MDIO1_MASK)) |
3192 + MCF_GPIO_PAR_FECI2C_MDC1_ATA_DIOR |
3193 + MCF_GPIO_PAR_FECI2C_MDIO1_ATA_DIOW;
3194 +
3195 + MCF_GPIO_PAR_ATA = MCF_GPIO_PAR_ATA_BUFEN |
3196 + MCF_GPIO_PAR_ATA_CS1 |
3197 + MCF_GPIO_PAR_ATA_CS0 |
3198 + MCF_GPIO_PAR_ATA_DA2 |
3199 + MCF_GPIO_PAR_ATA_DA1 |
3200 + MCF_GPIO_PAR_ATA_DA0 |
3201 + MCF_GPIO_PAR_ATA_RESET_RESET |
3202 + MCF_GPIO_PAR_ATA_DMARQ_DMARQ |
3203 + MCF_GPIO_PAR_ATA_IORDY_IORDY;
3204 +
3205 + MCF_GPIO_PAR_PCI = (MCF_GPIO_PAR_PCI &
3206 + (MCF_GPIO_PAR_PCI_GNT3_MASK &
3207 + MCF_GPIO_PAR_PCI_REQ3_MASK)) |
3208 + MCF_GPIO_PAR_PCI_GNT3_ATA_DMACK |
3209 + MCF_GPIO_PAR_PCI_REQ3_ATA_INTRQ;
3210 +
3211 + return 0;
3212 +}
3213 +
3214 +static void ata_exit(void)
3215 +{
3216 + printk(KERN_INFO "** ata_exit\n");
3217 +}
3218 +
3219 +static int ata_get_clk_rate(void)
3220 +{
3221 + return MCF_BUSCLK;
3222 +}
3223 +
3224 +/* JKM -- move these to a header file */
3225 +#define MCF_IDE_DMA_WATERMARK 32 /* DMA watermark level in bytes */
3226 +#define MCF_IDE_DMA_BD_NR (512/3/4) /* number of BDs per channel */
3227 +
3228 +static struct fsl_ata_platform_data ata_data = {
3229 + .init = ata_init,
3230 + .exit = ata_exit,
3231 + .get_clk_rate = ata_get_clk_rate,
3232 +#ifdef CONFIG_PATA_FSL_USE_DMA
3233 + .udma_mask = 0x0F, /* the board handles up to UDMA3 */
3234 + .fifo_alarm = MCF_IDE_DMA_WATERMARK / 2,
3235 + .max_sg = MCF_IDE_DMA_BD_NR,
3236 +#endif
3237 +};
3238 +
3239 +static struct resource pata_fsl_resources[] = {
3240 + [0] = { /* I/O */
3241 + .start = BASE_IO_ATA,
3242 + .end = BASE_IO_ATA + 0x000000d8,
3243 + .flags = IORESOURCE_MEM,
3244 + },
3245 + [2] = { /* IRQ */
3246 + .start = IRQ_ATA,
3247 + .end = IRQ_ATA,
3248 + .flags = IORESOURCE_IRQ,
3249 + },
3250 +};
3251 +
3252 +static struct platform_device pata_fsl_device = {
3253 + .name = "pata_fsl",
3254 + .id = -1,
3255 + .num_resources = ARRAY_SIZE(pata_fsl_resources),
3256 + .resource = pata_fsl_resources,
3257 + .dev = {
3258 + .platform_data = &ata_data,
3259 + .coherent_dma_mask = ~0, /* $$$ REVISIT */
3260 + },
3261 +};
3262 +
3263 +static inline void mcf5445x_init_pata(void)
3264 +{
3265 + (void)platform_device_register(&pata_fsl_device);
3266 +}
3267 +#else
3268 +static inline void mcf5445x_init_pata(void)
3269 +{
3270 +}
3271 +#endif
3272 +
3273 +static int __init mcf5445x_init_devices(void)
3274 +{
3275 + printk(KERN_INFO "MCF5445x INIT_DEVICES\n");
3276 +#if 0
3277 + mcf5445x_init_pata();
3278 +#endif
3279 +
3280 + return 0;
3281 +}
3282 +arch_initcall(mcf5445x_init_devices);
3283 --- /dev/null
3284 +++ b/arch/m68k/coldfire/mcf5445x-pci.c
3285 @@ -0,0 +1,431 @@
3286 +/*
3287 + * arch/m68k/coldfire/mcf5445x-pci.c
3288 + *
3289 + * Coldfire M5445x specific PCI implementation.
3290 + *
3291 + * Copyright (c) 2007 Freescale Semiconductor, Inc.
3292 + * Kurt Mahan <kmahan@freescale.com>
3293 + */
3294 +
3295 +#include <linux/delay.h>
3296 +#include <linux/interrupt.h>
3297 +#include <linux/pci.h>
3298 +
3299 +#include <asm/mcfsim.h>
3300 +#include <asm/pci.h>
3301 +#include <asm/irq.h>
3302 +
3303 +/*
3304 + * Layout MCF5445x to PCI memory mappings:
3305 + *
3306 + * WIN MCF5445x PCI TYPE
3307 + * --- -------- --- ----
3308 + * [0] 0xA0000000 -> 0xA7FFFFFF 0xA0000000 -> 0xA7FFFFFF MEM
3309 + * [1] 0xA8000000 -> 0xABFFFFFF 0xA8000000 -> 0xABFFFFFF MEM
3310 + * [2] 0xAC000000 -> 0xAFFFFFFF 0xAC000000 -> 0xAFFFFFFF IO
3311 + */
3312 +
3313 +#define MCF5445X_PCI_MEM_BASE 0xA0000000
3314 +#define MCF5445X_PCI_MEM_SIZE 0x0C000000
3315 +
3316 +#define MCF5445X_PCI_CONFIG_BASE 0xAC000000
3317 +#define MCF5445X_PCI_CONFIG_SIZE 0x04000000
3318 +
3319 +#define MCF5445X_PCI_IO_BASE 0xAC000000
3320 +#define MCF5445X_PCI_IO_SIZE 0x04000000
3321 +
3322 +/* PCI Bus memory resource block */
3323 +struct resource pci_iomem_resource = {
3324 + .name = "PCI memory space",
3325 + .start = MCF5445X_PCI_MEM_BASE,
3326 + .flags = IORESOURCE_MEM,
3327 + .end = MCF5445X_PCI_MEM_BASE + MCF5445X_PCI_MEM_SIZE - 1
3328 +};
3329 +
3330 +/* PCI Bus ioport resource block */
3331 +struct resource pci_ioport_resource = {
3332 + .name = "PCI I/O space",
3333 + .start = MCF5445X_PCI_IO_BASE,
3334 + .flags = IORESOURCE_IO,
3335 + .end = MCF5445X_PCI_IO_BASE + MCF5445X_PCI_IO_SIZE - 1
3336 +};
3337 +
3338 +/*
3339 + * The M54455EVB multiplexes all the PCI interrupts via
3340 + * the FPGA and routes them to a single interrupt. The
3341 + * PCI spec requires all PCI interrupt routines be smart
3342 + * enough to sort out their own interrupts.
3343 + * The interrupt source from the FPGA is configured
3344 + * to EPORT 3.
3345 + */
3346 +#define MCF5445X_PCI_IRQ 0x43
3347 +
3348 +#define PCI_SLOTS 4
3349 +
3350 +/*
3351 + * FPGA Info
3352 + */
3353 +#define FPGA_PCI_IRQ_ENABLE (u32 *)0x09000000
3354 +#define FPGA_PCI_IRQ_STATUS (u32 *)0x09000004
3355 +#define FPGA_PCI_IRQ_ROUTE (u32 *)0x0900000c
3356 +#define FPGA_SEVEN_LED (u32 *)0x09000014
3357 +
3358 +extern void set_fpga(u32 *addr, u32 val);
3359 +
3360 +#ifdef DEBUG
3361 +void mcf5445x_pci_dumpregs(void);
3362 +#endif
3363 +
3364 +/*
3365 + * mcf5445x_conf_device(struct pci_dev *dev)
3366 + *
3367 + * Machine dependent Configure the given device.
3368 + *
3369 + * Parameters:
3370 + *
3371 + * dev - the pci device.
3372 + */
3373 +void
3374 +mcf5445x_conf_device(struct pci_dev *dev)
3375 +{
3376 + set_fpga(FPGA_PCI_IRQ_ENABLE, 0x0f);
3377 +}
3378 +
3379 +/*
3380 + * int mcf5445x_pci_config_read(unsigned int seg, unsigned int bus,
3381 + * unsigned int devfn, int reg,
3382 + * u32 *value)
3383 + *
3384 + * Read from PCI configuration space.
3385 + *
3386 + */
3387 +int mcf5445x_pci_config_read(unsigned int seg, unsigned int bus,
3388 + unsigned int devfn, int reg, int len, u32 *value)
3389 +{
3390 + u32 addr = MCF_PCI_PCICAR_BUSNUM(bus) |
3391 + MCF_PCI_PCICAR_DEVNUM(PCI_SLOT(devfn)) |
3392 + MCF_PCI_PCICAR_FUNCNUM(PCI_FUNC(devfn)) |
3393 + MCF_PCI_PCICAR_DWORD(reg) |
3394 + MCF_PCI_PCICAR_E;
3395 +
3396 + if ((bus > 255) || (devfn > 255) || (reg > 255)) {
3397 + *value = -1;
3398 + return -EINVAL;
3399 + }
3400 +
3401 + /* setup for config mode */
3402 + MCF_PCI_PCICAR = addr;
3403 + __asm__ __volatile__("nop");
3404 +
3405 + switch (len) {
3406 + case 1:
3407 + *value = *(volatile u8 *)(MCF5445X_PCI_CONFIG_BASE+(reg&3));
3408 + break;
3409 + case 2:
3410 + *value = le16_to_cpu(*(volatile u16 *)
3411 + (MCF5445X_PCI_CONFIG_BASE + (reg&2)));
3412 + break;
3413 + case 4:
3414 + *value = le32_to_cpu(*(volatile u32 *)
3415 + (MCF5445X_PCI_CONFIG_BASE));
3416 + break;
3417 + }
3418 +
3419 + /* clear config mode */
3420 + MCF_PCI_PCICAR = ~MCF_PCI_PCICAR_E;
3421 + __asm__ __volatile__("nop");
3422 +
3423 + return 0;
3424 +}
3425 +
3426 +/*
3427 + * int mcf5445x_pci_config_write(unsigned int seg, unsigned int bus,
3428 + * unsigned int devfn, int reg,
3429 + * u32 *value)
3430 + *
3431 + * Write to PCI configuration space
3432 + */
3433 +int mcf5445x_pci_config_write(unsigned int seg, unsigned int bus,
3434 + unsigned int devfn, int reg, int len, u32 value)
3435 +{
3436 + u32 addr = MCF_PCI_PCICAR_BUSNUM(bus) |
3437 + MCF_PCI_PCICAR_DEVNUM(PCI_SLOT(devfn)) |
3438 + MCF_PCI_PCICAR_FUNCNUM(PCI_FUNC(devfn)) |
3439 + MCF_PCI_PCICAR_DWORD(reg) |
3440 + MCF_PCI_PCICAR_E;
3441 +
3442 + if ((bus > 255) || (devfn > 255) || (reg > 255))
3443 + return -EINVAL;
3444 +
3445 + /* setup for config mode */
3446 + MCF_PCI_PCICAR = addr;
3447 + __asm__ __volatile__("nop");
3448 +
3449 + switch (len) {
3450 + case 1:
3451 + *(volatile u8 *)(MCF5445X_PCI_CONFIG_BASE+(reg&3)) = (u8)value;
3452 + break;
3453 + case 2:
3454 + *(volatile u16 *)(MCF5445X_PCI_CONFIG_BASE+(reg&2)) =
3455 + cpu_to_le16((u16)value);
3456 + break;
3457 + case 4:
3458 + *(volatile u32 *)(MCF5445X_PCI_CONFIG_BASE) =
3459 + cpu_to_le32(value);
3460 + break;
3461 + }
3462 +
3463 + /* clear config mode */
3464 + MCF_PCI_PCICAR = ~MCF_PCI_PCICAR_E;
3465 + __asm__ __volatile__("nop");
3466 +
3467 + return 0;
3468 +}
3469 +
3470 +/* hardware operations */
3471 +static struct pci_raw_ops mcf5445x_pci_ops = {
3472 + .read = mcf5445x_pci_config_read,
3473 + .write = mcf5445x_pci_config_write,
3474 +};
3475 +
3476 +/*
3477 + * irqreturn_t mcf5445x_pci_interrupt( int irq, void *dev)
3478 + *
3479 + * PCI controller interrupt handler.
3480 + */
3481 +static irqreturn_t
3482 +mcf5445x_pci_interrupt(int irq, void *dev)
3483 +{
3484 + u32 status = MCF_PCI_PCIGSCR;
3485 +#ifdef DEBUG
3486 + printk(KERN_INFO "PCI: Controller irq status=0x%08x\n", status);
3487 +#endif
3488 + /* clear */
3489 + MCF_PCI_PCIGSCR = status;
3490 +
3491 + return IRQ_HANDLED;
3492 +}
3493 +
3494 +/*
3495 + * irqreturn_t mcf5445x_pci_arb_interrupt( int irq, void *dev)
3496 + *
3497 + * PCI Arbiter interrupt handler.
3498 + */
3499 +static irqreturn_t
3500 +mcf5445x_pci_arb_interrupt(int irq, void *dev)
3501 +{
3502 + u32 status = MCF_PCIARB_PASR;
3503 +#ifdef DEBUG
3504 + printk(KERN_INFO "PCI: Arbiter irq status=0x%08x\n", status);
3505 +#endif
3506 + /* clear */
3507 + MCF_PCIARB_PASR = status;
3508 + return IRQ_HANDLED;
3509 +}
3510 +
3511 +/*
3512 + * struct pci_bus_info *init_mcf5445x_pci(void)
3513 + *
3514 + * Machine specific initialisation:
3515 + *
3516 + * - Allocate and initialise a 'pci_bus_info' structure
3517 + * - Initialize hardware
3518 + *
3519 + * Result: pointer to 'pci_bus_info' structure.
3520 + */
3521 +int __init
3522 +init_mcf5445x_pci(void)
3523 +{
3524 + return 0;
3525 +#if 0
3526 + /*
3527 + * Initialize the PCI core
3528 + */
3529 +
3530 + /* arbitration controller */
3531 + MCF_PCIARB_PACR = MCF_PCIARB_PACR_INTMPRI |
3532 + MCF_PCIARB_PACR_EXTMPRI(0x0f) |
3533 + MCF_PCIARB_PACR_INTMINTEN |
3534 + MCF_PCIARB_PACR_EXTMINTEN(0x0f);
3535 +
3536 + /* pci pin assignment regs */
3537 + MCF_GPIO_PAR_PCI = MCF_GPIO_PAR_PCI_GNT0 |
3538 + MCF_GPIO_PAR_PCI_GNT1 |
3539 + MCF_GPIO_PAR_PCI_GNT2 |
3540 + MCF_GPIO_PAR_PCI_GNT3_GNT3 |
3541 + MCF_GPIO_PAR_PCI_REQ0 |
3542 + MCF_GPIO_PAR_PCI_REQ1 |
3543 + MCF_GPIO_PAR_PCI_REQ2 |
3544 + MCF_GPIO_PAR_PCI_REQ3_REQ3;
3545 +
3546 + /* target control reg */
3547 + MCF_PCI_PCITCR = MCF_PCI_PCITCR_P |
3548 + MCF_PCI_PCITCR_WCT(8);
3549 +
3550 + /* PCI MEM address */
3551 + MCF_PCI_PCIIW0BTAR = 0xA007A000;
3552 +
3553 + /* PCI MEM address */
3554 + MCF_PCI_PCIIW1BTAR = 0xA803A800;
3555 +
3556 + /* PCI IO address */
3557 + MCF_PCI_PCIIW2BTAR = 0xAC03AC00;
3558 +
3559 + /* window control */
3560 + MCF_PCI_PCIIWCR = MCF_PCI_PCIIWCR_WINCTRL0_ENABLE |
3561 + MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD |
3562 + MCF_PCI_PCIIWCR_WINCTRL1_ENABLE |
3563 + MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD |
3564 + MCF_PCI_PCIIWCR_WINCTRL2_ENABLE |
3565 + MCF_PCI_PCIIWCR_WINCTRL2_IO;
3566 +
3567 + /* initiator control reg */
3568 + MCF_PCI_PCIICR = 0x00ff;
3569 +
3570 + /* type 0 - command */
3571 + MCF_PCI_PCISCR = MCF_PCI_PCISCR_MW | /* mem write/inval */
3572 + MCF_PCI_PCISCR_B | /* bus master enable */
3573 + MCF_PCI_PCISCR_M; /* mem access enable */
3574 +
3575 + /* type 0 - config reg */
3576 + MCF_PCI_PCICR1 = MCF_PCI_PCICR1_CACHELINESIZE(8) |
3577 + MCF_PCI_PCICR1_LATTIMER(0xff);
3578 +
3579 + /* type 0 - config 2 reg */
3580 + MCF_PCI_PCICR2 = 0;
3581 +
3582 + /* target control reg */
3583 + MCF_PCI_PCITCR2 = MCF_PCI_PCITCR2_B0E |
3584 + MCF_PCI_PCITCR2_B4E;
3585 +
3586 + /* translate addresses from PCI[0] to CF[SDRAM] */
3587 + MCF_PCI_PCITBATR0 = MCF_RAMBAR1 | MCF_PCI_PCITBATR0_EN;
3588 + MCF_PCI_PCITBATR4 = MCF_RAMBAR1 | MCF_PCI_PCITBATR4_EN;
3589 +
3590 + /* setup controller interrupt handlers */
3591 + if (request_irq(55+128, mcf5445x_pci_interrupt, IRQF_SHARED,
3592 + "PCI Controller", NULL))
3593 + printk(KERN_ERR "PCI: Unable to register controller irq\n");
3594 +
3595 + if (request_irq (56+128, mcf5445x_pci_arb_interrupt, IRQF_SHARED, "PCI Arbiter", NULL))
3596 + printk(KERN_ERR "PCI: Unable to register arbiter irq\n");
3597 +
3598 + /* global control - clear reset bit */
3599 + MCF_PCI_PCIGSCR = MCF_PCI_PCIGSCR_SEE |
3600 + MCF_PCI_PCIGSCR_PEE;
3601 +
3602 + /* let everything settle */
3603 + udelay(1000);
3604 +
3605 + /* allocate bus ioport resource */
3606 + if (request_resource(&ioport_resource, &pci_ioport_resource) < 0)
3607 + printk(KERN_ERR "PCI: Unable to alloc ioport resource\n");
3608 +
3609 + /* allocate bus iomem resource */
3610 + if (request_resource(&iomem_resource, &pci_iomem_resource) < 0)
3611 + printk(KERN_ERR "PCI: Unable to alloc iomem resource\n");
3612 +
3613 + /* setup FPGA to route PCI to IRQ3(67), SW7 to IRQ7, SW6 to IRQ4 */
3614 + set_fpga(FPGA_PCI_IRQ_ENABLE, 0x00000000);
3615 + set_fpga(FPGA_PCI_IRQ_ROUTE, 0x00000039);
3616 + set_fpga(FPGA_SEVEN_LED, 0x000000FF);
3617 +
3618 + raw_pci_ops = &mcf5445x_pci_ops;
3619 +
3620 + return 0;
3621 +#endif
3622 +}
3623 +
3624 +/*
3625 + * DEBUGGING
3626 + */
3627 +
3628 +#ifdef DEBUG
3629 +struct regdump {
3630 + u32 addr;
3631 + char regname[16];
3632 +};
3633 +
3634 +struct regdump type0regs[] = {
3635 + { 0xfc0a8000, "PCIIDR" },
3636 + { 0xfc0a8004, "PCISCR" },
3637 + { 0xfc0a8008, "PCICCRIR" },
3638 + { 0xfc0a800c, "PCICR1" },
3639 + { 0xfc0a8010, "PCIBAR0" },
3640 + { 0xfc0a8014, "PCIBAR1" },
3641 + { 0xfc0a8018, "PCIBAR2" },
3642 + { 0xfc0a801c, "PCIBAR3" },
3643 + { 0xfc0a8020, "PCIBAR4" },
3644 + { 0xfc0a8024, "PCIBAR5" },
3645 + { 0xfc0a8028, "PCICCPR" },
3646 + { 0xfc0a802c, "PCISID" },
3647 + { 0xfc0a8030, "PCIERBAR" },
3648 + { 0xfc0a8034, "PCICPR" },
3649 + { 0xfc0a803c, "PCICR2" },
3650 + { 0, "" }
3651 +};
3652 +
3653 +struct regdump genregs[] = {
3654 + { 0xfc0a8060, "PCIGSCR" },
3655 + { 0xfc0a8064, "PCITBATR0" },
3656 + { 0xfc0a8068, "PCITBATR1" },
3657 + { 0xfc0a806c, "PCITCR1" },
3658 + { 0xfc0a8070, "PCIIW0BTAR" },
3659 + { 0xfc0a8074, "PCIIW1BTAR" },
3660 + { 0xfc0a8078, "PCIIW2BTAR" },
3661 + { 0xfc0a8080, "PCIIWCR" },
3662 + { 0xfc0a8084, "PCIICR" },
3663 + { 0xfc0a8088, "PCIISR" },
3664 + { 0xfc0a808c, "PCITCR2" },
3665 + { 0xfc0a8090, "PCITBATR0" },
3666 + { 0xfc0a8094, "PCITBATR1" },
3667 + { 0xfc0a8098, "PCITBATR2" },
3668 + { 0xfc0a809c, "PCITBATR3" },
3669 + { 0xfc0a80a0, "PCITBATR4" },
3670 + { 0xfc0a80a4, "PCITBATR5" },
3671 + { 0xfc0a80a8, "PCIINTR" },
3672 + { 0xfc0a80f8, "PCICAR" },
3673 + { 0, "" }
3674 +};
3675 +
3676 +struct regdump arbregs[] = {
3677 + { 0xfc0ac000, "PACR" },
3678 + { 0xfc0ac004, "PASR" }, /* documentation error */
3679 + { 0, "" }
3680 +};
3681 +
3682 +/*
3683 + * void mcf5445x_pci_dumpregs()
3684 + *
3685 + * Dump out all the PCI registers
3686 + */
3687 +void
3688 +mcf5445x_pci_dumpregs(void)
3689 +{
3690 + struct regdump *reg;
3691 +
3692 + printk(KERN_INFO "*** MCF5445x PCI TARGET 0 REGISTERS ***\n");
3693 +
3694 + reg = type0regs;
3695 + while (reg->addr) {
3696 + printk(KERN_INFO "0x%08x 0x%08x %s\n", reg->addr,
3697 + *((u32 *)reg->addr), reg->regname);
3698 + reg++;
3699 + }
3700 +
3701 + printk(KERN_INFO "\n*** MCF5445x PCI GENERAL REGISTERS ***\n");
3702 + reg = genregs;
3703 + while (reg->addr) {
3704 + printk(KERN_INFO "0x%08x 0x%08x %s\n", reg->addr,
3705 + *((u32 *)reg->addr), reg->regname);
3706 + reg++;
3707 + }
3708 + printk(KERN_INFO "\n*** MCF5445x PCI ARBITER REGISTERS ***\n");
3709 + reg = arbregs;
3710 + while (reg->addr) {
3711 + printk(KERN_INFO "0x%08x 0x%08x %s\n", reg->addr,
3712 + *((u32 *)reg->addr), reg->regname);
3713 + reg++;
3714 + }
3715 +}
3716 +#endif /* DEBUG */
3717 --- /dev/null
3718 +++ b/arch/m68k/coldfire/mcf548x-devices.c
3719 @@ -0,0 +1,94 @@
3720 +/*
3721 + * arch/m68k/coldfire/mcf5445x-devices.c
3722 + *
3723 + * Coldfire M5445x Platform Device Configuration
3724 + *
3725 + * Based on the Freescale MXC devices.c
3726 + *
3727 + * Copyright (c) 2007 Freescale Semiconductor, Inc.
3728 + * Kurt Mahan <kmahan@freescale.com>
3729 + */
3730 +#include <linux/module.h>
3731 +#include <linux/kernel.h>
3732 +#include <linux/init.h>
3733 +#include <linux/mtd/physmap.h>
3734 +#include <linux/platform_device.h>
3735 +#include <linux/fsl_devices.h>
3736 +
3737 +#include <asm/coldfire.h>
3738 +#include <asm/mcfsim.h>
3739 +
3740 +static struct resource coldfire_i2c_resources[] = {
3741 + [0] = { /* I/O */
3742 + .start = MCF_MBAR + 0x008F00,
3743 + .end = MCF_MBAR + 0x008F20,
3744 + .flags = IORESOURCE_MEM,
3745 + },
3746 + [2] = { /* IRQ */
3747 + .start = 40,
3748 + .end = 40,
3749 + .flags = IORESOURCE_IRQ,
3750 + },
3751 +};
3752 +
3753 +static struct platform_device coldfire_i2c_device = {
3754 + .name = "MCF548X-i2c",
3755 + .id = -1,
3756 + .num_resources = ARRAY_SIZE(coldfire_i2c_resources),
3757 + .resource = coldfire_i2c_resources,
3758 +};
3759 +
3760 +static struct resource coldfire_sec_resources[] = {
3761 + [0] = { /* I/O */
3762 + .start = MCF_MBAR + 0x00020000,
3763 + .end = MCF_MBAR + 0x00033000,
3764 + .flags = IORESOURCE_MEM,
3765 + },
3766 + [2] = { /* IRQ */
3767 + .start = ISC_SEC,
3768 + .end = ISC_SEC,
3769 + .flags = IORESOURCE_IRQ,
3770 + },
3771 +};
3772 +
3773 +static struct platform_device coldfire_sec_device = {
3774 + .name = "fsl-sec1",
3775 + .id = -1,
3776 + .num_resources = ARRAY_SIZE(coldfire_sec_resources),
3777 + .resource = coldfire_sec_resources,
3778 +};
3779 +
3780 +#if defined(CONFIG_MTD_PHYSMAP)
3781 +static struct physmap_flash_data mcf5485_flash_data = {
3782 + .width = 2,
3783 +};
3784 +
3785 +static struct resource mcf5485_flash_resource = {
3786 + .start = 0xf8000000,
3787 + .end = 0xf80fffff,
3788 + .flags = IORESOURCE_MEM,
3789 +};
3790 +
3791 +static struct platform_device mcf5485_flash_device = {
3792 + .name = "physmap-flash",
3793 + .id = 0,
3794 + .dev = {
3795 + .platform_data = &mcf5485_flash_data,
3796 + },
3797 + .num_resources = 1,
3798 + .resource = &mcf5485_flash_resource,
3799 +};
3800 +#endif
3801 +
3802 +static int __init mcf5485_init_devices(void)
3803 +{
3804 + printk(KERN_INFO "MCF5485x INIT_DEVICES\n");
3805 +
3806 + platform_device_register(&coldfire_i2c_device);
3807 + platform_device_register(&coldfire_sec_device);
3808 +/*#if defined(CONFIG_MTD_PHYSMAP)
3809 + platform_device_register(&mcf5485_flash_device);
3810 +#endif*/
3811 + return 0;
3812 +}
3813 +arch_initcall(mcf5485_init_devices);
3814 --- /dev/null
3815 +++ b/arch/m68k/coldfire/mcf548x-pci.c
3816 @@ -0,0 +1,959 @@
3817 +/*
3818 + * ColdFire 547x/548x PCI Host Controller functions
3819 + *
3820 + * Copyright (c) 2005-2008 Freescale Semiconductor, Inc.
3821 + *
3822 + * This code is based on the 2.6.10 version of pci.c
3823 + *
3824 + * This program is free software; you can redistribute it and/or modify
3825 + * it under the terms of the GNU General Public License as published by
3826 + * the Free Software Foundation; either version 2 of the License, or
3827 + * (at your option) any later version.
3828 + *
3829 + * This program is distributed in the hope that it will be useful,
3830 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3831 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3832 + * GNU General Public License for more details.
3833 + *
3834 + * You should have received a copy of the GNU General Public License
3835 + * along with this program; if not, write to the Free Software
3836 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
3837 + */
3838 +#include <linux/kernel.h>
3839 +#include <linux/types.h>
3840 +#include <linux/init.h>
3841 +#include <linux/mm.h>
3842 +#include <linux/string.h>
3843 +#include <linux/pci.h>
3844 +#include <linux/ioport.h>
3845 +#include <linux/slab.h>
3846 +#include <linux/version.h>
3847 +#include <linux/interrupt.h>
3848 +
3849 +#include <linux/dma-mapping.h>
3850 +#include <asm/coldfire.h>
3851 +#include <asm/io.h>
3852 +#include <asm/m5485sim.h>
3853 +#include <asm/m5485pci.h>
3854 +#include <asm/irq.h>
3855 +#include <asm/pci.h>
3856 +#include <asm/virtconvert.h>
3857 +
3858 +
3859 +#undef DEBUG
3860 +//#define DEBUG
3861 +
3862 +#ifdef DEBUG
3863 +//#define DBG(x...) printk(KERN_DEBUG x)
3864 +#define DBG(x...) printk(x)
3865 +#else
3866 +#define DBG(x...)
3867 +#endif
3868 +
3869 +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,5,75))
3870 +# define irqreturn_t void
3871 +# define IRQ_HANDLED
3872 +# define IRQ_NONE
3873 +#endif
3874 +
3875 +/*
3876 + * Bridge configration dafaults
3877 + */
3878 +#define PCI_RETRIES 0
3879 +#define PCI_CACHE_LINE 8
3880 +#define PCI_MINGNT 1
3881 +#define PCI_MAXLAT 42
3882 +
3883 +
3884 +/*
3885 + * Initiator windows setting
3886 + */
3887 +#define HOST_MEM_BASE 0xD0000000 /* ColdFire Memory window base */
3888 +#define PCI_MEM_BASE 0xD0000000 /* PCI Memory window base */
3889 +#define PCI_MEM_SIZE 0x08000000 /* Memory window size (128M) */
3890 +#define HOST_IO_BASE 0xD8000000 /* ColdFire I/O window base */
3891 +#define PCI_IO_BASE_ADDR 0x00000000 /* PCI I/O window base */
3892 +#define PCI_IO_SIZE 0x00010000 /* I/O window size (64K) */
3893 +#define HOST_CFG_BASE 0xD8000000 /* ColdFire config window base */
3894 +#define HOST_DMA_BASE CONFIG_SDRAM_BASE /* ColdFire PCI-DMA window base */
3895 +#define PCI_HDR_BASE (MCF_MBAR+0xB00)/* ColdFire config registers */
3896 +
3897 +#define PCI_MEM_MASK (PCI_MEM_SIZE-1)
3898 +#define PCI_IO_MASK (PCI_IO_SIZE-1)
3899 +
3900 +/* Macro to set initiator window */
3901 +#define WxBAR(host_address, pci_address, size) \
3902 + (((host_address) & 0xff000000) | \
3903 + ((((size)-1) & 0xff000000) >> 8) | \
3904 + ((pci_address) & 0xff000000) >> 16)
3905 +
3906 +/*
3907 + * BIOS internal data
3908 + */
3909 +static u8 revision; /* controller revision */
3910 +
3911 +/*
3912 + * Board specific setting
3913 + */
3914 +const unsigned int irq_lines[] = { 5, 7 };
3915 +
3916 +#define N_SLOTS (sizeof(board_info) / sizeof(board_info[0]))
3917 +#define N_IRQS (sizeof(irq_lines) / sizeof(irq_lines[0]))
3918 +#define BRIDGE_SLOT 0
3919 +
3920 +const struct slotinfo {
3921 + unsigned char idsel; /* device number */
3922 + unsigned char irq; /* external IRQ */
3923 + unsigned char req; /* REQ line number */
3924 + unsigned char gnt; /* GNT line number */
3925 +} board_info[] = {
3926 + {0, 0, 0, 0}, /* Bridge */
3927 + {17, 5, 1, 1}, /* Slot #1 */
3928 + {18, 5, 2, 2}, /* Slot #2 */
3929 + {20, 7, 3, 3}, /* Slot #3 */
3930 + {21, 7, 4, 4}, /* Slot #4 */
3931 +};
3932 +
3933 +/************************************************************************/
3934 +
3935 +/*
3936 + * static int mk_conf_addr()
3937 + *
3938 + * Return type0 or type1 configuration address
3939 + * by the means of device address and PCI dword location
3940 + * 0 - for not existing slots
3941 + */
3942 +static int mk_conf_addr(/*struct pci_dev *dev*/struct pci_bus *bus, unsigned int devfn, int where)
3943 +{
3944 + int slot, func, address, idsel, dev_fn;
3945 +
3946 + if (bus->number) {
3947 + address = MCF_PCICAR_E | (bus->number << 16) |
3948 + (devfn << 8) | (where & 0xfc);
3949 + } else {
3950 + slot = PCI_SLOT(devfn);
3951 + if (slot > N_SLOTS || slot == BRIDGE_SLOT)
3952 + return 0;
3953 + else {
3954 + func = PCI_FUNC(devfn);
3955 + idsel = board_info[slot].idsel;
3956 +
3957 + dev_fn = PCI_DEVFN(idsel, func);
3958 + address = MCF_PCICAR_E | (bus->number << 16) |
3959 + (dev_fn << 8) | (where & 0xfc);
3960 + }
3961 + }
3962 +
3963 + return (address);
3964 +}
3965 +
3966 +/*
3967 + * static int read_config_byte()
3968 + *
3969 + * Read a byte from configuration space of specified device
3970 + */
3971 +static int read_config_byte(/*struct pci_dev *dev*/struct pci_bus *bus, unsigned int devfn, int where, u8 *value)
3972 +{
3973 + int slot;
3974 + int address;
3975 + int result;
3976 +
3977 + *value = 0xff;
3978 + result = PCIBIOS_SUCCESSFUL;
3979 +
3980 + slot = PCI_SLOT(devfn);
3981 + if (slot == BRIDGE_SLOT) {
3982 + if (where <= 0x40)
3983 + *value = *(volatile u8 *) (PCI_HDR_BASE + (where ^ 3));
3984 + else
3985 + *value = 0;
3986 + } else {
3987 + address = mk_conf_addr(bus, devfn, where);
3988 + if (!address)
3989 + result = PCIBIOS_DEVICE_NOT_FOUND;
3990 + else {
3991 + MCF_PCICAR = address;
3992 + *value = *(volatile u8 *) (HOST_CFG_BASE + (where & 3));
3993 + }
3994 + }
3995 + __asm__ __volatile__("nop");
3996 + __asm__ __volatile__("nop");
3997 + MCF_PCICAR &= ~MCF_PCICAR_E;
3998 +
3999 + DBG("PCI: read_config_byte bus=%d, devfn=%d, addr=0x%02X, val=0x%02X, ret=%02X\n",
4000 + bus->number, devfn, where, *value, result);
4001 +
4002 + return (result);
4003 +}
4004 +
4005 +/*
4006 + * static int read_config_word()
4007 + *
4008 + * Read a word from configuration space of specified device
4009 + */
4010 +static int read_config_word(/*struct pci_dev *dev*/struct pci_bus *bus, unsigned int devfn, int where, u16 *value)
4011 +{
4012 + int slot;
4013 + int address;
4014 + int result;
4015 +
4016 + *value = 0xffff;
4017 + result = PCIBIOS_SUCCESSFUL;
4018 +
4019 + if (where & 0x1)
4020 + result = PCIBIOS_BAD_REGISTER_NUMBER;
4021 + else {
4022 + slot = PCI_SLOT(devfn);
4023 + if (slot == BRIDGE_SLOT) {
4024 + if (where <= 0x3f)
4025 + *value =
4026 + *(volatile u16 *) (PCI_HDR_BASE +
4027 + (where ^ 2));
4028 + else
4029 + *value = 0;
4030 + } else {
4031 + address = mk_conf_addr(bus, devfn, where);
4032 + if (!address)
4033 + result = PCIBIOS_DEVICE_NOT_FOUND;
4034 + else {
4035 + MCF_PCICAR = address;
4036 + *value = le16_to_cpu(*(volatile u16 *)
4037 + (HOST_CFG_BASE +
4038 + (where & 2)));
4039 + }
4040 + }
4041 + }
4042 + __asm__ __volatile__("nop");
4043 + __asm__ __volatile__("nop");
4044 + MCF_PCICAR &= ~MCF_PCICAR_E;
4045 +
4046 + DBG("PCI: read_config_word bus=%d, devfn=%d, addr=0x%02X, val=0x%04X ret=%02X\n",
4047 + bus->number, devfn, where, *value, result);
4048 +
4049 + return (result);
4050 +}
4051 +
4052 +/*
4053 + * static int read_config_dword()
4054 + *
4055 + * Read a long word from configuration space of specified device
4056 + */
4057 +static int read_config_dword(/*struct pci_dev *dev*/struct pci_bus *bus, unsigned int devfn, int where, u32 *value)
4058 +{
4059 + int slot;
4060 + int address;
4061 + int result;
4062 +
4063 + *value = 0xffffffff;
4064 + result = PCIBIOS_SUCCESSFUL;
4065 +
4066 + if (where & 0x3)
4067 + result = PCIBIOS_BAD_REGISTER_NUMBER;
4068 + else {
4069 + slot = PCI_SLOT(devfn);
4070 + if (slot == BRIDGE_SLOT) {
4071 + if (where <= 0x3d)
4072 + *value =
4073 + *(volatile u32 *) (PCI_HDR_BASE + where);
4074 + else
4075 + *value = 0;
4076 + __asm__ __volatile__("nop");
4077 + __asm__ __volatile__("nop");
4078 + } else {
4079 + address = mk_conf_addr(bus, devfn, where);
4080 + if (!address)
4081 + result = PCIBIOS_DEVICE_NOT_FOUND;
4082 + else {
4083 + MCF_PCICAR = address;
4084 + *value = le32_to_cpu(*(volatile u32 *)
4085 + (HOST_CFG_BASE));
4086 + __asm__ __volatile__("nop");
4087 + __asm__ __volatile__("nop");
4088 + if (bus->number != 0 && revision < 1) {
4089 + volatile u32 temp;
4090 +
4091 + MCF_PCICAR |= 0xff0000;
4092 + temp = *(volatile u32 *) (HOST_CFG_BASE);
4093 + }
4094 + }
4095 + }
4096 + }
4097 +
4098 + MCF_PCICAR &= ~MCF_PCICAR_E;
4099 +
4100 + DBG("PCI: read_config_dword bus=%d, devfn=%d, addr=0x%02X, value=0x%08X ret=%02X\n",
4101 + bus->number, devfn, where, *value, result);
4102 +
4103 + return (result);
4104 +}
4105 +
4106 +/*
4107 + * static int write_config_byte()
4108 + *
4109 + * Write a byte to configuration space of specified device
4110 + */
4111 +static int write_config_byte(/*struct pci_dev *dev*/struct pci_bus *bus, unsigned int devfn, int where, u8 value)
4112 +{
4113 + int slot;
4114 + int address;
4115 + int result;
4116 +
4117 + result = PCIBIOS_SUCCESSFUL;
4118 +
4119 + slot = PCI_SLOT(devfn);
4120 + if (slot == BRIDGE_SLOT) {
4121 + if (where <= 0x40)
4122 + *(volatile u8 *) (PCI_HDR_BASE + (where ^ 3)) = value;
4123 + } else {
4124 + address = mk_conf_addr(bus, devfn, where);
4125 + if (!address)
4126 + result = PCIBIOS_DEVICE_NOT_FOUND;
4127 + else {
4128 + MCF_PCICAR = address;
4129 + *(volatile u8 *) (HOST_CFG_BASE + (where & 3)) = value;
4130 + }
4131 + }
4132 + __asm__ __volatile__("nop");
4133 + __asm__ __volatile__("nop");
4134 + MCF_PCICAR &= ~MCF_PCICAR_E;
4135 +
4136 + DBG("PCI: write_config_byte bus=%d, devfn=%d, addr=0x%02X, value=0x%02X ret=%02X\n",
4137 + bus->number, devfn, where, value, result);
4138 +
4139 + return (result);
4140 +}
4141 +
4142 +/*
4143 + * static int write_config_word()
4144 + *
4145 + * Write a word to configuration space of specified device
4146 + */
4147 +static int write_config_word(/*struct pci_dev *dev*/struct pci_bus *bus, unsigned int devfn, int where, u16 value)
4148 +{
4149 + int slot;
4150 + int address;
4151 + int result;
4152 +
4153 + result = PCIBIOS_SUCCESSFUL;
4154 +
4155 + if (where & 0x1)
4156 + result = PCIBIOS_BAD_REGISTER_NUMBER;
4157 + else {
4158 + slot = PCI_SLOT(devfn);
4159 + if (slot == BRIDGE_SLOT) {
4160 + if (where <= 0x3f)
4161 + *(volatile u16 *) (PCI_HDR_BASE + (where ^ 2)) =
4162 + value;
4163 + } else {
4164 + address = mk_conf_addr(bus, devfn, where);
4165 + if (!address)
4166 + result = PCIBIOS_DEVICE_NOT_FOUND;
4167 + else {
4168 + MCF_PCICAR = address;
4169 + *(volatile u16 *) (HOST_CFG_BASE + (where & 2)) =
4170 + cpu_to_le16(value);
4171 + }
4172 + }
4173 + }
4174 + __asm__ __volatile__("nop");
4175 + __asm__ __volatile__("nop");
4176 + MCF_PCICAR &= ~MCF_PCICAR_E;
4177 +
4178 + DBG("PCI: write_config_word bus=%d, devfn=%d, addr=0x%02X, value=0x%04X ret=%02X\n",
4179 + bus->number, devfn, where, value, result);
4180 +
4181 + return (result);
4182 +}
4183 +
4184 +/*
4185 + * static int write_config_dword()
4186 + *
4187 + * Write a long word to configuration space of specified device
4188 + */
4189 +static int write_config_dword(/*struct pci_dev *dev*/struct pci_bus *bus, unsigned int devfn, int where, u32 value)
4190 +{
4191 + int slot;
4192 + int address;
4193 + int result;
4194 +
4195 + result = PCIBIOS_SUCCESSFUL;
4196 +
4197 + if (where & 0x3)
4198 + result = PCIBIOS_BAD_REGISTER_NUMBER;
4199 + else {
4200 + slot = PCI_SLOT(devfn);
4201 + if (slot == BRIDGE_SLOT) {
4202 + if (where <= 0x3d)
4203 + *(volatile u32 *) (PCI_HDR_BASE + where) =
4204 + value;
4205 + } else {
4206 + address = mk_conf_addr(bus, devfn, where);
4207 + if (!address)
4208 + result = PCIBIOS_DEVICE_NOT_FOUND;
4209 + else {
4210 + MCF_PCICAR = address;
4211 + *(volatile u32 *) (HOST_CFG_BASE) =
4212 + cpu_to_le32(value);
4213 + }
4214 + }
4215 + }
4216 + __asm__ __volatile__("nop");
4217 + __asm__ __volatile__("nop");
4218 + MCF_PCICAR &= ~MCF_PCICAR_E;
4219 +
4220 + DBG("PCI: write_config_dword dev=%d, fn=%d, addr=0x%02X, value=0x%08X ret=%02X\n",
4221 + PCI_SLOT(devfn), PCI_FUNC(devfn), where, value, result);
4222 +
4223 + return (result);
4224 +}
4225 +
4226 +static int config_read(struct pci_bus *bus, unsigned int devfn,
4227 + int where, int size, u32 * val)
4228 +{
4229 + switch (size) {
4230 + case 1:
4231 + return read_config_byte(bus, devfn, where, (u8 *) val);
4232 + case 2:
4233 + return read_config_word(bus, devfn, where, (u16 *) val);
4234 + default:
4235 + return read_config_dword(bus, devfn, where, val);
4236 + }
4237 +}
4238 +
4239 +static int config_write(struct pci_bus *bus, unsigned int devfn,
4240 + int where, int size, u32 val)
4241 +{
4242 + switch (size) {
4243 + case 1:
4244 + return write_config_byte(bus, devfn, where, (u8) val);
4245 + case 2:
4246 + return write_config_word(bus, devfn, where, (u16) val);
4247 + default:
4248 + return write_config_dword(bus, devfn, where, val);
4249 + }
4250 +}
4251 +
4252 +/*
4253 + * configuration routines entry points
4254 + */
4255 +static struct pci_ops bus_ops = {
4256 + read: config_read,
4257 + write: config_write
4258 +};
4259 +
4260 +/************************************************************************/
4261 +
4262 +/*
4263 + * u8 pci_inb()
4264 + *
4265 + * Read a byte at specified address from I/O space
4266 + */
4267 +unsigned char pci_inb(long addr)
4268 +{
4269 + char value;
4270 +
4271 + value = *(volatile unsigned char *) (HOST_IO_BASE | (addr & PCI_IO_MASK));
4272 + DBG("PCI: inb addr=0x%08X, value=0x%02X\n", addr, value);
4273 +
4274 + return (unsigned char) value;
4275 +}
4276 +
4277 +
4278 +/*
4279 + * u16 pci_inw()
4280 + *
4281 + * Read a word at specified address from I/O space
4282 + */
4283 +unsigned short pci_inw(long addr)
4284 +{
4285 + short value;
4286 + volatile unsigned short *ptr;
4287 +
4288 + ptr = (volatile unsigned short *) (HOST_IO_BASE | (addr & PCI_IO_MASK));
4289 + value = le16_to_cpu(*ptr);
4290 +
4291 + DBG("PCI: inw addr=0x%08X, value=0x%04X\n", addr, value);
4292 + return (unsigned short) value;
4293 +}
4294 +
4295 +/*
4296 + * u16 pci_raw_inw()
4297 + *
4298 + * Read a raw word at specified address from I/O space
4299 + */
4300 +unsigned short pci_raw_inw(long addr)
4301 +{
4302 + short value;
4303 + volatile unsigned short *ptr;
4304 +
4305 + ptr = (volatile unsigned short *) (HOST_IO_BASE | (addr & PCI_IO_MASK));
4306 + value = *ptr;
4307 +
4308 + DBG("PCI: raw_inw addr=0x%08X, value=0x%04X\n", addr, value);
4309 + return (unsigned short) value;
4310 +}
4311 +
4312 +/*
4313 + * u32 pci_inl()
4314 + *
4315 + * Read a dword at specified address from I/O space
4316 + */
4317 +unsigned long pci_inl(long addr)
4318 +{
4319 + long value;
4320 + volatile unsigned long *ptr;
4321 +
4322 + ptr = (volatile unsigned long *) (HOST_IO_BASE | (addr & PCI_IO_MASK));
4323 + value = le32_to_cpu(*ptr);
4324 +
4325 + DBG("PCI: inl addr=0x%08X, value=0x%08X\n", addr, value);
4326 + return (unsigned long) value;
4327 +}
4328 +
4329 +/*
4330 + * u32 pci_raw_inl()
4331 + *
4332 + * Read a raw dword at specified address from I/O space
4333 + */
4334 +unsigned long pci_raw_inl(long addr)
4335 +{
4336 + long value;
4337 + volatile unsigned long *ptr;
4338 +
4339 + ptr = (volatile unsigned long *) (HOST_IO_BASE | (addr & PCI_IO_MASK));
4340 + value = *ptr;
4341 +
4342 + DBG("PCI: raw_inl addr=0x%08X, value=0x%08X\n", addr, value);
4343 + return (unsigned long) value;
4344 +}
4345 +
4346 +/*
4347 + * void pci_outb()
4348 + *
4349 + * Write a byte value at specified address to I/O space
4350 + */
4351 +void pci_outb( unsigned char value, long addr)
4352 +{
4353 +
4354 + *(volatile unsigned char *) (HOST_IO_BASE | (addr & PCI_IO_MASK)) = value;
4355 + DBG("PCI: outb addr=0x%08X, value=0x%02X\n", addr, value);
4356 +}
4357 +
4358 +
4359 +/*
4360 + * void pci_outw()
4361 + *
4362 + * Write a word value at specified address to I/O space
4363 + */
4364 +void pci_outw(volatile unsigned short value, volatile long addr)
4365 +{
4366 + volatile unsigned short *ptr;
4367 +
4368 + ptr = (volatile unsigned short *) (HOST_IO_BASE | (addr & PCI_IO_MASK));
4369 + *ptr = cpu_to_le16(value);
4370 + DBG("PCI: outw addr=0x%08X, value=0x%04X\n", addr, value);
4371 +}
4372 +
4373 +/*
4374 + * void pci_raw_outw()
4375 + *
4376 + * Write a raw word value at specified address to I/O space
4377 + */
4378 +void pci_raw_outw(volatile unsigned short value, volatile long addr)
4379 +{
4380 + volatile unsigned short *ptr;
4381 +
4382 + ptr = (volatile unsigned short *) (HOST_IO_BASE | (addr & PCI_IO_MASK));
4383 + *ptr = value;
4384 + DBG("PCI: raw_outw addr=0x%08X, value=0x%04X\n", addr, value);
4385 +}
4386 +
4387 +/*
4388 + * void pci_outl()
4389 + *
4390 + * Write a long word value at specified address to I/O space
4391 + */
4392 +void pci_outl(volatile unsigned long value, volatile long addr)
4393 +{
4394 + volatile unsigned long *ptr;
4395 +
4396 + ptr = (volatile unsigned long *)(HOST_IO_BASE | (addr & PCI_IO_MASK));
4397 + *ptr = cpu_to_le32(value);
4398 + DBG("PCI: outl addr=0x%08X, value=0x%08X\n", addr, value);
4399 +}
4400 +
4401 +/*
4402 + * void pci_raw_outl()
4403 + *
4404 + * Write a raw long word value at specified address to I/O space
4405 + */
4406 +void pci_raw_outl(volatile unsigned long value, volatile long addr)
4407 +{
4408 + volatile unsigned long *ptr;
4409 +
4410 + ptr = (volatile unsigned long *)(HOST_IO_BASE | (addr & PCI_IO_MASK));
4411 + *ptr = value;
4412 + DBG("PCI: raw_outl addr=0x%08X, value=0x%08X\n", addr, value);
4413 +}
4414 +
4415 +/*
4416 + * void pci_insb()
4417 + *
4418 + * Read several byte values from specified I/O port
4419 + */
4420 +void pci_insb(volatile unsigned char *addr, unsigned char *buf, int len)
4421 +{
4422 + for (; len--; buf++)
4423 + *buf = pci_inb((unsigned long)addr);
4424 + DBG("PCI: pci_insb addr=0x%08X, buf=%p, len=%d\n", addr, buf, len);
4425 +}
4426 +
4427 +
4428 +/*
4429 + * void pci_insw()
4430 + *
4431 + * Read several word values from specified I/O port
4432 + */
4433 +void pci_insw(volatile unsigned short *addr, unsigned short *buf, int len)
4434 +{
4435 + for (; len--; buf++)
4436 + *buf = pci_inw((unsigned long)addr);
4437 + DBG("PCI: pci_insw addr=0x%08X, buf=%p, len=%d\n", addr, buf, len);
4438 +}
4439 +
4440 +/*
4441 + * void pci_insl()
4442 + *
4443 + * Read several dword values from specified I/O port
4444 + */
4445 +void pci_insl(volatile unsigned long *addr, unsigned long *buf, int len)
4446 +{
4447 + for (; len--; buf++)
4448 + *buf = pci_inl((unsigned long)addr);
4449 + DBG("PCI: pci_insl addr=0x%08X, buf=%p, len=%d\n", addr, buf, len);
4450 +}
4451 +
4452 +/*
4453 + * void pci_outsb()
4454 + *
4455 + * Write several byte values to specified I/O port
4456 + */
4457 +void pci_outsb(volatile unsigned char *addr, const unsigned char *buf, int len)
4458 +{
4459 + for (; len--; buf++)
4460 + pci_outb((unsigned long)addr, *buf);
4461 + DBG("PCI: pci_outsb addr=0x%08X, buf=%p, len=%d\n", addr, buf, len);
4462 +}
4463 +
4464 +/*
4465 + * void pci_outsw()
4466 + *
4467 + * Write several word values to specified I/O port
4468 + */
4469 +void pci_outsw(volatile unsigned short *addr, const unsigned short *buf, int len)
4470 +{
4471 + for (; len--; buf++)
4472 + pci_outw((unsigned long)addr, *buf);
4473 + DBG("PCI: pci_outsw addr=0x%08X, buf=%p, len=%d\n", addr, buf, len);
4474 +}
4475 +
4476 +/*
4477 + * void pci_outsl()
4478 + *
4479 + * Write several dword values to specified I/O port
4480 + */
4481 +void pci_outsl(volatile unsigned long *addr, const unsigned long *buf, int len)
4482 +{
4483 + for (; len--; buf++)
4484 + pci_outl((unsigned long)addr, *buf);
4485 + DBG("PCI: pci_outsl addr=0x%08X, buf=%p, len=%d\n", addr, buf, len);
4486 +}
4487 +
4488 +/*
4489 + * void pci_xlb_handler()
4490 + *
4491 + * PCI XLB interrupt handler
4492 + */
4493 +irqreturn_t xlb_interrupt(int irq, void *dev)
4494 +{
4495 + volatile int xlb_error = MCF_PCIISR;
4496 +
4497 + /* Acknowlege interrupt */
4498 + MCF_PCIISR = xlb_error;
4499 +
4500 + /* Dump interrupt reason */
4501 + if (xlb_error & MCF_PCIISR_RE)
4502 + DBG("PCI: Retry Error Received\n");
4503 +
4504 + if (xlb_error & MCF_PCIISR_IA)
4505 + DBG("PCI: Initiator Abort Received\n");
4506 +
4507 + if (xlb_error & MCF_PCIISR_TA)
4508 + DBG("PCI: Target Abort Received\n");
4509 +
4510 + return IRQ_HANDLED;
4511 +}
4512 +
4513 +
4514 +/*
4515 + * void pci_arbiter_handler()
4516 + *
4517 + * PCI arbiter interrupt handler
4518 + */
4519 +irqreturn_t arb_interrupt(int irq, void *dev)
4520 +{
4521 + volatile unsigned long arb_error = MCF_PCIARB_PASR;
4522 +
4523 + /* Acknowlege interrupt */
4524 + printk("%s\n",__FUNCTION__);
4525 + MCF_PCIARB_PASR = arb_error;
4526 +
4527 + if (arb_error & MCF_PCIARB_PASR_ITLMBK) {
4528 + DBG("PCI: coldfire master time-out\n");
4529 +
4530 + /* Set infinite number of retries */
4531 + MCF_PCIICR &= ~0xFF;
4532 + }
4533 +
4534 + if (arb_error & MCF_PCIARB_PASR_EXTMBK(0x1F)) {
4535 + arb_error >>= 17;
4536 + DBG("PCI: external master time-out (mask = 0x%X)\n", arb_error);
4537 +
4538 + /* raise arbitration priority level */
4539 + MCF_PCIARB_PACR = MCF_PCIARB_PACR_EXTMPRI(arb_error);
4540 + }
4541 +
4542 + return IRQ_HANDLED;
4543 +}
4544 +
4545 +
4546 +/*
4547 + * void pci_eint_handler()
4548 + *
4549 + * Eport interrupt handler
4550 + */
4551 +irqreturn_t eint_handler(int irq, void *dev)
4552 +{
4553 + /* Just acknowlege interrupt and exit */
4554 + MCF_EPFR = 0x1 << (irq - 64);
4555 + return IRQ_HANDLED;
4556 +}
4557 +
4558 +
4559 +/*
4560 + * void __init coldfire_fixup(int pci_modify)
4561 + *
4562 + * Assign IRQ numbers as used by Linux to the interrupt pins
4563 + * of the PCI cards.
4564 + */
4565 +static void __init coldfire_fixup(int pci_modify)
4566 +{
4567 + struct pci_dev *dev;
4568 + unsigned char slot, pin;
4569 +
4570 + DBG("%s\n",__FUNCTION__);
4571 +#ifdef NL_ORIGINAL
4572 + pci_for_each_dev(dev) {
4573 +#else
4574 + dev = NULL;
4575 + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
4576 +#endif
4577 + if (dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) {
4578 + slot = PCI_SLOT(dev->devfn);
4579 + dev->irq = 64 + board_info[slot].irq;
4580 +
4581 + /* Check if device needs interrupt */
4582 +#ifdef NL_ORIGINAL
4583 + pcibios_read_config_byte(
4584 + dev->bus->number, dev->devfn,
4585 + PCI_INTERRUPT_PIN, &pin);
4586 +
4587 + if ( pin ) {
4588 + pcibios_write_config_byte(
4589 + dev->bus->number, dev->devfn,
4590 + PCI_INTERRUPT_LINE, dev->irq);
4591 + }
4592 +#else
4593 + pci_read_config_byte(dev,
4594 + PCI_INTERRUPT_PIN, &pin);
4595 +
4596 + if ( pin ) {
4597 + pci_write_config_byte(dev,
4598 + PCI_INTERRUPT_LINE, dev->irq);
4599 + }
4600 +#endif
4601 + }
4602 + }
4603 +}
4604 +
4605 +static void __init configure_device(struct pci_dev *dev)
4606 +{
4607 + /* TODO: This should depend from disable_pci_burst setting */
4608 + DBG("%s\n",__FUNCTION__);
4609 +#ifdef NL_ORIGINAL
4610 + pcibios_write_config_byte(bus, devfn, PCI_CACHE_LINE_SIZE, PCI_CACHE_LINE);
4611 +#else
4612 + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, PCI_CACHE_LINE);
4613 +#endif
4614 +}
4615 +
4616 +struct pci_bus_info *__init init_coldfire_pci(void)
4617 +{
4618 + static struct pci_bus_info bus;
4619 + int i;
4620 + int pci_mem_va;
4621 + static char irq_name[N_IRQS][15];
4622 +
4623 + /* Get controller revision */
4624 + revision = MCF_PCICCRIR;
4625 + printk("ColdFire PCI Host Bridge (Rev. %d) detected:"
4626 + "MEMBase %x,MEMLen %x,IOBase %x,IOLen %x\n",
4627 + revision, HOST_MEM_BASE, PCI_MEM_SIZE - 1, 0, PCI_IO_SIZE - 1);
4628 +
4629 + /* Setup bus info structure. */
4630 + memset(&bus, 0, sizeof (struct pci_bus_info));
4631 +
4632 + /* Request intiator memory resource */
4633 + bus.mem_space.start = PCI_MEM_BASE;//HOST_MEM_BASE;
4634 + bus.mem_space.end = bus.mem_space.start + PCI_MEM_SIZE - 1;
4635 + bus.mem_space.name = "PCI Bus #0";
4636 + if (request_resource(&iomem_resource, &bus.mem_space) != 0)
4637 + {
4638 + printk("Failed to request bridge iomem resource\n");
4639 + return NULL;
4640 + }
4641 +
4642 + /* Request intiator memory resource */
4643 + bus.io_space.start = 0;
4644 + bus.io_space.end = bus.io_space.start + PCI_IO_SIZE - 1;
4645 + bus.io_space.name = "PCI Bus #0";
4646 + if (request_resource(&ioport_resource, &bus.io_space) != 0)
4647 + {
4648 + printk("Failed to request bridge ioport resource\n");
4649 + return NULL;
4650 + }
4651 +
4652 + /* Must Reset!!! If bootloader has PCI enabled, it will cause
4653 + * problem in linux when it tries to configure/find resources
4654 + * for the pci devices. Both registers need to be reset.
4655 + */
4656 + MCF_PCIGSCR = 0x1;
4657 + MCF_PCITCR = 0x00000000;
4658 +
4659 + /* Set up the arbiter */
4660 + MCF_PCIARB_PACR = 0 /*MCF_PCIARB_PACR_PKMD*/
4661 + | MCF_PCIARB_PACR_INTMPRI
4662 + | MCF_PCIARB_PACR_INTMINTEN
4663 + | MCF_PCIARB_PACR_EXTMPRI(0x1F)
4664 + | MCF_PCIARB_PACR_EXTMINTEN(0x1F);
4665 +
4666 + /* GNT and REQ */
4667 + MCF_PAR_PCIBG = 0x3FF;
4668 + MCF_PAR_PCIBR = 0x3FF;
4669 +
4670 + /* Enable bus mastering, memory access and MWI */
4671 + MCF_PCISCR = MCF_PCISCR_B | MCF_PCISCR_M | MCF_PCISCR_MW;
4672 +
4673 + /* Setup burst parameters */
4674 + MCF_PCICR1 = MCF_PCICR1_LATTIMER(32) |
4675 + MCF_PCICR1_CACHELINESIZE(PCI_CACHE_LINE);
4676 +
4677 + MCF_PCICR2 = 0;
4678 + /*MCF_PCICR2_MINGNT(PCI_MINGNT) |
4679 + MCF_PCICR2_MAXLAT(PCI_MAXLAT);
4680 + */
4681 + /* Turn on error signaling */
4682 + MCF_PCIICR = MCF_PCIICR_TAE | MCF_PCIICR_IAE | PCI_RETRIES;
4683 + MCF_PCIGSCR |= MCF_PCIGSCR_SEE;
4684 + /*
4685 + * Configure Initiator Windows
4686 + * Window 0: 128M PCI Memory @ HOST_MEM_BASE, 1:1 mapping
4687 + * Window 1: 64K I/O Memory @ HOST_IO_BASE, 1:0 mapping
4688 + */
4689 + MCF_PCIIW0BTAR = WxBAR(HOST_MEM_BASE, PCI_MEM_BASE, PCI_MEM_SIZE);
4690 + MCF_PCIIW1BTAR = WxBAR(HOST_IO_BASE, PCI_IO_BASE_ADDR, PCI_IO_SIZE);
4691 +
4692 + MCF_PCIIWCR = MCF_PCIIWCR_WINCTRL1_IO |
4693 + MCF_PCIIWCR_WINCTRL0_MEMRDLINE;
4694 +
4695 + /* Target PCI DMA Windows */
4696 + MCF_PCIBAR1 = PCI_DMA_BASE;
4697 + MCF_PCITBATR1 = HOST_DMA_BASE | MCF_PCITBATR1_EN;
4698 + MCF_PCIBAR0 = MCF_RAMBAR0;;
4699 + MCF_PCITBATR0 = MCF_RAMBAR0 | MCF_PCITBATR0_EN;
4700 + DBG("PCI TCR %x,MCF_PCIBAR1 %x,MCF_PCITBATR1 %x."
4701 + "MCF_PCIBAR0 %x,MCF_PCITBATR9 %x\n", MCF_PCITCR, MCF_PCIBAR1,
4702 + MCF_PCITBATR1, MCF_PCIBAR0, MCF_PCITBATR0);
4703 + /* Enable internal PCI controller interrupts */
4704 + MCF_ICR(ISC_PCI_XLB) = ILP_PCI_XLB;
4705 + /*request_irq(64+ISC_PCI_XLB, xlb_interrupt,
4706 + SA_INTERRUPT, "PCI XL Bus", (void*)-1);
4707 + enable_irq (64+ISC_PCI_XLB);
4708 + */
4709 + if(request_irq(64+ISC_PCI_XLB, xlb_interrupt,
4710 + IRQF_DISABLED, "PCI XL Bus", (void*)-1)){
4711 + printk("Cannot allocate ISC_PCI_XLB IRQ\n");
4712 + return (struct pci_bus_info *)-EBUSY;
4713 + }
4714 +
4715 + MCF_ICR(ISC_PCI_ARB) = ILP_PCI_ARB;
4716 + /*request_irq(64+ISC_PCI_ARB, arb_interrupt,
4717 + SA_INTERRUPT, "PCI Arbiter", (void*)-1);
4718 + enable_irq (64+ISC_PCI_ARB);
4719 + */
4720 + if(request_irq(64+ISC_PCI_ARB, arb_interrupt,
4721 + IRQF_DISABLED, "PCI Arbiter", (void*)-1)){
4722 + printk("Cannot allocate ISC_PCI_ARB IRQ\n");
4723 + return (struct pci_bus_info *)-EBUSY;
4724 + }
4725 +
4726 + /* Set slots interrupt setting */
4727 + for (i = 0; i < N_IRQS; i++)
4728 + {
4729 + /* Set trailing edge for PCI interrupts */
4730 + MCF_EPPAR &= ~MCF_EPPAR_EPPA(irq_lines[i], 0x3);
4731 + if (irq_lines[i] == 5)
4732 + MCF_EPPAR |= MCF_EPPAR_EPPA(irq_lines[i], MCF_EPPAR_EPPAx_FALLING);
4733 + else
4734 + MCF_EPPAR |= MCF_EPPAR_EPPA(irq_lines[i], 0/*MCF_EPPAR_EPPAx_FALLING*/);
4735 + /* Turn on irq line in eport */
4736 + MCF_EPIER |= MCF_EPIER_EPIE(irq_lines[i]);
4737 +
4738 + /* Enable irq in gpio */
4739 + if (irq_lines[i] == 5)
4740 + MCF_PAR_FECI2CIRQ |= 1;
4741 +
4742 + if (irq_lines[i] == 6)
4743 + MCF_PAR_FECI2CIRQ |= 2;
4744 +
4745 + /* Register external interrupt handlers */
4746 + sprintf(irq_name[i], "PCI IRQ%d", irq_lines[i]);
4747 + /*request_irq(64 + irq_lines[i], eint_handler,
4748 + SA_SHIRQ, irq_name[i], (void*)-1);
4749 + enable_irq(64 + irq_lines[i]);*/
4750 + if(request_irq(64 + irq_lines[i], eint_handler,
4751 + IRQF_SHARED, irq_name[i], (void*)-1)){
4752 + printk("Cannot allocate irq_lines[%d] IRQ\n", irq_lines[i]);
4753 + return (struct pci_bus_info *)-EBUSY;
4754 + }
4755 + }
4756 +
4757 + /* Clear PCI Reset and wait for devices to reset */
4758 + MCF_PCIGSCR &= ~MCF_PCIGSCR_PR;
4759 + schedule_timeout((5 * HZ) / 10);
4760 + /* Remap initiator windows (should be 1:1 to the physical memory) */
4761 + pci_mem_va = (int) ioremap_nocache(HOST_MEM_BASE, PCI_MEM_SIZE + PCI_IO_SIZE);
4762 +#if 1
4763 + printk("%s: MEMBase_phy %x, Virt %x, len %x\n",__FUNCTION__,
4764 + HOST_MEM_BASE,pci_mem_va,PCI_MEM_SIZE + PCI_IO_SIZE);
4765 +#endif
4766 + BUG_ON(pci_mem_va != HOST_MEM_BASE);
4767 +
4768 + /* Setup bios32 and pci bus driver callbacks */
4769 + bus.m68k_pci_ops = &bus_ops;
4770 + bus.fixup = coldfire_fixup;
4771 + bus.conf_device = configure_device;
4772 +
4773 + return &bus;
4774 +}
4775 +
4776 --- /dev/null
4777 +++ b/arch/m68k/coldfire/muldi3.S
4778 @@ -0,0 +1,64 @@
4779 +/*
4780 + * Coldfire muldi3 assembly verion
4781 + */
4782 +
4783 +#include <linux/linkage.h>
4784 +.globl __muldi3
4785 +
4786 +ENTRY(__muldi3)
4787 + linkw %fp,#0
4788 + lea %sp@(-32),%sp
4789 + moveml %d2-%d7/%a2-%a3,%sp@
4790 + moveal %fp@(8), %a2
4791 + moveal %fp@(12), %a3
4792 + moveal %fp@(16), %a0
4793 + moveal %fp@(20),%a1
4794 + movel %a3,%d2
4795 + andil #65535,%d2
4796 + movel %a3,%d3
4797 + clrw %d3
4798 + swap %d3
4799 + movel %a1,%d0
4800 + andil #65535,%d0
4801 + movel %a1,%d1
4802 + clrw %d1
4803 + swap %d1
4804 + movel %d2,%d7
4805 + mulsl %d0,%d7
4806 + movel %d2,%d4
4807 + mulsl %d1,%d4
4808 + movel %d3,%d2
4809 + mulsl %d0,%d2
4810 + mulsl %d1,%d3
4811 + movel %d7,%d0
4812 + clrw %d0
4813 + swap %d0
4814 + addl %d0,%d4
4815 + addl %d2,%d4
4816 + cmpl %d4,%d2
4817 + blss 1f
4818 + addil #65536,%d3
4819 +1:
4820 + movel %d4,%d0
4821 + clrw %d0
4822 + swap %d0
4823 + movel %d3,%d5
4824 + addl %d0,%d5
4825 + movew %d4,%d6
4826 + swap %d6
4827 + movew %d7,%d6
4828 + movel %d5,%d0
4829 + movel %d6,%d1
4830 + movel %a3,%d2
4831 + movel %a0,%d3
4832 + mulsl %d3,%d2
4833 + movel %a2,%d3
4834 + movel %a1,%d4
4835 + mulsl %d4,%d3
4836 + addl %d3,%d2
4837 + movel %d2,%d0
4838 + addl %d5,%d0
4839 + moveml %sp@, %d2-%d7/%a2-%a3
4840 + lea %sp@(32),%sp
4841 + unlk %fp
4842 + rts
4843 --- /dev/null
4844 +++ b/arch/m68k/coldfire/pci.c
4845 @@ -0,0 +1,245 @@
4846 +/*
4847 + * linux/arch/m68k/coldfire/pci.c
4848 + *
4849 + * PCI initialization for Coldfire architectures.
4850 + *
4851 + * Currently Supported:
4852 + * M5445x
4853 + *
4854 + * Copyright (c) 2007 Freescale Semiconductor, Inc.
4855 + * Kurt Mahan <kmahan@freescale.com>
4856 + */
4857 +
4858 +#include <linux/kernel.h>
4859 +#include <linux/init.h>
4860 +#include <linux/pci.h>
4861 +
4862 +#include <asm/mcfsim.h>
4863 +#include <asm/pci.h>
4864 +
4865 +/* pci ops for reading/writing config */
4866 +struct pci_raw_ops *raw_pci_ops;
4867 +
4868 +/* pci debug flag */
4869 +static int debug_pci;
4870 +
4871 +#ifdef CONFIG_M54455
4872 +extern int init_mcf5445x_pci(void);
4873 +extern void mcf5445x_conf_device(struct pci_dev *dev);
4874 +extern void mcf5445x_pci_dumpregs(void);
4875 +
4876 +extern struct resource pci_ioport_resource;
4877 +extern struct resource pci_iomem_resource;
4878 +#endif
4879 +
4880 +static int
4881 +pci_read(struct pci_bus *bus, unsigned int devfn, int where,
4882 + int size, u32 *value)
4883 +{
4884 + return raw_pci_ops->read(0, bus->number, devfn, where, size, value);
4885 +}
4886 +
4887 +static int
4888 +pci_write(struct pci_bus *bus, unsigned int devfn, int where,
4889 + int size, u32 value)
4890 +{
4891 + return raw_pci_ops->write(0, bus->number, devfn, where, size, value);
4892 +}
4893 +
4894 +struct pci_ops pci_root_ops = {
4895 + .read = pci_read,
4896 + .write = pci_write,
4897 +};
4898 +
4899 +/*
4900 + * pcibios_setup(char *)
4901 + *
4902 + * Initialize the pcibios based on cmd line params.
4903 + */
4904 +char *
4905 +pcibios_setup(char *str)
4906 +{
4907 + if (!strcmp(str, "debug")) {
4908 + debug_pci = 1;
4909 + return NULL;
4910 + }
4911 + return str;
4912 +}
4913 +
4914 +/*
4915 + * We need to avoid collisions with `mirrored' VGA ports
4916 + * and other strange ISA hardware, so we always want the
4917 + * addresses to be allocated in the 0x000-0x0ff region
4918 + * modulo 0x400.
4919 + *
4920 + * Why? Because some silly external IO cards only decode
4921 + * the low 10 bits of the IO address. The 0x00-0xff region
4922 + * is reserved for motherboard devices that decode all 16
4923 + * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
4924 + * but we want to try to avoid allocating at 0x2900-0x2bff
4925 + * which might have be mirrored at 0x0100-0x03ff..
4926 + */
4927 +void
4928 +pcibios_align_resource(void *data, struct resource *res, resource_size_t size,
4929 + resource_size_t align)
4930 +{
4931 + struct pci_dev *dev = data;
4932 +
4933 + if (res->flags & IORESOURCE_IO) {
4934 + resource_size_t start = res->start;
4935 +
4936 + if (size > 0x100)
4937 + printk(KERN_ERR "PCI: I/O Region %s/%d too large"
4938 + " (%ld bytes)\n", pci_name(dev),
4939 + dev->resource - res, (long int)size);
4940 +
4941 + if (start & 0x300) {
4942 + start = (start + 0x3ff) & ~0x3ff;
4943 + res->start = start;
4944 + }
4945 + }
4946 +}
4947 +
4948 +/*
4949 + * Swizzle the device pin each time we cross a bridge
4950 + * and return the slot number.
4951 + */
4952 +static u8 __devinit
4953 +pcibios_swizzle(struct pci_dev *dev, u8 *pin)
4954 +{
4955 + return 0;
4956 +}
4957 +
4958 +/*
4959 + * Map a slot/pin to an IRQ.
4960 + */
4961 +static int
4962 +pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
4963 +{
4964 + return 0x43;
4965 +}
4966 +
4967 +/*
4968 + * pcibios_update_irq(struct pci_dev *dev, int irq)
4969 + *
4970 + * Update a PCI interrupt.
4971 + */
4972 +void
4973 +pcibios_update_irq(struct pci_dev *dev, int irq)
4974 +{
4975 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
4976 +}
4977 +
4978 +/*
4979 + * pcibios_enable_device(struct pci_dev *dev, int mask)
4980 + *
4981 + * Enable a device on the PCI bus.
4982 + */
4983 +int
4984 +pcibios_enable_device(struct pci_dev *dev, int mask)
4985 +{
4986 + u16 cmd, old_cmd;
4987 + int idx;
4988 + struct resource *r;
4989 +
4990 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
4991 + old_cmd = cmd;
4992 + for (idx = 0; idx < 6; idx++) {
4993 + r = &dev->resource[idx];
4994 + if (!r->start && r->end) {
4995 + printk(KERN_ERR "PCI: Device %s not available because "
4996 + "of resource collisions\n", pci_name(dev));
4997 + return -EINVAL;
4998 + }
4999 + if (r->flags & IORESOURCE_IO)
5000 + cmd |= PCI_COMMAND_IO;
5001 + if (r->flags & IORESOURCE_MEM)
5002 + cmd |= PCI_COMMAND_MEMORY;
5003 + }
5004 + if (cmd != old_cmd) {
5005 + printk("PCI: Enabling device %s (%04x -> %04x)\n",
5006 + pci_name(dev), old_cmd, cmd);
5007 + pci_write_config_word(dev, PCI_COMMAND, cmd);
5008 +#ifdef CONFIG_M54455
5009 + mcf5445x_conf_device(dev);
5010 +#endif
5011 + }
5012 +
5013 + return 0;
5014 +}
5015 +
5016 +/*
5017 + * pcibios_fixup_bus(struct pci_bus *bus)
5018 + */
5019 +void
5020 +pcibios_fixup_bus(struct pci_bus *bus)
5021 +{
5022 + struct pci_dev *dev = bus->self;
5023 +
5024 + if (!dev) {
5025 + /* Root bus. */
5026 +#ifdef CONFIG_M54455
5027 + bus->resource[0] = &pci_ioport_resource;
5028 + bus->resource[1] = &pci_iomem_resource;
5029 +#endif
5030 + }
5031 +}
5032 +
5033 +/*
5034 + * pcibios_init(void)
5035 + *
5036 + * Allocate/initialize low level pci bus/devices.
5037 + */
5038 +static int __init
5039 +pcibios_init(void)
5040 +{
5041 + struct pci_bus *bus;
5042 +
5043 + if (!raw_pci_ops) {
5044 + printk(KERN_WARNING "PCIBIOS: FATAL: NO PCI Hardware found\n");
5045 + return 0;
5046 + }
5047 +
5048 + /* allocate and scan the (only) bus */
5049 + bus = pci_scan_bus_parented(NULL, 0, &pci_root_ops, NULL);
5050 +
5051 + /* setup everything */
5052 + if (bus) {
5053 + /* compute the bridge window sizes */
5054 + pci_bus_size_bridges(bus);
5055 +
5056 + /* (re)assign device resources */
5057 + pci_bus_assign_resources(bus);
5058 +
5059 + /* add the bus to the system */
5060 + pci_bus_add_devices(bus);
5061 +
5062 + /* fixup irqs */
5063 + pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq);
5064 + }
5065 +
5066 + return 0;
5067 +}
5068 +
5069 +/*
5070 + * pci_init(void)
5071 + *
5072 + * Initialize the PCI Hardware.
5073 + */
5074 +static int __init
5075 +pci_init(void)
5076 +{
5077 +#if defined(CONFIG_M54455)
5078 + init_mcf5445x_pci();
5079 +#endif
5080 + if (!raw_pci_ops)
5081 + printk(KERN_ERR "PCI: FATAL: NO PCI Detected\n");
5082 +
5083 + return 0;
5084 +}
5085 +
5086 +/* low level hardware (first) */
5087 +arch_initcall(pci_init);
5088 +
5089 +/* basic bios init (second) */
5090 +subsys_initcall(pcibios_init);
5091 --- /dev/null
5092 +++ b/arch/m68k/coldfire/signal.c
5093 @@ -0,0 +1,871 @@
5094 +/*
5095 + * linux/arch/m68k/kernel/signal.c
5096 + *
5097 + * Copyright (C) 1991, 1992 Linus Torvalds
5098 + *
5099 + * This file is subject to the terms and conditions of the GNU General Public
5100 + * License. See the file COPYING in the main directory of this archive
5101 + * for more details.
5102 + */
5103 +
5104 +/*
5105 + * Derived from m68k/kernel/signal.c and the original authors are credited
5106 + * there.
5107 + *
5108 + * Coldfire support by:
5109 + * Matt Waddel Matt.Waddel@freescale.com
5110 + * Copyright Freescale Semiconductor, Inc 2007
5111 + */
5112 +
5113 +#include <linux/sched.h>
5114 +#include <linux/mm.h>
5115 +#include <linux/kernel.h>
5116 +#include <linux/signal.h>
5117 +#include <linux/syscalls.h>
5118 +#include <linux/errno.h>
5119 +#include <linux/wait.h>
5120 +#include <linux/ptrace.h>
5121 +#include <linux/unistd.h>
5122 +#include <linux/stddef.h>
5123 +#include <linux/highuid.h>
5124 +#include <linux/personality.h>
5125 +#include <linux/tty.h>
5126 +#include <linux/binfmts.h>
5127 +
5128 +#include <asm/setup.h>
5129 +#include <asm/cf_uaccess.h>
5130 +#include <asm/cf_pgtable.h>
5131 +#include <asm/traps.h>
5132 +#include <asm/ucontext.h>
5133 +#include <asm/cacheflush.h>
5134 +
5135 +#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
5136 +
5137 +asmlinkage int do_signal(sigset_t *oldset, struct pt_regs *regs);
5138 +
5139 +const int frame_extra_sizes[16] = {
5140 + [1] = -1,
5141 + [2] = sizeof(((struct frame *)0)->un.fmt2),
5142 + [3] = sizeof(((struct frame *)0)->un.fmt3),
5143 + [4] = 0,
5144 + [5] = -1,
5145 + [6] = -1,
5146 + [7] = sizeof(((struct frame *)0)->un.fmt7),
5147 + [8] = -1,
5148 + [9] = sizeof(((struct frame *)0)->un.fmt9),
5149 + [10] = sizeof(((struct frame *)0)->un.fmta),
5150 + [11] = sizeof(((struct frame *)0)->un.fmtb),
5151 + [12] = -1,
5152 + [13] = -1,
5153 + [14] = -1,
5154 + [15] = -1,
5155 +};
5156 +
5157 +/*
5158 + * Atomically swap in the new signal mask, and wait for a signal.
5159 + */
5160 +asmlinkage int do_sigsuspend(struct pt_regs *regs)
5161 +{
5162 + old_sigset_t mask = regs->d3;
5163 + sigset_t saveset;
5164 +
5165 + mask &= _BLOCKABLE;
5166 + spin_lock_irq(&current->sighand->siglock);
5167 + saveset = current->blocked;
5168 + siginitset(&current->blocked, mask);
5169 + recalc_sigpending();
5170 + spin_unlock_irq(&current->sighand->siglock);
5171 +
5172 + regs->d0 = -EINTR;
5173 + while (1) {
5174 + current->state = TASK_INTERRUPTIBLE;
5175 + schedule();
5176 + if (do_signal(&saveset, regs))
5177 + return -EINTR;
5178 + }
5179 +}
5180 +
5181 +asmlinkage int
5182 +do_rt_sigsuspend(struct pt_regs *regs)
5183 +{
5184 + sigset_t __user *unewset = (sigset_t __user *)regs->d1;
5185 + size_t sigsetsize = (size_t)regs->d2;
5186 + sigset_t saveset, newset;
5187 +
5188 + /* XXX: Don't preclude handling different sized sigset_t's. */
5189 + if (sigsetsize != sizeof(sigset_t))
5190 + return -EINVAL;
5191 +
5192 + if (copy_from_user(&newset, unewset, sizeof(newset)))
5193 + return -EFAULT;
5194 + sigdelsetmask(&newset, ~_BLOCKABLE);
5195 +
5196 + spin_lock_irq(&current->sighand->siglock);
5197 + saveset = current->blocked;
5198 + current->blocked = newset;
5199 + recalc_sigpending();
5200 + spin_unlock_irq(&current->sighand->siglock);
5201 +
5202 + regs->d0 = -EINTR;
5203 + while (1) {
5204 + current->state = TASK_INTERRUPTIBLE;
5205 + schedule();
5206 + if (do_signal(&saveset, regs))
5207 + return -EINTR;
5208 + }
5209 +}
5210 +
5211 +asmlinkage int
5212 +sys_sigaction(int sig, const struct old_sigaction __user *act,
5213 + struct old_sigaction __user *oact)
5214 +{
5215 + struct k_sigaction new_ka, old_ka;
5216 + int ret;
5217 +
5218 + if (act) {
5219 + old_sigset_t mask;
5220 + if (!access_ok(VERIFY_READ, act, sizeof(*act)) ||
5221 + __get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
5222 + __get_user(new_ka.sa.sa_restorer, &act->sa_restorer))
5223 + return -EFAULT;
5224 + __get_user(new_ka.sa.sa_flags, &act->sa_flags);
5225 + __get_user(mask, &act->sa_mask);
5226 + siginitset(&new_ka.sa.sa_mask, mask);
5227 + }
5228 +
5229 + ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL);
5230 +
5231 + if (!ret && oact) {
5232 + if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) ||
5233 + __put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
5234 + __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer))
5235 + return -EFAULT;
5236 + __put_user(old_ka.sa.sa_flags, &oact->sa_flags);
5237 + __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask);
5238 + }
5239 +
5240 + return ret;
5241 +}
5242 +
5243 +asmlinkage int
5244 +sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss)
5245 +{
5246 + return do_sigaltstack(uss, uoss, rdusp());
5247 +}
5248 +
5249 +
5250 +/*
5251 + * Do a signal return; undo the signal stack.
5252 + *
5253 + * Keep the return code on the stack quadword aligned!
5254 + * That makes the cache flush below easier.
5255 + */
5256 +
5257 +struct sigframe
5258 +{
5259 + char __user *pretcode;
5260 + int sig;
5261 + int code;
5262 + struct sigcontext __user *psc;
5263 + char retcode[16];
5264 + unsigned long extramask[_NSIG_WORDS-1];
5265 + struct sigcontext sc;
5266 +};
5267 +
5268 +struct rt_sigframe
5269 +{
5270 + char __user *pretcode;
5271 + int sig;
5272 + struct siginfo __user *pinfo;
5273 + void __user *puc;
5274 + char retcode[16];
5275 + struct siginfo info;
5276 + struct ucontext uc;
5277 +};
5278 +
5279 +#define FPCONTEXT_SIZE 216
5280 +#define uc_fpstate uc_filler[0]
5281 +#define uc_formatvec uc_filler[FPCONTEXT_SIZE/4]
5282 +#define uc_extra uc_filler[FPCONTEXT_SIZE/4+1]
5283 +
5284 +#ifdef CONFIG_FPU
5285 +static unsigned char fpu_version; /* version num of fpu, set by setup_frame */
5286 +
5287 +static inline int restore_fpu_state(struct sigcontext *sc)
5288 +{
5289 + int err = 1;
5290 +
5291 + if (FPU_IS_EMU) {
5292 + /* restore registers */
5293 + memcpy(current->thread.fpcntl, sc->sc_fpcntl, 12);
5294 + memcpy(current->thread.fp, sc->sc_fpregs, 24);
5295 + return 0;
5296 + }
5297 +
5298 + if (CPU_IS_060 ? sc->sc_fpstate[2] : sc->sc_fpstate[0]) {
5299 + /* Verify the frame format. */
5300 + if (!CPU_IS_060 && (sc->sc_fpstate[0] != fpu_version))
5301 + goto out;
5302 + if (CPU_IS_020_OR_030) {
5303 + if (m68k_fputype & FPU_68881 &&
5304 + !(sc->sc_fpstate[1] == 0x18 || sc->sc_fpstate[1] == 0xb4))
5305 + goto out;
5306 + if (m68k_fputype & FPU_68882 &&
5307 + !(sc->sc_fpstate[1] == 0x38 || sc->sc_fpstate[1] == 0xd4))
5308 + goto out;
5309 + } else if (CPU_IS_040) {
5310 + if (!(sc->sc_fpstate[1] == 0x00 ||
5311 + sc->sc_fpstate[1] == 0x28 ||
5312 + sc->sc_fpstate[1] == 0x60))
5313 + goto out;
5314 + } else if (CPU_IS_060) {
5315 + if (!(sc->sc_fpstate[3] == 0x00 ||
5316 + sc->sc_fpstate[3] == 0x60 ||
5317 + sc->sc_fpstate[3] == 0xe0))
5318 + goto out;
5319 + } else
5320 + goto out;
5321 +
5322 + }
5323 + err = 0;
5324 +
5325 +out:
5326 + return err;
5327 +}
5328 +
5329 +static inline int rt_restore_fpu_state(struct ucontext __user *uc)
5330 +{
5331 + unsigned char fpstate[FPCONTEXT_SIZE];
5332 + int context_size = CPU_IS_060 ? 8 : 0;
5333 + fpregset_t fpregs;
5334 + int err = 1;
5335 +
5336 + if (FPU_IS_EMU) {
5337 + /* restore fpu control register */
5338 + if (__copy_from_user(current->thread.fpcntl,
5339 + uc->uc_mcontext.fpregs.f_fpcntl, 12))
5340 + goto out;
5341 + /* restore all other fpu register */
5342 + if (__copy_from_user(current->thread.fp,
5343 + uc->uc_mcontext.fpregs.f_fpregs, 96))
5344 + goto out;
5345 + return 0;
5346 + }
5347 +
5348 + if (__get_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate))
5349 + goto out;
5350 + if (CPU_IS_060 ? fpstate[2] : fpstate[0]) {
5351 + if (!CPU_IS_060)
5352 + context_size = fpstate[1];
5353 + /* Verify the frame format. */
5354 + if (!CPU_IS_060 && (fpstate[0] != fpu_version))
5355 + goto out;
5356 + if (CPU_IS_020_OR_030) {
5357 + if (m68k_fputype & FPU_68881 &&
5358 + !(context_size == 0x18 || context_size == 0xb4))
5359 + goto out;
5360 + if (m68k_fputype & FPU_68882 &&
5361 + !(context_size == 0x38 || context_size == 0xd4))
5362 + goto out;
5363 + } else if (CPU_IS_040) {
5364 + if (!(context_size == 0x00 ||
5365 + context_size == 0x28 ||
5366 + context_size == 0x60))
5367 + goto out;
5368 + } else if (CPU_IS_060) {
5369 + if (!(fpstate[3] == 0x00 ||
5370 + fpstate[3] == 0x60 ||
5371 + fpstate[3] == 0xe0))
5372 + goto out;
5373 + } else
5374 + goto out;
5375 + if (__copy_from_user(&fpregs, &uc->uc_mcontext.fpregs,
5376 + sizeof(fpregs)))
5377 + goto out;
5378 + }
5379 + if (context_size &&
5380 + __copy_from_user(fpstate + 4, (long __user *)&uc->uc_fpstate + 1,
5381 + context_size))
5382 + goto out;
5383 + err = 0;
5384 +
5385 +out:
5386 + return err;
5387 +}
5388 +#endif
5389 +
5390 +static inline int
5391 +restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc,
5392 + void __user *fp, int *pd0)
5393 +{
5394 + int fsize, formatvec;
5395 + struct sigcontext context;
5396 + int err = 0;
5397 +
5398 + /* get previous context */
5399 + if (copy_from_user(&context, usc, sizeof(context)))
5400 + goto badframe;
5401 +
5402 + /* restore passed registers */
5403 + regs->d1 = context.sc_d1;
5404 + regs->a0 = context.sc_a0;
5405 + regs->a1 = context.sc_a1;
5406 + regs->sr = (regs->sr & 0xff00) | (context.sc_sr & 0xff);
5407 + regs->pc = context.sc_pc;
5408 + regs->orig_d0 = -1; /* disable syscall checks */
5409 + wrusp(context.sc_usp);
5410 + formatvec = context.sc_formatvec;
5411 + regs->format = formatvec >> 12;
5412 + regs->vector = formatvec & 0xfff;
5413 +
5414 +#ifdef CONFIG_FPU
5415 + err = restore_fpu_state(&context);
5416 +#endif
5417 +
5418 + fsize = frame_extra_sizes[regs->format];
5419 + if (fsize < 0) {
5420 + /*
5421 + * user process trying to return with weird frame format
5422 + */
5423 +#ifdef DEBUG
5424 + printk(KERN_DEBUG "user process returning with weird \
5425 + frame format\n");
5426 +#endif
5427 + goto badframe;
5428 + }
5429 +
5430 + /* OK. Make room on the supervisor stack for the extra junk,
5431 + * if necessary.
5432 + */
5433 +
5434 + {
5435 + struct switch_stack *sw = (struct switch_stack *)regs - 1;
5436 + regs->d0 = context.sc_d0;
5437 +#define frame_offset (sizeof(struct pt_regs)+sizeof(struct switch_stack))
5438 + __asm__ __volatile__
5439 + (" movel %0,%/sp\n\t"
5440 + " bra ret_from_signal\n"
5441 + "4:\n"
5442 + ".section __ex_table,\"a\"\n"
5443 + " .align 4\n"
5444 + " .long 2b,4b\n"
5445 + ".previous"
5446 + : /* no outputs, it doesn't ever return */
5447 + : "a" (sw), "d" (fsize), "d" (frame_offset/4-1),
5448 + "n" (frame_offset), "a" (fp)
5449 + : "a0");
5450 +#undef frame_offset
5451 + /*
5452 + * If we ever get here an exception occurred while
5453 + * building the above stack-frame.
5454 + */
5455 + goto badframe;
5456 + }
5457 +
5458 + *pd0 = context.sc_d0;
5459 + return err;
5460 +
5461 +badframe:
5462 + return 1;
5463 +}
5464 +
5465 +static inline int
5466 +rt_restore_ucontext(struct pt_regs *regs, struct switch_stack *sw,
5467 + struct ucontext __user *uc, int *pd0)
5468 +{
5469 + int fsize, temp;
5470 + greg_t __user *gregs = uc->uc_mcontext.gregs;
5471 + unsigned long usp;
5472 + int err;
5473 +
5474 + err = __get_user(temp, &uc->uc_mcontext.version);
5475 + if (temp != MCONTEXT_VERSION)
5476 + goto badframe;
5477 + /* restore passed registers */
5478 + err |= __get_user(regs->d0, &gregs[0]);
5479 + err |= __get_user(regs->d1, &gregs[1]);
5480 + err |= __get_user(regs->d2, &gregs[2]);
5481 + err |= __get_user(regs->d3, &gregs[3]);
5482 + err |= __get_user(regs->d4, &gregs[4]);
5483 + err |= __get_user(regs->d5, &gregs[5]);
5484 + err |= __get_user(sw->d6, &gregs[6]);
5485 + err |= __get_user(sw->d7, &gregs[7]);
5486 + err |= __get_user(regs->a0, &gregs[8]);
5487 + err |= __get_user(regs->a1, &gregs[9]);
5488 + err |= __get_user(regs->a2, &gregs[10]);
5489 + err |= __get_user(sw->a3, &gregs[11]);
5490 + err |= __get_user(sw->a4, &gregs[12]);
5491 + err |= __get_user(sw->a5, &gregs[13]);
5492 + err |= __get_user(sw->a6, &gregs[14]);
5493 + err |= __get_user(usp, &gregs[15]);
5494 + wrusp(usp);
5495 + err |= __get_user(regs->pc, &gregs[16]);
5496 + err |= __get_user(temp, &gregs[17]);
5497 + regs->sr = (regs->sr & 0xff00) | (temp & 0xff);
5498 + regs->orig_d0 = -1; /* disable syscall checks */
5499 + err |= __get_user(temp, &uc->uc_formatvec);
5500 + regs->format = temp >> 12;
5501 + regs->vector = temp & 0xfff;
5502 +
5503 +#ifdef CONFIG_FPU
5504 + err |= rt_restore_fpu_state(uc);
5505 +#endif
5506 +
5507 + if (do_sigaltstack(&uc->uc_stack, NULL, usp) == -EFAULT)
5508 + goto badframe;
5509 +
5510 + fsize = frame_extra_sizes[regs->format];
5511 + if (fsize < 0) {
5512 + /*
5513 + * user process trying to return with weird frame format
5514 + */
5515 +#ifdef DEBUG
5516 + printk(KERN_DEBUG "user process returning with weird \
5517 + frame format\n");
5518 +#endif
5519 + goto badframe;
5520 + }
5521 +
5522 + /* OK. Make room on the supervisor stack for the extra junk,
5523 + * if necessary.
5524 + */
5525 +
5526 + {
5527 +#define frame_offset (sizeof(struct pt_regs)+sizeof(struct switch_stack))
5528 + __asm__ __volatile__
5529 + (" movel %0,%/sp\n\t"
5530 + " bra ret_from_signal\n"
5531 + "4:\n"
5532 + ".section __ex_table,\"a\"\n"
5533 + " .align 4\n"
5534 + " .long 2b,4b\n"
5535 + ".previous"
5536 + : /* no outputs, it doesn't ever return */
5537 + : "a" (sw), "d" (fsize), "d" (frame_offset/4-1),
5538 + "n" (frame_offset), "a" (&uc->uc_extra)
5539 + : "a0");
5540 +#undef frame_offset
5541 + /*
5542 + * If we ever get here an exception occurred while
5543 + * building the above stack-frame.
5544 + */
5545 + goto badframe;
5546 + }
5547 +
5548 + *pd0 = regs->d0;
5549 + return err;
5550 +
5551 +badframe:
5552 + return 1;
5553 +}
5554 +
5555 +asmlinkage int do_sigreturn(unsigned long __unused)
5556 +{
5557 + struct switch_stack *sw = (struct switch_stack *) &__unused;
5558 + struct pt_regs *regs = (struct pt_regs *) (sw + 1);
5559 + unsigned long usp = rdusp();
5560 + struct sigframe __user *frame = (struct sigframe __user *)(usp - 4);
5561 + sigset_t set;
5562 + int d0;
5563 +
5564 + if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
5565 + goto badframe;
5566 + if (__get_user(set.sig[0], &frame->sc.sc_mask) ||
5567 + (_NSIG_WORDS > 1 &&
5568 + __copy_from_user(&set.sig[1], &frame->extramask,
5569 + sizeof(frame->extramask))))
5570 + goto badframe;
5571 +
5572 + sigdelsetmask(&set, ~_BLOCKABLE);
5573 + spin_lock_irq(&current->sighand->siglock);
5574 + current->blocked = set;
5575 + recalc_sigpending();
5576 + spin_unlock_irq(&current->sighand->siglock);
5577 +
5578 + if (restore_sigcontext(regs, &frame->sc, frame + 1, &d0))
5579 + goto badframe;
5580 + return d0;
5581 +
5582 +badframe:
5583 + force_sig(SIGSEGV, current);
5584 + return 0;
5585 +}
5586 +
5587 +asmlinkage int do_rt_sigreturn(unsigned long __unused)
5588 +{
5589 + struct switch_stack *sw = (struct switch_stack *) &__unused;
5590 + struct pt_regs *regs = (struct pt_regs *) (sw + 1);
5591 + unsigned long usp = rdusp();
5592 + struct rt_sigframe __user *frame =
5593 + (struct rt_sigframe __user *)(usp - 4);
5594 + sigset_t set;
5595 + int d0;
5596 +
5597 + if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
5598 + goto badframe;
5599 + if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
5600 + goto badframe;
5601 +
5602 + sigdelsetmask(&set, ~_BLOCKABLE);
5603 + spin_lock_irq(&current->sighand->siglock);
5604 + current->blocked = set;
5605 + recalc_sigpending();
5606 + spin_unlock_irq(&current->sighand->siglock);
5607 +
5608 + if (rt_restore_ucontext(regs, sw, &frame->uc, &d0))
5609 + goto badframe;
5610 + return d0;
5611 +
5612 +badframe:
5613 + force_sig(SIGSEGV, current);
5614 + return 0;
5615 +}
5616 +
5617 +#ifdef CONFIG_FPU
5618 +/*
5619 + * Set up a signal frame.
5620 + */
5621 +
5622 +static inline void save_fpu_state(struct sigcontext *sc, struct pt_regs *regs)
5623 +{
5624 + if (FPU_IS_EMU) {
5625 + /* save registers */
5626 + memcpy(sc->sc_fpcntl, current->thread.fpcntl, 12);
5627 + memcpy(sc->sc_fpregs, current->thread.fp, 24);
5628 + return;
5629 + }
5630 +}
5631 +
5632 +static inline int rt_save_fpu_state(struct ucontext __user *uc,
5633 + struct pt_regs *regs)
5634 +{
5635 + int err = 0;
5636 +
5637 + if (FPU_IS_EMU) {
5638 + /* save fpu control register */
5639 + err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpcntl,
5640 + current->thread.fpcntl, 12);
5641 + /* save all other fpu register */
5642 + err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpregs,
5643 + current->thread.fp, 96);
5644 + return err;
5645 + }
5646 +
5647 + return err;
5648 +}
5649 +#endif
5650 +
5651 +static void setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs,
5652 + unsigned long mask)
5653 +{
5654 + sc->sc_mask = mask;
5655 + sc->sc_usp = rdusp();
5656 + sc->sc_d0 = regs->d0;
5657 + sc->sc_d1 = regs->d1;
5658 + sc->sc_a0 = regs->a0;
5659 + sc->sc_a1 = regs->a1;
5660 + sc->sc_sr = regs->sr;
5661 + sc->sc_pc = regs->pc;
5662 + sc->sc_formatvec = regs->format << 12 | regs->vector;
5663 +#ifdef CONFIG_FPU
5664 + save_fpu_state(sc, regs);
5665 +#endif
5666 +}
5667 +
5668 +static inline int rt_setup_ucontext(struct ucontext __user *uc,
5669 + struct pt_regs *regs)
5670 +{
5671 + struct switch_stack *sw = (struct switch_stack *)regs - 1;
5672 + greg_t __user *gregs = uc->uc_mcontext.gregs;
5673 + int err = 0;
5674 +
5675 + err |= __put_user(MCONTEXT_VERSION, &uc->uc_mcontext.version);
5676 + err |= __put_user(regs->d0, &gregs[0]);
5677 + err |= __put_user(regs->d1, &gregs[1]);
5678 + err |= __put_user(regs->d2, &gregs[2]);
5679 + err |= __put_user(regs->d3, &gregs[3]);
5680 + err |= __put_user(regs->d4, &gregs[4]);
5681 + err |= __put_user(regs->d5, &gregs[5]);
5682 + err |= __put_user(sw->d6, &gregs[6]);
5683 + err |= __put_user(sw->d7, &gregs[7]);
5684 + err |= __put_user(regs->a0, &gregs[8]);
5685 + err |= __put_user(regs->a1, &gregs[9]);
5686 + err |= __put_user(regs->a2, &gregs[10]);
5687 + err |= __put_user(sw->a3, &gregs[11]);
5688 + err |= __put_user(sw->a4, &gregs[12]);
5689 + err |= __put_user(sw->a5, &gregs[13]);
5690 + err |= __put_user(sw->a6, &gregs[14]);
5691 + err |= __put_user(rdusp(), &gregs[15]);
5692 + err |= __put_user(regs->pc, &gregs[16]);
5693 + err |= __put_user(regs->sr, &gregs[17]);
5694 + err |= __put_user((regs->format << 12) | regs->vector,
5695 + &uc->uc_formatvec);
5696 +#ifdef CONFIG_FPU
5697 + err |= rt_save_fpu_state(uc, regs);
5698 +#endif
5699 + return err;
5700 +}
5701 +
5702 +static inline void push_cache(unsigned long vaddr)
5703 +{
5704 +#if 0
5705 +// JKM -- need to add into the old cpushl cache stuff
5706 + cf_cache_push(__pa(vaddr), 8);
5707 +#endif
5708 +}
5709 +
5710 +static inline void __user *
5711 +get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size)
5712 +{
5713 + unsigned long usp;
5714 +
5715 + /* Default to using normal stack. */
5716 + usp = rdusp();
5717 +
5718 + /* This is the X/Open sanctioned signal stack switching. */
5719 + if (ka->sa.sa_flags & SA_ONSTACK) {
5720 + if (!sas_ss_flags(usp))
5721 + usp = current->sas_ss_sp + current->sas_ss_size;
5722 + }
5723 + return (void __user *)((usp - frame_size) & -8UL);
5724 +}
5725 +
5726 +static void setup_frame(int sig, struct k_sigaction *ka,
5727 + sigset_t *set, struct pt_regs *regs)
5728 +{
5729 + struct sigframe __user *frame;
5730 + int fsize = frame_extra_sizes[regs->format];
5731 + struct sigcontext context;
5732 + int err = 0;
5733 +
5734 + if (fsize < 0) {
5735 +#ifdef DEBUG
5736 + printk(KERN_DEBUG "setup_frame: Unknown frame format %#x\n",
5737 + regs->format);
5738 +#endif
5739 + goto give_sigsegv;
5740 + }
5741 +
5742 + frame = get_sigframe(ka, regs, sizeof(*frame));
5743 +
5744 + err |= __put_user((current_thread_info()->exec_domain
5745 + && current_thread_info()->exec_domain->signal_invmap
5746 + && sig < 32
5747 + ? current_thread_info()->exec_domain->signal_invmap[sig]
5748 + : sig),
5749 + &frame->sig);
5750 +
5751 + err |= __put_user(regs->vector, &frame->code);
5752 + err |= __put_user(&frame->sc, &frame->psc);
5753 +
5754 + if (_NSIG_WORDS > 1)
5755 + err |= copy_to_user(frame->extramask, &set->sig[1],
5756 + sizeof(frame->extramask));
5757 +
5758 + setup_sigcontext(&context, regs, set->sig[0]);
5759 + err |= copy_to_user(&frame->sc, &context, sizeof(context));
5760 +
5761 + /* Set up to return from userspace. */
5762 + err |= __put_user(frame->retcode, &frame->pretcode);
5763 + /* moveq #,d0; trap #0 */
5764 + err |= __put_user(0x70004e40 + (__NR_sigreturn << 16),
5765 + (long __user *)(frame->retcode));
5766 +
5767 + if (err)
5768 + goto give_sigsegv;
5769 +
5770 + push_cache((unsigned long) &frame->retcode);
5771 +
5772 + /* Set up registers for signal handler */
5773 + wrusp((unsigned long) frame);
5774 + regs->pc = (unsigned long) ka->sa.sa_handler;
5775 +
5776 +adjust_stack:
5777 + /* Prepare to skip over the extra stuff in the exception frame. */
5778 + if (regs->stkadj) {
5779 + struct pt_regs *tregs =
5780 + (struct pt_regs *)((ulong)regs + regs->stkadj);
5781 +#ifdef DEBUG
5782 + printk(KERN_DEBUG "Performing stackadjust=%04x\n",
5783 + regs->stkadj);
5784 +#endif
5785 + /* This must be copied with decreasing addresses to
5786 + handle overlaps. */
5787 + tregs->vector = 0;
5788 + tregs->format = 0;
5789 + tregs->pc = regs->pc;
5790 + tregs->sr = regs->sr;
5791 + }
5792 + return;
5793 +
5794 +give_sigsegv:
5795 + force_sigsegv(sig, current);
5796 + goto adjust_stack;
5797 +}
5798 +
5799 +static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
5800 + sigset_t *set, struct pt_regs *regs)
5801 +{
5802 + struct rt_sigframe __user *frame;
5803 + int fsize = frame_extra_sizes[regs->format];
5804 + int err = 0;
5805 +
5806 + if (fsize < 0) {
5807 +#ifdef DEBUG
5808 + printk(KERN_DEBUG "setup_frame: Unknown frame format %#x\n",
5809 + regs->format);
5810 +#endif
5811 + goto give_sigsegv;
5812 + }
5813 +
5814 + frame = get_sigframe(ka, regs, sizeof(*frame));
5815 +
5816 + if (fsize) {
5817 + err |= copy_to_user(&frame->uc.uc_extra, regs + 1, fsize);
5818 + regs->stkadj = fsize;
5819 + }
5820 +
5821 + err |= __put_user((current_thread_info()->exec_domain
5822 + && current_thread_info()->exec_domain->signal_invmap
5823 + && sig < 32
5824 + ? current_thread_info()->exec_domain->signal_invmap[sig]
5825 + : sig),
5826 + &frame->sig);
5827 + err |= __put_user(&frame->info, &frame->pinfo);
5828 + err |= __put_user(&frame->uc, &frame->puc);
5829 + err |= copy_siginfo_to_user(&frame->info, info);
5830 +
5831 + /* Create the ucontext. */
5832 + err |= __put_user(0, &frame->uc.uc_flags);
5833 + err |= __put_user(NULL, &frame->uc.uc_link);
5834 + err |= __put_user((void __user *)current->sas_ss_sp,
5835 + &frame->uc.uc_stack.ss_sp);
5836 + err |= __put_user(sas_ss_flags(rdusp()),
5837 + &frame->uc.uc_stack.ss_flags);
5838 + err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size);
5839 + err |= rt_setup_ucontext(&frame->uc, regs);
5840 + err |= copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set));
5841 +
5842 + /* Set up to return from userspace. */
5843 + err |= __put_user(frame->retcode, &frame->pretcode);
5844 +
5845 + /* moveq #,d0; andi.l #,D0; trap #0 */
5846 + err |= __put_user(0x70AD0280, (long *)(frame->retcode + 0));
5847 + err |= __put_user(0x000000ff, (long *)(frame->retcode + 4));
5848 + err |= __put_user(0x4e400000, (long *)(frame->retcode + 8));
5849 +
5850 + if (err)
5851 + goto give_sigsegv;
5852 +
5853 + push_cache((unsigned long) &frame->retcode);
5854 +
5855 + /* Set up registers for signal handler */
5856 + wrusp((unsigned long) frame);
5857 + regs->pc = (unsigned long) ka->sa.sa_handler;
5858 +
5859 +adjust_stack:
5860 + /* Prepare to skip over the extra stuff in the exception frame. */
5861 + if (regs->stkadj) {
5862 + struct pt_regs *tregs =
5863 + (struct pt_regs *)((ulong)regs + regs->stkadj);
5864 +#ifdef DEBUG
5865 + printk(KERN_DEBUG "Performing stackadjust=%04x\n",
5866 + regs->stkadj);
5867 +#endif
5868 + /* This must be copied with decreasing addresses to
5869 + handle overlaps. */
5870 + tregs->vector = 0;
5871 + tregs->format = 0;
5872 + tregs->pc = regs->pc;
5873 + tregs->sr = regs->sr;
5874 + }
5875 + return;
5876 +
5877 +give_sigsegv:
5878 + force_sigsegv(sig, current);
5879 + goto adjust_stack;
5880 +}
5881 +
5882 +static inline void
5883 +handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler)
5884 +{
5885 + switch (regs->d0) {
5886 + case -ERESTARTNOHAND:
5887 + if (!has_handler)
5888 + goto do_restart;
5889 + regs->d0 = -EINTR;
5890 + break;
5891 +
5892 + case -ERESTARTSYS:
5893 + if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) {
5894 + regs->d0 = -EINTR;
5895 + break;
5896 + }
5897 + /* fallthrough */
5898 + case -ERESTARTNOINTR:
5899 +do_restart:
5900 + regs->d0 = regs->orig_d0;
5901 + regs->pc -= 2;
5902 + break;
5903 + }
5904 +}
5905 +
5906 +/*
5907 + * OK, we're invoking a handler
5908 + */
5909 +static void
5910 +handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info,
5911 + sigset_t *oldset, struct pt_regs *regs)
5912 +{
5913 + /* are we from a system call? */
5914 + if (regs->orig_d0 >= 0)
5915 + /* If so, check system call restarting.. */
5916 + handle_restart(regs, ka, 1);
5917 +
5918 + /* set up the stack frame */
5919 + if (ka->sa.sa_flags & SA_SIGINFO)
5920 + setup_rt_frame(sig, ka, info, oldset, regs);
5921 + else
5922 + setup_frame(sig, ka, oldset, regs);
5923 +
5924 + if (ka->sa.sa_flags & SA_ONESHOT)
5925 + ka->sa.sa_handler = SIG_DFL;
5926 +
5927 + spin_lock_irq(&current->sighand->siglock);
5928 + sigorsets(&current->blocked, &current->blocked, &ka->sa.sa_mask);
5929 + if (!(ka->sa.sa_flags & SA_NODEFER))
5930 + sigaddset(&current->blocked, sig);
5931 + recalc_sigpending();
5932 + spin_unlock_irq(&current->sighand->siglock);
5933 +}
5934 +
5935 +/*
5936 + * Note that 'init' is a special process: it doesn't get signals it doesn't
5937 + * want to handle. Thus you cannot kill init even with a SIGKILL even by
5938 + * mistake.
5939 + */
5940 +asmlinkage int do_signal(sigset_t *oldset, struct pt_regs *regs)
5941 +{
5942 + siginfo_t info;
5943 + struct k_sigaction ka;
5944 + int signr;
5945 +
5946 + current->thread.esp0 = (unsigned long) regs;
5947 +
5948 + if (!oldset)
5949 + oldset = &current->blocked;
5950 +
5951 + signr = get_signal_to_deliver(&info, &ka, regs, NULL);
5952 + if (signr > 0) {
5953 + /* Whee! Actually deliver the signal. */
5954 + handle_signal(signr, &ka, &info, oldset, regs);
5955 + return 1;
5956 + }
5957 +
5958 + /* Did we come from a system call? */
5959 + if (regs->orig_d0 >= 0)
5960 + /* Restart the system call - no handlers present */
5961 + handle_restart(regs, NULL, 0);
5962 +
5963 + return 0;
5964 +}
5965 --- /dev/null
5966 +++ b/arch/m68k/coldfire/traps.c
5967 @@ -0,0 +1,455 @@
5968 +/*
5969 + * linux/arch/m68knommu/kernel/traps.c
5970 + *
5971 + * Copyright (C) 1993, 1994 by Hamish Macdonald
5972 + *
5973 + * 68040 fixes by Michael Rausch
5974 + * 68040 fixes by Martin Apel
5975 + * 68060 fixes by Roman Hodek
5976 + * 68060 fixes by Jesper Skov
5977 + * Coldfire fixes by Kurt Mahan
5978 + *
5979 + * This file is subject to the terms and conditions of the GNU General Public
5980 + * License. See the file COPYING in the main directory of this archive
5981 + * for more details.
5982 + */
5983 +
5984 +/*
5985 + * Sets up all exception vectors
5986 + */
5987 +#include <linux/sched.h>
5988 +#include <linux/signal.h>
5989 +#include <linux/kernel.h>
5990 +#include <linux/mm.h>
5991 +#include <linux/module.h>
5992 +#include <linux/types.h>
5993 +#include <linux/a.out.h>
5994 +#include <linux/user.h>
5995 +#include <linux/string.h>
5996 +#include <linux/linkage.h>
5997 +#include <linux/init.h>
5998 +#include <linux/ptrace.h>
5999 +#include <linux/kallsyms.h>
6000 +
6001 +#include <asm/setup.h>
6002 +#include <asm/fpu.h>
6003 +#include <asm/system.h>
6004 +#include <asm/uaccess.h>
6005 +#include <asm/traps.h>
6006 +#include <asm/pgtable.h>
6007 +#include <asm/machdep.h>
6008 +#include <asm/siginfo.h>
6009 +
6010 +static char const * const vec_names[] = {
6011 + "RESET SP", "RESET PC", "BUS ERROR", "ADDRESS ERROR",
6012 + "ILLEGAL INSTRUCTION", "ZERO DIVIDE", "CHK", "TRAPcc",
6013 + "PRIVILEGE VIOLATION", "TRACE", "LINE 1010", "LINE 1111",
6014 + "UNASSIGNED RESERVED 12", "COPROCESSOR PROTOCOL VIOLATION",
6015 + "FORMAT ERROR", "UNINITIALIZED INTERRUPT",
6016 + "UNASSIGNED RESERVED 16", "UNASSIGNED RESERVED 17",
6017 + "UNASSIGNED RESERVED 18", "UNASSIGNED RESERVED 19",
6018 + "UNASSIGNED RESERVED 20", "UNASSIGNED RESERVED 21",
6019 + "UNASSIGNED RESERVED 22", "UNASSIGNED RESERVED 23",
6020 + "SPURIOUS INTERRUPT", "LEVEL 1 INT", "LEVEL 2 INT", "LEVEL 3 INT",
6021 + "LEVEL 4 INT", "LEVEL 5 INT", "LEVEL 6 INT", "LEVEL 7 INT",
6022 + "SYSCALL", "TRAP #1", "TRAP #2", "TRAP #3",
6023 + "TRAP #4", "TRAP #5", "TRAP #6", "TRAP #7",
6024 + "TRAP #8", "TRAP #9", "TRAP #10", "TRAP #11",
6025 + "TRAP #12", "TRAP #13", "TRAP #14", "TRAP #15",
6026 + "FPCP BSUN", "FPCP INEXACT", "FPCP DIV BY 0", "FPCP UNDERFLOW",
6027 + "FPCP OPERAND ERROR", "FPCP OVERFLOW", "FPCP SNAN",
6028 + "FPCP UNSUPPORTED OPERATION",
6029 + "MMU CONFIGURATION ERROR"
6030 +};
6031 +
6032 +asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address,
6033 + unsigned long error_code);
6034 +asmlinkage void trap_c(struct frame *fp);
6035 +extern void __init coldfire_trap_init(void);
6036 +
6037 +void __init trap_init(void)
6038 +{
6039 + coldfire_trap_init();
6040 +}
6041 +
6042 +/* The following table converts the FS encoding of a ColdFire
6043 + exception stack frame into the error_code value needed by
6044 + do_fault. */
6045 +
6046 +static const unsigned char fs_err_code[] = {
6047 + 0, /* 0000 */
6048 + 0, /* 0001 */
6049 + 0, /* 0010 */
6050 + 0, /* 0011 */
6051 + 1, /* 0100 */
6052 + 0, /* 0101 */
6053 + 0, /* 0110 */
6054 + 0, /* 0111 */
6055 + 2, /* 1000 */
6056 + 3, /* 1001 */
6057 + 2, /* 1010 */
6058 + 0, /* 1011 */
6059 + 1, /* 1100 */
6060 + 1, /* 1101 */
6061 + 0, /* 1110 */
6062 + 0 /* 1111 */
6063 +};
6064 +
6065 +#ifdef DEBUG
6066 +static const char *fs_err_msg[16] = {
6067 + "Normal",
6068 + "Reserved",
6069 + "Interrupt during debug service routine",
6070 + "Reserved",
6071 + "X Protection",
6072 + "TLB X miss (opword)",
6073 + "TLB X miss (ext. word)",
6074 + "IFP in emulator mode",
6075 + "W Protection",
6076 + "Write error",
6077 + "TLB W miss",
6078 + "Reserved",
6079 + "R Protection",
6080 + "R/RMW Protection",
6081 + "TLB R miss",
6082 + "OEP in emulator mode",
6083 +};
6084 +#endif
6085 +
6086 +static inline void access_errorCF(struct frame *fp)
6087 +{
6088 + unsigned long int mmusr, complainingAddress;
6089 + unsigned int err_code, fs;
6090 + int need_page_fault;
6091 +
6092 + mmusr = fp->ptregs.mmusr;
6093 + complainingAddress = fp->ptregs.mmuar;
6094 +#ifdef DEBUG
6095 + printk(KERN_DEBUG "pc %#lx, mmusr %#lx, complainingAddress %#lx\n", \
6096 + fp->ptregs.pc, mmusr, complainingAddress);
6097 +#endif
6098 +
6099 + /*
6100 + * error_code:
6101 + * bit 0 == 0 means no page found, 1 means protection fault
6102 + * bit 1 == 0 means read, 1 means write
6103 + */
6104 +
6105 + fs = (fp->ptregs.fs2 << 2) | fp->ptregs.fs1;
6106 + switch (fs) {
6107 + case 5: /* 0101 TLB opword X miss */
6108 + need_page_fault = cf_tlb_miss(&fp->ptregs, 0, 0, 0);
6109 + complainingAddress = fp->ptregs.pc;
6110 + break;
6111 + case 6: /* 0110 TLB extension word X miss */
6112 + need_page_fault = cf_tlb_miss(&fp->ptregs, 0, 0, 1);
6113 + complainingAddress = fp->ptregs.pc + sizeof(long);
6114 + break;
6115 + case 10: /* 1010 TLB W miss */
6116 + need_page_fault = cf_tlb_miss(&fp->ptregs, 1, 1, 0);
6117 + break;
6118 + case 14: /* 1110 TLB R miss */
6119 + need_page_fault = cf_tlb_miss(&fp->ptregs, 0, 1, 0);
6120 + break;
6121 + default:
6122 + /* 0000 Normal */
6123 + /* 0001 Reserved */
6124 + /* 0010 Interrupt during debug service routine */
6125 + /* 0011 Reserved */
6126 + /* 0100 X Protection */
6127 + /* 0111 IFP in emulator mode */
6128 + /* 1000 W Protection*/
6129 + /* 1001 Write error*/
6130 + /* 1011 Reserved*/
6131 + /* 1100 R Protection*/
6132 + /* 1101 R Protection*/
6133 + /* 1111 OEP in emulator mode*/
6134 + need_page_fault = 1;
6135 + break;
6136 + }
6137 +
6138 + if (need_page_fault) {
6139 + err_code = fs_err_code[fs];
6140 + if ((fs == 13) && (mmusr & MMUSR_WF)) /* rd-mod-wr access */
6141 + err_code |= 2; /* bit1 - write, bit0 - protection */
6142 + do_page_fault(&fp->ptregs, complainingAddress, err_code);
6143 + }
6144 +}
6145 +
6146 +void die_if_kernel(char *str, struct pt_regs *fp, int nr)
6147 +{
6148 + if (!(fp->sr & PS_S))
6149 + return;
6150 +
6151 + console_verbose();
6152 + printk(KERN_EMERG "%s: %08x\n", str, nr);
6153 + printk(KERN_EMERG "PC: [<%08lx>]", fp->pc);
6154 + print_symbol(" %s", fp->pc);
6155 + printk(KERN_EMERG "\nSR: %04x SP: %p a2: %08lx\n",
6156 + fp->sr, fp, fp->a2);
6157 + printk(KERN_EMERG "d0: %08lx d1: %08lx d2: %08lx d3: %08lx\n",
6158 + fp->d0, fp->d1, fp->d2, fp->d3);
6159 + printk(KERN_EMERG "d4: %08lx d5: %08lx a0: %08lx a1: %08lx\n",
6160 + fp->d4, fp->d5, fp->a0, fp->a1);
6161 +
6162 + printk(KERN_EMERG "Process %s (pid: %d, stackpage=%08lx)\n",
6163 + current->comm, current->pid, PAGE_SIZE+(unsigned long)current);
6164 + show_stack(NULL, (unsigned long *)fp);
6165 + do_exit(SIGSEGV);
6166 +}
6167 +
6168 +asmlinkage void buserr_c(struct frame *fp)
6169 +{
6170 + unsigned int fs;
6171 +
6172 + /* Only set esp0 if coming from user mode */
6173 + if (user_mode(&fp->ptregs))
6174 + current->thread.esp0 = (unsigned long) fp;
6175 +
6176 + fs = (fp->ptregs.fs2 << 2) | fp->ptregs.fs1;
6177 +#if defined(DEBUG)
6178 + printk(KERN_DEBUG "*** Bus Error *** (%x)%s\n", fs,
6179 + fs_err_msg[fs & 0xf]);
6180 +#endif
6181 + switch (fs) {
6182 + case 0x5:
6183 + case 0x6:
6184 + case 0x7:
6185 + case 0x9:
6186 + case 0xa:
6187 + case 0xd:
6188 + case 0xe:
6189 + case 0xf:
6190 + access_errorCF(fp);
6191 + break;
6192 + default:
6193 + die_if_kernel("bad frame format", &fp->ptregs, 0);
6194 +#if defined(DEBUG)
6195 + printk(KERN_DEBUG "Unknown SIGSEGV - 4\n");
6196 +#endif
6197 + force_sig(SIGSEGV, current);
6198 + }
6199 +}
6200 +
6201 +
6202 +int kstack_depth_to_print = 48;
6203 +
6204 +void show_stack(struct task_struct *task, unsigned long *stack)
6205 +{
6206 + unsigned long *endstack, addr, symaddr;
6207 + extern char _start, _etext;
6208 + int i;
6209 +
6210 + if (!stack) {
6211 + if (task)
6212 + stack = (unsigned long *)task->thread.ksp;
6213 + else
6214 + stack = (unsigned long *)&stack;
6215 + }
6216 +
6217 + addr = (unsigned long) stack;
6218 + endstack = (unsigned long *) PAGE_ALIGN(addr);
6219 +
6220 + printk(KERN_EMERG "Stack from %08lx:", (unsigned long)stack);
6221 + for (i = 0; i < kstack_depth_to_print; i++) {
6222 + if (stack + 1 > endstack)
6223 + break;
6224 + if (i % 8 == 0)
6225 + printk("\n" KERN_EMERG " ");
6226 + symaddr = *stack;
6227 + printk(KERN_EMERG " %08lx", *stack++);
6228 + if ((symaddr >= 0xc0000000) && (symaddr < 0xc1000000))
6229 + print_symbol("(%s)", symaddr);
6230 + }
6231 + printk("\n");
6232 +
6233 + printk(KERN_EMERG "Call Trace:");
6234 + i = 0;
6235 + while (stack + 1 <= endstack) {
6236 + addr = *stack++;
6237 + /*
6238 + * If the address is either in the text segment of the
6239 + * kernel, or in the region which contains vmalloc'ed
6240 + * memory, it *may* be the address of a calling
6241 + * routine; if so, print it so that someone tracing
6242 + * down the cause of the crash will be able to figure
6243 + * out the call path that was taken.
6244 + */
6245 + if (((addr >= (unsigned long) &_start) &&
6246 + (addr <= (unsigned long) &_etext))) {
6247 + if (i % 4 == 0)
6248 + printk("\n" KERN_EMERG " ");
6249 + printk(KERN_EMERG " [<%08lx>]", addr);
6250 + i++;
6251 + }
6252 + }
6253 + printk("\n");
6254 +}
6255 +
6256 +void bad_super_trap(struct frame *fp)
6257 +{
6258 + console_verbose();
6259 + if (fp->ptregs.vector < sizeof(vec_names)/sizeof(vec_names[0]))
6260 + printk(KERN_WARNING "*** %s *** FORMAT=%X\n",
6261 + vec_names[fp->ptregs.vector],
6262 + fp->ptregs.format);
6263 + else
6264 + printk(KERN_WARNING "*** Exception %d *** FORMAT=%X\n",
6265 + fp->ptregs.vector,
6266 + fp->ptregs.format);
6267 + printk(KERN_WARNING "Current process id is %d\n", current->pid);
6268 + die_if_kernel("BAD KERNEL TRAP", &fp->ptregs, 0);
6269 +}
6270 +
6271 +asmlinkage void trap_c(struct frame *fp)
6272 +{
6273 + int sig;
6274 + siginfo_t info;
6275 +
6276 + if (fp->ptregs.sr & PS_S) {
6277 + if (fp->ptregs.vector == VEC_TRACE) {
6278 + /* traced a trapping instruction */
6279 + current->ptrace |= PT_DTRACE;
6280 + } else
6281 + bad_super_trap(fp);
6282 + return;
6283 + }
6284 +
6285 + /* send the appropriate signal to the user program */
6286 + switch (fp->ptregs.vector) {
6287 + case VEC_ADDRERR:
6288 + info.si_code = BUS_ADRALN;
6289 + sig = SIGBUS;
6290 + break;
6291 + case VEC_ILLEGAL:
6292 + case VEC_LINE10:
6293 + case VEC_LINE11:
6294 + info.si_code = ILL_ILLOPC;
6295 + sig = SIGILL;
6296 + break;
6297 + case VEC_PRIV:
6298 + info.si_code = ILL_PRVOPC;
6299 + sig = SIGILL;
6300 + break;
6301 + case VEC_COPROC:
6302 + info.si_code = ILL_COPROC;
6303 + sig = SIGILL;
6304 + break;
6305 + case VEC_TRAP1: /* gdbserver breakpoint */
6306 + fp->ptregs.pc -= 2;
6307 + info.si_code = TRAP_TRACE;
6308 + sig = SIGTRAP;
6309 + break;
6310 + case VEC_TRAP2:
6311 + case VEC_TRAP3:
6312 + case VEC_TRAP4:
6313 + case VEC_TRAP5:
6314 + case VEC_TRAP6:
6315 + case VEC_TRAP7:
6316 + case VEC_TRAP8:
6317 + case VEC_TRAP9:
6318 + case VEC_TRAP10:
6319 + case VEC_TRAP11:
6320 + case VEC_TRAP12:
6321 + case VEC_TRAP13:
6322 + case VEC_TRAP14:
6323 + info.si_code = ILL_ILLTRP;
6324 + sig = SIGILL;
6325 + break;
6326 + case VEC_FPBRUC:
6327 + case VEC_FPOE:
6328 + case VEC_FPNAN:
6329 + info.si_code = FPE_FLTINV;
6330 + sig = SIGFPE;
6331 + break;
6332 + case VEC_FPIR:
6333 + info.si_code = FPE_FLTRES;
6334 + sig = SIGFPE;
6335 + break;
6336 + case VEC_FPDIVZ:
6337 + info.si_code = FPE_FLTDIV;
6338 + sig = SIGFPE;
6339 + break;
6340 + case VEC_FPUNDER:
6341 + info.si_code = FPE_FLTUND;
6342 + sig = SIGFPE;
6343 + break;
6344 + case VEC_FPOVER:
6345 + info.si_code = FPE_FLTOVF;
6346 + sig = SIGFPE;
6347 + break;
6348 + case VEC_ZERODIV:
6349 + info.si_code = FPE_INTDIV;
6350 + sig = SIGFPE;
6351 + break;
6352 + case VEC_CHK:
6353 + case VEC_TRAP:
6354 + info.si_code = FPE_INTOVF;
6355 + sig = SIGFPE;
6356 + break;
6357 + case VEC_TRACE: /* ptrace single step */
6358 + info.si_code = TRAP_TRACE;
6359 + sig = SIGTRAP;
6360 + break;
6361 + case VEC_TRAP15: /* breakpoint */
6362 + info.si_code = TRAP_BRKPT;
6363 + sig = SIGTRAP;
6364 + break;
6365 + default:
6366 + info.si_code = ILL_ILLOPC;
6367 + sig = SIGILL;
6368 + break;
6369 + }
6370 + info.si_signo = sig;
6371 + info.si_errno = 0;
6372 + switch (fp->ptregs.format) {
6373 + default:
6374 + info.si_addr = (void *) fp->ptregs.pc;
6375 + break;
6376 + case 2:
6377 + info.si_addr = (void *) fp->un.fmt2.iaddr;
6378 + break;
6379 + case 7:
6380 + info.si_addr = (void *) fp->un.fmt7.effaddr;
6381 + break;
6382 + case 9:
6383 + info.si_addr = (void *) fp->un.fmt9.iaddr;
6384 + break;
6385 + case 10:
6386 + info.si_addr = (void *) fp->un.fmta.daddr;
6387 + break;
6388 + case 11:
6389 + info.si_addr = (void *) fp->un.fmtb.daddr;
6390 + break;
6391 + }
6392 + force_sig_info(sig, &info, current);
6393 +}
6394 +
6395 +asmlinkage void set_esp0(unsigned long ssp)
6396 +{
6397 + current->thread.esp0 = ssp;
6398 +}
6399 +
6400 +/*
6401 + * The architecture-independent backtrace generator
6402 + */
6403 +void dump_stack(void)
6404 +{
6405 + unsigned long stack;
6406 +
6407 + show_stack(current, &stack);
6408 +}
6409 +EXPORT_SYMBOL(dump_stack);
6410 +
6411 +#ifdef CONFIG_M68KFPU_EMU
6412 +asmlinkage void fpemu_signal(int signal, int code, void *addr)
6413 +{
6414 + siginfo_t info;
6415 +
6416 + info.si_signo = signal;
6417 + info.si_errno = 0;
6418 + info.si_code = code;
6419 + info.si_addr = addr;
6420 + force_sig_info(signal, &info, current);
6421 +}
6422 +#endif
6423 --- /dev/null
6424 +++ b/arch/m68k/coldfire/usb/Makefile
6425 @@ -0,0 +1,28 @@
6426 +#
6427 +# Makefile for the linux kernel.
6428 +#
6429 +
6430 +# Object file lists.
6431 +
6432 +ifneq ($(CONFIG_USB_EHCI_HCD),)
6433 + obj-y += otg_host.o
6434 +endif
6435 +
6436 +ifneq ($(CONFIG_USB_GADGET_MCF5445X),)
6437 + obj-y += otg_device.o
6438 +endif
6439 +
6440 +ifneq ($(strip $(CONFIG_USB_GADGET_MCF5445X) $(CONFIG_USB_EHCI_HCD)),)
6441 + obj-y += otg_cmn.o
6442 +endif
6443 +
6444 +ifneq ($(CONFIG_USB_OTG),)
6445 + obj-y += otg_otg.o
6446 +endif
6447 +
6448 +
6449 +# USB Transceiver driver:
6450 +ifneq ($(strip $(CONFIG_USB) $(CONFIG_USB_GADGET_MCF5445X)),)
6451 + obj-y += xcvr.o
6452 +endif
6453 +
6454 --- /dev/null
6455 +++ b/arch/m68k/coldfire/usb/otg_cmn.c
6456 @@ -0,0 +1,106 @@
6457 +/*
6458 + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6459 + */
6460 +
6461 +/*
6462 + * The code contained herein is licensed under the GNU General Public
6463 + * License. You may obtain a copy of the GNU General Public License
6464 + * Version 2 or later at the following locations:
6465 + *
6466 + * http://www.opensource.org/licenses/gpl-license.html
6467 + * http://www.gnu.org/copyleft/gpl.html
6468 + */
6469 +
6470 +#include <linux/module.h>
6471 +#include <linux/kernel.h>
6472 +#include <linux/types.h>
6473 +#include <linux/err.h>
6474 +#include <linux/errno.h>
6475 +#include <linux/init.h>
6476 +#include <linux/io.h>
6477 +#include <linux/irq.h>
6478 +#include <linux/platform_device.h>
6479 +#include <linux/delay.h>
6480 +#include <linux/fsl_devices.h>
6481 +#include <linux/usb/fsl_xcvr.h>
6482 +
6483 +#include <asm/system.h>
6484 +#include <asm/coldfire.h>
6485 +
6486 +extern void fsl_usb_enable_clk(void);
6487 +extern void fsl_usb_disable_clk(void);
6488 +extern int fsl_usb_mem_init(struct platform_device *pdev);
6489 +
6490 +extern struct fsl_xcvr_ops *xc_ops[];
6491 +
6492 +static int otg_used;
6493 +
6494 +int usbotg_init(struct platform_device *pdev)
6495 +{
6496 + struct fsl_usb2_platform_data *pdata;
6497 + struct fsl_xcvr_ops *xops = xc_ops[USB_CTRLR_OTG];
6498 + int rc;
6499 +
6500 + pdata = (struct fsl_usb2_platform_data *)pdev->dev.platform_data;
6501 +
6502 + pr_debug("%s: pdev=0x%p pdata=0x%p\n", __FUNCTION__, pdev, pdata);
6503 +
6504 + if (!xops) {
6505 + printk(KERN_ERR "OTG transceiver ops missing\n");
6506 + return -EINVAL;
6507 + }
6508 + pdata->xcvr_ops = xops;
6509 + pdata->xcvr_type = xops->xcvr_type;
6510 +
6511 + if (!otg_used) {
6512 + /* request_mem_region and ioremap registers */
6513 + rc = fsl_usb_mem_init(pdev);
6514 + if (rc)
6515 + return rc;
6516 +
6517 + fsl_usb_enable_clk();
6518 +
6519 + if (xops->init)
6520 + xops->init(pdev);
6521 + }
6522 +
6523 + otg_used++;
6524 + pr_debug("%s: success\n", __FUNCTION__);
6525 + return 0;
6526 +}
6527 +
6528 +void usbotg_uninit(struct platform_device *pdev)
6529 +{
6530 + struct fsl_usb2_platform_data *pdata;
6531 + pdata = (struct fsl_usb2_platform_data *)pdev->dev.platform_data;
6532 +
6533 + pr_debug("%s\n", __FUNCTION__);
6534 +
6535 + otg_used--;
6536 + if (!otg_used) {
6537 + if (pdata->xcvr_ops && pdata->xcvr_ops->uninit)
6538 + pdata->xcvr_ops->uninit(pdev);
6539 +
6540 + iounmap(pdata->regs);
6541 + release_mem_region(pdata->r_start, pdata->r_len);
6542 +
6543 + pdata->regs = NULL;
6544 + pdata->r_start = pdata->r_len = 0;
6545 +
6546 + fsl_usb_disable_clk();
6547 + }
6548 +}
6549 +
6550 +struct fsl_usb2_platform_data mxc_otg_config = {
6551 + .name = "OTG",
6552 + .platform_init = usbotg_init,
6553 + .platform_uninit = usbotg_uninit,
6554 + .es = 1,
6555 + .big_endian_mmio = 1,
6556 + .big_endian_desc = 1,
6557 + .le_setup_buf = 1,
6558 + .does_otg = 1,
6559 + .power_budget = 500, /* 500 mA max power */
6560 + .max_ep_nr = 4, /* DDD read from a register ? */
6561 + .phy_mode = FSL_USB2_PHY_ULPI, /* DDD redundant with xcvr_type */
6562 +};
6563 --- /dev/null
6564 +++ b/arch/m68k/coldfire/usb/otg_device.c
6565 @@ -0,0 +1,89 @@
6566 +/*
6567 + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6568 + */
6569 +
6570 +/*
6571 + * The code contained herein is licensed under the GNU General Public
6572 + * License. You may obtain a copy of the GNU General Public License
6573 + * Version 2 or later at the following locations:
6574 + *
6575 + * http://www.opensource.org/licenses/gpl-license.html
6576 + * http://www.gnu.org/copyleft/gpl.html
6577 + */
6578 +
6579 +#include <linux/module.h>
6580 +#include <linux/kernel.h>
6581 +#include <linux/types.h>
6582 +#include <linux/errno.h>
6583 +#include <linux/init.h>
6584 +#include <linux/io.h>
6585 +#include <linux/irq.h>
6586 +#include <linux/err.h>
6587 +#include <linux/platform_device.h>
6588 +#include <linux/usb/otg.h>
6589 +#include <linux/delay.h>
6590 +#include <linux/fsl_devices.h>
6591 +#include <linux/usb/fsl_xcvr.h>
6592 +
6593 +#include <asm/system.h>
6594 +#include <asm/coldfire.h>
6595 +
6596 +#define USB_OTGREGS_BASE MCF_REG32(0xFC0B0000)
6597 +#define INT_USB (64 + 64 + 47) /* INTC1:47 16.2.9.1 */
6598 +#define INT_UOCSR (64 + 64 + 53) /* INTC1:53 16.2.9.1 */
6599 +
6600 +extern int usbotg_init(struct platform_device *pdev);
6601 +extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata);
6602 +extern struct fsl_usb2_platform_data mxc_otg_config;
6603 +
6604 +struct platform_device otg_udc_device;
6605 +
6606 +/*!
6607 + * OTG Gadget device
6608 + */
6609 +
6610 +static void usb_release(struct device *dev)
6611 +{
6612 + /* normally not freed */
6613 +}
6614 +
6615 +static u64 udc_dmamask = ~(u32) 0;
6616 +static struct resource otg_udc_resources[] = {
6617 + [0] = {
6618 + .start = (u32) (&USB_OTGREGS_BASE),
6619 + .end = (u32) (&USB_OTGREGS_BASE + 0x1ff),
6620 + .flags = IORESOURCE_MEM,
6621 + },
6622 + [1] = {
6623 + .start = INT_USB,
6624 + .flags = IORESOURCE_IRQ,
6625 + },
6626 +};
6627 +
6628 +
6629 +struct platform_device otg_udc_device = {
6630 + .name = "fsl-usb2-udc",
6631 + .id = -1,
6632 + .dev = {
6633 + .release = usb_release,
6634 + .dma_mask = &udc_dmamask,
6635 + .coherent_dma_mask = 0xffffffff,
6636 + .platform_data = &mxc_otg_config,
6637 + },
6638 + .resource = otg_udc_resources,
6639 + .num_resources = ARRAY_SIZE(otg_udc_resources),
6640 +};
6641 +
6642 +static int __init udc_init(void)
6643 +{
6644 + int rc __attribute((unused));
6645 +
6646 + rc = platform_device_register(&otg_udc_device);
6647 + if (rc)
6648 + printk(KERN_ERR "usb: can't register OTG Gadget, rc=%d\n", rc);
6649 + else
6650 + printk(KERN_INFO "usb: OTG Gadget registered\n");
6651 + return rc;
6652 +}
6653 +
6654 +subsys_initcall(udc_init);
6655 --- /dev/null
6656 +++ b/arch/m68k/coldfire/usb/otg_host.c
6657 @@ -0,0 +1,68 @@
6658 +/*
6659 + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6660 + */
6661 +
6662 +/*
6663 + * The code contained herein is licensed under the GNU General Public
6664 + * License. You may obtain a copy of the GNU General Public License
6665 + * Version 2 or later at the following locations:
6666 + *
6667 + * http://www.opensource.org/licenses/gpl-license.html
6668 + * http://www.gnu.org/copyleft/gpl.html
6669 + */
6670 +
6671 +#include <linux/module.h>
6672 +#include <linux/kernel.h>
6673 +#include <linux/types.h>
6674 +#include <linux/errno.h>
6675 +#include <linux/init.h>
6676 +#include <linux/io.h>
6677 +#include <linux/irq.h>
6678 +#include <linux/err.h>
6679 +#include <linux/platform_device.h>
6680 +#include <linux/delay.h>
6681 +#include <linux/fsl_devices.h>
6682 +#include <linux/usb/fsl_xcvr.h>
6683 +
6684 +#include <asm/system.h>
6685 +#include <asm/mcfsim.h>
6686 +
6687 +#define USB_OTGREGS_BASE MCF_REG32(0xFC0B0000)
6688 +#define INT_USB (64 + 64 + 47) /* INTC1:47 16.2.9.1 */
6689 +#define INT_UOCSR (64 + 64 + 53) /* INTC1:53 16.2.9.1 */
6690 +
6691 +struct platform_device *otg_host_device;
6692 +
6693 +extern struct platform_device *host_pdev_register(struct resource *res,
6694 + int n_res,
6695 + struct fsl_usb2_platform_data
6696 + *config);
6697 +
6698 +extern int usbotg_init(struct platform_device *pdev);
6699 +extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata);
6700 +extern struct fsl_usb2_platform_data mxc_otg_config;
6701 +
6702 +/*!
6703 + * OTG host config
6704 + */
6705 +static struct resource otg_host_resources[] = {
6706 + [0] = {
6707 + .start = (u32) (&USB_OTGREGS_BASE),
6708 + .end = (u32) (&USB_OTGREGS_BASE + 0x1ff),
6709 + .flags = IORESOURCE_MEM,
6710 + },
6711 + [1] = {
6712 + .start = INT_USB,
6713 + .flags = IORESOURCE_IRQ,
6714 + },
6715 +};
6716 +
6717 +static int __init otg_host_init(void)
6718 +{
6719 + otg_host_device = host_pdev_register(otg_host_resources,
6720 + ARRAY_SIZE(otg_host_resources),
6721 + &mxc_otg_config);
6722 + return 0;
6723 +}
6724 +
6725 +subsys_initcall(otg_host_init);
6726 --- /dev/null
6727 +++ b/arch/m68k/coldfire/usb/otg_otg.c
6728 @@ -0,0 +1,96 @@
6729 +/*
6730 + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6731 + */
6732 +
6733 +/*
6734 + * The code contained herein is licensed under the GNU General Public
6735 + * License. You may obtain a copy of the GNU General Public License
6736 + * Version 2 or later at the following locations:
6737 + *
6738 + * http://www.opensource.org/licenses/gpl-license.html
6739 + * http://www.gnu.org/copyleft/gpl.html
6740 + */
6741 +
6742 +/*
6743 + * platform_device registration for ULPI OTG device
6744 + */
6745 +
6746 +#include <linux/module.h>
6747 +#include <linux/kernel.h>
6748 +#include <linux/types.h>
6749 +#include <linux/errno.h>
6750 +#include <linux/init.h>
6751 +#include <linux/err.h>
6752 +#include <linux/platform_device.h>
6753 +#include <linux/fsl_devices.h>
6754 +
6755 +#include <asm/mcfsim.h>
6756 +
6757 +#define USB_OTGREGS_BASE MCF_REG32(0xFC0B0000)
6758 +#define INT_USB (64 + 64 + 47) /* INTC1:47 16.2.9.1 */
6759 +#define INT_UOCSR (64 + 64 + 53) /* INTC1:53 16.2.9.1 */
6760 +
6761 +extern int usbotg_init(struct platform_device *pdev);
6762 +extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata);
6763 +extern struct fsl_usb2_platform_data mxc_otg_config;
6764 +
6765 +static void otg_otg_release(struct device *dev)
6766 +{
6767 + /* normally not freed */
6768 +}
6769 +
6770 +/* *INDENT-OFF* */
6771 +static struct resource otg_otg_resources[] = {
6772 + [0] = {
6773 + .start = (u32) (&USB_OTGREGS_BASE),
6774 + .end = (u32) (&USB_OTGREGS_BASE + 0x1ff),
6775 + .flags = IORESOURCE_MEM,
6776 + },
6777 + [1] = {
6778 + .start = INT_USB,
6779 + .flags = IORESOURCE_IRQ,
6780 + },
6781 +};
6782 +
6783 +/*!
6784 + * OTG device
6785 + */
6786 +static u64 otg_otg_dmamask = ~(u32) 0;
6787 +static struct platform_device otg_otg_device = {
6788 + .name = "fsl-usb2-otg",
6789 + .id = -1,
6790 + .dev = {
6791 + .release = otg_otg_release,
6792 + .dma_mask = &otg_otg_dmamask,
6793 + .coherent_dma_mask = 0xffffffff,
6794 + .platform_data = &mxc_otg_config,
6795 + },
6796 + .resource = otg_otg_resources,
6797 + .num_resources = ARRAY_SIZE(otg_otg_resources),
6798 +};
6799 +/* *INDENT-ON* */
6800 +
6801 +static int __init mx31_otg_otg_init(void)
6802 +{
6803 + int rc = 0;
6804 +
6805 + pr_debug("register OTG otg res=0x%p, size=%d\n",
6806 + otg_otg_device.resource, otg_otg_device.num_resources);
6807 +
6808 + rc = platform_device_register(&otg_otg_device);
6809 + if (rc) {
6810 + pr_debug("can't register ULPI OTG dvc, %d\n", rc);
6811 + } else {
6812 + printk(KERN_INFO "usb: OTG ULPI transceiver registered\n");
6813 + pr_debug("otg_otg_device=0x%p resources=0x%p.\n",
6814 + &otg_otg_device, otg_otg_device.resource);
6815 + }
6816 +
6817 + return rc;
6818 +}
6819 +
6820 +subsys_initcall(mx31_otg_otg_init);
6821 +
6822 +MODULE_AUTHOR("Freescale Semiconductor, Inc.");
6823 +MODULE_DESCRIPTION("ULPI OTG device registration");
6824 +MODULE_LICENSE("GPL");
6825 --- /dev/null
6826 +++ b/arch/m68k/coldfire/usb/xcvr.c
6827 @@ -0,0 +1,156 @@
6828 +/*
6829 + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6830 + */
6831 +
6832 +/*
6833 + * The code contained herein is licensed under the GNU General Public
6834 + * License. You may obtain a copy of the GNU General Public License
6835 + * Version 2 or later at the following locations:
6836 + *
6837 + * http://www.opensource.org/licenses/gpl-license.html
6838 + * http://www.gnu.org/copyleft/gpl.html
6839 + */
6840 +
6841 +#include <linux/module.h>
6842 +#include <linux/kernel.h>
6843 +#include <linux/types.h>
6844 +#include <linux/errno.h>
6845 +#include <linux/init.h>
6846 +#include <linux/err.h>
6847 +#include <linux/platform_device.h>
6848 +#include <linux/delay.h>
6849 +#include <linux/fsl_devices.h>
6850 +#include <linux/usb/fsl_xcvr.h>
6851 +#include <linux/usb/fsl_usb2.h>
6852 +
6853 +#include <asm/mcfsim.h>
6854 +
6855 +extern void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops);
6856 +extern void fsl_usb_xcvr_unregister(enum fsl_usb_ctrlr ctrlr);
6857 +
6858 +#define MCF_SCM_BCR MCF_REG32(0xFC040024)
6859 +#define MCF_SCM_BCR_GBR (1 << 9) /* global bursts for read */
6860 +#define MCF_SCM_BCR_GBW (1 << 8) /* global bursts for write */
6861 +#define MCF_SCM_BCR_SBE_ALL (0xff << 0) /* slave burst enable */
6862 +
6863 +
6864 +#ifdef ULPI_DEBUG
6865 +void print_ulpi_regs(void)
6866 +{
6867 + pr_debug("MCF_SCM_BCR=0x%08lx MCF_CCM_MISCCR=0x%08x "
6868 + "MCF_GPIO_PAR_DMA=0x%08x MCF_GPIO_PAR_USB=08%08x "
6869 + "MCF_GPIO_PAR_FEC=08%08x\n",
6870 + MCF_SCM_BCR, MCF_CCM_MISCCR, MCF_GPIO_PAR_DMA,
6871 + MCF_GPIO_PAR_USB, MCF_GPIO_PAR_FEC);
6872 +}
6873 +EXPORT_SYMBOL(print_ulpi_regs);
6874 +#endif
6875 +
6876 +
6877 +static void xcvr_init(struct platform_device *pdev)
6878 +{
6879 + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
6880 + struct fsl_xcvr_ops *this = pdata->xcvr_ops;
6881 + struct fsl_usb_host_regs *regs = pdata->regs;
6882 +
6883 + pr_debug("%s: ctrlr=%d pdata=0x%p regs=0x%p\n", __FUNCTION__,
6884 + this->ctrlr, pdata, pdata->regs);
6885 +
6886 + /* enable USB read, write and slave bursts */
6887 + MCF_SCM_BCR = MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW | MCF_SCM_BCR_SBE_ALL;
6888 +
6889 + /* Use external clock source if PLL isn't a multiple of 60MHz */
6890 + MCF_CCM_MISCCR &= ~MCF_CCM_MISCCR_USBSRC;
6891 +
6892 + /* Initialize the USB Clock: use USB input clock */
6893 + MCF_GPIO_PAR_DMA = (MCF_GPIO_PAR_DMA & MCF_GPIO_PAR_DMA_DREQ1_MASK) |
6894 + MCF_GPIO_PAR_DMA_DREQ1_USB_CLKIN;
6895 +
6896 + switch (this->xcvr_type) {
6897 + case PORTSCX_PTS_ULPI:
6898 + /* Enable the required ULPI signals */
6899 + MCF_GPIO_PAR_DMA = (MCF_GPIO_PAR_DMA &
6900 + MCF_GPIO_PAR_DMA_DACK1_MASK) |
6901 + MCF_GPIO_PAR_DMA_DACK1_ULPI_DIR;
6902 +
6903 + MCF_GPIO_PAR_USB = MCF_GPIO_PAR_USB_VBUSEN_ULPI_NXT |
6904 + MCF_GPIO_PAR_USB_VBUSOC_ULPI_STP;
6905 +
6906 + MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC &
6907 + MCF_GPIO_PAR_FEC_FEC0_MASK) |
6908 + MCF_GPIO_PAR_FEC_FEC0_RMII_ULPI;
6909 + break;
6910 + case PORTSCX_PTS_ONCHIP:
6911 + /* Enable VBUS_EN and VBUS_OC signals */
6912 + MCF_GPIO_PAR_USB = MCF_GPIO_PAR_USB_VBUSEN_VBUSEN |
6913 + MCF_GPIO_PAR_USB_VBUSOC_VBUSOC;
6914 +
6915 + /* Setup USB_VBUS_OC signal to be active-low */
6916 + MCF_CCM_MISCCR |= MCF_CCM_MISCCR_USBOC;
6917 +
6918 + break;
6919 + }
6920 +
6921 + pr_debug("&regs->portsc1=0x%p old portsc1=0x%x \n", &regs->portsc1,
6922 + regs->portsc1);
6923 +
6924 + regs->portsc1 &= ~PORTSCX_PTS_MASK;
6925 + regs->portsc1 |= this->xcvr_type;
6926 +
6927 + /*
6928 + * need to reset the controller here so that the ID pin
6929 + * is correctly detected.
6930 + */
6931 + regs->usbcmd |= USB_CMD_CTRL_RESET;
6932 +
6933 + /*
6934 + * allow controller to reset, and leave time for
6935 + * the ULPI transceiver to reset too.
6936 + */
6937 + mdelay(10);
6938 +
6939 + pr_debug("DDD %s: done. portsc1=0x%x\n", __FUNCTION__, regs->portsc1);
6940 +}
6941 +
6942 +static void xcvr_uninit(struct platform_device *pdev)
6943 +{
6944 + pr_debug("%s: pdev=0x%p\n", __FUNCTION__, pdev);
6945 +}
6946 +
6947 +
6948 +struct fsl_xcvr_ops xcvr_ops_otg = {
6949 + .ctrlr = USB_CTRLR_OTG,
6950 + .init = xcvr_init,
6951 + .uninit = xcvr_uninit,
6952 +
6953 +#ifdef CONFIG_USB_M5445X_ULPI
6954 + .xcvr_type = PORTSCX_PTS_ULPI,
6955 +#elif defined CONFIG_USB_M5445X_FSLS
6956 + .xcvr_type = PORTSCX_PTS_ONCHIP,
6957 +#else
6958 +#error "Invalid USB transceiver selection."
6959 +#endif
6960 +};
6961 +
6962 +static int __init usb_xcvr_init(void)
6963 +{
6964 + pr_debug("%s\n", __FUNCTION__);
6965 +
6966 + fsl_usb_xcvr_register(&xcvr_ops_otg);
6967 +
6968 + pr_debug("%s done\n", __FUNCTION__);
6969 + return 0;
6970 +}
6971 +
6972 +static void __exit usb_xcvr_exit(void)
6973 +{
6974 + fsl_usb_xcvr_unregister(USB_CTRLR_OTG);
6975 +}
6976 +
6977 +module_init(usb_xcvr_init);
6978 +module_exit(usb_xcvr_exit);
6979 +
6980 +MODULE_AUTHOR("Freescale Semiconductor, Inc.");
6981 +MODULE_DESCRIPTION("External ULPI xcvr driver");
6982 +MODULE_LICENSE("GPL");
6983 +
6984 --- /dev/null
6985 +++ b/arch/m68k/coldfire/usb.c
6986 @@ -0,0 +1,182 @@
6987 +/*
6988 + *
6989 + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6990 + *
6991 + * otg_{get,set}_transceiver() are from arm/plat-omap/usb.c.
6992 + * which is Copyright (C) 2004 Texas Instruments, Inc.
6993 + */
6994 +
6995 +/*
6996 + * The code contained herein is licensed under the GNU General Public
6997 + * License. You may obtain a copy of the GNU General Public License
6998 + * Version 2 or later at the following locations:
6999 + *
7000 + * http://www.opensource.org/licenses/gpl-license.html
7001 + * http://www.gnu.org/copyleft/gpl.html
7002 + */
7003 +
7004 +#include <linux/module.h>
7005 +#include <linux/kernel.h>
7006 +#include <linux/types.h>
7007 +#include <linux/errno.h>
7008 +#include <linux/init.h>
7009 +#include <linux/io.h>
7010 +#include <linux/err.h>
7011 +#include <linux/platform_device.h>
7012 +#include <linux/usb/otg.h>
7013 +#include <linux/delay.h>
7014 +#include <linux/fsl_devices.h>
7015 +#include <linux/usb/fsl_xcvr.h>
7016 +
7017 +
7018 +/* The dmamask must be set for EHCI to work */
7019 +static u64 ehci_dmamask = ~(u32) 0;
7020 +
7021 +struct fsl_xcvr_ops *xc_ops[3] = { NULL };
7022 +
7023 +void fsl_usb_enable_clk(void)
7024 +{
7025 +}
7026 +EXPORT_SYMBOL(fsl_usb_enable_clk);
7027 +
7028 +void fsl_usb_disable_clk(void)
7029 +{
7030 +}
7031 +EXPORT_SYMBOL(fsl_usb_disable_clk);
7032 +
7033 +void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops)
7034 +{
7035 + pr_debug("%s ctrlr=%d\n", __FUNCTION__, xcvr_ops->ctrlr);
7036 + xc_ops[xcvr_ops->ctrlr] = xcvr_ops;
7037 +
7038 +}
7039 +EXPORT_SYMBOL(fsl_usb_xcvr_register);
7040 +
7041 +void fsl_usb_xcvr_unregister(enum fsl_usb_ctrlr ctrlr)
7042 +{
7043 + pr_debug("%s ctrlr=%d\n", __FUNCTION__, ctrlr);
7044 + xc_ops[ctrlr] = NULL;
7045 +}
7046 +EXPORT_SYMBOL(fsl_usb_xcvr_unregister);
7047 +
7048 +/*!
7049 + * Register an instance of a USB host platform device.
7050 + *
7051 + * @param res: resource pointer
7052 + * @param n_res: number of resources
7053 + * @param config: config pointer
7054 + *
7055 + * @return newly-registered platform_device
7056 + *
7057 + * DDD fix this comment:
7058 + * The USB controller supports 3 host interfaces, and the
7059 + * kernel can be configured to support some number of them.
7060 + * Each supported host interface is registered as an instance
7061 + * of the "fsl-ehci" device. Call this function multiple times
7062 + * to register each host interface.
7063 + */
7064 +static int instance_id;
7065 +struct platform_device *host_pdev_register(struct resource *res, int n_res,
7066 + struct fsl_usb2_platform_data *config)
7067 +{
7068 + struct platform_device *pdev;
7069 +
7070 + pr_debug("register host res=0x%p, size=%d\n", res, n_res);
7071 +
7072 + pdev = platform_device_register_simple("fsl-ehci",
7073 + instance_id, res, n_res);
7074 + if (IS_ERR(pdev)) {
7075 + printk(KERN_ERR "usb: can't register %s Host, %ld\n",
7076 + config->name, PTR_ERR(pdev));
7077 + return NULL;
7078 + }
7079 +
7080 + pdev->dev.coherent_dma_mask = 0xffffffff;
7081 + pdev->dev.dma_mask = &ehci_dmamask;
7082 +
7083 + /*
7084 + * platform_device_add_data() makes a copy of
7085 + * the platform_data passed in. That makes it
7086 + * impossible to share the same config struct for
7087 + * all OTG devices (host,gadget,otg). So, just
7088 + * set the platform_data pointer ourselves.
7089 + */
7090 + pdev->dev.platform_data = config;
7091 +
7092 + printk(KERN_INFO "usb: %s Host registered\n", config->name);
7093 + pr_debug("pdev=0x%p dev=0x%p resources=0x%p pdata=0x%p\n",
7094 + pdev, &pdev->dev, pdev->resource, pdev->dev.platform_data);
7095 +
7096 + instance_id++;
7097 +
7098 + return pdev;
7099 +}
7100 +
7101 +
7102 +int fsl_usb_mem_init(struct platform_device *pdev)
7103 +{
7104 + struct resource *res;
7105 + struct fsl_usb2_platform_data *pdata;
7106 +
7107 + pdata = (struct fsl_usb2_platform_data *)pdev->dev.platform_data;
7108 +
7109 + pr_debug("%s: pdev=0x%p pdata=0x%p\n", __FUNCTION__, pdev, pdata);
7110 +
7111 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7112 + if (!res) {
7113 + dev_err(&pdev->dev, "no MEM resource.\n");
7114 + return -ENODEV;
7115 + }
7116 +
7117 + pdata->r_start = res->start;
7118 + pdata->r_len = res->end - res->start + 1;
7119 + pr_debug("%s: MEM resource start=0x%x len=0x%x\n", pdata->name,
7120 + res->start, pdata->r_len);
7121 +
7122 + if (!request_mem_region(pdata->r_start, pdata->r_len, "OTG")) {
7123 + dev_err(&pdev->dev, "request_mem_region failed\n");
7124 + return -EBUSY;
7125 + }
7126 + pdata->regs = ioremap(pdata->r_start, pdata->r_len);
7127 + pr_debug("ioremapped to 0x%p\n", pdata->regs);
7128 +
7129 + if (pdata->regs == NULL) {
7130 + dev_err(&pdev->dev, "ioremap failed\n");
7131 + release_mem_region(pdata->r_start, pdata->r_len);
7132 + return -EFAULT;
7133 + }
7134 +
7135 + pr_debug("%s: success\n", __FUNCTION__);
7136 + return 0;
7137 +}
7138 +
7139 +
7140 +#if defined(CONFIG_USB_OTG)
7141 +static struct otg_transceiver *xceiv;
7142 +
7143 +/**
7144 + * otg_get_transceiver - find the (single) OTG transceiver driver
7145 + *
7146 + * Returns the transceiver driver, after getting a refcount to it; or
7147 + * null if there is no such transceiver. The caller is responsible for
7148 + * releasing that count.
7149 + */
7150 +struct otg_transceiver *otg_get_transceiver(void)
7151 +{
7152 + pr_debug("%s xceiv=0x%p\n", __FUNCTION__, xceiv);
7153 + if (xceiv)
7154 + get_device(xceiv->dev);
7155 + return xceiv;
7156 +}
7157 +EXPORT_SYMBOL(otg_get_transceiver);
7158 +
7159 +int otg_set_transceiver(struct otg_transceiver *x)
7160 +{
7161 + pr_debug("%s xceiv=0x%p x=0x%p\n", __FUNCTION__, xceiv, x);
7162 + if (xceiv && x)
7163 + return -EBUSY;
7164 + xceiv = x;
7165 + return 0;
7166 +}
7167 +EXPORT_SYMBOL(otg_set_transceiver);
7168 +#endif
7169 --- /dev/null
7170 +++ b/arch/m68k/coldfire/vmlinux-cf.lds
7171 @@ -0,0 +1,130 @@
7172 +/* ld script to make m68k Coldfire Linux kernel
7173 + *
7174 + * Derived from arch/m68k/kernel/vmlinux-std.lds
7175 + *
7176 + * Updated 11/26/2007 for new CodeSourcery toolset
7177 + * by Kurt Mahan <kmahan@freescale.com>
7178 + */
7179 +
7180 +#define LOAD_OFFSET 0x00000000
7181 +
7182 +#include <asm-generic/vmlinux.lds.h>
7183 +#include <asm/page_offset.h>
7184 +
7185 +#define START_OFFSET 0x00020000
7186 +#define IMAGE_START PAGE_OFFSET_RAW + START_OFFSET
7187 +
7188 +OUTPUT_FORMAT("elf32-m68k", "elf32-m68k", "elf32-m68k")
7189 +OUTPUT_ARCH(m68k)
7190 +ENTRY(_stext)
7191 +jiffies = jiffies_64 + 4;
7192 +
7193 +SECTIONS
7194 +{
7195 + . = IMAGE_START;
7196 + .text.head : AT(ADDR(.text.head) - LOAD_OFFSET) {
7197 + _text = .; /* Text and read-only data */
7198 + *(.text.head)
7199 + } :text = 0x4e75
7200 +
7201 + .text : AT(ADDR(.text) - LOAD_OFFSET) {
7202 + TEXT_TEXT
7203 + SCHED_TEXT
7204 + LOCK_TEXT
7205 + *(.fixup)
7206 + *(.gnu.warning)
7207 + } :text = 0x4e75
7208 + _etext = .; /* End of text section */
7209 +
7210 + . = ALIGN(16);
7211 + __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) {
7212 + __start___ex_table = .;
7213 + *(__ex_table)
7214 + __stop___ex_table = .;
7215 + }
7216 +
7217 + RODATA
7218 +
7219 + . = ALIGN(8192);
7220 + .data : AT(ADDR(.data) - LOAD_OFFSET) { /* Data */
7221 + DATA_DATA
7222 + CONSTRUCTORS
7223 + } :data
7224 +
7225 +
7226 + . = ALIGN(16);
7227 + .data.cacheline_aligned : AT(ADDR(.data.cacheline_aligned) - LOAD_OFFSET ) {
7228 + *(.data.cacheline_aligned)
7229 + } :data
7230 +
7231 + _edata = .; /* End of data section */
7232 +
7233 + NOTES /* support ld --build-id */
7234 +
7235 + . = ALIGN(8192); /* Initrd */
7236 + .init.text : AT(ADDR(.init.text) - LOAD_OFFSET) {
7237 + __init_begin = .;
7238 + _sinittext = .;
7239 + *(.init.text)
7240 + _einittext = .;
7241 + }
7242 +
7243 + .init.data : AT(ADDR(.init.data) - LOAD_OFFSET) {
7244 + *(.init.data)
7245 + }
7246 +
7247 + . = ALIGN(16);
7248 + .init.setup : AT(ADDR(.init.setup) - LOAD_OFFSET) {
7249 + __setup_start = .;
7250 + *(.init.setup)
7251 + __setup_end = .;
7252 + }
7253 +
7254 + .initcall.init : AT(ADDR(.initcall.init) - LOAD_OFFSET) {
7255 + __initcall_start = .;
7256 + INITCALLS
7257 + __initcall_end = .;
7258 + }
7259 +
7260 + .con_initcall.init : AT(ADDR(.con_initcall.init) - LOAD_OFFSET) {
7261 + __con_initcall_start = .;
7262 + *(.con_initcall.init)
7263 + __con_initcall_end = .;
7264 + }
7265 +
7266 + SECURITY_INIT
7267 +
7268 +#ifdef CONFIG_BLK_DEV_INITRD
7269 + . = ALIGN(8192);
7270 + .init.ramfs : AT(ADDR(.init.ramfs) - LOAD_OFFSET) {
7271 + __initramfs_start = .;
7272 + *(.init.ramfs)
7273 + __initramfs_end = .;
7274 + }
7275 +#endif
7276 +
7277 + . = ALIGN(8192);
7278 + __init_end = .;
7279 +
7280 + .data.init_task : AT(ADDR(.data.init_task) - LOAD_OFFSET) {
7281 + *(.data.init_task) /* The initial task and kernel stack */
7282 + }
7283 +
7284 + _sbss = .;
7285 + .bss : AT(ADDR(.bss) - LOAD_OFFSET) { /* BSS */
7286 + *(.bss)
7287 + }
7288 + _ebss = .;
7289 +
7290 + _end = . ;
7291 +
7292 + /* Sections to be discarded */
7293 + /DISCARD/ : {
7294 + *(.exit.text)
7295 + *(.exit.data)
7296 + *(.exitcall.exit)
7297 + }
7298 +
7299 + /* Stabs debugging sections. */
7300 + STABS_DEBUG
7301 +}
7302 --- /dev/null
7303 +++ b/arch/m68k/configs/55_defconfig
7304 @@ -0,0 +1,830 @@
7305 +#
7306 +# Automatically generated make config: don't edit
7307 +# Linux kernel version: 2.6.25
7308 +# Thu Jun 26 16:17:41 2008
7309 +#
7310 +CONFIG_M68K=y
7311 +CONFIG_MMU=y
7312 +# CONFIG_GENERIC_TIME is not set
7313 +# CONFIG_GENERIC_CLOCKEVENTS is not set
7314 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
7315 +# CONFIG_ARCH_HAS_ILOG2_U32 is not set
7316 +# CONFIG_ARCH_HAS_ILOG2_U64 is not set
7317 +CONFIG_GENERIC_HWEIGHT=y
7318 +CONFIG_GENERIC_CALIBRATE_DELAY=y
7319 +CONFIG_TIME_LOW_RES=y
7320 +CONFIG_GENERIC_IOMAP=y
7321 +# CONFIG_NO_IOPORT is not set
7322 +# CONFIG_NO_DMA is not set
7323 +CONFIG_ARCH_SUPPORTS_AOUT=y
7324 +CONFIG_HZ=100
7325 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
7326 +
7327 +#
7328 +# General setup
7329 +#
7330 +CONFIG_EXPERIMENTAL=y
7331 +CONFIG_BROKEN_ON_SMP=y
7332 +CONFIG_INIT_ENV_ARG_LIMIT=32
7333 +CONFIG_LOCALVERSION=""
7334 +CONFIG_LOCALVERSION_AUTO=y
7335 +CONFIG_SWAP=y
7336 +CONFIG_SYSVIPC=y
7337 +CONFIG_SYSVIPC_SYSCTL=y
7338 +# CONFIG_POSIX_MQUEUE is not set
7339 +# CONFIG_BSD_PROCESS_ACCT is not set
7340 +# CONFIG_TASKSTATS is not set
7341 +# CONFIG_AUDIT is not set
7342 +CONFIG_IKCONFIG=y
7343 +CONFIG_IKCONFIG_PROC=y
7344 +CONFIG_LOG_BUF_SHIFT=17
7345 +# CONFIG_CGROUPS is not set
7346 +CONFIG_GROUP_SCHED=y
7347 +CONFIG_FAIR_GROUP_SCHED=y
7348 +# CONFIG_RT_GROUP_SCHED is not set
7349 +CONFIG_USER_SCHED=y
7350 +# CONFIG_CGROUP_SCHED is not set
7351 +CONFIG_SYSFS_DEPRECATED=y
7352 +CONFIG_SYSFS_DEPRECATED_V2=y
7353 +# CONFIG_RELAY is not set
7354 +CONFIG_NAMESPACES=y
7355 +# CONFIG_UTS_NS is not set
7356 +# CONFIG_IPC_NS is not set
7357 +# CONFIG_USER_NS is not set
7358 +# CONFIG_PID_NS is not set
7359 +# CONFIG_BLK_DEV_INITRD is not set
7360 +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
7361 +CONFIG_SYSCTL=y
7362 +# CONFIG_EMBEDDED is not set
7363 +CONFIG_UID16=y
7364 +CONFIG_SYSCTL_SYSCALL=y
7365 +CONFIG_KALLSYMS=y
7366 +# CONFIG_KALLSYMS_ALL is not set
7367 +# CONFIG_KALLSYMS_EXTRA_PASS is not set
7368 +CONFIG_HOTPLUG=y
7369 +CONFIG_PRINTK=y
7370 +CONFIG_BUG=y
7371 +CONFIG_ELF_CORE=y
7372 +CONFIG_COMPAT_BRK=y
7373 +CONFIG_BASE_FULL=y
7374 +CONFIG_FUTEX=y
7375 +CONFIG_ANON_INODES=y
7376 +CONFIG_EPOLL=y
7377 +CONFIG_SIGNALFD=y
7378 +CONFIG_TIMERFD=y
7379 +CONFIG_EVENTFD=y
7380 +CONFIG_SHMEM=y
7381 +CONFIG_VM_EVENT_COUNTERS=y
7382 +CONFIG_SLAB=y
7383 +# CONFIG_SLUB is not set
7384 +# CONFIG_SLOB is not set
7385 +# CONFIG_PROFILING is not set
7386 +# CONFIG_MARKERS is not set
7387 +# CONFIG_HAVE_OPROFILE is not set
7388 +# CONFIG_HAVE_KPROBES is not set
7389 +# CONFIG_HAVE_KRETPROBES is not set
7390 +CONFIG_PROC_PAGE_MONITOR=y
7391 +CONFIG_SLABINFO=y
7392 +CONFIG_RT_MUTEXES=y
7393 +# CONFIG_TINY_SHMEM is not set
7394 +CONFIG_BASE_SMALL=0
7395 +CONFIG_MODULES=y
7396 +CONFIG_MODULE_UNLOAD=y
7397 +CONFIG_MODULE_FORCE_UNLOAD=y
7398 +# CONFIG_MODVERSIONS is not set
7399 +# CONFIG_MODULE_SRCVERSION_ALL is not set
7400 +# CONFIG_KMOD is not set
7401 +CONFIG_BLOCK=y
7402 +CONFIG_LBD=y
7403 +# CONFIG_BLK_DEV_IO_TRACE is not set
7404 +# CONFIG_LSF is not set
7405 +# CONFIG_BLK_DEV_BSG is not set
7406 +
7407 +#
7408 +# IO Schedulers
7409 +#
7410 +CONFIG_IOSCHED_NOOP=y
7411 +CONFIG_IOSCHED_AS=y
7412 +CONFIG_IOSCHED_DEADLINE=y
7413 +CONFIG_IOSCHED_CFQ=y
7414 +# CONFIG_DEFAULT_AS is not set
7415 +# CONFIG_DEFAULT_DEADLINE is not set
7416 +CONFIG_DEFAULT_CFQ=y
7417 +# CONFIG_DEFAULT_NOOP is not set
7418 +CONFIG_DEFAULT_IOSCHED="cfq"
7419 +CONFIG_CLASSIC_RCU=y
7420 +
7421 +#
7422 +# Platform dependent setup
7423 +#
7424 +# CONFIG_SUN3 is not set
7425 +CONFIG_COLDFIRE=y
7426 +CONFIG_CFV4E=y
7427 +# CONFIG_AMIGA is not set
7428 +# CONFIG_ATARI is not set
7429 +# CONFIG_PCI is not set
7430 +# CONFIG_MAC is not set
7431 +# CONFIG_APOLLO is not set
7432 +# CONFIG_VME is not set
7433 +# CONFIG_HP300 is not set
7434 +# CONFIG_SUN3X is not set
7435 +# CONFIG_Q40 is not set
7436 +
7437 +#
7438 +# Processor type
7439 +#
7440 +# CONFIG_M68020 is not set
7441 +# CONFIG_M68030 is not set
7442 +# CONFIG_M68040 is not set
7443 +# CONFIG_M68060 is not set
7444 +CONFIG_M5445X=y
7445 +# CONFIG_M54451 is not set
7446 +CONFIG_M54455=y
7447 +# CONFIG_M54451EVB is not set
7448 +CONFIG_M54455EVB=y
7449 +# CONFIG_M547X_8X is not set
7450 +CONFIG_MCFCLK=266666666
7451 +# CONFIG_MCF_USER_HALT is not set
7452 +CONFIG_MMU_CFV4E=y
7453 +CONFIG_SDRAM_BASE=0x40000000
7454 +CONFIG_SDRAM_SIZE=0x10000000
7455 +CONFIG_NOR_FLASH_BASE=0x00000000
7456 +# CONFIG_M68KFPU_EMU is not set
7457 +CONFIG_ADVANCED=y
7458 +# CONFIG_RMW_INSNS is not set
7459 +CONFIG_SINGLE_MEMORY_CHUNK=y
7460 +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
7461 +CONFIG_SELECT_MEMORY_MODEL=y
7462 +CONFIG_FLATMEM_MANUAL=y
7463 +# CONFIG_DISCONTIGMEM_MANUAL is not set
7464 +# CONFIG_SPARSEMEM_MANUAL is not set
7465 +CONFIG_FLATMEM=y
7466 +CONFIG_FLAT_NODE_MEM_MAP=y
7467 +CONFIG_NEED_MULTIPLE_NODES=y
7468 +# CONFIG_SPARSEMEM_STATIC is not set
7469 +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
7470 +CONFIG_SPLIT_PTLOCK_CPUS=4
7471 +# CONFIG_RESOURCES_64BIT is not set
7472 +CONFIG_ZONE_DMA_FLAG=1
7473 +CONFIG_BOUNCE=y
7474 +CONFIG_VIRT_TO_BUS=y
7475 +
7476 +#
7477 +# General setup
7478 +#
7479 +CONFIG_BINFMT_ELF=y
7480 +# CONFIG_BINFMT_AOUT is not set
7481 +# CONFIG_BINFMT_MISC is not set
7482 +CONFIG_PROC_HARDWARE=y
7483 +CONFIG_ZONE_DMA=y
7484 +# CONFIG_ARCH_SUPPORTS_MSI is not set
7485 +
7486 +#
7487 +# Power management options
7488 +#
7489 +# CONFIG_PM is not set
7490 +
7491 +#
7492 +# Networking
7493 +#
7494 +CONFIG_NET=y
7495 +
7496 +#
7497 +# Networking options
7498 +#
7499 +CONFIG_PACKET=y
7500 +# CONFIG_PACKET_MMAP is not set
7501 +CONFIG_UNIX=y
7502 +CONFIG_XFRM=y
7503 +# CONFIG_XFRM_USER is not set
7504 +# CONFIG_XFRM_SUB_POLICY is not set
7505 +# CONFIG_XFRM_MIGRATE is not set
7506 +# CONFIG_XFRM_STATISTICS is not set
7507 +CONFIG_NET_KEY=y
7508 +# CONFIG_NET_KEY_MIGRATE is not set
7509 +CONFIG_INET=y
7510 +# CONFIG_IP_MULTICAST is not set
7511 +CONFIG_IP_ADVANCED_ROUTER=y
7512 +CONFIG_ASK_IP_FIB_HASH=y
7513 +# CONFIG_IP_FIB_TRIE is not set
7514 +CONFIG_IP_FIB_HASH=y
7515 +# CONFIG_IP_MULTIPLE_TABLES is not set
7516 +# CONFIG_IP_ROUTE_MULTIPATH is not set
7517 +# CONFIG_IP_ROUTE_VERBOSE is not set
7518 +CONFIG_IP_PNP=y
7519 +# CONFIG_IP_PNP_DHCP is not set
7520 +# CONFIG_IP_PNP_BOOTP is not set
7521 +# CONFIG_IP_PNP_RARP is not set
7522 +# CONFIG_NET_IPIP is not set
7523 +# CONFIG_NET_IPGRE is not set
7524 +# CONFIG_ARPD is not set
7525 +# CONFIG_SYN_COOKIES is not set
7526 +CONFIG_INET_AH=y
7527 +CONFIG_INET_ESP=y
7528 +# CONFIG_INET_IPCOMP is not set
7529 +# CONFIG_INET_XFRM_TUNNEL is not set
7530 +# CONFIG_INET_TUNNEL is not set
7531 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
7532 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
7533 +# CONFIG_INET_XFRM_MODE_BEET is not set
7534 +# CONFIG_INET_LRO is not set
7535 +CONFIG_INET_DIAG=y
7536 +CONFIG_INET_TCP_DIAG=y
7537 +# CONFIG_TCP_CONG_ADVANCED is not set
7538 +CONFIG_TCP_CONG_CUBIC=y
7539 +CONFIG_DEFAULT_TCP_CONG="cubic"
7540 +# CONFIG_TCP_MD5SIG is not set
7541 +# CONFIG_IPV6 is not set
7542 +# CONFIG_INET6_XFRM_TUNNEL is not set
7543 +# CONFIG_INET6_TUNNEL is not set
7544 +# CONFIG_NETWORK_SECMARK is not set
7545 +# CONFIG_NETFILTER is not set
7546 +# CONFIG_IP_DCCP is not set
7547 +# CONFIG_IP_SCTP is not set
7548 +# CONFIG_TIPC is not set
7549 +# CONFIG_ATM is not set
7550 +# CONFIG_BRIDGE is not set
7551 +# CONFIG_VLAN_8021Q is not set
7552 +# CONFIG_DECNET is not set
7553 +# CONFIG_LLC2 is not set
7554 +# CONFIG_IPX is not set
7555 +# CONFIG_ATALK is not set
7556 +# CONFIG_X25 is not set
7557 +# CONFIG_LAPB is not set
7558 +# CONFIG_ECONET is not set
7559 +# CONFIG_WAN_ROUTER is not set
7560 +# CONFIG_NET_SCHED is not set
7561 +
7562 +#
7563 +# Network testing
7564 +#
7565 +# CONFIG_NET_PKTGEN is not set
7566 +# CONFIG_HAMRADIO is not set
7567 +# CONFIG_CAN is not set
7568 +# CONFIG_IRDA is not set
7569 +# CONFIG_BT is not set
7570 +# CONFIG_AF_RXRPC is not set
7571 +
7572 +#
7573 +# Wireless
7574 +#
7575 +# CONFIG_CFG80211 is not set
7576 +# CONFIG_WIRELESS_EXT is not set
7577 +# CONFIG_MAC80211 is not set
7578 +# CONFIG_IEEE80211 is not set
7579 +# CONFIG_RFKILL is not set
7580 +# CONFIG_NET_9P is not set
7581 +
7582 +#
7583 +# Device Drivers
7584 +#
7585 +
7586 +#
7587 +# Generic Driver Options
7588 +#
7589 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
7590 +# CONFIG_STANDALONE is not set
7591 +CONFIG_PREVENT_FIRMWARE_BUILD=y
7592 +CONFIG_FW_LOADER=y
7593 +# CONFIG_DEBUG_DRIVER is not set
7594 +# CONFIG_DEBUG_DEVRES is not set
7595 +# CONFIG_SYS_HYPERVISOR is not set
7596 +# CONFIG_CONNECTOR is not set
7597 +# CONFIG_MTD is not set
7598 +# CONFIG_PARPORT is not set
7599 +CONFIG_BLK_DEV=y
7600 +# CONFIG_BLK_DEV_COW_COMMON is not set
7601 +CONFIG_BLK_DEV_LOOP=y
7602 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set
7603 +# CONFIG_BLK_DEV_NBD is not set
7604 +CONFIG_BLK_DEV_RAM=y
7605 +CONFIG_BLK_DEV_RAM_COUNT=16
7606 +CONFIG_BLK_DEV_RAM_SIZE=64000
7607 +# CONFIG_BLK_DEV_XIP is not set
7608 +# CONFIG_CDROM_PKTCDVD is not set
7609 +# CONFIG_ATA_OVER_ETH is not set
7610 +CONFIG_MISC_DEVICES=y
7611 +# CONFIG_COLDFIRE_SEC is not set
7612 +# CONFIG_EEPROM_93CX6 is not set
7613 +# CONFIG_ENCLOSURE_SERVICES is not set
7614 +CONFIG_HAVE_IDE=y
7615 +# CONFIG_IDE is not set
7616 +
7617 +#
7618 +# SCSI device support
7619 +#
7620 +# CONFIG_RAID_ATTRS is not set
7621 +CONFIG_SCSI=y
7622 +CONFIG_SCSI_DMA=y
7623 +# CONFIG_SCSI_TGT is not set
7624 +# CONFIG_SCSI_NETLINK is not set
7625 +CONFIG_SCSI_PROC_FS=y
7626 +
7627 +#
7628 +# SCSI support type (disk, tape, CD-ROM)
7629 +#
7630 +CONFIG_BLK_DEV_SD=y
7631 +# CONFIG_CHR_DEV_ST is not set
7632 +# CONFIG_CHR_DEV_OSST is not set
7633 +# CONFIG_BLK_DEV_SR is not set
7634 +# CONFIG_CHR_DEV_SG is not set
7635 +# CONFIG_CHR_DEV_SCH is not set
7636 +
7637 +#
7638 +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
7639 +#
7640 +CONFIG_SCSI_MULTI_LUN=y
7641 +# CONFIG_SCSI_CONSTANTS is not set
7642 +# CONFIG_SCSI_LOGGING is not set
7643 +# CONFIG_SCSI_SCAN_ASYNC is not set
7644 +CONFIG_SCSI_WAIT_SCAN=m
7645 +
7646 +#
7647 +# SCSI Transports
7648 +#
7649 +# CONFIG_SCSI_SPI_ATTRS is not set
7650 +# CONFIG_SCSI_FC_ATTRS is not set
7651 +# CONFIG_SCSI_ISCSI_ATTRS is not set
7652 +# CONFIG_SCSI_SAS_LIBSAS is not set
7653 +# CONFIG_SCSI_SRP_ATTRS is not set
7654 +CONFIG_SCSI_LOWLEVEL=y
7655 +# CONFIG_ISCSI_TCP is not set
7656 +# CONFIG_SCSI_DEBUG is not set
7657 +# CONFIG_ATA is not set
7658 +# CONFIG_MD is not set
7659 +CONFIG_NETDEVICES=y
7660 +# CONFIG_NETDEVICES_MULTIQUEUE is not set
7661 +# CONFIG_DUMMY is not set
7662 +# CONFIG_BONDING is not set
7663 +# CONFIG_MACVLAN is not set
7664 +# CONFIG_EQUALIZER is not set
7665 +# CONFIG_TUN is not set
7666 +# CONFIG_VETH is not set
7667 +# CONFIG_PHYLIB is not set
7668 +CONFIG_NET_ETHERNET=y
7669 +CONFIG_MII=y
7670 +# CONFIG_IBM_NEW_EMAC_ZMII is not set
7671 +# CONFIG_IBM_NEW_EMAC_RGMII is not set
7672 +# CONFIG_IBM_NEW_EMAC_TAH is not set
7673 +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
7674 +# CONFIG_B44 is not set
7675 +CONFIG_FEC=y
7676 +# CONFIG_FEC2 is not set
7677 +# CONFIG_NETDEV_1000 is not set
7678 +# CONFIG_NETDEV_10000 is not set
7679 +
7680 +#
7681 +# Wireless LAN
7682 +#
7683 +# CONFIG_WLAN_PRE80211 is not set
7684 +# CONFIG_WLAN_80211 is not set
7685 +# CONFIG_WAN is not set
7686 +# CONFIG_PPP is not set
7687 +# CONFIG_SLIP is not set
7688 +# CONFIG_NETCONSOLE is not set
7689 +# CONFIG_NETPOLL is not set
7690 +# CONFIG_NET_POLL_CONTROLLER is not set
7691 +# CONFIG_ISDN is not set
7692 +# CONFIG_PHONE is not set
7693 +
7694 +#
7695 +# Input device support
7696 +#
7697 +CONFIG_INPUT=y
7698 +# CONFIG_INPUT_FF_MEMLESS is not set
7699 +# CONFIG_INPUT_POLLDEV is not set
7700 +
7701 +#
7702 +# Userland interfaces
7703 +#
7704 +CONFIG_INPUT_MOUSEDEV=y
7705 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
7706 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
7707 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
7708 +# CONFIG_INPUT_JOYDEV is not set
7709 +CONFIG_INPUT_EVDEV=y
7710 +# CONFIG_INPUT_EVBUG is not set
7711 +
7712 +#
7713 +# Input Device Drivers
7714 +#
7715 +CONFIG_INPUT_KEYBOARD=y
7716 +# CONFIG_KEYBOARD_ATKBD is not set
7717 +# CONFIG_KEYBOARD_SUNKBD is not set
7718 +# CONFIG_KEYBOARD_LKKBD is not set
7719 +# CONFIG_KEYBOARD_XTKBD is not set
7720 +# CONFIG_KEYBOARD_NEWTON is not set
7721 +# CONFIG_KEYBOARD_STOWAWAY is not set
7722 +# CONFIG_INPUT_MOUSE is not set
7723 +# CONFIG_INPUT_JOYSTICK is not set
7724 +# CONFIG_INPUT_TABLET is not set
7725 +# CONFIG_INPUT_TOUCHSCREEN is not set
7726 +# CONFIG_INPUT_MISC is not set
7727 +
7728 +#
7729 +# Hardware I/O ports
7730 +#
7731 +CONFIG_SERIO=y
7732 +CONFIG_SERIO_SERPORT=y
7733 +# CONFIG_SERIO_RAW is not set
7734 +# CONFIG_GAMEPORT is not set
7735 +
7736 +#
7737 +# Character devices
7738 +#
7739 +CONFIG_VT=y
7740 +CONFIG_VT_CONSOLE=y
7741 +CONFIG_HW_CONSOLE=y
7742 +# CONFIG_VT_HW_CONSOLE_BINDING is not set
7743 +# CONFIG_SERIAL_NONSTANDARD is not set
7744 +
7745 +#
7746 +# Serial drivers
7747 +#
7748 +# CONFIG_SERIAL_8250 is not set
7749 +
7750 +#
7751 +# Non-8250 serial port support
7752 +#
7753 +CONFIG_SERIAL_COLDFIRE=y
7754 +# CONFIG_SERIAL_MCF is not set
7755 +CONFIG_UNIX98_PTYS=y
7756 +# CONFIG_LEGACY_PTYS is not set
7757 +# CONFIG_IPMI_HANDLER is not set
7758 +# CONFIG_HW_RANDOM is not set
7759 +# CONFIG_GEN_RTC is not set
7760 +# CONFIG_R3964 is not set
7761 +# CONFIG_RAW_DRIVER is not set
7762 +# CONFIG_TCG_TPM is not set
7763 +CONFIG_I2C=y
7764 +CONFIG_I2C_BOARDINFO=y
7765 +CONFIG_I2C_CHARDEV=y
7766 +
7767 +#
7768 +# I2C Algorithms
7769 +#
7770 +# CONFIG_I2C_ALGOBIT is not set
7771 +# CONFIG_I2C_ALGOPCF is not set
7772 +# CONFIG_I2C_ALGOPCA is not set
7773 +
7774 +#
7775 +# I2C Hardware Bus support
7776 +#
7777 +# CONFIG_I2C_MCF548x is not set
7778 +CONFIG_I2C_MCF=y
7779 +# CONFIG_I2C_OCORES is not set
7780 +# CONFIG_I2C_PARPORT_LIGHT is not set
7781 +# CONFIG_I2C_SIMTEC is not set
7782 +# CONFIG_I2C_TAOS_EVM is not set
7783 +# CONFIG_I2C_STUB is not set
7784 +
7785 +#
7786 +# Miscellaneous I2C Chip support
7787 +#
7788 +# CONFIG_DS1682 is not set
7789 +# CONFIG_SENSORS_EEPROM is not set
7790 +# CONFIG_SENSORS_PCF8574 is not set
7791 +# CONFIG_PCF8575 is not set
7792 +# CONFIG_SENSORS_PCF8591 is not set
7793 +# CONFIG_TPS65010 is not set
7794 +# CONFIG_SENSORS_MAX6875 is not set
7795 +# CONFIG_SENSORS_TSL2550 is not set
7796 +# CONFIG_I2C_DEBUG_CORE is not set
7797 +# CONFIG_I2C_DEBUG_ALGO is not set
7798 +# CONFIG_I2C_DEBUG_BUS is not set
7799 +# CONFIG_I2C_DEBUG_CHIP is not set
7800 +
7801 +#
7802 +# SPI support
7803 +#
7804 +# CONFIG_SPI is not set
7805 +# CONFIG_COLDFIRE_EDMA is not set
7806 +# CONFIG_SPI_MASTER is not set
7807 +# CONFIG_W1 is not set
7808 +# CONFIG_POWER_SUPPLY is not set
7809 +# CONFIG_HWMON is not set
7810 +# CONFIG_THERMAL is not set
7811 +# CONFIG_WATCHDOG is not set
7812 +
7813 +#
7814 +# Sonics Silicon Backplane
7815 +#
7816 +CONFIG_SSB_POSSIBLE=y
7817 +# CONFIG_SSB is not set
7818 +
7819 +#
7820 +# Multifunction device drivers
7821 +#
7822 +# CONFIG_MFD_SM501 is not set
7823 +
7824 +#
7825 +# Multimedia devices
7826 +#
7827 +# CONFIG_VIDEO_DEV is not set
7828 +# CONFIG_DVB_CORE is not set
7829 +CONFIG_DAB=y
7830 +
7831 +#
7832 +# Graphics support
7833 +#
7834 +# CONFIG_VGASTATE is not set
7835 +CONFIG_VIDEO_OUTPUT_CONTROL=m
7836 +# CONFIG_FB is not set
7837 +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
7838 +
7839 +#
7840 +# Display device support
7841 +#
7842 +# CONFIG_DISPLAY_SUPPORT is not set
7843 +
7844 +#
7845 +# Console display driver support
7846 +#
7847 +CONFIG_DUMMY_CONSOLE=y
7848 +
7849 +#
7850 +# Sound
7851 +#
7852 +# CONFIG_SOUND is not set
7853 +# CONFIG_HID_SUPPORT is not set
7854 +# CONFIG_USB_SUPPORT is not set
7855 +# CONFIG_MMC is not set
7856 +# CONFIG_MEMSTICK is not set
7857 +# CONFIG_NEW_LEDS is not set
7858 +# CONFIG_RTC_CLASS is not set
7859 +
7860 +#
7861 +# Userspace I/O
7862 +#
7863 +# CONFIG_UIO is not set
7864 +
7865 +#
7866 +# Character devices
7867 +#
7868 +# CONFIG_SERIAL_CONSOLE is not set
7869 +
7870 +#
7871 +# File systems
7872 +#
7873 +CONFIG_EXT2_FS=y
7874 +# CONFIG_EXT2_FS_XATTR is not set
7875 +# CONFIG_EXT2_FS_XIP is not set
7876 +CONFIG_EXT3_FS=y
7877 +CONFIG_EXT3_FS_XATTR=y
7878 +# CONFIG_EXT3_FS_POSIX_ACL is not set
7879 +# CONFIG_EXT3_FS_SECURITY is not set
7880 +# CONFIG_EXT4DEV_FS is not set
7881 +CONFIG_JBD=y
7882 +CONFIG_FS_MBCACHE=y
7883 +# CONFIG_REISERFS_FS is not set
7884 +# CONFIG_JFS_FS is not set
7885 +# CONFIG_FS_POSIX_ACL is not set
7886 +# CONFIG_XFS_FS is not set
7887 +# CONFIG_GFS2_FS is not set
7888 +# CONFIG_OCFS2_FS is not set
7889 +CONFIG_DNOTIFY=y
7890 +# CONFIG_INOTIFY is not set
7891 +# CONFIG_QUOTA is not set
7892 +# CONFIG_AUTOFS_FS is not set
7893 +# CONFIG_AUTOFS4_FS is not set
7894 +# CONFIG_FUSE_FS is not set
7895 +
7896 +#
7897 +# CD-ROM/DVD Filesystems
7898 +#
7899 +# CONFIG_ISO9660_FS is not set
7900 +# CONFIG_UDF_FS is not set
7901 +
7902 +#
7903 +# DOS/FAT/NT Filesystems
7904 +#
7905 +CONFIG_FAT_FS=y
7906 +CONFIG_MSDOS_FS=y
7907 +CONFIG_VFAT_FS=y
7908 +CONFIG_FAT_DEFAULT_CODEPAGE=437
7909 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
7910 +CONFIG_NTFS_FS=y
7911 +# CONFIG_NTFS_DEBUG is not set
7912 +CONFIG_NTFS_RW=y
7913 +
7914 +#
7915 +# Pseudo filesystems
7916 +#
7917 +CONFIG_PROC_FS=y
7918 +# CONFIG_PROC_KCORE is not set
7919 +CONFIG_PROC_SYSCTL=y
7920 +CONFIG_SYSFS=y
7921 +CONFIG_TMPFS=y
7922 +# CONFIG_TMPFS_POSIX_ACL is not set
7923 +# CONFIG_HUGETLB_PAGE is not set
7924 +# CONFIG_CONFIGFS_FS is not set
7925 +
7926 +#
7927 +# Miscellaneous filesystems
7928 +#
7929 +# CONFIG_ADFS_FS is not set
7930 +# CONFIG_AFFS_FS is not set
7931 +# CONFIG_HFS_FS is not set
7932 +# CONFIG_HFSPLUS_FS is not set
7933 +# CONFIG_BEFS_FS is not set
7934 +# CONFIG_BFS_FS is not set
7935 +# CONFIG_EFS_FS is not set
7936 +# CONFIG_CRAMFS is not set
7937 +# CONFIG_VXFS_FS is not set
7938 +CONFIG_MINIX_FS=y
7939 +# CONFIG_HPFS_FS is not set
7940 +# CONFIG_QNX4FS_FS is not set
7941 +# CONFIG_ROMFS_FS is not set
7942 +# CONFIG_SYSV_FS is not set
7943 +# CONFIG_UFS_FS is not set
7944 +CONFIG_NETWORK_FILESYSTEMS=y
7945 +CONFIG_NFS_FS=y
7946 +# CONFIG_NFS_V3 is not set
7947 +# CONFIG_NFS_V4 is not set
7948 +# CONFIG_NFS_DIRECTIO is not set
7949 +# CONFIG_NFSD is not set
7950 +CONFIG_ROOT_NFS=y
7951 +CONFIG_LOCKD=y
7952 +CONFIG_NFS_COMMON=y
7953 +CONFIG_SUNRPC=y
7954 +# CONFIG_SUNRPC_BIND34 is not set
7955 +# CONFIG_RPCSEC_GSS_KRB5 is not set
7956 +# CONFIG_RPCSEC_GSS_SPKM3 is not set
7957 +# CONFIG_SMB_FS is not set
7958 +# CONFIG_CIFS is not set
7959 +# CONFIG_NCP_FS is not set
7960 +# CONFIG_CODA_FS is not set
7961 +# CONFIG_AFS_FS is not set
7962 +
7963 +#
7964 +# Partition Types
7965 +#
7966 +CONFIG_PARTITION_ADVANCED=y
7967 +# CONFIG_ACORN_PARTITION is not set
7968 +# CONFIG_OSF_PARTITION is not set
7969 +# CONFIG_AMIGA_PARTITION is not set
7970 +# CONFIG_ATARI_PARTITION is not set
7971 +# CONFIG_MAC_PARTITION is not set
7972 +CONFIG_MSDOS_PARTITION=y
7973 +# CONFIG_BSD_DISKLABEL is not set
7974 +# CONFIG_MINIX_SUBPARTITION is not set
7975 +# CONFIG_SOLARIS_X86_PARTITION is not set
7976 +# CONFIG_UNIXWARE_DISKLABEL is not set
7977 +# CONFIG_LDM_PARTITION is not set
7978 +# CONFIG_SGI_PARTITION is not set
7979 +# CONFIG_ULTRIX_PARTITION is not set
7980 +# CONFIG_SUN_PARTITION is not set
7981 +# CONFIG_KARMA_PARTITION is not set
7982 +# CONFIG_EFI_PARTITION is not set
7983 +# CONFIG_SYSV68_PARTITION is not set
7984 +CONFIG_NLS=y
7985 +CONFIG_NLS_DEFAULT="iso8859-1"
7986 +CONFIG_NLS_CODEPAGE_437=y
7987 +# CONFIG_NLS_CODEPAGE_737 is not set
7988 +# CONFIG_NLS_CODEPAGE_775 is not set
7989 +# CONFIG_NLS_CODEPAGE_850 is not set
7990 +# CONFIG_NLS_CODEPAGE_852 is not set
7991 +# CONFIG_NLS_CODEPAGE_855 is not set
7992 +# CONFIG_NLS_CODEPAGE_857 is not set
7993 +# CONFIG_NLS_CODEPAGE_860 is not set
7994 +# CONFIG_NLS_CODEPAGE_861 is not set
7995 +# CONFIG_NLS_CODEPAGE_862 is not set
7996 +# CONFIG_NLS_CODEPAGE_863 is not set
7997 +# CONFIG_NLS_CODEPAGE_864 is not set
7998 +# CONFIG_NLS_CODEPAGE_865 is not set
7999 +# CONFIG_NLS_CODEPAGE_866 is not set
8000 +# CONFIG_NLS_CODEPAGE_869 is not set
8001 +# CONFIG_NLS_CODEPAGE_936 is not set
8002 +# CONFIG_NLS_CODEPAGE_950 is not set
8003 +# CONFIG_NLS_CODEPAGE_932 is not set
8004 +# CONFIG_NLS_CODEPAGE_949 is not set
8005 +# CONFIG_NLS_CODEPAGE_874 is not set
8006 +# CONFIG_NLS_ISO8859_8 is not set
8007 +# CONFIG_NLS_CODEPAGE_1250 is not set
8008 +# CONFIG_NLS_CODEPAGE_1251 is not set
8009 +# CONFIG_NLS_ASCII is not set
8010 +CONFIG_NLS_ISO8859_1=y
8011 +# CONFIG_NLS_ISO8859_2 is not set
8012 +# CONFIG_NLS_ISO8859_3 is not set
8013 +# CONFIG_NLS_ISO8859_4 is not set
8014 +# CONFIG_NLS_ISO8859_5 is not set
8015 +# CONFIG_NLS_ISO8859_6 is not set
8016 +# CONFIG_NLS_ISO8859_7 is not set
8017 +# CONFIG_NLS_ISO8859_9 is not set
8018 +# CONFIG_NLS_ISO8859_13 is not set
8019 +# CONFIG_NLS_ISO8859_14 is not set
8020 +# CONFIG_NLS_ISO8859_15 is not set
8021 +# CONFIG_NLS_KOI8_R is not set
8022 +# CONFIG_NLS_KOI8_U is not set
8023 +CONFIG_NLS_UTF8=y
8024 +# CONFIG_DLM is not set
8025 +
8026 +#
8027 +# Kernel hacking
8028 +#
8029 +# CONFIG_PRINTK_TIME is not set
8030 +CONFIG_ENABLE_WARN_DEPRECATED=y
8031 +# CONFIG_ENABLE_MUST_CHECK is not set
8032 +# CONFIG_MAGIC_SYSRQ is not set
8033 +# CONFIG_UNUSED_SYMBOLS is not set
8034 +# CONFIG_DEBUG_FS is not set
8035 +# CONFIG_HEADERS_CHECK is not set
8036 +CONFIG_DEBUG_KERNEL=y
8037 +CONFIG_DETECT_SOFTLOCKUP=y
8038 +CONFIG_SCHED_DEBUG=y
8039 +# CONFIG_SCHEDSTATS is not set
8040 +# CONFIG_TIMER_STATS is not set
8041 +CONFIG_DEBUG_SLAB=y
8042 +# CONFIG_DEBUG_SLAB_LEAK is not set
8043 +# CONFIG_DEBUG_RT_MUTEXES is not set
8044 +# CONFIG_RT_MUTEX_TESTER is not set
8045 +# CONFIG_DEBUG_SPINLOCK is not set
8046 +# CONFIG_DEBUG_MUTEXES is not set
8047 +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
8048 +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
8049 +# CONFIG_DEBUG_KOBJECT is not set
8050 +CONFIG_DEBUG_BUGVERBOSE=y
8051 +CONFIG_DEBUG_INFO=y
8052 +# CONFIG_DEBUG_VM is not set
8053 +# CONFIG_DEBUG_LIST is not set
8054 +# CONFIG_DEBUG_SG is not set
8055 +# CONFIG_FRAME_POINTER is not set
8056 +# CONFIG_BOOT_PRINTK_DELAY is not set
8057 +# CONFIG_RCU_TORTURE_TEST is not set
8058 +# CONFIG_BACKTRACE_SELF_TEST is not set
8059 +# CONFIG_FAULT_INJECTION is not set
8060 +# CONFIG_SAMPLES is not set
8061 +CONFIG_BOOTPARAM=y
8062 +CONFIG_BOOTPARAM_STRING="root=/dev/nfs rw nfsroot=172.27.155.1:/tftpboot/redstripe ip=172.27.155.55:172.27.155.1:172.27.255.254:255.255.0.0::eth0:off mtdparts=phys_mapped_flash:16m(User)"
8063 +
8064 +#
8065 +# Security options
8066 +#
8067 +# CONFIG_KEYS is not set
8068 +# CONFIG_SECURITY is not set
8069 +# CONFIG_SECURITY_FILE_CAPABILITIES is not set
8070 +CONFIG_CRYPTO=y
8071 +CONFIG_CRYPTO_ALGAPI=y
8072 +CONFIG_CRYPTO_AEAD=y
8073 +CONFIG_CRYPTO_BLKCIPHER=y
8074 +# CONFIG_CRYPTO_SEQIV is not set
8075 +CONFIG_CRYPTO_HASH=y
8076 +CONFIG_CRYPTO_MANAGER=y
8077 +CONFIG_CRYPTO_HMAC=y
8078 +# CONFIG_CRYPTO_XCBC is not set
8079 +# CONFIG_CRYPTO_NULL is not set
8080 +# CONFIG_CRYPTO_MD4 is not set
8081 +CONFIG_CRYPTO_MD5=y
8082 +CONFIG_CRYPTO_SHA1=y
8083 +# CONFIG_CRYPTO_SHA256 is not set
8084 +# CONFIG_CRYPTO_SHA512 is not set
8085 +# CONFIG_CRYPTO_WP512 is not set
8086 +# CONFIG_CRYPTO_TGR192 is not set
8087 +# CONFIG_CRYPTO_GF128MUL is not set
8088 +CONFIG_CRYPTO_ECB=y
8089 +CONFIG_CRYPTO_CBC=y
8090 +CONFIG_CRYPTO_PCBC=m
8091 +# CONFIG_CRYPTO_LRW is not set
8092 +# CONFIG_CRYPTO_XTS is not set
8093 +# CONFIG_CRYPTO_CTR is not set
8094 +# CONFIG_CRYPTO_GCM is not set
8095 +# CONFIG_CRYPTO_CCM is not set
8096 +# CONFIG_CRYPTO_CRYPTD is not set
8097 +CONFIG_CRYPTO_DES=y
8098 +# CONFIG_CRYPTO_FCRYPT is not set
8099 +# CONFIG_CRYPTO_BLOWFISH is not set
8100 +# CONFIG_CRYPTO_TWOFISH is not set
8101 +# CONFIG_CRYPTO_SERPENT is not set
8102 +# CONFIG_CRYPTO_AES is not set
8103 +# CONFIG_CRYPTO_CAST5 is not set
8104 +# CONFIG_CRYPTO_CAST6 is not set
8105 +# CONFIG_CRYPTO_TEA is not set
8106 +# CONFIG_CRYPTO_ARC4 is not set
8107 +# CONFIG_CRYPTO_KHAZAD is not set
8108 +# CONFIG_CRYPTO_ANUBIS is not set
8109 +# CONFIG_CRYPTO_SEED is not set
8110 +# CONFIG_CRYPTO_SALSA20 is not set
8111 +# CONFIG_CRYPTO_DEFLATE is not set
8112 +# CONFIG_CRYPTO_MICHAEL_MIC is not set
8113 +# CONFIG_CRYPTO_CRC32C is not set
8114 +# CONFIG_CRYPTO_CAMELLIA is not set
8115 +CONFIG_CRYPTO_TEST=m
8116 +CONFIG_CRYPTO_AUTHENC=y
8117 +# CONFIG_CRYPTO_LZO is not set
8118 +CONFIG_CRYPTO_HW=y
8119 +# CONFIG_CRYPTO_DEV_MCFCAU is not set
8120 +
8121 +#
8122 +# Library routines
8123 +#
8124 +CONFIG_BITREVERSE=y
8125 +CONFIG_CRC_CCITT=y
8126 +CONFIG_CRC16=y
8127 +# CONFIG_CRC_ITU_T is not set
8128 +CONFIG_CRC32=y
8129 +# CONFIG_CRC7 is not set
8130 +CONFIG_LIBCRC32C=y
8131 +CONFIG_PLIST=y
8132 +CONFIG_HAS_IOMEM=y
8133 +CONFIG_HAS_IOPORT=y
8134 +CONFIG_HAS_DMA=y
8135 --- /dev/null
8136 +++ b/arch/m68k/configs/m54455evb_defconfig
8137 @@ -0,0 +1,1037 @@
8138 +#
8139 +# Automatically generated make config: don't edit
8140 +# Linux kernel version: 2.6.23
8141 +# Thu Dec 6 12:14:18 2007
8142 +#
8143 +CONFIG_M68K=y
8144 +CONFIG_MMU=y
8145 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
8146 +# CONFIG_ARCH_HAS_ILOG2_U32 is not set
8147 +# CONFIG_ARCH_HAS_ILOG2_U64 is not set
8148 +CONFIG_GENERIC_HWEIGHT=y
8149 +CONFIG_GENERIC_CALIBRATE_DELAY=y
8150 +CONFIG_TIME_LOW_RES=y
8151 +CONFIG_GENERIC_IOMAP=y
8152 +CONFIG_NO_IOPORT=y
8153 +# CONFIG_NO_DMA is not set
8154 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
8155 +
8156 +#
8157 +# General setup
8158 +#
8159 +CONFIG_EXPERIMENTAL=y
8160 +CONFIG_BROKEN_ON_SMP=y
8161 +CONFIG_INIT_ENV_ARG_LIMIT=32
8162 +CONFIG_LOCALVERSION=""
8163 +CONFIG_LOCALVERSION_AUTO=y
8164 +CONFIG_SWAP=y
8165 +CONFIG_SYSVIPC=y
8166 +CONFIG_SYSVIPC_SYSCTL=y
8167 +# CONFIG_POSIX_MQUEUE is not set
8168 +# CONFIG_BSD_PROCESS_ACCT is not set
8169 +# CONFIG_TASKSTATS is not set
8170 +# CONFIG_USER_NS is not set
8171 +# CONFIG_AUDIT is not set
8172 +CONFIG_IKCONFIG=y
8173 +CONFIG_IKCONFIG_PROC=y
8174 +CONFIG_LOG_BUF_SHIFT=17
8175 +CONFIG_SYSFS_DEPRECATED=y
8176 +# CONFIG_RELAY is not set
8177 +# CONFIG_BLK_DEV_INITRD is not set
8178 +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
8179 +CONFIG_SYSCTL=y
8180 +# CONFIG_EMBEDDED is not set
8181 +CONFIG_UID16=y
8182 +CONFIG_SYSCTL_SYSCALL=y
8183 +CONFIG_KALLSYMS=y
8184 +# CONFIG_KALLSYMS_ALL is not set
8185 +# CONFIG_KALLSYMS_EXTRA_PASS is not set
8186 +CONFIG_HOTPLUG=y
8187 +CONFIG_PRINTK=y
8188 +CONFIG_BUG=y
8189 +CONFIG_ELF_CORE=y
8190 +CONFIG_BASE_FULL=y
8191 +CONFIG_FUTEX=y
8192 +CONFIG_ANON_INODES=y
8193 +CONFIG_EPOLL=y
8194 +CONFIG_SIGNALFD=y
8195 +CONFIG_EVENTFD=y
8196 +CONFIG_SHMEM=y
8197 +CONFIG_VM_EVENT_COUNTERS=y
8198 +CONFIG_SLAB=y
8199 +# CONFIG_SLUB is not set
8200 +# CONFIG_SLOB is not set
8201 +CONFIG_RT_MUTEXES=y
8202 +# CONFIG_TINY_SHMEM is not set
8203 +CONFIG_BASE_SMALL=0
8204 +CONFIG_MODULES=y
8205 +CONFIG_MODULE_UNLOAD=y
8206 +CONFIG_MODULE_FORCE_UNLOAD=y
8207 +# CONFIG_MODVERSIONS is not set
8208 +# CONFIG_MODULE_SRCVERSION_ALL is not set
8209 +# CONFIG_KMOD is not set
8210 +CONFIG_BLOCK=y
8211 +CONFIG_LBD=y
8212 +# CONFIG_BLK_DEV_IO_TRACE is not set
8213 +# CONFIG_LSF is not set
8214 +# CONFIG_BLK_DEV_BSG is not set
8215 +
8216 +#
8217 +# IO Schedulers
8218 +#
8219 +CONFIG_IOSCHED_NOOP=y
8220 +CONFIG_IOSCHED_AS=y
8221 +CONFIG_IOSCHED_DEADLINE=y
8222 +CONFIG_IOSCHED_CFQ=y
8223 +# CONFIG_DEFAULT_AS is not set
8224 +# CONFIG_DEFAULT_DEADLINE is not set
8225 +CONFIG_DEFAULT_CFQ=y
8226 +# CONFIG_DEFAULT_NOOP is not set
8227 +CONFIG_DEFAULT_IOSCHED="cfq"
8228 +
8229 +#
8230 +# Platform dependent setup
8231 +#
8232 +# CONFIG_SUN3 is not set
8233 +CONFIG_COLDFIRE=y
8234 +CONFIG_CFV4E=y
8235 +# CONFIG_AMIGA is not set
8236 +# CONFIG_ATARI is not set
8237 +# CONFIG_MAC is not set
8238 +# CONFIG_APOLLO is not set
8239 +# CONFIG_VME is not set
8240 +# CONFIG_HP300 is not set
8241 +# CONFIG_SUN3X is not set
8242 +# CONFIG_Q40 is not set
8243 +
8244 +#
8245 +# Processor type
8246 +#
8247 +# CONFIG_M68020 is not set
8248 +# CONFIG_M68030 is not set
8249 +# CONFIG_M68040 is not set
8250 +# CONFIG_M68060 is not set
8251 +CONFIG_M54455=y
8252 +CONFIG_MCFCLK=266666666
8253 +# CONFIG_MCF_USER_HALT is not set
8254 +CONFIG_MMU_CFV4E=y
8255 +CONFIG_SDRAM_BASE=0x40000000
8256 +CONFIG_SDRAM_SIZE=0x0FFFFFFF
8257 +CONFIG_NOR_FLASH_BASE=0x00000000
8258 +# CONFIG_M68KFPU_EMU is not set
8259 +CONFIG_ADVANCED=y
8260 +# CONFIG_RMW_INSNS is not set
8261 +CONFIG_SINGLE_MEMORY_CHUNK=y
8262 +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
8263 +CONFIG_SELECT_MEMORY_MODEL=y
8264 +CONFIG_FLATMEM_MANUAL=y
8265 +# CONFIG_DISCONTIGMEM_MANUAL is not set
8266 +# CONFIG_SPARSEMEM_MANUAL is not set
8267 +CONFIG_FLATMEM=y
8268 +CONFIG_FLAT_NODE_MEM_MAP=y
8269 +CONFIG_NEED_MULTIPLE_NODES=y
8270 +# CONFIG_SPARSEMEM_STATIC is not set
8271 +CONFIG_SPLIT_PTLOCK_CPUS=4
8272 +# CONFIG_RESOURCES_64BIT is not set
8273 +CONFIG_ZONE_DMA_FLAG=1
8274 +CONFIG_BOUNCE=y
8275 +CONFIG_VIRT_TO_BUS=y
8276 +
8277 +#
8278 +# General setup
8279 +#
8280 +CONFIG_BINFMT_ELF=y
8281 +# CONFIG_BINFMT_AOUT is not set
8282 +# CONFIG_BINFMT_MISC is not set
8283 +CONFIG_PROC_HARDWARE=y
8284 +CONFIG_ZONE_DMA=y
8285 +# CONFIG_ARCH_SUPPORTS_MSI is not set
8286 +
8287 +#
8288 +# Power management options
8289 +#
8290 +# CONFIG_PM is not set
8291 +
8292 +#
8293 +# Networking
8294 +#
8295 +CONFIG_NET=y
8296 +
8297 +#
8298 +# Networking options
8299 +#
8300 +CONFIG_PACKET=y
8301 +# CONFIG_PACKET_MMAP is not set
8302 +CONFIG_UNIX=y
8303 +CONFIG_XFRM=y
8304 +# CONFIG_XFRM_USER is not set
8305 +# CONFIG_XFRM_SUB_POLICY is not set
8306 +# CONFIG_XFRM_MIGRATE is not set
8307 +CONFIG_NET_KEY=y
8308 +# CONFIG_NET_KEY_MIGRATE is not set
8309 +CONFIG_INET=y
8310 +# CONFIG_IP_MULTICAST is not set
8311 +CONFIG_IP_ADVANCED_ROUTER=y
8312 +CONFIG_ASK_IP_FIB_HASH=y
8313 +# CONFIG_IP_FIB_TRIE is not set
8314 +CONFIG_IP_FIB_HASH=y
8315 +# CONFIG_IP_MULTIPLE_TABLES is not set
8316 +# CONFIG_IP_ROUTE_MULTIPATH is not set
8317 +# CONFIG_IP_ROUTE_VERBOSE is not set
8318 +CONFIG_IP_PNP=y
8319 +# CONFIG_IP_PNP_DHCP is not set
8320 +# CONFIG_IP_PNP_BOOTP is not set
8321 +# CONFIG_IP_PNP_RARP is not set
8322 +# CONFIG_NET_IPIP is not set
8323 +# CONFIG_NET_IPGRE is not set
8324 +# CONFIG_ARPD is not set
8325 +# CONFIG_SYN_COOKIES is not set
8326 +CONFIG_INET_AH=y
8327 +CONFIG_INET_ESP=y
8328 +# CONFIG_INET_IPCOMP is not set
8329 +# CONFIG_INET_XFRM_TUNNEL is not set
8330 +# CONFIG_INET_TUNNEL is not set
8331 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
8332 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
8333 +# CONFIG_INET_XFRM_MODE_BEET is not set
8334 +CONFIG_INET_DIAG=y
8335 +CONFIG_INET_TCP_DIAG=y
8336 +# CONFIG_TCP_CONG_ADVANCED is not set
8337 +CONFIG_TCP_CONG_CUBIC=y
8338 +CONFIG_DEFAULT_TCP_CONG="cubic"
8339 +# CONFIG_TCP_MD5SIG is not set
8340 +# CONFIG_IPV6 is not set
8341 +# CONFIG_INET6_XFRM_TUNNEL is not set
8342 +# CONFIG_INET6_TUNNEL is not set
8343 +# CONFIG_NETWORK_SECMARK is not set
8344 +# CONFIG_NETFILTER is not set
8345 +# CONFIG_IP_DCCP is not set
8346 +# CONFIG_IP_SCTP is not set
8347 +# CONFIG_TIPC is not set
8348 +# CONFIG_ATM is not set
8349 +# CONFIG_BRIDGE is not set
8350 +# CONFIG_VLAN_8021Q is not set
8351 +# CONFIG_DECNET is not set
8352 +# CONFIG_LLC2 is not set
8353 +# CONFIG_IPX is not set
8354 +# CONFIG_ATALK is not set
8355 +# CONFIG_X25 is not set
8356 +# CONFIG_LAPB is not set
8357 +# CONFIG_ECONET is not set
8358 +# CONFIG_WAN_ROUTER is not set
8359 +
8360 +#
8361 +# QoS and/or fair queueing
8362 +#
8363 +# CONFIG_NET_SCHED is not set
8364 +
8365 +#
8366 +# Network testing
8367 +#
8368 +# CONFIG_NET_PKTGEN is not set
8369 +# CONFIG_HAMRADIO is not set
8370 +# CONFIG_IRDA is not set
8371 +# CONFIG_BT is not set
8372 +# CONFIG_AF_RXRPC is not set
8373 +
8374 +#
8375 +# Wireless
8376 +#
8377 +# CONFIG_CFG80211 is not set
8378 +# CONFIG_WIRELESS_EXT is not set
8379 +# CONFIG_MAC80211 is not set
8380 +# CONFIG_IEEE80211 is not set
8381 +# CONFIG_RFKILL is not set
8382 +# CONFIG_NET_9P is not set
8383 +
8384 +#
8385 +# Device Drivers
8386 +#
8387 +
8388 +#
8389 +# Generic Driver Options
8390 +#
8391 +# CONFIG_STANDALONE is not set
8392 +CONFIG_PREVENT_FIRMWARE_BUILD=y
8393 +CONFIG_FW_LOADER=y
8394 +# CONFIG_DEBUG_DRIVER is not set
8395 +# CONFIG_DEBUG_DEVRES is not set
8396 +# CONFIG_SYS_HYPERVISOR is not set
8397 +# CONFIG_CONNECTOR is not set
8398 +CONFIG_MTD=y
8399 +CONFIG_MTD_DEBUG=y
8400 +CONFIG_MTD_DEBUG_VERBOSE=0
8401 +CONFIG_MTD_CONCAT=y
8402 +CONFIG_MTD_PARTITIONS=y
8403 +# CONFIG_MTD_REDBOOT_PARTS is not set
8404 +CONFIG_MTD_CMDLINE_PARTS=y
8405 +
8406 +#
8407 +# User Modules And Translation Layers
8408 +#
8409 +CONFIG_MTD_CHAR=y
8410 +CONFIG_MTD_BLKDEVS=y
8411 +CONFIG_MTD_BLOCK=y
8412 +# CONFIG_FTL is not set
8413 +# CONFIG_NFTL is not set
8414 +# CONFIG_INFTL is not set
8415 +# CONFIG_RFD_FTL is not set
8416 +# CONFIG_SSFDC is not set
8417 +
8418 +#
8419 +# RAM/ROM/Flash chip drivers
8420 +#
8421 +CONFIG_MTD_CFI=y
8422 +# CONFIG_MTD_JEDECPROBE is not set
8423 +CONFIG_MTD_GEN_PROBE=y
8424 +CONFIG_MTD_CFI_ADV_OPTIONS=y
8425 +CONFIG_MTD_CFI_NOSWAP=y
8426 +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
8427 +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
8428 +CONFIG_MTD_CFI_GEOMETRY=y
8429 +CONFIG_MTD_MAP_BANK_WIDTH_1=y
8430 +# CONFIG_MTD_MAP_BANK_WIDTH_2 is not set
8431 +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
8432 +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
8433 +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
8434 +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
8435 +CONFIG_MTD_CFI_I1=y
8436 +# CONFIG_MTD_CFI_I2 is not set
8437 +# CONFIG_MTD_CFI_I4 is not set
8438 +# CONFIG_MTD_CFI_I8 is not set
8439 +# CONFIG_MTD_OTP is not set
8440 +CONFIG_MTD_CFI_INTELEXT=y
8441 +# CONFIG_MTD_CFI_AMDSTD is not set
8442 +# CONFIG_MTD_CFI_STAA is not set
8443 +CONFIG_MTD_CFI_UTIL=y
8444 +# CONFIG_MTD_RAM is not set
8445 +# CONFIG_MTD_ROM is not set
8446 +# CONFIG_MTD_ABSENT is not set
8447 +
8448 +#
8449 +# Mapping drivers for chip access
8450 +#
8451 +# CONFIG_MTD_COMPLEX_MAPPINGS is not set
8452 +CONFIG_MTD_PHYSMAP=y
8453 +CONFIG_MTD_PHYSMAP_START=0x00000000
8454 +CONFIG_MTD_PHYSMAP_LEN=0x1000000
8455 +CONFIG_MTD_PHYSMAP_BANKWIDTH=1
8456 +# CONFIG_MTD_PLATRAM is not set
8457 +
8458 +#
8459 +# Self-contained MTD device drivers
8460 +#
8461 +# CONFIG_MTD_DATAFLASH is not set
8462 +# CONFIG_MTD_M25P80 is not set
8463 +# CONFIG_MTD_SLRAM is not set
8464 +# CONFIG_MTD_PHRAM is not set
8465 +# CONFIG_MTD_MTDRAM is not set
8466 +# CONFIG_MTD_BLOCK2MTD is not set
8467 +
8468 +#
8469 +# Disk-On-Chip Device Drivers
8470 +#
8471 +# CONFIG_MTD_DOC2000 is not set
8472 +# CONFIG_MTD_DOC2001 is not set
8473 +# CONFIG_MTD_DOC2001PLUS is not set
8474 +# CONFIG_MTD_NAND is not set
8475 +# CONFIG_MTD_ONENAND is not set
8476 +
8477 +#
8478 +# UBI - Unsorted block images
8479 +#
8480 +# CONFIG_MTD_UBI is not set
8481 +# CONFIG_PARPORT is not set
8482 +CONFIG_BLK_DEV=y
8483 +# CONFIG_BLK_DEV_COW_COMMON is not set
8484 +CONFIG_BLK_DEV_LOOP=y
8485 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set
8486 +# CONFIG_BLK_DEV_NBD is not set
8487 +# CONFIG_BLK_DEV_UB is not set
8488 +CONFIG_BLK_DEV_RAM=y
8489 +CONFIG_BLK_DEV_RAM_COUNT=16
8490 +CONFIG_BLK_DEV_RAM_SIZE=64000
8491 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
8492 +# CONFIG_CDROM_PKTCDVD is not set
8493 +# CONFIG_ATA_OVER_ETH is not set
8494 +CONFIG_MISC_DEVICES=y
8495 +# CONFIG_EEPROM_93CX6 is not set
8496 +# CONFIG_IDE is not set
8497 +
8498 +#
8499 +# SCSI device support
8500 +#
8501 +# CONFIG_RAID_ATTRS is not set
8502 +CONFIG_SCSI=y
8503 +CONFIG_SCSI_DMA=y
8504 +# CONFIG_SCSI_TGT is not set
8505 +# CONFIG_SCSI_NETLINK is not set
8506 +CONFIG_SCSI_PROC_FS=y
8507 +
8508 +#
8509 +# SCSI support type (disk, tape, CD-ROM)
8510 +#
8511 +CONFIG_BLK_DEV_SD=y
8512 +# CONFIG_CHR_DEV_ST is not set
8513 +# CONFIG_CHR_DEV_OSST is not set
8514 +# CONFIG_BLK_DEV_SR is not set
8515 +# CONFIG_CHR_DEV_SG is not set
8516 +# CONFIG_CHR_DEV_SCH is not set
8517 +
8518 +#
8519 +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
8520 +#
8521 +CONFIG_SCSI_MULTI_LUN=y
8522 +# CONFIG_SCSI_CONSTANTS is not set
8523 +# CONFIG_SCSI_LOGGING is not set
8524 +# CONFIG_SCSI_SCAN_ASYNC is not set
8525 +CONFIG_SCSI_WAIT_SCAN=m
8526 +
8527 +#
8528 +# SCSI Transports
8529 +#
8530 +# CONFIG_SCSI_SPI_ATTRS is not set
8531 +# CONFIG_SCSI_FC_ATTRS is not set
8532 +# CONFIG_SCSI_ISCSI_ATTRS is not set
8533 +# CONFIG_SCSI_SAS_LIBSAS is not set
8534 +CONFIG_SCSI_LOWLEVEL=y
8535 +# CONFIG_ISCSI_TCP is not set
8536 +# CONFIG_SCSI_DEBUG is not set
8537 +CONFIG_ATA=m
8538 +# CONFIG_ATA_NONSTANDARD is not set
8539 +CONFIG_PATA_FSL=m
8540 +# CONFIG_MD is not set
8541 +CONFIG_NETDEVICES=y
8542 +# CONFIG_NETDEVICES_MULTIQUEUE is not set
8543 +# CONFIG_DUMMY is not set
8544 +# CONFIG_BONDING is not set
8545 +# CONFIG_MACVLAN is not set
8546 +# CONFIG_EQUALIZER is not set
8547 +# CONFIG_TUN is not set
8548 +# CONFIG_PHYLIB is not set
8549 +CONFIG_NET_ETHERNET=y
8550 +CONFIG_MII=y
8551 +CONFIG_FEC=y
8552 +# CONFIG_FEC2 is not set
8553 +CONFIG_NETDEV_1000=y
8554 +CONFIG_NETDEV_10000=y
8555 +
8556 +#
8557 +# Wireless LAN
8558 +#
8559 +# CONFIG_WLAN_PRE80211 is not set
8560 +# CONFIG_WLAN_80211 is not set
8561 +
8562 +#
8563 +# USB Network Adapters
8564 +#
8565 +# CONFIG_USB_CATC is not set
8566 +# CONFIG_USB_KAWETH is not set
8567 +CONFIG_USB_PEGASUS=m
8568 +CONFIG_USB_RTL8150=m
8569 +CONFIG_USB_USBNET_MII=m
8570 +CONFIG_USB_USBNET=m
8571 +CONFIG_USB_NET_AX8817X=m
8572 +CONFIG_USB_NET_CDCETHER=m
8573 +# CONFIG_USB_NET_DM9601 is not set
8574 +# CONFIG_USB_NET_GL620A is not set
8575 +# CONFIG_USB_NET_NET1080 is not set
8576 +# CONFIG_USB_NET_PLUSB is not set
8577 +# CONFIG_USB_NET_MCS7830 is not set
8578 +# CONFIG_USB_NET_RNDIS_HOST is not set
8579 +# CONFIG_USB_NET_CDC_SUBSET is not set
8580 +# CONFIG_USB_NET_ZAURUS is not set
8581 +# CONFIG_WAN is not set
8582 +# CONFIG_PPP is not set
8583 +# CONFIG_SLIP is not set
8584 +# CONFIG_SHAPER is not set
8585 +# CONFIG_NETCONSOLE is not set
8586 +# CONFIG_NETPOLL is not set
8587 +# CONFIG_NET_POLL_CONTROLLER is not set
8588 +# CONFIG_ISDN is not set
8589 +# CONFIG_PHONE is not set
8590 +
8591 +#
8592 +# Input device support
8593 +#
8594 +CONFIG_INPUT=y
8595 +# CONFIG_INPUT_FF_MEMLESS is not set
8596 +# CONFIG_INPUT_POLLDEV is not set
8597 +
8598 +#
8599 +# Userland interfaces
8600 +#
8601 +CONFIG_INPUT_MOUSEDEV=y
8602 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
8603 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
8604 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
8605 +# CONFIG_INPUT_JOYDEV is not set
8606 +# CONFIG_INPUT_TSDEV is not set
8607 +CONFIG_INPUT_EVDEV=y
8608 +# CONFIG_INPUT_EVBUG is not set
8609 +
8610 +#
8611 +# Input Device Drivers
8612 +#
8613 +CONFIG_INPUT_KEYBOARD=y
8614 +# CONFIG_KEYBOARD_ATKBD is not set
8615 +# CONFIG_KEYBOARD_SUNKBD is not set
8616 +# CONFIG_KEYBOARD_LKKBD is not set
8617 +# CONFIG_KEYBOARD_XTKBD is not set
8618 +# CONFIG_KEYBOARD_NEWTON is not set
8619 +# CONFIG_KEYBOARD_STOWAWAY is not set
8620 +# CONFIG_INPUT_MOUSE is not set
8621 +# CONFIG_INPUT_JOYSTICK is not set
8622 +# CONFIG_INPUT_TABLET is not set
8623 +# CONFIG_INPUT_TOUCHSCREEN is not set
8624 +# CONFIG_INPUT_MISC is not set
8625 +
8626 +#
8627 +# Hardware I/O ports
8628 +#
8629 +CONFIG_SERIO=y
8630 +CONFIG_SERIO_SERPORT=y
8631 +# CONFIG_SERIO_RAW is not set
8632 +# CONFIG_GAMEPORT is not set
8633 +
8634 +#
8635 +# Character devices
8636 +#
8637 +CONFIG_VT=y
8638 +CONFIG_VT_CONSOLE=y
8639 +CONFIG_HW_CONSOLE=y
8640 +# CONFIG_VT_HW_CONSOLE_BINDING is not set
8641 +# CONFIG_SERIAL_NONSTANDARD is not set
8642 +
8643 +#
8644 +# Serial drivers
8645 +#
8646 +# CONFIG_SERIAL_8250 is not set
8647 +
8648 +#
8649 +# Non-8250 serial port support
8650 +#
8651 +CONFIG_SERIAL_COLDFIRE=y
8652 +CONFIG_UNIX98_PTYS=y
8653 +# CONFIG_LEGACY_PTYS is not set
8654 +# CONFIG_IPMI_HANDLER is not set
8655 +# CONFIG_WATCHDOG is not set
8656 +# CONFIG_HW_RANDOM is not set
8657 +# CONFIG_GEN_RTC is not set
8658 +# CONFIG_R3964 is not set
8659 +# CONFIG_RAW_DRIVER is not set
8660 +# CONFIG_TCG_TPM is not set
8661 +# CONFIG_I2C is not set
8662 +
8663 +#
8664 +# SPI support
8665 +#
8666 +CONFIG_SPI=y
8667 +# CONFIG_SPI_DEBUG is not set
8668 +CONFIG_COLDFIRE_EDMA=y
8669 +CONFIG_SPI_MASTER=y
8670 +
8671 +#
8672 +# SPI Master Controller Drivers
8673 +#
8674 +# CONFIG_SPI_BITBANG is not set
8675 +CONFIG_SPI_COLDFIRE=y
8676 +CONFIG_SPI_COLDFIRE_DSPI_EDMA=y
8677 +
8678 +#
8679 +# SPI Protocol Masters
8680 +#
8681 +# CONFIG_SPI_AT25 is not set
8682 +# CONFIG_SPI_SPIDEV is not set
8683 +# CONFIG_SPI_TLE62X0 is not set
8684 +CONFIG_SPI_COLDFIRE_SSI_AUDIO=y
8685 +# CONFIG_SSIAUDIO_USE_EDMA is not set
8686 +# CONFIG_W1 is not set
8687 +# CONFIG_POWER_SUPPLY is not set
8688 +# CONFIG_HWMON is not set
8689 +
8690 +#
8691 +# Multifunction device drivers
8692 +#
8693 +# CONFIG_MFD_SM501 is not set
8694 +
8695 +#
8696 +# Multimedia devices
8697 +#
8698 +# CONFIG_VIDEO_DEV is not set
8699 +# CONFIG_DVB_CORE is not set
8700 +CONFIG_DAB=y
8701 +# CONFIG_USB_DABUSB is not set
8702 +
8703 +#
8704 +# Graphics support
8705 +#
8706 +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
8707 +
8708 +#
8709 +# Display device support
8710 +#
8711 +# CONFIG_DISPLAY_SUPPORT is not set
8712 +# CONFIG_VGASTATE is not set
8713 +CONFIG_VIDEO_OUTPUT_CONTROL=m
8714 +# CONFIG_FB is not set
8715 +
8716 +#
8717 +# Console display driver support
8718 +#
8719 +CONFIG_DUMMY_CONSOLE=y
8720 +
8721 +#
8722 +# Sound
8723 +#
8724 +# CONFIG_SOUND is not set
8725 +CONFIG_HID_SUPPORT=y
8726 +CONFIG_HID=y
8727 +CONFIG_HID_DEBUG=y
8728 +
8729 +#
8730 +# USB Input Devices
8731 +#
8732 +CONFIG_USB_HID=y
8733 +# CONFIG_USB_HIDINPUT_POWERBOOK is not set
8734 +# CONFIG_HID_FF is not set
8735 +# CONFIG_USB_HIDDEV is not set
8736 +CONFIG_USB_SUPPORT=y
8737 +CONFIG_USB_ARCH_HAS_HCD=y
8738 +# CONFIG_USB_ARCH_HAS_OHCI is not set
8739 +CONFIG_USB_ARCH_HAS_EHCI=y
8740 +CONFIG_USB=y
8741 +# CONFIG_USB_DEBUG is not set
8742 +
8743 +#
8744 +# Miscellaneous USB options
8745 +#
8746 +CONFIG_USB_DEVICEFS=y
8747 +# CONFIG_USB_DEVICE_CLASS is not set
8748 +# CONFIG_USB_DYNAMIC_MINORS is not set
8749 +# CONFIG_USB_OTG is not set
8750 +
8751 +#
8752 +# USB Host Controller Drivers
8753 +#
8754 +CONFIG_USB_EHCI_HCD=m
8755 +CONFIG_USB_EHCI_SPLIT_ISO=y
8756 +CONFIG_USB_EHCI_ROOT_HUB_TT=y
8757 +# CONFIG_USB_EHCI_TT_NEWSCHED is not set
8758 +CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
8759 +CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
8760 +# CONFIG_USB_ISP116X_HCD is not set
8761 +# CONFIG_USB_SL811_HCD is not set
8762 +# CONFIG_USB_R8A66597_HCD is not set
8763 +CONFIG_USB_M5445X_ULPI=y
8764 +# CONFIG_USB_M5445X_FSLS is not set
8765 +
8766 +#
8767 +# USB Device Class drivers
8768 +#
8769 +# CONFIG_USB_ACM is not set
8770 +# CONFIG_USB_PRINTER is not set
8771 +
8772 +#
8773 +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
8774 +#
8775 +
8776 +#
8777 +# may also be needed; see USB_STORAGE Help for more information
8778 +#
8779 +CONFIG_USB_STORAGE=y
8780 +# CONFIG_USB_STORAGE_DEBUG is not set
8781 +# CONFIG_USB_STORAGE_DATAFAB is not set
8782 +# CONFIG_USB_STORAGE_FREECOM is not set
8783 +# CONFIG_USB_STORAGE_DPCM is not set
8784 +# CONFIG_USB_STORAGE_USBAT is not set
8785 +# CONFIG_USB_STORAGE_SDDR09 is not set
8786 +# CONFIG_USB_STORAGE_SDDR55 is not set
8787 +# CONFIG_USB_STORAGE_JUMPSHOT is not set
8788 +# CONFIG_USB_STORAGE_ALAUDA is not set
8789 +# CONFIG_USB_STORAGE_ONETOUCH is not set
8790 +# CONFIG_USB_STORAGE_KARMA is not set
8791 +# CONFIG_USB_LIBUSUAL is not set
8792 +
8793 +#
8794 +# USB Imaging devices
8795 +#
8796 +# CONFIG_USB_MDC800 is not set
8797 +# CONFIG_USB_MICROTEK is not set
8798 +# CONFIG_USB_MON is not set
8799 +
8800 +#
8801 +# USB port drivers
8802 +#
8803 +
8804 +#
8805 +# USB Serial Converter support
8806 +#
8807 +# CONFIG_USB_SERIAL is not set
8808 +
8809 +#
8810 +# USB Miscellaneous drivers
8811 +#
8812 +# CONFIG_USB_EMI62 is not set
8813 +# CONFIG_USB_EMI26 is not set
8814 +# CONFIG_USB_ADUTUX is not set
8815 +# CONFIG_USB_AUERSWALD is not set
8816 +# CONFIG_USB_RIO500 is not set
8817 +# CONFIG_USB_LEGOTOWER is not set
8818 +# CONFIG_USB_LCD is not set
8819 +# CONFIG_USB_BERRY_CHARGE is not set
8820 +# CONFIG_USB_LED is not set
8821 +# CONFIG_USB_CYPRESS_CY7C63 is not set
8822 +# CONFIG_USB_CYTHERM is not set
8823 +# CONFIG_USB_PHIDGET is not set
8824 +# CONFIG_USB_IDMOUSE is not set
8825 +# CONFIG_USB_FTDI_ELAN is not set
8826 +# CONFIG_USB_APPLEDISPLAY is not set
8827 +# CONFIG_USB_SISUSBVGA is not set
8828 +# CONFIG_USB_LD is not set
8829 +# CONFIG_USB_TRANCEVIBRATOR is not set
8830 +# CONFIG_USB_IOWARRIOR is not set
8831 +# CONFIG_USB_TEST is not set
8832 +
8833 +#
8834 +# USB DSL modem support
8835 +#
8836 +
8837 +#
8838 +# USB Gadget Support
8839 +#
8840 +CONFIG_USB_GADGET=m
8841 +# CONFIG_USB_GADGET_DEBUG is not set
8842 +# CONFIG_USB_GADGET_DEBUG_FILES is not set
8843 +CONFIG_USB_GADGET_SELECTED=y
8844 +# CONFIG_USB_GADGET_AMD5536UDC is not set
8845 +# CONFIG_USB_GADGET_FSL_USB2 is not set
8846 +# CONFIG_USB_GADGET_NET2280 is not set
8847 +# CONFIG_USB_GADGET_PXA2XX is not set
8848 +# CONFIG_USB_GADGET_M66592 is not set
8849 +CONFIG_USB_GADGET_MCF5445X=y
8850 +CONFIG_USB_MCF5445X=m
8851 +# CONFIG_USB_GADGET_GOKU is not set
8852 +# CONFIG_USB_GADGET_LH7A40X is not set
8853 +# CONFIG_USB_GADGET_OMAP is not set
8854 +# CONFIG_USB_GADGET_S3C2410 is not set
8855 +# CONFIG_USB_GADGET_AT91 is not set
8856 +# CONFIG_USB_GADGET_DUMMY_HCD is not set
8857 +CONFIG_USB_GADGET_DUALSPEED=y
8858 +# CONFIG_USB_ZERO is not set
8859 +CONFIG_USB_ETH=m
8860 +CONFIG_USB_ETH_RNDIS=y
8861 +CONFIG_USB_GADGETFS=m
8862 +CONFIG_USB_FILE_STORAGE=m
8863 +# CONFIG_USB_FILE_STORAGE_TEST is not set
8864 +# CONFIG_USB_G_SERIAL is not set
8865 +# CONFIG_USB_MIDI_GADGET is not set
8866 +# CONFIG_MMC is not set
8867 +# CONFIG_NEW_LEDS is not set
8868 +# CONFIG_RTC_CLASS is not set
8869 +
8870 +#
8871 +# DMA Engine support
8872 +#
8873 +# CONFIG_DMA_ENGINE is not set
8874 +
8875 +#
8876 +# DMA Clients
8877 +#
8878 +
8879 +#
8880 +# DMA Devices
8881 +#
8882 +
8883 +#
8884 +# Userspace I/O
8885 +#
8886 +# CONFIG_UIO is not set
8887 +
8888 +#
8889 +# Character devices
8890 +#
8891 +# CONFIG_SERIAL_CONSOLE is not set
8892 +
8893 +#
8894 +# File systems
8895 +#
8896 +CONFIG_EXT2_FS=y
8897 +# CONFIG_EXT2_FS_XATTR is not set
8898 +# CONFIG_EXT2_FS_XIP is not set
8899 +CONFIG_EXT3_FS=y
8900 +CONFIG_EXT3_FS_XATTR=y
8901 +# CONFIG_EXT3_FS_POSIX_ACL is not set
8902 +# CONFIG_EXT3_FS_SECURITY is not set
8903 +# CONFIG_EXT4DEV_FS is not set
8904 +CONFIG_JBD=y
8905 +# CONFIG_JBD_DEBUG is not set
8906 +CONFIG_FS_MBCACHE=y
8907 +# CONFIG_REISERFS_FS is not set
8908 +# CONFIG_JFS_FS is not set
8909 +# CONFIG_FS_POSIX_ACL is not set
8910 +# CONFIG_XFS_FS is not set
8911 +# CONFIG_GFS2_FS is not set
8912 +# CONFIG_OCFS2_FS is not set
8913 +CONFIG_MINIX_FS=y
8914 +# CONFIG_ROMFS_FS is not set
8915 +# CONFIG_INOTIFY is not set
8916 +# CONFIG_QUOTA is not set
8917 +CONFIG_DNOTIFY=y
8918 +# CONFIG_AUTOFS_FS is not set
8919 +# CONFIG_AUTOFS4_FS is not set
8920 +# CONFIG_FUSE_FS is not set
8921 +
8922 +#
8923 +# CD-ROM/DVD Filesystems
8924 +#
8925 +# CONFIG_ISO9660_FS is not set
8926 +# CONFIG_UDF_FS is not set
8927 +
8928 +#
8929 +# DOS/FAT/NT Filesystems
8930 +#
8931 +CONFIG_FAT_FS=y
8932 +CONFIG_MSDOS_FS=y
8933 +CONFIG_VFAT_FS=y
8934 +CONFIG_FAT_DEFAULT_CODEPAGE=437
8935 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
8936 +CONFIG_NTFS_FS=y
8937 +# CONFIG_NTFS_DEBUG is not set
8938 +CONFIG_NTFS_RW=y
8939 +
8940 +#
8941 +# Pseudo filesystems
8942 +#
8943 +CONFIG_PROC_FS=y
8944 +# CONFIG_PROC_KCORE is not set
8945 +CONFIG_PROC_SYSCTL=y
8946 +CONFIG_SYSFS=y
8947 +CONFIG_TMPFS=y
8948 +# CONFIG_TMPFS_POSIX_ACL is not set
8949 +# CONFIG_HUGETLB_PAGE is not set
8950 +CONFIG_RAMFS=y
8951 +# CONFIG_CONFIGFS_FS is not set
8952 +
8953 +#
8954 +# Miscellaneous filesystems
8955 +#
8956 +# CONFIG_ADFS_FS is not set
8957 +# CONFIG_AFFS_FS is not set
8958 +# CONFIG_HFS_FS is not set
8959 +# CONFIG_HFSPLUS_FS is not set
8960 +# CONFIG_BEFS_FS is not set
8961 +# CONFIG_BFS_FS is not set
8962 +# CONFIG_EFS_FS is not set
8963 +CONFIG_JFFS2_FS=y
8964 +CONFIG_JFFS2_FS_DEBUG=0
8965 +CONFIG_JFFS2_FS_WRITEBUFFER=y
8966 +# CONFIG_JFFS2_SUMMARY is not set
8967 +# CONFIG_JFFS2_FS_XATTR is not set
8968 +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
8969 +CONFIG_JFFS2_ZLIB=y
8970 +CONFIG_JFFS2_RTIME=y
8971 +# CONFIG_JFFS2_RUBIN is not set
8972 +# CONFIG_CRAMFS is not set
8973 +# CONFIG_VXFS_FS is not set
8974 +# CONFIG_HPFS_FS is not set
8975 +# CONFIG_QNX4FS_FS is not set
8976 +# CONFIG_SYSV_FS is not set
8977 +# CONFIG_UFS_FS is not set
8978 +
8979 +#
8980 +# Network File Systems
8981 +#
8982 +CONFIG_NFS_FS=y
8983 +# CONFIG_NFS_V3 is not set
8984 +# CONFIG_NFS_V4 is not set
8985 +# CONFIG_NFS_DIRECTIO is not set
8986 +# CONFIG_NFSD is not set
8987 +CONFIG_ROOT_NFS=y
8988 +CONFIG_LOCKD=y
8989 +CONFIG_NFS_COMMON=y
8990 +CONFIG_SUNRPC=y
8991 +# CONFIG_SUNRPC_BIND34 is not set
8992 +# CONFIG_RPCSEC_GSS_KRB5 is not set
8993 +# CONFIG_RPCSEC_GSS_SPKM3 is not set
8994 +# CONFIG_SMB_FS is not set
8995 +# CONFIG_CIFS is not set
8996 +# CONFIG_NCP_FS is not set
8997 +# CONFIG_CODA_FS is not set
8998 +# CONFIG_AFS_FS is not set
8999 +
9000 +#
9001 +# Partition Types
9002 +#
9003 +CONFIG_PARTITION_ADVANCED=y
9004 +# CONFIG_ACORN_PARTITION is not set
9005 +# CONFIG_OSF_PARTITION is not set
9006 +# CONFIG_AMIGA_PARTITION is not set
9007 +# CONFIG_ATARI_PARTITION is not set
9008 +# CONFIG_MAC_PARTITION is not set
9009 +CONFIG_MSDOS_PARTITION=y
9010 +# CONFIG_BSD_DISKLABEL is not set
9011 +# CONFIG_MINIX_SUBPARTITION is not set
9012 +# CONFIG_SOLARIS_X86_PARTITION is not set
9013 +# CONFIG_UNIXWARE_DISKLABEL is not set
9014 +# CONFIG_LDM_PARTITION is not set
9015 +# CONFIG_SGI_PARTITION is not set
9016 +# CONFIG_ULTRIX_PARTITION is not set
9017 +# CONFIG_SUN_PARTITION is not set
9018 +# CONFIG_KARMA_PARTITION is not set
9019 +# CONFIG_EFI_PARTITION is not set
9020 +# CONFIG_SYSV68_PARTITION is not set
9021 +
9022 +#
9023 +# Native Language Support
9024 +#
9025 +CONFIG_NLS=y
9026 +CONFIG_NLS_DEFAULT="iso8859-1"
9027 +CONFIG_NLS_CODEPAGE_437=y
9028 +# CONFIG_NLS_CODEPAGE_737 is not set
9029 +# CONFIG_NLS_CODEPAGE_775 is not set
9030 +# CONFIG_NLS_CODEPAGE_850 is not set
9031 +# CONFIG_NLS_CODEPAGE_852 is not set
9032 +# CONFIG_NLS_CODEPAGE_855 is not set
9033 +# CONFIG_NLS_CODEPAGE_857 is not set
9034 +# CONFIG_NLS_CODEPAGE_860 is not set
9035 +# CONFIG_NLS_CODEPAGE_861 is not set
9036 +# CONFIG_NLS_CODEPAGE_862 is not set
9037 +# CONFIG_NLS_CODEPAGE_863 is not set
9038 +# CONFIG_NLS_CODEPAGE_864 is not set
9039 +# CONFIG_NLS_CODEPAGE_865 is not set
9040 +# CONFIG_NLS_CODEPAGE_866 is not set
9041 +# CONFIG_NLS_CODEPAGE_869 is not set
9042 +# CONFIG_NLS_CODEPAGE_936 is not set
9043 +# CONFIG_NLS_CODEPAGE_950 is not set
9044 +# CONFIG_NLS_CODEPAGE_932 is not set
9045 +# CONFIG_NLS_CODEPAGE_949 is not set
9046 +# CONFIG_NLS_CODEPAGE_874 is not set
9047 +# CONFIG_NLS_ISO8859_8 is not set
9048 +# CONFIG_NLS_CODEPAGE_1250 is not set
9049 +# CONFIG_NLS_CODEPAGE_1251 is not set
9050 +# CONFIG_NLS_ASCII is not set
9051 +CONFIG_NLS_ISO8859_1=y
9052 +# CONFIG_NLS_ISO8859_2 is not set
9053 +# CONFIG_NLS_ISO8859_3 is not set
9054 +# CONFIG_NLS_ISO8859_4 is not set
9055 +# CONFIG_NLS_ISO8859_5 is not set
9056 +# CONFIG_NLS_ISO8859_6 is not set
9057 +# CONFIG_NLS_ISO8859_7 is not set
9058 +# CONFIG_NLS_ISO8859_9 is not set
9059 +# CONFIG_NLS_ISO8859_13 is not set
9060 +# CONFIG_NLS_ISO8859_14 is not set
9061 +# CONFIG_NLS_ISO8859_15 is not set
9062 +# CONFIG_NLS_KOI8_R is not set
9063 +# CONFIG_NLS_KOI8_U is not set
9064 +CONFIG_NLS_UTF8=y
9065 +
9066 +#
9067 +# Distributed Lock Manager
9068 +#
9069 +# CONFIG_DLM is not set
9070 +
9071 +#
9072 +# Kernel hacking
9073 +#
9074 +# CONFIG_PRINTK_TIME is not set
9075 +# CONFIG_ENABLE_MUST_CHECK is not set
9076 +# CONFIG_MAGIC_SYSRQ is not set
9077 +# CONFIG_UNUSED_SYMBOLS is not set
9078 +# CONFIG_DEBUG_FS is not set
9079 +# CONFIG_HEADERS_CHECK is not set
9080 +CONFIG_DEBUG_KERNEL=y
9081 +CONFIG_DETECT_SOFTLOCKUP=y
9082 +CONFIG_SCHED_DEBUG=y
9083 +# CONFIG_SCHEDSTATS is not set
9084 +# CONFIG_TIMER_STATS is not set
9085 +CONFIG_DEBUG_SLAB=y
9086 +# CONFIG_DEBUG_SLAB_LEAK is not set
9087 +# CONFIG_DEBUG_RT_MUTEXES is not set
9088 +# CONFIG_RT_MUTEX_TESTER is not set
9089 +# CONFIG_DEBUG_SPINLOCK is not set
9090 +# CONFIG_DEBUG_MUTEXES is not set
9091 +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
9092 +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
9093 +# CONFIG_DEBUG_KOBJECT is not set
9094 +CONFIG_DEBUG_BUGVERBOSE=y
9095 +CONFIG_DEBUG_INFO=y
9096 +# CONFIG_DEBUG_VM is not set
9097 +# CONFIG_DEBUG_LIST is not set
9098 +# CONFIG_FRAME_POINTER is not set
9099 +CONFIG_FORCED_INLINING=y
9100 +# CONFIG_RCU_TORTURE_TEST is not set
9101 +# CONFIG_FAULT_INJECTION is not set
9102 +CONFIG_BOOTPARAM=y
9103 +CONFIG_BOOTPARAM_STRING="root=/dev/nfs rw nfsroot=172.27.155.1:/tftpboot/redstripe ip=172.27.155.55:172.27.155.1:172.27.255.254:255.255.0.0::eth0:off mtdparts=phys_mapped_flash:16m(User)"
9104 +
9105 +#
9106 +# CodeTEST Setup
9107 +#
9108 +# CONFIG_CODETEST is not set
9109 +
9110 +#
9111 +# Security options
9112 +#
9113 +# CONFIG_KEYS is not set
9114 +# CONFIG_SECURITY is not set
9115 +CONFIG_CRYPTO=y
9116 +CONFIG_CRYPTO_ALGAPI=y
9117 +CONFIG_CRYPTO_BLKCIPHER=y
9118 +CONFIG_CRYPTO_HASH=y
9119 +CONFIG_CRYPTO_MANAGER=y
9120 +CONFIG_CRYPTO_HMAC=y
9121 +# CONFIG_CRYPTO_XCBC is not set
9122 +# CONFIG_CRYPTO_NULL is not set
9123 +# CONFIG_CRYPTO_MD4 is not set
9124 +CONFIG_CRYPTO_MD5=y
9125 +CONFIG_CRYPTO_SHA1=y
9126 +# CONFIG_CRYPTO_SHA256 is not set
9127 +# CONFIG_CRYPTO_SHA512 is not set
9128 +# CONFIG_CRYPTO_WP512 is not set
9129 +# CONFIG_CRYPTO_TGR192 is not set
9130 +# CONFIG_CRYPTO_GF128MUL is not set
9131 +CONFIG_CRYPTO_ECB=y
9132 +CONFIG_CRYPTO_CBC=y
9133 +CONFIG_CRYPTO_PCBC=m
9134 +# CONFIG_CRYPTO_LRW is not set
9135 +# CONFIG_CRYPTO_CRYPTD is not set
9136 +CONFIG_CRYPTO_DES=y
9137 +# CONFIG_CRYPTO_FCRYPT is not set
9138 +# CONFIG_CRYPTO_BLOWFISH is not set
9139 +# CONFIG_CRYPTO_TWOFISH is not set
9140 +# CONFIG_CRYPTO_SERPENT is not set
9141 +# CONFIG_CRYPTO_AES is not set
9142 +# CONFIG_CRYPTO_CAST5 is not set
9143 +# CONFIG_CRYPTO_CAST6 is not set
9144 +# CONFIG_CRYPTO_TEA is not set
9145 +# CONFIG_CRYPTO_ARC4 is not set
9146 +# CONFIG_CRYPTO_KHAZAD is not set
9147 +# CONFIG_CRYPTO_ANUBIS is not set
9148 +# CONFIG_CRYPTO_DEFLATE is not set
9149 +# CONFIG_CRYPTO_MICHAEL_MIC is not set
9150 +# CONFIG_CRYPTO_CRC32C is not set
9151 +# CONFIG_CRYPTO_CAMELLIA is not set
9152 +CONFIG_CRYPTO_TEST=m
9153 +CONFIG_CRYPTO_HW=y
9154 +CONFIG_CRYPTO_DEV_MCFCAU=y
9155 +CONFIG_CRYPTO_DEV_MCFCAU_DES=y
9156 +CONFIG_CRYPTO_DEV_MCFCAU_AES=y
9157 +CONFIG_CRYPTO_DEV_MCFCAU_MD5=y
9158 +CONFIG_CRYPTO_DEV_MCFCAU_SHA1=y
9159 +
9160 +#
9161 +# Library routines
9162 +#
9163 +CONFIG_BITREVERSE=y
9164 +CONFIG_CRC_CCITT=y
9165 +CONFIG_CRC16=y
9166 +# CONFIG_CRC_ITU_T is not set
9167 +CONFIG_CRC32=y
9168 +# CONFIG_CRC7 is not set
9169 +CONFIG_LIBCRC32C=y
9170 +CONFIG_ZLIB_INFLATE=y
9171 +CONFIG_ZLIB_DEFLATE=y
9172 +CONFIG_PLIST=y
9173 +CONFIG_HAS_IOMEM=y
9174 +CONFIG_HAS_DMA=y
9175 --- /dev/null
9176 +++ b/arch/m68k/configs/m5475evb_defconfig
9177 @@ -0,0 +1,954 @@
9178 +#
9179 +# Automatically generated make config: don't edit
9180 +# Linux kernel version: 2.6.25
9181 +# Wed Jul 9 16:09:19 2008
9182 +#
9183 +CONFIG_M68K=y
9184 +CONFIG_MMU=y
9185 +# CONFIG_GENERIC_TIME is not set
9186 +# CONFIG_GENERIC_CLOCKEVENTS is not set
9187 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
9188 +# CONFIG_ARCH_HAS_ILOG2_U32 is not set
9189 +# CONFIG_ARCH_HAS_ILOG2_U64 is not set
9190 +CONFIG_GENERIC_HWEIGHT=y
9191 +CONFIG_GENERIC_CALIBRATE_DELAY=y
9192 +CONFIG_TIME_LOW_RES=y
9193 +CONFIG_GENERIC_IOMAP=y
9194 +# CONFIG_NO_IOPORT is not set
9195 +# CONFIG_NO_DMA is not set
9196 +CONFIG_ARCH_SUPPORTS_AOUT=y
9197 +CONFIG_HZ=100
9198 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
9199 +
9200 +#
9201 +# General setup
9202 +#
9203 +CONFIG_EXPERIMENTAL=y
9204 +CONFIG_BROKEN_ON_SMP=y
9205 +CONFIG_INIT_ENV_ARG_LIMIT=32
9206 +CONFIG_LOCALVERSION=""
9207 +CONFIG_LOCALVERSION_AUTO=y
9208 +CONFIG_SWAP=y
9209 +CONFIG_SYSVIPC=y
9210 +CONFIG_SYSVIPC_SYSCTL=y
9211 +# CONFIG_POSIX_MQUEUE is not set
9212 +# CONFIG_BSD_PROCESS_ACCT is not set
9213 +# CONFIG_TASKSTATS is not set
9214 +# CONFIG_AUDIT is not set
9215 +CONFIG_IKCONFIG=y
9216 +CONFIG_IKCONFIG_PROC=y
9217 +CONFIG_LOG_BUF_SHIFT=17
9218 +# CONFIG_CGROUPS is not set
9219 +CONFIG_GROUP_SCHED=y
9220 +CONFIG_FAIR_GROUP_SCHED=y
9221 +# CONFIG_RT_GROUP_SCHED is not set
9222 +CONFIG_USER_SCHED=y
9223 +# CONFIG_CGROUP_SCHED is not set
9224 +CONFIG_SYSFS_DEPRECATED=y
9225 +CONFIG_SYSFS_DEPRECATED_V2=y
9226 +# CONFIG_RELAY is not set
9227 +CONFIG_NAMESPACES=y
9228 +# CONFIG_UTS_NS is not set
9229 +# CONFIG_IPC_NS is not set
9230 +# CONFIG_USER_NS is not set
9231 +# CONFIG_PID_NS is not set
9232 +# CONFIG_BLK_DEV_INITRD is not set
9233 +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
9234 +CONFIG_SYSCTL=y
9235 +# CONFIG_EMBEDDED is not set
9236 +CONFIG_UID16=y
9237 +CONFIG_SYSCTL_SYSCALL=y
9238 +CONFIG_KALLSYMS=y
9239 +# CONFIG_KALLSYMS_ALL is not set
9240 +# CONFIG_KALLSYMS_EXTRA_PASS is not set
9241 +CONFIG_HOTPLUG=y
9242 +CONFIG_PRINTK=y
9243 +CONFIG_BUG=y
9244 +CONFIG_ELF_CORE=y
9245 +CONFIG_COMPAT_BRK=y
9246 +CONFIG_BASE_FULL=y
9247 +CONFIG_FUTEX=y
9248 +CONFIG_ANON_INODES=y
9249 +CONFIG_EPOLL=y
9250 +CONFIG_SIGNALFD=y
9251 +CONFIG_TIMERFD=y
9252 +CONFIG_EVENTFD=y
9253 +CONFIG_SHMEM=y
9254 +CONFIG_VM_EVENT_COUNTERS=y
9255 +CONFIG_SLAB=y
9256 +# CONFIG_SLUB is not set
9257 +# CONFIG_SLOB is not set
9258 +# CONFIG_PROFILING is not set
9259 +# CONFIG_MARKERS is not set
9260 +# CONFIG_HAVE_OPROFILE is not set
9261 +# CONFIG_HAVE_KPROBES is not set
9262 +# CONFIG_HAVE_KRETPROBES is not set
9263 +CONFIG_PROC_PAGE_MONITOR=y
9264 +CONFIG_SLABINFO=y
9265 +CONFIG_RT_MUTEXES=y
9266 +# CONFIG_TINY_SHMEM is not set
9267 +CONFIG_BASE_SMALL=0
9268 +CONFIG_MODULES=y
9269 +CONFIG_MODULE_UNLOAD=y
9270 +CONFIG_MODULE_FORCE_UNLOAD=y
9271 +# CONFIG_MODVERSIONS is not set
9272 +# CONFIG_MODULE_SRCVERSION_ALL is not set
9273 +# CONFIG_KMOD is not set
9274 +CONFIG_BLOCK=y
9275 +CONFIG_LBD=y
9276 +# CONFIG_BLK_DEV_IO_TRACE is not set
9277 +# CONFIG_LSF is not set
9278 +# CONFIG_BLK_DEV_BSG is not set
9279 +
9280 +#
9281 +# IO Schedulers
9282 +#
9283 +CONFIG_IOSCHED_NOOP=y
9284 +CONFIG_IOSCHED_AS=y
9285 +CONFIG_IOSCHED_DEADLINE=y
9286 +CONFIG_IOSCHED_CFQ=y
9287 +# CONFIG_DEFAULT_AS is not set
9288 +# CONFIG_DEFAULT_DEADLINE is not set
9289 +CONFIG_DEFAULT_CFQ=y
9290 +# CONFIG_DEFAULT_NOOP is not set
9291 +CONFIG_DEFAULT_IOSCHED="cfq"
9292 +CONFIG_CLASSIC_RCU=y
9293 +
9294 +#
9295 +# Platform dependent setup
9296 +#
9297 +# CONFIG_SUN3 is not set
9298 +CONFIG_COLDFIRE=y
9299 +CONFIG_CFV4E=y
9300 +CONFIG_MCD_DMA=y
9301 +# CONFIG_AMIGA is not set
9302 +# CONFIG_ATARI is not set
9303 +CONFIG_PCI=y
9304 +# CONFIG_MAC is not set
9305 +# CONFIG_APOLLO is not set
9306 +# CONFIG_VME is not set
9307 +# CONFIG_HP300 is not set
9308 +# CONFIG_SUN3X is not set
9309 +# CONFIG_Q40 is not set
9310 +
9311 +#
9312 +# Processor type
9313 +#
9314 +# CONFIG_M68020 is not set
9315 +# CONFIG_M68030 is not set
9316 +# CONFIG_M68040 is not set
9317 +# CONFIG_M68060 is not set
9318 +# CONFIG_M5445X is not set
9319 +CONFIG_M547X_8X=y
9320 +CONFIG_M547X=y
9321 +# CONFIG_M548X is not set
9322 +# CONFIG_M5475AFE is not set
9323 +# CONFIG_M5475BFE is not set
9324 +CONFIG_M5475CFE=y
9325 +# CONFIG_M5475DFE is not set
9326 +# CONFIG_M5475EFE is not set
9327 +# CONFIG_M5475FFE is not set
9328 +# CONFIG_M5485AFE is not set
9329 +# CONFIG_M5485BFE is not set
9330 +# CONFIG_M5485CFE is not set
9331 +# CONFIG_M5485DFE is not set
9332 +# CONFIG_M5485EFE is not set
9333 +# CONFIG_M5485FFE is not set
9334 +CONFIG_MCFCLK=266000000
9335 +# CONFIG_MCF_USER_HALT is not set
9336 +CONFIG_MMU_CFV4E=y
9337 +CONFIG_SDRAM_BASE=0x00000000
9338 +CONFIG_SDRAM_SIZE=0x04000000
9339 +CONFIG_NOR_FLASH_BASE=0xE0000000
9340 +# CONFIG_M68KFPU_EMU is not set
9341 +CONFIG_ADVANCED=y
9342 +# CONFIG_RMW_INSNS is not set
9343 +CONFIG_SINGLE_MEMORY_CHUNK=y
9344 +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
9345 +CONFIG_SELECT_MEMORY_MODEL=y
9346 +CONFIG_FLATMEM_MANUAL=y
9347 +# CONFIG_DISCONTIGMEM_MANUAL is not set
9348 +# CONFIG_SPARSEMEM_MANUAL is not set
9349 +CONFIG_FLATMEM=y
9350 +CONFIG_FLAT_NODE_MEM_MAP=y
9351 +CONFIG_NEED_MULTIPLE_NODES=y
9352 +# CONFIG_SPARSEMEM_STATIC is not set
9353 +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
9354 +CONFIG_SPLIT_PTLOCK_CPUS=4
9355 +# CONFIG_RESOURCES_64BIT is not set
9356 +CONFIG_ZONE_DMA_FLAG=1
9357 +CONFIG_BOUNCE=y
9358 +CONFIG_VIRT_TO_BUS=y
9359 +
9360 +#
9361 +# General setup
9362 +#
9363 +CONFIG_BINFMT_ELF=y
9364 +# CONFIG_BINFMT_AOUT is not set
9365 +# CONFIG_BINFMT_MISC is not set
9366 +CONFIG_PROC_HARDWARE=y
9367 +CONFIG_ZONE_DMA=y
9368 +# CONFIG_ARCH_SUPPORTS_MSI is not set
9369 +CONFIG_PCI_LEGACY=y
9370 +# CONFIG_PCI_DEBUG is not set
9371 +
9372 +#
9373 +# Power management options
9374 +#
9375 +# CONFIG_PM is not set
9376 +
9377 +#
9378 +# Networking
9379 +#
9380 +CONFIG_NET=y
9381 +
9382 +#
9383 +# Networking options
9384 +#
9385 +CONFIG_PACKET=y
9386 +# CONFIG_PACKET_MMAP is not set
9387 +CONFIG_UNIX=y
9388 +CONFIG_XFRM=y
9389 +# CONFIG_XFRM_USER is not set
9390 +# CONFIG_XFRM_SUB_POLICY is not set
9391 +# CONFIG_XFRM_MIGRATE is not set
9392 +# CONFIG_XFRM_STATISTICS is not set
9393 +CONFIG_NET_KEY=y
9394 +# CONFIG_NET_KEY_MIGRATE is not set
9395 +CONFIG_INET=y
9396 +# CONFIG_IP_MULTICAST is not set
9397 +CONFIG_IP_ADVANCED_ROUTER=y
9398 +CONFIG_ASK_IP_FIB_HASH=y
9399 +# CONFIG_IP_FIB_TRIE is not set
9400 +CONFIG_IP_FIB_HASH=y
9401 +# CONFIG_IP_MULTIPLE_TABLES is not set
9402 +# CONFIG_IP_ROUTE_MULTIPATH is not set
9403 +# CONFIG_IP_ROUTE_VERBOSE is not set
9404 +CONFIG_IP_PNP=y
9405 +# CONFIG_IP_PNP_DHCP is not set
9406 +# CONFIG_IP_PNP_BOOTP is not set
9407 +# CONFIG_IP_PNP_RARP is not set
9408 +# CONFIG_NET_IPIP is not set
9409 +# CONFIG_NET_IPGRE is not set
9410 +# CONFIG_ARPD is not set
9411 +# CONFIG_SYN_COOKIES is not set
9412 +CONFIG_INET_AH=y
9413 +CONFIG_INET_ESP=y
9414 +# CONFIG_INET_IPCOMP is not set
9415 +# CONFIG_INET_XFRM_TUNNEL is not set
9416 +# CONFIG_INET_TUNNEL is not set
9417 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
9418 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
9419 +# CONFIG_INET_XFRM_MODE_BEET is not set
9420 +# CONFIG_INET_LRO is not set
9421 +CONFIG_INET_DIAG=y
9422 +CONFIG_INET_TCP_DIAG=y
9423 +# CONFIG_TCP_CONG_ADVANCED is not set
9424 +CONFIG_TCP_CONG_CUBIC=y
9425 +CONFIG_DEFAULT_TCP_CONG="cubic"
9426 +# CONFIG_TCP_MD5SIG is not set
9427 +# CONFIG_IPV6 is not set
9428 +# CONFIG_INET6_XFRM_TUNNEL is not set
9429 +# CONFIG_INET6_TUNNEL is not set
9430 +# CONFIG_NETWORK_SECMARK is not set
9431 +# CONFIG_NETFILTER is not set
9432 +# CONFIG_IP_DCCP is not set
9433 +# CONFIG_IP_SCTP is not set
9434 +# CONFIG_TIPC is not set
9435 +# CONFIG_ATM is not set
9436 +# CONFIG_BRIDGE is not set
9437 +# CONFIG_VLAN_8021Q is not set
9438 +# CONFIG_DECNET is not set
9439 +# CONFIG_LLC2 is not set
9440 +# CONFIG_IPX is not set
9441 +# CONFIG_ATALK is not set
9442 +# CONFIG_X25 is not set
9443 +# CONFIG_LAPB is not set
9444 +# CONFIG_ECONET is not set
9445 +# CONFIG_WAN_ROUTER is not set
9446 +# CONFIG_NET_SCHED is not set
9447 +
9448 +#
9449 +# Network testing
9450 +#
9451 +# CONFIG_NET_PKTGEN is not set
9452 +# CONFIG_HAMRADIO is not set
9453 +CONFIG_CAN=y
9454 +CONFIG_CAN_RAW=y
9455 +# CONFIG_CAN_BCM is not set
9456 +
9457 +#
9458 +# CAN Device Drivers
9459 +#
9460 +# CONFIG_CAN_VCAN is not set
9461 +CONFIG_CAN_FLEXCAN=y
9462 +CONFIG_CAN_MCF547X_8X=y
9463 +# CONFIG_CAN_DEBUG_DEVICES is not set
9464 +# CONFIG_IRDA is not set
9465 +# CONFIG_BT is not set
9466 +# CONFIG_AF_RXRPC is not set
9467 +
9468 +#
9469 +# Wireless
9470 +#
9471 +# CONFIG_CFG80211 is not set
9472 +# CONFIG_WIRELESS_EXT is not set
9473 +# CONFIG_MAC80211 is not set
9474 +# CONFIG_IEEE80211 is not set
9475 +# CONFIG_RFKILL is not set
9476 +# CONFIG_NET_9P is not set
9477 +
9478 +#
9479 +# Device Drivers
9480 +#
9481 +
9482 +#
9483 +# Generic Driver Options
9484 +#
9485 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
9486 +# CONFIG_STANDALONE is not set
9487 +CONFIG_PREVENT_FIRMWARE_BUILD=y
9488 +CONFIG_FW_LOADER=y
9489 +# CONFIG_DEBUG_DRIVER is not set
9490 +# CONFIG_DEBUG_DEVRES is not set
9491 +# CONFIG_SYS_HYPERVISOR is not set
9492 +# CONFIG_CONNECTOR is not set
9493 +CONFIG_MTD=y
9494 +# CONFIG_MTD_DEBUG is not set
9495 +# CONFIG_MTD_CONCAT is not set
9496 +CONFIG_MTD_PARTITIONS=y
9497 +# CONFIG_MTD_REDBOOT_PARTS is not set
9498 +CONFIG_MTD_CMDLINE_PARTS=y
9499 +
9500 +#
9501 +# User Modules And Translation Layers
9502 +#
9503 +# CONFIG_MTD_CHAR is not set
9504 +CONFIG_MTD_BLKDEVS=y
9505 +CONFIG_MTD_BLOCK=y
9506 +# CONFIG_FTL is not set
9507 +# CONFIG_NFTL is not set
9508 +# CONFIG_INFTL is not set
9509 +# CONFIG_RFD_FTL is not set
9510 +# CONFIG_SSFDC is not set
9511 +# CONFIG_MTD_OOPS is not set
9512 +
9513 +#
9514 +# RAM/ROM/Flash chip drivers
9515 +#
9516 +# CONFIG_MTD_CFI is not set
9517 +# CONFIG_MTD_JEDECPROBE is not set
9518 +CONFIG_MTD_MAP_BANK_WIDTH_1=y
9519 +CONFIG_MTD_MAP_BANK_WIDTH_2=y
9520 +CONFIG_MTD_MAP_BANK_WIDTH_4=y
9521 +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
9522 +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
9523 +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
9524 +CONFIG_MTD_CFI_I1=y
9525 +CONFIG_MTD_CFI_I2=y
9526 +# CONFIG_MTD_CFI_I4 is not set
9527 +# CONFIG_MTD_CFI_I8 is not set
9528 +CONFIG_MTD_RAM=y
9529 +CONFIG_MTD_ROM=y
9530 +# CONFIG_MTD_ABSENT is not set
9531 +
9532 +#
9533 +# Mapping drivers for chip access
9534 +#
9535 +# CONFIG_MTD_COMPLEX_MAPPINGS is not set
9536 +# CONFIG_MTD_PHYSMAP is not set
9537 +# CONFIG_MTD_INTEL_VR_NOR is not set
9538 +# CONFIG_MTD_PLATRAM is not set
9539 +
9540 +#
9541 +# Self-contained MTD device drivers
9542 +#
9543 +# CONFIG_MTD_PMC551 is not set
9544 +# CONFIG_MTD_DATAFLASH is not set
9545 +# CONFIG_MTD_M25P80 is not set
9546 +# CONFIG_MTD_SLRAM is not set
9547 +# CONFIG_MTD_PHRAM is not set
9548 +# CONFIG_MTD_MTDRAM is not set
9549 +# CONFIG_MTD_BLOCK2MTD is not set
9550 +
9551 +#
9552 +# Disk-On-Chip Device Drivers
9553 +#
9554 +# CONFIG_MTD_DOC2000 is not set
9555 +# CONFIG_MTD_DOC2001 is not set
9556 +# CONFIG_MTD_DOC2001PLUS is not set
9557 +# CONFIG_MTD_NAND is not set
9558 +# CONFIG_MTD_ONENAND is not set
9559 +
9560 +#
9561 +# UBI - Unsorted block images
9562 +#
9563 +# CONFIG_MTD_UBI is not set
9564 +# CONFIG_PARPORT is not set
9565 +CONFIG_BLK_DEV=y
9566 +# CONFIG_BLK_CPQ_DA is not set
9567 +# CONFIG_BLK_CPQ_CISS_DA is not set
9568 +# CONFIG_BLK_DEV_DAC960 is not set
9569 +# CONFIG_BLK_DEV_UMEM is not set
9570 +# CONFIG_BLK_DEV_COW_COMMON is not set
9571 +CONFIG_BLK_DEV_LOOP=y
9572 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set
9573 +# CONFIG_BLK_DEV_NBD is not set
9574 +# CONFIG_BLK_DEV_SX8 is not set
9575 +CONFIG_BLK_DEV_RAM=y
9576 +CONFIG_BLK_DEV_RAM_COUNT=16
9577 +CONFIG_BLK_DEV_RAM_SIZE=64000
9578 +# CONFIG_BLK_DEV_XIP is not set
9579 +# CONFIG_CDROM_PKTCDVD is not set
9580 +# CONFIG_ATA_OVER_ETH is not set
9581 +CONFIG_MISC_DEVICES=y
9582 +CONFIG_COLDFIRE_SEC=y
9583 +CONFIG_SEC_DEVICE=y
9584 +# CONFIG_PHANTOM is not set
9585 +# CONFIG_EEPROM_93CX6 is not set
9586 +# CONFIG_SGI_IOC4 is not set
9587 +# CONFIG_TIFM_CORE is not set
9588 +# CONFIG_ENCLOSURE_SERVICES is not set
9589 +CONFIG_HAVE_IDE=y
9590 +# CONFIG_IDE is not set
9591 +
9592 +#
9593 +# SCSI device support
9594 +#
9595 +# CONFIG_RAID_ATTRS is not set
9596 +CONFIG_SCSI=y
9597 +CONFIG_SCSI_DMA=y
9598 +# CONFIG_SCSI_TGT is not set
9599 +# CONFIG_SCSI_NETLINK is not set
9600 +CONFIG_SCSI_PROC_FS=y
9601 +
9602 +#
9603 +# SCSI support type (disk, tape, CD-ROM)
9604 +#
9605 +CONFIG_BLK_DEV_SD=y
9606 +# CONFIG_CHR_DEV_ST is not set
9607 +# CONFIG_CHR_DEV_OSST is not set
9608 +# CONFIG_BLK_DEV_SR is not set
9609 +# CONFIG_CHR_DEV_SG is not set
9610 +# CONFIG_CHR_DEV_SCH is not set
9611 +
9612 +#
9613 +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
9614 +#
9615 +CONFIG_SCSI_MULTI_LUN=y
9616 +# CONFIG_SCSI_CONSTANTS is not set
9617 +# CONFIG_SCSI_LOGGING is not set
9618 +# CONFIG_SCSI_SCAN_ASYNC is not set
9619 +CONFIG_SCSI_WAIT_SCAN=m
9620 +
9621 +#
9622 +# SCSI Transports
9623 +#
9624 +# CONFIG_SCSI_SPI_ATTRS is not set
9625 +# CONFIG_SCSI_FC_ATTRS is not set
9626 +# CONFIG_SCSI_ISCSI_ATTRS is not set
9627 +# CONFIG_SCSI_SAS_LIBSAS is not set
9628 +# CONFIG_SCSI_SRP_ATTRS is not set
9629 +# CONFIG_SCSI_LOWLEVEL is not set
9630 +# CONFIG_ATA is not set
9631 +# CONFIG_MD is not set
9632 +# CONFIG_FUSION is not set
9633 +
9634 +#
9635 +# IEEE 1394 (FireWire) support
9636 +#
9637 +# CONFIG_FIREWIRE is not set
9638 +# CONFIG_IEEE1394 is not set
9639 +# CONFIG_I2O is not set
9640 +CONFIG_NETDEVICES=y
9641 +# CONFIG_NETDEVICES_MULTIQUEUE is not set
9642 +# CONFIG_DUMMY is not set
9643 +# CONFIG_BONDING is not set
9644 +# CONFIG_MACVLAN is not set
9645 +# CONFIG_EQUALIZER is not set
9646 +# CONFIG_TUN is not set
9647 +# CONFIG_VETH is not set
9648 +# CONFIG_ARCNET is not set
9649 +# CONFIG_PHYLIB is not set
9650 +CONFIG_NET_ETHERNET=y
9651 +CONFIG_MII=y
9652 +CONFIG_FEC_548x=y
9653 +CONFIG_FEC_548x_AUTO_NEGOTIATION=y
9654 +# CONFIG_FEC_548x_ENABLE_FEC2 is not set
9655 +# CONFIG_HAPPYMEAL is not set
9656 +# CONFIG_SUNGEM is not set
9657 +# CONFIG_CASSINI is not set
9658 +# CONFIG_NET_VENDOR_3COM is not set
9659 +# CONFIG_ENC28J60 is not set
9660 +# CONFIG_NET_TULIP is not set
9661 +# CONFIG_HP100 is not set
9662 +# CONFIG_IBM_NEW_EMAC_ZMII is not set
9663 +# CONFIG_IBM_NEW_EMAC_RGMII is not set
9664 +# CONFIG_IBM_NEW_EMAC_TAH is not set
9665 +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
9666 +# CONFIG_NET_PCI is not set
9667 +# CONFIG_B44 is not set
9668 +# CONFIG_NETDEV_1000 is not set
9669 +# CONFIG_NETDEV_10000 is not set
9670 +# CONFIG_TR is not set
9671 +
9672 +#
9673 +# Wireless LAN
9674 +#
9675 +# CONFIG_WLAN_PRE80211 is not set
9676 +# CONFIG_WLAN_80211 is not set
9677 +# CONFIG_WAN is not set
9678 +# CONFIG_FDDI is not set
9679 +# CONFIG_HIPPI is not set
9680 +# CONFIG_PPP is not set
9681 +# CONFIG_SLIP is not set
9682 +# CONFIG_NET_FC is not set
9683 +# CONFIG_NETCONSOLE is not set
9684 +# CONFIG_NETPOLL is not set
9685 +# CONFIG_NET_POLL_CONTROLLER is not set
9686 +# CONFIG_ISDN is not set
9687 +# CONFIG_PHONE is not set
9688 +
9689 +#
9690 +# Input device support
9691 +#
9692 +CONFIG_INPUT=y
9693 +# CONFIG_INPUT_FF_MEMLESS is not set
9694 +# CONFIG_INPUT_POLLDEV is not set
9695 +
9696 +#
9697 +# Userland interfaces
9698 +#
9699 +CONFIG_INPUT_MOUSEDEV=y
9700 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
9701 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
9702 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
9703 +# CONFIG_INPUT_JOYDEV is not set
9704 +CONFIG_INPUT_EVDEV=y
9705 +# CONFIG_INPUT_EVBUG is not set
9706 +
9707 +#
9708 +# Input Device Drivers
9709 +#
9710 +CONFIG_INPUT_KEYBOARD=y
9711 +# CONFIG_KEYBOARD_ATKBD is not set
9712 +# CONFIG_KEYBOARD_SUNKBD is not set
9713 +# CONFIG_KEYBOARD_LKKBD is not set
9714 +# CONFIG_KEYBOARD_XTKBD is not set
9715 +# CONFIG_KEYBOARD_NEWTON is not set
9716 +# CONFIG_KEYBOARD_STOWAWAY is not set
9717 +# CONFIG_INPUT_MOUSE is not set
9718 +# CONFIG_INPUT_JOYSTICK is not set
9719 +# CONFIG_INPUT_TABLET is not set
9720 +# CONFIG_INPUT_TOUCHSCREEN is not set
9721 +# CONFIG_INPUT_MISC is not set
9722 +
9723 +#
9724 +# Hardware I/O ports
9725 +#
9726 +CONFIG_SERIO=y
9727 +CONFIG_SERIO_SERPORT=y
9728 +# CONFIG_SERIO_PCIPS2 is not set
9729 +# CONFIG_SERIO_RAW is not set
9730 +# CONFIG_GAMEPORT is not set
9731 +
9732 +#
9733 +# Character devices
9734 +#
9735 +CONFIG_VT=y
9736 +CONFIG_VT_CONSOLE=y
9737 +CONFIG_HW_CONSOLE=y
9738 +# CONFIG_VT_HW_CONSOLE_BINDING is not set
9739 +# CONFIG_SERIAL_NONSTANDARD is not set
9740 +# CONFIG_NOZOMI is not set
9741 +
9742 +#
9743 +# Serial drivers
9744 +#
9745 +# CONFIG_SERIAL_8250 is not set
9746 +
9747 +#
9748 +# Non-8250 serial port support
9749 +#
9750 +CONFIG_SERIAL_COLDFIRE=y
9751 +CONFIG_SERIAL_COLDFIRE_IRDA=y
9752 +# CONFIG_SERIAL_MCF is not set
9753 +# CONFIG_SERIAL_JSM is not set
9754 +CONFIG_UNIX98_PTYS=y
9755 +# CONFIG_LEGACY_PTYS is not set
9756 +# CONFIG_IPMI_HANDLER is not set
9757 +# CONFIG_HW_RANDOM is not set
9758 +# CONFIG_GEN_RTC is not set
9759 +# CONFIG_R3964 is not set
9760 +# CONFIG_APPLICOM is not set
9761 +# CONFIG_RAW_DRIVER is not set
9762 +# CONFIG_TCG_TPM is not set
9763 +# CONFIG_I2C is not set
9764 +
9765 +#
9766 +# SPI support
9767 +#
9768 +CONFIG_SPI=y
9769 +CONFIG_SPI_DEBUG=y
9770 +# CONFIG_COLDFIRE_EDMA is not set
9771 +CONFIG_SPI_MASTER=y
9772 +
9773 +#
9774 +# SPI Master Controller Drivers
9775 +#
9776 +# CONFIG_SPI_BITBANG is not set
9777 +CONFIG_SPI_COLDFIRE=y
9778 +
9779 +#
9780 +# SPI Protocol Masters
9781 +#
9782 +# CONFIG_SPI_AT25 is not set
9783 +# CONFIG_SPI_SPIDEV is not set
9784 +# CONFIG_SPI_TLE62X0 is not set
9785 +# CONFIG_SPI_COLDFIRE_SSI_AUDIO is not set
9786 +# CONFIG_W1 is not set
9787 +# CONFIG_POWER_SUPPLY is not set
9788 +# CONFIG_HWMON is not set
9789 +# CONFIG_THERMAL is not set
9790 +CONFIG_WATCHDOG=y
9791 +# CONFIG_WATCHDOG_NOWAYOUT is not set
9792 +
9793 +#
9794 +# Watchdog Device Drivers
9795 +#
9796 +# CONFIG_SOFT_WATCHDOG is not set
9797 +CONFIG_COLDFIRE_WATCHDOG=m
9798 +
9799 +#
9800 +# PCI-based Watchdog Cards
9801 +#
9802 +# CONFIG_PCIPCWATCHDOG is not set
9803 +# CONFIG_WDTPCI is not set
9804 +
9805 +#
9806 +# Sonics Silicon Backplane
9807 +#
9808 +CONFIG_SSB_POSSIBLE=y
9809 +# CONFIG_SSB is not set
9810 +
9811 +#
9812 +# Multifunction device drivers
9813 +#
9814 +# CONFIG_MFD_SM501 is not set
9815 +
9816 +#
9817 +# Multimedia devices
9818 +#
9819 +# CONFIG_VIDEO_DEV is not set
9820 +# CONFIG_DVB_CORE is not set
9821 +CONFIG_DAB=y
9822 +
9823 +#
9824 +# Graphics support
9825 +#
9826 +# CONFIG_DRM is not set
9827 +# CONFIG_VGASTATE is not set
9828 +CONFIG_VIDEO_OUTPUT_CONTROL=m
9829 +# CONFIG_FB is not set
9830 +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
9831 +
9832 +#
9833 +# Display device support
9834 +#
9835 +# CONFIG_DISPLAY_SUPPORT is not set
9836 +
9837 +#
9838 +# Console display driver support
9839 +#
9840 +CONFIG_DUMMY_CONSOLE=y
9841 +
9842 +#
9843 +# Sound
9844 +#
9845 +# CONFIG_SOUND is not set
9846 +CONFIG_HID_SUPPORT=y
9847 +CONFIG_HID=y
9848 +CONFIG_HID_DEBUG=y
9849 +# CONFIG_HIDRAW is not set
9850 +# CONFIG_USB_SUPPORT is not set
9851 +# CONFIG_MMC is not set
9852 +# CONFIG_MEMSTICK is not set
9853 +# CONFIG_NEW_LEDS is not set
9854 +# CONFIG_INFINIBAND is not set
9855 +# CONFIG_RTC_CLASS is not set
9856 +
9857 +#
9858 +# Userspace I/O
9859 +#
9860 +# CONFIG_UIO is not set
9861 +
9862 +#
9863 +# Character devices
9864 +#
9865 +# CONFIG_SERIAL_CONSOLE is not set
9866 +
9867 +#
9868 +# File systems
9869 +#
9870 +CONFIG_EXT2_FS=y
9871 +# CONFIG_EXT2_FS_XATTR is not set
9872 +# CONFIG_EXT2_FS_XIP is not set
9873 +CONFIG_EXT3_FS=y
9874 +CONFIG_EXT3_FS_XATTR=y
9875 +# CONFIG_EXT3_FS_POSIX_ACL is not set
9876 +# CONFIG_EXT3_FS_SECURITY is not set
9877 +# CONFIG_EXT4DEV_FS is not set
9878 +CONFIG_JBD=y
9879 +CONFIG_FS_MBCACHE=y
9880 +# CONFIG_REISERFS_FS is not set
9881 +# CONFIG_JFS_FS is not set
9882 +# CONFIG_FS_POSIX_ACL is not set
9883 +# CONFIG_XFS_FS is not set
9884 +# CONFIG_GFS2_FS is not set
9885 +# CONFIG_OCFS2_FS is not set
9886 +CONFIG_DNOTIFY=y
9887 +# CONFIG_INOTIFY is not set
9888 +# CONFIG_QUOTA is not set
9889 +# CONFIG_AUTOFS_FS is not set
9890 +# CONFIG_AUTOFS4_FS is not set
9891 +# CONFIG_FUSE_FS is not set
9892 +
9893 +#
9894 +# CD-ROM/DVD Filesystems
9895 +#
9896 +# CONFIG_ISO9660_FS is not set
9897 +# CONFIG_UDF_FS is not set
9898 +
9899 +#
9900 +# DOS/FAT/NT Filesystems
9901 +#
9902 +CONFIG_FAT_FS=y
9903 +CONFIG_MSDOS_FS=y
9904 +CONFIG_VFAT_FS=y
9905 +CONFIG_FAT_DEFAULT_CODEPAGE=437
9906 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
9907 +CONFIG_NTFS_FS=y
9908 +# CONFIG_NTFS_DEBUG is not set
9909 +CONFIG_NTFS_RW=y
9910 +
9911 +#
9912 +# Pseudo filesystems
9913 +#
9914 +CONFIG_PROC_FS=y
9915 +# CONFIG_PROC_KCORE is not set
9916 +CONFIG_PROC_SYSCTL=y
9917 +CONFIG_SYSFS=y
9918 +CONFIG_TMPFS=y
9919 +# CONFIG_TMPFS_POSIX_ACL is not set
9920 +# CONFIG_HUGETLB_PAGE is not set
9921 +# CONFIG_CONFIGFS_FS is not set
9922 +
9923 +#
9924 +# Miscellaneous filesystems
9925 +#
9926 +# CONFIG_ADFS_FS is not set
9927 +# CONFIG_AFFS_FS is not set
9928 +# CONFIG_HFS_FS is not set
9929 +# CONFIG_HFSPLUS_FS is not set
9930 +# CONFIG_BEFS_FS is not set
9931 +# CONFIG_BFS_FS is not set
9932 +# CONFIG_EFS_FS is not set
9933 +# CONFIG_JFFS2_FS is not set
9934 +# CONFIG_CRAMFS is not set
9935 +# CONFIG_VXFS_FS is not set
9936 +CONFIG_MINIX_FS=y
9937 +# CONFIG_HPFS_FS is not set
9938 +# CONFIG_QNX4FS_FS is not set
9939 +CONFIG_ROMFS_FS=y
9940 +# CONFIG_SYSV_FS is not set
9941 +# CONFIG_UFS_FS is not set
9942 +CONFIG_NETWORK_FILESYSTEMS=y
9943 +CONFIG_NFS_FS=y
9944 +# CONFIG_NFS_V3 is not set
9945 +# CONFIG_NFS_V4 is not set
9946 +# CONFIG_NFS_DIRECTIO is not set
9947 +# CONFIG_NFSD is not set
9948 +CONFIG_ROOT_NFS=y
9949 +CONFIG_LOCKD=y
9950 +CONFIG_NFS_COMMON=y
9951 +CONFIG_SUNRPC=y
9952 +# CONFIG_SUNRPC_BIND34 is not set
9953 +# CONFIG_RPCSEC_GSS_KRB5 is not set
9954 +# CONFIG_RPCSEC_GSS_SPKM3 is not set
9955 +# CONFIG_SMB_FS is not set
9956 +# CONFIG_CIFS is not set
9957 +# CONFIG_NCP_FS is not set
9958 +# CONFIG_CODA_FS is not set
9959 +# CONFIG_AFS_FS is not set
9960 +
9961 +#
9962 +# Partition Types
9963 +#
9964 +CONFIG_PARTITION_ADVANCED=y
9965 +# CONFIG_ACORN_PARTITION is not set
9966 +# CONFIG_OSF_PARTITION is not set
9967 +# CONFIG_AMIGA_PARTITION is not set
9968 +# CONFIG_ATARI_PARTITION is not set
9969 +# CONFIG_MAC_PARTITION is not set
9970 +CONFIG_MSDOS_PARTITION=y
9971 +# CONFIG_BSD_DISKLABEL is not set
9972 +# CONFIG_MINIX_SUBPARTITION is not set
9973 +# CONFIG_SOLARIS_X86_PARTITION is not set
9974 +# CONFIG_UNIXWARE_DISKLABEL is not set
9975 +# CONFIG_LDM_PARTITION is not set
9976 +# CONFIG_SGI_PARTITION is not set
9977 +# CONFIG_ULTRIX_PARTITION is not set
9978 +# CONFIG_SUN_PARTITION is not set
9979 +# CONFIG_KARMA_PARTITION is not set
9980 +# CONFIG_EFI_PARTITION is not set
9981 +# CONFIG_SYSV68_PARTITION is not set
9982 +CONFIG_NLS=y
9983 +CONFIG_NLS_DEFAULT="iso8859-1"
9984 +CONFIG_NLS_CODEPAGE_437=y
9985 +# CONFIG_NLS_CODEPAGE_737 is not set
9986 +# CONFIG_NLS_CODEPAGE_775 is not set
9987 +# CONFIG_NLS_CODEPAGE_850 is not set
9988 +# CONFIG_NLS_CODEPAGE_852 is not set
9989 +# CONFIG_NLS_CODEPAGE_855 is not set
9990 +# CONFIG_NLS_CODEPAGE_857 is not set
9991 +# CONFIG_NLS_CODEPAGE_860 is not set
9992 +# CONFIG_NLS_CODEPAGE_861 is not set
9993 +# CONFIG_NLS_CODEPAGE_862 is not set
9994 +# CONFIG_NLS_CODEPAGE_863 is not set
9995 +# CONFIG_NLS_CODEPAGE_864 is not set
9996 +# CONFIG_NLS_CODEPAGE_865 is not set
9997 +# CONFIG_NLS_CODEPAGE_866 is not set
9998 +# CONFIG_NLS_CODEPAGE_869 is not set
9999 +# CONFIG_NLS_CODEPAGE_936 is not set
10000 +# CONFIG_NLS_CODEPAGE_950 is not set
10001 +# CONFIG_NLS_CODEPAGE_932 is not set
10002 +# CONFIG_NLS_CODEPAGE_949 is not set
10003 +# CONFIG_NLS_CODEPAGE_874 is not set
10004 +# CONFIG_NLS_ISO8859_8 is not set
10005 +# CONFIG_NLS_CODEPAGE_1250 is not set
10006 +# CONFIG_NLS_CODEPAGE_1251 is not set
10007 +# CONFIG_NLS_ASCII is not set
10008 +CONFIG_NLS_ISO8859_1=y
10009 +# CONFIG_NLS_ISO8859_2 is not set
10010 +# CONFIG_NLS_ISO8859_3 is not set
10011 +# CONFIG_NLS_ISO8859_4 is not set
10012 +# CONFIG_NLS_ISO8859_5 is not set
10013 +# CONFIG_NLS_ISO8859_6 is not set
10014 +# CONFIG_NLS_ISO8859_7 is not set
10015 +# CONFIG_NLS_ISO8859_9 is not set
10016 +# CONFIG_NLS_ISO8859_13 is not set
10017 +# CONFIG_NLS_ISO8859_14 is not set
10018 +# CONFIG_NLS_ISO8859_15 is not set
10019 +# CONFIG_NLS_KOI8_R is not set
10020 +# CONFIG_NLS_KOI8_U is not set
10021 +CONFIG_NLS_UTF8=y
10022 +# CONFIG_DLM is not set
10023 +
10024 +#
10025 +# Kernel hacking
10026 +#
10027 +# CONFIG_PRINTK_TIME is not set
10028 +CONFIG_ENABLE_WARN_DEPRECATED=y
10029 +# CONFIG_ENABLE_MUST_CHECK is not set
10030 +# CONFIG_MAGIC_SYSRQ is not set
10031 +# CONFIG_UNUSED_SYMBOLS is not set
10032 +# CONFIG_DEBUG_FS is not set
10033 +# CONFIG_HEADERS_CHECK is not set
10034 +CONFIG_DEBUG_KERNEL=y
10035 +CONFIG_DETECT_SOFTLOCKUP=y
10036 +CONFIG_SCHED_DEBUG=y
10037 +# CONFIG_SCHEDSTATS is not set
10038 +# CONFIG_TIMER_STATS is not set
10039 +CONFIG_DEBUG_SLAB=y
10040 +# CONFIG_DEBUG_SLAB_LEAK is not set
10041 +# CONFIG_DEBUG_RT_MUTEXES is not set
10042 +# CONFIG_RT_MUTEX_TESTER is not set
10043 +# CONFIG_DEBUG_SPINLOCK is not set
10044 +# CONFIG_DEBUG_MUTEXES is not set
10045 +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
10046 +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
10047 +# CONFIG_DEBUG_KOBJECT is not set
10048 +CONFIG_DEBUG_BUGVERBOSE=y
10049 +CONFIG_DEBUG_INFO=y
10050 +# CONFIG_DEBUG_VM is not set
10051 +# CONFIG_DEBUG_LIST is not set
10052 +# CONFIG_DEBUG_SG is not set
10053 +# CONFIG_FRAME_POINTER is not set
10054 +# CONFIG_BOOT_PRINTK_DELAY is not set
10055 +# CONFIG_RCU_TORTURE_TEST is not set
10056 +# CONFIG_BACKTRACE_SELF_TEST is not set
10057 +# CONFIG_FAULT_INJECTION is not set
10058 +# CONFIG_SAMPLES is not set
10059 +CONFIG_BOOTPARAM=y
10060 +CONFIG_BOOTPARAM_STRING="root=/dev/nfs rw nfsroot=172.27.163.2:/tftpboot/ltib ip=172.27.163.3:172.27.163.2:172.27.255.254:255.255.0.0::eth0:off mtdparts=phys_mapped_flash:16m(User)"
10061 +
10062 +#
10063 +# Security options
10064 +#
10065 +# CONFIG_KEYS is not set
10066 +# CONFIG_SECURITY is not set
10067 +# CONFIG_SECURITY_FILE_CAPABILITIES is not set
10068 +CONFIG_CRYPTO=y
10069 +CONFIG_CRYPTO_ALGAPI=y
10070 +CONFIG_CRYPTO_AEAD=y
10071 +CONFIG_CRYPTO_BLKCIPHER=y
10072 +# CONFIG_CRYPTO_SEQIV is not set
10073 +CONFIG_CRYPTO_HASH=y
10074 +CONFIG_CRYPTO_MANAGER=y
10075 +CONFIG_CRYPTO_HMAC=y
10076 +# CONFIG_CRYPTO_XCBC is not set
10077 +# CONFIG_CRYPTO_NULL is not set
10078 +# CONFIG_CRYPTO_MD4 is not set
10079 +CONFIG_CRYPTO_MD5=y
10080 +CONFIG_CRYPTO_SHA1=y
10081 +# CONFIG_CRYPTO_SHA256 is not set
10082 +# CONFIG_CRYPTO_SHA512 is not set
10083 +# CONFIG_CRYPTO_WP512 is not set
10084 +# CONFIG_CRYPTO_TGR192 is not set
10085 +# CONFIG_CRYPTO_GF128MUL is not set
10086 +# CONFIG_CRYPTO_ECB is not set
10087 +CONFIG_CRYPTO_CBC=y
10088 +# CONFIG_CRYPTO_PCBC is not set
10089 +# CONFIG_CRYPTO_LRW is not set
10090 +# CONFIG_CRYPTO_XTS is not set
10091 +# CONFIG_CRYPTO_CTR is not set
10092 +# CONFIG_CRYPTO_GCM is not set
10093 +# CONFIG_CRYPTO_CCM is not set
10094 +# CONFIG_CRYPTO_CRYPTD is not set
10095 +CONFIG_CRYPTO_DES=y
10096 +# CONFIG_CRYPTO_FCRYPT is not set
10097 +# CONFIG_CRYPTO_BLOWFISH is not set
10098 +# CONFIG_CRYPTO_TWOFISH is not set
10099 +# CONFIG_CRYPTO_SERPENT is not set
10100 +# CONFIG_CRYPTO_AES is not set
10101 +# CONFIG_CRYPTO_CAST5 is not set
10102 +# CONFIG_CRYPTO_CAST6 is not set
10103 +# CONFIG_CRYPTO_TEA is not set
10104 +# CONFIG_CRYPTO_ARC4 is not set
10105 +# CONFIG_CRYPTO_KHAZAD is not set
10106 +# CONFIG_CRYPTO_ANUBIS is not set
10107 +# CONFIG_CRYPTO_SEED is not set
10108 +# CONFIG_CRYPTO_SALSA20 is not set
10109 +# CONFIG_CRYPTO_DEFLATE is not set
10110 +# CONFIG_CRYPTO_MICHAEL_MIC is not set
10111 +# CONFIG_CRYPTO_CRC32C is not set
10112 +# CONFIG_CRYPTO_CAMELLIA is not set
10113 +CONFIG_CRYPTO_TEST=m
10114 +CONFIG_CRYPTO_AUTHENC=y
10115 +# CONFIG_CRYPTO_LZO is not set
10116 +# CONFIG_CRYPTO_HW is not set
10117 +
10118 +#
10119 +# Library routines
10120 +#
10121 +CONFIG_BITREVERSE=y
10122 +CONFIG_CRC_CCITT=y
10123 +CONFIG_CRC16=y
10124 +# CONFIG_CRC_ITU_T is not set
10125 +CONFIG_CRC32=y
10126 +# CONFIG_CRC7 is not set
10127 +CONFIG_LIBCRC32C=y
10128 +CONFIG_PLIST=y
10129 +CONFIG_HAS_IOMEM=y
10130 +CONFIG_HAS_IOPORT=y
10131 +CONFIG_HAS_DMA=y
10132 --- /dev/null
10133 +++ b/arch/m68k/configs/m5485evb_defconfig
10134 @@ -0,0 +1,859 @@
10135 +#
10136 +# Automatically generated make config: don't edit
10137 +# Linux kernel version: 2.6.25
10138 +# Thu Jul 10 16:12:53 2008
10139 +#
10140 +CONFIG_M68K=y
10141 +CONFIG_MMU=y
10142 +# CONFIG_GENERIC_TIME is not set
10143 +# CONFIG_GENERIC_CLOCKEVENTS is not set
10144 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
10145 +# CONFIG_ARCH_HAS_ILOG2_U32 is not set
10146 +# CONFIG_ARCH_HAS_ILOG2_U64 is not set
10147 +CONFIG_GENERIC_HWEIGHT=y
10148 +CONFIG_GENERIC_CALIBRATE_DELAY=y
10149 +CONFIG_TIME_LOW_RES=y
10150 +CONFIG_GENERIC_IOMAP=y
10151 +# CONFIG_NO_IOPORT is not set
10152 +# CONFIG_NO_DMA is not set
10153 +CONFIG_ARCH_SUPPORTS_AOUT=y
10154 +CONFIG_HZ=100
10155 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
10156 +
10157 +#
10158 +# General setup
10159 +#
10160 +CONFIG_EXPERIMENTAL=y
10161 +CONFIG_BROKEN_ON_SMP=y
10162 +CONFIG_INIT_ENV_ARG_LIMIT=32
10163 +CONFIG_LOCALVERSION=""
10164 +CONFIG_LOCALVERSION_AUTO=y
10165 +CONFIG_SWAP=y
10166 +CONFIG_SYSVIPC=y
10167 +CONFIG_SYSVIPC_SYSCTL=y
10168 +# CONFIG_POSIX_MQUEUE is not set
10169 +# CONFIG_BSD_PROCESS_ACCT is not set
10170 +# CONFIG_TASKSTATS is not set
10171 +# CONFIG_AUDIT is not set
10172 +CONFIG_IKCONFIG=y
10173 +CONFIG_IKCONFIG_PROC=y
10174 +CONFIG_LOG_BUF_SHIFT=17
10175 +# CONFIG_CGROUPS is not set
10176 +CONFIG_GROUP_SCHED=y
10177 +CONFIG_FAIR_GROUP_SCHED=y
10178 +# CONFIG_RT_GROUP_SCHED is not set
10179 +CONFIG_USER_SCHED=y
10180 +# CONFIG_CGROUP_SCHED is not set
10181 +CONFIG_SYSFS_DEPRECATED=y
10182 +CONFIG_SYSFS_DEPRECATED_V2=y
10183 +# CONFIG_RELAY is not set
10184 +CONFIG_NAMESPACES=y
10185 +# CONFIG_UTS_NS is not set
10186 +# CONFIG_IPC_NS is not set
10187 +# CONFIG_USER_NS is not set
10188 +# CONFIG_PID_NS is not set
10189 +# CONFIG_BLK_DEV_INITRD is not set
10190 +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
10191 +CONFIG_SYSCTL=y
10192 +# CONFIG_EMBEDDED is not set
10193 +CONFIG_UID16=y
10194 +CONFIG_SYSCTL_SYSCALL=y
10195 +CONFIG_KALLSYMS=y
10196 +# CONFIG_KALLSYMS_ALL is not set
10197 +# CONFIG_KALLSYMS_EXTRA_PASS is not set
10198 +CONFIG_HOTPLUG=y
10199 +CONFIG_PRINTK=y
10200 +CONFIG_BUG=y
10201 +CONFIG_ELF_CORE=y
10202 +CONFIG_COMPAT_BRK=y
10203 +CONFIG_BASE_FULL=y
10204 +CONFIG_FUTEX=y
10205 +CONFIG_ANON_INODES=y
10206 +CONFIG_EPOLL=y
10207 +CONFIG_SIGNALFD=y
10208 +CONFIG_TIMERFD=y
10209 +CONFIG_EVENTFD=y
10210 +CONFIG_SHMEM=y
10211 +CONFIG_VM_EVENT_COUNTERS=y
10212 +CONFIG_SLAB=y
10213 +# CONFIG_SLUB is not set
10214 +# CONFIG_SLOB is not set
10215 +# CONFIG_PROFILING is not set
10216 +# CONFIG_MARKERS is not set
10217 +# CONFIG_HAVE_OPROFILE is not set
10218 +# CONFIG_HAVE_KPROBES is not set
10219 +# CONFIG_HAVE_KRETPROBES is not set
10220 +CONFIG_PROC_PAGE_MONITOR=y
10221 +CONFIG_SLABINFO=y
10222 +CONFIG_RT_MUTEXES=y
10223 +# CONFIG_TINY_SHMEM is not set
10224 +CONFIG_BASE_SMALL=0
10225 +CONFIG_MODULES=y
10226 +CONFIG_MODULE_UNLOAD=y
10227 +CONFIG_MODULE_FORCE_UNLOAD=y
10228 +# CONFIG_MODVERSIONS is not set
10229 +# CONFIG_MODULE_SRCVERSION_ALL is not set
10230 +# CONFIG_KMOD is not set
10231 +CONFIG_BLOCK=y
10232 +CONFIG_LBD=y
10233 +# CONFIG_BLK_DEV_IO_TRACE is not set
10234 +# CONFIG_LSF is not set
10235 +# CONFIG_BLK_DEV_BSG is not set
10236 +
10237 +#
10238 +# IO Schedulers
10239 +#
10240 +CONFIG_IOSCHED_NOOP=y
10241 +CONFIG_IOSCHED_AS=y
10242 +CONFIG_IOSCHED_DEADLINE=y
10243 +CONFIG_IOSCHED_CFQ=y
10244 +# CONFIG_DEFAULT_AS is not set
10245 +# CONFIG_DEFAULT_DEADLINE is not set
10246 +CONFIG_DEFAULT_CFQ=y
10247 +# CONFIG_DEFAULT_NOOP is not set
10248 +CONFIG_DEFAULT_IOSCHED="cfq"
10249 +CONFIG_CLASSIC_RCU=y
10250 +
10251 +#
10252 +# Platform dependent setup
10253 +#
10254 +# CONFIG_SUN3 is not set
10255 +CONFIG_COLDFIRE=y
10256 +CONFIG_CFV4E=y
10257 +CONFIG_MCD_DMA=y
10258 +# CONFIG_AMIGA is not set
10259 +# CONFIG_ATARI is not set
10260 +# CONFIG_MAC is not set
10261 +# CONFIG_APOLLO is not set
10262 +# CONFIG_VME is not set
10263 +# CONFIG_HP300 is not set
10264 +# CONFIG_SUN3X is not set
10265 +# CONFIG_Q40 is not set
10266 +
10267 +#
10268 +# Processor type
10269 +#
10270 +# CONFIG_M68020 is not set
10271 +# CONFIG_M68030 is not set
10272 +# CONFIG_M68040 is not set
10273 +# CONFIG_M68060 is not set
10274 +# CONFIG_M5445X is not set
10275 +CONFIG_M547X_8X=y
10276 +# CONFIG_M547X is not set
10277 +CONFIG_M548X=y
10278 +# CONFIG_M5475AFE is not set
10279 +# CONFIG_M5475BFE is not set
10280 +# CONFIG_M5475CFE is not set
10281 +# CONFIG_M5475DFE is not set
10282 +# CONFIG_M5475EFE is not set
10283 +# CONFIG_M5475FFE is not set
10284 +# CONFIG_M5485AFE is not set
10285 +# CONFIG_M5485BFE is not set
10286 +CONFIG_M5485CFE=y
10287 +# CONFIG_M5485DFE is not set
10288 +# CONFIG_M5485EFE is not set
10289 +# CONFIG_M5485FFE is not set
10290 +CONFIG_MCFCLK=200000000
10291 +# CONFIG_MCF_USER_HALT is not set
10292 +CONFIG_MMU_CFV4E=y
10293 +CONFIG_SDRAM_BASE=0x00000000
10294 +CONFIG_SDRAM_SIZE=0x04000000
10295 +CONFIG_NOR_FLASH_BASE=0xE0000000
10296 +# CONFIG_M68KFPU_EMU is not set
10297 +CONFIG_ADVANCED=y
10298 +# CONFIG_RMW_INSNS is not set
10299 +CONFIG_SINGLE_MEMORY_CHUNK=y
10300 +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
10301 +CONFIG_SELECT_MEMORY_MODEL=y
10302 +CONFIG_FLATMEM_MANUAL=y
10303 +# CONFIG_DISCONTIGMEM_MANUAL is not set
10304 +# CONFIG_SPARSEMEM_MANUAL is not set
10305 +CONFIG_FLATMEM=y
10306 +CONFIG_FLAT_NODE_MEM_MAP=y
10307 +CONFIG_NEED_MULTIPLE_NODES=y
10308 +# CONFIG_SPARSEMEM_STATIC is not set
10309 +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
10310 +CONFIG_SPLIT_PTLOCK_CPUS=4
10311 +# CONFIG_RESOURCES_64BIT is not set
10312 +CONFIG_ZONE_DMA_FLAG=1
10313 +CONFIG_BOUNCE=y
10314 +CONFIG_VIRT_TO_BUS=y
10315 +
10316 +#
10317 +# General setup
10318 +#
10319 +CONFIG_BINFMT_ELF=y
10320 +# CONFIG_BINFMT_AOUT is not set
10321 +# CONFIG_BINFMT_MISC is not set
10322 +CONFIG_PROC_HARDWARE=y
10323 +CONFIG_ZONE_DMA=y
10324 +# CONFIG_ARCH_SUPPORTS_MSI is not set
10325 +
10326 +#
10327 +# Power management options
10328 +#
10329 +# CONFIG_PM is not set
10330 +
10331 +#
10332 +# Networking
10333 +#
10334 +CONFIG_NET=y
10335 +
10336 +#
10337 +# Networking options
10338 +#
10339 +CONFIG_PACKET=y
10340 +# CONFIG_PACKET_MMAP is not set
10341 +CONFIG_UNIX=y
10342 +CONFIG_XFRM=y
10343 +# CONFIG_XFRM_USER is not set
10344 +# CONFIG_XFRM_SUB_POLICY is not set
10345 +# CONFIG_XFRM_MIGRATE is not set
10346 +# CONFIG_XFRM_STATISTICS is not set
10347 +CONFIG_NET_KEY=y
10348 +# CONFIG_NET_KEY_MIGRATE is not set
10349 +CONFIG_INET=y
10350 +# CONFIG_IP_MULTICAST is not set
10351 +CONFIG_IP_ADVANCED_ROUTER=y
10352 +CONFIG_ASK_IP_FIB_HASH=y
10353 +# CONFIG_IP_FIB_TRIE is not set
10354 +CONFIG_IP_FIB_HASH=y
10355 +# CONFIG_IP_MULTIPLE_TABLES is not set
10356 +# CONFIG_IP_ROUTE_MULTIPATH is not set
10357 +# CONFIG_IP_ROUTE_VERBOSE is not set
10358 +CONFIG_IP_PNP=y
10359 +# CONFIG_IP_PNP_DHCP is not set
10360 +# CONFIG_IP_PNP_BOOTP is not set
10361 +# CONFIG_IP_PNP_RARP is not set
10362 +# CONFIG_NET_IPIP is not set
10363 +# CONFIG_NET_IPGRE is not set
10364 +# CONFIG_ARPD is not set
10365 +# CONFIG_SYN_COOKIES is not set
10366 +CONFIG_INET_AH=y
10367 +CONFIG_INET_ESP=y
10368 +# CONFIG_INET_IPCOMP is not set
10369 +# CONFIG_INET_XFRM_TUNNEL is not set
10370 +# CONFIG_INET_TUNNEL is not set
10371 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
10372 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
10373 +# CONFIG_INET_XFRM_MODE_BEET is not set
10374 +# CONFIG_INET_LRO is not set
10375 +CONFIG_INET_DIAG=y
10376 +CONFIG_INET_TCP_DIAG=y
10377 +# CONFIG_TCP_CONG_ADVANCED is not set
10378 +CONFIG_TCP_CONG_CUBIC=y
10379 +CONFIG_DEFAULT_TCP_CONG="cubic"
10380 +# CONFIG_TCP_MD5SIG is not set
10381 +# CONFIG_IPV6 is not set
10382 +# CONFIG_INET6_XFRM_TUNNEL is not set
10383 +# CONFIG_INET6_TUNNEL is not set
10384 +# CONFIG_NETWORK_SECMARK is not set
10385 +# CONFIG_NETFILTER is not set
10386 +# CONFIG_IP_DCCP is not set
10387 +# CONFIG_IP_SCTP is not set
10388 +# CONFIG_TIPC is not set
10389 +# CONFIG_ATM is not set
10390 +# CONFIG_BRIDGE is not set
10391 +# CONFIG_VLAN_8021Q is not set
10392 +# CONFIG_DECNET is not set
10393 +# CONFIG_LLC2 is not set
10394 +# CONFIG_IPX is not set
10395 +# CONFIG_ATALK is not set
10396 +# CONFIG_X25 is not set
10397 +# CONFIG_LAPB is not set
10398 +# CONFIG_ECONET is not set
10399 +# CONFIG_WAN_ROUTER is not set
10400 +# CONFIG_NET_SCHED is not set
10401 +
10402 +#
10403 +# Network testing
10404 +#
10405 +# CONFIG_NET_PKTGEN is not set
10406 +# CONFIG_HAMRADIO is not set
10407 +# CONFIG_CAN is not set
10408 +# CONFIG_IRDA is not set
10409 +# CONFIG_BT is not set
10410 +# CONFIG_AF_RXRPC is not set
10411 +
10412 +#
10413 +# Wireless
10414 +#
10415 +# CONFIG_CFG80211 is not set
10416 +# CONFIG_WIRELESS_EXT is not set
10417 +# CONFIG_MAC80211 is not set
10418 +# CONFIG_IEEE80211 is not set
10419 +# CONFIG_RFKILL is not set
10420 +# CONFIG_NET_9P is not set
10421 +
10422 +#
10423 +# Device Drivers
10424 +#
10425 +
10426 +#
10427 +# Generic Driver Options
10428 +#
10429 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
10430 +# CONFIG_STANDALONE is not set
10431 +CONFIG_PREVENT_FIRMWARE_BUILD=y
10432 +CONFIG_FW_LOADER=y
10433 +# CONFIG_DEBUG_DRIVER is not set
10434 +# CONFIG_DEBUG_DEVRES is not set
10435 +# CONFIG_SYS_HYPERVISOR is not set
10436 +# CONFIG_CONNECTOR is not set
10437 +# CONFIG_MTD is not set
10438 +# CONFIG_PARPORT is not set
10439 +CONFIG_BLK_DEV=y
10440 +# CONFIG_BLK_DEV_COW_COMMON is not set
10441 +CONFIG_BLK_DEV_LOOP=y
10442 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set
10443 +# CONFIG_BLK_DEV_NBD is not set
10444 +CONFIG_BLK_DEV_RAM=y
10445 +CONFIG_BLK_DEV_RAM_COUNT=16
10446 +CONFIG_BLK_DEV_RAM_SIZE=64000
10447 +# CONFIG_BLK_DEV_XIP is not set
10448 +# CONFIG_CDROM_PKTCDVD is not set
10449 +# CONFIG_ATA_OVER_ETH is not set
10450 +CONFIG_MISC_DEVICES=y
10451 +CONFIG_COLDFIRE_SEC=y
10452 +CONFIG_SEC_DEVICE=y
10453 +# CONFIG_EEPROM_93CX6 is not set
10454 +# CONFIG_ENCLOSURE_SERVICES is not set
10455 +CONFIG_HAVE_IDE=y
10456 +# CONFIG_IDE is not set
10457 +
10458 +#
10459 +# SCSI device support
10460 +#
10461 +# CONFIG_RAID_ATTRS is not set
10462 +CONFIG_SCSI=y
10463 +CONFIG_SCSI_DMA=y
10464 +# CONFIG_SCSI_TGT is not set
10465 +# CONFIG_SCSI_NETLINK is not set
10466 +CONFIG_SCSI_PROC_FS=y
10467 +
10468 +#
10469 +# SCSI support type (disk, tape, CD-ROM)
10470 +#
10471 +CONFIG_BLK_DEV_SD=y
10472 +# CONFIG_CHR_DEV_ST is not set
10473 +# CONFIG_CHR_DEV_OSST is not set
10474 +# CONFIG_BLK_DEV_SR is not set
10475 +# CONFIG_CHR_DEV_SG is not set
10476 +# CONFIG_CHR_DEV_SCH is not set
10477 +
10478 +#
10479 +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
10480 +#
10481 +CONFIG_SCSI_MULTI_LUN=y
10482 +# CONFIG_SCSI_CONSTANTS is not set
10483 +# CONFIG_SCSI_LOGGING is not set
10484 +# CONFIG_SCSI_SCAN_ASYNC is not set
10485 +CONFIG_SCSI_WAIT_SCAN=m
10486 +
10487 +#
10488 +# SCSI Transports
10489 +#
10490 +# CONFIG_SCSI_SPI_ATTRS is not set
10491 +# CONFIG_SCSI_FC_ATTRS is not set
10492 +# CONFIG_SCSI_ISCSI_ATTRS is not set
10493 +# CONFIG_SCSI_SAS_LIBSAS is not set
10494 +# CONFIG_SCSI_SRP_ATTRS is not set
10495 +# CONFIG_SCSI_LOWLEVEL is not set
10496 +# CONFIG_ATA is not set
10497 +# CONFIG_MD is not set
10498 +CONFIG_NETDEVICES=y
10499 +# CONFIG_NETDEVICES_MULTIQUEUE is not set
10500 +# CONFIG_DUMMY is not set
10501 +# CONFIG_BONDING is not set
10502 +# CONFIG_MACVLAN is not set
10503 +# CONFIG_EQUALIZER is not set
10504 +# CONFIG_TUN is not set
10505 +# CONFIG_VETH is not set
10506 +# CONFIG_PHYLIB is not set
10507 +CONFIG_NET_ETHERNET=y
10508 +CONFIG_MII=y
10509 +CONFIG_FEC_548x=y
10510 +CONFIG_FEC_548x_AUTO_NEGOTIATION=y
10511 +# CONFIG_FEC_548x_ENABLE_FEC2 is not set
10512 +# CONFIG_ENC28J60 is not set
10513 +# CONFIG_IBM_NEW_EMAC_ZMII is not set
10514 +# CONFIG_IBM_NEW_EMAC_RGMII is not set
10515 +# CONFIG_IBM_NEW_EMAC_TAH is not set
10516 +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
10517 +# CONFIG_B44 is not set
10518 +# CONFIG_NETDEV_1000 is not set
10519 +# CONFIG_NETDEV_10000 is not set
10520 +
10521 +#
10522 +# Wireless LAN
10523 +#
10524 +# CONFIG_WLAN_PRE80211 is not set
10525 +# CONFIG_WLAN_80211 is not set
10526 +# CONFIG_WAN is not set
10527 +# CONFIG_PPP is not set
10528 +# CONFIG_SLIP is not set
10529 +# CONFIG_NETCONSOLE is not set
10530 +# CONFIG_NETPOLL is not set
10531 +# CONFIG_NET_POLL_CONTROLLER is not set
10532 +# CONFIG_ISDN is not set
10533 +# CONFIG_PHONE is not set
10534 +
10535 +#
10536 +# Input device support
10537 +#
10538 +CONFIG_INPUT=y
10539 +# CONFIG_INPUT_FF_MEMLESS is not set
10540 +# CONFIG_INPUT_POLLDEV is not set
10541 +
10542 +#
10543 +# Userland interfaces
10544 +#
10545 +CONFIG_INPUT_MOUSEDEV=y
10546 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
10547 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
10548 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
10549 +# CONFIG_INPUT_JOYDEV is not set
10550 +CONFIG_INPUT_EVDEV=y
10551 +# CONFIG_INPUT_EVBUG is not set
10552 +
10553 +#
10554 +# Input Device Drivers
10555 +#
10556 +CONFIG_INPUT_KEYBOARD=y
10557 +# CONFIG_KEYBOARD_ATKBD is not set
10558 +# CONFIG_KEYBOARD_SUNKBD is not set
10559 +# CONFIG_KEYBOARD_LKKBD is not set
10560 +# CONFIG_KEYBOARD_XTKBD is not set
10561 +# CONFIG_KEYBOARD_NEWTON is not set
10562 +# CONFIG_KEYBOARD_STOWAWAY is not set
10563 +# CONFIG_INPUT_MOUSE is not set
10564 +# CONFIG_INPUT_JOYSTICK is not set
10565 +# CONFIG_INPUT_TABLET is not set
10566 +# CONFIG_INPUT_TOUCHSCREEN is not set
10567 +# CONFIG_INPUT_MISC is not set
10568 +
10569 +#
10570 +# Hardware I/O ports
10571 +#
10572 +CONFIG_SERIO=y
10573 +CONFIG_SERIO_SERPORT=y
10574 +# CONFIG_SERIO_RAW is not set
10575 +# CONFIG_GAMEPORT is not set
10576 +
10577 +#
10578 +# Character devices
10579 +#
10580 +CONFIG_VT=y
10581 +CONFIG_VT_CONSOLE=y
10582 +CONFIG_HW_CONSOLE=y
10583 +# CONFIG_VT_HW_CONSOLE_BINDING is not set
10584 +# CONFIG_SERIAL_NONSTANDARD is not set
10585 +
10586 +#
10587 +# Serial drivers
10588 +#
10589 +# CONFIG_SERIAL_8250 is not set
10590 +
10591 +#
10592 +# Non-8250 serial port support
10593 +#
10594 +CONFIG_SERIAL_COLDFIRE=y
10595 +# CONFIG_SERIAL_COLDFIRE_IRDA is not set
10596 +# CONFIG_SERIAL_MCF is not set
10597 +CONFIG_UNIX98_PTYS=y
10598 +# CONFIG_LEGACY_PTYS is not set
10599 +# CONFIG_IPMI_HANDLER is not set
10600 +# CONFIG_HW_RANDOM is not set
10601 +# CONFIG_GEN_RTC is not set
10602 +# CONFIG_R3964 is not set
10603 +# CONFIG_RAW_DRIVER is not set
10604 +# CONFIG_TCG_TPM is not set
10605 +CONFIG_I2C=y
10606 +CONFIG_I2C_BOARDINFO=y
10607 +# CONFIG_I2C_CHARDEV is not set
10608 +
10609 +#
10610 +# I2C Algorithms
10611 +#
10612 +# CONFIG_I2C_ALGOBIT is not set
10613 +# CONFIG_I2C_ALGOPCF is not set
10614 +# CONFIG_I2C_ALGOPCA is not set
10615 +
10616 +#
10617 +# I2C Hardware Bus support
10618 +#
10619 +CONFIG_I2C_MCF548x=y
10620 +# CONFIG_I2C_MCF is not set
10621 +# CONFIG_I2C_OCORES is not set
10622 +# CONFIG_I2C_PARPORT_LIGHT is not set
10623 +# CONFIG_I2C_SIMTEC is not set
10624 +# CONFIG_I2C_TAOS_EVM is not set
10625 +# CONFIG_I2C_STUB is not set
10626 +
10627 +#
10628 +# Miscellaneous I2C Chip support
10629 +#
10630 +# CONFIG_DS1682 is not set
10631 +# CONFIG_SENSORS_EEPROM is not set
10632 +# CONFIG_SENSORS_PCF8574 is not set
10633 +# CONFIG_PCF8575 is not set
10634 +# CONFIG_SENSORS_PCF8591 is not set
10635 +# CONFIG_TPS65010 is not set
10636 +# CONFIG_SENSORS_MAX6875 is not set
10637 +# CONFIG_SENSORS_TSL2550 is not set
10638 +# CONFIG_I2C_DEBUG_CORE is not set
10639 +# CONFIG_I2C_DEBUG_ALGO is not set
10640 +# CONFIG_I2C_DEBUG_BUS is not set
10641 +# CONFIG_I2C_DEBUG_CHIP is not set
10642 +
10643 +#
10644 +# SPI support
10645 +#
10646 +CONFIG_SPI=y
10647 +CONFIG_SPI_DEBUG=y
10648 +# CONFIG_COLDFIRE_EDMA is not set
10649 +CONFIG_SPI_MASTER=y
10650 +
10651 +#
10652 +# SPI Master Controller Drivers
10653 +#
10654 +# CONFIG_SPI_BITBANG is not set
10655 +CONFIG_SPI_COLDFIRE=y
10656 +
10657 +#
10658 +# SPI Protocol Masters
10659 +#
10660 +# CONFIG_SPI_AT25 is not set
10661 +# CONFIG_SPI_SPIDEV is not set
10662 +# CONFIG_SPI_TLE62X0 is not set
10663 +# CONFIG_SPI_COLDFIRE_SSI_AUDIO is not set
10664 +# CONFIG_W1 is not set
10665 +# CONFIG_POWER_SUPPLY is not set
10666 +# CONFIG_HWMON is not set
10667 +# CONFIG_THERMAL is not set
10668 +# CONFIG_WATCHDOG is not set
10669 +
10670 +#
10671 +# Sonics Silicon Backplane
10672 +#
10673 +CONFIG_SSB_POSSIBLE=y
10674 +# CONFIG_SSB is not set
10675 +
10676 +#
10677 +# Multifunction device drivers
10678 +#
10679 +# CONFIG_MFD_SM501 is not set
10680 +
10681 +#
10682 +# Multimedia devices
10683 +#
10684 +# CONFIG_VIDEO_DEV is not set
10685 +# CONFIG_DVB_CORE is not set
10686 +CONFIG_DAB=y
10687 +
10688 +#
10689 +# Graphics support
10690 +#
10691 +# CONFIG_VGASTATE is not set
10692 +CONFIG_VIDEO_OUTPUT_CONTROL=m
10693 +# CONFIG_FB is not set
10694 +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
10695 +
10696 +#
10697 +# Display device support
10698 +#
10699 +# CONFIG_DISPLAY_SUPPORT is not set
10700 +
10701 +#
10702 +# Console display driver support
10703 +#
10704 +CONFIG_DUMMY_CONSOLE=y
10705 +
10706 +#
10707 +# Sound
10708 +#
10709 +# CONFIG_SOUND is not set
10710 +CONFIG_HID_SUPPORT=y
10711 +CONFIG_HID=y
10712 +CONFIG_HID_DEBUG=y
10713 +# CONFIG_HIDRAW is not set
10714 +# CONFIG_USB_SUPPORT is not set
10715 +# CONFIG_MMC is not set
10716 +# CONFIG_MEMSTICK is not set
10717 +# CONFIG_NEW_LEDS is not set
10718 +# CONFIG_RTC_CLASS is not set
10719 +
10720 +#
10721 +# Userspace I/O
10722 +#
10723 +# CONFIG_UIO is not set
10724 +
10725 +#
10726 +# Character devices
10727 +#
10728 +# CONFIG_SERIAL_CONSOLE is not set
10729 +
10730 +#
10731 +# File systems
10732 +#
10733 +CONFIG_EXT2_FS=y
10734 +# CONFIG_EXT2_FS_XATTR is not set
10735 +# CONFIG_EXT2_FS_XIP is not set
10736 +CONFIG_EXT3_FS=y
10737 +CONFIG_EXT3_FS_XATTR=y
10738 +# CONFIG_EXT3_FS_POSIX_ACL is not set
10739 +# CONFIG_EXT3_FS_SECURITY is not set
10740 +# CONFIG_EXT4DEV_FS is not set
10741 +CONFIG_JBD=y
10742 +CONFIG_FS_MBCACHE=y
10743 +# CONFIG_REISERFS_FS is not set
10744 +# CONFIG_JFS_FS is not set
10745 +# CONFIG_FS_POSIX_ACL is not set
10746 +# CONFIG_XFS_FS is not set
10747 +# CONFIG_GFS2_FS is not set
10748 +# CONFIG_OCFS2_FS is not set
10749 +CONFIG_DNOTIFY=y
10750 +# CONFIG_INOTIFY is not set
10751 +# CONFIG_QUOTA is not set
10752 +# CONFIG_AUTOFS_FS is not set
10753 +# CONFIG_AUTOFS4_FS is not set
10754 +# CONFIG_FUSE_FS is not set
10755 +
10756 +#
10757 +# CD-ROM/DVD Filesystems
10758 +#
10759 +# CONFIG_ISO9660_FS is not set
10760 +# CONFIG_UDF_FS is not set
10761 +
10762 +#
10763 +# DOS/FAT/NT Filesystems
10764 +#
10765 +CONFIG_FAT_FS=y
10766 +CONFIG_MSDOS_FS=y
10767 +CONFIG_VFAT_FS=y
10768 +CONFIG_FAT_DEFAULT_CODEPAGE=437
10769 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
10770 +CONFIG_NTFS_FS=y
10771 +# CONFIG_NTFS_DEBUG is not set
10772 +CONFIG_NTFS_RW=y
10773 +
10774 +#
10775 +# Pseudo filesystems
10776 +#
10777 +CONFIG_PROC_FS=y
10778 +# CONFIG_PROC_KCORE is not set
10779 +CONFIG_PROC_SYSCTL=y
10780 +CONFIG_SYSFS=y
10781 +CONFIG_TMPFS=y
10782 +# CONFIG_TMPFS_POSIX_ACL is not set
10783 +# CONFIG_HUGETLB_PAGE is not set
10784 +# CONFIG_CONFIGFS_FS is not set
10785 +
10786 +#
10787 +# Miscellaneous filesystems
10788 +#
10789 +# CONFIG_ADFS_FS is not set
10790 +# CONFIG_AFFS_FS is not set
10791 +# CONFIG_HFS_FS is not set
10792 +# CONFIG_HFSPLUS_FS is not set
10793 +# CONFIG_BEFS_FS is not set
10794 +# CONFIG_BFS_FS is not set
10795 +# CONFIG_EFS_FS is not set
10796 +# CONFIG_CRAMFS is not set
10797 +# CONFIG_VXFS_FS is not set
10798 +CONFIG_MINIX_FS=y
10799 +# CONFIG_HPFS_FS is not set
10800 +# CONFIG_QNX4FS_FS is not set
10801 +CONFIG_ROMFS_FS=y
10802 +# CONFIG_SYSV_FS is not set
10803 +# CONFIG_UFS_FS is not set
10804 +CONFIG_NETWORK_FILESYSTEMS=y
10805 +CONFIG_NFS_FS=y
10806 +# CONFIG_NFS_V3 is not set
10807 +# CONFIG_NFS_V4 is not set
10808 +# CONFIG_NFS_DIRECTIO is not set
10809 +# CONFIG_NFSD is not set
10810 +CONFIG_ROOT_NFS=y
10811 +CONFIG_LOCKD=y
10812 +CONFIG_NFS_COMMON=y
10813 +CONFIG_SUNRPC=y
10814 +# CONFIG_SUNRPC_BIND34 is not set
10815 +# CONFIG_RPCSEC_GSS_KRB5 is not set
10816 +# CONFIG_RPCSEC_GSS_SPKM3 is not set
10817 +# CONFIG_SMB_FS is not set
10818 +# CONFIG_CIFS is not set
10819 +# CONFIG_NCP_FS is not set
10820 +# CONFIG_CODA_FS is not set
10821 +# CONFIG_AFS_FS is not set
10822 +
10823 +#
10824 +# Partition Types
10825 +#
10826 +CONFIG_PARTITION_ADVANCED=y
10827 +# CONFIG_ACORN_PARTITION is not set
10828 +# CONFIG_OSF_PARTITION is not set
10829 +# CONFIG_AMIGA_PARTITION is not set
10830 +# CONFIG_ATARI_PARTITION is not set
10831 +# CONFIG_MAC_PARTITION is not set
10832 +CONFIG_MSDOS_PARTITION=y
10833 +# CONFIG_BSD_DISKLABEL is not set
10834 +# CONFIG_MINIX_SUBPARTITION is not set
10835 +# CONFIG_SOLARIS_X86_PARTITION is not set
10836 +# CONFIG_UNIXWARE_DISKLABEL is not set
10837 +# CONFIG_LDM_PARTITION is not set
10838 +# CONFIG_SGI_PARTITION is not set
10839 +# CONFIG_ULTRIX_PARTITION is not set
10840 +# CONFIG_SUN_PARTITION is not set
10841 +# CONFIG_KARMA_PARTITION is not set
10842 +# CONFIG_EFI_PARTITION is not set
10843 +# CONFIG_SYSV68_PARTITION is not set
10844 +CONFIG_NLS=y
10845 +CONFIG_NLS_DEFAULT="iso8859-1"
10846 +CONFIG_NLS_CODEPAGE_437=y
10847 +# CONFIG_NLS_CODEPAGE_737 is not set
10848 +# CONFIG_NLS_CODEPAGE_775 is not set
10849 +# CONFIG_NLS_CODEPAGE_850 is not set
10850 +# CONFIG_NLS_CODEPAGE_852 is not set
10851 +# CONFIG_NLS_CODEPAGE_855 is not set
10852 +# CONFIG_NLS_CODEPAGE_857 is not set
10853 +# CONFIG_NLS_CODEPAGE_860 is not set
10854 +# CONFIG_NLS_CODEPAGE_861 is not set
10855 +# CONFIG_NLS_CODEPAGE_862 is not set
10856 +# CONFIG_NLS_CODEPAGE_863 is not set
10857 +# CONFIG_NLS_CODEPAGE_864 is not set
10858 +# CONFIG_NLS_CODEPAGE_865 is not set
10859 +# CONFIG_NLS_CODEPAGE_866 is not set
10860 +# CONFIG_NLS_CODEPAGE_869 is not set
10861 +# CONFIG_NLS_CODEPAGE_936 is not set
10862 +# CONFIG_NLS_CODEPAGE_950 is not set
10863 +# CONFIG_NLS_CODEPAGE_932 is not set
10864 +# CONFIG_NLS_CODEPAGE_949 is not set
10865 +# CONFIG_NLS_CODEPAGE_874 is not set
10866 +# CONFIG_NLS_ISO8859_8 is not set
10867 +# CONFIG_NLS_CODEPAGE_1250 is not set
10868 +# CONFIG_NLS_CODEPAGE_1251 is not set
10869 +# CONFIG_NLS_ASCII is not set
10870 +CONFIG_NLS_ISO8859_1=y
10871 +# CONFIG_NLS_ISO8859_2 is not set
10872 +# CONFIG_NLS_ISO8859_3 is not set
10873 +# CONFIG_NLS_ISO8859_4 is not set
10874 +# CONFIG_NLS_ISO8859_5 is not set
10875 +# CONFIG_NLS_ISO8859_6 is not set
10876 +# CONFIG_NLS_ISO8859_7 is not set
10877 +# CONFIG_NLS_ISO8859_9 is not set
10878 +# CONFIG_NLS_ISO8859_13 is not set
10879 +# CONFIG_NLS_ISO8859_14 is not set
10880 +# CONFIG_NLS_ISO8859_15 is not set
10881 +# CONFIG_NLS_KOI8_R is not set
10882 +# CONFIG_NLS_KOI8_U is not set
10883 +CONFIG_NLS_UTF8=y
10884 +# CONFIG_DLM is not set
10885 +
10886 +#
10887 +# Kernel hacking
10888 +#
10889 +# CONFIG_PRINTK_TIME is not set
10890 +CONFIG_ENABLE_WARN_DEPRECATED=y
10891 +# CONFIG_ENABLE_MUST_CHECK is not set
10892 +# CONFIG_MAGIC_SYSRQ is not set
10893 +# CONFIG_UNUSED_SYMBOLS is not set
10894 +# CONFIG_DEBUG_FS is not set
10895 +# CONFIG_HEADERS_CHECK is not set
10896 +CONFIG_DEBUG_KERNEL=y
10897 +CONFIG_DETECT_SOFTLOCKUP=y
10898 +CONFIG_SCHED_DEBUG=y
10899 +# CONFIG_SCHEDSTATS is not set
10900 +# CONFIG_TIMER_STATS is not set
10901 +CONFIG_DEBUG_SLAB=y
10902 +# CONFIG_DEBUG_SLAB_LEAK is not set
10903 +# CONFIG_DEBUG_RT_MUTEXES is not set
10904 +# CONFIG_RT_MUTEX_TESTER is not set
10905 +# CONFIG_DEBUG_SPINLOCK is not set
10906 +# CONFIG_DEBUG_MUTEXES is not set
10907 +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
10908 +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
10909 +# CONFIG_DEBUG_KOBJECT is not set
10910 +CONFIG_DEBUG_BUGVERBOSE=y
10911 +CONFIG_DEBUG_INFO=y
10912 +# CONFIG_DEBUG_VM is not set
10913 +# CONFIG_DEBUG_LIST is not set
10914 +# CONFIG_DEBUG_SG is not set
10915 +# CONFIG_FRAME_POINTER is not set
10916 +# CONFIG_BOOT_PRINTK_DELAY is not set
10917 +# CONFIG_RCU_TORTURE_TEST is not set
10918 +# CONFIG_BACKTRACE_SELF_TEST is not set
10919 +# CONFIG_FAULT_INJECTION is not set
10920 +# CONFIG_SAMPLES is not set
10921 +CONFIG_BOOTPARAM=y
10922 +CONFIG_BOOTPARAM_STRING="root=/dev/nfs rw nfsroot=172.27.163.2:/tftpboot/ltib ip=172.27.163.3:172.27.163.2:172.27.255.254:255.255.0.0::eth0:off mtdparts=phys_mapped_flash:16m(User)"
10923 +
10924 +#
10925 +# Security options
10926 +#
10927 +# CONFIG_KEYS is not set
10928 +# CONFIG_SECURITY is not set
10929 +# CONFIG_SECURITY_FILE_CAPABILITIES is not set
10930 +CONFIG_CRYPTO=y
10931 +CONFIG_CRYPTO_ALGAPI=y
10932 +CONFIG_CRYPTO_AEAD=y
10933 +CONFIG_CRYPTO_BLKCIPHER=y
10934 +# CONFIG_CRYPTO_SEQIV is not set
10935 +CONFIG_CRYPTO_HASH=y
10936 +CONFIG_CRYPTO_MANAGER=y
10937 +CONFIG_CRYPTO_HMAC=y
10938 +# CONFIG_CRYPTO_XCBC is not set
10939 +# CONFIG_CRYPTO_NULL is not set
10940 +# CONFIG_CRYPTO_MD4 is not set
10941 +CONFIG_CRYPTO_MD5=y
10942 +CONFIG_CRYPTO_SHA1=y
10943 +# CONFIG_CRYPTO_SHA256 is not set
10944 +# CONFIG_CRYPTO_SHA512 is not set
10945 +# CONFIG_CRYPTO_WP512 is not set
10946 +# CONFIG_CRYPTO_TGR192 is not set
10947 +# CONFIG_CRYPTO_GF128MUL is not set
10948 +# CONFIG_CRYPTO_ECB is not set
10949 +CONFIG_CRYPTO_CBC=y
10950 +# CONFIG_CRYPTO_PCBC is not set
10951 +# CONFIG_CRYPTO_LRW is not set
10952 +# CONFIG_CRYPTO_XTS is not set
10953 +# CONFIG_CRYPTO_CTR is not set
10954 +# CONFIG_CRYPTO_GCM is not set
10955 +# CONFIG_CRYPTO_CCM is not set
10956 +# CONFIG_CRYPTO_CRYPTD is not set
10957 +CONFIG_CRYPTO_DES=y
10958 +# CONFIG_CRYPTO_FCRYPT is not set
10959 +# CONFIG_CRYPTO_BLOWFISH is not set
10960 +# CONFIG_CRYPTO_TWOFISH is not set
10961 +# CONFIG_CRYPTO_SERPENT is not set
10962 +# CONFIG_CRYPTO_AES is not set
10963 +# CONFIG_CRYPTO_CAST5 is not set
10964 +# CONFIG_CRYPTO_CAST6 is not set
10965 +# CONFIG_CRYPTO_TEA is not set
10966 +# CONFIG_CRYPTO_ARC4 is not set
10967 +# CONFIG_CRYPTO_KHAZAD is not set
10968 +# CONFIG_CRYPTO_ANUBIS is not set
10969 +# CONFIG_CRYPTO_SEED is not set
10970 +# CONFIG_CRYPTO_SALSA20 is not set
10971 +# CONFIG_CRYPTO_DEFLATE is not set
10972 +# CONFIG_CRYPTO_MICHAEL_MIC is not set
10973 +# CONFIG_CRYPTO_CRC32C is not set
10974 +# CONFIG_CRYPTO_CAMELLIA is not set
10975 +CONFIG_CRYPTO_TEST=m
10976 +CONFIG_CRYPTO_AUTHENC=y
10977 +# CONFIG_CRYPTO_LZO is not set
10978 +# CONFIG_CRYPTO_HW is not set
10979 +
10980 +#
10981 +# Library routines
10982 +#
10983 +CONFIG_BITREVERSE=y
10984 +CONFIG_CRC_CCITT=y
10985 +CONFIG_CRC16=y
10986 +# CONFIG_CRC_ITU_T is not set
10987 +CONFIG_CRC32=y
10988 +# CONFIG_CRC7 is not set
10989 +CONFIG_LIBCRC32C=y
10990 +CONFIG_PLIST=y
10991 +CONFIG_HAS_IOMEM=y
10992 +CONFIG_HAS_IOPORT=y
10993 +CONFIG_HAS_DMA=y
10994 --- a/arch/m68k/Kconfig
10995 +++ b/arch/m68k/Kconfig
10996 @@ -11,6 +11,14 @@ config MMU
10997 bool
10998 default y
10999
11000 +config GENERIC_TIME
11001 + bool
11002 + default n
11003 +
11004 +config GENERIC_CLOCKEVENTS
11005 + bool
11006 + default n
11007 +
11008 config RWSEM_GENERIC_SPINLOCK
11009 bool
11010 default y
11011 @@ -48,7 +56,7 @@ config ARCH_MAY_HAVE_PC_FDC
11012 default y
11013
11014 config NO_IOPORT
11015 - def_bool y
11016 + def_bool !(M5445X || M547X_8X)
11017
11018 config NO_DMA
11019 def_bool SUN3
11020 @@ -119,6 +127,29 @@ config SUN3
11021
11022 If you don't want to compile a kernel exclusively for a Sun 3, say N.
11023
11024 +config COLDFIRE
11025 + bool "ColdFire V4e support"
11026 + default y
11027 + select CFV4E
11028 + help
11029 + Say Y if you want to build a kernel to run on one of the ColdFire
11030 + V4e boards.
11031 +
11032 +config CFV4E
11033 + bool
11034 + depends on COLDFIRE
11035 + select MMU_CFV4E if MMU
11036 + default y
11037 +
11038 +config MCD_DMA
11039 + bool "ColdFire MCD DMA support"
11040 + depends on M547X_8X
11041 + default y
11042 + help
11043 + This enables support for the ColdFire 547x/548x family
11044 + multichannel DMA support. Many drivers need it.
11045 + If you want it, say Y
11046 +
11047 config AMIGA
11048 bool "Amiga support"
11049 depends on !MMU_SUN3
11050 @@ -144,9 +175,9 @@ config HADES
11051 to use this kernel on a Hades, say Y here; otherwise say N.
11052
11053 config PCI
11054 - bool
11055 - depends on HADES
11056 - default y
11057 + bool "PCI bus support"
11058 + depends on HADES || M54455 || M547X_8X
11059 + default n
11060 help
11061 Find out whether you have a PCI motherboard. PCI is the name of a
11062 bus system, i.e. the way the CPU talks to the other stuff inside
11063 @@ -294,14 +325,142 @@ config M68060
11064 If you anticipate running this kernel on a computer with a MC68060
11065 processor, say Y. Otherwise, say N.
11066
11067 +config M5445X
11068 + bool "MCF5445x support"
11069 + depends on COLDFIRE
11070 + help
11071 + This option will add support for the MCF5445 processor with mmu.
11072 +
11073 +config M54451
11074 + bool
11075 + depends on M5445X
11076 + default n
11077 +
11078 +config M54455
11079 + bool
11080 + depends on M5445X
11081 + default n
11082 +
11083 +choice
11084 + prompt "Model"
11085 + depends on M5445X
11086 + default M54451EVB
11087 + config M54451EVB
11088 + bool "M54451EVB"
11089 + select M54451
11090 + config M54455EVB
11091 + bool "M54455EVB"
11092 + select M54455
11093 +endchoice
11094 +
11095 +
11096 +config M547X_8X
11097 + bool "MCF547x/MCF548x support"
11098 + depends on COLDFIRE
11099 + help
11100 + This option will add support for the MCF547x/MCF548x processor with mmu.
11101 +
11102 +config M547X
11103 + bool
11104 + depends on M547X_8X
11105 + default n
11106 +
11107 +config M548X
11108 + bool
11109 + depends on M547X_8X
11110 + default n
11111 +
11112 +choice
11113 + prompt "Model"
11114 + depends on M547X_8X
11115 + default M5485CFE
11116 + config M5475AFE
11117 + bool "MCF5475AFE"
11118 + select M547X
11119 + config M5475BFE
11120 + bool "MCF5475BFE"
11121 + select M547X
11122 + config M5475CFE
11123 + bool "MCF5475CFE"
11124 + select M547X
11125 + config M5475DFE
11126 + bool "MCF5475DFE"
11127 + select M547X
11128 + config M5475EFE
11129 + bool "MCF5475EFE"
11130 + select M547X
11131 + config M5475FFE
11132 + bool "MCF5475FFE"
11133 + select M547X
11134 +
11135 + config M5485AFE
11136 + bool "MCF5485AFE"
11137 + select M548X
11138 + config M5485BFE
11139 + bool "MCF5485BFE"
11140 + select M548X
11141 + config M5485CFE
11142 + bool "MCF5485CFE"
11143 + select M548X
11144 + config M5485DFE
11145 + bool "MCF5485DFE"
11146 + select M548X
11147 + config M5485EFE
11148 + bool "MCF5485EFE"
11149 + select M548X
11150 + config M5485FFE
11151 + bool "MCF5485FFE"
11152 + select M548X
11153 +
11154 +endchoice
11155 +
11156 +config MCFCLK
11157 + int
11158 + default 266666666 if M54455EVB
11159 + default 240000000 if M54451EVB
11160 + default 266000000 if M547X
11161 + default 200000000 if M548X
11162 + help
11163 + Coldfire System clock.
11164 +
11165 +config MCF_USER_HALT
11166 + bool "Coldfire User Halt Enable"
11167 + depends on M5445X || M547X_8X
11168 + default n
11169 + help
11170 + Enables the HALT instruction in User Mode.
11171 +
11172 config MMU_MOTOROLA
11173 bool
11174 - depends on MMU && !MMU_SUN3
11175 + depends on MMU && !MMU_SUN3 && !COLDFIRE
11176 default y
11177
11178 config MMU_SUN3
11179 bool
11180
11181 +config MMU_CFV4E
11182 + bool
11183 +
11184 +config SDRAM_BASE
11185 + hex
11186 + depends on COLDFIRE
11187 + default 0x40000000 if M5445X
11188 + default 0x00000000 if M547X_8X
11189 +
11190 +config SDRAM_SIZE
11191 + hex
11192 + depends on COLDFIRE
11193 + default 0x08000000 if M54451EVB
11194 + default 0x10000000 if M54455EVB
11195 + default 0x04000000 if M547X_8X
11196 +
11197 +config NOR_FLASH_BASE
11198 + hex "NOR Flash Base Address"
11199 + depends on COLDFIRE
11200 + default 0x00000000 if M54451EVB
11201 + default 0x00000000 if M54455EVB
11202 + default 0xE0000000 if M547X_8X
11203 +
11204 config M68KFPU_EMU
11205 bool "Math emulation support (EXPERIMENTAL)"
11206 depends on EXPERIMENTAL
11207 @@ -468,6 +627,14 @@ config ZONE_DMA
11208 source "drivers/pci/Kconfig"
11209
11210 source "drivers/zorro/Kconfig"
11211 +endmenu
11212 +
11213 +menu "Power management options"
11214 +
11215 +config PM
11216 + bool "Power Management support"
11217 + help
11218 + Support processor power management modes
11219
11220 endmenu
11221
11222 @@ -647,7 +814,7 @@ config DN_SERIAL
11223
11224 config SERIAL_CONSOLE
11225 bool "Support for serial port console"
11226 - depends on (AMIGA || ATARI || MAC || SUN3 || SUN3X || VME || APOLLO) && (ATARI_MFPSER=y || ATARI_SCC=y || ATARI_MIDI=y || MAC_SCC=y || AMIGA_BUILTIN_SERIAL=y || GVPIOEXT=y || MULTIFACE_III_TTY=y || SERIAL=y || MVME147_SCC || SERIAL167 || MVME162_SCC || BVME6000_SCC || DN_SERIAL)
11227 + depends on (AMIGA || ATARI || MAC || SUN3 || SUN3X || VME || APOLLO || COLDFIRE) && (ATARI_MFPSER=y || ATARI_SCC=y || ATARI_MIDI=y || MAC_SCC=y || AMIGA_BUILTIN_SERIAL=y || GVPIOEXT=y || MULTIFACE_III_TTY=y || SERIAL=y || MVME147_SCC || SERIAL167 || MVME162_SCC || BVME6000_SCC || DN_SERIAL || SERIAL_COLDFIRE)
11228 ---help---
11229 If you say Y here, it will be possible to use a serial port as the
11230 system console (the system console is the device which receives all
11231 --- a/arch/m68k/Kconfig.debug
11232 +++ b/arch/m68k/Kconfig.debug
11233 @@ -2,4 +2,13 @@ menu "Kernel hacking"
11234
11235 source "lib/Kconfig.debug"
11236
11237 +config BOOTPARAM
11238 + bool 'Compiled-in Kernel Boot Parameter'
11239 + depends on COLDFIRE
11240 +
11241 +config BOOTPARAM_STRING
11242 + string 'Kernel Boot Parameter'
11243 + default 'console=ttyS0,115200'
11244 + depends on BOOTPARAM
11245 +
11246 endmenu
11247 --- a/arch/m68k/kernel/asm-offsets.c
11248 +++ b/arch/m68k/kernel/asm-offsets.c
11249 @@ -58,8 +58,15 @@ int main(void)
11250 DEFINE(PT_A2, offsetof(struct pt_regs, a2));
11251 DEFINE(PT_PC, offsetof(struct pt_regs, pc));
11252 DEFINE(PT_SR, offsetof(struct pt_regs, sr));
11253 +#ifdef CONFIG_COLDFIRE
11254 + /* Need to get the context out of struct mm for ASID setting */
11255 + DEFINE(MM_CONTEXT, offsetof(struct mm_struct, context));
11256 + /* Coldfire exception frame has vector *before* pc */
11257 + DEFINE(PT_VECTOR, offsetof(struct pt_regs, pc) - 4);
11258 +#else
11259 /* bitfields are a bit difficult */
11260 DEFINE(PT_VECTOR, offsetof(struct pt_regs, pc) + 4);
11261 +#endif
11262
11263 /* offsets into the irq_handler struct */
11264 DEFINE(IRQ_HANDLER, offsetof(struct irq_node, handler));
11265 --- /dev/null
11266 +++ b/arch/m68k/kernel/bios32_mcf548x.c
11267 @@ -0,0 +1,631 @@
11268 +/*
11269 + * bios32.c - PCI BIOS functions for m68k systems.
11270 + *
11271 + * Written by Wout Klaren.
11272 + *
11273 + * Based on the DEC Alpha bios32.c by Dave Rusling and David Mosberger.
11274 + */
11275 +#include <linux/init.h>
11276 +#include <linux/kernel.h>
11277 +
11278 +#if 0
11279 +# define DBG_DEVS(args) printk args
11280 +#else
11281 +# define DBG_DEVS(args)
11282 +#endif
11283 +
11284 +#ifdef CONFIG_PCI
11285 +
11286 +/*
11287 + * PCI support for Linux/m68k. Currently only the Hades is supported.
11288 + *
11289 + * The support for PCI bridges in the DEC Alpha version has
11290 + * been removed in this version.
11291 + */
11292 +
11293 +#include <linux/pci.h>
11294 +#include <linux/slab.h>
11295 +#include <linux/mm.h>
11296 +
11297 +#include <asm/io.h>
11298 +#include <asm/pci.h>
11299 +#include <asm/uaccess.h>
11300 +
11301 +#define KB 1024
11302 +#define MB (1024*KB)
11303 +#define GB (1024*MB)
11304 +
11305 +#define MAJOR_REV 0
11306 +#define MINOR_REV 5
11307 +
11308 +/*
11309 + * Align VAL to ALIGN, which must be a power of two.
11310 + */
11311 +
11312 +#define MAX(val1, val2) (((val1) > (val2)) ? val1 : val2)
11313 +
11314 +/*
11315 + * Offsets relative to the I/O and memory base addresses from where resources
11316 + * are allocated.
11317 + */
11318 +
11319 +#ifdef CONFIG_COLDFIRE
11320 +#define IO_ALLOC_OFFSET 0x00000100
11321 +#define MEM_ALLOC_OFFSET 0x00000000
11322 +#else /* CONFIG_COLDFIRE */
11323 +#define IO_ALLOC_OFFSET 0x00004000
11324 +#define MEM_ALLOC_OFFSET 0x04000000
11325 +#endif /* CONFIG_COLDFIRE */
11326 +
11327 +/*
11328 + * Declarations of hardware specific initialisation functions.
11329 + */
11330 +
11331 +extern struct pci_bus_info *init_hades_pci(void);
11332 +
11333 +/*
11334 + * Bus info structure of the PCI bus. A pointer to this structure is
11335 + * put in the sysdata member of the pci_bus structure.
11336 + */
11337 +
11338 +static struct pci_bus_info *bus_info;
11339 +
11340 +static int pci_modify = 1; /* If set, layout the PCI bus ourself. */
11341 +static int skip_vga; /* If set do not modify base addresses
11342 + of vga cards.*/
11343 +static int disable_pci_burst; /* If set do not allow PCI bursts. */
11344 +
11345 +static unsigned int io_base;
11346 +static unsigned int mem_base;
11347 +
11348 +/*
11349 + * static void disable_dev(struct pci_dev *dev)
11350 + *
11351 + * Disable PCI device DEV so that it does not respond to I/O or memory
11352 + * accesses.
11353 + *
11354 + * Parameters:
11355 + *
11356 + * dev - device to disable.
11357 + */
11358 +
11359 +static void __init disable_dev(struct pci_dev *dev)
11360 +{
11361 + unsigned short cmd;
11362 +
11363 + if (((dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA) ||
11364 + (dev->class >> 8 == PCI_CLASS_DISPLAY_VGA) ||
11365 + (dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)) && skip_vga)
11366 + return;
11367 +
11368 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
11369 +
11370 + cmd &= (~PCI_COMMAND_IO & ~PCI_COMMAND_MEMORY & ~PCI_COMMAND_MASTER);
11371 + pci_write_config_word(dev, PCI_COMMAND, cmd);
11372 +}
11373 +
11374 +/* Stolen from pcibios_enable_resources/i386 */
11375 +int pcibios_enable_device(struct pci_dev *dev, int mask)
11376 +{
11377 + u16 cmd, old_cmd;
11378 + int idx;
11379 + struct resource *r;
11380 +
11381 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
11382 + old_cmd = cmd;
11383 + for(idx=0; idx<6; idx++) {
11384 + /* Only set up the requested stuff */
11385 + if (!(mask & (1<<idx)))
11386 + continue;
11387 +
11388 + r = &dev->resource[idx];
11389 + if (!r->start && r->end) {
11390 + printk("PCI: Device %s not available because"
11391 + " of resource collisions\n", dev->dev.bus_id);
11392 + return -EINVAL;
11393 + }
11394 + if (r->flags & IORESOURCE_IO)
11395 + cmd |= PCI_COMMAND_IO;
11396 + if (r->flags & IORESOURCE_MEM)
11397 + cmd |= PCI_COMMAND_MEMORY;
11398 + }
11399 + if (dev->resource[PCI_ROM_RESOURCE].start)
11400 + cmd |= PCI_COMMAND_MEMORY;
11401 + if (cmd != old_cmd) {
11402 + printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->dev.bus_id, old_cmd, cmd);
11403 + pci_write_config_word(dev, PCI_COMMAND, cmd);
11404 + }
11405 + return 0;
11406 +}
11407 +
11408 +/*
11409 + * static void layout_dev(struct pci_dev *dev)
11410 + *
11411 + * Layout memory and I/O for a device.
11412 + *
11413 + * Parameters:
11414 + *
11415 + * device - device to layout memory and I/O for.
11416 + */
11417 +
11418 +static void __init layout_dev(struct pci_dev *dev)
11419 +{
11420 + unsigned short cmd;
11421 + unsigned int base, mask, size, reg;
11422 + unsigned int alignto;
11423 + int i;
11424 +
11425 + /*
11426 + * Skip video cards if requested.
11427 + */
11428 + if (((dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA) ||
11429 + (dev->class >> 8 == PCI_CLASS_DISPLAY_VGA) ||
11430 + (dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)) && skip_vga){
11431 + printk("%s: VGA\n",__FUNCTION__);
11432 + return;
11433 + }
11434 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
11435 +
11436 + for (reg = PCI_BASE_ADDRESS_0, i = 0; reg <= PCI_BASE_ADDRESS_5; reg += 4, i++)
11437 + {
11438 + /*
11439 + * Figure out how much space and of what type this
11440 + * device wants.
11441 + */
11442 +
11443 + pci_write_config_dword(dev, reg, 0xffffffff);
11444 + pci_read_config_dword(dev, reg, &base);
11445 + if (!base)
11446 + {
11447 + /* this base-address register is unused */
11448 + dev->resource[i].start = 0;
11449 + dev->resource[i].end = 0;
11450 + dev->resource[i].flags = 0;
11451 + continue;
11452 + }
11453 +
11454 + /*
11455 + * We've read the base address register back after
11456 + * writing all ones and so now we must decode it.
11457 + */
11458 +
11459 + if (base & PCI_BASE_ADDRESS_SPACE_IO)
11460 + {
11461 + /*
11462 + * I/O space base address register.
11463 + */
11464 +
11465 + cmd |= PCI_COMMAND_IO;
11466 +
11467 + base &= PCI_BASE_ADDRESS_IO_MASK;
11468 + mask = (~base << 1) | 0x1;
11469 + size = (mask & base) & 0xffffffff;
11470 +
11471 + /*
11472 + * Align to multiple of size of minimum base.
11473 + */
11474 +
11475 +#ifdef CONFIG_COLDFIRE
11476 + alignto = MAX(PAGE_SIZE, size) ;
11477 +#else /* CONFIG_COLDFIRE */
11478 + alignto = MAX(0x040, size) ;
11479 +#endif /* CONFIG_COLDFIRE */
11480 + base = ALIGN(io_base, alignto);
11481 + io_base = base + size;
11482 + pci_write_config_dword(dev, reg, base | PCI_BASE_ADDRESS_SPACE_IO);
11483 +
11484 + dev->resource[i].start = base;
11485 + dev->resource[i].end = dev->resource[i].start + size - 1;
11486 + dev->resource[i].flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
11487 +
11488 + DBG_DEVS(("layout_dev: IO address: %x\n", base));
11489 + }
11490 + else
11491 + {
11492 + unsigned int type;
11493 +
11494 + /*
11495 + * Memory space base address register.
11496 + */
11497 +
11498 + cmd |= PCI_COMMAND_MEMORY;
11499 + type = base & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
11500 + base &= PCI_BASE_ADDRESS_MEM_MASK;
11501 + mask = (~base << 1) | 0x1;
11502 + size = (mask & base) & 0xffffffff;
11503 + switch (type)
11504 + {
11505 + case PCI_BASE_ADDRESS_MEM_TYPE_32:
11506 + case PCI_BASE_ADDRESS_MEM_TYPE_64:
11507 + break;
11508 +
11509 + case PCI_BASE_ADDRESS_MEM_TYPE_1M:
11510 + printk("bios32 WARNING: slot %d, function %d "
11511 + "requests memory below 1MB---don't "
11512 + "know how to do that.\n",
11513 + PCI_SLOT(dev->devfn),
11514 + PCI_FUNC(dev->devfn));
11515 + continue;
11516 + }
11517 + DBG_DEVS(("%s MEM: base %x,type %x,mask %x,size %x\n",
11518 + __FUNCTION__, base, type, mask, size));
11519 + /*
11520 + * Align to multiple of size of minimum base.
11521 + */
11522 +
11523 + alignto = max_t(unsigned int, 0x1000, size);
11524 + base = ALIGN(mem_base, alignto);
11525 + mem_base = base + size;
11526 + pci_write_config_dword(dev, reg, base);
11527 +
11528 + dev->resource[i].start = base;
11529 + dev->resource[i].end = dev->resource[i].start + size - 1;
11530 + dev->resource[i].flags = IORESOURCE_MEM;
11531 + DBG_DEVS(("%s MEM :base %x,size %x\n",
11532 + __FUNCTION__, base, size));
11533 + if (type == PCI_BASE_ADDRESS_MEM_TYPE_64)
11534 + {
11535 + /*
11536 + * 64-bit address, set the highest 32 bits
11537 + * to zero.
11538 + */
11539 +
11540 + reg += 4;
11541 + pci_write_config_dword(dev, reg, 0);
11542 +
11543 + i++;
11544 + dev->resource[i].start = 0;
11545 + dev->resource[i].end = 0;
11546 + dev->resource[i].flags = 0;
11547 + printk("%s:type == 64\n",__FUNCTION__);
11548 + }
11549 + }
11550 + }
11551 +
11552 + /*
11553 + * Enable device:
11554 + */
11555 +
11556 + if (dev->class >> 8 == PCI_CLASS_NOT_DEFINED ||
11557 + dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA ||
11558 + dev->class >> 8 == PCI_CLASS_DISPLAY_VGA ||
11559 + dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)
11560 + {
11561 + /*
11562 + * All of these (may) have I/O scattered all around
11563 + * and may not use i/o-base address registers at all.
11564 + * So we just have to always enable I/O to these
11565 + * devices.
11566 + */
11567 + cmd |= PCI_COMMAND_IO;
11568 + }
11569 +
11570 + pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER);
11571 +
11572 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, (disable_pci_burst) ? 0 : 32);
11573 +
11574 + if (bus_info != NULL)
11575 + bus_info->conf_device(dev); /* Machine dependent configuration. */
11576 +
11577 + printk(KERN_INFO "layout_dev: bus %d slot 0x%x VID 0x%x DID 0x%x class 0x%x\n",
11578 + dev->bus->number, PCI_SLOT(dev->devfn),
11579 + dev->vendor, dev->device, dev->class);
11580 +}
11581 +
11582 +/*
11583 + * static void layout_bus(struct pci_bus *bus)
11584 + *
11585 + * Layout memory and I/O for all devices on the given bus.
11586 + *
11587 + * Parameters:
11588 + *
11589 + * bus - bus.
11590 + */
11591 +
11592 +static void __init layout_bus(struct pci_bus *bus)
11593 +{
11594 + unsigned int bio, bmem;
11595 + struct pci_dev *dev;
11596 +
11597 + DBG_DEVS(("layout_bus: starting bus %d\n", bus->number));
11598 +
11599 + if (list_empty(&bus->devices) && list_empty(&bus->children))
11600 + return;
11601 +
11602 + /*
11603 + * Align the current bases on appropriate boundaries (4K for
11604 + * IO and 1MB for memory).
11605 + */
11606 +
11607 + bio = io_base = ALIGN(io_base, 4*KB);
11608 + bmem = mem_base = ALIGN(mem_base, 1*MB);
11609 +
11610 + /*
11611 + * PCI devices might have been setup by a PCI BIOS emulation
11612 + * running under TOS. In these cases there is a
11613 + * window during which two devices may have an overlapping
11614 + * address range. To avoid this causing trouble, we first
11615 + * turn off the I/O and memory address decoders for all PCI
11616 + * devices. They'll be re-enabled only once all address
11617 + * decoders are programmed consistently.
11618 + */
11619 +
11620 + DBG_DEVS(("layout_bus: disable_dev for bus %d\n", bus->number));
11621 +
11622 +#ifdef NL_ORIGINAL
11623 + for (dev = bus->devices; dev; dev = dev->sibling)
11624 +#else
11625 + dev = NULL;
11626 + while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL)
11627 +#endif
11628 + {
11629 + if ((dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) ||
11630 + (dev->class >> 8 == PCI_CLASS_BRIDGE_PCMCIA))
11631 + disable_dev(dev);
11632 + }
11633 +
11634 + /*
11635 + * Allocate space to each device:
11636 + */
11637 +
11638 + DBG_DEVS(("layout_bus: starting bus %d devices\n", bus->number));
11639 +
11640 +#ifdef NL_ORIGINAL
11641 + for (dev = bus->devices; dev; dev = dev->sibling)
11642 +#else
11643 + dev = NULL;
11644 + while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL)
11645 +#endif
11646 + {
11647 + if ((dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) ||
11648 + (dev->class >> 8 == PCI_CLASS_BRIDGE_PCMCIA))
11649 + layout_dev(dev);
11650 + }
11651 +
11652 + DBG_DEVS(("layout_bus: bus %d finished\n", bus->number));
11653 +}
11654 +
11655 +/*
11656 + * static void pcibios_fixup(void)
11657 + *
11658 + * Layout memory and I/O of all devices on the PCI bus if 'pci_modify' is
11659 + * true. This might be necessary because not every m68k machine with a PCI
11660 + * bus has a PCI BIOS. This function should be called right after
11661 + * pci_scan_bus() in pcibios_init().
11662 + */
11663 +
11664 +static void __init pcibios_fixup(void)
11665 +{
11666 + DBG_DEVS(("%s\n", __FUNCTION__));
11667 + if (pci_modify)
11668 + {
11669 + /*
11670 + * Set base addresses for allocation of I/O and memory space.
11671 + */
11672 +
11673 + io_base = bus_info->io_space.start + IO_ALLOC_OFFSET;
11674 + mem_base = bus_info->mem_space.start + MEM_ALLOC_OFFSET;
11675 +
11676 + /*
11677 + * Scan the tree, allocating PCI memory and I/O space.
11678 + */
11679 +
11680 +#ifdef NL_ORIGINAL
11681 + layout_bus(pci_bus_b(pci_root.next));
11682 +#else
11683 + layout_bus(pci_bus_b(pci_root_buses.next));
11684 +#endif
11685 + }
11686 +
11687 + /*
11688 + * Fix interrupt assignments, etc.
11689 + */
11690 +
11691 + bus_info->fixup(pci_modify);
11692 +}
11693 +
11694 +/*
11695 + * static void pcibios_claim_resources(struct pci_bus *bus)
11696 + *
11697 + * Claim all resources that are assigned to devices on the given bus.
11698 + *
11699 + * Parameters:
11700 + *
11701 + * bus - bus.
11702 + */
11703 +
11704 +static void __init pcibios_claim_resources(struct pci_bus *bus)
11705 +{
11706 + struct pci_dev *dev;
11707 + int i;
11708 + DBG_DEVS(("%s\n", __FUNCTION__));
11709 +#ifdef NL_ORIGINAL
11710 + while (bus)
11711 +#else
11712 + while ((bus = pci_find_next_bus(bus)) != NULL)
11713 +#endif
11714 + {
11715 +
11716 +#ifdef NL_ORIGINAL
11717 + for (dev = bus->devices; (dev != NULL); dev = dev->sibling)
11718 +#else
11719 + dev = NULL;
11720 + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL)
11721 +#endif
11722 + {
11723 + for (i = 0; i < PCI_NUM_RESOURCES; i++)
11724 + {
11725 + struct resource *r = &dev->resource[i];
11726 + struct resource *pr;
11727 + struct pci_bus_info *bus_info =
11728 + (struct pci_bus_info *) dev->sysdata;
11729 +
11730 + if ((r->start == 0) || (r->parent != NULL))
11731 + continue;
11732 +
11733 +#ifdef CONFIG_COLDFIRE
11734 + if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE)
11735 + continue;
11736 +#endif /* CONFIG_COLDFIRE */
11737 +#if 1
11738 + if (r->flags & IORESOURCE_IO)
11739 + pr = &bus_info->io_space;
11740 + else
11741 + pr = &bus_info->mem_space;
11742 +#else
11743 + if (r->flags & IORESOURCE_IO)
11744 + pr = &ioport_resource;
11745 + else
11746 + pr = &iomem_resource;
11747 +#endif
11748 + if (request_resource(pr, r) < 0)
11749 + {
11750 +#ifdef NL_ORIGINAL
11751 + DBG_DEVS(("PCI: Address space collision on "
11752 + "region %d of device %s\n", i, dev->name));
11753 +#else
11754 + printk("PCI: Address space collision on region %d of device %s\n", i, dev->dev.bus_id);
11755 +#endif
11756 + }
11757 + }
11758 + }
11759 +
11760 +#ifdef NL_ORIGINAL
11761 + if (bus->children)
11762 + pcibios_claim_resources(bus->children);
11763 +#else
11764 + if (!list_empty(&bus->children))
11765 + pcibios_claim_resources(pci_bus_b(bus->children.next));
11766 +#endif
11767 +
11768 +#ifdef NL_ORIGINAL
11769 + bus = bus->next;
11770 +#endif
11771 + }
11772 +}
11773 +
11774 +/*
11775 + * int pcibios_assign_resource(struct pci_dev *dev, int i)
11776 + *
11777 + * Assign a new address to a PCI resource.
11778 + *
11779 + * Parameters:
11780 + *
11781 + * dev - device.
11782 + * i - resource.
11783 + *
11784 + * Result: 0 if successful.
11785 + */
11786 +
11787 +int __init pcibios_assign_resource(struct pci_dev *dev, int i)
11788 +{
11789 + struct resource *r = &dev->resource[i];
11790 + struct resource *pr = pci_find_parent_resource(dev, r);
11791 + unsigned long size = r->end + 1;
11792 + DBG_DEVS(("%s:IO_ALLOC_OFFSET %x\n", __FUNCTION__, IO_ALLOC_OFFSET));
11793 + if (!pr)
11794 + return -EINVAL;
11795 +
11796 + if (r->flags & IORESOURCE_IO)
11797 + {
11798 + DBG_DEVS(("%s:IORESOURCE_IO:start %x, size %lx\n",
11799 + __FUNCTION__, bus_info->io_space.start, size));
11800 + if (size > 0x100)
11801 + return -EFBIG;
11802 +
11803 +#ifdef NL_ORIGINAL
11804 + if (allocate_resource(pr, r, size, bus_info->io_space.start +
11805 + IO_ALLOC_OFFSET, bus_info->io_space.end, 1024))
11806 +#else
11807 + if (allocate_resource(pr, r, size, bus_info->io_space.start +
11808 + IO_ALLOC_OFFSET, bus_info->io_space.end, 1024, NULL, NULL))
11809 +#endif
11810 + return -EBUSY;
11811 + }
11812 + else
11813 + {
11814 + DBG_DEVS(("%s:IORESOURCE_MEM:start %x, size %lx\n",
11815 + __FUNCTION__, bus_info->mem_space.start, size));
11816 +#ifdef NL_ORIGINAL
11817 + if (allocate_resource(pr, r, size, bus_info->mem_space.start +
11818 + MEM_ALLOC_OFFSET, bus_info->mem_space.end, size))
11819 +#else
11820 + if (allocate_resource(pr, r, size, bus_info->io_space.start +
11821 + IO_ALLOC_OFFSET, bus_info->io_space.end, 1024, NULL, NULL))
11822 +#endif
11823 + return -EBUSY;
11824 + }
11825 +
11826 + if (i < 6)
11827 + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, r->start);
11828 +
11829 + return 0;
11830 +}
11831 +
11832 +void pcibios_fixup_bus(struct pci_bus *bus)
11833 +{
11834 + struct pci_dev *dev;
11835 + void *sysdata;
11836 +
11837 + sysdata = (bus->parent) ? bus->parent->sysdata : bus->sysdata;
11838 +
11839 +#ifdef NL_ORIGINAL
11840 + for (dev = bus->devices; (dev != NULL); dev = dev->sibling)
11841 +#else
11842 + dev = NULL;
11843 + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL)
11844 +#endif
11845 + dev->sysdata = sysdata;
11846 +}
11847 +
11848 +int __init pcibios_init(void)
11849 +{
11850 + printk("Linux/m68k PCI BIOS32 revision %x.%02x\n", MAJOR_REV, MINOR_REV);
11851 +
11852 + bus_info = NULL;
11853 +#ifdef CONFIG_COLDFIRE
11854 + bus_info = init_coldfire_pci();
11855 +#endif /* CONFIG_COLDFIRE */
11856 +#ifdef CONFIG_HADES
11857 + if (MACH_IS_HADES)
11858 + bus_info = init_hades_pci();
11859 +#endif
11860 + if (bus_info != NULL)
11861 + {
11862 + printk("PCI: Probing PCI hardware\n");
11863 + pci_scan_bus(0, bus_info->m68k_pci_ops, bus_info);
11864 + pcibios_fixup();
11865 +#ifdef NL_ORIGINAL
11866 + pcibios_claim_resources(pci_root);
11867 +#else
11868 + pcibios_claim_resources(pci_bus_b(pci_root_buses.next));
11869 +#endif
11870 + }
11871 + else
11872 + printk("PCI: No PCI bus detected\n");
11873 + return 0;
11874 +}
11875 +
11876 +subsys_initcall(pcibios_init);
11877 +
11878 +char * pcibios_setup(char *str)
11879 +{
11880 + if (!strcmp(str, "nomodify"))
11881 + {
11882 + pci_modify = 0;
11883 + return NULL;
11884 + }
11885 + else if (!strcmp(str, "skipvga"))
11886 + {
11887 + skip_vga = 1;
11888 + return NULL;
11889 + }
11890 + else if (!strcmp(str, "noburst"))
11891 + {
11892 + disable_pci_burst = 1;
11893 + return NULL;
11894 + }
11895 +
11896 + return str;
11897 +}
11898 +#endif /* CONFIG_PCI */
11899 --- a/arch/m68k/kernel/dma.c
11900 +++ b/arch/m68k/kernel/dma.c
11901 @@ -11,12 +11,24 @@
11902 #include <linux/kernel.h>
11903 #include <linux/scatterlist.h>
11904 #include <linux/vmalloc.h>
11905 -
11906 +#include <linux/pci.h>
11907 #include <asm/pgalloc.h>
11908
11909 void *dma_alloc_coherent(struct device *dev, size_t size,
11910 dma_addr_t *handle, gfp_t flag)
11911 {
11912 +#if defined(CONFIG_M547X_8X) | defined(CONFIG_M54455)
11913 + /*
11914 + * On the M5445x platform the memory allocated with GFP_DMA
11915 + * is guaranteed to be DMA'able.
11916 + */
11917 + void *addr;
11918 +
11919 + size = PAGE_ALIGN(size);
11920 + addr = kmalloc(size, GFP_DMA);
11921 + *handle = virt_to_phys(addr);
11922 + return addr;
11923 +#else
11924 struct page *page, **map;
11925 pgprot_t pgprot;
11926 void *addr;
11927 @@ -55,6 +67,7 @@ void *dma_alloc_coherent(struct device *
11928 kfree(map);
11929
11930 return addr;
11931 +#endif
11932 }
11933 EXPORT_SYMBOL(dma_alloc_coherent);
11934
11935 @@ -62,7 +75,11 @@ void dma_free_coherent(struct device *de
11936 void *addr, dma_addr_t handle)
11937 {
11938 pr_debug("dma_free_coherent: %p, %x\n", addr, handle);
11939 +#if defined(CONFIG_M547X_8X) | defined(CONFIG_M54455)
11940 + kfree(addr);
11941 +#else
11942 vfree(addr);
11943 +#endif
11944 }
11945 EXPORT_SYMBOL(dma_free_coherent);
11946
11947 --- a/arch/m68k/kernel/Makefile
11948 +++ b/arch/m68k/kernel/Makefile
11949 @@ -2,19 +2,27 @@
11950 # Makefile for the linux kernel.
11951 #
11952
11953 -ifndef CONFIG_SUN3
11954 - extra-y := head.o
11955 +ifdef CONFIG_SUN3
11956 + extra-y := sun3-head.o vmlinux.lds
11957 + obj-y := entry.o signal.o ints.o
11958 else
11959 - extra-y := sun3-head.o
11960 +ifndef CONFIG_COLDFIRE
11961 + extra-y := head.o vmlinux.lds
11962 + obj-y := entry.o signal.o traps.o ints.o
11963 + obj-$(CONFIG_PCI) += bios32.o
11964 +else # CONFIG_COLDFIRE
11965 + extra-y := ../coldfire/head.o vmlinux.lds
11966 +ifdef CONFIG_M547X_8X
11967 + obj-$(CONFIG_PCI) += bios32_mcf548x.o
11968 +endif
11969 +endif
11970 endif
11971 -extra-y += vmlinux.lds
11972
11973 -obj-y := entry.o process.o traps.o ints.o signal.o ptrace.o module.o \
11974 +obj-y += process.o ptrace.o module.o \
11975 sys_m68k.o time.o semaphore.o setup.o m68k_ksyms.o devres.o
11976
11977 devres-y = ../../../kernel/irq/devres.o
11978
11979 -obj-$(CONFIG_PCI) += bios32.o
11980 obj-y$(CONFIG_MMU_SUN3) += dma.o # no, it's not a typo
11981
11982 EXTRA_AFLAGS := -traditional
11983 --- a/arch/m68k/kernel/process.c
11984 +++ b/arch/m68k/kernel/process.c
11985 @@ -191,6 +191,7 @@ EXPORT_SYMBOL(kernel_thread);
11986
11987 void flush_thread(void)
11988 {
11989 +#if !defined(CONFIG_COLDFIRE)
11990 unsigned long zero = 0;
11991 set_fs(USER_DS);
11992 current->thread.fs = __USER_DS;
11993 @@ -198,6 +199,14 @@ void flush_thread(void)
11994 asm volatile (".chip 68k/68881\n\t"
11995 "frestore %0@\n\t"
11996 ".chip 68k" : : "a" (&zero));
11997 +#else
11998 + set_fs(USER_DS);
11999 + current->thread.fs = USER_DS;
12000 +#if defined(CONFIG_FPU)
12001 + if (!FPU_IS_EMU)
12002 + asm volatile ("frestore %0@\n\t" : : "a" (&zero));
12003 +#endif
12004 +#endif
12005 }
12006
12007 /*
12008 @@ -261,6 +270,7 @@ int copy_thread(int nr, unsigned long cl
12009 * Must save the current SFC/DFC value, NOT the value when
12010 * the parent was last descheduled - RGH 10-08-96
12011 */
12012 +#if !defined(CONFIG_COLDFIRE)
12013 p->thread.fs = get_fs().seg;
12014
12015 if (!FPU_IS_EMU) {
12016 @@ -272,9 +282,34 @@ int copy_thread(int nr, unsigned long cl
12017 "fmoveml %/fpiar/%/fpcr/%/fpsr,%1"
12018 : : "m" (p->thread.fp[0]), "m" (p->thread.fpcntl[0])
12019 : "memory");
12020 +#else
12021 + p->thread.fs = get_fs();
12022 +
12023 +#if defined(CONFIG_FPU)
12024 + if (!FPU_IS_EMU) {
12025 + /* Copy the current fpu state */
12026 + asm volatile ("fsave %0" : : "m" (p->thread.fpstate[0])
12027 + : "memory");
12028 +
12029 + if (p->thread.fpstate[0]) {
12030 + asm volatile ("fmovemd %/fp0-%/fp7,%0"
12031 + : : "m" (p->thread.fp[0])
12032 + : "memory");
12033 + asm volatile ("fmovel %/fpiar,%0"
12034 + : : "m" (p->thread.fpcntl[0])
12035 + : "memory");
12036 + asm volatile ("fmovel %/fpcr,%0"
12037 + : : "m" (p->thread.fpcntl[1])
12038 + : "memory");
12039 + asm volatile ("fmovel %/fpsr,%0"
12040 + : : "m" (p->thread.fpcntl[2])
12041 + : "memory");
12042 + }
12043 /* Restore the state in case the fpu was busy */
12044 asm volatile ("frestore %0" : : "m" (p->thread.fpstate[0]));
12045 }
12046 +#endif
12047 +#endif
12048
12049 return 0;
12050 }
12051 @@ -283,7 +318,9 @@ int copy_thread(int nr, unsigned long cl
12052
12053 int dump_fpu (struct pt_regs *regs, struct user_m68kfp_struct *fpu)
12054 {
12055 +#if !defined(CONFIG_COLDFIRE) || defined(CONFIG_FPU)
12056 char fpustate[216];
12057 +#endif
12058
12059 if (FPU_IS_EMU) {
12060 int i;
12061 @@ -300,6 +337,7 @@ int dump_fpu (struct pt_regs *regs, stru
12062 }
12063
12064 /* First dump the fpu context to avoid protocol violation. */
12065 +#if !defined(CONFIG_COLDFIRE)
12066 asm volatile ("fsave %0" :: "m" (fpustate[0]) : "memory");
12067 if (!CPU_IS_060 ? !fpustate[0] : !fpustate[2])
12068 return 0;
12069 @@ -310,6 +348,25 @@ int dump_fpu (struct pt_regs *regs, stru
12070 asm volatile ("fmovemx %/fp0-%/fp7,%0"
12071 :: "m" (fpu->fpregs[0])
12072 : "memory");
12073 +#elif defined(CONFIG_FPU)
12074 + asm volatile ("fsave %0" :: "m" (fpustate[0]) : "memory");
12075 + if (!CPU_IS_060 ? !fpustate[0] : !fpustate[2])
12076 + return 0;
12077 +
12078 + asm volatile ("fmovel %/fpiar,%0"
12079 + : : "m" (fpu->fpcntl[0])
12080 + : "memory");
12081 + asm volatile ("fmovel %/fpcr,%0"
12082 + : : "m" (fpu->fpcntl[1])
12083 + : "memory");
12084 + asm volatile ("fmovel %/fpsr,%0"
12085 + : : "m" (fpu->fpcntl[2])
12086 + : "memory");
12087 + asm volatile ("fmovemd %/fp0-%/fp7,%0"
12088 + : : "m" (fpu->fpregs[0])
12089 + : "memory");
12090 +#endif
12091 +
12092 return 1;
12093 }
12094 EXPORT_SYMBOL(dump_fpu);
12095 --- a/arch/m68k/kernel/setup.c
12096 +++ b/arch/m68k/kernel/setup.c
12097 @@ -67,13 +67,22 @@ EXPORT_SYMBOL(m68k_memory);
12098
12099 struct mem_info m68k_ramdisk;
12100
12101 +#if !defined(CONFIG_COLDFIRE)
12102 static char m68k_command_line[CL_SIZE];
12103 +#else
12104 +char m68k_command_line[CL_SIZE];
12105 +unsigned long uboot_info_stk;
12106 +EXPORT_SYMBOL(uboot_info_stk);
12107 +#endif
12108
12109 void (*mach_sched_init) (irq_handler_t handler) __initdata = NULL;
12110 /* machine dependent irq functions */
12111 void (*mach_init_IRQ) (void) __initdata = NULL;
12112 void (*mach_get_model) (char *model);
12113 int (*mach_get_hardware_list) (char *buffer);
12114 +#ifdef CONFIG_COLDFIRE
12115 +void (*mach_tick)(void);
12116 +#endif
12117 /* machine dependent timer functions */
12118 unsigned long (*mach_gettimeoffset) (void);
12119 int (*mach_hwclk) (int, struct rtc_time*);
12120 @@ -128,13 +137,17 @@ extern void config_hp300(void);
12121 extern void config_q40(void);
12122 extern void config_sun3x(void);
12123
12124 +#ifdef CONFIG_COLDFIRE
12125 +void coldfire_sort_memrec(void);
12126 +#endif
12127 +
12128 #define MASK_256K 0xfffc0000
12129
12130 extern void paging_init(void);
12131
12132 static void __init m68k_parse_bootinfo(const struct bi_record *record)
12133 {
12134 - while (record->tag != BI_LAST) {
12135 + while ((record->tag != BI_LAST) && !(CONFIG_COLDFIRE)) {
12136 int unknown = 0;
12137 const unsigned long *data = record->data;
12138
12139 @@ -192,7 +205,11 @@ static void __init m68k_parse_bootinfo(c
12140 record->size);
12141 }
12142
12143 - m68k_realnum_memory = m68k_num_memory;
12144 +#ifdef CONFIG_COLDFIRE
12145 + coldfire_sort_memrec();
12146 +#endif
12147 +
12148 + m68k_realnum_memory = m68k_num_memory;
12149 #ifdef CONFIG_SINGLE_MEMORY_CHUNK
12150 if (m68k_num_memory > 1) {
12151 printk("Ignoring last %i chunks of physical memory\n",
12152 @@ -205,7 +222,9 @@ static void __init m68k_parse_bootinfo(c
12153 void __init setup_arch(char **cmdline_p)
12154 {
12155 extern int _etext, _edata, _end;
12156 +#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
12157 int i;
12158 +#endif
12159
12160 /* The bootinfo is located right after the kernel bss */
12161 m68k_parse_bootinfo((const struct bi_record *)&_end);
12162 @@ -220,9 +239,10 @@ void __init setup_arch(char **cmdline_p)
12163 * We should really do our own FPU check at startup.
12164 * [what do we do with buggy 68LC040s? if we have problems
12165 * with them, we should add a test to check_bugs() below] */
12166 -#ifndef CONFIG_M68KFPU_EMU_ONLY
12167 +#if !defined(CONFIG_M68KFPU_EMU_ONLY) && defined(CONFIG_FPU)
12168 /* clear the fpu if we have one */
12169 - if (m68k_fputype & (FPU_68881|FPU_68882|FPU_68040|FPU_68060)) {
12170 + if (m68k_fputype & (FPU_68881|FPU_68882|FPU_68040|FPU_68060|
12171 + FPU_CFV4E)) {
12172 volatile int zero = 0;
12173 asm volatile ("frestore %0" : : "m" (zero));
12174 }
12175 @@ -310,13 +330,18 @@ void __init setup_arch(char **cmdline_p)
12176 config_sun3x();
12177 break;
12178 #endif
12179 +#ifdef CONFIG_COLDFIRE
12180 + case MACH_CFMMU:
12181 + config_coldfire();
12182 + break;
12183 +#endif
12184 default:
12185 panic("No configuration setup");
12186 }
12187
12188 paging_init();
12189
12190 -#ifndef CONFIG_SUN3
12191 +#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
12192 for (i = 1; i < m68k_num_memory; i++)
12193 free_bootmem_node(NODE_DATA(i), m68k_memory[i].addr,
12194 m68k_memory[i].size);
12195 @@ -343,6 +368,10 @@ void __init setup_arch(char **cmdline_p)
12196
12197 #endif /* !CONFIG_SUN3 */
12198
12199 +#ifdef CONFIG_COLDFIRE
12200 + mmu_context_init();
12201 +#endif
12202 +
12203 /* set ISA defs early as possible */
12204 #if defined(CONFIG_ISA) && defined(MULTI_ISA)
12205 #if defined(CONFIG_Q40)
12206 @@ -373,6 +402,7 @@ static int show_cpuinfo(struct seq_file
12207 #define LOOP_CYCLES_68030 (8)
12208 #define LOOP_CYCLES_68040 (3)
12209 #define LOOP_CYCLES_68060 (1)
12210 +#define LOOP_CYCLES_COLDFIRE (2)
12211
12212 if (CPU_IS_020) {
12213 cpu = "68020";
12214 @@ -386,6 +416,9 @@ static int show_cpuinfo(struct seq_file
12215 } else if (CPU_IS_060) {
12216 cpu = "68060";
12217 clockfactor = LOOP_CYCLES_68060;
12218 + } else if (CPU_IS_CFV4E) {
12219 + cpu = "ColdFire V4e";
12220 + clockfactor = LOOP_CYCLES_COLDFIRE;
12221 } else {
12222 cpu = "680x0";
12223 clockfactor = 0;
12224 @@ -404,6 +437,8 @@ static int show_cpuinfo(struct seq_file
12225 fpu = "68060";
12226 else if (m68k_fputype & FPU_SUNFPA)
12227 fpu = "Sun FPA";
12228 + else if (m68k_fputype & FPU_CFV4E)
12229 + fpu = "ColdFire V4e";
12230 else
12231 fpu = "none";
12232 #endif
12233 @@ -420,6 +455,8 @@ static int show_cpuinfo(struct seq_file
12234 mmu = "Sun-3";
12235 else if (m68k_mmutype & MMU_APOLLO)
12236 mmu = "Apollo";
12237 + else if (m68k_mmutype & MMU_CFV4E)
12238 + mmu = "ColdFire";
12239 else
12240 mmu = "unknown";
12241
12242 @@ -482,7 +519,7 @@ int get_hardware_list(char *buffer)
12243
12244 void check_bugs(void)
12245 {
12246 -#ifndef CONFIG_M68KFPU_EMU
12247 +#if !defined(CONFIG_M68KFPU_EMU) && !defined(CONFIG_M5445X)
12248 if (m68k_fputype == 0) {
12249 printk(KERN_EMERG "*** YOU DO NOT HAVE A FLOATING POINT UNIT, "
12250 "WHICH IS REQUIRED BY LINUX/M68K ***\n");
12251 --- a/arch/m68k/kernel/sys_m68k.c
12252 +++ b/arch/m68k/kernel/sys_m68k.c
12253 @@ -29,6 +29,9 @@
12254 #include <asm/traps.h>
12255 #include <asm/page.h>
12256 #include <asm/unistd.h>
12257 +#ifdef CONFIG_COLDFIRE
12258 +#include <asm/cacheflush.h>
12259 +#endif
12260
12261 /*
12262 * sys_pipe() is the normal C calling standard for creating
12263 @@ -257,6 +260,7 @@ asmlinkage int sys_ipc (uint call, int f
12264 return -EINVAL;
12265 }
12266
12267 +#ifndef CONFIG_COLDFIRE
12268 /* Convert virtual (user) address VADDR to physical address PADDR */
12269 #define virt_to_phys_040(vaddr) \
12270 ({ \
12271 @@ -580,6 +584,7 @@ cache_flush_060 (unsigned long addr, int
12272 }
12273 return 0;
12274 }
12275 +#endif /* CONFIG_COLDFIRE */
12276
12277 /* sys_cacheflush -- flush (part of) the processor cache. */
12278 asmlinkage int
12279 @@ -612,6 +617,7 @@ sys_cacheflush (unsigned long addr, int
12280 goto out;
12281 }
12282
12283 +#ifndef CONFIG_COLDFIRE
12284 if (CPU_IS_020_OR_030) {
12285 if (scope == FLUSH_SCOPE_LINE && len < 256) {
12286 unsigned long cacr;
12287 @@ -656,6 +662,16 @@ sys_cacheflush (unsigned long addr, int
12288 ret = cache_flush_060 (addr, scope, cache, len);
12289 }
12290 }
12291 +#else /* CONFIG_COLDFIRE */
12292 + if ((cache & FLUSH_CACHE_INSN) && (cache & FLUSH_CACHE_DATA))
12293 + flush_bcache();
12294 + else if (cache & FLUSH_CACHE_INSN)
12295 + flush_icache();
12296 + else
12297 + flush_dcache();
12298 +
12299 + ret = 0;
12300 +#endif /* CONFIG_COLDFIRE */
12301 out:
12302 unlock_kernel();
12303 return ret;
12304 --- a/arch/m68k/kernel/time.c
12305 +++ b/arch/m68k/kernel/time.c
12306 @@ -40,6 +40,11 @@ static inline int set_rtc_mmss(unsigned
12307 */
12308 static irqreturn_t timer_interrupt(int irq, void *dummy)
12309 {
12310 +#ifdef CONFIG_COLDFIRE
12311 + /* kick hardware timer if necessary */
12312 + if (mach_tick)
12313 + mach_tick();
12314 +#endif
12315 do_timer(1);
12316 #ifndef CONFIG_SMP
12317 update_process_times(user_mode(get_irq_regs()));
12318 --- a/arch/m68k/kernel/vmlinux.lds.S
12319 +++ b/arch/m68k/kernel/vmlinux.lds.S
12320 @@ -1,10 +1,13 @@
12321 PHDRS
12322 {
12323 - text PT_LOAD FILEHDR PHDRS FLAGS (7);
12324 + headers PT_PHDR PHDRS ;
12325 + text PT_LOAD FILEHDR PHDRS FLAGS (5);
12326 data PT_LOAD FLAGS (7);
12327 }
12328 #ifdef CONFIG_SUN3
12329 #include "vmlinux-sun3.lds"
12330 +#elif CONFIG_COLDFIRE
12331 +#include "../coldfire/vmlinux-cf.lds"
12332 #else
12333 #include "vmlinux-std.lds"
12334 #endif
12335 --- a/arch/m68k/lib/checksum.c
12336 +++ b/arch/m68k/lib/checksum.c
12337 @@ -39,8 +39,131 @@
12338 * computes a partial checksum, e.g. for TCP/UDP fragments
12339 */
12340
12341 +#ifdef CONFIG_COLDFIRE
12342 +
12343 +static inline unsigned short from32to16(unsigned long x)
12344 +{
12345 + /* add up 16-bit and 16-bit for 16+c bit */
12346 + x = (x & 0xffff) + (x >> 16);
12347 + /* add up carry.. */
12348 + x = (x & 0xffff) + (x >> 16);
12349 + return x;
12350 +}
12351 +
12352 +static unsigned long do_csum(const unsigned char *buff, int len)
12353 +{
12354 + int odd, count;
12355 + unsigned long result = 0;
12356 +
12357 + if (len <= 0)
12358 + goto out;
12359 + odd = 1 & (unsigned long) buff;
12360 + if (odd) {
12361 + result = *buff;
12362 + len--;
12363 + buff++;
12364 + }
12365 + count = len >> 1; /* nr of 16-bit words.. */
12366 + if (count) {
12367 + if (2 & (unsigned long) buff) {
12368 + result += *(unsigned short *) buff;
12369 + count--;
12370 + len -= 2;
12371 + buff += 2;
12372 + }
12373 + count >>= 1; /* nr of 32-bit words.. */
12374 + if (count) {
12375 + unsigned long carry = 0;
12376 + do {
12377 + unsigned long w = *(unsigned long *) buff;
12378 + count--;
12379 + buff += 4;
12380 + result += carry;
12381 + result += w;
12382 + carry = (w > result);
12383 + } while (count);
12384 + result += carry;
12385 + result = (result & 0xffff) + (result >> 16);
12386 + }
12387 + if (len & 2) {
12388 + result += *(unsigned short *) buff;
12389 + buff += 2;
12390 + }
12391 + }
12392 + if (len & 1)
12393 + result += (*buff << 8);
12394 + result = from32to16(result);
12395 + if (odd)
12396 + result = ((result >> 8) & 0xff) | ((result & 0xff) << 8);
12397 +out:
12398 + return result;
12399 +}
12400 +
12401 +/*
12402 + * This is a version of ip_compute_csum() optimized for IP headers,
12403 + * which always checksum on 4 octet boundaries.
12404 + */
12405 +__sum16 ip_fast_csum(const void *iph, unsigned int ihl)
12406 +{
12407 + return ~do_csum(iph, ihl*4);
12408 +}
12409 +EXPORT_SYMBOL(ip_fast_csum);
12410 +
12411 +/*
12412 + * computes the checksum of a memory block at buff, length len,
12413 + * and adds in "sum" (32-bit)
12414 + *
12415 + * returns a 32-bit number suitable for feeding into itself
12416 + * or csum_tcpudp_magic
12417 + *
12418 + * this function must be called with even lengths, except
12419 + * for the last fragment, which may be odd
12420 + *
12421 + * it's best to have buff aligned on a 32-bit boundary
12422 + */
12423 __wsum csum_partial(const void *buff, int len, __wsum sum)
12424 {
12425 + unsigned int result = do_csum(buff, len);
12426 +
12427 + /* add in old sum, and carry.. */
12428 + result += sum;
12429 + if (sum > result)
12430 + result += 1;
12431 + return result;
12432 +}
12433 +EXPORT_SYMBOL(csum_partial);
12434 +
12435 +/*
12436 + * copy from fs while checksumming, otherwise like csum_partial
12437 + */
12438 +
12439 +__wsum
12440 +csum_partial_copy_from_user(const void __user *src, void *dst, int len,
12441 + __wsum sum, int *csum_err)
12442 +{
12443 + if (csum_err) *csum_err = 0;
12444 + memcpy(dst, src, len);
12445 + return csum_partial(dst, len, sum);
12446 +}
12447 +EXPORT_SYMBOL(csum_partial_copy_from_user);
12448 +
12449 +/*
12450 + * copy from ds while checksumming, otherwise like csum_partial
12451 + */
12452 +
12453 +__wsum
12454 +csum_partial_copy_nocheck(const void *src, void *dst, int len, __wsum sum)
12455 +{
12456 + memcpy(dst, src, len);
12457 + return csum_partial(dst, len, sum);
12458 +}
12459 +EXPORT_SYMBOL(csum_partial_copy_nocheck);
12460 +
12461 +#else /* !CONFIG_COLDFIRE */
12462 +
12463 +unsigned int
12464 +csum_partial(const unsigned char *buff, int len, unsigned int sum)
12465 +{
12466 unsigned long tmp1, tmp2;
12467 /*
12468 * Experiments with ethernet and slip connections show that buff
12469 @@ -423,3 +546,4 @@ csum_partial_copy_nocheck(const void *sr
12470 return(sum);
12471 }
12472 EXPORT_SYMBOL(csum_partial_copy_nocheck);
12473 +#endif /* CONFIG_COLDFIRE */
12474 --- a/arch/m68k/lib/muldi3.c
12475 +++ b/arch/m68k/lib/muldi3.c
12476 @@ -21,12 +21,22 @@ Boston, MA 02111-1307, USA. */
12477
12478 #define BITS_PER_UNIT 8
12479
12480 +#ifdef CONFIG_COLDFIRE
12481 +#define umul_ppmm(w1, w0, u, v) \
12482 + do { \
12483 + unsigned long long x; \
12484 + x = (unsigned long long)u * v; \
12485 + w0 = (unsigned long)(x & 0x00000000ffffffff); \
12486 + w1 = (unsigned long)(x & 0xffffffff00000000) >> 32; \
12487 + } while (0)
12488 +#else /* CONFIG_COLDFIRE */
12489 #define umul_ppmm(w1, w0, u, v) \
12490 __asm__ ("mulu%.l %3,%1:%0" \
12491 : "=d" ((USItype)(w0)), \
12492 "=d" ((USItype)(w1)) \
12493 : "%0" ((USItype)(u)), \
12494 "dmi" ((USItype)(v)))
12495 +#endif /* CONFIG_COLDFIRE */
12496
12497 #define __umulsidi3(u, v) \
12498 ({DIunion __w; \
12499 --- a/arch/m68k/lib/semaphore.S
12500 +++ b/arch/m68k/lib/semaphore.S
12501 @@ -16,11 +16,24 @@
12502 * there is contention on the semaphore.
12503 */
12504 ENTRY(__down_failed)
12505 +#ifndef CONFIG_COLDFIRE
12506 moveml %a0/%d0/%d1,-(%sp)
12507 +#else
12508 + movel %a0,-(%sp)
12509 + movel %d0,-(%sp)
12510 + movel %d1,-(%sp)
12511 +#endif
12512 movel %a1,-(%sp)
12513 jbsr __down
12514 movel (%sp)+,%a1
12515 +#ifndef CONFIG_COLDFIRE
12516 moveml (%sp)+,%a0/%d0/%d1
12517 +#else
12518 + movel (%sp)+,%d1
12519 + movel (%sp)+,%d0
12520 + movel (%sp)+,%a0
12521 +#endif
12522 +
12523 rts
12524
12525 ENTRY(__down_failed_interruptible)
12526 @@ -44,10 +57,22 @@ ENTRY(__down_failed_trylock)
12527 rts
12528
12529 ENTRY(__up_wakeup)
12530 +#ifndef CONFIG_COLDFIRE
12531 moveml %a0/%d0/%d1,-(%sp)
12532 +#else
12533 + movel %a0,-(%sp)
12534 + movel %d0,-(%sp)
12535 + movel %d1,-(%sp)
12536 +#endif
12537 movel %a1,-(%sp)
12538 jbsr __up
12539 movel (%sp)+,%a1
12540 +#ifndef CONFIG_COLDFIRE
12541 moveml (%sp)+,%a0/%d0/%d1
12542 +#else
12543 + movel (%sp)+,%d1
12544 + movel (%sp)+,%d0
12545 + movel (%sp)+,%a0
12546 +#endif
12547 rts
12548
12549 --- a/arch/m68k/lib/string.c
12550 +++ b/arch/m68k/lib/string.c
12551 @@ -15,6 +15,7 @@ char *strcpy(char *dest, const char *src
12552 }
12553 EXPORT_SYMBOL(strcpy);
12554
12555 +#ifndef CONFIG_COLDFIRE
12556 void *memset(void *s, int c, size_t count)
12557 {
12558 void *xs = s;
12559 @@ -143,6 +144,69 @@ void *memcpy(void *to, const void *from,
12560 }
12561 EXPORT_SYMBOL(memcpy);
12562
12563 +#else /* CONFIG_COLDFIRE */
12564 +
12565 +void *memset(void *s, int c, size_t count)
12566 +{
12567 + unsigned long x;
12568 + void *originalTo;
12569 +
12570 + for (x = 0; x < count; x++)
12571 + *(unsigned char *)s++ = (unsigned char)c;
12572 +
12573 + return originalTo;
12574 +}
12575 +EXPORT_SYMBOL(memset);
12576 +
12577 +void *memcpy(void *to, const void *from, size_t n)
12578 +{
12579 + void *xto = to;
12580 + size_t temp;
12581 +
12582 + if (!n)
12583 + return xto;
12584 + if ((long) to & 1) {
12585 + char *cto = to;
12586 + const char *cfrom = from;
12587 + *cto++ = *cfrom++;
12588 + to = cto;
12589 + from = cfrom;
12590 + n--;
12591 + }
12592 + if (n > 2 && (long) to & 2) {
12593 + short *sto = to;
12594 + const short *sfrom = from;
12595 + *sto++ = *sfrom++;
12596 + to = sto;
12597 + from = sfrom;
12598 + n -= 2;
12599 + }
12600 + temp = n >> 2;
12601 + if (temp) {
12602 + long *lto = to;
12603 + const long *lfrom = from;
12604 + for (; temp; temp--)
12605 + *lto++ = *lfrom++;
12606 + to = lto;
12607 + from = lfrom;
12608 + }
12609 + if (n & 2) {
12610 + short *sto = to;
12611 + const short *sfrom = from;
12612 + *sto++ = *sfrom++;
12613 + to = sto;
12614 + from = sfrom;
12615 + }
12616 + if (n & 1) {
12617 + char *cto = to;
12618 + const char *cfrom = from;
12619 + *cto = *cfrom;
12620 + }
12621 + return xto;
12622 +}
12623 +EXPORT_SYMBOL(memcpy);
12624 +#endif /* CONFIG_COLDFIRE */
12625 +
12626 void *memmove(void *dest, const void *src, size_t n)
12627 {
12628 void *xdest = dest;
12629 --- a/arch/m68k/lib/uaccess.c
12630 +++ b/arch/m68k/lib/uaccess.c
12631 @@ -5,6 +5,7 @@
12632 */
12633
12634 #include <linux/module.h>
12635 +#ifndef CONFIG_COLDFIRE
12636 #include <asm/uaccess.h>
12637
12638 unsigned long __generic_copy_from_user(void *to, const void __user *from,
12639 @@ -220,3 +221,244 @@ unsigned long __clear_user(void __user *
12640 return res;
12641 }
12642 EXPORT_SYMBOL(__clear_user);
12643 +
12644 +#else /* CONFIG_COLDFIRE */
12645 +
12646 +#include <asm/cf_uaccess.h>
12647 +
12648 +unsigned long __generic_copy_from_user(void *to, const void *from,
12649 + unsigned long n)
12650 +{
12651 + unsigned long tmp;
12652 + __asm__ __volatile__
12653 + (" tstl %2\n"
12654 + " jeq 2f\n"
12655 + "1: movel (%1)+,%3\n"
12656 + " movel %3,(%0)+\n"
12657 + " subql #1,%2\n"
12658 + " jne 1b\n"
12659 + "2: movel %4,%2\n"
12660 + " bclr #1,%2\n"
12661 + " jeq 4f\n"
12662 + "3: movew (%1)+,%3\n"
12663 + " movew %3,(%0)+\n"
12664 + "4: bclr #0,%2\n"
12665 + " jeq 6f\n"
12666 + "5: moveb (%1)+,%3\n"
12667 + " moveb %3,(%0)+\n"
12668 + "6:\n"
12669 + ".section .fixup,\"ax\"\n"
12670 + " .even\n"
12671 + "7: movel %2,%%d0\n"
12672 + "71:clrl (%0)+\n"
12673 + " subql #1,%%d0\n"
12674 + " jne 71b\n"
12675 + " lsll #2,%2\n"
12676 + " addl %4,%2\n"
12677 + " btst #1,%4\n"
12678 + " jne 81f\n"
12679 + " btst #0,%4\n"
12680 + " jne 91f\n"
12681 + " jra 6b\n"
12682 + "8: addql #2,%2\n"
12683 + "81:clrw (%0)+\n"
12684 + " btst #0,%4\n"
12685 + " jne 91f\n"
12686 + " jra 6b\n"
12687 + "9: addql #1,%2\n"
12688 + "91:clrb (%0)+\n"
12689 + " jra 6b\n"
12690 + ".previous\n"
12691 + ".section __ex_table,\"a\"\n"
12692 + " .align 4\n"
12693 + " .long 1b,7b\n"
12694 + " .long 3b,8b\n"
12695 + " .long 5b,9b\n"
12696 + ".previous"
12697 + : "=a"(to), "=a"(from), "=d"(n), "=&d"(tmp)
12698 + : "d"(n & 3), "0"(to), "1"(from), "2"(n/4)
12699 + : "d0", "memory");
12700 + return n;
12701 +}
12702 +EXPORT_SYMBOL(__generic_copy_from_user);
12703 +
12704 +
12705 +unsigned long __generic_copy_to_user(void *to, const void *from,
12706 + unsigned long n)
12707 +{
12708 + unsigned long tmp;
12709 + __asm__ __volatile__
12710 + (" tstl %2\n"
12711 + " jeq 3f\n"
12712 + "1: movel (%1)+,%3\n"
12713 + "22:movel %3,(%0)+\n"
12714 + "2: subql #1,%2\n"
12715 + " jne 1b\n"
12716 + "3: movel %4,%2\n"
12717 + " bclr #1,%2\n"
12718 + " jeq 4f\n"
12719 + " movew (%1)+,%3\n"
12720 + "24:movew %3,(%0)+\n"
12721 + "4: bclr #0,%2\n"
12722 + " jeq 5f\n"
12723 + " moveb (%1)+,%3\n"
12724 + "25:moveb %3,(%0)+\n"
12725 + "5:\n"
12726 + ".section .fixup,\"ax\"\n"
12727 + " .even\n"
12728 + "60:addql #1,%2\n"
12729 + "6: lsll #2,%2\n"
12730 + " addl %4,%2\n"
12731 + " jra 5b\n"
12732 + "7: addql #2,%2\n"
12733 + " jra 5b\n"
12734 + "8: addql #1,%2\n"
12735 + " jra 5b\n"
12736 + ".previous\n"
12737 + ".section __ex_table,\"a\"\n"
12738 + " .align 4\n"
12739 + " .long 1b,60b\n"
12740 + " .long 22b,6b\n"
12741 + " .long 2b,6b\n"
12742 + " .long 24b,7b\n"
12743 + " .long 3b,60b\n"
12744 + " .long 4b,7b\n"
12745 + " .long 25b,8b\n"
12746 + " .long 5b,8b\n"
12747 + ".previous"
12748 + : "=a"(to), "=a"(from), "=d"(n), "=&d"(tmp)
12749 + : "r"(n & 3), "0"(to), "1"(from), "2"(n / 4)
12750 + : "memory");
12751 + return n;
12752 +}
12753 +EXPORT_SYMBOL(__generic_copy_to_user);
12754 +
12755 +/*
12756 + * Copy a null terminated string from userspace.
12757 + */
12758 +
12759 +long strncpy_from_user(char *dst, const char *src, long count)
12760 +{
12761 + long res = -EFAULT;
12762 + if (!(access_ok(VERIFY_READ, src, 1))) /* --tym-- */
12763 + return res;
12764 + if (count == 0) return count;
12765 + __asm__ __volatile__
12766 + ("1: moveb (%2)+,%%d0\n"
12767 + "12:moveb %%d0,(%1)+\n"
12768 + " jeq 2f\n"
12769 + " subql #1,%3\n"
12770 + " jne 1b\n"
12771 + "2: subl %3,%0\n"
12772 + "3:\n"
12773 + ".section .fixup,\"ax\"\n"
12774 + " .even\n"
12775 + "4: movel %4,%0\n"
12776 + " jra 3b\n"
12777 + ".previous\n"
12778 + ".section __ex_table,\"a\"\n"
12779 + " .align 4\n"
12780 + " .long 1b,4b\n"
12781 + " .long 12b,4b\n"
12782 + ".previous"
12783 + : "=d"(res), "=a"(dst), "=a"(src), "=d"(count)
12784 + : "i"(-EFAULT), "0"(count), "1"(dst), "2"(src), "3"(count)
12785 + : "d0", "memory");
12786 + return res;
12787 +}
12788 +EXPORT_SYMBOL(strncpy_from_user);
12789 +
12790 +/*
12791 + * Return the size of a string (including the ending 0)
12792 + *
12793 + * Return 0 on exception, a value greater than N if too long
12794 + */
12795 +long strnlen_user(const char *src, long n)
12796 +{
12797 + long res = -EFAULT;
12798 + if (!(access_ok(VERIFY_READ, src, 1))) /* --tym-- */
12799 + return res;
12800 +
12801 + res = -(long)src;
12802 + __asm__ __volatile__
12803 + ("1:\n"
12804 + " tstl %2\n"
12805 + " jeq 3f\n"
12806 + "2: moveb (%1)+,%%d0\n"
12807 + "22:\n"
12808 + " subql #1,%2\n"
12809 + " tstb %%d0\n"
12810 + " jne 1b\n"
12811 + " jra 4f\n"
12812 + "3:\n"
12813 + " addql #1,%0\n"
12814 + "4:\n"
12815 + " addl %1,%0\n"
12816 + "5:\n"
12817 + ".section .fixup,\"ax\"\n"
12818 + " .even\n"
12819 + "6: moveq %3,%0\n"
12820 + " jra 5b\n"
12821 + ".previous\n"
12822 + ".section __ex_table,\"a\"\n"
12823 + " .align 4\n"
12824 + " .long 2b,6b\n"
12825 + " .long 22b,6b\n"
12826 + ".previous"
12827 + : "=d"(res), "=a"(src), "=d"(n)
12828 + : "i"(0), "0"(res), "1"(src), "2"(n)
12829 + : "d0");
12830 + return res;
12831 +}
12832 +EXPORT_SYMBOL(strnlen_user);
12833 +
12834 +
12835 +/*
12836 + * Zero Userspace
12837 + */
12838 +
12839 +unsigned long __clear_user(void *to, unsigned long n)
12840 +{
12841 + __asm__ __volatile__
12842 + (" tstl %1\n"
12843 + " jeq 3f\n"
12844 + "1: movel %3,(%0)+\n"
12845 + "2: subql #1,%1\n"
12846 + " jne 1b\n"
12847 + "3: movel %2,%1\n"
12848 + " bclr #1,%1\n"
12849 + " jeq 4f\n"
12850 + "24:movew %3,(%0)+\n"
12851 + "4: bclr #0,%1\n"
12852 + " jeq 5f\n"
12853 + "25:moveb %3,(%0)+\n"
12854 + "5:\n"
12855 + ".section .fixup,\"ax\"\n"
12856 + " .even\n"
12857 + "61:addql #1,%1\n"
12858 + "6: lsll #2,%1\n"
12859 + " addl %2,%1\n"
12860 + " jra 5b\n"
12861 + "7: addql #2,%1\n"
12862 + " jra 5b\n"
12863 + "8: addql #1,%1\n"
12864 + " jra 5b\n"
12865 + ".previous\n"
12866 + ".section __ex_table,\"a\"\n"
12867 + " .align 4\n"
12868 + " .long 1b,61b\n"
12869 + " .long 2b,6b\n"
12870 + " .long 3b,61b\n"
12871 + " .long 24b,7b\n"
12872 + " .long 4b,7b\n"
12873 + " .long 25b,8b\n"
12874 + " .long 5b,8b\n"
12875 + ".previous"
12876 + : "=a"(to), "=d"(n)
12877 + : "r"(n & 3), "d"(0), "0"(to), "1"(n/4));
12878 + return n;
12879 +}
12880 +EXPORT_SYMBOL(__clear_user);
12881 +
12882 +#endif /* CONFIG_COLDFIRE */
12883 +
12884 --- a/arch/m68k/Makefile
12885 +++ b/arch/m68k/Makefile
12886 @@ -16,7 +16,9 @@
12887 KBUILD_DEFCONFIG := amiga_defconfig
12888
12889 # override top level makefile
12890 +ifndef CONFIG_COLDFIRE
12891 AS += -m68020
12892 +endif
12893 LDFLAGS := -m m68kelf
12894 LDFLAGS_MODULE += -T $(srctree)/arch/m68k/kernel/module.lds
12895 ifneq ($(SUBARCH),$(ARCH))
12896 @@ -30,12 +32,18 @@ ifdef CONFIG_SUN3
12897 LDFLAGS_vmlinux = -N
12898 endif
12899
12900 +ifdef CONFIG_COLDFIRE
12901 +# OBJCOPYFLAGS := -R .note -R .note.gnu.build-id -R .comment -S
12902 +# LDFLAGS_vmlinux = --verbose
12903 +endif
12904 +
12905 CHECKFLAGS += -D__mc68000__
12906
12907 # without -fno-strength-reduce the 53c7xx.c driver fails ;-(
12908 KBUILD_CFLAGS += -pipe -fno-strength-reduce -ffixed-a2
12909
12910 # enable processor switch if compiled only for a single cpu
12911 +ifndef CONFIG_COLDFIRE
12912 ifndef CONFIG_M68020
12913 ifndef CONFIG_M68030
12914
12915 @@ -49,6 +57,16 @@ endif
12916
12917 endif
12918 endif
12919 +endif
12920 +
12921 +ifdef CONFIG_M5445X
12922 +KBUILD_CFLAGS += -march=isac -mcpu=54455 -msoft-float -g
12923 +KBUILD_AFLAGS += -march=isac -mcpu=54455 -msoft-float
12924 +endif
12925 +ifdef CONFIG_M547X_8X
12926 +KBUILD_CFLAGS += -mcfv4e -g
12927 +KBUILD_AFLAGS += -mcfv4e
12928 +endif
12929
12930 ifdef CONFIG_KGDB
12931 # If configured for kgdb support, include debugging infos and keep the
12932 @@ -57,8 +75,12 @@ KBUILD_CFLAGS := $(subst -fomit-frame-po
12933 endif
12934
12935 ifndef CONFIG_SUN3
12936 +ifndef CONFIG_COLDFIRE
12937 head-y := arch/m68k/kernel/head.o
12938 else
12939 +head-y := arch/m68k/coldfire/head.o
12940 +endif
12941 +else
12942 head-y := arch/m68k/kernel/sun3-head.o
12943 endif
12944
12945 @@ -79,6 +101,7 @@ core-$(CONFIG_SUN3) += arch/m68k/sun3/
12946 core-$(CONFIG_M68040) += arch/m68k/fpsp040/
12947 core-$(CONFIG_M68060) += arch/m68k/ifpsp060/
12948 core-$(CONFIG_M68KFPU_EMU) += arch/m68k/math-emu/
12949 +core-$(CONFIG_COLDFIRE) += arch/m68k/coldfire/
12950
12951 all: zImage
12952
12953 --- a/arch/m68k/mm/cache.c
12954 +++ b/arch/m68k/mm/cache.c
12955 @@ -10,7 +10,11 @@
12956 #include <asm/pgalloc.h>
12957 #include <asm/traps.h>
12958
12959 +#ifdef CONFIG_COLDFIRE
12960 +#include <asm/cfcache.h>
12961 +#endif /* CONFIG_COLDFIRE */
12962
12963 +#ifndef CONFIG_COLDFIRE
12964 static unsigned long virt_to_phys_slow(unsigned long vaddr)
12965 {
12966 if (CPU_IS_060) {
12967 @@ -69,11 +73,18 @@ static unsigned long virt_to_phys_slow(u
12968 }
12969 return 0;
12970 }
12971 +#endif /* CONFIG_COLDFIRE */
12972 +
12973
12974 /* Push n pages at kernel virtual address and clear the icache */
12975 /* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
12976 void flush_icache_range(unsigned long address, unsigned long endaddr)
12977 {
12978 +#ifdef CONFIG_COLDFIRE
12979 +// JKM -- hack until new cpushl stuff is in
12980 +// cf_icache_flush_range(address, endaddr);
12981 + flush_icache();
12982 +#else /* !CONFIG_COLDFIRE */
12983
12984 if (CPU_IS_040_OR_060) {
12985 address &= PAGE_MASK;
12986 @@ -94,9 +105,11 @@ void flush_icache_range(unsigned long ad
12987 : "=&d" (tmp)
12988 : "di" (FLUSH_I));
12989 }
12990 +#endif /* CONFIG_COLDFIRE */
12991 }
12992 EXPORT_SYMBOL(flush_icache_range);
12993
12994 +#ifndef CONFIG_COLDFIRE
12995 void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
12996 unsigned long addr, int len)
12997 {
12998 @@ -115,4 +128,5 @@ void flush_icache_user_range(struct vm_a
12999 : "di" (FLUSH_I));
13000 }
13001 }
13002 +#endif /* CONFIG_COLDFIRE */
13003
13004 --- /dev/null
13005 +++ b/arch/m68k/mm/cf-mmu.c
13006 @@ -0,0 +1,260 @@
13007 +/*
13008 + * linux/arch/m68k/mm/cf-mmu.c
13009 + *
13010 + * Based upon linux/arch/m68k/mm/sun3mmu.c
13011 + * Based upon linux/arch/ppc/mm/mmu_context.c
13012 + *
13013 + * Implementations of mm routines specific to the Coldfire MMU.
13014 + *
13015 + * Copyright (c) 2008 Freescale Semiconductor, Inc.
13016 + */
13017 +
13018 +#include <linux/signal.h>
13019 +#include <linux/sched.h>
13020 +#include <linux/mm.h>
13021 +#include <linux/swap.h>
13022 +#include <linux/kernel.h>
13023 +#include <linux/string.h>
13024 +#include <linux/types.h>
13025 +#include <linux/init.h>
13026 +#ifdef CONFIG_BLK_DEV_RAM
13027 +#include <linux/blkdev.h>
13028 +#endif
13029 +#include <linux/bootmem.h>
13030 +
13031 +#include <asm/setup.h>
13032 +#include <asm/uaccess.h>
13033 +#include <asm/page.h>
13034 +#include <asm/pgtable.h>
13035 +#include <asm/system.h>
13036 +#include <asm/machdep.h>
13037 +#include <asm/io.h>
13038 +#include <asm/mmu_context.h>
13039 +#include <asm/cf_pgalloc.h>
13040 +
13041 +#include <asm/coldfire.h>
13042 +#include <asm/tlbflush.h>
13043 +
13044 +#define KMAPAREA(x) ((x >= VMALLOC_START) && ( x < KMAP_END))
13045 +
13046 +#undef DEBUG
13047 +
13048 +mm_context_t next_mmu_context;
13049 +unsigned long context_map[LAST_CONTEXT / BITS_PER_LONG + 1];
13050 +
13051 +atomic_t nr_free_contexts;
13052 +struct mm_struct *context_mm[LAST_CONTEXT+1];
13053 +void steal_context(void);
13054 +
13055 +
13056 +const char bad_pmd_string[] = "Bad pmd in pte_alloc: %08lx\n";
13057 +
13058 +extern unsigned long empty_bad_page_table;
13059 +extern unsigned long empty_bad_page;
13060 +extern unsigned long num_pages;
13061 +
13062 +extern char __init_begin, __init_end;
13063 +
13064 +void free_initmem(void)
13065 +{
13066 +#if 0
13067 + unsigned long addr;
13068 + unsigned long start = (unsigned long)&__init_begin;
13069 + unsigned long end = (unsigned long)&__init_end;
13070 +
13071 + printk(KERN_INFO "free_initmem: __init_begin = 0x%lx __init_end = 0x%lx\n", start, end);
13072 +
13073 + addr = (unsigned long)&__init_begin;
13074 + for (; addr < (unsigned long)&__init_end; addr += PAGE_SIZE) {
13075 + /* not currently used */
13076 + virt_to_page(addr)->flags &= ~(1 << PG_reserved);
13077 + init_page_count(virt_to_page(addr));
13078 + free_page(addr);
13079 + totalram_pages++;
13080 + }
13081 +#endif
13082 +}
13083 +
13084 +/* Coldfire paging_init derived from sun3 */
13085 +void __init paging_init(void)
13086 +{
13087 + pgd_t * pg_dir;
13088 + pte_t * pg_table;
13089 + int i;
13090 + unsigned long address;
13091 + unsigned long next_pgtable;
13092 + unsigned long bootmem_end;
13093 + unsigned long zones_size[MAX_NR_ZONES];
13094 + unsigned long size;
13095 + enum zone_type zone;
13096 +
13097 + empty_zero_page = (void *)alloc_bootmem_pages(PAGE_SIZE);
13098 + memset((void *)empty_zero_page, 0, PAGE_SIZE);
13099 +
13100 + pg_dir = swapper_pg_dir;
13101 + memset(swapper_pg_dir, 0, sizeof (swapper_pg_dir));
13102 +
13103 + size = num_pages * sizeof(pte_t);
13104 + size = (size + PAGE_SIZE) & ~(PAGE_SIZE-1);
13105 + next_pgtable = (unsigned long)alloc_bootmem_pages(size);
13106 +
13107 + bootmem_end = (next_pgtable + size + PAGE_SIZE) & PAGE_MASK;
13108 + pg_dir += PAGE_OFFSET >> PGDIR_SHIFT;
13109 +
13110 + address = PAGE_OFFSET;
13111 + while (address < (unsigned long)high_memory)
13112 + {
13113 + pg_table = (pte_t *)next_pgtable;
13114 + next_pgtable += PTRS_PER_PTE * sizeof (pte_t);
13115 + pgd_val(*pg_dir) = (unsigned long) pg_table;
13116 + pg_dir++;
13117 +
13118 + /* now change pg_table to kernel virtual addresses */
13119 + for (i=0; i<PTRS_PER_PTE; ++i, ++pg_table)
13120 + {
13121 + pte_t pte = pfn_pte(virt_to_pfn(address), PAGE_INIT);
13122 + if (address >= (unsigned long)high_memory)
13123 + pte_val (pte) = 0;
13124 +
13125 + set_pte (pg_table, pte);
13126 + address += PAGE_SIZE;
13127 + }
13128 + }
13129 +
13130 + current->mm = NULL;
13131 +
13132 + /* clear zones */
13133 + for (zone = 0; zone < MAX_NR_ZONES; zone++)
13134 + zones_size[zone] = 0x0;
13135 +
13136 + /* allocate the bottom 32M (0x40x 0x41x) to DMA - head.S marks them NO CACHE */
13137 + /* JKM - this should be changed to allocate from the TOP (0x4f,0x4e) but the
13138 + * allocator is being a bit challenging */
13139 + zones_size[ZONE_DMA] = (32*1024*1024) >> PAGE_SHIFT;
13140 +
13141 + /* allocate the rest to NORMAL - head.S marks them CACHE */
13142 + zones_size[ZONE_NORMAL] = (((unsigned long)high_memory - PAGE_OFFSET) >> PAGE_SHIFT) - zones_size[0];
13143 +
13144 + free_area_init(zones_size);
13145 +}
13146 +
13147 +
13148 +int cf_tlb_miss(struct pt_regs *regs, int write, int dtlb, int extension_word)
13149 +{
13150 + struct mm_struct *mm;
13151 + pgd_t *pgd;
13152 + pmd_t *pmd;
13153 + pte_t *pte;
13154 + unsigned long mmuar;
13155 + int asid;
13156 + int flags;
13157 +
13158 + local_save_flags(flags);
13159 + local_irq_disable();
13160 +
13161 + mmuar = ( dtlb ) ? regs->mmuar
13162 + : regs->pc + (extension_word * sizeof(long));
13163 +
13164 + mm = (!user_mode(regs) && KMAPAREA(mmuar)) ? &init_mm : current->mm;
13165 +
13166 + if (!mm) {
13167 + local_irq_restore(flags);
13168 + return (-1);
13169 + }
13170 +
13171 + pgd = pgd_offset(mm, mmuar);
13172 + if (pgd_none(*pgd)) {
13173 + local_irq_restore(flags);
13174 + return (-1);
13175 + }
13176 +
13177 + pmd = pmd_offset(pgd, mmuar);
13178 + if (pmd_none(*pmd)) {
13179 + local_irq_restore(flags);
13180 + return (-1);
13181 + }
13182 +
13183 + pte = (KMAPAREA(mmuar)) ? pte_offset_kernel(pmd, mmuar)
13184 + : pte_offset_map(pmd, mmuar);
13185 + if (pte_none(*pte) || !pte_present(*pte)) {
13186 + local_irq_restore(flags);
13187 + return (-1);
13188 + }
13189 +
13190 + if (write) {
13191 + if (!pte_write(*pte)) {
13192 + local_irq_restore(flags);
13193 + return (-1);
13194 + }
13195 + set_pte(pte, pte_mkdirty(*pte));
13196 + }
13197 +
13198 + set_pte(pte, pte_mkyoung(*pte));
13199 + asid = mm->context & 0xff;
13200 + if (!pte_dirty(*pte) && !KMAPAREA(mmuar))
13201 + set_pte(pte, pte_wrprotect(*pte));
13202 +
13203 + *MMUTR = (mmuar & PAGE_MASK) | (asid << CF_ASID_MMU_SHIFT)
13204 + | (((int)(pte->pte) & (int)CF_PAGE_MMUTR_MASK ) >> CF_PAGE_MMUTR_SHIFT)
13205 + | MMUTR_V;
13206 +
13207 + *MMUDR = (pte_val(*pte) & PAGE_MASK)
13208 + | ((pte->pte) & CF_PAGE_MMUDR_MASK)
13209 + | MMUDR_SZ8K | MMUDR_X;
13210 +
13211 + if ( dtlb )
13212 + *MMUOR = MMUOR_ACC | MMUOR_UAA;
13213 + else
13214 + *MMUOR = MMUOR_ITLB | MMUOR_ACC | MMUOR_UAA;
13215 +
13216 + asm("nop");
13217 +
13218 +#ifdef DEBUG
13219 + printk("cf_tlb_miss: va=%lx, pa=%lx\n", (mmuar & PAGE_MASK),
13220 + (pte_val(*pte) & PAGE_MASK));
13221 +#endif
13222 + local_irq_restore(flags);
13223 + return (0);
13224 +}
13225 +
13226 +
13227 +/* The following was taken from arch/ppc/mmu_context.c
13228 + *
13229 + * Initialize the context management stuff.
13230 + */
13231 +void __init mmu_context_init(void)
13232 +{
13233 + /*
13234 + * Some processors have too few contexts to reserve one for
13235 + * init_mm, and require using context 0 for a normal task.
13236 + * Other processors reserve the use of context zero for the kernel.
13237 + * This code assumes FIRST_CONTEXT < 32.
13238 + */
13239 + context_map[0] = (1 << FIRST_CONTEXT) - 1;
13240 + next_mmu_context = FIRST_CONTEXT;
13241 + atomic_set(&nr_free_contexts, LAST_CONTEXT - FIRST_CONTEXT + 1);
13242 +}
13243 +
13244 +/*
13245 + * Steal a context from a task that has one at the moment.
13246 + * This is only used on 8xx and 4xx and we presently assume that
13247 + * they don't do SMP. If they do then thicfpgalloc.hs will have to check
13248 + * whether the MM we steal is in use.
13249 + * We also assume that this is only used on systems that don't
13250 + * use an MMU hash table - this is true for 8xx and 4xx.
13251 + * This isn't an LRU system, it just frees up each context in
13252 + * turn (sort-of pseudo-random replacement :). This would be the
13253 + * place to implement an LRU scheme if anyone was motivated to do it.
13254 + * -- paulus
13255 + */
13256 +void steal_context(void)
13257 +{
13258 + struct mm_struct *mm;
13259 + /* free up context `next_mmu_context' */
13260 + /* if we shouldn't free context 0, don't... */
13261 + if (next_mmu_context < FIRST_CONTEXT)
13262 + next_mmu_context = FIRST_CONTEXT;
13263 + mm = context_mm[next_mmu_context];
13264 + flush_tlb_mm(mm);
13265 + destroy_context(mm);
13266 +}
13267 --- /dev/null
13268 +++ b/arch/m68k/mm/cf-mmu.c.orig
13269 @@ -0,0 +1,265 @@
13270 +/*
13271 + * linux/arch/m68k/mm/cf-mmu.c
13272 + *
13273 + * Based upon linux/arch/m68k/mm/sun3mmu.c
13274 + * Based upon linux/arch/ppc/mm/mmu_context.c
13275 + *
13276 + * Implementations of mm routines specific to the Coldfire MMU.
13277 + *
13278 + * Copyright (c) 2008 Freescale Semiconductor, Inc.
13279 + */
13280 +
13281 +#include <linux/signal.h>
13282 +#include <linux/sched.h>
13283 +#include <linux/mm.h>
13284 +#include <linux/swap.h>
13285 +#include <linux/kernel.h>
13286 +#include <linux/string.h>
13287 +#include <linux/types.h>
13288 +#include <linux/init.h>
13289 +#ifdef CONFIG_BLK_DEV_RAM
13290 +#include <linux/blkdev.h>
13291 +#endif
13292 +#include <linux/bootmem.h>
13293 +
13294 +#include <asm/setup.h>
13295 +#include <asm/uaccess.h>
13296 +#include <asm/page.h>
13297 +#include <asm/pgtable.h>
13298 +#include <asm/system.h>
13299 +#include <asm/machdep.h>
13300 +#include <asm/io.h>
13301 +#include <asm/mmu_context.h>
13302 +#include <asm/cf_pgalloc.h>
13303 +
13304 +#include <asm/coldfire.h>
13305 +#include <asm/tlbflush.h>
13306 +
13307 +#if PAGE_OFFSET == CONFIG_SDRAM_BASE
13308 +#define KERNRAM(x) ((x >= PAGE_OFFSET) && (x < (PAGE_OFFSET + CONFIG_SDRAM_SIZE)))
13309 +#else
13310 +#define KERNRAM(x) (x >= PAGE_OFFSET)
13311 +#endif
13312 +
13313 +mm_context_t next_mmu_context;
13314 +unsigned long context_map[LAST_CONTEXT / BITS_PER_LONG + 1];
13315 +
13316 +atomic_t nr_free_contexts;
13317 +struct mm_struct *context_mm[LAST_CONTEXT+1];
13318 +void steal_context(void);
13319 +
13320 +
13321 +const char bad_pmd_string[] = "Bad pmd in pte_alloc: %08lx\n";
13322 +
13323 +extern unsigned long empty_bad_page_table;
13324 +extern unsigned long empty_bad_page;
13325 +extern unsigned long num_pages;
13326 +
13327 +extern char __init_begin, __init_end;
13328 +
13329 +void free_initmem(void)
13330 +{
13331 +#if 0
13332 + unsigned long addr;
13333 + unsigned long start = (unsigned long)&__init_begin;
13334 + unsigned long end = (unsigned long)&__init_end;
13335 +
13336 +/*
13337 + * JKM -- revisit -- the latest round of vmlinux.lds changes has caused
13338 + * a little grief with how init areas are handled. With the new toolchain
13339 + * release I'll fix this.
13340 + */
13341 + printk(KERN_INFO "free_initmem: __init_begin = 0x%lx __init_end = 0x%lx\n", start, end);
13342 +
13343 + addr = (unsigned long)&__init_begin;
13344 + for (; addr < (unsigned long)&__init_end; addr += PAGE_SIZE) {
13345 + /* not currently used */
13346 + virt_to_page(addr)->flags &= ~(1 << PG_reserved);
13347 + init_page_count(virt_to_page(addr));
13348 + free_page(addr);
13349 + totalram_pages++;
13350 + }
13351 +#endif
13352 +}
13353 +
13354 +/* Coldfire paging_init derived from sun3 */
13355 +void __init paging_init(void)
13356 +{
13357 + pgd_t * pg_dir;
13358 + pte_t * pg_table;
13359 + int i;
13360 + unsigned long address;
13361 + unsigned long next_pgtable;
13362 + unsigned long bootmem_end;
13363 + unsigned long zones_size[MAX_NR_ZONES];
13364 + unsigned long size;
13365 + enum zone_type zone;
13366 +
13367 + empty_zero_page = (void *)alloc_bootmem_pages(PAGE_SIZE);
13368 + memset((void *)empty_zero_page, 0, PAGE_SIZE);
13369 +
13370 + pg_dir = swapper_pg_dir;
13371 + memset(swapper_pg_dir, 0, sizeof (swapper_pg_dir));
13372 +
13373 + size = num_pages * sizeof(pte_t);
13374 + size = (size + PAGE_SIZE) & ~(PAGE_SIZE-1);
13375 + next_pgtable = (unsigned long)alloc_bootmem_pages(size);
13376 +
13377 + bootmem_end = (next_pgtable + size + PAGE_SIZE) & PAGE_MASK;
13378 + pg_dir += PAGE_OFFSET >> PGDIR_SHIFT;
13379 +
13380 + address = PAGE_OFFSET;
13381 + while (address < (unsigned long)high_memory)
13382 + {
13383 + pg_table = (pte_t *)next_pgtable;
13384 + next_pgtable += PTRS_PER_PTE * sizeof (pte_t);
13385 + pgd_val(*pg_dir) = (unsigned long) pg_table;
13386 + pg_dir++;
13387 +
13388 + /* now change pg_table to kernel virtual addresses */
13389 + for (i=0; i<PTRS_PER_PTE; ++i, ++pg_table)
13390 + {
13391 + pte_t pte = pfn_pte(virt_to_pfn(address), PAGE_INIT);
13392 + if (address >= (unsigned long)high_memory)
13393 + pte_val (pte) = 0;
13394 +
13395 + set_pte (pg_table, pte);
13396 + address += PAGE_SIZE;
13397 + }
13398 + }
13399 +
13400 + current->mm = NULL;
13401 +
13402 + /* clear zones */
13403 + for (zone = 0; zone < MAX_NR_ZONES; zone++)
13404 + zones_size[zone] = 0x0;
13405 +
13406 + /* allocate the bottom 32M (0x40x 0x41x) to DMA - head.S marks them NO CACHE */
13407 + /* JKM - this should be changed to allocate from the TOP (0x4f,0x4e) but the
13408 + * allocator is being a bit challenging */
13409 + zones_size[ZONE_DMA] = (32*1024*1024) >> PAGE_SHIFT;
13410 +
13411 + /* allocate the rest to NORMAL - head.S marks them CACHE */
13412 + zones_size[ZONE_NORMAL] = (((unsigned long)high_memory - PAGE_OFFSET) >> PAGE_SHIFT) - zones_size[0];
13413 +
13414 + free_area_init(zones_size);
13415 +}
13416 +
13417 +
13418 +int cf_tlb_miss(struct pt_regs *regs, int write, int dtlb, int extension_word)
13419 +{
13420 + struct mm_struct *mm;
13421 + pgd_t *pgd;
13422 + pmd_t *pmd;
13423 + pte_t *pte;
13424 + unsigned long mmuar;
13425 + int asid;
13426 + int flags;
13427 +
13428 + local_save_flags(flags);
13429 + local_irq_disable();
13430 +
13431 + mmuar = ( dtlb ) ? regs->mmuar
13432 + : regs->pc + (extension_word * sizeof(long));
13433 +
13434 + mm = (!user_mode(regs) && KERNRAM(mmuar)) ? &init_mm : current->mm;
13435 +
13436 + if (!mm) {
13437 + local_irq_restore(flags);
13438 + return (-1);
13439 + }
13440 +
13441 + pgd = pgd_offset(mm, mmuar);
13442 + if (pgd_none(*pgd)) {
13443 + local_irq_restore(flags);
13444 + return (-1);
13445 + }
13446 +
13447 + pmd = pmd_offset(pgd, mmuar);
13448 + if (pmd_none(*pmd)) {
13449 + local_irq_restore(flags);
13450 + return (-1);
13451 + }
13452 +
13453 + pte = (KERNRAM(mmuar)) ? pte_offset_kernel(pmd, mmuar)
13454 + : pte_offset_map(pmd, mmuar);
13455 + if (pte_none(*pte) || !pte_present(*pte)) {
13456 + local_irq_restore(flags);
13457 + return (-1);
13458 + }
13459 +
13460 + if (write) {
13461 + if (!pte_write(*pte)) {
13462 + local_irq_restore(flags);
13463 + return (-1);
13464 + }
13465 + set_pte(pte, pte_mkdirty(*pte));
13466 + }
13467 +
13468 + set_pte(pte, pte_mkyoung(*pte));
13469 + asid = mm->context & 0xff;
13470 + if (!pte_dirty(*pte) && !KERNRAM(mmuar))
13471 + set_pte(pte, pte_wrprotect(*pte));
13472 +
13473 + *MMUTR = (mmuar & PAGE_MASK) | (asid << CF_ASID_MMU_SHIFT)
13474 + | (((int)(pte->pte) & (int)CF_PAGE_MMUTR_MASK ) >> CF_PAGE_MMUTR_SHIFT)
13475 + | MMUTR_V;
13476 +
13477 + *MMUDR = (pte_val(*pte) & PAGE_MASK)
13478 + | ((pte->pte) & CF_PAGE_MMUDR_MASK)
13479 + | MMUDR_SZ8K | MMUDR_X;
13480 +
13481 + if ( dtlb )
13482 + *MMUOR = MMUOR_ACC | MMUOR_UAA;
13483 + else
13484 + *MMUOR = MMUOR_ITLB | MMUOR_ACC | MMUOR_UAA;
13485 +
13486 + asm("nop");
13487 +
13488 + /*printk("cf_tlb_miss: va=%lx, pa=%lx\n", (mmuar & PAGE_MASK),
13489 + (pte_val(*pte) & PAGE_MASK));*/
13490 + local_irq_restore(flags);
13491 + return (0);
13492 +}
13493 +
13494 +
13495 +/* The following was taken from arch/ppc/mmu_context.c
13496 + *
13497 + * Initialize the context management stuff.
13498 + */
13499 +void __init mmu_context_init(void)
13500 +{
13501 + /*
13502 + * Some processors have too few contexts to reserve one for
13503 + * init_mm, and require using context 0 for a normal task.
13504 + * Other processors reserve the use of context zero for the kernel.
13505 + * This code assumes FIRST_CONTEXT < 32.
13506 + */
13507 + context_map[0] = (1 << FIRST_CONTEXT) - 1;
13508 + next_mmu_context = FIRST_CONTEXT;
13509 + atomic_set(&nr_free_contexts, LAST_CONTEXT - FIRST_CONTEXT + 1);
13510 +}
13511 +
13512 +/*
13513 + * Steal a context from a task that has one at the moment.
13514 + * This is only used on 8xx and 4xx and we presently assume that
13515 + * they don't do SMP. If they do then thicfpgalloc.hs will have to check
13516 + * whether the MM we steal is in use.
13517 + * We also assume that this is only used on systems that don't
13518 + * use an MMU hash table - this is true for 8xx and 4xx.
13519 + * This isn't an LRU system, it just frees up each context in
13520 + * turn (sort-of pseudo-random replacement :). This would be the
13521 + * place to implement an LRU scheme if anyone was motivated to do it.
13522 + * -- paulus
13523 + */
13524 +void steal_context(void)
13525 +{
13526 + struct mm_struct *mm;
13527 + /* free up context `next_mmu_context' */
13528 + /* if we shouldn't free context 0, don't... */
13529 + if (next_mmu_context < FIRST_CONTEXT)
13530 + next_mmu_context = FIRST_CONTEXT;
13531 + mm = context_mm[next_mmu_context];
13532 + flush_tlb_mm(mm);
13533 + destroy_context(mm);
13534 +}
13535 --- a/arch/m68k/mm/hwtest.c
13536 +++ b/arch/m68k/mm/hwtest.c
13537 @@ -25,6 +25,7 @@
13538
13539 #include <linux/module.h>
13540
13541 +#ifndef CONFIG_COLDFIRE
13542 int hwreg_present( volatile void *regp )
13543 {
13544 int ret = 0;
13545 @@ -82,4 +83,5 @@ int hwreg_write( volatile void *regp, un
13546 return( ret );
13547 }
13548 EXPORT_SYMBOL(hwreg_write);
13549 +#endif
13550
13551 --- a/arch/m68k/mm/init.c
13552 +++ b/arch/m68k/mm/init.c
13553 @@ -122,7 +122,6 @@ void __init mem_init(void)
13554 if (MACH_IS_ATARI)
13555 atari_stram_mem_init_hook();
13556 #endif
13557 -
13558 /* this will put all memory onto the freelists */
13559 totalram_pages = num_physpages = 0;
13560 for_each_online_pgdat(pgdat) {
13561 @@ -146,7 +145,7 @@ void __init mem_init(void)
13562 }
13563 }
13564
13565 -#ifndef CONFIG_SUN3
13566 +#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
13567 /* insert pointer tables allocated so far into the tablelist */
13568 init_pointer_table((unsigned long)kernel_pg_dir);
13569 for (i = 0; i < PTRS_PER_PGD; i++) {
13570 --- a/arch/m68k/mm/kmap.c
13571 +++ b/arch/m68k/mm/kmap.c
13572 @@ -24,7 +24,11 @@
13573
13574 #undef DEBUG
13575
13576 +#ifndef CONFIG_COLDFIRE
13577 #define PTRTREESIZE (256*1024)
13578 +#else
13579 +#define PTRTREESIZE PAGE_SIZE
13580 +#endif
13581
13582 /*
13583 * For 040/060 we can use the virtual memory area like other architectures,
13584 @@ -50,7 +54,11 @@ static inline void free_io_area(void *ad
13585
13586 #else
13587
13588 +#ifdef CONFIG_COLDFIRE
13589 +#define IO_SIZE PAGE_SIZE
13590 +#else
13591 #define IO_SIZE (256*1024)
13592 +#endif
13593
13594 static struct vm_struct *iolist;
13595
13596 @@ -125,8 +133,34 @@ void __iomem *__ioremap(unsigned long ph
13597 }
13598 #endif
13599
13600 +#ifdef CONFIG_M5445X
13601 + if (physaddr >= 0xf0000000) {
13602 + /*
13603 + * On the M5445x processors an ACR is setup to map
13604 + * the 0xF0000000 range into kernel memory as
13605 + * non-cacheable.
13606 + */
13607 + return (void __iomem *)physaddr;
13608 + }
13609 +#endif
13610 +
13611 +#ifdef CONFIG_M547X_8X
13612 + if (physaddr >= 0xf0000000) {
13613 + /*
13614 + * On the M547x/M548x processors an ACR is setup to map
13615 + * the 0xF0000000 range into kernel memory as
13616 + * non-cacheable.
13617 + */
13618 + return (void __iomem *)physaddr;
13619 + }
13620 + if ((physaddr >= 0xd0000000) && (physaddr + size < 0xd800ffff)) {
13621 + printk("ioremap:PCI 0x%lx,0x%lx(%d) - PCI area hit\n", physaddr, size, cacheflag);
13622 + return (void *)physaddr;
13623 + }
13624 +#endif
13625 +
13626 #ifdef DEBUG
13627 - printk("ioremap: 0x%lx,0x%lx(%d) - ", physaddr, size, cacheflag);
13628 + printk("ioremap: paddr=0x%lx,size=0x%lx(%d) - ", physaddr, size, cacheflag);
13629 #endif
13630 /*
13631 * Mappings have to be aligned
13632 @@ -145,7 +179,7 @@ void __iomem *__ioremap(unsigned long ph
13633 virtaddr = (unsigned long)area->addr;
13634 retaddr = virtaddr + offset;
13635 #ifdef DEBUG
13636 - printk("0x%lx,0x%lx,0x%lx", physaddr, virtaddr, retaddr);
13637 + printk(" paddr=0x%lx,vaddr=0x%lx,retaddr=0x%lx", physaddr, virtaddr, retaddr);
13638 #endif
13639
13640 /*
13641 @@ -170,7 +204,12 @@ void __iomem *__ioremap(unsigned long ph
13642 break;
13643 }
13644 } else {
13645 +#ifndef CONFIG_COLDFIRE
13646 physaddr |= (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY);
13647 +#else
13648 + physaddr |= (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY | \
13649 + _PAGE_READWRITE);
13650 +#endif
13651 switch (cacheflag) {
13652 case IOMAP_NOCACHE_SER:
13653 case IOMAP_NOCACHE_NONSER:
13654 @@ -249,7 +288,12 @@ void __iounmap(void *addr, unsigned long
13655 pgd_t *pgd_dir;
13656 pmd_t *pmd_dir;
13657 pte_t *pte_dir;
13658 -
13659 +#ifdef CONFIG_M547X_8X
13660 + if ((addr >= (void*)0xd0000000) && (addr + size < (void*)0xd800ffff)) {
13661 + printk("%s: PCI address\n",__FUNCTION__);
13662 + return;
13663 + }
13664 +#endif
13665 while ((long)size > 0) {
13666 pgd_dir = pgd_offset_k(virtaddr);
13667 if (pgd_bad(*pgd_dir)) {
13668 --- a/arch/m68k/mm/Makefile
13669 +++ b/arch/m68k/mm/Makefile
13670 @@ -6,3 +6,4 @@ obj-y := cache.o init.o fault.o hwtest.
13671
13672 obj-$(CONFIG_MMU_MOTOROLA) += kmap.o memory.o motorola.o
13673 obj-$(CONFIG_MMU_SUN3) += sun3kmap.o sun3mmu.o
13674 +obj-$(CONFIG_MMU_CFV4E) += cf-mmu.o kmap.o memory.o
13675 --- a/arch/m68k/mm/memory.c
13676 +++ b/arch/m68k/mm/memory.c
13677 @@ -127,6 +127,7 @@ int free_pointer_table (pmd_t *ptable)
13678 return 0;
13679 }
13680
13681 +#ifndef CONFIG_COLDFIRE
13682 /* invalidate page in both caches */
13683 static inline void clear040(unsigned long paddr)
13684 {
13685 @@ -173,6 +174,7 @@ static inline void pushcl040(unsigned lo
13686 clear040(paddr);
13687 local_irq_restore(flags);
13688 }
13689 +#endif /* CONFIG_COLDFIRE */
13690
13691 /*
13692 * 040: Hit every page containing an address in the range paddr..paddr+len-1.
13693 @@ -203,6 +205,11 @@ static inline void pushcl040(unsigned lo
13694
13695 void cache_clear (unsigned long paddr, int len)
13696 {
13697 +#ifdef CONFIG_COLDFIRE
13698 +// JKM -- revise to use proper caching
13699 +// cf_cache_clear(paddr, len);
13700 + flush_bcache();
13701 +#else
13702 if (CPU_IS_040_OR_060) {
13703 int tmp;
13704
13705 @@ -237,6 +244,7 @@ void cache_clear (unsigned long paddr, i
13706 if(mach_l2_flush)
13707 mach_l2_flush(0);
13708 #endif
13709 +#endif /* CONFIG_COLDFIRE */
13710 }
13711 EXPORT_SYMBOL(cache_clear);
13712
13713 @@ -250,6 +258,11 @@ EXPORT_SYMBOL(cache_clear);
13714
13715 void cache_push (unsigned long paddr, int len)
13716 {
13717 +#ifdef CONFIG_COLDFIRE
13718 +// JKM -- revise to use proper caching
13719 +// cf_cache_push(paddr, len);
13720 + flush_bcache();
13721 +#else
13722 if (CPU_IS_040_OR_060) {
13723 int tmp = PAGE_SIZE;
13724
13725 @@ -290,6 +303,7 @@ void cache_push (unsigned long paddr, in
13726 if(mach_l2_flush)
13727 mach_l2_flush(1);
13728 #endif
13729 +#endif /* CONFIG_COLDFIRE */
13730 }
13731 EXPORT_SYMBOL(cache_push);
13732
13733 --- a/drivers/ata/Kconfig
13734 +++ b/drivers/ata/Kconfig
13735 @@ -6,7 +6,7 @@ menuconfig ATA
13736 tristate "Serial ATA (prod) and Parallel ATA (experimental) drivers"
13737 depends on HAS_IOMEM
13738 depends on BLOCK
13739 - depends on !(M32R || M68K) || BROKEN
13740 + depends on !M32R || BROKEN
13741 depends on !SUN4 || BROKEN
13742 select SCSI
13743 ---help---
13744 @@ -679,4 +679,13 @@ config PATA_BF54X
13745
13746 If unsure, say N.
13747
13748 +config PATA_FSL
13749 + tristate "Freescale on-chip PATA support"
13750 + depends on (ARCH_MX3 || ARCH_MX27 || PPC_512x || M54455)
13751 + help
13752 + On Freescale processors, say Y here if you wish to use the on-chip
13753 + ATA interface.
13754 +
13755 + If you are unsure, say N to this.
13756 +
13757 endif # ATA
13758 --- a/drivers/ata/Makefile
13759 +++ b/drivers/ata/Makefile
13760 @@ -1,4 +1,3 @@
13761 -
13762 obj-$(CONFIG_ATA) += libata.o
13763
13764 obj-$(CONFIG_SATA_AHCI) += ahci.o
13765 @@ -71,6 +70,7 @@ obj-$(CONFIG_PATA_BF54X) += pata_bf54x.o
13766 obj-$(CONFIG_PATA_PLATFORM) += pata_platform.o
13767 obj-$(CONFIG_PATA_OF_PLATFORM) += pata_of_platform.o
13768 obj-$(CONFIG_PATA_ICSIDE) += pata_icside.o
13769 +obj-$(CONFIG_PATA_FSL) += pata_fsl.o
13770 # Should be last but two libata driver
13771 obj-$(CONFIG_PATA_ACPI) += pata_acpi.o
13772 # Should be last but one libata driver
13773 --- /dev/null
13774 +++ b/drivers/ata/pata_fsl.c
13775 @@ -0,0 +1,814 @@
13776 +/*
13777 + * Freescale integrated PATA driver
13778 + */
13779 +
13780 +/*
13781 + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
13782 + */
13783 +
13784 +/*
13785 + * The code contained herein is licensed under the GNU General Public
13786 + * License. You may obtain a copy of the GNU General Public License
13787 + * Version 2 or later at the following locations:
13788 + *
13789 + * http://www.opensource.org/licenses/gpl-license.html
13790 + * http://www.gnu.org/copyleft/gpl.html
13791 + */
13792 +
13793 +#include <linux/kernel.h>
13794 +#include <linux/module.h>
13795 +#include <linux/init.h>
13796 +#include <linux/blkdev.h>
13797 +#include <scsi/scsi_host.h>
13798 +#include <linux/ata.h>
13799 +#include <linux/libata.h>
13800 +#include <linux/platform_device.h>
13801 +#include <linux/fsl_devices.h>
13802 +#ifdef CONFIG_FSL_PATA_USE_DMA
13803 +#include <asm/dma.h>
13804 +#endif
13805 +
13806 +#define DRV_NAME "pata_fsl"
13807 +#define DRV_VERSION "1.0"
13808 +
13809 +#ifdef CONFIG_M54455
13810 +#define WRITE_ATA8(val, reg) \
13811 + __raw_writeb(val, (ata_regs + reg));
13812 +#define WRITE_ATA16(val, reg) \
13813 + __raw_writew(val, (ata_regs + reg));
13814 +#else
13815 +#define WRITE_ATA8(val, reg) \
13816 + __raw_writel(val, (ata_regs + reg));
13817 +#define WRITE_ATA16(val, reg) \
13818 + __raw_writel(val, (ata_regs + reg));
13819 +#endif
13820 +
13821 +struct pata_fsl_priv {
13822 +#ifdef CONFIG_FSL_PATA_USE_DMA
13823 + int ultra;
13824 +#endif
13825 + u8 *fsl_ata_regs;
13826 +#ifdef CONFIG_FSL_PATA_USE_DMA
13827 + int dma_rchan;
13828 + int dma_wchan;
13829 + int dma_done;
13830 + int dma_dir;
13831 +#endif
13832 +};
13833 +
13834 +enum {
13835 + /* various constants */
13836 +
13837 +#ifdef CONFIG_FSL_PATA_USE_DMA
13838 + FSL_ATA_MAX_SG_LEN = 65534,
13839 +#endif
13840 +
13841 + /* offsets to registers */
13842 +
13843 + FSL_ATA_TIMING_REGS = 0x00,
13844 + FSL_ATA_FIFO_FILL = 0x20,
13845 + FSL_ATA_CONTROL = 0x24,
13846 + FSL_ATA_INT_PEND = 0x28,
13847 + FSL_ATA_INT_EN = 0x2C,
13848 + FSL_ATA_INT_CLEAR = 0x30,
13849 + FSL_ATA_FIFO_ALARM = 0x34,
13850 + FSL_ATA_DRIVE_DATA = 0xA0,
13851 + FSL_ATA_DRIVE_CONTROL = 0xD8,
13852 +
13853 + /* bits within FSL_ATA_CONTROL */
13854 +
13855 + FSL_ATA_CTRL_FIFO_RST_B = 0x80,
13856 + FSL_ATA_CTRL_ATA_RST_B = 0x40,
13857 + FSL_ATA_CTRL_FIFO_TX_EN = 0x20,
13858 + FSL_ATA_CTRL_FIFO_RCV_EN = 0x10,
13859 + FSL_ATA_CTRL_DMA_PENDING = 0x08,
13860 + FSL_ATA_CTRL_DMA_ULTRA = 0x04,
13861 + FSL_ATA_CTRL_DMA_WRITE = 0x02,
13862 + FSL_ATA_CTRL_IORDY_EN = 0x01,
13863 +
13864 + /* bits within the interrupt control registers */
13865 +
13866 + FSL_ATA_INTR_ATA_INTRQ1 = 0x80,
13867 + FSL_ATA_INTR_FIFO_UNDERFLOW = 0x40,
13868 + FSL_ATA_INTR_FIFO_OVERFLOW = 0x20,
13869 + FSL_ATA_INTR_CTRL_IDLE = 0x10,
13870 + FSL_ATA_INTR_ATA_INTRQ2 = 0x08,
13871 +};
13872 +
13873 +/*
13874 + * This structure contains the timing parameters for
13875 + * ATA bus timing in the 5 PIO modes. The timings
13876 + * are in nanoseconds, and are converted to clock
13877 + * cycles before being stored in the ATA controller
13878 + * timing registers.
13879 + */
13880 +static struct {
13881 + short t0, t1, t2_8, t2_16, t2i, t4, t9, tA;
13882 +} pio_specs[] = {
13883 + [0] = {
13884 + .t0 = 600, .t1 = 70, .t2_8 = 290, .t2_16 = 165, .t2i = 0,
13885 + .t4 = 30,.t9 = 20,.tA = 50
13886 + },
13887 + [1] = {
13888 + .t0 = 383, .t1 = 50, .t2_8 = 290, .t2_16 = 125, .t2i = 0,
13889 + .t4 = 20, .t9 = 15, .tA = 50
13890 + },
13891 + [2] = {
13892 + .t0 = 240, .t1 = 30, .t2_8 = 290, .t2_16 = 100, .t2i = 0,
13893 + .t4 = 15, .t9 = 10, .tA = 50
13894 + },
13895 + [3] = {
13896 + .t0 = 180, .t1 = 30, .t2_8 = 80, .t2_16 = 80, .t2i = 0,
13897 + .t4 = 10, .t9 = 10, .tA = 50
13898 + },
13899 + [4] = {
13900 + .t0 = 120, .t1 = 25, .t2_8 = 70, .t2_16 = 70, .t2i = 0,
13901 + .t4 = 10, .t9 = 10, .tA = 50
13902 + },
13903 +};
13904 +
13905 +#define NR_PIO_SPECS (sizeof pio_specs / sizeof pio_specs[0])
13906 +
13907 +/*
13908 + * This structure contains the timing parameters for
13909 + * ATA bus timing in the 3 MDMA modes. The timings
13910 + * are in nanoseconds, and are converted to clock
13911 + * cycles before being stored in the ATA controller
13912 + * timing registers.
13913 + */
13914 +static struct {
13915 + short t0M, tD, tH, tJ, tKW, tM, tN, tJNH;
13916 +} mdma_specs[] = {
13917 + [0] = {
13918 + .t0M = 480, .tD = 215, .tH = 20, .tJ = 20, .tKW = 215,
13919 + .tM = 50, .tN = 15, .tJNH = 20
13920 + },
13921 + [1] = {
13922 + .t0M = 150, .tD = 80, .tH = 15, .tJ = 5, .tKW = 50,
13923 + .tM = 30, .tN = 10, .tJNH = 15
13924 + },
13925 + [2] = {
13926 + .t0M = 120, .tD = 70, .tH = 10, .tJ = 5, .tKW = 25,
13927 + .tM = 25, .tN = 10, .tJNH = 10
13928 + },
13929 +};
13930 +
13931 +#define NR_MDMA_SPECS (sizeof mdma_specs / sizeof mdma_specs[0])
13932 +
13933 +/*
13934 + * This structure contains the timing parameters for
13935 + * ATA bus timing in the 6 UDMA modes. The timings
13936 + * are in nanoseconds, and are converted to clock
13937 + * cycles before being stored in the ATA controller
13938 + * timing registers.
13939 + */
13940 +static struct {
13941 + short t2CYC, tCYC, tDS, tDH, tDVS, tDVH, tCVS, tCVH, tFS_min, tLI_max,
13942 + tMLI, tAZ, tZAH, tENV_min, tSR, tRFS, tRP, tACK, tSS, tDZFS;
13943 +} udma_specs[] = {
13944 + [0] = {
13945 + .t2CYC = 235, .tCYC = 114, .tDS = 15, .tDH = 5, .tDVS = 70,
13946 + .tDVH = 6, .tCVS = 70, .tCVH = 6, .tFS_min = 0,
13947 + .tLI_max = 100, .tMLI = 20, .tAZ = 10, .tZAH = 20,
13948 + .tENV_min = 20, .tSR = 50, .tRFS = 75, .tRP = 160,
13949 + .tACK = 20, .tSS = 50, .tDZFS = 80
13950 + },
13951 + [1] = {
13952 + .t2CYC = 156, .tCYC = 75, .tDS = 10, .tDH = 5, .tDVS = 48,
13953 + .tDVH = 6, .tCVS = 48, .tCVH = 6, .tFS_min = 0,
13954 + .tLI_max = 100, .tMLI = 20, .tAZ = 10, .tZAH = 20,
13955 + .tENV_min = 20, .tSR = 30, .tRFS = 70, .tRP = 125,
13956 + .tACK = 20, .tSS = 50, .tDZFS = 63
13957 + },
13958 + [2] = {
13959 + .t2CYC = 117, .tCYC = 55, .tDS = 7, .tDH = 5, .tDVS = 34,
13960 + .tDVH = 6, .tCVS = 34, .tCVH = 6, .tFS_min = 0,
13961 + .tLI_max = 100, .tMLI = 20, .tAZ = 10, .tZAH = 20,
13962 + .tENV_min = 20, .tSR = 20, .tRFS = 60, .tRP = 100,
13963 + .tACK = 20, .tSS = 50, .tDZFS = 47
13964 + },
13965 + [3] = {
13966 + .t2CYC = 86, .tCYC = 39, .tDS = 7, .tDH = 5, .tDVS = 20,
13967 + .tDVH = 6, .tCVS = 20, .tCVH = 6, .tFS_min = 0,
13968 + .tLI_max = 100, .tMLI = 20, .tAZ = 10, .tZAH = 20,
13969 + .tENV_min = 20, .tSR = 20, .tRFS = 60, .tRP = 100,
13970 + .tACK = 20, .tSS = 50, .tDZFS = 35
13971 + },
13972 + [4] = {
13973 + .t2CYC = 57, .tCYC = 25, .tDS = 5, .tDH = 5, .tDVS = 7,
13974 + .tDVH = 6, .tCVS = 7, .tCVH = 6, .tFS_min = 0,
13975 + .tLI_max = 100, .tMLI = 20, .tAZ = 10, .tZAH = 20,
13976 + .tENV_min = 20, .tSR = 50, .tRFS = 60, .tRP = 100,
13977 + .tACK = 20, .tSS = 50, .tDZFS = 25
13978 + },
13979 + [5] = {
13980 + .t2CYC = 38, .tCYC = 17, .tDS = 4, .tDH = 5, .tDVS = 5,
13981 + .tDVH = 6, .tCVS = 10, .tCVH = 10, .tFS_min = 0,
13982 + .tLI_max = 75, .tMLI = 20, .tAZ = 10, .tZAH = 20,
13983 + .tENV_min = 20, .tSR = 20, .tRFS = 50, .tRP = 85,
13984 + .tACK = 20, .tSS = 50, .tDZFS = 40
13985 + },
13986 +};
13987 +
13988 +#define NR_UDMA_SPECS (sizeof udma_specs / sizeof udma_specs[0])
13989 +
13990 +struct fsl_ata_time_regs {
13991 + u8 time_off, time_on, time_1, time_2w;
13992 + u8 time_2r, time_ax, time_pio_rdx, time_4;
13993 + u8 time_9, time_m, time_jn, time_d;
13994 + u8 time_k, time_ack, time_env, time_rpx;
13995 + u8 time_zah, time_mlix, time_dvh, time_dzfs;
13996 + u8 time_dvs, time_cvh, time_ss, time_cyc;
13997 +};
13998 +
13999 +static void update_timing_config(struct fsl_ata_time_regs *tp, struct ata_host *host)
14000 +{
14001 + u32 *lp = (u32 *)tp;
14002 + struct pata_fsl_priv *priv = host->private_data;
14003 + u32 *ctlp = (u32 *)priv->fsl_ata_regs;
14004 + int i;
14005 +
14006 + /*
14007 + * JKM - this could have endianess issues on BE depending
14008 + * on how the controller is glued to the bus -- probably
14009 + * should rewrite this to write byte at a time.
14010 + */
14011 + for (i = 0; i < 5; i++) {
14012 + __raw_writel(*lp, ctlp);
14013 + lp++;
14014 + ctlp++;
14015 + }
14016 + mb();
14017 +}
14018 +
14019 +/*!
14020 + * Calculate values for the ATA bus timing registers and store
14021 + * them into the hardware.
14022 + *
14023 + * @param xfer_mode specifies XFER xfer_mode
14024 + * @param pdev specifies platform_device
14025 + *
14026 + * @return EINVAL speed out of range, or illegal mode
14027 + */
14028 +static int set_ata_bus_timing(u8 xfer_mode, struct platform_device *pdev)
14029 +{
14030 + struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *)
14031 + pdev->dev.platform_data;
14032 + struct ata_host *host = dev_get_drvdata(&pdev->dev);
14033 +
14034 + /* get the bus clock cycle time, in ns */
14035 + int T = 1 * 1000 * 1000 * 1000 / plat->get_clk_rate();
14036 + struct fsl_ata_time_regs tr = {0};
14037 + DPRINTK("clk_rate = %d T = %d\n",plat->get_clk_rate(), T);
14038 +
14039 + /*
14040 + * every mode gets the same t_off and t_on
14041 + */
14042 + tr.time_off = 3;
14043 + tr.time_on = 3;
14044 +
14045 + if (xfer_mode >= XFER_UDMA_0) {
14046 + int speed = xfer_mode - XFER_UDMA_0;
14047 + if (speed >= NR_UDMA_SPECS) {
14048 + return -EINVAL;
14049 + }
14050 + tr.time_ack = (udma_specs[speed].tACK + T) / T;
14051 + tr.time_env = (udma_specs[speed].tENV_min + T) / T;
14052 + tr.time_rpx = (udma_specs[speed].tRP + T) / T + 2;
14053 +
14054 + tr.time_zah = (udma_specs[speed].tZAH + T) / T;
14055 + tr.time_mlix = (udma_specs[speed].tMLI + T) / T;
14056 + tr.time_dvh = (udma_specs[speed].tDVH + T) / T + 1;
14057 + tr.time_dzfs = (udma_specs[speed].tDZFS + T) / T;
14058 +
14059 + tr.time_dvs = (udma_specs[speed].tDVS + T) / T;
14060 + tr.time_cvh = (udma_specs[speed].tCVH + T) / T;
14061 + tr.time_ss = (udma_specs[speed].tSS + T) / T;
14062 + tr.time_cyc = (udma_specs[speed].tCYC + T) / T;
14063 + } else if (xfer_mode >= XFER_MW_DMA_0) {
14064 + int speed = xfer_mode - XFER_MW_DMA_0;
14065 + if (speed >= NR_MDMA_SPECS) {
14066 + return -EINVAL;
14067 + }
14068 + tr.time_m = (mdma_specs[speed].tM + T) / T;
14069 + tr.time_jn = (mdma_specs[speed].tJNH + T) / T;
14070 + tr.time_d = (mdma_specs[speed].tD + T) / T;
14071 +
14072 + tr.time_k = (mdma_specs[speed].tKW + T) / T;
14073 + } else {
14074 + int speed = xfer_mode - XFER_PIO_0;
14075 + if (speed >= NR_PIO_SPECS) {
14076 + return -EINVAL;
14077 + }
14078 + tr.time_1 = (pio_specs[speed].t1 + T) / T;
14079 + tr.time_2w = (pio_specs[speed].t2_8 + T) / T;
14080 +
14081 + tr.time_2r = (pio_specs[speed].t2_8 + T) / T;
14082 + tr.time_ax = (pio_specs[speed].tA + T) / T + 2;
14083 + tr.time_pio_rdx = 1;
14084 + tr.time_4 = (pio_specs[speed].t4 + T) / T;
14085 +
14086 + tr.time_9 = (pio_specs[speed].t9 + T) / T;
14087 + }
14088 +
14089 + update_timing_config(&tr, host);
14090 +
14091 + return 0;
14092 +}
14093 +
14094 +static void pata_fsl_set_piomode(struct ata_port *ap, struct ata_device *adev)
14095 +{
14096 + set_ata_bus_timing(adev->pio_mode, to_platform_device(ap->dev));
14097 +}
14098 +
14099 +#ifdef CONFIG_FSL_PATA_USE_DMA
14100 +static void pata_fsl_set_dmamode(struct ata_port *ap, struct ata_device *adev)
14101 +{
14102 + struct pata_fsl_priv *priv = ap->host->private_data;
14103 +
14104 + priv->ultra = adev->dma_mode >= XFER_UDMA_0;
14105 +
14106 + set_ata_bus_timing(adev->dma_mode, to_platform_device(ap->dev));
14107 +}
14108 +#endif
14109 +
14110 +static int pata_fsl_port_start(struct ata_port *ap)
14111 +{
14112 + return 0;
14113 +}
14114 +
14115 +#ifdef CONFIG_FSL_PATA_USE_DMA
14116 +static void dma_callback(void *arg, int error_status, unsigned int count)
14117 +{
14118 + struct ata_port *ap = arg;
14119 + struct pata_fsl_priv *priv = ap->host->private_data;
14120 + u8 *ata_regs = priv->fsl_ata_regs;
14121 +
14122 + priv->dma_done = 1;
14123 + /*
14124 + * DMA is finished, so unmask INTRQ from the drive to allow the
14125 + * normal ISR to fire.
14126 + */
14127 +#if 0
14128 + __raw_writel(FSL_ATA_INTR_ATA_INTRQ2, ata_regs + FSL_ATA_INT_EN);
14129 +#else
14130 + WRITE_ATA8(FSL_ATA_INTR_ATA_INTRQ2, FSL_ATA_INT_EN);
14131 +#endif
14132 + mb();
14133 +}
14134 +
14135 +static void pata_fsl_bmdma_setup(struct ata_queued_cmd *qc)
14136 +{
14137 + int nr_sg = 0;
14138 + int chan;
14139 + int dma_mode = 0, dma_ultra;
14140 + u8 ata_control;
14141 + struct ata_port *ap = qc->ap;
14142 + struct pata_fsl_priv *priv = ap->host->private_data;
14143 + u8 *ata_regs = priv->fsl_ata_regs;
14144 + struct fsl_ata_platform_data *plat = ap->dev->platform_data;
14145 + struct scatterlist tmp[plat->max_sg], *tsg, *sg;
14146 + int err;
14147 +
14148 + DPRINTK("ENTER\n");
14149 +
14150 + priv->dma_dir = qc->dma_dir;
14151 +
14152 + /*
14153 + * Configure the on-chip ATA interface hardware.
14154 + */
14155 + dma_ultra = priv->ultra ?
14156 + FSL_ATA_CTRL_DMA_ULTRA : 0;
14157 +
14158 + ata_control = FSL_ATA_CTRL_FIFO_RST_B |
14159 + FSL_ATA_CTRL_ATA_RST_B |
14160 + FSL_ATA_CTRL_DMA_PENDING |
14161 + dma_ultra;
14162 +
14163 + if (qc->dma_dir == DMA_TO_DEVICE) {
14164 + chan = priv->dma_wchan;
14165 + ata_control |= FSL_ATA_CTRL_FIFO_TX_EN |
14166 + FSL_ATA_CTRL_DMA_WRITE;
14167 + dma_mode = DMA_MODE_WRITE;
14168 + } else {
14169 + chan = priv->dma_rchan;
14170 + ata_control |= FSL_ATA_CTRL_FIFO_RCV_EN;
14171 + dma_mode = DMA_MODE_READ;
14172 + }
14173 +#if 0
14174 + __raw_writel(ata_control, ata_regs + FSL_ATA_CONTROL);
14175 + __raw_writel(plat->fifo_alarm, ata_regs + FSL_ATA_FIFO_ALARM);
14176 + __raw_writel(FSL_ATA_INTR_ATA_INTRQ1, ata_regs + FSL_ATA_INT_EN);
14177 +#else
14178 + WRITE_ATA8(ata_control, FSL_ATA_CONTROL);
14179 + WRITE_ATA8(plat->fifo_alarm, FSL_ATA_FIFO_ALARM);
14180 + WRITE_ATA8(FSL_ATA_INTR_ATA_INTRQ1, FSL_ATA_INT_EN);
14181 +#endif
14182 + mb();
14183 +
14184 + /*
14185 + * Set up the DMA completion callback.
14186 + */
14187 + mxc_dma_callback_set(chan, dma_callback, (void *)ap);
14188 +
14189 + /*
14190 + * Copy the sg list to an array.
14191 + */
14192 + tsg = tmp;
14193 + ata_for_each_sg(sg, qc) {
14194 + memcpy(tsg, sg, sizeof *sg);
14195 + tsg++;
14196 + nr_sg++;
14197 + }
14198 +
14199 + err = mxc_dma_sg_config(chan, tmp, nr_sg, 0, dma_mode);
14200 + if (err) {
14201 + printk(KERN_ERR "pata_fsl_bmdma_setup: error %d\n", err);
14202 + }
14203 + DPRINTK("EXIT\n");
14204 +}
14205 +
14206 +static void pata_fsl_bmdma_start(struct ata_queued_cmd *qc)
14207 +{
14208 + struct ata_port *ap = qc->ap;
14209 + struct pata_fsl_priv *priv = ap->host->private_data;
14210 + int chan;
14211 + int err;
14212 +
14213 + /*
14214 + * Start the channel.
14215 + */
14216 + chan = qc->dma_dir == DMA_TO_DEVICE ? priv->dma_wchan : priv->dma_rchan;
14217 +
14218 + priv->dma_done = 0;
14219 +
14220 + err = mxc_dma_enable(chan);
14221 + if (err) {
14222 + printk(KERN_ERR "%s: : error %d\n", __func__, err);
14223 + }
14224 +
14225 + ap->ops->exec_command(ap, &qc->tf);
14226 +}
14227 +
14228 +static void pata_fsl_bmdma_stop(struct ata_queued_cmd *qc)
14229 +{
14230 + struct ata_port *ap = qc->ap;
14231 +
14232 + /* do a dummy read as in ata_bmdma_stop */
14233 + ata_altstatus(ap);
14234 +}
14235 +
14236 +static u8 pata_fsl_bmdma_status(struct ata_port *ap)
14237 +{
14238 + struct pata_fsl_priv *priv = ap->host->private_data;
14239 +
14240 + return priv->dma_done ? ATA_DMA_INTR : 0;
14241 +}
14242 +
14243 +static void pata_fsl_dma_init(struct ata_port *ap)
14244 +{
14245 + struct pata_fsl_priv *priv = ap->host->private_data;
14246 +
14247 + priv->dma_rchan = -1;
14248 + priv->dma_wchan = -1;
14249 +
14250 + priv->dma_rchan = mxc_dma_request(MXC_DMA_ATA_RX, "MXC ATA RX");
14251 + if (priv->dma_rchan < 0) {
14252 + dev_printk(KERN_ERR, ap->dev, "couldn't get RX DMA channel\n");
14253 + goto err_out;
14254 + }
14255 +
14256 + priv->dma_wchan = mxc_dma_request(MXC_DMA_ATA_TX, "MXC ATA TX");
14257 + if (priv->dma_wchan < 0) {
14258 + dev_printk(KERN_ERR, ap->dev, "couldn't get TX DMA channel\n");
14259 + goto err_out;
14260 + }
14261 +
14262 + dev_printk(KERN_ERR, ap->dev, "rchan=%d wchan=%d\n", priv->dma_rchan,
14263 + priv->dma_wchan);
14264 + return;
14265 +
14266 +err_out:
14267 + ap->mwdma_mask = 0;
14268 + ap->udma_mask = 0;
14269 + mxc_dma_free(priv->dma_rchan);
14270 + mxc_dma_free(priv->dma_wchan);
14271 + kfree(priv);
14272 +}
14273 +#endif /* CONFIG_FSL_PATA_USE_DMA */
14274 +
14275 +static void ata_dummy_noret(struct ata_port *ap) { return; }
14276 +
14277 +static struct scsi_host_template pata_fsl_sht = {
14278 + .module = THIS_MODULE,
14279 + .name = DRV_NAME,
14280 + .ioctl = ata_scsi_ioctl,
14281 + .queuecommand = ata_scsi_queuecmd,
14282 + .can_queue = ATA_DEF_QUEUE,
14283 + .this_id = ATA_SHT_THIS_ID,
14284 + .sg_tablesize = LIBATA_MAX_PRD,
14285 + .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
14286 + .emulated = ATA_SHT_EMULATED,
14287 + .use_clustering = ATA_SHT_USE_CLUSTERING,
14288 + .proc_name = DRV_NAME,
14289 +#ifdef CONFIG_FSL_PATA_USE_DMA
14290 + .dma_boundary = FSL_ATA_MAX_SG_LEN,
14291 +#endif
14292 + .slave_configure = ata_scsi_slave_config,
14293 + .slave_destroy = ata_scsi_slave_destroy,
14294 + .bios_param = ata_std_bios_param,
14295 +};
14296 +
14297 +static struct ata_port_operations pata_fsl_port_ops = {
14298 + .set_piomode = pata_fsl_set_piomode,
14299 +#ifdef CONFIG_FSL_PATA_USE_DMA
14300 + .set_dmamode = pata_fsl_set_dmamode,
14301 +#endif
14302 +
14303 + .tf_load = ata_tf_load,
14304 + .tf_read = ata_tf_read,
14305 + .check_status = ata_check_status,
14306 + .exec_command = ata_exec_command,
14307 + .dev_select = ata_std_dev_select,
14308 +
14309 + .freeze = ata_bmdma_freeze,
14310 + .thaw = ata_bmdma_thaw,
14311 + .error_handler = ata_bmdma_error_handler,
14312 + .post_internal_cmd = ata_bmdma_post_internal_cmd,
14313 + .cable_detect = ata_cable_unknown,
14314 +
14315 +#ifdef CONFIG_FSL_PATA_USE_DMA
14316 + .bmdma_setup = pata_fsl_bmdma_setup,
14317 + .bmdma_start = pata_fsl_bmdma_start,
14318 +#endif
14319 +
14320 + .qc_prep = ata_noop_qc_prep,
14321 + .qc_issue = ata_qc_issue_prot,
14322 +
14323 + .data_xfer = ata_data_xfer_noirq,
14324 +
14325 + .irq_clear = ata_dummy_noret,
14326 + .irq_on = ata_irq_on,
14327 +
14328 + .port_start = pata_fsl_port_start,
14329 +
14330 +#ifdef CONFIG_FSL_PATA_USE_DMA
14331 + .bmdma_stop = pata_fsl_bmdma_stop,
14332 + .bmdma_status = pata_fsl_bmdma_status,
14333 +#endif
14334 +};
14335 +
14336 +static void fsl_setup_port(struct ata_ioports *ioaddr)
14337 +{
14338 + unsigned int shift = 2;
14339 +
14340 + ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << shift);
14341 + ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << shift);
14342 + ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << shift);
14343 + ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << shift);
14344 + ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << shift);
14345 + ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << shift);
14346 + ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << shift);
14347 + ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << shift);
14348 + ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << shift);
14349 + ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << shift);
14350 +}
14351 +
14352 +/**
14353 + * pata_fsl_probe - attach a platform interface
14354 + * @pdev: platform device
14355 + *
14356 + * Register a platform bus integrated ATA host controller
14357 + *
14358 + * The 3 platform device resources are used as follows:
14359 + *
14360 + * - I/O Base (IORESOURCE_MEM) virt. addr. of ATA controller regs
14361 + * - CTL Base (IORESOURCE_MEM) unused
14362 + * - IRQ (IORESOURCE_IRQ) platform IRQ assigned to ATA
14363 + *
14364 + */
14365 +static int __devinit pata_fsl_probe(struct platform_device *pdev)
14366 +{
14367 + struct resource *io_res;
14368 + struct ata_host *host;
14369 + struct ata_port *ap;
14370 + struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *)
14371 + pdev->dev.platform_data;
14372 + struct pata_fsl_priv *priv;
14373 + u8 *ata_regs;
14374 + int ret;
14375 +
14376 + DPRINTK("ENTER\n");
14377 + /*
14378 + * Get an ata_host structure for this device
14379 + */
14380 + host = ata_host_alloc(&pdev->dev, 1);
14381 + if (!host)
14382 + return -ENOMEM;
14383 + ap = host->ports[0];
14384 +
14385 + /*
14386 + * Allocate private data
14387 + */
14388 + priv = kzalloc(sizeof (struct pata_fsl_priv), GFP_KERNEL);
14389 + if(priv == NULL) {
14390 + /* free(host); */
14391 + return -ENOMEM;
14392 + }
14393 + host->private_data = priv;
14394 +
14395 + /*
14396 + * Set up resources
14397 + */
14398 + if (unlikely(pdev->num_resources != 3)) {
14399 + dev_err(&pdev->dev, "invalid number of resources\n");
14400 + return -EINVAL;
14401 + }
14402 +
14403 + io_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
14404 + ata_regs = (u8 *)io_res->start;
14405 + priv->fsl_ata_regs = ata_regs;
14406 + ap->ioaddr.cmd_addr = (void *)(ata_regs + FSL_ATA_DRIVE_DATA);
14407 + ap->ioaddr.ctl_addr = (void *)(ata_regs + FSL_ATA_DRIVE_CONTROL);
14408 + ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
14409 + ap->ops = &pata_fsl_port_ops;
14410 + ap->pio_mask = 0x7F;
14411 +#ifdef CONFIG_FSL_PATA_USE_DMA
14412 + ap->mwdma_mask = 0x7F;
14413 + ap->udma_mask = plat->udma_mask;
14414 + pata_fsl_sht.sg_tablesize = plat->max_sg;
14415 +#else
14416 + ap->mwdma_mask = 0x00;
14417 + ap->udma_mask = 0x00;
14418 +#endif
14419 + fsl_setup_port(&ap->ioaddr);
14420 +
14421 + /*
14422 + * Do platform-specific initialization (e.g. allocate pins,
14423 + * turn on clock). After this call it is assumed that
14424 + * plat->get_clk_rate() can be called to calculate
14425 + * timing.
14426 + */
14427 + if (plat->init && plat->init(pdev)) {
14428 + /* REVISIT: don't leak what ata_host_alloc() allocated */
14429 + return -ENODEV;
14430 + }
14431 +
14432 + /* Deassert the reset bit to enable the interface */
14433 + WRITE_ATA8(FSL_ATA_CTRL_ATA_RST_B, FSL_ATA_CONTROL);
14434 + mb();
14435 +
14436 + /* Set initial timing and mode */
14437 + set_ata_bus_timing(XFER_PIO_4, pdev);
14438 +
14439 +#ifdef CONFIG_FSL_PATA_USE_DMA
14440 + /* get DMA ready */
14441 + pata_fsl_dma_init(ap);
14442 +#endif
14443 +
14444 + /*
14445 + * Enable the ATA INTRQ interrupt from the bus, but
14446 + * only allow the CPU to see it (INTRQ2) at this point.
14447 + * INTRQ1, which goes to the DMA, will be enabled later.
14448 + */
14449 +#if 0
14450 + __raw_writel(FSL_ATA_INTR_ATA_INTRQ2, ata_regs + FSL_ATA_INT_EN);
14451 +#else
14452 + WRITE_ATA8(FSL_ATA_INTR_ATA_INTRQ2, FSL_ATA_INT_EN);
14453 +#endif
14454 + mb();
14455 +
14456 + /* activate */
14457 + ret = ata_host_activate(host, platform_get_irq(pdev, 0), ata_interrupt,
14458 + 0, &pata_fsl_sht);
14459 + DPRINTK("EXIT ret=%d\n", ret);
14460 + return ret;
14461 +}
14462 +
14463 +/**
14464 + * pata_fsl_remove - unplug a platform interface
14465 + * @pdev: platform device
14466 + *
14467 + * A platform bus ATA device has been unplugged. Perform the needed
14468 + * cleanup. Also called on module unload for any active devices.
14469 + */
14470 +static int __devexit pata_fsl_remove(struct platform_device *pdev)
14471 +{
14472 + struct device *dev = &pdev->dev;
14473 + struct ata_host *host = dev_get_drvdata(dev);
14474 + struct pata_fsl_priv *priv = host->private_data;
14475 + struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *)
14476 + pdev->dev.platform_data;
14477 + u8 *ata_regs = priv->fsl_ata_regs;
14478 +
14479 +#if 0
14480 + __raw_writel(0, ata_regs + FSL_ATA_INT_EN); /* Disable interrupts */
14481 +#else
14482 + WRITE_ATA8(0, FSL_ATA_INT_EN); /* Disable interrupts */
14483 +#endif
14484 + mb();
14485 +
14486 + ata_host_detach(host);
14487 +
14488 + if (plat->exit)
14489 + plat->exit();
14490 +
14491 + kfree(priv);
14492 +
14493 + return 0;
14494 +}
14495 +
14496 +#ifdef CONFIG_PM
14497 +static int pata_fsl_suspend(struct platform_device *pdev, pm_message_t state)
14498 +{
14499 + struct ata_host *host = dev_get_drvdata(&pdev->dev);
14500 + struct pata_fsl_priv *priv = host->private_data;
14501 + struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *)
14502 + pdev->dev.platform_data;
14503 + u8 *ata_regs = priv->fsl_ata_regs;
14504 +
14505 + /* Disable interrupts. */
14506 +#if 0
14507 + __raw_writel(0, ata_regs + FSL_ATA_INT_EN);
14508 +#else
14509 + WRITE_ATA8(0, FSL_ATA_INT_EN);
14510 +#endif
14511 + mb();
14512 +
14513 + if (plat->exit)
14514 + plat->exit();
14515 +
14516 + return 0;
14517 +}
14518 +
14519 +static int pata_fsl_resume(struct platform_device *pdev)
14520 +{
14521 + struct ata_host *host = dev_get_drvdata(&pdev->dev);
14522 + struct pata_fsl_priv *priv = host->private_data;
14523 + struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *)
14524 + pdev->dev.platform_data;
14525 + u8 *ata_regs = priv->fsl_ata_regs;
14526 +
14527 + if (plat->init && plat->init(pdev)) {
14528 + return -ENODEV;
14529 + }
14530 +
14531 + /* Deassert the reset bit to enable the interface */
14532 +#if 0
14533 + __raw_writel(FSL_ATA_CTRL_ATA_RST_B, ata_regs + FSL_ATA_CONTROL);
14534 +#else
14535 + WRITE_ATA8(FSL_ATA_CTRL_ATA_RST_B, FSL_ATA_CONTROL);
14536 +#endif
14537 + mb();
14538 +
14539 + /* Set initial timing and mode */
14540 + set_ata_bus_timing(XFER_PIO_4, pdev);
14541 +
14542 + /*
14543 + * Enable hardware interrupts.
14544 + */
14545 +#if 0
14546 + __raw_writel(FSL_ATA_INTR_ATA_INTRQ2, ata_regs + FSL_ATA_INT_EN);
14547 +#else
14548 + WRITE_ATA8(FSL_ATA_INTR_ATA_INTRQ2, FSL_ATA_INT_EN);
14549 +#endif
14550 + mb();
14551 +
14552 + return 0;
14553 +}
14554 +#endif
14555 +
14556 +static struct platform_driver pata_fsl_driver = {
14557 + .probe = pata_fsl_probe,
14558 + .remove = __devexit_p(pata_fsl_remove),
14559 +#ifdef CONFIG_PM
14560 + .suspend = pata_fsl_suspend,
14561 + .resume = pata_fsl_resume,
14562 +#endif
14563 + .driver = {
14564 + .name = DRV_NAME,
14565 + .owner = THIS_MODULE,
14566 + },
14567 +};
14568 +
14569 +static int __init pata_fsl_init(void)
14570 +{
14571 + int ret;
14572 +
14573 + DPRINTK("ENTER\n");
14574 + ret = platform_driver_register(&pata_fsl_driver);
14575 + DPRINTK("EXIT ret=%d\n", ret);
14576 + return ret;
14577 +}
14578 +
14579 +static void __exit pata_fsl_exit(void)
14580 +{
14581 + platform_driver_unregister(&pata_fsl_driver);
14582 +}
14583 +module_init(pata_fsl_init);
14584 +module_exit(pata_fsl_exit);
14585 +
14586 +MODULE_AUTHOR("Freescale Semiconductor, Inc.");
14587 +MODULE_DESCRIPTION("low-level driver for Freescale ATA");
14588 +MODULE_LICENSE("GPL");
14589 +MODULE_VERSION(DRV_VERSION);
14590 --- a/drivers/crypto/Kconfig
14591 +++ b/drivers/crypto/Kconfig
14592 @@ -60,6 +60,69 @@ config CRYPTO_DEV_GEODE
14593 To compile this driver as a module, choose M here: the module
14594 will be called geode-aes.
14595
14596 +config CRYPTO_DEV_MCFCAU
14597 + bool "Support for Freescale Coldfire Cryptographic Acceleration Unit (CAU)"
14598 + depends on M5445X
14599 + select CRYPTO_ALGAPI
14600 + help
14601 + The cryptographic acceleration unit (CAU) is a ColdFire coprocessor
14602 + implementing a set of specialized operations in hardware. For example, you can
14603 + find it on MCF5445X.
14604 +
14605 +config CRYPTO_DEV_MCFCAU_DES
14606 + tristate "DES and Triple DES cipher algorithms (MCF5445X)"
14607 + depends on CRYPTO_DEV_MCFCAU
14608 + select CRYPTO_ALGAPI
14609 + select CRYPTO_BLKCIPHER
14610 + help
14611 + DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3).
14612 +
14613 + Say 'Y' here to use the CAU coprocessor for
14614 + the CryptoAPI DES and 3DES alogrithms.
14615 +
14616 + To compile this driver as a module, choose M here: the module
14617 + will be called mcfcau-des.
14618 +
14619 +config CRYPTO_DEV_MCFCAU_AES
14620 + tristate "AES cipher algorithm (MCF5445X)"
14621 + depends on CRYPTO_DEV_MCFCAU
14622 + select CRYPTO_ALGAPI
14623 + select CRYPTO_BLKCIPHER
14624 + help
14625 + AES cipher algorithm (FIPS 197).
14626 +
14627 + Say 'Y' here to use the CAU coprocessor for
14628 + the CryptoAPI AES alogrithm.
14629 +
14630 + To compile this driver as a module, choose M here: the module
14631 + will be called mcfcau-aes.
14632 +
14633 +config CRYPTO_DEV_MCFCAU_MD5
14634 + tristate "MD5 digest algorithm (MCF5445X)"
14635 + depends on CRYPTO_DEV_MCFCAU
14636 + select CRYPTO_ALGAPI
14637 + help
14638 + MD5 message digest algorithm (RFC1321).
14639 +
14640 + Say 'Y' here to use the CAU coprocessor for
14641 + the CryptoAPI MD5 alogrithm.
14642 +
14643 + To compile this driver as a module, choose M here: the module
14644 + will be called mcfcau-md5.
14645 +
14646 +config CRYPTO_DEV_MCFCAU_SHA1
14647 + tristate "SHA1 digest algorithm (MCF5445X)"
14648 + depends on CRYPTO_DEV_MCFCAU
14649 + select CRYPTO_ALGAPI
14650 + help
14651 + SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2).
14652 +
14653 + Say 'Y' here to use the CAU coprocessor for
14654 + the CryptoAPI SHA1 alogrithm.
14655 +
14656 + To compile this driver as a module, choose M here: the module
14657 + will be called mcfcau-sha1.
14658 +
14659 config ZCRYPT
14660 tristate "Support for PCI-attached cryptographic adapters"
14661 depends on S390
14662 --- a/drivers/crypto/Makefile
14663 +++ b/drivers/crypto/Makefile
14664 @@ -2,3 +2,8 @@ obj-$(CONFIG_CRYPTO_DEV_PADLOCK_AES) +=
14665 obj-$(CONFIG_CRYPTO_DEV_PADLOCK_SHA) += padlock-sha.o
14666 obj-$(CONFIG_CRYPTO_DEV_GEODE) += geode-aes.o
14667 obj-$(CONFIG_CRYPTO_DEV_HIFN_795X) += hifn_795x.o
14668 +obj-$(CONFIG_CRYPTO_DEV_MCFCAU) += mcfcau.o
14669 +obj-$(CONFIG_CRYPTO_DEV_MCFCAU_DES) += mcfcau-des.o
14670 +obj-$(CONFIG_CRYPTO_DEV_MCFCAU_AES) += mcfcau-aes.o
14671 +obj-$(CONFIG_CRYPTO_DEV_MCFCAU_MD5) += mcfcau-md5.o
14672 +obj-$(CONFIG_CRYPTO_DEV_MCFCAU_SHA1) += mcfcau-sha1.o
14673 --- /dev/null
14674 +++ b/drivers/crypto/mcfcau-aes.c
14675 @@ -0,0 +1,311 @@
14676 + /***************************************************************************
14677 + * mcfcau-aes.c - Implementation of AES Cipher Algorithm
14678 + * for Freescale ColdFire Cryptographic Acceleration Unit (CAU).
14679 + *
14680 + * Author: Andrey Butok
14681 + * Copyright Freescale Semiconductor Inc. 2007
14682 + *
14683 + * NOTE: You can find the ColdFire CAU module on MCF5445X and MCF52235.
14684 + *
14685 + * This program is free software; you can redistribute it and/or modify it
14686 + * under the terms of the GNU General Public License as published by the
14687 + * Free Software Foundation; either version 2 of the License, or (at your
14688 + * option) any later version.
14689 + *
14690 + * This program is distributed in the hope that it will be useful, but
14691 + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14692 + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14693 + * for more details.
14694 + *
14695 + * You should have received a copy of the GNU General Public License
14696 + * along with this program; if not, write to the Free Software Foundation,
14697 + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
14698 + *
14699 + ***************************************************************************
14700 + * Changes:
14701 + * v0.01 17 September 2007 Andrey Butok
14702 + * Initial Release - developed on 2.6.20 Linux kernel.
14703 + */
14704 +
14705 +#include <linux/module.h>
14706 +#include <linux/init.h>
14707 +#include <linux/types.h>
14708 +#include <linux/errno.h>
14709 +#include <linux/crypto.h>
14710 +
14711 +/*
14712 +#undef DEBUG
14713 +#define DEBUG 1
14714 +*/
14715 +
14716 +#include "mcfcau.h"
14717 +
14718 +#define MCFCAU_AES_MIN_KEY_SIZE (16)
14719 +#define MCFCAU_AES_MAX_KEY_SIZE (32)
14720 +#define MCFCAU_AES_BLOCK_SIZE (16)
14721 +
14722 +#define MCFCAU_AES_DRIVER_DESC "AES ColdFire CAU driver"
14723 +#define MCFCAU_AES_DRIVER_VERSION "v0.01"
14724 +
14725 +struct mcfcau_aes_ctx {
14726 + int Nr_1;
14727 + u32 buf[120];
14728 + u32 buf_tmp[16];
14729 +};
14730 +
14731 +static u32 mcfcau_rco_tab[10]={ 0x01000000, 0x02000000, 0x04000000, 0x08000000,
14732 + 0x10000000, 0x20000000, 0x40000000, 0x80000000,
14733 + 0x1b000000, 0x36000000};
14734 +
14735 +int mcfcau_aes_setkey(struct crypto_tfm *tfm, const u8 *in_key,
14736 + unsigned int key_len)
14737 +{
14738 + struct mcfcau_aes_ctx *ctx = crypto_tfm_ctx(tfm);
14739 + const u32 * key = (const u32 *)in_key;
14740 + u32 *flags = &tfm->crt_flags;
14741 + u32 i;
14742 + u32* key_sch = (&ctx->buf[0]);
14743 + u32 * temp_p, * rcon_p;
14744 + u32 Nx;
14745 + u32 Nk;
14746 + unsigned long iflags;
14747 +
14748 + DBG("\n");
14749 +
14750 + if (key_len % 8) {
14751 + *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
14752 + return -EINVAL;
14753 + }
14754 +
14755 + Nk = key_len>>2;
14756 +
14757 + for(i=0;i<Nk;i++){
14758 + key_sch[i] = key[i];
14759 + }
14760 +
14761 + ctx->Nr_1 = Nk+5;
14762 +
14763 + /* Key Expansion */
14764 + temp_p=&key_sch[Nk-1];
14765 + rcon_p=&mcfcau_rco_tab[0];
14766 +
14767 + spin_lock_irqsave(&mcfcau_lock, iflags);
14768 +
14769 + asm volatile ("move.l %0, %%a1"::"m"(temp_p):"a1");
14770 + asm volatile ("move.l %0, %%a3"::"m"(rcon_p):"a3");
14771 + asm volatile ("move.l %0, %%a4"::"m"(key_sch):"a4");
14772 +
14773 + Nx=(Nk+7)<<2; /* (Nr+1)*Nb */
14774 +
14775 + for(i=Nk; i<Nx; i++)
14776 + {
14777 + /* temp = key_sch[Nk-1] */
14778 + asm volatile ("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CAA):"a1");
14779 +
14780 + if(i%Nk==0){
14781 + asm volatile ("moveq #8, %%d0":::"d0");
14782 + /* CAA=RotWord(temp) */
14783 + asm volatile ("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA):"d0");
14784 + /* SubWord(CAA) */
14785 + asm volatile ("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_AESS+MCFCAU_CAA));
14786 + /* ACC xor rcon[i/Nk] */
14787 + asm volatile ("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_XOR+MCFCAU_CAA):"a3");
14788 +
14789 + }else if((Nk>6) && (i%Nk ==4)){
14790 + /* SubWord(ACC) */
14791 + asm volatile ("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_AESS+MCFCAU_CAA));
14792 + }
14793 +
14794 + /* key_sch[i]^=key_sch[i-Nk]; store ACC to key_sch[i] */
14795 + asm volatile ("cp0ld.l (%%a4)+,%%d0,#1,%0" ::"n"(MCFCAU_XOR+MCFCAU_CAA):"a4");
14796 + asm volatile ("cp0st.l %%d0,(%%a1),#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CAA));
14797 + }
14798 + spin_unlock_irqrestore(&mcfcau_lock, iflags);
14799 +
14800 + return 0;
14801 +}
14802 +
14803 +
14804 +/* encrypt a block of text */
14805 +static void mcfcau_aes_encrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
14806 +{
14807 + struct mcfcau_aes_ctx *ctx = crypto_tfm_ctx(tfm);
14808 + const int Nr_1 = ctx->Nr_1;
14809 +
14810 + u32* key_sch = &(ctx->buf[0]);
14811 + u32 i;
14812 + unsigned long iflags;
14813 +
14814 + DBG("\n");
14815 +
14816 + spin_lock_irqsave(&mcfcau_lock, iflags);
14817 + asm("move.l %0, %%a1"::"m"(in):"a1");
14818 + asm("move.l %0, %%a0"::"m"(key_sch):"a0");
14819 + /* state=in */
14820 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA0):"a1");
14821 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA1):"a1");
14822 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA2):"a1");
14823 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA3):"a1");
14824 + /* AddRoundKey() */
14825 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_XOR+MCFCAU_CA0):"a0");
14826 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_XOR+MCFCAU_CA1):"a0");
14827 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_XOR+MCFCAU_CA2):"a0");
14828 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_XOR+MCFCAU_CA3):"a0");
14829 +
14830 + for(i=Nr_1;i>0;i--){
14831 + /* SubBytes(state) */
14832 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_AESS+MCFCAU_CA0));
14833 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_AESS+MCFCAU_CA1));
14834 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_AESS+MCFCAU_CA2));
14835 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_AESS+MCFCAU_CA3));
14836 + /* ShiftRows(state) */
14837 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_AESR));
14838 + /* MixColumns(state); AddRoundKey() */
14839 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_AESC+MCFCAU_CA0):"a0");
14840 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_AESC+MCFCAU_CA1):"a0");
14841 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_AESC+MCFCAU_CA2):"a0");
14842 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_AESC+MCFCAU_CA3):"a0");
14843 + }
14844 + /* SubBytes(state)*/
14845 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_AESS+MCFCAU_CA0));
14846 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_AESS+MCFCAU_CA1));
14847 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_AESS+MCFCAU_CA2));
14848 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_AESS+MCFCAU_CA3));
14849 + /* ShiftRows(state) */
14850 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_AESR));
14851 + /* AddRoundKey() */
14852 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_XOR+MCFCAU_CA0):"a0");
14853 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_XOR+MCFCAU_CA1):"a0");
14854 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_XOR+MCFCAU_CA2):"a0");
14855 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_XOR+MCFCAU_CA3):"a0");
14856 + /* out = state */
14857 + asm("move.l %0, %%a1" ::"m"(out):"a1");
14858 + asm("cp0st.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CA0):"d0");
14859 + asm("cp0st.l %%d0,%%d1,#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CA1):"d1");
14860 +
14861 + asm("move.l %%d0,(%%a1)+":::"a1");
14862 + asm("move.l %%d1,(%%a1)+":::"a1");
14863 +
14864 + asm("cp0st.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CA2):"d0");
14865 + asm("cp0st.l %%d0,%%d1,#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CA3):"d1");
14866 +
14867 + asm("move.l %%d0,(%%a1)+":::"a1");
14868 + asm("move.l %%d1,(%%a1)+":::"a1");
14869 + spin_unlock_irqrestore(&mcfcau_lock, iflags);
14870 +}
14871 +
14872 +
14873 +/* decrypt a block of text */
14874 +static void mcfcau_aes_decrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
14875 +{
14876 + struct mcfcau_aes_ctx *ctx = crypto_tfm_ctx(tfm);
14877 + u32* key_sch = &(ctx->buf[0]);
14878 + u32 i;
14879 + unsigned long iflags;
14880 + const int Nr_1 = ctx->Nr_1;
14881 + key_sch=&key_sch[(Nr_1+2)*4];
14882 +
14883 + DBG("\n");
14884 +
14885 + spin_lock_irqsave(&mcfcau_lock, iflags);
14886 +
14887 + asm("move.l %0, %%a1"::"m"(in):"a1");
14888 + asm("move.l %0, %%a0"::"m"(key_sch):"a0");
14889 + /* state=in */
14890 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA0):"a1");
14891 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA1):"a1");
14892 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA2):"a1");
14893 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA3):"a1");
14894 + /* AddRoundKey() */
14895 + asm("cp0ld.l -(%%a0),%%d0,#1,%0" ::"n"(MCFCAU_XOR+MCFCAU_CA3):"a0");
14896 + asm("cp0ld.l -(%%a0),%%d0,#1,%0" ::"n"(MCFCAU_XOR+MCFCAU_CA2):"a0");
14897 + asm("cp0ld.l -(%%a0),%%d0,#1,%0" ::"n"(MCFCAU_XOR+MCFCAU_CA1):"a0");
14898 + asm("cp0ld.l -(%%a0),%%d0,#1,%0" ::"n"(MCFCAU_XOR+MCFCAU_CA0):"a0");
14899 +
14900 + for(i=Nr_1;i>0;i--){
14901 + /* InvShiftRows(state) */
14902 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_AESIR));
14903 + /* InvSubBytes(state) */
14904 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_AESIS+MCFCAU_CA3));
14905 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_AESIS+MCFCAU_CA2));
14906 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_AESIS+MCFCAU_CA1));
14907 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_AESIS+MCFCAU_CA0));
14908 + /* InvMixColumns(state); AddRoundKey() */
14909 + asm("cp0ld.l -(%%a0),%%d0,#1,%0" ::"n"(MCFCAU_AESIC+MCFCAU_CA3):"a0");
14910 + asm("cp0ld.l -(%%a0),%%d0,#1,%0" ::"n"(MCFCAU_AESIC+MCFCAU_CA2):"a0");
14911 + asm("cp0ld.l -(%%a0),%%d0,#1,%0" ::"n"(MCFCAU_AESIC+MCFCAU_CA1):"a0");
14912 + asm("cp0ld.l -(%%a0),%%d0,#1,%0" ::"n"(MCFCAU_AESIC+MCFCAU_CA0):"a0");
14913 + }
14914 + /* InvShiftRows(state) */
14915 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_AESIR));
14916 + /* InvSubBytes(state)*/
14917 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_AESIS+MCFCAU_CA3));
14918 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_AESIS+MCFCAU_CA2));
14919 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_AESIS+MCFCAU_CA1));
14920 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_AESIS+MCFCAU_CA0));
14921 + /* AddRoundKey() */
14922 + asm("cp0ld.l -(%%a0),%%d0,#1,%0" ::"n"(MCFCAU_XOR+MCFCAU_CA3):"a0");
14923 + asm("cp0ld.l -(%%a0),%%d0,#1,%0" ::"n"(MCFCAU_XOR+MCFCAU_CA2):"a0");
14924 + asm("cp0ld.l -(%%a0),%%d0,#1,%0" ::"n"(MCFCAU_XOR+MCFCAU_CA1):"a0");
14925 + asm("cp0ld.l -(%%a0),%%d0,#1,%0" ::"n"(MCFCAU_XOR+MCFCAU_CA0):"a0");
14926 + /* out = state */
14927 + asm("move.l %0, %%a1" ::"m"(out):"a1");
14928 + asm("cp0st.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CA0):"d0");
14929 + asm("cp0st.l %%d0,%%d1,#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CA1):"d1");
14930 +
14931 + asm("move.l %%d0,(%%a1)+":::"a1");
14932 + asm("move.l %%d1,(%%a1)+":::"a1");
14933 +
14934 + asm("cp0st.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CA2):"d0");
14935 + asm("cp0st.l %%d0,%%d1,#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CA3):"d1");
14936 +
14937 + asm("move.l %%d0,(%%a1)+":::"a1");
14938 + asm("move.l %%d1,(%%a1)+":::"a1");
14939 + spin_unlock_irqrestore(&mcfcau_lock, iflags);
14940 +
14941 +}
14942 +
14943 +
14944 +static struct crypto_alg mcfcau_aes_alg = {
14945 + .cra_name = "aes",
14946 + .cra_driver_name = "aes-mcfcau",
14947 + .cra_priority = MCFCAU_CRA_PRIORITY,
14948 + .cra_flags = CRYPTO_ALG_TYPE_CIPHER,
14949 + .cra_blocksize = MCFCAU_AES_BLOCK_SIZE,
14950 + .cra_ctxsize = sizeof(struct mcfcau_aes_ctx),
14951 + .cra_alignmask = 3,
14952 + .cra_module = THIS_MODULE,
14953 + .cra_list = LIST_HEAD_INIT(mcfcau_aes_alg.cra_list),
14954 + .cra_u = {
14955 + .cipher = {
14956 + .cia_min_keysize = MCFCAU_AES_MIN_KEY_SIZE,
14957 + .cia_max_keysize = MCFCAU_AES_MAX_KEY_SIZE,
14958 + .cia_setkey = mcfcau_aes_setkey,
14959 + .cia_encrypt = mcfcau_aes_encrypt,
14960 + .cia_decrypt = mcfcau_aes_decrypt
14961 + }
14962 + }
14963 +};
14964 +
14965 +static int __init mcfcau_aes_init(void)
14966 +{
14967 + int ret = crypto_register_alg(&mcfcau_aes_alg);
14968 +
14969 + printk(KERN_INFO MCFCAU_AES_DRIVER_DESC " "
14970 + MCFCAU_AES_DRIVER_VERSION " %s.\n",ret?"failed":"registered");
14971 + return ret;
14972 +}
14973 +
14974 +static void __exit mcfcau_aes_fini(void)
14975 +{
14976 + crypto_unregister_alg(&mcfcau_aes_alg);
14977 + printk(KERN_INFO MCFCAU_AES_DRIVER_DESC " "
14978 + MCFCAU_AES_DRIVER_VERSION " unregistered.\n");
14979 +}
14980 +
14981 +module_init(mcfcau_aes_init);
14982 +module_exit(mcfcau_aes_fini);
14983 +
14984 +MODULE_DESCRIPTION(MCFCAU_AES_DRIVER_DESC);
14985 +MODULE_LICENSE("Dual BSD/GPL");
14986 +MODULE_AUTHOR("Andrey Butok");
14987 --- /dev/null
14988 +++ b/drivers/crypto/mcfcau.c
14989 @@ -0,0 +1,32 @@
14990 +/***************************************************************************
14991 + * mcfcau.c - Implementation of DES & Triple DES EDE Cipher Algorithms
14992 + * for Freescale ColdFire Cryptographic Acceleration Unit (CAU).
14993 + *
14994 + * Author: Andrey Butok
14995 + * Copyright Freescale Semiconductor Inc. 2007
14996 + *
14997 + * NOTE: You can find the ColdFire CAU module on MCF5445X and MCF52235.
14998 + *
14999 + * This program is free software; you can redistribute it and/or modify it
15000 + * under the terms of the GNU General Public License as published by the
15001 + * Free Software Foundation; either version 2 of the License, or (at your
15002 + * option) any later version.
15003 + *
15004 + * This program is distributed in the hope that it will be useful, but
15005 + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15006 + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15007 + * for more details.
15008 + *
15009 + * You should have received a copy of the GNU General Public License
15010 + * along with this program; if not, write to the Free Software Foundation,
15011 + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
15012 + *
15013 + ***************************************************************************
15014 + * Changes:
15015 + * v0.01 28 September 2006 Andrey Butok
15016 + * Initial Release - developed on 2.6.20 Linux kernel.
15017 + */
15018 +#include <linux/module.h>
15019 +
15020 +DEFINE_SPINLOCK(mcfcau_lock);
15021 +EXPORT_SYMBOL(mcfcau_lock);
15022 --- /dev/null
15023 +++ b/drivers/crypto/mcfcau-des.c
15024 @@ -0,0 +1,437 @@
15025 +/***************************************************************************
15026 + * mcfcau-des.c - Implementation of DES & Triple DES EDE Cipher Algorithms
15027 + * for Freescale ColdFire Cryptographic Acceleration Unit (CAU).
15028 + *
15029 + * Author: Andrey Butok
15030 + * Copyright Freescale Semiconductor Inc. 2007
15031 + *
15032 + * NOTE: You can find the ColdFire CAU module on MCF5445X and MCF52235.
15033 + *
15034 + * This program is free software; you can redistribute it and/or modify it
15035 + * under the terms of the GNU General Public License as published by the
15036 + * Free Software Foundation; either version 2 of the License, or (at your
15037 + * option) any later version.
15038 + *
15039 + * This program is distributed in the hope that it will be useful, but
15040 + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15041 + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15042 + * for more details.
15043 + *
15044 + * You should have received a copy of the GNU General Public License
15045 + * along with this program; if not, write to the Free Software Foundation,
15046 + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
15047 + *
15048 + ***************************************************************************
15049 + * Changes:
15050 + * v0.01 14 August 2007 Andrey Butok
15051 + * Initial Release - developed on 2.6.20 Linux kernel.
15052 + */
15053 +
15054 +#include <linux/init.h>
15055 +#include <linux/module.h>
15056 +#include <linux/errno.h>
15057 +#include <linux/crypto.h>
15058 +#include <linux/types.h>
15059 +
15060 +/*
15061 +#undef DEBUG
15062 +#define DEBUG 1
15063 +*/
15064 +
15065 +#include "mcfcau.h"
15066 +
15067 +#define MCFCAU_DES_KEY_SIZE (8)
15068 +#define MCFCAU_DES_EXPKEY_WORDS (32)
15069 +#define MCFCAU_DES_BLOCK_SIZE (8)
15070 +
15071 +#define MCFCAU_DES3_EDE_KEY_SIZE (3 * MCFCAU_DES_KEY_SIZE)
15072 +#define MCFCAU_DES3_EDE_EXPKEY_WORDS (3 * MCFCAU_DES_EXPKEY_WORDS)
15073 +#define MCFCAU_DES3_EDE_BLOCK_SIZE (MCFCAU_DES_BLOCK_SIZE)
15074 +
15075 +#define MCFCAU_DES_DRIVER_DESC "DES & 3DES ColdFire CAU driver"
15076 +#define MCFCAU_DES_DRIVER_VERSION "v0.01"
15077 +
15078 +struct mcfcau_des_ctx {
15079 + u32 expkey[MCFCAU_DES_EXPKEY_WORDS];
15080 +};
15081 +
15082 +struct mcfcau_des3_ede_ctx {
15083 + u32 expkey[MCFCAU_DES3_EDE_EXPKEY_WORDS];
15084 +};
15085 +
15086 +/* DES round operations */
15087 +static inline void mcfcau_des_encipher(void)
15088 +{
15089 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESK));
15090 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_IP+MCFCAU_KSL1));
15091 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSL2));
15092 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSL2));
15093 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSL2));
15094 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSL2));
15095 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSL2));
15096 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSL2));
15097 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSL1));
15098 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSL2));
15099 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSL2));
15100 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSL2));
15101 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSL2));
15102 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSL2));
15103 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSL2));
15104 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSL1));
15105 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_FP+MCFCAU_KSL1));
15106 +}
15107 +
15108 +static inline void mcfcau_des_decipher(void)
15109 +{
15110 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESK+MCFCAU_DC));
15111 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_IP+MCFCAU_KSR1));
15112 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSR2));
15113 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSR2));
15114 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSR2));
15115 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSR2));
15116 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSR2));
15117 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSR2));
15118 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSR1));
15119 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSR2));
15120 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSR2));
15121 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSR2));
15122 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSR2));
15123 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSR2));
15124 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSR2));
15125 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_KSR1));
15126 + asm("cp0ld.l %%d0,%%d0,#1,%0"::"n"(MCFCAU_DESR+MCFCAU_FP+MCFCAU_KSL1));
15127 +}
15128 +
15129 +
15130 +static int mcfcau_des_setkey(struct crypto_tfm *tfm, const u8 *key_p,
15131 + unsigned int keylen)
15132 +{
15133 + struct mcfcau_des_ctx *dctx = crypto_tfm_ctx(tfm);
15134 + u32 *flags = &tfm->crt_flags;
15135 + u32 * key = (u32 *) key_p;
15136 +
15137 + DBG("\n");
15138 +
15139 + /*
15140 + * RFC2451: Weak key checks SHOULD be performed.
15141 + *
15142 + * FIPS 74:
15143 + * Keys having duals are keys which produce all zeros, all ones, or
15144 + * alternating zero-one patterns in the C and D registers after Permuted
15145 + * Choice 1 has operated on the key.
15146 + *
15147 + */
15148 + if(*flags & CRYPTO_TFM_REQ_WEAK_KEY){ /* FIPS 74 */
15149 + if(key[0]<0xE001E00l){
15150 + if(key[0]<0x1FE01FE0){
15151 + if(key[0]<0x01E001E0){
15152 + if(((key[0]==0x01010101)&&(key[1]==0x01010101))||
15153 + ((key[0]==0x011F011F)&&(key[1]==0x010E010E)) )
15154 + goto WEAK_KEY;
15155 + }
15156 + else{
15157 + if(((key[0]==0x01E001E0)&&(key[1]==0x01F101F1))||
15158 + ((key[0]==0x01FE01FE)&&(key[1]==0x01FE01FE)) )
15159 + goto WEAK_KEY;
15160 + }
15161 + }
15162 + else{
15163 + if(key[0]<0x1F1F1F1F){
15164 + if(((key[0]==0x1FE01FE0)&&(key[1]==0x0EF10EF1))||
15165 + ((key[0]==0x1F011F0l)&&(key[1]==0x0E010E01)) )
15166 + goto WEAK_KEY;
15167 + }
15168 + else{
15169 + if(((key[0]==0x1F1F1F1F)&&(key[1]==0x0E0E0E0E))||
15170 + ((key[0]==0x1FFE1FFE)&&(key[1]==0x0EFE0EFE)) )
15171 + goto WEAK_KEY;
15172 + }
15173 + }
15174 + } else {
15175 + if(key[0]<0xFE01FE01){
15176 + if(key[0]<0xE0E0E0E0){
15177 + if(((key[0]==0xE001E00l)&&(key[1]==0xF101F101))||
15178 + ((key[0]==0xE01FE01F)&&(key[1]==0xF10EF10E)) )
15179 + goto WEAK_KEY;
15180 + }
15181 + else{
15182 + if(((key[0]==0xE0E0E0E0)&&(key[1]==0xF1F1F1F1))||
15183 + ((key[0]==0xE0FEE0FE)&&(key[1]==0xF1FEF1FE)) )
15184 + goto WEAK_KEY;
15185 + }
15186 + }
15187 + else{
15188 + if(key[0]<0xFEE0FEE0){
15189 + if(((key[0]==0xFE01FE01)&&(key[1]==0xFE01FE01))||
15190 + ((key[0]==0xFE1FFE1F)&&(key[1]==0xFE0EFE0E)) )
15191 + goto WEAK_KEY;
15192 + }
15193 + else{
15194 + if(((key[0]==0xFEE0FEE0)&&(key[1]==0xFEF1FEF1))||
15195 + ((key[0]==0xFEFEFEFE)&&(key[1]==0xFEFEFEFE)) )
15196 + goto WEAK_KEY;
15197 + }
15198 + }
15199 + }
15200 + }
15201 + memcpy(dctx->expkey, key_p, keylen);
15202 + return 0;
15203 +WEAK_KEY:
15204 + *flags |= CRYPTO_TFM_RES_WEAK_KEY;
15205 + return -EINVAL;
15206 +}
15207 +
15208 +
15209 +void mcfcau_des_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
15210 +{
15211 + struct mcfcau_des_ctx *ctx = crypto_tfm_ctx(tfm);
15212 + u32 * des_key_tmp = ctx->expkey;
15213 + unsigned long iflags;
15214 +
15215 + DBG("\n");
15216 +
15217 + spin_lock_irqsave(&mcfcau_lock, iflags);
15218 +
15219 + asm("move.l %0, %%a0"::"m"(src):"a0");
15220 + asm("move.l %0, %%a1"::"m"(des_key_tmp):"a1");
15221 +
15222 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA2):"a0");
15223 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA3));
15224 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA0):"a1");
15225 + asm("cp0ld.l (%%a1),%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA1));
15226 +
15227 + mcfcau_des_encipher();
15228 +
15229 + asm("cp0st.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CA2):"d0");
15230 + asm("cp0st.l %%d0,%%d1,#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CA3):"d1");
15231 + asm("move.l %0, %%a1" ::"m"(dst):"a1");
15232 + asm("move.l %d0,(%a1)+");
15233 + asm("move.l %d1,(%a1)");
15234 +
15235 + spin_unlock_irqrestore(&mcfcau_lock, iflags);
15236 +}
15237 +
15238 +
15239 +void mcfcau_des_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
15240 +{
15241 + struct mcfcau_des_ctx *ctx = crypto_tfm_ctx(tfm);
15242 + u32 * des_key_tmp = ctx->expkey;
15243 + unsigned long iflags;
15244 +
15245 + DBG("\n");
15246 +
15247 + spin_lock_irqsave(&mcfcau_lock, iflags);
15248 +
15249 + asm("move.l %0, %%a0"::"m"(src):"a0");
15250 + asm("move.l %0, %%a1"::"m"(des_key_tmp):"a1");
15251 +
15252 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA2):"a0");
15253 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA3));
15254 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA0):"a1");
15255 + asm("cp0ld.l (%%a1),%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA1));
15256 +
15257 + mcfcau_des_decipher();
15258 +
15259 + asm("move.l %0, %%a1" ::"m"(dst):"a1");
15260 + asm("cp0st.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CA2):"d0");
15261 + asm("cp0st.l %%d0,%%d1,#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CA3):"d1");
15262 + asm("move.l %d0,(%a1)+");
15263 + asm("move.l %d1,(%a1)");
15264 +
15265 + spin_unlock_irqrestore(&mcfcau_lock, iflags);
15266 +}
15267 +
15268 +
15269 +/*
15270 + * RFC2451:
15271 + *
15272 + * For DES-EDE3, there is no known need to reject weak or
15273 + * complementation keys. Any weakness is obviated by the use of
15274 + * multiple keys.
15275 + *
15276 + * However, if the first two or last two independent 64-bit keys are
15277 + * equal (k1 == k2 or k2 == k3), then the DES3 operation is simply the
15278 + * same as DES. Implementers MUST reject keys that exhibit this
15279 + * property.
15280 + *
15281 + */
15282 +
15283 +static int mcfcau_des3_ede_setkey(struct crypto_tfm *tfm, const u8 *key_p, unsigned int keylen)
15284 +{
15285 + const u32 *key = (const u32 *)key_p;
15286 + struct mcfcau_des3_ede_ctx *dctx = crypto_tfm_ctx(tfm);
15287 + u32 *flags = &tfm->crt_flags;
15288 +
15289 +DBG("\n");
15290 +
15291 + if (unlikely(!((key[0] ^ key[2]) | (key[1] ^ key[3])) ||
15292 + !((key[2] ^ key[4]) | (key[3] ^ key[5]))))
15293 + {
15294 + *flags |= CRYPTO_TFM_RES_BAD_KEY_SCHED;
15295 + return -EINVAL;
15296 + }
15297 +
15298 + memcpy(dctx->expkey,key_p,keylen);
15299 +
15300 + return 0;
15301 +}
15302 +
15303 +static void mcfcau_des3_ede_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
15304 +{
15305 + struct mcfcau_des3_ede_ctx *dctx = crypto_tfm_ctx(tfm);
15306 + const u32 * des_key_tmp = dctx->expkey;
15307 + unsigned long iflags;
15308 +
15309 + DBG("\n");
15310 +
15311 + spin_lock_irqsave(&mcfcau_lock, iflags);
15312 +
15313 + /*EK1*/
15314 + asm("move.l %0, %%a0"::"m"(src):"a0");
15315 + asm("move.l %0, %%a1"::"m"(des_key_tmp):"a1");
15316 +
15317 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA2):"a0");
15318 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA3));
15319 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA0):"a1");
15320 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA1):"a1");
15321 +
15322 + mcfcau_des_encipher();
15323 +
15324 + /*DK2*/
15325 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA0):"a1");
15326 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA1):"a1");
15327 +
15328 + mcfcau_des_decipher();
15329 +
15330 + /*EK3*/
15331 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA0):"a1");
15332 + asm("cp0ld.l (%%a1),%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA1));
15333 +
15334 + mcfcau_des_encipher();
15335 +
15336 + asm("move.l %0, %%a1" ::"m"(dst):"a1");
15337 + asm("cp0st.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CA2):"d0");
15338 + asm("cp0st.l %%d0,%%d1,#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CA3):"d1");
15339 + asm("move.l %d0,(%a1)+");
15340 + asm("move.l %d1,(%a1)");
15341 +
15342 + spin_unlock_irqrestore(&mcfcau_lock, iflags);
15343 +}
15344 +
15345 +static void mcfcau_des3_ede_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
15346 +{
15347 + struct mcfcau_des3_ede_ctx *dctx = crypto_tfm_ctx(tfm);
15348 + const u32 * des_key_tmp = dctx->expkey + 6 - 2;
15349 + unsigned long iflags;
15350 +
15351 + DBG("\n");
15352 +
15353 + spin_lock_irqsave(&mcfcau_lock, iflags);
15354 +
15355 + /*DK3*/
15356 + asm("move.l %0, %%a0"::"m"(src):"a0");
15357 + asm("move.l %0, %%a1"::"m"(des_key_tmp):"a1");
15358 +
15359 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA2):"a0");
15360 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA3));
15361 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA0):"a1");
15362 + asm("cp0ld.l (%%a1),%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA1));
15363 +
15364 + mcfcau_des_decipher();
15365 +
15366 + /*EK2*/
15367 + asm("suba.l #12,%a1"); /*dec key pointer*/
15368 +
15369 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA0):"a1");
15370 + asm("cp0ld.l (%%a1),%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA1));
15371 +
15372 + mcfcau_des_encipher();
15373 +
15374 + /*DK1*/
15375 + asm("suba.l #12,%a1"); /*dec key pointer*/
15376 +
15377 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA0):"a1");
15378 + asm("cp0ld.l (%%a1),%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA1));
15379 +
15380 + mcfcau_des_decipher();
15381 +
15382 + asm("move.l %0, %%a1" ::"m"(dst):"a1");
15383 + asm("cp0st.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CA2):"d0");
15384 + asm("cp0st.l %%d0,%%d1,#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CA3):"d1");
15385 + asm("move.l %d0,(%a1)+");
15386 + asm("move.l %d1,(%a1)");
15387 +
15388 + spin_unlock_irqrestore(&mcfcau_lock, iflags);
15389 +}
15390 +
15391 +
15392 +static struct crypto_alg mcfcau_des_alg = {
15393 + .cra_name = "des",
15394 + .cra_driver_name = "des-mcfcau",
15395 + .cra_priority = MCFCAU_CRA_PRIORITY,
15396 + .cra_flags = CRYPTO_ALG_TYPE_CIPHER,
15397 + .cra_blocksize = MCFCAU_DES_BLOCK_SIZE,
15398 + .cra_ctxsize = sizeof(struct mcfcau_des_ctx),
15399 + .cra_module = THIS_MODULE,
15400 + .cra_alignmask = 3,
15401 + .cra_list = LIST_HEAD_INIT(mcfcau_des_alg.cra_list),
15402 + .cra_u = { .cipher = {
15403 + .cia_min_keysize = MCFCAU_DES_KEY_SIZE,
15404 + .cia_max_keysize = MCFCAU_DES_KEY_SIZE,
15405 + .cia_setkey = mcfcau_des_setkey,
15406 + .cia_encrypt = mcfcau_des_encrypt,
15407 + .cia_decrypt = mcfcau_des_decrypt } }
15408 +};
15409 +
15410 +static struct crypto_alg mcfcau_des3_ede_alg = {
15411 + .cra_name = "des3_ede",
15412 + .cra_driver_name = "des3_ede-mcfcau",
15413 + .cra_priority = MCFCAU_CRA_PRIORITY,
15414 + .cra_flags = CRYPTO_ALG_TYPE_CIPHER,
15415 + .cra_blocksize = MCFCAU_DES3_EDE_BLOCK_SIZE,
15416 + .cra_ctxsize = sizeof(struct mcfcau_des3_ede_ctx),
15417 + .cra_module = THIS_MODULE,
15418 + .cra_alignmask = 3,
15419 + .cra_list = LIST_HEAD_INIT(mcfcau_des3_ede_alg.cra_list),
15420 + .cra_u = { .cipher = {
15421 + .cia_min_keysize = MCFCAU_DES3_EDE_KEY_SIZE,
15422 + .cia_max_keysize = MCFCAU_DES3_EDE_KEY_SIZE,
15423 + .cia_setkey = mcfcau_des3_ede_setkey,
15424 + .cia_encrypt = mcfcau_des3_ede_encrypt,
15425 + .cia_decrypt = mcfcau_des3_ede_decrypt } }
15426 +};
15427 +
15428 +MODULE_ALIAS("mcfcau_des3_ede");
15429 +
15430 +static int __init mcfcau_des_init(void)
15431 +{
15432 + int ret;
15433 +
15434 + ret = crypto_register_alg(&mcfcau_des_alg);
15435 + if (ret < 0)
15436 + goto out;
15437 +
15438 + ret = crypto_register_alg(&mcfcau_des3_ede_alg);
15439 + if (ret < 0)
15440 + crypto_unregister_alg(&mcfcau_des_alg);
15441 +out:
15442 + printk(KERN_INFO MCFCAU_DES_DRIVER_DESC " "
15443 + MCFCAU_DES_DRIVER_VERSION " %s.\n",ret?"failed":"registered");
15444 + return ret;
15445 +}
15446 +
15447 +static void __exit mcfcau_des_exit(void)
15448 +{
15449 + crypto_unregister_alg(&mcfcau_des3_ede_alg);
15450 + crypto_unregister_alg(&mcfcau_des_alg);
15451 +
15452 + printk(KERN_INFO MCFCAU_DES_DRIVER_DESC " "
15453 + MCFCAU_DES_DRIVER_VERSION " unregistered.\n");
15454 +}
15455 +
15456 +module_init(mcfcau_des_init);
15457 +module_exit(mcfcau_des_exit);
15458 +
15459 +MODULE_LICENSE("GPL");
15460 +MODULE_DESCRIPTION("DES & Triple DES EDE Cipher Algorithms for ColdFire CAU");
15461 +MODULE_AUTHOR("Andrey Butok");
15462 --- /dev/null
15463 +++ b/drivers/crypto/mcfcau.h
15464 @@ -0,0 +1,98 @@
15465 +/***************************************************************************
15466 + * mcfcau.h - Common header file for Freescale ColdFire
15467 + * Cryptographic Acceleration Unit (CAU) drivers.
15468 + *
15469 + * Author: Andrey Butok
15470 + * Copyright Freescale Semiconductor Inc. 2007
15471 + *
15472 + * NOTE: You can find the ColdFire CAU module on MCF5445X and MCF52235.
15473 + *
15474 + * This program is free software; you can redistribute it and/or modify it
15475 + * under the terms of the GNU General Public License as published by the
15476 + * Free Software Foundation; either version 2 of the License, or (at your
15477 + * option) any later version.
15478 + *
15479 + * This program is distributed in the hope that it will be useful, but
15480 + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15481 + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15482 + * for more details.
15483 + *
15484 + * You should have received a copy of the GNU General Public License
15485 + * along with this program; if not, write to the Free Software Foundation,
15486 + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
15487 + *
15488 + ***************************************************************************
15489 + * Changes:
15490 + * v0.01 14 August 2007 Andrey Butok
15491 + */
15492 +
15493 +#ifndef MCFCAU_H
15494 +#define MCFCAU_H
15495 +
15496 +#include <linux/spinlock.h>
15497 +
15498 +/* CAU Registers (CAx) */
15499 +#define MCFCAU_CASR (0x0)
15500 +#define MCFCAU_CAA (0x1)
15501 +#define MCFCAU_CA0 (0x2)
15502 +#define MCFCAU_CA1 (0x3)
15503 +#define MCFCAU_CA2 (0x4)
15504 +#define MCFCAU_CA3 (0x5)
15505 +#define MCFCAU_CA4 (0x6)
15506 +#define MCFCAU_CA5 (0x7)
15507 +
15508 + /* CAU Commands */
15509 +#define MCFCAU_CNOP (0x000)
15510 +#define MCFCAU_LDR (0x010)
15511 +#define MCFCAU_STR (0x020)
15512 +#define MCFCAU_ADR (0x030)
15513 +#define MCFCAU_RADR (0x040)
15514 +#define MCFCAU_ADRA (0x050)
15515 +#define MCFCAU_XOR (0x060)
15516 +#define MCFCAU_ROTL (0x070)
15517 +#define MCFCAU_MVRA (0x080)
15518 +#define MCFCAU_MVAR (0x090)
15519 +#define MCFCAU_AESS (0x0A0)
15520 +#define MCFCAU_AESIS (0x0B0)
15521 +#define MCFCAU_AESC (0x0C0)
15522 +#define MCFCAU_AESIC (0x0D0)
15523 +#define MCFCAU_AESR (0x0E0)
15524 +#define MCFCAU_AESIR (0x0F0)
15525 +#define MCFCAU_DESR (0x100)
15526 +#define MCFCAU_DESK (0x110)
15527 +#define MCFCAU_HASH (0x120)
15528 +#define MCFCAU_SHS (0x130)
15529 +#define MCFCAU_MDS (0x140)
15530 +#define MCFCAU_ILL (0x1F0)
15531 +
15532 +/* DESR Fields */
15533 +#define MCFCAU_IP (0x08) /* initial permutation */
15534 +#define MCFCAU_FP (0x04) /* final permutation */
15535 +#define MCFCAU_KSL1 (0x00) /* key schedule left 1 bit */
15536 +#define MCFCAU_KSL2 (0x01) /* key schedule left 2 bits */
15537 +#define MCFCAU_KSR1 (0x02) /* key schedule right 1 bit */
15538 +#define MCFCAU_KSR2 (0x03) /* key schedule right 2 bits */
15539 +
15540 +/* DESK Field */
15541 +#define MCFCAU_DC (0x01) /* decrypt key schedule */
15542 +#define MCFCAU_CP (0x02) /* check parity */
15543 +
15544 +/* HASH Functions Codes */
15545 +#define MCFCAU_HFF (0x0) /* MD5 F() CA1&CA2 | ~CA1&CA3 */
15546 +#define MCFCAU_HFG (0x1) /* MD5 G() CA1&CA3 | CA2&~CA3 */
15547 +#define MCFCAU_HFH (0x2) /* MD5 H(), SHA Parity() CA1^CA2^CA3 */
15548 +#define MCFCAU_HFI (0x3) /* MD5 I() CA2^(CA1|~CA3) */
15549 +#define MCFCAU_HFC (0x4) /* SHA Ch() CA1&CA2 ^ ~CA1&CA3 */
15550 +#define MCFCAU_HFM (0x5) /* SHA Maj() CA1&CA2 ^ CA1&CA3 ^ CA2&CA3 */
15551 +
15552 +#define MCFCAU_CRA_PRIORITY (300)
15553 +
15554 +extern spinlock_t mcfcau_lock;
15555 +
15556 +#ifdef DEBUG
15557 +#define DBG(fmt, args...) printk( "[%s] " fmt , __FUNCTION__, ## args)
15558 +#else
15559 +#define DBG(fmt, args...) do{}while(0)
15560 +#endif
15561 +
15562 +#endif
15563 --- /dev/null
15564 +++ b/drivers/crypto/mcfcau-md5.c
15565 @@ -0,0 +1,654 @@
15566 + /***************************************************************************
15567 + * mcfcau-md5.c - Implementation of MD5 Message Digest Algorithm (RFC1321)
15568 + * for Freescale ColdFire Cryptographic Acceleration Unit (CAU).
15569 + *
15570 + * Author: Andrey Butok
15571 + * Copyright Freescale Semiconductor Inc. 2007
15572 + *
15573 + * NOTE: You can find the ColdFire CAU module on MCF5445X and MCF52235.
15574 + *
15575 + * This program is free software; you can redistribute it and/or modify it
15576 + * under the terms of the GNU General Public License as published by the
15577 + * Free Software Foundation; either version 2 of the License, or (at your
15578 + * option) any later version.
15579 + *
15580 + * This program is distributed in the hope that it will be useful, but
15581 + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15582 + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15583 + * for more details.
15584 + *
15585 + * You should have received a copy of the GNU General Public License
15586 + * along with this program; if not, write to the Free Software Foundation,
15587 + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
15588 + *
15589 + ***************************************************************************
15590 + * Changes:
15591 + * v0.01 30 September 2007 Andrey Butok
15592 + * Initial Release - developed on 2.6.20 Linux kernel.
15593 + */
15594 +#include <linux/init.h>
15595 +#include <linux/module.h>
15596 +#include <linux/string.h>
15597 +#include <linux/crypto.h>
15598 +#include <linux/types.h>
15599 +#include <asm/byteorder.h>
15600 +
15601 +/*
15602 +#undef DEBUG
15603 +#define DEBUG 1
15604 +*/
15605 +
15606 +#include "mcfcau.h"
15607 +
15608 +
15609 +#define MCFCAU_MD5_DIGEST_SIZE (16)
15610 +#define MCFCAU_MD5_HMAC_BLOCK_SIZE (64)
15611 +#define MCFCAU_MD5_BLOCK_WORDS (16)
15612 +#define MCFCAU_MD5_HASH_WORDS (4)
15613 +
15614 +#define MCFCAU_MD5_DRIVER_DESC "MD5 ColdFire CAU driver"
15615 +#define MCFCAU_MD5_DRIVER_VERSION "v0.01"
15616 +
15617 +
15618 +struct mcfcau_md5_ctx {
15619 + u32 hash[MCFCAU_MD5_HASH_WORDS];
15620 + u32 block[MCFCAU_MD5_BLOCK_WORDS];
15621 + u64 byte_count;
15622 +};
15623 +
15624 +u32 mcfcau_md5_t[64]={0xd76aa478, 0xe8c7b756, 0x242070db, 0xc1bdceee,
15625 + 0xf57c0faf, 0x4787c62a, 0xa8304613, 0xfd469501,
15626 + 0x698098d8, 0x8b44f7af, 0xffff5bb1, 0x895cd7be,
15627 + 0x6b901122, 0xfd987193, 0xa679438e, 0x49b40821,
15628 + 0xf61e2562, 0xc040b340, 0x265e5a51, 0xe9b6c7aa,
15629 + 0xd62f105d, 0x02441453, 0xd8a1e681, 0xe7d3fbc8,
15630 + 0x21e1cde6, 0xc33707d6, 0xf4d50d87, 0x455a14ed,
15631 + 0xa9e3e905, 0xfcefa3f8, 0x676f02d9, 0x8d2a4c8a,
15632 + 0xfffa3942, 0x8771f681, 0x6d9d6122, 0xfde5380c,
15633 + 0xa4beea44, 0x4bdecfa9, 0xf6bb4b60, 0xbebfbc70,
15634 + 0x289b7ec6, 0xeaa127fa, 0xd4ef3085, 0x04881d05,
15635 + 0xd9d4d039, 0xe6db99e5, 0x1fa27cf8, 0xc4ac5665,
15636 + 0xf4292244, 0x432aff97, 0xab9423a7, 0xfc93a039,
15637 + 0x655b59c3, 0x8f0ccc92, 0xffeff47d, 0x85845dd1,
15638 + 0x6fa87e4f, 0xfe2ce6e0, 0xa3014314, 0x4e0811a1,
15639 + 0xf7537e82, 0xbd3af235, 0x2ad7d2bb, 0xeb86d391};
15640 +
15641 +
15642 +
15643 +static void mcfcau_md5_transform(u32 *hash, u32 const *in)
15644 +{
15645 + int i;
15646 + u32 * md5_t_p=&mcfcau_md5_t[0];
15647 + unsigned long iflags;
15648 +
15649 + spin_lock_irqsave(&mcfcau_lock, iflags);
15650 + asm("move.l %0, %%a1"::"m"(hash):"a1");
15651 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CAA):"a1");/*a*/
15652 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA1):"a1");/*b*/
15653 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA2):"a1");/*c*/
15654 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA3):"a1");/*d*/
15655 + asm("move.l %0, %%a0"::"m"(in):"a0"); /* X[] */
15656 + asm("move.l %0, %%a3"::"m"(md5_t_p):"a3"); /* T[] */
15657 +
15658 +
15659 + /* Round 1 */
15660 + asm("moveq.l #7, %%d4":::"d4"); /* for rotating by 7 */
15661 + asm("moveq.l #12, %%d5":::"d5"); /* for rotating by 12 */
15662 + asm("moveq.l #17, %%d6":::"d6"); /* for rotating by 17 */
15663 + asm("moveq.l #22, %%d7":::"d7"); /* for rotating by 22 */
15664 +
15665 + for(i=0; i<4;i++){
15666 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFF)); /* a+F(b,c,d) */
15667 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0"); /* add byterev x[i] */
15668 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3"); /* add t[i] */
15669 + asm("cp0ld.l %%d4,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA)); /* rotate by 7 */
15670 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1)); /* add b */
15671 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS)); /* register to register shift */
15672 +
15673 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFF));
15674 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15675 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15676 + asm("cp0ld.l %%d5,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15677 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15678 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15679 +
15680 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFF));
15681 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15682 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15683 + asm("cp0ld.l %%d6,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15684 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15685 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15686 +
15687 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFF));
15688 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15689 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15690 + asm("cp0ld.l %%d7,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15691 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15692 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15693 + };
15694 +
15695 +
15696 + /* Round 2 */
15697 + asm("moveq.l #5, %%d4":::"d4"); /* for rotating by 5 */
15698 + asm("moveq.l #9, %%d5":::"d5"); /* for rotating by 9 */
15699 + asm("moveq.l #14, %%d6":::"d6"); /* for rotating by 14 */
15700 + asm("moveq.l #20, %%d7":::"d7"); /* for rotating by 20 */
15701 +
15702 + asm("lea -60(%%a0),%%a0":::"a0");
15703 +
15704 + for(i=0; i<2;i++){
15705 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFG));
15706 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15707 + asm("lea 20(%%a0),%%a0" :::"a0");
15708 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15709 + asm("cp0ld.l %%d4,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15710 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15711 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15712 +
15713 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFG));
15714 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15715 + asm("lea 20(%%a0),%%a0" :::"a0");
15716 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15717 + asm("cp0ld.l %%d5,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15718 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15719 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15720 +
15721 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFG));
15722 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15723 + asm("lea -44(%%a0),%%a0" :::"a0");
15724 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15725 + asm("cp0ld.l %%d6,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15726 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15727 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15728 +
15729 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFG));
15730 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15731 + asm("lea 20(%%a0),%%a0" :::"a0");
15732 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15733 + asm("cp0ld.l %%d7,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15734 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15735 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15736 + };
15737 +
15738 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFG));
15739 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15740 + asm("lea 20(%%a0),%%a0" :::"a0");
15741 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15742 + asm("cp0ld.l %%d4,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15743 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15744 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15745 +
15746 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFG));
15747 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15748 + asm("lea -44(%%a0),%%a0" :::"a0");
15749 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15750 + asm("cp0ld.l %%d5,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15751 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15752 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15753 +
15754 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFG));
15755 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15756 + asm("lea 20(%%a0),%%a0" :::"a0");
15757 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15758 + asm("cp0ld.l %%d6,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15759 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15760 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15761 +
15762 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFG));
15763 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15764 + asm("lea 20(%%a0),%%a0" :::"a0");
15765 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15766 + asm("cp0ld.l %%d7,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15767 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15768 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15769 +
15770 +
15771 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFG));
15772 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15773 + asm("lea -44(%%a0),%%a0" :::"a0");
15774 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15775 + asm("cp0ld.l %%d4,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15776 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15777 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15778 +
15779 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFG));
15780 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15781 + asm("lea 20(%%a0),%%a0" :::"a0");
15782 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15783 + asm("cp0ld.l %%d5,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15784 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15785 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15786 +
15787 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFG));
15788 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15789 + asm("lea 20(%%a0),%%a0" :::"a0");
15790 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15791 + asm("cp0ld.l %%d6,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15792 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15793 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15794 +
15795 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFG));
15796 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15797 + asm("lea -28(%%a0),%%a0" :::"a0");
15798 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15799 + asm("cp0ld.l %%d7,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15800 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15801 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15802 +
15803 +
15804 + /* Round 3 */
15805 + asm("moveq.l #4, %%d4":::"d4"); /* for rotating by 5 */
15806 + asm("moveq.l #11, %%d5":::"d5"); /* for rotating by 9 */
15807 + asm("moveq.l #16, %%d6":::"d6"); /* for rotating by 14 */
15808 + asm("moveq.l #23, %%d7":::"d7"); /* for rotating by 20 */
15809 +
15810 +
15811 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFH));
15812 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15813 + asm("lea 12(%%a0),%%a0" :::"a0");
15814 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15815 + asm("cp0ld.l %%d4,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15816 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15817 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15818 +
15819 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFH));
15820 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15821 + asm("lea 12(%%a0),%%a0" :::"a0");
15822 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15823 + asm("cp0ld.l %%d5,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15824 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15825 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15826 +
15827 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFH));
15828 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15829 + asm("lea 12(%%a0),%%a0" :::"a0");
15830 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15831 + asm("cp0ld.l %%d6,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15832 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15833 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15834 +
15835 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFH));
15836 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15837 + asm("lea -52(%%a0),%%a0" :::"a0");
15838 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15839 + asm("cp0ld.l %%d7,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15840 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15841 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15842 +
15843 +
15844 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFH));
15845 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15846 + asm("lea 12(%%a0),%%a0" :::"a0");
15847 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15848 + asm("cp0ld.l %%d4,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15849 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15850 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15851 +
15852 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFH));
15853 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15854 + asm("lea 12(%%a0),%%a0" :::"a0");
15855 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15856 + asm("cp0ld.l %%d5,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15857 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15858 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15859 +
15860 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFH));
15861 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15862 + asm("lea 12(%%a0),%%a0" :::"a0");
15863 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15864 + asm("cp0ld.l %%d6,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15865 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15866 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15867 +
15868 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFH));
15869 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15870 + asm("lea 12(%%a0),%%a0" :::"a0");
15871 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15872 + asm("cp0ld.l %%d7,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15873 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15874 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15875 +
15876 +
15877 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFH));
15878 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15879 + asm("lea -52(%%a0),%%a0" :::"a0");
15880 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15881 + asm("cp0ld.l %%d4,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15882 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15883 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15884 +
15885 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFH));
15886 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15887 + asm("lea 12(%%a0),%%a0" :::"a0");
15888 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15889 + asm("cp0ld.l %%d5,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15890 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15891 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15892 +
15893 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFH));
15894 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15895 + asm("lea 12(%%a0),%%a0" :::"a0");
15896 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15897 + asm("cp0ld.l %%d6,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15898 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15899 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15900 +
15901 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFH));
15902 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15903 + asm("lea 12(%%a0),%%a0" :::"a0");
15904 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15905 + asm("cp0ld.l %%d7,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15906 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15907 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15908 +
15909 +
15910 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFH));
15911 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15912 + asm("lea 12(%%a0),%%a0" :::"a0");
15913 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15914 + asm("cp0ld.l %%d4,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15915 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15916 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15917 +
15918 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFH));
15919 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15920 + asm("lea 12(%%a0),%%a0" :::"a0");
15921 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15922 + asm("cp0ld.l %%d5,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15923 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15924 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15925 +
15926 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFH));
15927 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15928 + asm("lea -52(%%a0),%%a0" :::"a0");
15929 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15930 + asm("cp0ld.l %%d6,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15931 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15932 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15933 +
15934 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFH));
15935 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15936 + asm("lea -8(%%a0),%%a0" :::"a0");
15937 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15938 + asm("cp0ld.l %%d7,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15939 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15940 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15941 +
15942 +
15943 + /* Round 4 */
15944 + asm("moveq.l #6, %%d4":::"d4"); /* for rotating by 6 */
15945 + asm("moveq.l #10, %%d5":::"d5"); /* for rotating by 10 */
15946 + asm("moveq.l #15, %%d6":::"d6"); /* for rotating by 15 */
15947 + asm("moveq.l #21, %%d7":::"d7"); /* for rotating by 21 */
15948 +
15949 +
15950 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFI));
15951 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15952 + asm("lea 28(%%a0),%%a0" :::"a0");
15953 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15954 + asm("cp0ld.l %%d4,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15955 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15956 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15957 +
15958 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFI));
15959 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15960 + asm("lea 28(%%a0),%%a0" :::"a0");
15961 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15962 + asm("cp0ld.l %%d5,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15963 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15964 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15965 +
15966 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFI));
15967 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15968 + asm("lea -36(%%a0),%%a0" :::"a0");
15969 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15970 + asm("cp0ld.l %%d6,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15971 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15972 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15973 +
15974 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFI));
15975 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15976 + asm("lea 28(%%a0),%%a0" :::"a0");
15977 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15978 + asm("cp0ld.l %%d7,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15979 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15980 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15981 +
15982 +
15983 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFI));
15984 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15985 + asm("lea -36(%%a0),%%a0" :::"a0");
15986 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15987 + asm("cp0ld.l %%d4,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15988 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15989 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15990 +
15991 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFI));
15992 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
15993 + asm("lea 28(%%a0),%%a0" :::"a0");
15994 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
15995 + asm("cp0ld.l %%d5,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
15996 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
15997 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
15998 +
15999 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFI));
16000 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
16001 + asm("lea -36(%%a0),%%a0" :::"a0");
16002 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
16003 + asm("cp0ld.l %%d6,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
16004 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
16005 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
16006 +
16007 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFI));
16008 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
16009 + asm("lea 28(%%a0),%%a0" :::"a0");
16010 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
16011 + asm("cp0ld.l %%d7,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
16012 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
16013 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
16014 +
16015 +
16016 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFI));
16017 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
16018 + asm("lea 28(%%a0),%%a0" :::"a0");
16019 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
16020 + asm("cp0ld.l %%d4,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
16021 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
16022 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
16023 +
16024 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFI));
16025 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
16026 + asm("lea -36(%%a0),%%a0" :::"a0");
16027 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
16028 + asm("cp0ld.l %%d5,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
16029 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
16030 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
16031 +
16032 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFI));
16033 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
16034 + asm("lea 28(%%a0),%%a0" :::"a0");
16035 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
16036 + asm("cp0ld.l %%d6,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
16037 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
16038 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
16039 +
16040 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFI));
16041 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
16042 + asm("lea -36(%%a0),%%a0" :::"a0");
16043 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
16044 + asm("cp0ld.l %%d7,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
16045 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
16046 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
16047 +
16048 +
16049 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFI));
16050 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
16051 + asm("lea 28(%%a0),%%a0" :::"a0");
16052 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
16053 + asm("cp0ld.l %%d4,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
16054 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
16055 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
16056 +
16057 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFI));
16058 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
16059 + asm("lea -36(%%a0),%%a0" :::"a0");
16060 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
16061 + asm("cp0ld.l %%d5,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
16062 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
16063 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
16064 +
16065 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFI));
16066 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
16067 + asm("lea 28(%%a0),%%a0" :::"a0");
16068 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
16069 + asm("cp0ld.l %%d6,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
16070 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
16071 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
16072 +
16073 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFI));
16074 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_RADR+MCFCAU_CAA):"a0");
16075 + asm("lea 28(%%a0),%%a0" :::"a0");
16076 + asm("cp0ld.l (%%a3)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a3");
16077 + asm("cp0ld.l %%d7,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA));
16078 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA1));
16079 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MDS));
16080 +
16081 +
16082 + asm("move.l %0, %%a1"::"m"(hash):"a1");
16083 +
16084 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a1");/*a*/
16085 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CA1):"a1");/*b*/
16086 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CA2):"a1");/*c*/
16087 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CA3):"a1");/*d*/
16088 +
16089 + asm("cp0st.l %%d0,-(%%a1),#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CA3):"a1");/*d*/
16090 + asm("cp0st.l %%d0,-(%%a1),#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CA2):"a1");/*c*/
16091 + asm("cp0st.l %%d0,-(%%a1),#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CA1):"a1");/*b*/
16092 + asm("cp0st.l %%d0,-(%%a1),#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CAA):"a1");/*a*/
16093 + spin_unlock_irqrestore(&mcfcau_lock, iflags);
16094 +}
16095 +
16096 +static inline void le32_to_cpu_array(u32 *buf, unsigned int words)
16097 +{
16098 + while (words--) {
16099 + __le32_to_cpus(buf);
16100 + buf++;
16101 + }
16102 +}
16103 +
16104 +static inline void cpu_to_le32_array(u32 *buf, unsigned int words)
16105 +{
16106 + while (words--) {
16107 + __cpu_to_le32s(buf);
16108 + buf++;
16109 + }
16110 +}
16111 +
16112 +static void mcfcau_md5_initialization(struct crypto_tfm *tfm)
16113 +{
16114 + struct mcfcau_md5_ctx *mctx = crypto_tfm_ctx(tfm);
16115 +
16116 + DBG("\n");
16117 + mctx->hash[0] = 0x67452301;
16118 + mctx->hash[1] = 0xefcdab89;
16119 + mctx->hash[2] = 0x98badcfe;
16120 + mctx->hash[3] = 0x10325476;
16121 + mctx->byte_count = 0;
16122 +}
16123 +
16124 +static void mcfcau_md5_update(struct crypto_tfm *tfm, const u8 *data, unsigned int len)
16125 +{
16126 + struct mcfcau_md5_ctx *mctx = crypto_tfm_ctx(tfm);
16127 + const u32 avail = sizeof(mctx->block) - (mctx->byte_count & 0x3f);
16128 +
16129 + DBG("\n");
16130 + mctx->byte_count += len;
16131 +
16132 + if (avail > len) {
16133 + memcpy((char *)mctx->block + (sizeof(mctx->block) - avail),
16134 + data, len);
16135 + }
16136 + else {
16137 + memcpy((char *)mctx->block + (sizeof(mctx->block) - avail), data, avail);
16138 +
16139 + mcfcau_md5_transform(mctx->hash, mctx->block);
16140 + data += avail;
16141 + len -= avail;
16142 +
16143 + while (len >= sizeof(mctx->block)) {
16144 + memcpy(mctx->block, data, sizeof(mctx->block));
16145 + mcfcau_md5_transform(mctx->hash, mctx->block);
16146 + data += sizeof(mctx->block);
16147 + len -= sizeof(mctx->block);
16148 + }
16149 +
16150 + memcpy(mctx->block, data, len);
16151 + }
16152 +}
16153 +
16154 +static void mcfcau_md5_final(struct crypto_tfm *tfm, u8 *out)
16155 +{
16156 + struct mcfcau_md5_ctx *mctx = crypto_tfm_ctx(tfm);
16157 + const unsigned int offset = mctx->byte_count & 0x3f;
16158 + char *p = (char *)mctx->block + offset;
16159 + int padding = 56 - (offset + 1);
16160 +
16161 + DBG("\n");
16162 +
16163 + *p++ = 0x80;
16164 + if (padding < 0) {
16165 + memset(p, 0x00, padding + sizeof (u64));
16166 + mcfcau_md5_transform(mctx->hash, mctx->block);
16167 + p = (char *)mctx->block;
16168 + padding = 56;
16169 + }
16170 +
16171 + memset(p, 0, padding);
16172 + mctx->block[14] = mctx->byte_count << 3;
16173 + mctx->block[15] = mctx->byte_count >> 29;
16174 + le32_to_cpu_array(&mctx->block[14], 2);
16175 +
16176 + mcfcau_md5_transform(mctx->hash, mctx->block);
16177 +
16178 + cpu_to_le32_array(mctx->hash, sizeof(mctx->hash) / sizeof(u32));
16179 + memcpy(out, mctx->hash, sizeof(mctx->hash));
16180 + memset(mctx, 0, sizeof(*mctx));
16181 +}
16182 +
16183 +static struct crypto_alg mcfcau_md5_alg = {
16184 + .cra_name = "md5",
16185 + .cra_driver_name = "md5-mcfcau",
16186 + .cra_priority = MCFCAU_CRA_PRIORITY,
16187 + .cra_flags = CRYPTO_ALG_TYPE_DIGEST,
16188 + .cra_blocksize = MCFCAU_MD5_HMAC_BLOCK_SIZE,
16189 + .cra_ctxsize = sizeof(struct mcfcau_md5_ctx),
16190 + .cra_module = THIS_MODULE,
16191 + .cra_list = LIST_HEAD_INIT(mcfcau_md5_alg.cra_list),
16192 + .cra_u = { .digest = {
16193 + .dia_digestsize = MCFCAU_MD5_DIGEST_SIZE,
16194 + .dia_init = mcfcau_md5_initialization,
16195 + .dia_update = mcfcau_md5_update,
16196 + .dia_final = mcfcau_md5_final } }
16197 +};
16198 +
16199 +static int __init mcfcau_md5_init(void)
16200 +{
16201 + int ret = crypto_register_alg(&mcfcau_md5_alg);
16202 + printk(KERN_INFO MCFCAU_MD5_DRIVER_DESC " "
16203 + MCFCAU_MD5_DRIVER_VERSION " %s.\n",ret?"failed":"registered");
16204 + return ret;
16205 +}
16206 +
16207 +static void __exit mcfcau_md5_exit(void)
16208 +{
16209 + crypto_unregister_alg(&mcfcau_md5_alg);
16210 + printk(KERN_INFO MCFCAU_MD5_DRIVER_DESC " "
16211 + MCFCAU_MD5_DRIVER_VERSION " unregistered.\n");
16212 +}
16213 +
16214 +module_init(mcfcau_md5_init);
16215 +module_exit(mcfcau_md5_exit);
16216 +
16217 +MODULE_LICENSE("GPL");
16218 +MODULE_DESCRIPTION(MCFCAU_MD5_DRIVER_DESC);
16219 +MODULE_AUTHOR("Andrey Butok");
16220 --- /dev/null
16221 +++ b/drivers/crypto/mcfcau-sha1.c
16222 @@ -0,0 +1,280 @@
16223 + /***************************************************************************
16224 + * mcfcau-sha1.c - Implementation of SHA1 Secure Hash Algorithm
16225 + * for Freescale ColdFire Cryptographic Acceleration Unit (CAU).
16226 + *
16227 + * Author: Andrey Butok
16228 + * Copyright Freescale Semiconductor Inc. 2007
16229 + *
16230 + * NOTE: You can find the ColdFire CAU module on MCF5445X and MCF52235.
16231 + *
16232 + * This program is free software; you can redistribute it and/or modify it
16233 + * under the terms of the GNU General Public License as published by the
16234 + * Free Software Foundation; either version 2 of the License, or (at your
16235 + * option) any later version.
16236 + *
16237 + * This program is distributed in the hope that it will be useful, but
16238 + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16239 + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16240 + * for more details.
16241 + *
16242 + * You should have received a copy of the GNU General Public License
16243 + * along with this program; if not, write to the Free Software Foundation,
16244 + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
16245 + *
16246 + ***************************************************************************
16247 + * Changes:
16248 + * v0.01 15 October 2007 Andrey Butok
16249 + * Initial Release - developed on 2.6.20 Linux kernel.
16250 + */
16251 +
16252 +#include <linux/init.h>
16253 +#include <linux/module.h>
16254 +#include <linux/mm.h>
16255 +#include <linux/crypto.h>
16256 +#include <linux/types.h>
16257 +
16258 +
16259 +/*
16260 +#undef DEBUG
16261 +#define DEBUG 1
16262 +*/
16263 +
16264 +#include "mcfcau.h"
16265 +
16266 +#define MCFCAU_SHA1_DIGEST_WORDS (5)
16267 +#define MCFCAU_SHA1_WORKSPACE_WORDS (80)
16268 +
16269 +#define MCFCAU_SHA1_DIGEST_SIZE (20)
16270 +#define MCFCAU_SHA1_HMAC_BLOCK_SIZE (64)
16271 +
16272 +#define MCFCAU_SHA1_DRIVER_DESC "SHA1 ColdFire CAU driver"
16273 +#define MCFCAU_SHA1_DRIVER_VERSION "v0.01"
16274 +
16275 +struct mcfcau_sha1_ctx {
16276 + u64 count;
16277 + u32 state[5];
16278 + u8 buffer[64];
16279 +};
16280 +
16281 +const static u32 K[4]={0x5A827999L, /* Rounds 0-19: sqrt(2) * 2^30 */
16282 + 0x6ED9EBA1L, /* Rounds 20-39: sqrt(3) * 2^30 */
16283 + 0x8F1BBCDCL, /* Rounds 40-59: sqrt(5) * 2^30 */
16284 + 0xCA62C1D6L}; /* Rounds 60-79: sqrt(10) * 2^30 */
16285 +
16286 +static void noinline mcfcau_sha1_transform(__u32 *digest, const char *in, __u32 *W)
16287 +{
16288 + int i;
16289 + u32 * tmp_p;
16290 + unsigned long iflags;
16291 +
16292 + /* (a) Devide M(i) into 16 words W */
16293 + for (i = 0; i < 16; i++)
16294 + W[i] = ((const u32 *)in)[i];
16295 +
16296 + /* (b) W[i+16] = S^1(W[i+13] ^ W[i+8] ^ W[i+2] ^ W[i]) */
16297 + tmp_p=&W[16];
16298 +
16299 + spin_lock_irqsave(&mcfcau_lock, iflags);
16300 + asm("move.l %0, %%a0"::"m"(tmp_p):"a0");
16301 + asm("moveq.l #1, %%d3":::"d3");
16302 +
16303 + for (i = 0; i < 64; i++){
16304 + asm("cp0ld.l -64(%%a0),%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA0));
16305 + asm("cp0ld.l -56(%%a0),%%d0,#1,%0" ::"n"(MCFCAU_XOR+MCFCAU_CA0));
16306 + asm("cp0ld.l -32(%%a0),%%d0,#1,%0" ::"n"(MCFCAU_XOR+MCFCAU_CA0));
16307 + asm("cp0ld.l -12(%%a0),%%d0,#1,%0" ::"n"(MCFCAU_XOR+MCFCAU_CA0));
16308 + asm("cp0ld.l %%d3,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CA0):"d3");
16309 + asm("cp0st.l %%d0,(%%a0)+,#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CA0));
16310 + }
16311 +
16312 + /* (c) */
16313 + asm("move.l %0, %%a0"::"m"(digest):"a0");
16314 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA0):"a0"); /* a */
16315 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA1):"a0"); /* b */
16316 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA2):"a0"); /* c */
16317 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA3):"a0"); /* d */
16318 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_LDR+MCFCAU_CA4):"a0"); /* e */
16319 +
16320 + /* (d) */
16321 + asm("moveq.l #5, %%d0":::"d0");
16322 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_MVRA+MCFCAU_CA0));
16323 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ROTL+MCFCAU_CAA)); /*S^5(A)*/
16324 +
16325 + tmp_p=(u32*)K;
16326 + asm("move.l %0, %%a0"::"m"(tmp_p):"a0");
16327 + asm("move.l %0, %%a1"::"m"(W):"a1");
16328 +
16329 + for (i = 0; i < 20; i++) {
16330 + /* t = f1(b, c, d) + K1 + rol32(a, 5) + e + W[i]; */
16331 + /* e = d; d = c; c = rol32(b, 30); b = a; a = t; */
16332 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFC)); /*f(b,c,d)*/
16333 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA4)); /*+e*/
16334 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA)); /*+K*/
16335 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a1"); /*+W*/
16336 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_SHS));
16337 + }
16338 +
16339 + asm("add.l #4,%%a0" :::"a0"); /* update K */
16340 +
16341 + for (; i < 40; i ++) {
16342 + /* t = f2(b, c, d) + K2 + rol32(a, 5) + e + W[i]; */
16343 + /* e = d; d = c; c = rol32(b, 30); b = a; a = t; */
16344 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFH)); /*f(b,c,d)*/
16345 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA4)); /*+e*/
16346 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA)); /*+K*/
16347 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a1"); /*+W*/
16348 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_SHS));
16349 + }
16350 +
16351 + asm("add.l #4,%%a0" :::"a0"); /* update K */
16352 +
16353 + for (; i < 60; i ++) {
16354 + /* t = f3(b, c, d) + K3 + rol32(a, 5) + e + W[i]; */
16355 + /* e = d; d = c; c = rol32(b, 30); b = a; a = t; */
16356 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFM)); /*f(b,c,d)*/
16357 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA4)); /*+e*/
16358 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA)); /*+K*/
16359 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a1"); /*+W*/
16360 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_SHS));
16361 + }
16362 +
16363 + asm("add.l #4,%%a0" :::"a0"); /* update K */
16364 +
16365 + for (; i < 80; i ++) {
16366 + /* t = f2(b, c, d) + K4 + rol32(a, 5) + e + W[i]; */
16367 + /* e = d; d = c; c = rol32(b, 30); b = a; a = t; */
16368 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_HASH+MCFCAU_HFH)); /*f(b,c,d)*/
16369 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_ADRA+MCFCAU_CA4)); /*+e*/
16370 + asm("cp0ld.l (%%a0),%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA)); /*+K*/
16371 + asm("cp0ld.l (%%a1)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CAA):"a1"); /*+W*/
16372 + asm("cp0ld.l %%d0,%%d0,#1,%0" ::"n"(MCFCAU_SHS));
16373 + }
16374 +
16375 + /* (e) */
16376 + asm("move.l %0, %%a0"::"m"(digest):"a0");
16377 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CA0):"a0"); /* +a */
16378 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CA1):"a0"); /* +b */
16379 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CA2):"a0"); /* +c */
16380 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CA3):"a0"); /* +d */
16381 + asm("cp0ld.l (%%a0)+,%%d0,#1,%0" ::"n"(MCFCAU_ADR+MCFCAU_CA4):"a0"); /* +e */
16382 +
16383 + asm("cp0st.l %%d0,-(%%a0),#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CA4):"a0");
16384 + asm("cp0st.l %%d0,-(%%a0),#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CA3):"a0");
16385 + asm("cp0st.l %%d0,-(%%a0),#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CA2):"a0");
16386 + asm("cp0st.l %%d0,-(%%a0),#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CA1):"a0");
16387 + asm("cp0st.l %%d0,-(%%a0),#1,%0" ::"n"(MCFCAU_STR+MCFCAU_CA0):"a0");
16388 + spin_unlock_irqrestore(&mcfcau_lock, iflags);
16389 +}
16390 +
16391 +static void mcfcau_sha1_init(struct crypto_tfm *tfm)
16392 +{
16393 + struct mcfcau_sha1_ctx *sctx = crypto_tfm_ctx(tfm);
16394 + static const struct mcfcau_sha1_ctx initstate = {
16395 + 0,
16396 + { 0x67452301, 0xEFCDAB89, 0x98BADCFE, 0x10325476, 0xC3D2E1F0 },
16397 + { 0, }
16398 + };
16399 +
16400 + *sctx = initstate;
16401 +}
16402 +
16403 +static void mcfcau_sha1_update(struct crypto_tfm *tfm, const u8 *data,
16404 + unsigned int len)
16405 +{
16406 + struct mcfcau_sha1_ctx *sctx = crypto_tfm_ctx(tfm);
16407 + unsigned int partial, done;
16408 + const u8 *src;
16409 +
16410 + partial = sctx->count & 0x3f;
16411 + sctx->count += len;
16412 + done = 0;
16413 + src = data;
16414 +
16415 + if ((partial + len) > 63) {
16416 + u32 temp[MCFCAU_SHA1_WORKSPACE_WORDS];
16417 +
16418 + if (partial) {
16419 + done = -partial;
16420 + memcpy(sctx->buffer + partial, data, done + 64);
16421 + src = sctx->buffer;
16422 + }
16423 +
16424 + do {
16425 + mcfcau_sha1_transform(sctx->state, src, temp);
16426 + done += 64;
16427 + src = data + done;
16428 + } while (done + 63 < len);
16429 +
16430 + memset(temp, 0, sizeof(temp));
16431 + partial = 0;
16432 + }
16433 + memcpy(sctx->buffer + partial, src, len - done);
16434 +}
16435 +
16436 +
16437 +/* Add padding and return the message digest. */
16438 +static void mcfcau_sha1_final(struct crypto_tfm *tfm, u8 *out)
16439 +{
16440 + struct mcfcau_sha1_ctx *sctx = crypto_tfm_ctx(tfm);
16441 + u32 *dst = (u32 *)out;
16442 + u32 i, index, padlen;
16443 + u64 bits;
16444 + static const u8 padding[64] = { 0x80, };
16445 +
16446 + bits = sctx->count << 3;
16447 +
16448 + /* Pad out to 56 mod 64 */
16449 + index = sctx->count & 0x3f;
16450 + padlen = (index < 56) ? (56 - index) : ((64+56) - index);
16451 + mcfcau_sha1_update(tfm, padding, padlen);
16452 +
16453 + /* Append length */
16454 + mcfcau_sha1_update(tfm, (const u8 *)&bits, sizeof(bits));
16455 +
16456 + /* Store state in digest */
16457 + for (i = 0; i < 5; i++)
16458 + dst[i] = sctx->state[i];
16459 +
16460 +
16461 + /* Wipe context */
16462 + memset(sctx, 0, sizeof *sctx);
16463 +}
16464 +
16465 +static struct crypto_alg mcfcau_sha1_alg = {
16466 + .cra_name = "sha1",
16467 + .cra_driver_name= "sha1-mcfcau",
16468 + .cra_priority = MCFCAU_CRA_PRIORITY,
16469 + .cra_flags = CRYPTO_ALG_TYPE_DIGEST,
16470 + .cra_blocksize = MCFCAU_SHA1_HMAC_BLOCK_SIZE,
16471 + .cra_ctxsize = sizeof(struct mcfcau_sha1_ctx),
16472 + .cra_module = THIS_MODULE,
16473 + .cra_alignmask = 3,
16474 + .cra_list = LIST_HEAD_INIT(mcfcau_sha1_alg.cra_list),
16475 + .cra_u = { .digest = {
16476 + .dia_digestsize = MCFCAU_SHA1_DIGEST_SIZE,
16477 + .dia_init = mcfcau_sha1_init,
16478 + .dia_update = mcfcau_sha1_update,
16479 + .dia_final = mcfcau_sha1_final } }
16480 +};
16481 +
16482 +static int __init init(void)
16483 +{
16484 + int ret = crypto_register_alg(&mcfcau_sha1_alg);
16485 + printk(KERN_INFO MCFCAU_SHA1_DRIVER_DESC " "
16486 + MCFCAU_SHA1_DRIVER_VERSION " %s.\n",ret?"failed":"registered");
16487 + return ret;
16488 +}
16489 +
16490 +static void __exit fini(void)
16491 +{
16492 + crypto_unregister_alg(&mcfcau_sha1_alg);
16493 + printk(KERN_INFO MCFCAU_SHA1_DRIVER_DESC " "
16494 + MCFCAU_SHA1_DRIVER_VERSION " unregistered.\n");
16495 +}
16496 +
16497 +module_init(init);
16498 +module_exit(fini);
16499 +
16500 +MODULE_LICENSE("GPL");
16501 +MODULE_DESCRIPTION(MCFCAU_SHA1_DRIVER_DESC);
16502 +MODULE_AUTHOR("Andrey Butok");
16503 --- a/drivers/dma/Makefile
16504 +++ b/drivers/dma/Makefile
16505 @@ -4,3 +4,5 @@ obj-$(CONFIG_INTEL_IOATDMA) += ioatdma.o
16506 ioatdma-objs := ioat.o ioat_dma.o ioat_dca.o
16507 obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o
16508 obj-$(CONFIG_FSL_DMA) += fsldma.o
16509 +obj-$(CONFIG_MCD_DMA) += mcddma.o
16510 +mcddma-objs := MCD_dmaApi.o MCD_tasks.o MCD_tasksInit.o
16511 --- /dev/null
16512 +++ b/drivers/dma/MCD_dmaApi.c
16513 @@ -0,0 +1,965 @@
16514 +/*
16515 + * drivers/dma/MCD_dmaApi.c
16516 + *
16517 + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
16518 + * Kurt Mahan <kmahan@freescale.com>
16519 + *
16520 + * This program is free software; you can redistribute it and/or
16521 + * modify it under the terms of the GNU General Public License as
16522 + * published by the Free Software Foundation; either version 2 of
16523 + * the License, or (at your option) any later version.
16524 + *
16525 + * This program is distributed in the hope that it will be useful,
16526 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
16527 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16528 + * GNU General Public License for more details.
16529 + *
16530 + * You should have received a copy of the GNU General Public License
16531 + * along with this program; if not, write to the Free Software
16532 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
16533 + * MA 02111-1307 USA
16534 + */
16535 +
16536 +#include "MCD_dma.h"
16537 +#include "MCD_tasksInit.h"
16538 +#include "MCD_progCheck.h"
16539 +
16540 +/********************************************************************/
16541 +/*
16542 + * This is an API-internal pointer to the DMA's registers
16543 + */
16544 +dmaRegs *MCD_dmaBar;
16545 +
16546 +/*
16547 + * These are the real and model task tables as generated by the
16548 + * build process
16549 + */
16550 +extern TaskTableEntry MCD_realTaskTableSrc[NCHANNELS];
16551 +extern TaskTableEntry MCD_modelTaskTableSrc[NUMOFVARIANTS];
16552 +
16553 +/*
16554 + * However, this (usually) gets relocated to on-chip SRAM, at which
16555 + * point we access them as these tables
16556 + */
16557 +volatile TaskTableEntry *MCD_taskTable;
16558 +TaskTableEntry *MCD_modelTaskTable;
16559 +
16560 +
16561 +/*
16562 + * MCD_chStatus[] is an array of status indicators for remembering
16563 + * whether a DMA has ever been attempted on each channel, pausing
16564 + * status, etc.
16565 + */
16566 +static int MCD_chStatus[NCHANNELS] =
16567 +{
16568 + MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
16569 + MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
16570 + MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
16571 + MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA
16572 +};
16573 +
16574 +/*
16575 + * Prototypes for local functions
16576 + */
16577 +static void MCD_memcpy (int *dest, int *src, u32 size);
16578 +static void MCD_resmActions (int channel);
16579 +
16580 +/*
16581 + * Buffer descriptors used for storage of progress info for single Dmas
16582 + * Also used as storage for the DMA for CRCs for single DMAs
16583 + * Otherwise, the DMA does not parse these buffer descriptors
16584 + */
16585 +#ifdef MCD_INCLUDE_EU
16586 +extern MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
16587 +#else
16588 +MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
16589 +#endif
16590 +MCD_bufDesc *MCD_relocBuffDesc;
16591 +
16592 +
16593 +/*
16594 + * Defines for the debug control register's functions
16595 + */
16596 +#define DBG_CTL_COMP1_TASK (0x00002000) /* have comparator 1 look for a task # */
16597 +#define DBG_CTL_ENABLE (DBG_CTL_AUTO_ARM | \
16598 + DBG_CTL_BREAK | \
16599 + DBG_CTL_INT_BREAK | \
16600 + DBG_CTL_COMP1_TASK)
16601 +#define DBG_CTL_DISABLE (DBG_CTL_AUTO_ARM | \
16602 + DBG_CTL_INT_BREAK | \
16603 + DBG_CTL_COMP1_TASK)
16604 +#define DBG_KILL_ALL_STAT (0xFFFFFFFF)
16605 +
16606 +/*
16607 + * Offset to context save area where progress info is stored
16608 + */
16609 +#define CSAVE_OFFSET 10
16610 +
16611 +/*
16612 + * Defines for Byte Swapping
16613 + */
16614 +#define MCD_BYTE_SWAP_KILLER 0xFFF8888F
16615 +#define MCD_NO_BYTE_SWAP_ATALL 0x00040000
16616 +
16617 +/*
16618 + * Execution Unit Identifiers
16619 + */
16620 +#define MAC 0 /* legacy - not used */
16621 +#define LUAC 1 /* legacy - not used */
16622 +#define CRC 2 /* legacy - not used */
16623 +#define LURC 3 /* Logic Unit with CRC */
16624 +
16625 +/*
16626 + * Task Identifiers
16627 + */
16628 +#define TASK_CHAINNOEU 0
16629 +#define TASK_SINGLENOEU 1
16630 +#ifdef MCD_INCLUDE_EU
16631 +#define TASK_CHAINEU 2
16632 +#define TASK_SINGLEEU 3
16633 +#define TASK_FECRX 4
16634 +#define TASK_FECTX 5
16635 +#else
16636 +#define TASK_CHAINEU 0
16637 +#define TASK_SINGLEEU 1
16638 +#define TASK_FECRX 2
16639 +#define TASK_FECTX 3
16640 +#endif
16641 +
16642 +/*
16643 + * Structure to remember which variant is on which channel
16644 + */
16645 +typedef struct MCD_remVariants_struct MCD_remVariant;
16646 +struct MCD_remVariants_struct
16647 +{
16648 + int remDestRsdIncr[NCHANNELS]; /* -1,0,1 */
16649 + int remSrcRsdIncr[NCHANNELS]; /* -1,0,1 */
16650 + s16 remDestIncr[NCHANNELS]; /* DestIncr */
16651 + s16 remSrcIncr[NCHANNELS]; /* srcIncr */
16652 + u32 remXferSize[NCHANNELS]; /* xferSize */
16653 +};
16654 +
16655 +/*
16656 + * Structure to remember the startDma parameters for each channel
16657 + */
16658 +MCD_remVariant MCD_remVariants;
16659 +
16660 +/********************************************************************/
16661 +/*
16662 + * Function: MCD_initDma
16663 + * Purpose: Initializes the DMA API by setting up a pointer to the DMA
16664 + * registers, relocating and creating the appropriate task
16665 + * structures, and setting up some global settings
16666 + * Arguments:
16667 + * dmaBarAddr - pointer to the multichannel DMA registers
16668 + * taskTableDest - location to move DMA task code and structs to
16669 + * flags - operational parameters
16670 + * Return Value:
16671 + * MCD_TABLE_UNALIGNED if taskTableDest is not 512-byte aligned
16672 + * MCD_OK otherwise
16673 + */
16674 +extern u32 MCD_funcDescTab0[];
16675 +
16676 +int MCD_initDma (dmaRegs *dmaBarAddr, void *taskTableDest, u32 flags)
16677 +{
16678 + int i;
16679 + TaskTableEntry *entryPtr;
16680 +
16681 + /* Setup the local pointer to register set */
16682 + MCD_dmaBar = dmaBarAddr;
16683 +
16684 + /* Do we need to move/create a task table */
16685 + if ((flags & MCD_RELOC_TASKS) != 0)
16686 + {
16687 + int fixedSize;
16688 + u32 *fixedPtr;
16689 + int varTabsOffset, funcDescTabsOffset, contextSavesOffset;
16690 + int taskDescTabsOffset;
16691 + int taskTableSize, varTabsSize, funcDescTabsSize, contextSavesSize;
16692 + int taskDescTabSize;
16693 +
16694 + int i;
16695 +
16696 + /* Check if physical address is aligned on 512 byte boundary */
16697 + if (((u32)taskTableDest & 0x000001ff) != 0)
16698 + return(MCD_TABLE_UNALIGNED);
16699 +
16700 + MCD_taskTable = taskTableDest; /* set up local pointer to task Table */
16701 +
16702 + /*
16703 + * Create a task table:
16704 + * - compute aligned base offsets for variable tables and
16705 + * function descriptor tables, then
16706 + * - loop through the task table and setup the pointers
16707 + * - copy over model task table with the the actual task descriptor
16708 + * tables
16709 + */
16710 + taskTableSize = NCHANNELS * sizeof(TaskTableEntry);
16711 + /* Align variable tables to size */
16712 + varTabsOffset = taskTableSize + (u32)taskTableDest;
16713 + if ((varTabsOffset & (VAR_TAB_SIZE - 1)) != 0)
16714 + varTabsOffset = (varTabsOffset + VAR_TAB_SIZE) & (~VAR_TAB_SIZE);
16715 + /* Align function descriptor tables */
16716 + varTabsSize = NCHANNELS * VAR_TAB_SIZE;
16717 + funcDescTabsOffset = varTabsOffset + varTabsSize;
16718 +
16719 + if ((funcDescTabsOffset & (FUNCDESC_TAB_SIZE - 1)) != 0)
16720 + funcDescTabsOffset = (funcDescTabsOffset + FUNCDESC_TAB_SIZE) &
16721 + (~FUNCDESC_TAB_SIZE);
16722 +
16723 + funcDescTabsSize = FUNCDESC_TAB_NUM * FUNCDESC_TAB_SIZE;
16724 + contextSavesOffset = funcDescTabsOffset + funcDescTabsSize;
16725 + contextSavesSize = (NCHANNELS * CONTEXT_SAVE_SIZE);
16726 + fixedSize = taskTableSize + varTabsSize + funcDescTabsSize +
16727 + contextSavesSize;
16728 +
16729 + /* Zero the thing out */
16730 + fixedPtr = (u32 *)taskTableDest;
16731 + for (i = 0;i<(fixedSize/4);i++)
16732 + fixedPtr[i] = 0;
16733 +
16734 + entryPtr = (TaskTableEntry*)MCD_taskTable;
16735 + /* Set up fixed pointers */
16736 + for (i = 0; i < NCHANNELS; i++)
16737 + {
16738 + entryPtr[i].varTab = (u32)varTabsOffset; /* update ptr to local value */
16739 + entryPtr[i].FDTandFlags = (u32)funcDescTabsOffset | MCD_TT_FLAGS_DEF;
16740 + entryPtr[i].contextSaveSpace = (u32)contextSavesOffset;
16741 + varTabsOffset += VAR_TAB_SIZE;
16742 +#ifdef MCD_INCLUDE_EU /* if not there is only one, just point to the same one */
16743 + funcDescTabsOffset += FUNCDESC_TAB_SIZE;
16744 +#endif
16745 + contextSavesOffset += CONTEXT_SAVE_SIZE;
16746 + }
16747 + /* Copy over the function descriptor table */
16748 + for ( i = 0; i < FUNCDESC_TAB_NUM; i++)
16749 + {
16750 + MCD_memcpy((void*)(entryPtr[i].FDTandFlags & ~MCD_TT_FLAGS_MASK),
16751 + (void*)MCD_funcDescTab0, FUNCDESC_TAB_SIZE);
16752 + }
16753 +
16754 + /* Copy model task table to where the context save stuff leaves off */
16755 + MCD_modelTaskTable = (TaskTableEntry*)contextSavesOffset;
16756 +
16757 + MCD_memcpy ((void*)MCD_modelTaskTable, (void*)MCD_modelTaskTableSrc,
16758 + NUMOFVARIANTS * sizeof(TaskTableEntry));
16759 +
16760 + /* Point to local version of model task table */
16761 + entryPtr = MCD_modelTaskTable;
16762 + taskDescTabsOffset = (u32)MCD_modelTaskTable +
16763 + (NUMOFVARIANTS * sizeof(TaskTableEntry));
16764 +
16765 + /* Copy actual task code and update TDT ptrs in local model task table */
16766 + for (i = 0; i < NUMOFVARIANTS; i++)
16767 + {
16768 + taskDescTabSize = entryPtr[i].TDTend - entryPtr[i].TDTstart + 4;
16769 + MCD_memcpy ((void*)taskDescTabsOffset, (void*)entryPtr[i].TDTstart, taskDescTabSize);
16770 + entryPtr[i].TDTstart = (u32)taskDescTabsOffset;
16771 + taskDescTabsOffset += taskDescTabSize;
16772 + entryPtr[i].TDTend = (u32)taskDescTabsOffset - 4;
16773 + }
16774 +#ifdef MCD_INCLUDE_EU
16775 + /*
16776 + * Tack single DMA BDs onto end of code so API controls where
16777 + * they are since DMA might write to them
16778 + */
16779 + MCD_relocBuffDesc = (MCD_bufDesc*)(entryPtr[NUMOFVARIANTS - 1].TDTend + 4);
16780 +#else
16781 + /*
16782 + * DMA does not touch them so they can be wherever and we don't need to
16783 + * waste SRAM on them
16784 + */
16785 + MCD_relocBuffDesc = MCD_singleBufDescs;
16786 +#endif
16787 + }
16788 + else
16789 + {
16790 + /*
16791 + * Point the would-be relocated task tables and the buffer descriptors
16792 + * to the ones the linker generated
16793 + */
16794 + if (((u32)MCD_realTaskTableSrc & 0x000001ff) != 0)
16795 + return(MCD_TABLE_UNALIGNED);
16796 +
16797 + entryPtr = MCD_realTaskTableSrc;
16798 + for (i = 0; i < NCHANNELS; i++)
16799 + {
16800 + if (((entryPtr[i].varTab & (VAR_TAB_SIZE - 1)) != 0) ||
16801 + ((entryPtr[i].FDTandFlags & (FUNCDESC_TAB_SIZE - 1)) != 0))
16802 + return(MCD_TABLE_UNALIGNED);
16803 + }
16804 +
16805 + MCD_taskTable = MCD_realTaskTableSrc;
16806 + MCD_modelTaskTable = MCD_modelTaskTableSrc;
16807 + MCD_relocBuffDesc = MCD_singleBufDescs;
16808 + }
16809 +
16810 + /* Make all channels inactive, and remember them as such: */
16811 + MCD_dmaBar->taskbar = (u32) MCD_taskTable;
16812 + for (i = 0; i < NCHANNELS; i++)
16813 + {
16814 + MCD_dmaBar->taskControl[i] = 0x0;
16815 + MCD_chStatus[i] = MCD_NO_DMA;
16816 + }
16817 +
16818 + /* Set up pausing mechanism to inactive state: */
16819 + MCD_dmaBar->debugComp1 = 0;
16820 + MCD_dmaBar->debugComp2 = 0;
16821 + MCD_dmaBar->debugControl = DBG_CTL_DISABLE;
16822 + MCD_dmaBar->debugStatus = DBG_KILL_ALL_STAT;
16823 +
16824 + /* Enable or disable commbus prefetch */
16825 + if ((flags & MCD_COMM_PREFETCH_EN) != 0)
16826 + MCD_dmaBar->ptdControl &= ~PTD_CTL_COMM_PREFETCH;
16827 + else
16828 + MCD_dmaBar->ptdControl |= PTD_CTL_COMM_PREFETCH;
16829 +
16830 + return(MCD_OK);
16831 +}
16832 +/*********************** End of MCD_initDma() ***********************/
16833 +
16834 +/********************************************************************/
16835 +/* Function: MCD_dmaStatus
16836 + * Purpose: Returns the status of the DMA on the requested channel
16837 + * Arguments: channel - channel number
16838 + * Returns: Predefined status indicators
16839 + */
16840 +int MCD_dmaStatus (int channel)
16841 +{
16842 + u16 tcrValue;
16843 +
16844 + if((channel < 0) || (channel >= NCHANNELS))
16845 + return(MCD_CHANNEL_INVALID);
16846 +
16847 + tcrValue = MCD_dmaBar->taskControl[channel];
16848 + if ((tcrValue & TASK_CTL_EN) == 0)
16849 + { /* Nothing running if last reported with task enabled */
16850 + if ( MCD_chStatus[channel] == MCD_RUNNING
16851 + || MCD_chStatus[channel] == MCD_IDLE)
16852 + MCD_chStatus[channel] = MCD_DONE;
16853 + }
16854 + else /* something is running */
16855 + {
16856 + /* There are three possibilities: paused, running or idle. */
16857 + if ( MCD_chStatus[channel] == MCD_RUNNING
16858 + || MCD_chStatus[channel] == MCD_IDLE)
16859 + {
16860 + MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT;
16861 + /* Determine which initiator is asserted. */
16862 + if ((MCD_dmaBar->ptdDebug >> channel ) & 0x1 )
16863 + MCD_chStatus[channel] = MCD_RUNNING;
16864 + else
16865 + MCD_chStatus[channel] = MCD_IDLE;
16866 + /* Do not change the status if it is already paused */
16867 + }
16868 + }
16869 + return MCD_chStatus[channel];
16870 +}
16871 +/******************** End of MCD_dmaStatus() ************************/
16872 +
16873 +/********************************************************************/
16874 +/* Function: MCD_startDma
16875 + * Ppurpose: Starts a particular kind of DMA
16876 + * Arguments: see below
16877 + * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
16878 + */
16879 +
16880 +int MCD_startDma (
16881 + int channel, /* the channel on which to run the DMA */
16882 + s8 *srcAddr, /* the address to move data from, or physical buffer-descriptor address */
16883 + s16 srcIncr, /* the amount to increment the source address per transfer */
16884 + s8 *destAddr, /* the address to move data to */
16885 + s16 destIncr, /* the amount to increment the destination address per transfer */
16886 + u32 dmaSize, /* the number of bytes to transfer independent of the transfer size */
16887 + u32 xferSize, /* the number bytes in of each data movement (1, 2, or 4) */
16888 + u32 initiator, /* what device initiates the DMA */
16889 + int priority, /* priority of the DMA */
16890 + u32 flags, /* flags describing the DMA */
16891 + u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */
16892 +#ifdef MCD_NEED_ADDR_TRANS
16893 + s8 *srcAddrVirt /* virtual buffer descriptor address TBD*/
16894 +#endif
16895 +)
16896 +{
16897 + int srcRsdIncr, destRsdIncr;
16898 + int *cSave;
16899 + short xferSizeIncr;
16900 + int tcrCount = 0;
16901 +#ifdef MCD_INCLUDE_EU
16902 + u32 *realFuncArray;
16903 +#endif
16904 +
16905 + if((channel < 0) || (channel >= NCHANNELS))
16906 + return(MCD_CHANNEL_INVALID);
16907 +
16908 +#ifndef MCD_INCLUDE_EU
16909 + funcDesc = MCD_FUNC_NOEU1;
16910 +#endif
16911 +
16912 +#ifdef MCD_DEBUG
16913 +printf("startDma:Setting up params\n");
16914 +#endif
16915 +
16916 + /* Enable task-wise priority */
16917 + MCD_dmaBar->ptdControl |= (u16) 0x8000;
16918 +
16919 + /* Calculate additional parameters to the regular DMA calls. */
16920 + srcRsdIncr = srcIncr < 0 ? -1 : (srcIncr > 0 ? 1 : 0);
16921 + destRsdIncr = destIncr < 0 ? -1 : (destIncr > 0 ? 1 : 0);
16922 + xferSizeIncr = (xferSize & 0xffff) | 0x20000000;
16923 +
16924 + /* Remember which variant is running for each channel */
16925 + MCD_remVariants.remSrcRsdIncr[channel] = srcRsdIncr;
16926 + MCD_remVariants.remDestRsdIncr[channel] = destRsdIncr;
16927 + MCD_remVariants.remDestIncr[channel] = destIncr;
16928 + MCD_remVariants.remSrcIncr[channel] = srcIncr;
16929 + MCD_remVariants.remXferSize[channel] = xferSize;
16930 +
16931 + cSave = (int*)(MCD_taskTable[channel].contextSaveSpace)
16932 + + CSAVE_OFFSET
16933 + + CURRBD;
16934 +
16935 +#ifdef MCD_INCLUDE_EU
16936 + realFuncArray = (u32 *) (MCD_taskTable[channel].FDTandFlags & 0xffffff00);
16937 +
16938 + /*
16939 + * Modify the LURC's normal and byte-residue-loop functions
16940 + * according to parameter.
16941 + */
16942 + switch (xferSize)
16943 + {
16944 + case 4:
16945 + realFuncArray[(LURC*16)] = funcDesc;
16946 + break;
16947 + case 2:
16948 + realFuncArray[(LURC*16)] = funcDesc & 0xfffff00f;
16949 + break;
16950 + case 1:
16951 + default:
16952 + realFuncArray[(LURC*16)] = funcDesc & 0xffff000f;
16953 + break;
16954 + }
16955 +
16956 + realFuncArray[(LURC*16+1)] = 0
16957 + | (funcDesc & MCD_BYTE_SWAP_KILLER)
16958 + | MCD_NO_BYTE_SWAP_ATALL;
16959 +#endif
16960 +
16961 + /* Write the initiator field in the TCR and set the initiator-hold bit*/
16962 + MCD_dmaBar->taskControl[channel] = 0
16963 + | (initiator << 8)
16964 + | TASK_CTL_HIPRITSKEN
16965 + | TASK_CTL_HLDINITNUM;
16966 +
16967 + /*
16968 + * Current versions of the MPC8220 MCD have a hardware quirk that could
16969 + * cause the write to the TCR to collide with an MDE access to the
16970 + * initiator-register file, so we have to verify that the write occurred
16971 + * correctly by reading back the value. On MCF547x/8x devices and any
16972 + * future revisions of the MPC8220, this loop will not be entered.
16973 + */
16974 + while(((MCD_dmaBar->taskControl[channel] & 0x1fff) !=
16975 + ((initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM)) &&
16976 + (tcrCount < 1000))
16977 + {
16978 + tcrCount++;
16979 + MCD_dmaBar->taskControl[channel] = 0
16980 + | (initiator << 8)
16981 + | TASK_CTL_HIPRITSKEN
16982 + | TASK_CTL_HLDINITNUM;
16983 + }
16984 +
16985 + MCD_dmaBar->priority[channel] = (u8)priority & PRIORITY_PRI_MASK;
16986 +
16987 + if (channel < 8 && channel >= 0)
16988 + {
16989 + MCD_dmaBar->taskSize0 &= ~(0xf << (7-channel)*4);
16990 + MCD_dmaBar->taskSize0 |= (xferSize & 3) << (((7 - channel)*4) + 2);
16991 + MCD_dmaBar->taskSize0 |= (xferSize & 3) << ((7 - channel)*4);
16992 + }
16993 + else
16994 + {
16995 + MCD_dmaBar->taskSize1 &= ~(0xf << (15-channel)*4);
16996 + MCD_dmaBar->taskSize1 |= (xferSize & 3) << (((15 - channel)*4) + 2);
16997 + MCD_dmaBar->taskSize1 |= (xferSize & 3) << ((15 - channel)*4);
16998 + }
16999 +
17000 + /* Setup task table flags/options */
17001 + MCD_taskTable[channel].FDTandFlags &= ~MCD_TT_FLAGS_MASK;
17002 + MCD_taskTable[channel].FDTandFlags |= (MCD_TT_FLAGS_MASK & flags);
17003 +
17004 + if (flags & MCD_FECTX_DMA)
17005 + {
17006 + /* TDTStart and TDTEnd */
17007 + MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_FECTX].TDTstart;
17008 + MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_FECTX].TDTend;
17009 + MCD_startDmaENetXmit(srcAddr, srcAddr, destAddr, MCD_taskTable, channel);
17010 + }
17011 + else if (flags & MCD_FECRX_DMA)
17012 + {
17013 + /* TDTStart and TDTEnd */
17014 + MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_FECRX].TDTstart;
17015 + MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_FECRX].TDTend;
17016 + MCD_startDmaENetRcv(srcAddr, srcAddr, destAddr, MCD_taskTable, channel);
17017 + }
17018 + else if(flags & MCD_SINGLE_DMA)
17019 + {
17020 + /*
17021 + * This buffer descriptor is used for storing off initial parameters
17022 + * for later progress query calculation and for the DMA to write the
17023 + * resulting checksum. The DMA does not use this to determine how to
17024 + * operate, that info is passed with the init routine
17025 + */
17026 + MCD_relocBuffDesc[channel].srcAddr = srcAddr;
17027 + MCD_relocBuffDesc[channel].destAddr = destAddr;
17028 + MCD_relocBuffDesc[channel].lastDestAddr = destAddr;
17029 + MCD_relocBuffDesc[channel].dmaSize = dmaSize;
17030 + MCD_relocBuffDesc[channel].flags = 0; /* not used */
17031 + MCD_relocBuffDesc[channel].csumResult = 0; /* not used */
17032 + MCD_relocBuffDesc[channel].next = 0; /* not used */
17033 +
17034 + /* Initialize the progress-querying stuff to show no progress:*/
17035 + ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET]
17036 + = (int)srcAddr;
17037 + ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET]
17038 + = (int)destAddr;
17039 + ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET]
17040 + = 0;
17041 + ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET]
17042 + = (u32) &(MCD_relocBuffDesc[channel]);
17043 +
17044 + if( funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2)
17045 + {
17046 + /* TDTStart and TDTEnd */
17047 + MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_SINGLENOEU].TDTstart;
17048 + MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_SINGLENOEU].TDTend;
17049 + MCD_startDmaSingleNoEu(srcAddr, srcIncr, destAddr, destIncr, dmaSize,
17050 + xferSizeIncr, flags, (int *)&(MCD_relocBuffDesc[channel]),
17051 + cSave, MCD_taskTable, channel);
17052 + }
17053 + else
17054 + {
17055 + /* TDTStart and TDTEnd */
17056 + MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_SINGLEEU].TDTstart;
17057 + MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_SINGLEEU].TDTend;
17058 + MCD_startDmaSingleEu(srcAddr, srcIncr, destAddr, destIncr, dmaSize,
17059 + xferSizeIncr, flags, (int *)&(MCD_relocBuffDesc[channel]),
17060 + cSave, MCD_taskTable, channel);
17061 + }
17062 + }
17063 + else /* Chained DMA */
17064 + {
17065 + /* Initialize the progress-querying stuff to show no progress:*/
17066 +#if 1 /* (!defined(MCD_NEED_ADDR_TRANS)) */
17067 + ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET]
17068 + = (int)((MCD_bufDesc*) srcAddr)->srcAddr;
17069 + ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET]
17070 + = (int)((MCD_bufDesc*) srcAddr)->destAddr;
17071 +#else /* if using address translation, need the virtual addr of the first buffdesc */
17072 + ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET]
17073 + = (int)((MCD_bufDesc*) srcAddrVirt)->srcAddr;
17074 + ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET]
17075 + = (int)((MCD_bufDesc*) srcAddrVirt)->destAddr;
17076 +#endif
17077 + ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET]
17078 + = 0;
17079 + ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET]
17080 + = (u32) srcAddr;
17081 +
17082 + if( funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2)
17083 + {
17084 + /* TDTStart and TDTEnd */
17085 + MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_CHAINNOEU].TDTstart;
17086 + MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_CHAINNOEU].TDTend;
17087 + MCD_startDmaChainNoEu((int *)srcAddr, srcIncr, destIncr, xferSize,
17088 + xferSizeIncr, cSave, MCD_taskTable, channel);
17089 + }
17090 + else
17091 + {
17092 + /* TDTStart and TDTEnd */
17093 + MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_CHAINEU].TDTstart;
17094 + MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_CHAINEU].TDTend;
17095 + MCD_startDmaChainEu((int *)srcAddr, srcIncr, destIncr, xferSize,
17096 + xferSizeIncr, cSave, MCD_taskTable, channel);
17097 + }
17098 + }
17099 +
17100 + MCD_chStatus[channel] = MCD_IDLE;
17101 + return(MCD_OK);
17102 +}
17103 +
17104 +/************************ End of MCD_startDma() *********************/
17105 +
17106 +/********************************************************************/
17107 +/* Function: MCD_XferProgrQuery
17108 + * Purpose: Returns progress of DMA on requested channel
17109 + * Arguments: channel - channel to retrieve progress for
17110 + * progRep - pointer to user supplied MCD_XferProg struct
17111 + * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
17112 + *
17113 + * Notes:
17114 + * MCD_XferProgrQuery() upon completing or after aborting a DMA, or
17115 + * while the DMA is in progress, this function returns the first
17116 + * DMA-destination address not (or not yet) used in the DMA. When
17117 + * encountering a non-ready buffer descriptor, the information for
17118 + * the last completed descriptor is returned.
17119 + *
17120 + * MCD_XferProgQuery() has to avoid the possibility of getting
17121 + * partially-updated information in the event that we should happen
17122 + * to query DMA progress just as the DMA is updating it. It does that
17123 + * by taking advantage of the fact context is not saved frequently for
17124 + * the most part. We therefore read it at least twice until we get the
17125 + * same information twice in a row.
17126 + *
17127 + * Because a small, but not insignificant, amount of time is required
17128 + * to write out the progress-query information, especially upon
17129 + * completion of the DMA, it would be wise to guarantee some time lag
17130 + * between successive readings of the progress-query information.
17131 + */
17132 +
17133 +/*
17134 + * How many iterations of the loop below to execute to stabilize values
17135 + */
17136 +#define STABTIME 0
17137 +
17138 +int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep)
17139 +{
17140 + MCD_XferProg prevRep;
17141 + int again; /* true if we are to try again to get consistent results */
17142 + int i; /* used as a time-waste counter */
17143 + int destDiffBytes; /* Total number of bytes that we think actually got xfered. */
17144 + int numIterations; /* number of iterations */
17145 + int bytesNotXfered; /* bytes that did not get xfered. */
17146 + s8 *LWAlignedInitDestAddr, *LWAlignedCurrDestAddr;
17147 + int subModVal, addModVal; /* Mode values to added and subtracted from the
17148 + final destAddr */
17149 +
17150 + if((channel < 0) || (channel >= NCHANNELS))
17151 + return(MCD_CHANNEL_INVALID);
17152 +
17153 + /* Read a trial value for the progress-reporting values*/
17154 + prevRep.lastSrcAddr =
17155 + (s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET];
17156 + prevRep.lastDestAddr =
17157 + (s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET];
17158 + prevRep.dmaSize = ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET];
17159 + prevRep.currBufDesc =
17160 + (MCD_bufDesc*) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET];
17161 +
17162 + /* Repeatedly reread those values until they match previous values: */
17163 + do {
17164 + /* Take a little bit of time to ensure stability: */
17165 + for (i = 0; i < STABTIME; i++)
17166 + i += i >> 2; /* make sure this loop does something so that it
17167 + doesn't get optimized out */
17168 + /* Check them again: */
17169 + progRep->lastSrcAddr =
17170 + (s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET];
17171 + progRep->lastDestAddr =
17172 + (s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET];
17173 + progRep->dmaSize = ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET];
17174 + progRep->currBufDesc =
17175 + (MCD_bufDesc*) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET];
17176 +
17177 + /* See if they match: */
17178 + if ( prevRep.lastSrcAddr != progRep->lastSrcAddr
17179 + || prevRep.lastDestAddr != progRep->lastDestAddr
17180 + || prevRep.dmaSize != progRep->dmaSize
17181 + || prevRep.currBufDesc != progRep->currBufDesc)
17182 + {
17183 + /* If they don't match, remember previous values and try again:*/
17184 + prevRep.lastSrcAddr = progRep->lastSrcAddr;
17185 + prevRep.lastDestAddr = progRep->lastDestAddr;
17186 + prevRep.dmaSize = progRep->dmaSize;
17187 + prevRep.currBufDesc = progRep->currBufDesc;
17188 + again = MCD_TRUE;
17189 + }
17190 + else
17191 + again = MCD_FALSE;
17192 + } while (again == MCD_TRUE);
17193 +
17194 +
17195 + /* Update dmaSize and lastDestAddr */
17196 + switch(MCD_remVariants.remDestRsdIncr[channel])
17197 + {
17198 + case MINUS1:
17199 + subModVal = ((int)progRep->lastDestAddr)
17200 + & ((MCD_remVariants.remXferSize[channel]) - 1);
17201 + addModVal = ((int)progRep->currBufDesc->destAddr)
17202 + & ((MCD_remVariants.remXferSize[channel]) - 1);
17203 + LWAlignedInitDestAddr = (progRep->currBufDesc->destAddr) - addModVal;
17204 + LWAlignedCurrDestAddr = (progRep->lastDestAddr) - subModVal;
17205 + destDiffBytes = LWAlignedInitDestAddr - LWAlignedCurrDestAddr;
17206 + bytesNotXfered = (destDiffBytes/MCD_remVariants.remDestIncr[channel]) *
17207 + ( MCD_remVariants.remDestIncr[channel]
17208 + + MCD_remVariants.remXferSize[channel]);
17209 + progRep->dmaSize = destDiffBytes - bytesNotXfered + addModVal - subModVal;
17210 + break;
17211 + case ZERO:
17212 + progRep->lastDestAddr = progRep->currBufDesc->destAddr;
17213 + break;
17214 + case PLUS1:
17215 + /* This value has to be subtracted from the final calculated dmaSize. */
17216 + subModVal = ((int)progRep->currBufDesc->destAddr)
17217 + & ((MCD_remVariants.remXferSize[channel]) - 1);
17218 + /* These bytes are already in lastDestAddr. */
17219 + addModVal = ((int)progRep->lastDestAddr)
17220 + & ((MCD_remVariants.remXferSize[channel]) - 1);
17221 + LWAlignedInitDestAddr = (progRep->currBufDesc->destAddr) - subModVal;
17222 + LWAlignedCurrDestAddr = (progRep->lastDestAddr) - addModVal;
17223 + destDiffBytes = (progRep->lastDestAddr - LWAlignedInitDestAddr);
17224 + numIterations = ( LWAlignedCurrDestAddr - LWAlignedInitDestAddr)/MCD_remVariants.remDestIncr[channel];
17225 + bytesNotXfered = numIterations *
17226 + (MCD_remVariants.remDestIncr[channel]
17227 + - MCD_remVariants.remXferSize[channel]);
17228 + progRep->dmaSize = destDiffBytes - bytesNotXfered - subModVal;
17229 + break;
17230 + default:
17231 + break;
17232 + }
17233 +
17234 + /* This covers M1,P1,Z for source */
17235 + switch(MCD_remVariants.remSrcRsdIncr[channel])
17236 + {
17237 + case MINUS1:
17238 + progRep->lastSrcAddr =
17239 + progRep->currBufDesc->srcAddr +
17240 + ( MCD_remVariants.remSrcIncr[channel] *
17241 + (progRep->dmaSize/MCD_remVariants.remXferSize[channel]));
17242 + break;
17243 + case ZERO:
17244 + progRep->lastSrcAddr = progRep->currBufDesc->srcAddr;
17245 + break;
17246 + case PLUS1:
17247 + progRep->lastSrcAddr =
17248 + progRep->currBufDesc->srcAddr +
17249 + ( MCD_remVariants.remSrcIncr[channel] *
17250 + (progRep->dmaSize/MCD_remVariants.remXferSize[channel]));
17251 + break;
17252 + default:
17253 + break;
17254 + }
17255 +
17256 + return(MCD_OK);
17257 +}
17258 +/******************* End of MCD_XferProgrQuery() ********************/
17259 +
17260 +/********************************************************************/
17261 +/* MCD_resmActions() does the majority of the actions of a DMA resume.
17262 + * It is called from MCD_killDma() and MCD_resumeDma(). It has to be
17263 + * a separate function because the kill function has to negate the task
17264 + * enable before resuming it, but the resume function has to do nothing
17265 + * if there is no DMA on that channel (i.e., if the enable bit is 0).
17266 + */
17267 +static void MCD_resmActions (int channel)
17268 +{
17269 + MCD_dmaBar->debugControl = DBG_CTL_DISABLE;
17270 + MCD_dmaBar->debugStatus = MCD_dmaBar->debugStatus;
17271 +
17272 + /* Determine which initiators are asserted */
17273 + MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT;
17274 +
17275 + if((MCD_dmaBar->ptdDebug >> channel ) & 0x1)
17276 + MCD_chStatus[channel] = MCD_RUNNING;
17277 + else
17278 + MCD_chStatus[channel] = MCD_IDLE;
17279 +}
17280 +/********************* End of MCD_resmActions() *********************/
17281 +
17282 +/********************************************************************/
17283 +/* Function: MCD_killDma
17284 + * Purpose: Halt the DMA on the requested channel, without any
17285 + * intention of resuming the DMA.
17286 + * Arguments: channel - requested channel
17287 + * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
17288 + *
17289 + * Notes:
17290 + * A DMA may be killed from any state, including paused state, and it
17291 + * always goes to the MCD_HALTED state even if it is killed while in
17292 + * the MCD_NO_DMA or MCD_IDLE states.
17293 + */
17294 +int MCD_killDma (int channel)
17295 +{
17296 + if((channel < 0) || (channel >= NCHANNELS))
17297 + return(MCD_CHANNEL_INVALID);
17298 +
17299 + MCD_dmaBar->taskControl[channel] = 0x0;
17300 +
17301 + /* Clean up after a paused task */
17302 + if (MCD_chStatus[channel] == MCD_PAUSED)
17303 + {
17304 + MCD_dmaBar->debugControl = DBG_CTL_DISABLE;
17305 + MCD_dmaBar->debugStatus = MCD_dmaBar->debugStatus;
17306 + }
17307 +
17308 + MCD_chStatus[channel] = MCD_HALTED;
17309 +
17310 + return(MCD_OK);
17311 +}
17312 +/************************ End of MCD_killDma() **********************/
17313 +
17314 +/********************************************************************/
17315 +/* Function: MCD_continDma
17316 + * Purpose: Continue a DMA which as stopped due to encountering an
17317 + * unready buffer descriptor.
17318 + * Arguments: channel - channel to continue the DMA on
17319 + * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
17320 + *
17321 + * Notes:
17322 + * This routine does not check to see if there is a task which can
17323 + * be continued. Also this routine should not be used with single DMAs.
17324 + */
17325 +int MCD_continDma (int channel)
17326 +{
17327 + if((channel < 0) || (channel >= NCHANNELS))
17328 + return(MCD_CHANNEL_INVALID);
17329 +
17330 + MCD_dmaBar->taskControl[channel] |= TASK_CTL_EN;
17331 + MCD_chStatus[channel] = MCD_RUNNING;
17332 +
17333 + return(MCD_OK);
17334 +}
17335 +/********************** End of MCD_continDma() **********************/
17336 +
17337 +/*********************************************************************
17338 + * MCD_pauseDma() and MCD_resumeDma() below use the DMA's debug unit
17339 + * to freeze a task and resume it. We freeze a task by breakpointing
17340 + * on the stated task. That is, not any specific place in the task,
17341 + * but any time that task executes. In particular, when that task
17342 + * executes, we want to freeze that task and only that task.
17343 + *
17344 + * The bits of the debug control register influence interrupts vs.
17345 + * breakpoints as follows:
17346 + * - Bits 14 and 0 enable or disable debug functions. If enabled, you
17347 + * will get the interrupt but you may or may not get a breakpoint.
17348 + * - Bits 2 and 1 decide whether you also get a breakpoint in addition
17349 + * to an interrupt.
17350 + *
17351 + * The debug unit can do these actions in response to either internally
17352 + * detected breakpoint conditions from the comparators, or in response
17353 + * to the external breakpoint pin, or both.
17354 + * - Bits 14 and 1 perform the above-described functions for
17355 + * internally-generated conditions, i.e., the debug comparators.
17356 + * - Bits 0 and 2 perform the above-described functions for external
17357 + * conditions, i.e., the breakpoint external pin.
17358 + *
17359 + * Note that, although you "always" get the interrupt when you turn
17360 + * the debug functions, the interrupt can nevertheless, if desired, be
17361 + * masked by the corresponding bit in the PTD's IMR. Note also that
17362 + * this means that bits 14 and 0 must enable debug functions before
17363 + * bits 1 and 2, respectively, have any effect.
17364 + *
17365 + * NOTE: It's extremely important to not pause more than one DMA channel
17366 + * at a time.
17367 + ********************************************************************/
17368 +
17369 +/********************************************************************/
17370 +/* Function: MCD_pauseDma
17371 + * Purpose: Pauses the DMA on a given channel (if any DMA is running
17372 + * on that channel).
17373 + * Arguments: channel
17374 + * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
17375 + */
17376 +int MCD_pauseDma (int channel)
17377 +{
17378 + if((channel < 0) || (channel >= NCHANNELS))
17379 + return(MCD_CHANNEL_INVALID);
17380 +
17381 + if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN)
17382 + {
17383 + MCD_dmaBar->debugComp1 = channel;
17384 + MCD_dmaBar->debugControl = DBG_CTL_ENABLE | (1 << (channel + 16));
17385 + MCD_chStatus[channel] = MCD_PAUSED;
17386 + }
17387 + return(MCD_OK);
17388 +}
17389 +/************************* End of MCD_pauseDma() ********************/
17390 +
17391 +/********************************************************************/
17392 +/* Function: MCD_resumeDma
17393 + * Purpose: Resumes the DMA on a given channel (if any DMA is
17394 + * running on that channel).
17395 + * Arguments: channel - channel on which to resume DMA
17396 + * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
17397 + */
17398 +int MCD_resumeDma (int channel)
17399 +{
17400 + if((channel < 0) || (channel >= NCHANNELS))
17401 + return(MCD_CHANNEL_INVALID);
17402 +
17403 + if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN)
17404 + MCD_resmActions (channel);
17405 +
17406 + return(MCD_OK);
17407 +}
17408 +/************************ End of MCD_resumeDma() ********************/
17409 +
17410 +/********************************************************************/
17411 +/* Function: MCD_csumQuery
17412 + * Purpose: Provide the checksum after performing a non-chained DMA
17413 + * Arguments: channel - channel to report on
17414 + * csum - pointer to where to write the checksum/CRC
17415 + * Returns: MCD_ERROR if the channel is invalid, else MCD_OK
17416 + *
17417 + * Notes:
17418 + *
17419 + */
17420 +int MCD_csumQuery (int channel, u32 *csum)
17421 +{
17422 +#ifdef MCD_INCLUDE_EU
17423 + if((channel < 0) || (channel >= NCHANNELS))
17424 + return(MCD_CHANNEL_INVALID);
17425 +
17426 + *csum = MCD_relocBuffDesc[channel].csumResult;
17427 + return(MCD_OK);
17428 +#else
17429 + return(MCD_ERROR);
17430 +#endif
17431 +}
17432 +/*********************** End of MCD_resumeDma() *********************/
17433 +
17434 +/********************************************************************/
17435 +/* Function: MCD_getCodeSize
17436 + * Purpose: Provide the size requirements of the microcoded tasks
17437 + * Returns: Size in bytes
17438 + */
17439 +int MCD_getCodeSize(void)
17440 +{
17441 +#ifdef MCD_INCLUDE_EU
17442 + return(0x2b64);
17443 +#else
17444 + return(0x1744);
17445 +#endif
17446 +}
17447 +/********************** End of MCD_getCodeSize() ********************/
17448 +
17449 +/********************************************************************/
17450 +/* Function: MCD_getVersion
17451 + * Purpose: Provide the version string and number
17452 + * Arguments: longVersion - user supplied pointer to a pointer to a char
17453 + * which points to the version string
17454 + * Returns: Version number and version string (by reference)
17455 + */
17456 +char MCD_versionString[] = "Multi-channel DMA API v1.0";
17457 +#define MCD_REV_MAJOR 0x01
17458 +#define MCD_REV_MINOR 0x00
17459 +
17460 +int MCD_getVersion(char **longVersion)
17461 +{
17462 + *longVersion = MCD_versionString;
17463 + return((MCD_REV_MAJOR << 8) | MCD_REV_MINOR);
17464 +}
17465 +/********************** End of MCD_getVersion() *********************/
17466 +
17467 +/********************************************************************/
17468 +/* Private version of memcpy()
17469 + * Note that everything this is used for is longword-aligned.
17470 + */
17471 +static void MCD_memcpy (int *dest, int *src, u32 size)
17472 +{
17473 + u32 i;
17474 +
17475 + for (i = 0; i < size; i += sizeof(int), dest++, src++)
17476 + *dest = *src;
17477 +}
17478 +/********************************************************************/
17479 --- /dev/null
17480 +++ b/drivers/dma/MCD_dma.h
17481 @@ -0,0 +1,378 @@
17482 +/*
17483 + * drivers/dma/MCD_dma.h
17484 + *
17485 + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
17486 + * Kurt Mahan <kmahan@freescale.com>
17487 + *
17488 + * This program is free software; you can redistribute it and/or
17489 + * modify it under the terms of the GNU General Public License as
17490 + * published by the Free Software Foundation; either version 2 of
17491 + * the License, or (at your option) any later version.
17492 + *
17493 + * This program is distributed in the hope that it will be useful,
17494 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
17495 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17496 + * GNU General Public License for more details.
17497 + *
17498 + * You should have received a copy of the GNU General Public License
17499 + * along with this program; if not, write to the Free Software
17500 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17501 + * MA 02111-1307 USA
17502 + */
17503 +#ifndef _MCD_API_H
17504 +#define _MCD_API_H
17505 +
17506 +/*
17507 + * Turn Execution Unit tasks ON (#define) or OFF (#undef)
17508 + */
17509 +#undef MCD_INCLUDE_EU
17510 +
17511 +/*
17512 + * Number of DMA channels
17513 + */
17514 +#define NCHANNELS 16
17515 +
17516 +/*
17517 + * Total number of variants
17518 + */
17519 +#ifdef MCD_INCLUDE_EU
17520 +#define NUMOFVARIANTS 6
17521 +#else
17522 +#define NUMOFVARIANTS 4
17523 +#endif
17524 +
17525 +/*
17526 + * Define sizes of the various tables
17527 + */
17528 +#define TASK_TABLE_SIZE (NCHANNELS*32)
17529 +#define VAR_TAB_SIZE (128)
17530 +#define CONTEXT_SAVE_SIZE (128)
17531 +#define FUNCDESC_TAB_SIZE (256)
17532 +
17533 +#ifdef MCD_INCLUDE_EU
17534 +#define FUNCDESC_TAB_NUM 16
17535 +#else
17536 +#define FUNCDESC_TAB_NUM 1
17537 +#endif
17538 +
17539 +
17540 +#ifndef DEFINESONLY
17541 +
17542 +/*
17543 + * Portability typedefs
17544 + */
17545 +typedef int s32;
17546 +typedef unsigned int u32;
17547 +typedef short s16;
17548 +typedef unsigned short u16;
17549 +typedef char s8;
17550 +typedef unsigned char u8;
17551 +
17552 +/*
17553 + * These structures represent the internal registers of the
17554 + * multi-channel DMA
17555 + */
17556 +struct dmaRegs_s {
17557 + u32 taskbar; /* task table base address register */
17558 + u32 currPtr;
17559 + u32 endPtr;
17560 + u32 varTablePtr;
17561 + u16 dma_rsvd0;
17562 + u16 ptdControl; /* ptd control */
17563 + u32 intPending; /* interrupt pending register */
17564 + u32 intMask; /* interrupt mask register */
17565 + u16 taskControl[16]; /* task control registers */
17566 + u8 priority[32]; /* priority registers */
17567 + u32 initiatorMux; /* initiator mux control */
17568 + u32 taskSize0; /* task size control register 0. */
17569 + u32 taskSize1; /* task size control register 1. */
17570 + u32 dma_rsvd1; /* reserved */
17571 + u32 dma_rsvd2; /* reserved */
17572 + u32 debugComp1; /* debug comparator 1 */
17573 + u32 debugComp2; /* debug comparator 2 */
17574 + u32 debugControl; /* debug control */
17575 + u32 debugStatus; /* debug status */
17576 + u32 ptdDebug; /* priority task decode debug */
17577 + u32 dma_rsvd3[31]; /* reserved */
17578 +};
17579 +typedef volatile struct dmaRegs_s dmaRegs;
17580 +
17581 +#endif
17582 +
17583 +/*
17584 + * PTD contrl reg bits
17585 + */
17586 +#define PTD_CTL_TSK_PRI 0x8000
17587 +#define PTD_CTL_COMM_PREFETCH 0x0001
17588 +
17589 +/*
17590 + * Task Control reg bits and field masks
17591 + */
17592 +#define TASK_CTL_EN 0x8000
17593 +#define TASK_CTL_VALID 0x4000
17594 +#define TASK_CTL_ALWAYS 0x2000
17595 +#define TASK_CTL_INIT_MASK 0x1f00
17596 +#define TASK_CTL_ASTRT 0x0080
17597 +#define TASK_CTL_HIPRITSKEN 0x0040
17598 +#define TASK_CTL_HLDINITNUM 0x0020
17599 +#define TASK_CTL_ASTSKNUM_MASK 0x000f
17600 +
17601 +/*
17602 + * Priority reg bits and field masks
17603 + */
17604 +#define PRIORITY_HLD 0x80
17605 +#define PRIORITY_PRI_MASK 0x07
17606 +
17607 +/*
17608 + * Debug Control reg bits and field masks
17609 + */
17610 +#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000
17611 +#define DBG_CTL_AUTO_ARM 0x00008000
17612 +#define DBG_CTL_BREAK 0x00004000
17613 +#define DBG_CTL_COMP1_TYP_MASK 0x00003800
17614 +#define DBG_CTL_COMP2_TYP_MASK 0x00000070
17615 +#define DBG_CTL_EXT_BREAK 0x00000004
17616 +#define DBG_CTL_INT_BREAK 0x00000002
17617 +
17618 +/*
17619 + * PTD Debug reg selector addresses
17620 + * This reg must be written with a value to show the contents of
17621 + * one of the desired internal register.
17622 + */
17623 +#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */
17624 +#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and
17625 + have initiators asserted */
17626 +
17627 +
17628 +/*
17629 + * General return values
17630 + */
17631 +#define MCD_OK 0
17632 +#define MCD_ERROR -1
17633 +#define MCD_TABLE_UNALIGNED -2
17634 +#define MCD_CHANNEL_INVALID -3
17635 +
17636 +/*
17637 + * MCD_initDma input flags
17638 + */
17639 +#define MCD_RELOC_TASKS 0x00000001
17640 +#define MCD_NO_RELOC_TASKS 0x00000000
17641 +#define MCD_COMM_PREFETCH_EN 0x00000002 /* Commbus Prefetching - MCF547x/548x ONLY */
17642 +
17643 +/*
17644 + * MCD_dmaStatus Status Values for each channel
17645 + */
17646 +#define MCD_NO_DMA 1 /* No DMA has been requested since reset */
17647 +#define MCD_IDLE 2 /* DMA active, but the initiator is currently inactive */
17648 +#define MCD_RUNNING 3 /* DMA active, and the initiator is currently active */
17649 +#define MCD_PAUSED 4 /* DMA active but it is currently paused */
17650 +#define MCD_HALTED 5 /* the most recent DMA has been killed with MCD_killTask() */
17651 +#define MCD_DONE 6 /* the most recent DMA has completed. */
17652 +
17653 +
17654 +/*
17655 + * MCD_startDma parameter defines
17656 + */
17657 +
17658 +/*
17659 + * Constants for the funcDesc parameter
17660 + */
17661 +/* Byte swapping: */
17662 +#define MCD_NO_BYTE_SWAP 0x00045670 /* to disable byte swapping. */
17663 +#define MCD_BYTE_REVERSE 0x00076540 /* to reverse the bytes of each u32 of the DMAed data. */
17664 +#define MCD_U16_REVERSE 0x00067450 /* to reverse the 16-bit halves of
17665 + each 32-bit data value being DMAed.*/
17666 +#define MCD_U16_BYTE_REVERSE 0x00054760 /* to reverse the byte halves of each
17667 + 16-bit half of each 32-bit data value DMAed */
17668 +#define MCD_NO_BIT_REV 0x00000000 /* do not reverse the bits of each byte DMAed. */
17669 +#define MCD_BIT_REV 0x00088880 /* reverse the bits of each byte DMAed */
17670 +/* CRCing: */
17671 +#define MCD_CRC16 0xc0100000 /* to perform CRC-16 on DMAed data. */
17672 +#define MCD_CRCCCITT 0xc0200000 /* to perform CRC-CCITT on DMAed data. */
17673 +#define MCD_CRC32 0xc0300000 /* to perform CRC-32 on DMAed data. */
17674 +#define MCD_CSUMINET 0xc0400000 /* to perform internet checksums on DMAed data.*/
17675 +#define MCD_NO_CSUM 0xa0000000 /* to perform no checksumming. */
17676 +
17677 +#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | MCD_NO_CSUM)
17678 +#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
17679 +
17680 +/*
17681 + * Constants for the flags parameter
17682 + */
17683 +#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */
17684 +#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */
17685 +#define MCD_TT_FLAGS_SP 0x00000004 /* Speculative prefetch(XLB) MCF547x/548x ONLY */
17686 +#define MCD_TT_FLAGS_PI 0x00000040 /* Precise Increment */
17687 +#define MCD_TT_FLAGS_MASK 0x000000ff
17688 +#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
17689 +
17690 +#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */
17691 +#define MCD_CHAIN_DMA /* TBD */
17692 +#define MCD_EU_DMA /* TBD */
17693 +#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */
17694 +#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */
17695 +
17696 +
17697 +/* these flags are valid for MCD_startDma and the chained buffer descriptors */
17698 +#define MCD_BUF_READY 0x80000000 /* indicates that this buffer is now under the DMA's control */
17699 +#define MCD_WRAP 0x20000000 /* to tell the FEC Dmas to wrap to the first BD */
17700 +#define MCD_INTERRUPT 0x10000000 /* to generate an interrupt after completion of the DMA. */
17701 +#define MCD_END_FRAME 0x08000000 /* tell the DMA to end the frame when transferring
17702 + last byte of data in buffer */
17703 +#define MCD_CRC_RESTART 0x40000000 /* to empty out the accumulated checksum
17704 + prior to performing the DMA. */
17705 +
17706 +/* Defines for the FEC buffer descriptor control/status word*/
17707 +#define MCD_FEC_BUF_READY 0x8000
17708 +#define MCD_FEC_WRAP 0x2000
17709 +#define MCD_FEC_INTERRUPT 0x1000
17710 +#define MCD_FEC_END_FRAME 0x0800
17711 +
17712 +
17713 +/*
17714 + * Defines for general intuitiveness
17715 + */
17716 +
17717 +#define MCD_TRUE 1
17718 +#define MCD_FALSE 0
17719 +
17720 +/*
17721 + * Three different cases for destination and source.
17722 + */
17723 +#define MINUS1 -1
17724 +#define ZERO 0
17725 +#define PLUS1 1
17726 +
17727 +#ifndef DEFINESONLY
17728 +
17729 +/* Task Table Entry struct*/
17730 +typedef struct {
17731 + u32 TDTstart; /* task descriptor table start */
17732 + u32 TDTend; /* task descriptor table end */
17733 + u32 varTab; /* variable table start */
17734 + u32 FDTandFlags; /* function descriptor table start and flags */
17735 + volatile u32 descAddrAndStatus;
17736 + volatile u32 modifiedVarTab;
17737 + u32 contextSaveSpace; /* context save space start */
17738 + u32 literalBases;
17739 +} TaskTableEntry;
17740 +
17741 +
17742 +/* Chained buffer descriptor */
17743 +typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
17744 +struct MCD_bufDesc_struct {
17745 + u32 flags; /* flags describing the DMA */
17746 + u32 csumResult; /* checksum from checksumming performed since last checksum reset */
17747 + s8 *srcAddr; /* the address to move data from */
17748 + s8 *destAddr; /* the address to move data to */
17749 + s8 *lastDestAddr; /* the last address written to */
17750 + u32 dmaSize; /* the number of bytes to transfer independent of the transfer size */
17751 + MCD_bufDesc *next; /* next buffer descriptor in chain */
17752 + u32 info; /* private information about this descriptor; DMA does not affect it */
17753 +};
17754 +
17755 +/* Progress Query struct */
17756 +typedef volatile struct MCD_XferProg_struct {
17757 + s8 *lastSrcAddr; /* the most-recent or last, post-increment source address */
17758 + s8 *lastDestAddr; /* the most-recent or last, post-increment destination address */
17759 + u32 dmaSize; /* the amount of data transferred for the current buffer */
17760 + MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */
17761 +} MCD_XferProg;
17762 +
17763 +
17764 +/* FEC buffer descriptor */
17765 +typedef volatile struct MCD_bufDescFec_struct {
17766 + u16 statCtrl;
17767 + u16 length;
17768 + u32 dataPointer;
17769 +} MCD_bufDescFec;
17770 +
17771 +
17772 +/*************************************************************************/
17773 +/*
17774 + * API function Prototypes - see MCD_dmaApi.c for further notes
17775 + */
17776 +
17777 +/*
17778 + * MCD_startDma starts a particular kind of DMA .
17779 + */
17780 +int MCD_startDma (
17781 + int channel, /* the channel on which to run the DMA */
17782 + s8 *srcAddr, /* the address to move data from, or buffer-descriptor address */
17783 + s16 srcIncr, /* the amount to increment the source address per transfer */
17784 + s8 *destAddr, /* the address to move data to */
17785 + s16 destIncr, /* the amount to increment the destination address per transfer */
17786 + u32 dmaSize, /* the number of bytes to transfer independent of the transfer size */
17787 + u32 xferSize, /* the number bytes in of each data movement (1, 2, or 4) */
17788 + u32 initiator, /* what device initiates the DMA */
17789 + int priority, /* priority of the DMA */
17790 + u32 flags, /* flags describing the DMA */
17791 + u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */
17792 +);
17793 +
17794 +/*
17795 + * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
17796 + * registers, relocating and creating the appropriate task structures, and
17797 + * setting up some global settings
17798 + */
17799 +int MCD_initDma (dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags);
17800 +
17801 +/*
17802 + * MCD_dmaStatus() returns the status of the DMA on the requested channel.
17803 + */
17804 +int MCD_dmaStatus (int channel);
17805 +
17806 +/*
17807 + * MCD_XferProgrQuery() returns progress of DMA on requested channel
17808 + */
17809 +int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep);
17810 +
17811 +/*
17812 + * MCD_killDma() halts the DMA on the requested channel, without any
17813 + * intention of resuming the DMA.
17814 + */
17815 +int MCD_killDma (int channel);
17816 +
17817 +/*
17818 + * MCD_continDma() continues a DMA which as stopped due to encountering an
17819 + * unready buffer descriptor.
17820 + */
17821 +int MCD_continDma (int channel);
17822 +
17823 +/*
17824 + * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
17825 + * running on that channel).
17826 + */
17827 +int MCD_pauseDma (int channel);
17828 +
17829 +/*
17830 + * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
17831 + * running on that channel).
17832 + */
17833 +int MCD_resumeDma (int channel);
17834 +
17835 +/*
17836 + * MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA
17837 + */
17838 +int MCD_csumQuery (int channel, u32 *csum);
17839 +
17840 +/*
17841 + * MCD_getCodeSize provides the packed size required by the microcoded task
17842 + * and structures.
17843 + */
17844 +int MCD_getCodeSize(void);
17845 +
17846 +/*
17847 + * MCD_getVersion provides a pointer to a version string and returns a
17848 + * version number.
17849 + */
17850 +int MCD_getVersion(char **longVersion);
17851 +
17852 +/* macro for setting a location in the variable table */
17853 +#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value
17854 + /* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
17855 + so I'm avoiding surrounding it with "do {} while(0)" */
17856 +
17857 +#endif /* DEFINESONLY */
17858 +
17859 +#endif /* _MCD_API_H */
17860 --- /dev/null
17861 +++ b/drivers/dma/MCD_progCheck.h
17862 @@ -0,0 +1,28 @@
17863 +/*
17864 + * drivers/dma/MCD_progCheck.h
17865 + *
17866 + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
17867 + * Kurt Mahan <kmahan@freescale.com>
17868 + *
17869 + * This program is free software; you can redistribute it and/or
17870 + * modify it under the terms of the GNU General Public License as
17871 + * published by the Free Software Foundation; either version 2 of
17872 + * the License, or (at your option) any later version.
17873 + *
17874 + * This program is distributed in the hope that it will be useful,
17875 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
17876 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17877 + * GNU General Public License for more details.
17878 + *
17879 + * You should have received a copy of the GNU General Public License
17880 + * along with this program; if not, write to the Free Software
17881 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17882 + * MA 02111-1307 USA
17883 + */
17884 +
17885 +/* This file is autogenerated. Do not change */
17886 +
17887 +#define CURRBD 4
17888 +#define DCOUNT 6
17889 +#define DESTPTR 5
17890 +#define SRCPTR 7
17891 --- /dev/null
17892 +++ b/drivers/dma/MCD_tasks.c
17893 @@ -0,0 +1,2465 @@
17894 +/*
17895 + * drivers/dma/MCD_tasks.c
17896 + *
17897 + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
17898 + * Kurt Mahan <kmahan@freescale.com>
17899 + *
17900 + * This program is free software; you can redistribute it and/or
17901 + * modify it under the terms of the GNU General Public License as
17902 + * published by the Free Software Foundation; either version 2 of
17903 + * the License, or (at your option) any later version.
17904 + *
17905 + * This program is distributed in the hope that it will be useful,
17906 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
17907 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17908 + * GNU General Public License for more details.
17909 + *
17910 + * You should have received a copy of the GNU General Public License
17911 + * along with this program; if not, write to the Free Software
17912 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17913 + * MA 02111-1307 USA
17914 + */
17915 +
17916 +#include "MCD_dma.h"
17917 +
17918 +u32 MCD_varTab0[];
17919 +u32 MCD_varTab1[];
17920 +u32 MCD_varTab2[];
17921 +u32 MCD_varTab3[];
17922 +u32 MCD_varTab4[];
17923 +u32 MCD_varTab5[];
17924 +u32 MCD_varTab6[];
17925 +u32 MCD_varTab7[];
17926 +u32 MCD_varTab8[];
17927 +u32 MCD_varTab9[];
17928 +u32 MCD_varTab10[];
17929 +u32 MCD_varTab11[];
17930 +u32 MCD_varTab12[];
17931 +u32 MCD_varTab13[];
17932 +u32 MCD_varTab14[];
17933 +u32 MCD_varTab15[];
17934 +
17935 +u32 MCD_funcDescTab0[];
17936 +#ifdef MCD_INCLUDE_EU
17937 +u32 MCD_funcDescTab1[];
17938 +u32 MCD_funcDescTab2[];
17939 +u32 MCD_funcDescTab3[];
17940 +u32 MCD_funcDescTab4[];
17941 +u32 MCD_funcDescTab5[];
17942 +u32 MCD_funcDescTab6[];
17943 +u32 MCD_funcDescTab7[];
17944 +u32 MCD_funcDescTab8[];
17945 +u32 MCD_funcDescTab9[];
17946 +u32 MCD_funcDescTab10[];
17947 +u32 MCD_funcDescTab11[];
17948 +u32 MCD_funcDescTab12[];
17949 +u32 MCD_funcDescTab13[];
17950 +u32 MCD_funcDescTab14[];
17951 +u32 MCD_funcDescTab15[];
17952 +#endif
17953 +
17954 +u32 MCD_contextSave0[];
17955 +u32 MCD_contextSave1[];
17956 +u32 MCD_contextSave2[];
17957 +u32 MCD_contextSave3[];
17958 +u32 MCD_contextSave4[];
17959 +u32 MCD_contextSave5[];
17960 +u32 MCD_contextSave6[];
17961 +u32 MCD_contextSave7[];
17962 +u32 MCD_contextSave8[];
17963 +u32 MCD_contextSave9[];
17964 +u32 MCD_contextSave10[];
17965 +u32 MCD_contextSave11[];
17966 +u32 MCD_contextSave12[];
17967 +u32 MCD_contextSave13[];
17968 +u32 MCD_contextSave14[];
17969 +u32 MCD_contextSave15[];
17970 +
17971 +u32 MCD_realTaskTableSrc[] =
17972 +{
17973 + 0x00000000,
17974 + 0x00000000,
17975 + (u32)MCD_varTab0, /* Task 0 Variable Table */
17976 + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
17977 + 0x00000000,
17978 + 0x00000000,
17979 + (u32)MCD_contextSave0, /* Task 0 context save space */
17980 + 0x00000000,
17981 + 0x00000000,
17982 + 0x00000000,
17983 + (u32)MCD_varTab1, /* Task 1 Variable Table */
17984 +#ifdef MCD_INCLUDE_EU
17985 + (u32)MCD_funcDescTab1, /* Task 1 Function Descriptor Table & Flags */
17986 +#else
17987 + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
17988 +#endif
17989 + 0x00000000,
17990 + 0x00000000,
17991 + (u32)MCD_contextSave1, /* Task 1 context save space */
17992 + 0x00000000,
17993 + 0x00000000,
17994 + 0x00000000,
17995 + (u32)MCD_varTab2, /* Task 2 Variable Table */
17996 +#ifdef MCD_INCLUDE_EU
17997 + (u32)MCD_funcDescTab2, /* Task 2 Function Descriptor Table & Flags */
17998 +#else
17999 + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
18000 +#endif
18001 + 0x00000000,
18002 + 0x00000000,
18003 + (u32)MCD_contextSave2, /* Task 2 context save space */
18004 + 0x00000000,
18005 + 0x00000000,
18006 + 0x00000000,
18007 + (u32)MCD_varTab3, /* Task 3 Variable Table */
18008 +#ifdef MCD_INCLUDE_EU
18009 + (u32)MCD_funcDescTab3, /* Task 3 Function Descriptor Table & Flags */
18010 +#else
18011 + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
18012 +#endif
18013 + 0x00000000,
18014 + 0x00000000,
18015 + (u32)MCD_contextSave3, /* Task 3 context save space */
18016 + 0x00000000,
18017 + 0x00000000,
18018 + 0x00000000,
18019 + (u32)MCD_varTab4, /* Task 4 Variable Table */
18020 +#ifdef MCD_INCLUDE_EU
18021 + (u32)MCD_funcDescTab4, /* Task 4 Function Descriptor Table & Flags */
18022 +#else
18023 + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
18024 +#endif
18025 + 0x00000000,
18026 + 0x00000000,
18027 + (u32)MCD_contextSave4, /* Task 4 context save space */
18028 + 0x00000000,
18029 + 0x00000000,
18030 + 0x00000000,
18031 + (u32)MCD_varTab5, /* Task 5 Variable Table */
18032 +#ifdef MCD_INCLUDE_EU
18033 + (u32)MCD_funcDescTab5, /* Task 5 Function Descriptor Table & Flags */
18034 +#else
18035 + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
18036 +#endif
18037 + 0x00000000,
18038 + 0x00000000,
18039 + (u32)MCD_contextSave5, /* Task 5 context save space */
18040 + 0x00000000,
18041 + 0x00000000,
18042 + 0x00000000,
18043 + (u32)MCD_varTab6, /* Task 6 Variable Table */
18044 +#ifdef MCD_INCLUDE_EU
18045 + (u32)MCD_funcDescTab6, /* Task 6 Function Descriptor Table & Flags */
18046 +#else
18047 + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
18048 +#endif
18049 + 0x00000000,
18050 + 0x00000000,
18051 + (u32)MCD_contextSave6, /* Task 6 context save space */
18052 + 0x00000000,
18053 + 0x00000000,
18054 + 0x00000000,
18055 + (u32)MCD_varTab7, /* Task 7 Variable Table */
18056 +#ifdef MCD_INCLUDE_EU
18057 + (u32)MCD_funcDescTab7, /* Task 7 Function Descriptor Table & Flags */
18058 +#else
18059 + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
18060 +#endif
18061 + 0x00000000,
18062 + 0x00000000,
18063 + (u32)MCD_contextSave7, /* Task 7 context save space */
18064 + 0x00000000,
18065 + 0x00000000,
18066 + 0x00000000,
18067 + (u32)MCD_varTab8, /* Task 8 Variable Table */
18068 +#ifdef MCD_INCLUDE_EU
18069 + (u32)MCD_funcDescTab8, /* Task 8 Function Descriptor Table & Flags */
18070 +#else
18071 + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
18072 +#endif
18073 + 0x00000000,
18074 + 0x00000000,
18075 + (u32)MCD_contextSave8, /* Task 8 context save space */
18076 + 0x00000000,
18077 + 0x00000000,
18078 + 0x00000000,
18079 + (u32)MCD_varTab9, /* Task 9 Variable Table */
18080 +#ifdef MCD_INCLUDE_EU
18081 + (u32)MCD_funcDescTab9, /* Task 9 Function Descriptor Table & Flags */
18082 +#else
18083 + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
18084 +#endif
18085 + 0x00000000,
18086 + 0x00000000,
18087 + (u32)MCD_contextSave9, /* Task 9 context save space */
18088 + 0x00000000,
18089 + 0x00000000,
18090 + 0x00000000,
18091 + (u32)MCD_varTab10, /* Task 10 Variable Table */
18092 +#ifdef MCD_INCLUDE_EU
18093 + (u32)MCD_funcDescTab10, /* Task 10 Function Descriptor Table & Flags */
18094 +#else
18095 + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
18096 +#endif
18097 + 0x00000000,
18098 + 0x00000000,
18099 + (u32)MCD_contextSave10, /* Task 10 context save space */
18100 + 0x00000000,
18101 + 0x00000000,
18102 + 0x00000000,
18103 + (u32)MCD_varTab11, /* Task 11 Variable Table */
18104 +#ifdef MCD_INCLUDE_EU
18105 + (u32)MCD_funcDescTab11, /* Task 11 Function Descriptor Table & Flags */
18106 +#else
18107 + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
18108 +#endif
18109 + 0x00000000,
18110 + 0x00000000,
18111 + (u32)MCD_contextSave11, /* Task 11 context save space */
18112 + 0x00000000,
18113 + 0x00000000,
18114 + 0x00000000,
18115 + (u32)MCD_varTab12, /* Task 12 Variable Table */
18116 +#ifdef MCD_INCLUDE_EU
18117 + (u32)MCD_funcDescTab12, /* Task 12 Function Descriptor Table & Flags */
18118 +#else
18119 + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
18120 +#endif
18121 + 0x00000000,
18122 + 0x00000000,
18123 + (u32)MCD_contextSave12, /* Task 12 context save space */
18124 + 0x00000000,
18125 + 0x00000000,
18126 + 0x00000000,
18127 + (u32)MCD_varTab13, /* Task 13 Variable Table */
18128 +#ifdef MCD_INCLUDE_EU
18129 + (u32)MCD_funcDescTab13, /* Task 13 Function Descriptor Table & Flags */
18130 +#else
18131 + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
18132 +#endif
18133 + 0x00000000,
18134 + 0x00000000,
18135 + (u32)MCD_contextSave13, /* Task 13 context save space */
18136 + 0x00000000,
18137 + 0x00000000,
18138 + 0x00000000,
18139 + (u32)MCD_varTab14, /* Task 14 Variable Table */
18140 +#ifdef MCD_INCLUDE_EU
18141 + (u32)MCD_funcDescTab14, /* Task 14 Function Descriptor Table & Flags */
18142 +#else
18143 + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
18144 +#endif
18145 + 0x00000000,
18146 + 0x00000000,
18147 + (u32)MCD_contextSave14, /* Task 14 context save space */
18148 + 0x00000000,
18149 + 0x00000000,
18150 + 0x00000000,
18151 + (u32)MCD_varTab15, /* Task 15 Variable Table */
18152 +#ifdef MCD_INCLUDE_EU
18153 + (u32)MCD_funcDescTab15, /* Task 15 Function Descriptor Table & Flags */
18154 +#else
18155 + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
18156 +#endif
18157 + 0x00000000,
18158 + 0x00000000,
18159 + (u32)MCD_contextSave15, /* Task 15 context save space */
18160 + 0x00000000,
18161 +};
18162 +
18163 +
18164 +u32 MCD_varTab0[] =
18165 +{ /* Task 0 Variable Table */
18166 + 0x00000000, /* var[0] */
18167 + 0x00000000, /* var[1] */
18168 + 0x00000000, /* var[2] */
18169 + 0x00000000, /* var[3] */
18170 + 0x00000000, /* var[4] */
18171 + 0x00000000, /* var[5] */
18172 + 0x00000000, /* var[6] */
18173 + 0x00000000, /* var[7] */
18174 + 0x00000000, /* var[8] */
18175 + 0x00000000, /* var[9] */
18176 + 0x00000000, /* var[10] */
18177 + 0x00000000, /* var[11] */
18178 + 0x00000000, /* var[12] */
18179 + 0x00000000, /* var[13] */
18180 + 0x00000000, /* var[14] */
18181 + 0x00000000, /* var[15] */
18182 + 0x00000000, /* var[16] */
18183 + 0x00000000, /* var[17] */
18184 + 0x00000000, /* var[18] */
18185 + 0x00000000, /* var[19] */
18186 + 0x00000000, /* var[20] */
18187 + 0x00000000, /* var[21] */
18188 + 0x00000000, /* var[22] */
18189 + 0x00000000, /* var[23] */
18190 + 0xe0000000, /* inc[0] */
18191 + 0x20000000, /* inc[1] */
18192 + 0x2000ffff, /* inc[2] */
18193 + 0x00000000, /* inc[3] */
18194 + 0x00000000, /* inc[4] */
18195 + 0x00000000, /* inc[5] */
18196 + 0x00000000, /* inc[6] */
18197 + 0x00000000, /* inc[7] */
18198 +};
18199 +
18200 +
18201 +u32 MCD_varTab1[] =
18202 +{ /* Task 1 Variable Table */
18203 + 0x00000000, /* var[0] */
18204 + 0x00000000, /* var[1] */
18205 + 0x00000000, /* var[2] */
18206 + 0x00000000, /* var[3] */
18207 + 0x00000000, /* var[4] */
18208 + 0x00000000, /* var[5] */
18209 + 0x00000000, /* var[6] */
18210 + 0x00000000, /* var[7] */
18211 + 0x00000000, /* var[8] */
18212 + 0x00000000, /* var[9] */
18213 + 0x00000000, /* var[10] */
18214 + 0x00000000, /* var[11] */
18215 + 0x00000000, /* var[12] */
18216 + 0x00000000, /* var[13] */
18217 + 0x00000000, /* var[14] */
18218 + 0x00000000, /* var[15] */
18219 + 0x00000000, /* var[16] */
18220 + 0x00000000, /* var[17] */
18221 + 0x00000000, /* var[18] */
18222 + 0x00000000, /* var[19] */
18223 + 0x00000000, /* var[20] */
18224 + 0x00000000, /* var[21] */
18225 + 0x00000000, /* var[22] */
18226 + 0x00000000, /* var[23] */
18227 + 0xe0000000, /* inc[0] */
18228 + 0x20000000, /* inc[1] */
18229 + 0x2000ffff, /* inc[2] */
18230 + 0x00000000, /* inc[3] */
18231 + 0x00000000, /* inc[4] */
18232 + 0x00000000, /* inc[5] */
18233 + 0x00000000, /* inc[6] */
18234 + 0x00000000, /* inc[7] */
18235 +};
18236 +
18237 +u32 MCD_varTab2[]=
18238 +{ /* Task 2 Variable Table */
18239 + 0x00000000, /* var[0] */
18240 + 0x00000000, /* var[1] */
18241 + 0x00000000, /* var[2] */
18242 + 0x00000000, /* var[3] */
18243 + 0x00000000, /* var[4] */
18244 + 0x00000000, /* var[5] */
18245 + 0x00000000, /* var[6] */
18246 + 0x00000000, /* var[7] */
18247 + 0x00000000, /* var[8] */
18248 + 0x00000000, /* var[9] */
18249 + 0x00000000, /* var[10] */
18250 + 0x00000000, /* var[11] */
18251 + 0x00000000, /* var[12] */
18252 + 0x00000000, /* var[13] */
18253 + 0x00000000, /* var[14] */
18254 + 0x00000000, /* var[15] */
18255 + 0x00000000, /* var[16] */
18256 + 0x00000000, /* var[17] */
18257 + 0x00000000, /* var[18] */
18258 + 0x00000000, /* var[19] */
18259 + 0x00000000, /* var[20] */
18260 + 0x00000000, /* var[21] */
18261 + 0x00000000, /* var[22] */
18262 + 0x00000000, /* var[23] */
18263 + 0xe0000000, /* inc[0] */
18264 + 0x20000000, /* inc[1] */
18265 + 0x2000ffff, /* inc[2] */
18266 + 0x00000000, /* inc[3] */
18267 + 0x00000000, /* inc[4] */
18268 + 0x00000000, /* inc[5] */
18269 + 0x00000000, /* inc[6] */
18270 + 0x00000000, /* inc[7] */
18271 +};
18272 +
18273 +u32 MCD_varTab3[]=
18274 +{ /* Task 3 Variable Table */
18275 + 0x00000000, /* var[0] */
18276 + 0x00000000, /* var[1] */
18277 + 0x00000000, /* var[2] */
18278 + 0x00000000, /* var[3] */
18279 + 0x00000000, /* var[4] */
18280 + 0x00000000, /* var[5] */
18281 + 0x00000000, /* var[6] */
18282 + 0x00000000, /* var[7] */
18283 + 0x00000000, /* var[8] */
18284 + 0x00000000, /* var[9] */
18285 + 0x00000000, /* var[10] */
18286 + 0x00000000, /* var[11] */
18287 + 0x00000000, /* var[12] */
18288 + 0x00000000, /* var[13] */
18289 + 0x00000000, /* var[14] */
18290 + 0x00000000, /* var[15] */
18291 + 0x00000000, /* var[16] */
18292 + 0x00000000, /* var[17] */
18293 + 0x00000000, /* var[18] */
18294 + 0x00000000, /* var[19] */
18295 + 0x00000000, /* var[20] */
18296 + 0x00000000, /* var[21] */
18297 + 0x00000000, /* var[22] */
18298 + 0x00000000, /* var[23] */
18299 + 0xe0000000, /* inc[0] */
18300 + 0x20000000, /* inc[1] */
18301 + 0x2000ffff, /* inc[2] */
18302 + 0x00000000, /* inc[3] */
18303 + 0x00000000, /* inc[4] */
18304 + 0x00000000, /* inc[5] */
18305 + 0x00000000, /* inc[6] */
18306 + 0x00000000, /* inc[7] */
18307 +};
18308 +
18309 +u32 MCD_varTab4[]=
18310 +{ /* Task 4 Variable Table */
18311 + 0x00000000, /* var[0] */
18312 + 0x00000000, /* var[1] */
18313 + 0x00000000, /* var[2] */
18314 + 0x00000000, /* var[3] */
18315 + 0x00000000, /* var[4] */
18316 + 0x00000000, /* var[5] */
18317 + 0x00000000, /* var[6] */
18318 + 0x00000000, /* var[7] */
18319 + 0x00000000, /* var[8] */
18320 + 0x00000000, /* var[9] */
18321 + 0x00000000, /* var[10] */
18322 + 0x00000000, /* var[11] */
18323 + 0x00000000, /* var[12] */
18324 + 0x00000000, /* var[13] */
18325 + 0x00000000, /* var[14] */
18326 + 0x00000000, /* var[15] */
18327 + 0x00000000, /* var[16] */
18328 + 0x00000000, /* var[17] */
18329 + 0x00000000, /* var[18] */
18330 + 0x00000000, /* var[19] */
18331 + 0x00000000, /* var[20] */
18332 + 0x00000000, /* var[21] */
18333 + 0x00000000, /* var[22] */
18334 + 0x00000000, /* var[23] */
18335 + 0xe0000000, /* inc[0] */
18336 + 0x20000000, /* inc[1] */
18337 + 0x2000ffff, /* inc[2] */
18338 + 0x00000000, /* inc[3] */
18339 + 0x00000000, /* inc[4] */
18340 + 0x00000000, /* inc[5] */
18341 + 0x00000000, /* inc[6] */
18342 + 0x00000000, /* inc[7] */
18343 +};
18344 +
18345 +u32 MCD_varTab5[]=
18346 +{ /* Task 5 Variable Table */
18347 + 0x00000000, /* var[0] */
18348 + 0x00000000, /* var[1] */
18349 + 0x00000000, /* var[2] */
18350 + 0x00000000, /* var[3] */
18351 + 0x00000000, /* var[4] */
18352 + 0x00000000, /* var[5] */
18353 + 0x00000000, /* var[6] */
18354 + 0x00000000, /* var[7] */
18355 + 0x00000000, /* var[8] */
18356 + 0x00000000, /* var[9] */
18357 + 0x00000000, /* var[10] */
18358 + 0x00000000, /* var[11] */
18359 + 0x00000000, /* var[12] */
18360 + 0x00000000, /* var[13] */
18361 + 0x00000000, /* var[14] */
18362 + 0x00000000, /* var[15] */
18363 + 0x00000000, /* var[16] */
18364 + 0x00000000, /* var[17] */
18365 + 0x00000000, /* var[18] */
18366 + 0x00000000, /* var[19] */
18367 + 0x00000000, /* var[20] */
18368 + 0x00000000, /* var[21] */
18369 + 0x00000000, /* var[22] */
18370 + 0x00000000, /* var[23] */
18371 + 0xe0000000, /* inc[0] */
18372 + 0x20000000, /* inc[1] */
18373 + 0x2000ffff, /* inc[2] */
18374 + 0x00000000, /* inc[3] */
18375 + 0x00000000, /* inc[4] */
18376 + 0x00000000, /* inc[5] */
18377 + 0x00000000, /* inc[6] */
18378 + 0x00000000, /* inc[7] */
18379 +};
18380 +
18381 +u32 MCD_varTab6[]=
18382 +{ /* Task 6 Variable Table */
18383 + 0x00000000, /* var[0] */
18384 + 0x00000000, /* var[1] */
18385 + 0x00000000, /* var[2] */
18386 + 0x00000000, /* var[3] */
18387 + 0x00000000, /* var[4] */
18388 + 0x00000000, /* var[5] */
18389 + 0x00000000, /* var[6] */
18390 + 0x00000000, /* var[7] */
18391 + 0x00000000, /* var[8] */
18392 + 0x00000000, /* var[9] */
18393 + 0x00000000, /* var[10] */
18394 + 0x00000000, /* var[11] */
18395 + 0x00000000, /* var[12] */
18396 + 0x00000000, /* var[13] */
18397 + 0x00000000, /* var[14] */
18398 + 0x00000000, /* var[15] */
18399 + 0x00000000, /* var[16] */
18400 + 0x00000000, /* var[17] */
18401 + 0x00000000, /* var[18] */
18402 + 0x00000000, /* var[19] */
18403 + 0x00000000, /* var[20] */
18404 + 0x00000000, /* var[21] */
18405 + 0x00000000, /* var[22] */
18406 + 0x00000000, /* var[23] */
18407 + 0xe0000000, /* inc[0] */
18408 + 0x20000000, /* inc[1] */
18409 + 0x2000ffff, /* inc[2] */
18410 + 0x00000000, /* inc[3] */
18411 + 0x00000000, /* inc[4] */
18412 + 0x00000000, /* inc[5] */
18413 + 0x00000000, /* inc[6] */
18414 + 0x00000000, /* inc[7] */
18415 +};
18416 +
18417 +u32 MCD_varTab7[]=
18418 +{ /* Task 7 Variable Table */
18419 + 0x00000000, /* var[0] */
18420 + 0x00000000, /* var[1] */
18421 + 0x00000000, /* var[2] */
18422 + 0x00000000, /* var[3] */
18423 + 0x00000000, /* var[4] */
18424 + 0x00000000, /* var[5] */
18425 + 0x00000000, /* var[6] */
18426 + 0x00000000, /* var[7] */
18427 + 0x00000000, /* var[8] */
18428 + 0x00000000, /* var[9] */
18429 + 0x00000000, /* var[10] */
18430 + 0x00000000, /* var[11] */
18431 + 0x00000000, /* var[12] */
18432 + 0x00000000, /* var[13] */
18433 + 0x00000000, /* var[14] */
18434 + 0x00000000, /* var[15] */
18435 + 0x00000000, /* var[16] */
18436 + 0x00000000, /* var[17] */
18437 + 0x00000000, /* var[18] */
18438 + 0x00000000, /* var[19] */
18439 + 0x00000000, /* var[20] */
18440 + 0x00000000, /* var[21] */
18441 + 0x00000000, /* var[22] */
18442 + 0x00000000, /* var[23] */
18443 + 0xe0000000, /* inc[0] */
18444 + 0x20000000, /* inc[1] */
18445 + 0x2000ffff, /* inc[2] */
18446 + 0x00000000, /* inc[3] */
18447 + 0x00000000, /* inc[4] */
18448 + 0x00000000, /* inc[5] */
18449 + 0x00000000, /* inc[6] */
18450 + 0x00000000, /* inc[7] */
18451 +};
18452 +
18453 +u32 MCD_varTab8[]=
18454 +{ /* Task 8 Variable Table */
18455 + 0x00000000, /* var[0] */
18456 + 0x00000000, /* var[1] */
18457 + 0x00000000, /* var[2] */
18458 + 0x00000000, /* var[3] */
18459 + 0x00000000, /* var[4] */
18460 + 0x00000000, /* var[5] */
18461 + 0x00000000, /* var[6] */
18462 + 0x00000000, /* var[7] */
18463 + 0x00000000, /* var[8] */
18464 + 0x00000000, /* var[9] */
18465 + 0x00000000, /* var[10] */
18466 + 0x00000000, /* var[11] */
18467 + 0x00000000, /* var[12] */
18468 + 0x00000000, /* var[13] */
18469 + 0x00000000, /* var[14] */
18470 + 0x00000000, /* var[15] */
18471 + 0x00000000, /* var[16] */
18472 + 0x00000000, /* var[17] */
18473 + 0x00000000, /* var[18] */
18474 + 0x00000000, /* var[19] */
18475 + 0x00000000, /* var[20] */
18476 + 0x00000000, /* var[21] */
18477 + 0x00000000, /* var[22] */
18478 + 0x00000000, /* var[23] */
18479 + 0xe0000000, /* inc[0] */
18480 + 0x20000000, /* inc[1] */
18481 + 0x2000ffff, /* inc[2] */
18482 + 0x00000000, /* inc[3] */
18483 + 0x00000000, /* inc[4] */
18484 + 0x00000000, /* inc[5] */
18485 + 0x00000000, /* inc[6] */
18486 + 0x00000000, /* inc[7] */
18487 +};
18488 +
18489 +u32 MCD_varTab9[]=
18490 +{ /* Task 9 Variable Table */
18491 + 0x00000000, /* var[0] */
18492 + 0x00000000, /* var[1] */
18493 + 0x00000000, /* var[2] */
18494 + 0x00000000, /* var[3] */
18495 + 0x00000000, /* var[4] */
18496 + 0x00000000, /* var[5] */
18497 + 0x00000000, /* var[6] */
18498 + 0x00000000, /* var[7] */
18499 + 0x00000000, /* var[8] */
18500 + 0x00000000, /* var[9] */
18501 + 0x00000000, /* var[10] */
18502 + 0x00000000, /* var[11] */
18503 + 0x00000000, /* var[12] */
18504 + 0x00000000, /* var[13] */
18505 + 0x00000000, /* var[14] */
18506 + 0x00000000, /* var[15] */
18507 + 0x00000000, /* var[16] */
18508 + 0x00000000, /* var[17] */
18509 + 0x00000000, /* var[18] */
18510 + 0x00000000, /* var[19] */
18511 + 0x00000000, /* var[20] */
18512 + 0x00000000, /* var[21] */
18513 + 0x00000000, /* var[22] */
18514 + 0x00000000, /* var[23] */
18515 + 0xe0000000, /* inc[0] */
18516 + 0x20000000, /* inc[1] */
18517 + 0x2000ffff, /* inc[2] */
18518 + 0x00000000, /* inc[3] */
18519 + 0x00000000, /* inc[4] */
18520 + 0x00000000, /* inc[5] */
18521 + 0x00000000, /* inc[6] */
18522 + 0x00000000, /* inc[7] */
18523 +};
18524 +
18525 +u32 MCD_varTab10[]=
18526 +{ /* Task 10 Variable Table */
18527 + 0x00000000, /* var[0] */
18528 + 0x00000000, /* var[1] */
18529 + 0x00000000, /* var[2] */
18530 + 0x00000000, /* var[3] */
18531 + 0x00000000, /* var[4] */
18532 + 0x00000000, /* var[5] */
18533 + 0x00000000, /* var[6] */
18534 + 0x00000000, /* var[7] */
18535 + 0x00000000, /* var[8] */
18536 + 0x00000000, /* var[9] */
18537 + 0x00000000, /* var[10] */
18538 + 0x00000000, /* var[11] */
18539 + 0x00000000, /* var[12] */
18540 + 0x00000000, /* var[13] */
18541 + 0x00000000, /* var[14] */
18542 + 0x00000000, /* var[15] */
18543 + 0x00000000, /* var[16] */
18544 + 0x00000000, /* var[17] */
18545 + 0x00000000, /* var[18] */
18546 + 0x00000000, /* var[19] */
18547 + 0x00000000, /* var[20] */
18548 + 0x00000000, /* var[21] */
18549 + 0x00000000, /* var[22] */
18550 + 0x00000000, /* var[23] */
18551 + 0xe0000000, /* inc[0] */
18552 + 0x20000000, /* inc[1] */
18553 + 0x2000ffff, /* inc[2] */
18554 + 0x00000000, /* inc[3] */
18555 + 0x00000000, /* inc[4] */
18556 + 0x00000000, /* inc[5] */
18557 + 0x00000000, /* inc[6] */
18558 + 0x00000000, /* inc[7] */
18559 +};
18560 +
18561 +u32 MCD_varTab11[]=
18562 +{ /* Task 11 Variable Table */
18563 + 0x00000000, /* var[0] */
18564 + 0x00000000, /* var[1] */
18565 + 0x00000000, /* var[2] */
18566 + 0x00000000, /* var[3] */
18567 + 0x00000000, /* var[4] */
18568 + 0x00000000, /* var[5] */
18569 + 0x00000000, /* var[6] */
18570 + 0x00000000, /* var[7] */
18571 + 0x00000000, /* var[8] */
18572 + 0x00000000, /* var[9] */
18573 + 0x00000000, /* var[10] */
18574 + 0x00000000, /* var[11] */
18575 + 0x00000000, /* var[12] */
18576 + 0x00000000, /* var[13] */
18577 + 0x00000000, /* var[14] */
18578 + 0x00000000, /* var[15] */
18579 + 0x00000000, /* var[16] */
18580 + 0x00000000, /* var[17] */
18581 + 0x00000000, /* var[18] */
18582 + 0x00000000, /* var[19] */
18583 + 0x00000000, /* var[20] */
18584 + 0x00000000, /* var[21] */
18585 + 0x00000000, /* var[22] */
18586 + 0x00000000, /* var[23] */
18587 + 0xe0000000, /* inc[0] */
18588 + 0x20000000, /* inc[1] */
18589 + 0x2000ffff, /* inc[2] */
18590 + 0x00000000, /* inc[3] */
18591 + 0x00000000, /* inc[4] */
18592 + 0x00000000, /* inc[5] */
18593 + 0x00000000, /* inc[6] */
18594 + 0x00000000, /* inc[7] */
18595 +};
18596 +
18597 +u32 MCD_varTab12[]=
18598 +{ /* Task 12 Variable Table */
18599 + 0x00000000, /* var[0] */
18600 + 0x00000000, /* var[1] */
18601 + 0x00000000, /* var[2] */
18602 + 0x00000000, /* var[3] */
18603 + 0x00000000, /* var[4] */
18604 + 0x00000000, /* var[5] */
18605 + 0x00000000, /* var[6] */
18606 + 0x00000000, /* var[7] */
18607 + 0x00000000, /* var[8] */
18608 + 0x00000000, /* var[9] */
18609 + 0x00000000, /* var[10] */
18610 + 0x00000000, /* var[11] */
18611 + 0x00000000, /* var[12] */
18612 + 0x00000000, /* var[13] */
18613 + 0x00000000, /* var[14] */
18614 + 0x00000000, /* var[15] */
18615 + 0x00000000, /* var[16] */
18616 + 0x00000000, /* var[17] */
18617 + 0x00000000, /* var[18] */
18618 + 0x00000000, /* var[19] */
18619 + 0x00000000, /* var[20] */
18620 + 0x00000000, /* var[21] */
18621 + 0x00000000, /* var[22] */
18622 + 0x00000000, /* var[23] */
18623 + 0xe0000000, /* inc[0] */
18624 + 0x20000000, /* inc[1] */
18625 + 0x2000ffff, /* inc[2] */
18626 + 0x00000000, /* inc[3] */
18627 + 0x00000000, /* inc[4] */
18628 + 0x00000000, /* inc[5] */
18629 + 0x00000000, /* inc[6] */
18630 + 0x00000000, /* inc[7] */
18631 +};
18632 +
18633 +u32 MCD_varTab13[]=
18634 +{ /* Task 13 Variable Table */
18635 + 0x00000000, /* var[0] */
18636 + 0x00000000, /* var[1] */
18637 + 0x00000000, /* var[2] */
18638 + 0x00000000, /* var[3] */
18639 + 0x00000000, /* var[4] */
18640 + 0x00000000, /* var[5] */
18641 + 0x00000000, /* var[6] */
18642 + 0x00000000, /* var[7] */
18643 + 0x00000000, /* var[8] */
18644 + 0x00000000, /* var[9] */
18645 + 0x00000000, /* var[10] */
18646 + 0x00000000, /* var[11] */
18647 + 0x00000000, /* var[12] */
18648 + 0x00000000, /* var[13] */
18649 + 0x00000000, /* var[14] */
18650 + 0x00000000, /* var[15] */
18651 + 0x00000000, /* var[16] */
18652 + 0x00000000, /* var[17] */
18653 + 0x00000000, /* var[18] */
18654 + 0x00000000, /* var[19] */
18655 + 0x00000000, /* var[20] */
18656 + 0x00000000, /* var[21] */
18657 + 0x00000000, /* var[22] */
18658 + 0x00000000, /* var[23] */
18659 + 0xe0000000, /* inc[0] */
18660 + 0x20000000, /* inc[1] */
18661 + 0x2000ffff, /* inc[2] */
18662 + 0x00000000, /* inc[3] */
18663 + 0x00000000, /* inc[4] */
18664 + 0x00000000, /* inc[5] */
18665 + 0x00000000, /* inc[6] */
18666 + 0x00000000, /* inc[7] */
18667 +};
18668 +
18669 +u32 MCD_varTab14[]=
18670 +{ /* Task 14 Variable Table */
18671 + 0x00000000, /* var[0] */
18672 + 0x00000000, /* var[1] */
18673 + 0x00000000, /* var[2] */
18674 + 0x00000000, /* var[3] */
18675 + 0x00000000, /* var[4] */
18676 + 0x00000000, /* var[5] */
18677 + 0x00000000, /* var[6] */
18678 + 0x00000000, /* var[7] */
18679 + 0x00000000, /* var[8] */
18680 + 0x00000000, /* var[9] */
18681 + 0x00000000, /* var[10] */
18682 + 0x00000000, /* var[11] */
18683 + 0x00000000, /* var[12] */
18684 + 0x00000000, /* var[13] */
18685 + 0x00000000, /* var[14] */
18686 + 0x00000000, /* var[15] */
18687 + 0x00000000, /* var[16] */
18688 + 0x00000000, /* var[17] */
18689 + 0x00000000, /* var[18] */
18690 + 0x00000000, /* var[19] */
18691 + 0x00000000, /* var[20] */
18692 + 0x00000000, /* var[21] */
18693 + 0x00000000, /* var[22] */
18694 + 0x00000000, /* var[23] */
18695 + 0xe0000000, /* inc[0] */
18696 + 0x20000000, /* inc[1] */
18697 + 0x2000ffff, /* inc[2] */
18698 + 0x00000000, /* inc[3] */
18699 + 0x00000000, /* inc[4] */
18700 + 0x00000000, /* inc[5] */
18701 + 0x00000000, /* inc[6] */
18702 + 0x00000000, /* inc[7] */
18703 +};
18704 +
18705 +u32 MCD_varTab15[]=
18706 +{ /* Task 15 Variable Table */
18707 + 0x00000000, /* var[0] */
18708 + 0x00000000, /* var[1] */
18709 + 0x00000000, /* var[2] */
18710 + 0x00000000, /* var[3] */
18711 + 0x00000000, /* var[4] */
18712 + 0x00000000, /* var[5] */
18713 + 0x00000000, /* var[6] */
18714 + 0x00000000, /* var[7] */
18715 + 0x00000000, /* var[8] */
18716 + 0x00000000, /* var[9] */
18717 + 0x00000000, /* var[10] */
18718 + 0x00000000, /* var[11] */
18719 + 0x00000000, /* var[12] */
18720 + 0x00000000, /* var[13] */
18721 + 0x00000000, /* var[14] */
18722 + 0x00000000, /* var[15] */
18723 + 0x00000000, /* var[16] */
18724 + 0x00000000, /* var[17] */
18725 + 0x00000000, /* var[18] */
18726 + 0x00000000, /* var[19] */
18727 + 0x00000000, /* var[20] */
18728 + 0x00000000, /* var[21] */
18729 + 0x00000000, /* var[22] */
18730 + 0x00000000, /* var[23] */
18731 + 0xe0000000, /* inc[0] */
18732 + 0x20000000, /* inc[1] */
18733 + 0x2000ffff, /* inc[2] */
18734 + 0x00000000, /* inc[3] */
18735 + 0x00000000, /* inc[4] */
18736 + 0x00000000, /* inc[5] */
18737 + 0x00000000, /* inc[6] */
18738 + 0x00000000, /* inc[7] */
18739 +};
18740 +
18741 +u32 MCD_funcDescTab0[]=
18742 +{ /* Task 0 Function Descriptor Table */
18743 + 0x00000000,
18744 + 0x00000000,
18745 + 0x00000000,
18746 + 0x00000000,
18747 + 0x00000000,
18748 + 0x00000000,
18749 + 0x00000000,
18750 + 0x00000000,
18751 + 0x00000000,
18752 + 0x00000000,
18753 + 0x00000000,
18754 + 0x00000000,
18755 + 0x00000000,
18756 + 0x00000000,
18757 + 0x00000000,
18758 + 0x00000000,
18759 + 0x00000000,
18760 + 0x00000000,
18761 + 0x00000000,
18762 + 0x00000000,
18763 + 0x00000000,
18764 + 0x00000000,
18765 + 0x00000000,
18766 + 0x00000000,
18767 + 0x00000000,
18768 + 0x00000000,
18769 + 0x00000000,
18770 + 0x00000000,
18771 + 0x00000000,
18772 + 0x00000000,
18773 + 0x00000000,
18774 + 0x00000000,
18775 + 0x00000000,
18776 + 0x00000000,
18777 + 0x00000000,
18778 + 0x00000000,
18779 + 0x00000000,
18780 + 0x00000000,
18781 + 0x00000000,
18782 + 0x00000000,
18783 + 0x00000000,
18784 + 0x00000000,
18785 + 0x00000000,
18786 + 0x00000000,
18787 + 0x00000000,
18788 + 0x00000000,
18789 + 0x00000000,
18790 + 0x00000000,
18791 + 0xa0045670, /* mainFunc(), EU# 3 */
18792 + 0xa0000000, /* rsduFunc(), EU# 3 */
18793 + 0xa0000000, /* crcAccumVal(), EU# 3 */
18794 + 0x20000000, /* setCrcAccum(), EU# 3 */
18795 + 0x21800000, /* and(), EU# 3 */
18796 + 0x21e00000, /* or(), EU# 3 */
18797 + 0x20400000, /* add(), EU# 3 */
18798 + 0x20500000, /* sub(), EU# 3 */
18799 + 0x205a0000, /* andNot(), EU# 3 */
18800 + 0x20a00000, /* shiftR(), EU# 3 */
18801 + 0x202fa000, /* andReadyBit(), EU# 3 */
18802 + 0x202f9000, /* andNotReadyBit(), EU# 3 */
18803 + 0x202ea000, /* andWrapBit(), EU# 3 */
18804 + 0x202da000, /* andLastBit(), EU# 3 */
18805 + 0x202e2000, /* andInterruptBit(), EU# 3 */
18806 + 0x202f2000, /* andCrcRestartBit(), EU# 3 */
18807 +};
18808 +
18809 +#ifdef MCD_INCLUDE_EU
18810 +u32 MCD_funcDescTab1[]=
18811 +{ /* Task 1 Function Descriptor Table */
18812 + 0x00000000,
18813 + 0x00000000,
18814 + 0x00000000,
18815 + 0x00000000,
18816 + 0x00000000,
18817 + 0x00000000,
18818 + 0x00000000,
18819 + 0x00000000,
18820 + 0x00000000,
18821 + 0x00000000,
18822 + 0x00000000,
18823 + 0x00000000,
18824 + 0x00000000,
18825 + 0x00000000,
18826 + 0x00000000,
18827 + 0x00000000,
18828 + 0x00000000,
18829 + 0x00000000,
18830 + 0x00000000,
18831 + 0x00000000,
18832 + 0x00000000,
18833 + 0x00000000,
18834 + 0x00000000,
18835 + 0x00000000,
18836 + 0x00000000,
18837 + 0x00000000,
18838 + 0x00000000,
18839 + 0x00000000,
18840 + 0x00000000,
18841 + 0x00000000,
18842 + 0x00000000,
18843 + 0x00000000,
18844 + 0x00000000,
18845 + 0x00000000,
18846 + 0x00000000,
18847 + 0x00000000,
18848 + 0x00000000,
18849 + 0x00000000,
18850 + 0x00000000,
18851 + 0x00000000,
18852 + 0x00000000,
18853 + 0x00000000,
18854 + 0x00000000,
18855 + 0x00000000,
18856 + 0x00000000,
18857 + 0x00000000,
18858 + 0x00000000,
18859 + 0x00000000,
18860 + 0xa0045670, /* mainFunc(), EU# 3 */
18861 + 0xa0000000, /* rsduFunc(), EU# 3 */
18862 + 0xa0000000, /* crcAccumVal(), EU# 3 */
18863 + 0x20000000, /* setCrcAccum(), EU# 3 */
18864 + 0x21800000, /* and(), EU# 3 */
18865 + 0x21e00000, /* or(), EU# 3 */
18866 + 0x20400000, /* add(), EU# 3 */
18867 + 0x20500000, /* sub(), EU# 3 */
18868 + 0x205a0000, /* andNot(), EU# 3 */
18869 + 0x20a00000, /* shiftR(), EU# 3 */
18870 + 0x202fa000, /* andReadyBit(), EU# 3 */
18871 + 0x202f9000, /* andNotReadyBit(), EU# 3 */
18872 + 0x202ea000, /* andWrapBit(), EU# 3 */
18873 + 0x202da000, /* andLastBit(), EU# 3 */
18874 + 0x202e2000, /* andInterruptBit(), EU# 3 */
18875 + 0x202f2000, /* andCrcRestartBit(), EU# 3 */
18876 +};
18877 +
18878 +u32 MCD_funcDescTab2[]=
18879 +{ /* Task 2 Function Descriptor Table */
18880 + 0x00000000,
18881 + 0x00000000,
18882 + 0x00000000,
18883 + 0x00000000,
18884 + 0x00000000,
18885 + 0x00000000,
18886 + 0x00000000,
18887 + 0x00000000,
18888 + 0x00000000,
18889 + 0x00000000,
18890 + 0x00000000,
18891 + 0x00000000,
18892 + 0x00000000,
18893 + 0x00000000,
18894 + 0x00000000,
18895 + 0x00000000,
18896 + 0x00000000,
18897 + 0x00000000,
18898 + 0x00000000,
18899 + 0x00000000,
18900 + 0x00000000,
18901 + 0x00000000,
18902 + 0x00000000,
18903 + 0x00000000,
18904 + 0x00000000,
18905 + 0x00000000,
18906 + 0x00000000,
18907 + 0x00000000,
18908 + 0x00000000,
18909 + 0x00000000,
18910 + 0x00000000,
18911 + 0x00000000,
18912 + 0x00000000,
18913 + 0x00000000,
18914 + 0x00000000,
18915 + 0x00000000,
18916 + 0x00000000,
18917 + 0x00000000,
18918 + 0x00000000,
18919 + 0x00000000,
18920 + 0x00000000,
18921 + 0x00000000,
18922 + 0x00000000,
18923 + 0x00000000,
18924 + 0x00000000,
18925 + 0x00000000,
18926 + 0x00000000,
18927 + 0x00000000,
18928 + 0xa0045670, /* mainFunc(), EU# 3 */
18929 + 0xa0000000, /* rsduFunc(), EU# 3 */
18930 + 0xa0000000, /* crcAccumVal(), EU# 3 */
18931 + 0x20000000, /* setCrcAccum(), EU# 3 */
18932 + 0x21800000, /* and(), EU# 3 */
18933 + 0x21e00000, /* or(), EU# 3 */
18934 + 0x20400000, /* add(), EU# 3 */
18935 + 0x20500000, /* sub(), EU# 3 */
18936 + 0x205a0000, /* andNot(), EU# 3 */
18937 + 0x20a00000, /* shiftR(), EU# 3 */
18938 + 0x202fa000, /* andReadyBit(), EU# 3 */
18939 + 0x202f9000, /* andNotReadyBit(), EU# 3 */
18940 + 0x202ea000, /* andWrapBit(), EU# 3 */
18941 + 0x202da000, /* andLastBit(), EU# 3 */
18942 + 0x202e2000, /* andInterruptBit(), EU# 3 */
18943 + 0x202f2000, /* andCrcRestartBit(), EU# 3 */
18944 +};
18945 +
18946 +u32 MCD_funcDescTab3[]=
18947 +{ /* Task 3 Function Descriptor Table */
18948 + 0x00000000,
18949 + 0x00000000,
18950 + 0x00000000,
18951 + 0x00000000,
18952 + 0x00000000,
18953 + 0x00000000,
18954 + 0x00000000,
18955 + 0x00000000,
18956 + 0x00000000,
18957 + 0x00000000,
18958 + 0x00000000,
18959 + 0x00000000,
18960 + 0x00000000,
18961 + 0x00000000,
18962 + 0x00000000,
18963 + 0x00000000,
18964 + 0x00000000,
18965 + 0x00000000,
18966 + 0x00000000,
18967 + 0x00000000,
18968 + 0x00000000,
18969 + 0x00000000,
18970 + 0x00000000,
18971 + 0x00000000,
18972 + 0x00000000,
18973 + 0x00000000,
18974 + 0x00000000,
18975 + 0x00000000,
18976 + 0x00000000,
18977 + 0x00000000,
18978 + 0x00000000,
18979 + 0x00000000,
18980 + 0x00000000,
18981 + 0x00000000,
18982 + 0x00000000,
18983 + 0x00000000,
18984 + 0x00000000,
18985 + 0x00000000,
18986 + 0x00000000,
18987 + 0x00000000,
18988 + 0x00000000,
18989 + 0x00000000,
18990 + 0x00000000,
18991 + 0x00000000,
18992 + 0x00000000,
18993 + 0x00000000,
18994 + 0x00000000,
18995 + 0x00000000,
18996 + 0xa0045670, /* mainFunc(), EU# 3 */
18997 + 0xa0000000, /* rsduFunc(), EU# 3 */
18998 + 0xa0000000, /* crcAccumVal(), EU# 3 */
18999 + 0x20000000, /* setCrcAccum(), EU# 3 */
19000 + 0x21800000, /* and(), EU# 3 */
19001 + 0x21e00000, /* or(), EU# 3 */
19002 + 0x20400000, /* add(), EU# 3 */
19003 + 0x20500000, /* sub(), EU# 3 */
19004 + 0x205a0000, /* andNot(), EU# 3 */
19005 + 0x20a00000, /* shiftR(), EU# 3 */
19006 + 0x202fa000, /* andReadyBit(), EU# 3 */
19007 + 0x202f9000, /* andNotReadyBit(), EU# 3 */
19008 + 0x202ea000, /* andWrapBit(), EU# 3 */
19009 + 0x202da000, /* andLastBit(), EU# 3 */
19010 + 0x202e2000, /* andInterruptBit(), EU# 3 */
19011 + 0x202f2000, /* andCrcRestartBit(), EU# 3 */
19012 +};
19013 +
19014 +u32 MCD_funcDescTab4[]=
19015 +{ /* Task 4 Function Descriptor Table */
19016 + 0x00000000,
19017 + 0x00000000,
19018 + 0x00000000,
19019 + 0x00000000,
19020 + 0x00000000,
19021 + 0x00000000,
19022 + 0x00000000,
19023 + 0x00000000,
19024 + 0x00000000,
19025 + 0x00000000,
19026 + 0x00000000,
19027 + 0x00000000,
19028 + 0x00000000,
19029 + 0x00000000,
19030 + 0x00000000,
19031 + 0x00000000,
19032 + 0x00000000,
19033 + 0x00000000,
19034 + 0x00000000,
19035 + 0x00000000,
19036 + 0x00000000,
19037 + 0x00000000,
19038 + 0x00000000,
19039 + 0x00000000,
19040 + 0x00000000,
19041 + 0x00000000,
19042 + 0x00000000,
19043 + 0x00000000,
19044 + 0x00000000,
19045 + 0x00000000,
19046 + 0x00000000,
19047 + 0x00000000,
19048 + 0x00000000,
19049 + 0x00000000,
19050 + 0x00000000,
19051 + 0x00000000,
19052 + 0x00000000,
19053 + 0x00000000,
19054 + 0x00000000,
19055 + 0x00000000,
19056 + 0x00000000,
19057 + 0x00000000,
19058 + 0x00000000,
19059 + 0x00000000,
19060 + 0x00000000,
19061 + 0x00000000,
19062 + 0x00000000,
19063 + 0x00000000,
19064 + 0xa0045670, /* mainFunc(), EU# 3 */
19065 + 0xa0000000, /* rsduFunc(), EU# 3 */
19066 + 0xa0000000, /* crcAccumVal(), EU# 3 */
19067 + 0x20000000, /* setCrcAccum(), EU# 3 */
19068 + 0x21800000, /* and(), EU# 3 */
19069 + 0x21e00000, /* or(), EU# 3 */
19070 + 0x20400000, /* add(), EU# 3 */
19071 + 0x20500000, /* sub(), EU# 3 */
19072 + 0x205a0000, /* andNot(), EU# 3 */
19073 + 0x20a00000, /* shiftR(), EU# 3 */
19074 + 0x202fa000, /* andReadyBit(), EU# 3 */
19075 + 0x202f9000, /* andNotReadyBit(), EU# 3 */
19076 + 0x202ea000, /* andWrapBit(), EU# 3 */
19077 + 0x202da000, /* andLastBit(), EU# 3 */
19078 + 0x202e2000, /* andInterruptBit(), EU# 3 */
19079 + 0x202f2000, /* andCrcRestartBit(), EU# 3 */
19080 +};
19081 +
19082 +u32 MCD_funcDescTab5[]=
19083 +{ /* Task 5 Function Descriptor Table */
19084 + 0x00000000,
19085 + 0x00000000,
19086 + 0x00000000,
19087 + 0x00000000,
19088 + 0x00000000,
19089 + 0x00000000,
19090 + 0x00000000,
19091 + 0x00000000,
19092 + 0x00000000,
19093 + 0x00000000,
19094 + 0x00000000,
19095 + 0x00000000,
19096 + 0x00000000,
19097 + 0x00000000,
19098 + 0x00000000,
19099 + 0x00000000,
19100 + 0x00000000,
19101 + 0x00000000,
19102 + 0x00000000,
19103 + 0x00000000,
19104 + 0x00000000,
19105 + 0x00000000,
19106 + 0x00000000,
19107 + 0x00000000,
19108 + 0x00000000,
19109 + 0x00000000,
19110 + 0x00000000,
19111 + 0x00000000,
19112 + 0x00000000,
19113 + 0x00000000,
19114 + 0x00000000,
19115 + 0x00000000,
19116 + 0x00000000,
19117 + 0x00000000,
19118 + 0x00000000,
19119 + 0x00000000,
19120 + 0x00000000,
19121 + 0x00000000,
19122 + 0x00000000,
19123 + 0x00000000,
19124 + 0x00000000,
19125 + 0x00000000,
19126 + 0x00000000,
19127 + 0x00000000,
19128 + 0x00000000,
19129 + 0x00000000,
19130 + 0x00000000,
19131 + 0x00000000,
19132 + 0xa0045670, /* mainFunc(), EU# 3 */
19133 + 0xa0000000, /* rsduFunc(), EU# 3 */
19134 + 0xa0000000, /* crcAccumVal(), EU# 3 */
19135 + 0x20000000, /* setCrcAccum(), EU# 3 */
19136 + 0x21800000, /* and(), EU# 3 */
19137 + 0x21e00000, /* or(), EU# 3 */
19138 + 0x20400000, /* add(), EU# 3 */
19139 + 0x20500000, /* sub(), EU# 3 */
19140 + 0x205a0000, /* andNot(), EU# 3 */
19141 + 0x20a00000, /* shiftR(), EU# 3 */
19142 + 0x202fa000, /* andReadyBit(), EU# 3 */
19143 + 0x202f9000, /* andNotReadyBit(), EU# 3 */
19144 + 0x202ea000, /* andWrapBit(), EU# 3 */
19145 + 0x202da000, /* andLastBit(), EU# 3 */
19146 + 0x202e2000, /* andInterruptBit(), EU# 3 */
19147 + 0x202f2000, /* andCrcRestartBit(), EU# 3 */
19148 +};
19149 +
19150 +u32 MCD_funcDescTab6[]=
19151 +{ /* Task 6 Function Descriptor Table */
19152 + 0x00000000,
19153 + 0x00000000,
19154 + 0x00000000,
19155 + 0x00000000,
19156 + 0x00000000,
19157 + 0x00000000,
19158 + 0x00000000,
19159 + 0x00000000,
19160 + 0x00000000,
19161 + 0x00000000,
19162 + 0x00000000,
19163 + 0x00000000,
19164 + 0x00000000,
19165 + 0x00000000,
19166 + 0x00000000,
19167 + 0x00000000,
19168 + 0x00000000,
19169 + 0x00000000,
19170 + 0x00000000,
19171 + 0x00000000,
19172 + 0x00000000,
19173 + 0x00000000,
19174 + 0x00000000,
19175 + 0x00000000,
19176 + 0x00000000,
19177 + 0x00000000,
19178 + 0x00000000,
19179 + 0x00000000,
19180 + 0x00000000,
19181 + 0x00000000,
19182 + 0x00000000,
19183 + 0x00000000,
19184 + 0x00000000,
19185 + 0x00000000,
19186 + 0x00000000,
19187 + 0x00000000,
19188 + 0x00000000,
19189 + 0x00000000,
19190 + 0x00000000,
19191 + 0x00000000,
19192 + 0x00000000,
19193 + 0x00000000,
19194 + 0x00000000,
19195 + 0x00000000,
19196 + 0x00000000,
19197 + 0x00000000,
19198 + 0x00000000,
19199 + 0x00000000,
19200 + 0xa0045670, /* mainFunc(), EU# 3 */
19201 + 0xa0000000, /* rsduFunc(), EU# 3 */
19202 + 0xa0000000, /* crcAccumVal(), EU# 3 */
19203 + 0x20000000, /* setCrcAccum(), EU# 3 */
19204 + 0x21800000, /* and(), EU# 3 */
19205 + 0x21e00000, /* or(), EU# 3 */
19206 + 0x20400000, /* add(), EU# 3 */
19207 + 0x20500000, /* sub(), EU# 3 */
19208 + 0x205a0000, /* andNot(), EU# 3 */
19209 + 0x20a00000, /* shiftR(), EU# 3 */
19210 + 0x202fa000, /* andReadyBit(), EU# 3 */
19211 + 0x202f9000, /* andNotReadyBit(), EU# 3 */
19212 + 0x202ea000, /* andWrapBit(), EU# 3 */
19213 + 0x202da000, /* andLastBit(), EU# 3 */
19214 + 0x202e2000, /* andInterruptBit(), EU# 3 */
19215 + 0x202f2000, /* andCrcRestartBit(), EU# 3 */
19216 +};
19217 +
19218 +u32 MCD_funcDescTab7[]=
19219 +{ /* Task 7 Function Descriptor Table */
19220 + 0x00000000,
19221 + 0x00000000,
19222 + 0x00000000,
19223 + 0x00000000,
19224 + 0x00000000,
19225 + 0x00000000,
19226 + 0x00000000,
19227 + 0x00000000,
19228 + 0x00000000,
19229 + 0x00000000,
19230 + 0x00000000,
19231 + 0x00000000,
19232 + 0x00000000,
19233 + 0x00000000,
19234 + 0x00000000,
19235 + 0x00000000,
19236 + 0x00000000,
19237 + 0x00000000,
19238 + 0x00000000,
19239 + 0x00000000,
19240 + 0x00000000,
19241 + 0x00000000,
19242 + 0x00000000,
19243 + 0x00000000,
19244 + 0x00000000,
19245 + 0x00000000,
19246 + 0x00000000,
19247 + 0x00000000,
19248 + 0x00000000,
19249 + 0x00000000,
19250 + 0x00000000,
19251 + 0x00000000,
19252 + 0x00000000,
19253 + 0x00000000,
19254 + 0x00000000,
19255 + 0x00000000,
19256 + 0x00000000,
19257 + 0x00000000,
19258 + 0x00000000,
19259 + 0x00000000,
19260 + 0x00000000,
19261 + 0x00000000,
19262 + 0x00000000,
19263 + 0x00000000,
19264 + 0x00000000,
19265 + 0x00000000,
19266 + 0x00000000,
19267 + 0x00000000,
19268 + 0xa0045670, /* mainFunc(), EU# 3 */
19269 + 0xa0000000, /* rsduFunc(), EU# 3 */
19270 + 0xa0000000, /* crcAccumVal(), EU# 3 */
19271 + 0x20000000, /* setCrcAccum(), EU# 3 */
19272 + 0x21800000, /* and(), EU# 3 */
19273 + 0x21e00000, /* or(), EU# 3 */
19274 + 0x20400000, /* add(), EU# 3 */
19275 + 0x20500000, /* sub(), EU# 3 */
19276 + 0x205a0000, /* andNot(), EU# 3 */
19277 + 0x20a00000, /* shiftR(), EU# 3 */
19278 + 0x202fa000, /* andReadyBit(), EU# 3 */
19279 + 0x202f9000, /* andNotReadyBit(), EU# 3 */
19280 + 0x202ea000, /* andWrapBit(), EU# 3 */
19281 + 0x202da000, /* andLastBit(), EU# 3 */
19282 + 0x202e2000, /* andInterruptBit(), EU# 3 */
19283 + 0x202f2000, /* andCrcRestartBit(), EU# 3 */
19284 +};
19285 +
19286 +u32 MCD_funcDescTab8[]=
19287 +{ /* Task 8 Function Descriptor Table */
19288 + 0x00000000,
19289 + 0x00000000,
19290 + 0x00000000,
19291 + 0x00000000,
19292 + 0x00000000,
19293 + 0x00000000,
19294 + 0x00000000,
19295 + 0x00000000,
19296 + 0x00000000,
19297 + 0x00000000,
19298 + 0x00000000,
19299 + 0x00000000,
19300 + 0x00000000,
19301 + 0x00000000,
19302 + 0x00000000,
19303 + 0x00000000,
19304 + 0x00000000,
19305 + 0x00000000,
19306 + 0x00000000,
19307 + 0x00000000,
19308 + 0x00000000,
19309 + 0x00000000,
19310 + 0x00000000,
19311 + 0x00000000,
19312 + 0x00000000,
19313 + 0x00000000,
19314 + 0x00000000,
19315 + 0x00000000,
19316 + 0x00000000,
19317 + 0x00000000,
19318 + 0x00000000,
19319 + 0x00000000,
19320 + 0x00000000,
19321 + 0x00000000,
19322 + 0x00000000,
19323 + 0x00000000,
19324 + 0x00000000,
19325 + 0x00000000,
19326 + 0x00000000,
19327 + 0x00000000,
19328 + 0x00000000,
19329 + 0x00000000,
19330 + 0x00000000,
19331 + 0x00000000,
19332 + 0x00000000,
19333 + 0x00000000,
19334 + 0x00000000,
19335 + 0x00000000,
19336 + 0xa0045670, /* mainFunc(), EU# 3 */
19337 + 0xa0000000, /* rsduFunc(), EU# 3 */
19338 + 0xa0000000, /* crcAccumVal(), EU# 3 */
19339 + 0x20000000, /* setCrcAccum(), EU# 3 */
19340 + 0x21800000, /* and(), EU# 3 */
19341 + 0x21e00000, /* or(), EU# 3 */
19342 + 0x20400000, /* add(), EU# 3 */
19343 + 0x20500000, /* sub(), EU# 3 */
19344 + 0x205a0000, /* andNot(), EU# 3 */
19345 + 0x20a00000, /* shiftR(), EU# 3 */
19346 + 0x202fa000, /* andReadyBit(), EU# 3 */
19347 + 0x202f9000, /* andNotReadyBit(), EU# 3 */
19348 + 0x202ea000, /* andWrapBit(), EU# 3 */
19349 + 0x202da000, /* andLastBit(), EU# 3 */
19350 + 0x202e2000, /* andInterruptBit(), EU# 3 */
19351 + 0x202f2000, /* andCrcRestartBit(), EU# 3 */
19352 +};
19353 +
19354 +u32 MCD_funcDescTab9[]=
19355 +{ /* Task 9 Function Descriptor Table */
19356 + 0x00000000,
19357 + 0x00000000,
19358 + 0x00000000,
19359 + 0x00000000,
19360 + 0x00000000,
19361 + 0x00000000,
19362 + 0x00000000,
19363 + 0x00000000,
19364 + 0x00000000,
19365 + 0x00000000,
19366 + 0x00000000,
19367 + 0x00000000,
19368 + 0x00000000,
19369 + 0x00000000,
19370 + 0x00000000,
19371 + 0x00000000,
19372 + 0x00000000,
19373 + 0x00000000,
19374 + 0x00000000,
19375 + 0x00000000,
19376 + 0x00000000,
19377 + 0x00000000,
19378 + 0x00000000,
19379 + 0x00000000,
19380 + 0x00000000,
19381 + 0x00000000,
19382 + 0x00000000,
19383 + 0x00000000,
19384 + 0x00000000,
19385 + 0x00000000,
19386 + 0x00000000,
19387 + 0x00000000,
19388 + 0x00000000,
19389 + 0x00000000,
19390 + 0x00000000,
19391 + 0x00000000,
19392 + 0x00000000,
19393 + 0x00000000,
19394 + 0x00000000,
19395 + 0x00000000,
19396 + 0x00000000,
19397 + 0x00000000,
19398 + 0x00000000,
19399 + 0x00000000,
19400 + 0x00000000,
19401 + 0x00000000,
19402 + 0x00000000,
19403 + 0x00000000,
19404 + 0xa0045670, /* mainFunc(), EU# 3 */
19405 + 0xa0000000, /* rsduFunc(), EU# 3 */
19406 + 0xa0000000, /* crcAccumVal(), EU# 3 */
19407 + 0x20000000, /* setCrcAccum(), EU# 3 */
19408 + 0x21800000, /* and(), EU# 3 */
19409 + 0x21e00000, /* or(), EU# 3 */
19410 + 0x20400000, /* add(), EU# 3 */
19411 + 0x20500000, /* sub(), EU# 3 */
19412 + 0x205a0000, /* andNot(), EU# 3 */
19413 + 0x20a00000, /* shiftR(), EU# 3 */
19414 + 0x202fa000, /* andReadyBit(), EU# 3 */
19415 + 0x202f9000, /* andNotReadyBit(), EU# 3 */
19416 + 0x202ea000, /* andWrapBit(), EU# 3 */
19417 + 0x202da000, /* andLastBit(), EU# 3 */
19418 + 0x202e2000, /* andInterruptBit(), EU# 3 */
19419 + 0x202f2000, /* andCrcRestartBit(), EU# 3 */
19420 +};
19421 +
19422 +u32 MCD_funcDescTab10[]=
19423 +{ /* Task 10 Function Descriptor Table */
19424 + 0x00000000,
19425 + 0x00000000,
19426 + 0x00000000,
19427 + 0x00000000,
19428 + 0x00000000,
19429 + 0x00000000,
19430 + 0x00000000,
19431 + 0x00000000,
19432 + 0x00000000,
19433 + 0x00000000,
19434 + 0x00000000,
19435 + 0x00000000,
19436 + 0x00000000,
19437 + 0x00000000,
19438 + 0x00000000,
19439 + 0x00000000,
19440 + 0x00000000,
19441 + 0x00000000,
19442 + 0x00000000,
19443 + 0x00000000,
19444 + 0x00000000,
19445 + 0x00000000,
19446 + 0x00000000,
19447 + 0x00000000,
19448 + 0x00000000,
19449 + 0x00000000,
19450 + 0x00000000,
19451 + 0x00000000,
19452 + 0x00000000,
19453 + 0x00000000,
19454 + 0x00000000,
19455 + 0x00000000,
19456 + 0x00000000,
19457 + 0x00000000,
19458 + 0x00000000,
19459 + 0x00000000,
19460 + 0x00000000,
19461 + 0x00000000,
19462 + 0x00000000,
19463 + 0x00000000,
19464 + 0x00000000,
19465 + 0x00000000,
19466 + 0x00000000,
19467 + 0x00000000,
19468 + 0x00000000,
19469 + 0x00000000,
19470 + 0x00000000,
19471 + 0x00000000,
19472 + 0xa0045670, /* mainFunc(), EU# 3 */
19473 + 0xa0000000, /* rsduFunc(), EU# 3 */
19474 + 0xa0000000, /* crcAccumVal(), EU# 3 */
19475 + 0x20000000, /* setCrcAccum(), EU# 3 */
19476 + 0x21800000, /* and(), EU# 3 */
19477 + 0x21e00000, /* or(), EU# 3 */
19478 + 0x20400000, /* add(), EU# 3 */
19479 + 0x20500000, /* sub(), EU# 3 */
19480 + 0x205a0000, /* andNot(), EU# 3 */
19481 + 0x20a00000, /* shiftR(), EU# 3 */
19482 + 0x202fa000, /* andReadyBit(), EU# 3 */
19483 + 0x202f9000, /* andNotReadyBit(), EU# 3 */
19484 + 0x202ea000, /* andWrapBit(), EU# 3 */
19485 + 0x202da000, /* andLastBit(), EU# 3 */
19486 + 0x202e2000, /* andInterruptBit(), EU# 3 */
19487 + 0x202f2000, /* andCrcRestartBit(), EU# 3 */
19488 +};
19489 +
19490 +u32 MCD_funcDescTab11[]=
19491 +{ /* Task 11 Function Descriptor Table */
19492 + 0x00000000,
19493 + 0x00000000,
19494 + 0x00000000,
19495 + 0x00000000,
19496 + 0x00000000,
19497 + 0x00000000,
19498 + 0x00000000,
19499 + 0x00000000,
19500 + 0x00000000,
19501 + 0x00000000,
19502 + 0x00000000,
19503 + 0x00000000,
19504 + 0x00000000,
19505 + 0x00000000,
19506 + 0x00000000,
19507 + 0x00000000,
19508 + 0x00000000,
19509 + 0x00000000,
19510 + 0x00000000,
19511 + 0x00000000,
19512 + 0x00000000,
19513 + 0x00000000,
19514 + 0x00000000,
19515 + 0x00000000,
19516 + 0x00000000,
19517 + 0x00000000,
19518 + 0x00000000,
19519 + 0x00000000,
19520 + 0x00000000,
19521 + 0x00000000,
19522 + 0x00000000,
19523 + 0x00000000,
19524 + 0x00000000,
19525 + 0x00000000,
19526 + 0x00000000,
19527 + 0x00000000,
19528 + 0x00000000,
19529 + 0x00000000,
19530 + 0x00000000,
19531 + 0x00000000,
19532 + 0x00000000,
19533 + 0x00000000,
19534 + 0x00000000,
19535 + 0x00000000,
19536 + 0x00000000,
19537 + 0x00000000,
19538 + 0x00000000,
19539 + 0x00000000,
19540 + 0xa0045670, /* mainFunc(), EU# 3 */
19541 + 0xa0000000, /* rsduFunc(), EU# 3 */
19542 + 0xa0000000, /* crcAccumVal(), EU# 3 */
19543 + 0x20000000, /* setCrcAccum(), EU# 3 */
19544 + 0x21800000, /* and(), EU# 3 */
19545 + 0x21e00000, /* or(), EU# 3 */
19546 + 0x20400000, /* add(), EU# 3 */
19547 + 0x20500000, /* sub(), EU# 3 */
19548 + 0x205a0000, /* andNot(), EU# 3 */
19549 + 0x20a00000, /* shiftR(), EU# 3 */
19550 + 0x202fa000, /* andReadyBit(), EU# 3 */
19551 + 0x202f9000, /* andNotReadyBit(), EU# 3 */
19552 + 0x202ea000, /* andWrapBit(), EU# 3 */
19553 + 0x202da000, /* andLastBit(), EU# 3 */
19554 + 0x202e2000, /* andInterruptBit(), EU# 3 */
19555 + 0x202f2000, /* andCrcRestartBit(), EU# 3 */
19556 +};
19557 +
19558 +u32 MCD_funcDescTab12[]=
19559 +{ /* Task 12 Function Descriptor Table */
19560 + 0x00000000,
19561 + 0x00000000,
19562 + 0x00000000,
19563 + 0x00000000,
19564 + 0x00000000,
19565 + 0x00000000,
19566 + 0x00000000,
19567 + 0x00000000,
19568 + 0x00000000,
19569 + 0x00000000,
19570 + 0x00000000,
19571 + 0x00000000,
19572 + 0x00000000,
19573 + 0x00000000,
19574 + 0x00000000,
19575 + 0x00000000,
19576 + 0x00000000,
19577 + 0x00000000,
19578 + 0x00000000,
19579 + 0x00000000,
19580 + 0x00000000,
19581 + 0x00000000,
19582 + 0x00000000,
19583 + 0x00000000,
19584 + 0x00000000,
19585 + 0x00000000,
19586 + 0x00000000,
19587 + 0x00000000,
19588 + 0x00000000,
19589 + 0x00000000,
19590 + 0x00000000,
19591 + 0x00000000,
19592 + 0x00000000,
19593 + 0x00000000,
19594 + 0x00000000,
19595 + 0x00000000,
19596 + 0x00000000,
19597 + 0x00000000,
19598 + 0x00000000,
19599 + 0x00000000,
19600 + 0x00000000,
19601 + 0x00000000,
19602 + 0x00000000,
19603 + 0x00000000,
19604 + 0x00000000,
19605 + 0x00000000,
19606 + 0x00000000,
19607 + 0x00000000,
19608 + 0xa0045670, /* mainFunc(), EU# 3 */
19609 + 0xa0000000, /* rsduFunc(), EU# 3 */
19610 + 0xa0000000, /* crcAccumVal(), EU# 3 */
19611 + 0x20000000, /* setCrcAccum(), EU# 3 */
19612 + 0x21800000, /* and(), EU# 3 */
19613 + 0x21e00000, /* or(), EU# 3 */
19614 + 0x20400000, /* add(), EU# 3 */
19615 + 0x20500000, /* sub(), EU# 3 */
19616 + 0x205a0000, /* andNot(), EU# 3 */
19617 + 0x20a00000, /* shiftR(), EU# 3 */
19618 + 0x202fa000, /* andReadyBit(), EU# 3 */
19619 + 0x202f9000, /* andNotReadyBit(), EU# 3 */
19620 + 0x202ea000, /* andWrapBit(), EU# 3 */
19621 + 0x202da000, /* andLastBit(), EU# 3 */
19622 + 0x202e2000, /* andInterruptBit(), EU# 3 */
19623 + 0x202f2000, /* andCrcRestartBit(), EU# 3 */
19624 +};
19625 +
19626 +u32 MCD_funcDescTab13[]=
19627 +{ /* Task 13 Function Descriptor Table */
19628 + 0x00000000,
19629 + 0x00000000,
19630 + 0x00000000,
19631 + 0x00000000,
19632 + 0x00000000,
19633 + 0x00000000,
19634 + 0x00000000,
19635 + 0x00000000,
19636 + 0x00000000,
19637 + 0x00000000,
19638 + 0x00000000,
19639 + 0x00000000,
19640 + 0x00000000,
19641 + 0x00000000,
19642 + 0x00000000,
19643 + 0x00000000,
19644 + 0x00000000,
19645 + 0x00000000,
19646 + 0x00000000,
19647 + 0x00000000,
19648 + 0x00000000,
19649 + 0x00000000,
19650 + 0x00000000,
19651 + 0x00000000,
19652 + 0x00000000,
19653 + 0x00000000,
19654 + 0x00000000,
19655 + 0x00000000,
19656 + 0x00000000,
19657 + 0x00000000,
19658 + 0x00000000,
19659 + 0x00000000,
19660 + 0x00000000,
19661 + 0x00000000,
19662 + 0x00000000,
19663 + 0x00000000,
19664 + 0x00000000,
19665 + 0x00000000,
19666 + 0x00000000,
19667 + 0x00000000,
19668 + 0x00000000,
19669 + 0x00000000,
19670 + 0x00000000,
19671 + 0x00000000,
19672 + 0x00000000,
19673 + 0x00000000,
19674 + 0x00000000,
19675 + 0x00000000,
19676 + 0xa0045670, /* mainFunc(), EU# 3 */
19677 + 0xa0000000, /* rsduFunc(), EU# 3 */
19678 + 0xa0000000, /* crcAccumVal(), EU# 3 */
19679 + 0x20000000, /* setCrcAccum(), EU# 3 */
19680 + 0x21800000, /* and(), EU# 3 */
19681 + 0x21e00000, /* or(), EU# 3 */
19682 + 0x20400000, /* add(), EU# 3 */
19683 + 0x20500000, /* sub(), EU# 3 */
19684 + 0x205a0000, /* andNot(), EU# 3 */
19685 + 0x20a00000, /* shiftR(), EU# 3 */
19686 + 0x202fa000, /* andReadyBit(), EU# 3 */
19687 + 0x202f9000, /* andNotReadyBit(), EU# 3 */
19688 + 0x202ea000, /* andWrapBit(), EU# 3 */
19689 + 0x202da000, /* andLastBit(), EU# 3 */
19690 + 0x202e2000, /* andInterruptBit(), EU# 3 */
19691 + 0x202f2000, /* andCrcRestartBit(), EU# 3 */
19692 +};
19693 +
19694 +u32 MCD_funcDescTab14[]=
19695 +{ /* Task 14 Function Descriptor Table */
19696 + 0x00000000,
19697 + 0x00000000,
19698 + 0x00000000,
19699 + 0x00000000,
19700 + 0x00000000,
19701 + 0x00000000,
19702 + 0x00000000,
19703 + 0x00000000,
19704 + 0x00000000,
19705 + 0x00000000,
19706 + 0x00000000,
19707 + 0x00000000,
19708 + 0x00000000,
19709 + 0x00000000,
19710 + 0x00000000,
19711 + 0x00000000,
19712 + 0x00000000,
19713 + 0x00000000,
19714 + 0x00000000,
19715 + 0x00000000,
19716 + 0x00000000,
19717 + 0x00000000,
19718 + 0x00000000,
19719 + 0x00000000,
19720 + 0x00000000,
19721 + 0x00000000,
19722 + 0x00000000,
19723 + 0x00000000,
19724 + 0x00000000,
19725 + 0x00000000,
19726 + 0x00000000,
19727 + 0x00000000,
19728 + 0x00000000,
19729 + 0x00000000,
19730 + 0x00000000,
19731 + 0x00000000,
19732 + 0x00000000,
19733 + 0x00000000,
19734 + 0x00000000,
19735 + 0x00000000,
19736 + 0x00000000,
19737 + 0x00000000,
19738 + 0x00000000,
19739 + 0x00000000,
19740 + 0x00000000,
19741 + 0x00000000,
19742 + 0x00000000,
19743 + 0x00000000,
19744 + 0xa0045670, /* mainFunc(), EU# 3 */
19745 + 0xa0000000, /* rsduFunc(), EU# 3 */
19746 + 0xa0000000, /* crcAccumVal(), EU# 3 */
19747 + 0x20000000, /* setCrcAccum(), EU# 3 */
19748 + 0x21800000, /* and(), EU# 3 */
19749 + 0x21e00000, /* or(), EU# 3 */
19750 + 0x20400000, /* add(), EU# 3 */
19751 + 0x20500000, /* sub(), EU# 3 */
19752 + 0x205a0000, /* andNot(), EU# 3 */
19753 + 0x20a00000, /* shiftR(), EU# 3 */
19754 + 0x202fa000, /* andReadyBit(), EU# 3 */
19755 + 0x202f9000, /* andNotReadyBit(), EU# 3 */
19756 + 0x202ea000, /* andWrapBit(), EU# 3 */
19757 + 0x202da000, /* andLastBit(), EU# 3 */
19758 + 0x202e2000, /* andInterruptBit(), EU# 3 */
19759 + 0x202f2000, /* andCrcRestartBit(), EU# 3 */
19760 +};
19761 +
19762 +u32 MCD_funcDescTab15[]=
19763 +{ /* Task 15 Function Descriptor Table */
19764 + 0x00000000,
19765 + 0x00000000,
19766 + 0x00000000,
19767 + 0x00000000,
19768 + 0x00000000,
19769 + 0x00000000,
19770 + 0x00000000,
19771 + 0x00000000,
19772 + 0x00000000,
19773 + 0x00000000,
19774 + 0x00000000,
19775 + 0x00000000,
19776 + 0x00000000,
19777 + 0x00000000,
19778 + 0x00000000,
19779 + 0x00000000,
19780 + 0x00000000,
19781 + 0x00000000,
19782 + 0x00000000,
19783 + 0x00000000,
19784 + 0x00000000,
19785 + 0x00000000,
19786 + 0x00000000,
19787 + 0x00000000,
19788 + 0x00000000,
19789 + 0x00000000,
19790 + 0x00000000,
19791 + 0x00000000,
19792 + 0x00000000,
19793 + 0x00000000,
19794 + 0x00000000,
19795 + 0x00000000,
19796 + 0x00000000,
19797 + 0x00000000,
19798 + 0x00000000,
19799 + 0x00000000,
19800 + 0x00000000,
19801 + 0x00000000,
19802 + 0x00000000,
19803 + 0x00000000,
19804 + 0x00000000,
19805 + 0x00000000,
19806 + 0x00000000,
19807 + 0x00000000,
19808 + 0x00000000,
19809 + 0x00000000,
19810 + 0x00000000,
19811 + 0x00000000,
19812 + 0xa0045670, /* mainFunc(), EU# 3 */
19813 + 0xa0000000, /* rsduFunc(), EU# 3 */
19814 + 0xa0000000, /* crcAccumVal(), EU# 3 */
19815 + 0x20000000, /* setCrcAccum(), EU# 3 */
19816 + 0x21800000, /* and(), EU# 3 */
19817 + 0x21e00000, /* or(), EU# 3 */
19818 + 0x20400000, /* add(), EU# 3 */
19819 + 0x20500000, /* sub(), EU# 3 */
19820 + 0x205a0000, /* andNot(), EU# 3 */
19821 + 0x20a00000, /* shiftR(), EU# 3 */
19822 + 0x202fa000, /* andReadyBit(), EU# 3 */
19823 + 0x202f9000, /* andNotReadyBit(), EU# 3 */
19824 + 0x202ea000, /* andWrapBit(), EU# 3 */
19825 + 0x202da000, /* andLastBit(), EU# 3 */
19826 + 0x202e2000, /* andInterruptBit(), EU# 3 */
19827 + 0x202f2000, /* andCrcRestartBit(), EU# 3 */
19828 +};
19829 +#endif /*MCD_INCLUDE_EU*/
19830 +
19831 +u32 MCD_contextSave0[128]; /* Task 0 context save space */
19832 +u32 MCD_contextSave1[128]; /* Task 1 context save space */
19833 +u32 MCD_contextSave2[128]; /* Task 2 context save space */
19834 +u32 MCD_contextSave3[128]; /* Task 3 context save space */
19835 +u32 MCD_contextSave4[128]; /* Task 4 context save space */
19836 +u32 MCD_contextSave5[128]; /* Task 5 context save space */
19837 +u32 MCD_contextSave6[128]; /* Task 6 context save space */
19838 +u32 MCD_contextSave7[128]; /* Task 7 context save space */
19839 +u32 MCD_contextSave8[128]; /* Task 8 context save space */
19840 +u32 MCD_contextSave9[128]; /* Task 9 context save space */
19841 +u32 MCD_contextSave10[128]; /* Task 10 context save space */
19842 +u32 MCD_contextSave11[128]; /* Task 11 context save space */
19843 +u32 MCD_contextSave12[128]; /* Task 12 context save space */
19844 +u32 MCD_contextSave13[128]; /* Task 13 context save space */
19845 +u32 MCD_contextSave14[128]; /* Task 14 context save space */
19846 +u32 MCD_contextSave15[128]; /* Task 15 context save space */
19847 +
19848 +u32 MCD_ChainNoEu_TDT[];
19849 +u32 MCD_SingleNoEu_TDT[];
19850 +#ifdef MCD_INCLUDE_EU
19851 +u32 MCD_ChainEu_TDT[];
19852 +u32 MCD_SingleEu_TDT[];
19853 +#endif
19854 +u32 MCD_ENetRcv_TDT[];
19855 +u32 MCD_ENetXmit_TDT[];
19856 +
19857 +u32 MCD_modelTaskTableSrc[]=
19858 +{
19859 + (u32)MCD_ChainNoEu_TDT,
19860 + (u32)&((u8*)MCD_ChainNoEu_TDT)[0x0000016c],
19861 + 0x00000000,
19862 + 0x00000000,
19863 + 0x00000000,
19864 + 0x00000000,
19865 + 0x00000000,
19866 + 0x00000000,
19867 + (u32)MCD_SingleNoEu_TDT,
19868 + (u32)&((u8*)MCD_SingleNoEu_TDT)[0x000000d4],
19869 + 0x00000000,
19870 + 0x00000000,
19871 + 0x00000000,
19872 + 0x00000000,
19873 + 0x00000000,
19874 + 0x00000000,
19875 +#ifdef MCD_INCLUDE_EU
19876 + (u32)MCD_ChainEu_TDT,
19877 + (u32)&((u8*)MCD_ChainEu_TDT)[0x000001b4],
19878 + 0x00000000,
19879 + 0x00000000,
19880 + 0x00000000,
19881 + 0x00000000,
19882 + 0x00000000,
19883 + 0x00000000,
19884 + (u32)MCD_SingleEu_TDT,
19885 + (u32)&((u8*)MCD_SingleEu_TDT)[0x00000124],
19886 + 0x00000000,
19887 + 0x00000000,
19888 + 0x00000000,
19889 + 0x00000000,
19890 + 0x00000000,
19891 + 0x00000000,
19892 +#endif
19893 + (u32)MCD_ENetRcv_TDT,
19894 + (u32)&((u8*)MCD_ENetRcv_TDT)[0x000000a4],
19895 + 0x00000000,
19896 + 0x00000000,
19897 + 0x00000000,
19898 + 0x00000000,
19899 + 0x00000000,
19900 + 0x00000000,
19901 + (u32)MCD_ENetXmit_TDT,
19902 + (u32)&((u8*)MCD_ENetXmit_TDT)[0x000000d0],
19903 + 0x00000000,
19904 + 0x00000000,
19905 + 0x00000000,
19906 + 0x00000000,
19907 + 0x00000000,
19908 + 0x00000000,
19909 +};
19910 +u32 MCD_ChainNoEu_TDT[]=
19911 +{
19912 + 0x80004000, /* 0000(:370): LCDEXT: idx0 = 0x00000000; ; */
19913 + 0x8118801b, /* 0004(:370): LCD: idx1 = var2; idx1 once var0; idx1 += inc3 */
19914 + 0xb8c60018, /* 0008(:371): LCD: idx2 = *(idx1 + var12); idx2 once var0; idx2 += inc3 */
19915 + 0x10002b10, /* 000C(:372): DRD1A: var10 = idx2; FN=0 MORE init=0 WS=0 RS=0 */
19916 + 0x7000000d, /* 0010(:373): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */
19917 + 0x018cf89f, /* 0014(:373): DRD2B1: var6 = EU3(); EU3(idx2) */
19918 + 0x6000000a, /* 0018(:374): DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT init=0 WS=0 RS=0 */
19919 + 0x080cf89f, /* 001C(:374): DRD2B1: idx0 = EU3(); EU3(idx2) */
19920 + 0x000001f8, /* 0020(:0): NOP */
19921 + 0x98180364, /* 0024(:378): LCD: idx0 = idx0; idx0 == var13; idx0 += inc4 */
19922 + 0x8118801b, /* 0028(:380): LCD: idx1 = var2; idx1 once var0; idx1 += inc3 */
19923 + 0xf8c6001a, /* 002C(:381): LCDEXT: idx2 = *(idx1 + var12 + 8); idx2 once var0; idx2 += inc3 */
19924 + 0xb8c6601b, /* 0030(:382): LCD: idx3 = *(idx1 + var12 + 12); ; idx3 += inc3 */
19925 + 0x10002710, /* 0034(:384): DRD1A: var9 = idx2; FN=0 MORE init=0 WS=0 RS=0 */
19926 + 0x00000f18, /* 0038(:385): DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */
19927 + 0xb8c6001d, /* 003C(:387): LCD: idx2 = *(idx1 + var12 + 20); idx2 once var0; idx2 += inc3 */
19928 + 0x10001310, /* 0040(:388): DRD1A: var4 = idx2; FN=0 MORE init=0 WS=0 RS=0 */
19929 + 0x60000007, /* 0044(:389): DRD2A: EU0=0 EU1=0 EU2=0 EU3=7 EXT init=0 WS=0 RS=0 */
19930 + 0x014cf88b, /* 0048(:389): DRD2B1: var5 = EU3(); EU3(idx2,var11) */
19931 + 0x98c6001c, /* 004C(:391): LCD: idx2 = idx1 + var12 + 4; idx2 once var0; idx2 += inc3 */
19932 + 0x00000710, /* 0050(:392): DRD1A: var1 = idx2; FN=0 init=0 WS=0 RS=0 */
19933 + 0x98c70018, /* 0054(:393): LCD: idx2 = idx1 + var14; idx2 once var0; idx2 += inc3 */
19934 + 0x10001f10, /* 0058(:394): DRD1A: var7 = idx2; FN=0 MORE init=0 WS=0 RS=0 */
19935 + 0x0000c818, /* 005C(:395): DRD1A: *idx2 = var3; FN=0 init=0 WS=0 RS=0 */
19936 + 0x000001f8, /* 0060(:0): NOP */
19937 + 0xc1476018, /* 0064(:399): LCDEXT: idx1 = var2 + var14; ; idx1 += inc3 */
19938 + 0xc003231d, /* 0068(:399): LCDEXT: idx2 = var0, idx3 = var6; idx3 == var12; idx2 += inc3, idx3 += inc5 */
19939 + 0x811a601b, /* 006C(:400): LCD: idx4 = var2; ; idx4 += inc3 */
19940 + 0xc1862102, /* 0070(:403): LCDEXT: idx5 = var3, idx6 = var12; idx6 < var4; idx5 += inc0, idx6 += inc2 */
19941 + 0x849be009, /* 0074(:403): LCD: idx7 = var9; ; idx7 += inc1 */
19942 + 0x03fed7b8, /* 0078(:406): DRD1A: *idx7; FN=0 init=31 WS=3 RS=3 */
19943 + 0xda9b001b, /* 007C(:408): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */
19944 + 0x9b9be01b, /* 0080(:408): LCD: idx7 = idx7; ; idx7 += inc3 */
19945 + 0x1000cb20, /* 0084(:409): DRD1A: *idx2 = idx4; FN=0 MORE init=0 WS=0 RS=0 */
19946 + 0x70000006, /* 0088(:410): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
19947 + 0x088cf88f, /* 008C(:410): DRD2B1: idx2 = EU3(); EU3(idx2,var15) */
19948 + 0x1000cb28, /* 0090(:411): DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */
19949 + 0x70000006, /* 0094(:412): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
19950 + 0x088cf88f, /* 0098(:412): DRD2B1: idx2 = EU3(); EU3(idx2,var15) */
19951 + 0x1000cb30, /* 009C(:413): DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */
19952 + 0x70000006, /* 00A0(:414): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
19953 + 0x088cf88f, /* 00A4(:414): DRD2B1: idx2 = EU3(); EU3(idx2,var15) */
19954 + 0x1000cb38, /* 00A8(:415): DRD1A: *idx2 = idx7; FN=0 MORE init=0 WS=0 RS=0 */
19955 + 0x0000c728, /* 00AC(:416): DRD1A: *idx1 = idx5; FN=0 init=0 WS=0 RS=0 */
19956 + 0x000001f8, /* 00B0(:0): NOP */
19957 + 0xc1476018, /* 00B4(:420): LCDEXT: idx1 = var2 + var14; ; idx1 += inc3 */
19958 + 0xc003241d, /* 00B8(:420): LCDEXT: idx2 = var0, idx3 = var6; idx3 == var16; idx2 += inc3, idx3 += inc5 */
19959 + 0x811a601b, /* 00BC(:421): LCD: idx4 = var2; ; idx4 += inc3 */
19960 + 0xda9b001b, /* 00C0(:424): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */
19961 + 0x9b9be01b, /* 00C4(:424): LCD: idx7 = idx7; ; idx7 += inc3 */
19962 + 0x0000d3a0, /* 00C8(:425): DRD1A: *idx4; FN=0 init=0 WS=0 RS=0 */
19963 + 0xc1862102, /* 00CC(:427): LCDEXT: idx5 = var3, idx6 = var12; idx6 < var4; idx5 += inc0, idx6 += inc2 */
19964 + 0x849be009, /* 00D0(:427): LCD: idx7 = var9; ; idx7 += inc1 */
19965 + 0x0bfed7b8, /* 00D4(:430): DRD1A: *idx7; FN=0 TFD init=31 WS=3 RS=3 */
19966 + 0xda9b001b, /* 00D8(:432): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */
19967 + 0x9b9be01b, /* 00DC(:432): LCD: idx7 = idx7; ; idx7 += inc3 */
19968 + 0x1000cb20, /* 00E0(:433): DRD1A: *idx2 = idx4; FN=0 MORE init=0 WS=0 RS=0 */
19969 + 0x70000006, /* 00E4(:434): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
19970 + 0x088cf88f, /* 00E8(:434): DRD2B1: idx2 = EU3(); EU3(idx2,var15) */
19971 + 0x1000cb28, /* 00EC(:435): DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */
19972 + 0x70000006, /* 00F0(:436): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
19973 + 0x088cf88f, /* 00F4(:436): DRD2B1: idx2 = EU3(); EU3(idx2,var15) */
19974 + 0x1000cb30, /* 00F8(:437): DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */
19975 + 0x70000006, /* 00FC(:438): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
19976 + 0x088cf88f, /* 0100(:438): DRD2B1: idx2 = EU3(); EU3(idx2,var15) */
19977 + 0x1000cb38, /* 0104(:439): DRD1A: *idx2 = idx7; FN=0 MORE init=0 WS=0 RS=0 */
19978 + 0x0000c728, /* 0108(:440): DRD1A: *idx1 = idx5; FN=0 init=0 WS=0 RS=0 */
19979 + 0x000001f8, /* 010C(:0): NOP */
19980 + 0x8118801b, /* 0110(:444): LCD: idx1 = var2; idx1 once var0; idx1 += inc3 */
19981 + 0xd8c60018, /* 0114(:446): LCDEXT: idx2 = idx1 + var12; idx2 once var0; idx2 += inc3 */
19982 + 0x98c6601c, /* 0118(:446): LCD: idx3 = idx1 + var12 + 4; ; idx3 += inc3 */
19983 + 0x6000000b, /* 011C(:447): DRD2A: EU0=0 EU1=0 EU2=0 EU3=11 EXT init=0 WS=0 RS=0 */
19984 + 0x0c8cfc9f, /* 0120(:447): DRD2B1: *idx2 = EU3(); EU3(*idx2) */
19985 + 0x000001f8, /* 0124(:0): NOP */
19986 + 0xa146001e, /* 0128(:450): LCD: idx1 = *(var2 + var12 + 24); idx1 once var0; idx1 += inc3 */
19987 + 0x10000b08, /* 012C(:451): DRD1A: var2 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
19988 + 0x10002050, /* 0130(:452): DRD1A: var8 = var10; FN=0 MORE init=0 WS=0 RS=0 */
19989 + 0xb8c60018, /* 0134(:453): LCD: idx2 = *(idx1 + var12); idx2 once var0; idx2 += inc3 */
19990 + 0x10002b10, /* 0138(:454): DRD1A: var10 = idx2; FN=0 MORE init=0 WS=0 RS=0 */
19991 + 0x7000000a, /* 013C(:455): DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT MORE init=0 WS=0 RS=0 */
19992 + 0x080cf89f, /* 0140(:455): DRD2B1: idx0 = EU3(); EU3(idx2) */
19993 + 0x6000000d, /* 0144(:456): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT init=0 WS=0 RS=0 */
19994 + 0x018cf89f, /* 0148(:456): DRD2B1: var6 = EU3(); EU3(idx2) */
19995 + 0x000001f8, /* 014C(:0): NOP */
19996 + 0x8618801b, /* 0150(:462): LCD: idx1 = var12; idx1 once var0; idx1 += inc3 */
19997 + 0x7000000e, /* 0154(:463): DRD2A: EU0=0 EU1=0 EU2=0 EU3=14 EXT MORE init=0 WS=0 RS=0 */
19998 + 0x084cf21f, /* 0158(:463): DRD2B1: idx1 = EU3(); EU3(var8) */
19999 + 0xd8990336, /* 015C(:464): LCDEXT: idx2 = idx1; idx2 > var12; idx2 += inc6 */
20000 + 0x8019801b, /* 0160(:464): LCD: idx3 = var0; idx3 once var0; idx3 += inc3 */
20001 + 0x040001f8, /* 0164(:465): DRD1A: FN=0 INT init=0 WS=0 RS=0 */
20002 + 0x000001f8, /* 0168(:0): NOP */
20003 + 0x000001f8, /* 016C(:0): NOP */
20004 +};
20005 +u32 MCD_SingleNoEu_TDT[]=
20006 +{
20007 + 0x8198001b, /* 0000(:657): LCD: idx0 = var3; idx0 once var0; idx0 += inc3 */
20008 + 0x7000000d, /* 0004(:658): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */
20009 + 0x080cf81f, /* 0008(:658): DRD2B1: idx0 = EU3(); EU3(idx0) */
20010 + 0x8198801b, /* 000C(:659): LCD: idx1 = var3; idx1 once var0; idx1 += inc3 */
20011 + 0x6000000e, /* 0010(:660): DRD2A: EU0=0 EU1=0 EU2=0 EU3=14 EXT init=0 WS=0 RS=0 */
20012 + 0x084cf85f, /* 0014(:660): DRD2B1: idx1 = EU3(); EU3(idx1) */
20013 + 0x000001f8, /* 0018(:0): NOP */
20014 + 0x8298001b, /* 001C(:664): LCD: idx0 = var5; idx0 once var0; idx0 += inc3 */
20015 + 0x7000000d, /* 0020(:665): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */
20016 + 0x010cf81f, /* 0024(:665): DRD2B1: var4 = EU3(); EU3(idx0) */
20017 + 0x6000000e, /* 0028(:666): DRD2A: EU0=0 EU1=0 EU2=0 EU3=14 EXT init=0 WS=0 RS=0 */
20018 + 0x018cf81f, /* 002C(:666): DRD2B1: var6 = EU3(); EU3(idx0) */
20019 + 0xc202601b, /* 0030(:669): LCDEXT: idx0 = var4, idx1 = var4; ; idx0 += inc3, idx1 += inc3 */
20020 + 0xc002221c, /* 0034(:669): LCDEXT: idx2 = var0, idx3 = var4; idx3 == var8; idx2 += inc3, idx3 += inc4 */
20021 + 0x809a601b, /* 0038(:670): LCD: idx4 = var1; ; idx4 += inc3 */
20022 + 0xc10420c2, /* 003C(:673): LCDEXT: idx5 = var2, idx6 = var8; idx6 < var3; idx5 += inc0, idx6 += inc2 */
20023 + 0x839be009, /* 0040(:673): LCD: idx7 = var7; ; idx7 += inc1 */
20024 + 0x03fed7b8, /* 0044(:676): DRD1A: *idx7; FN=0 init=31 WS=3 RS=3 */
20025 + 0xda9b001b, /* 0048(:678): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */
20026 + 0x9b9be01b, /* 004C(:678): LCD: idx7 = idx7; ; idx7 += inc3 */
20027 + 0x70000006, /* 0050(:680): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
20028 + 0x088cf889, /* 0054(:680): DRD2B1: idx2 = EU3(); EU3(idx2,var9) */
20029 + 0x1000cb28, /* 0058(:681): DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */
20030 + 0x70000006, /* 005C(:682): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
20031 + 0x088cf889, /* 0060(:682): DRD2B1: idx2 = EU3(); EU3(idx2,var9) */
20032 + 0x1000cb30, /* 0064(:683): DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */
20033 + 0x70000006, /* 0068(:684): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
20034 + 0x088cf889, /* 006C(:684): DRD2B1: idx2 = EU3(); EU3(idx2,var9) */
20035 + 0x0000cb38, /* 0070(:685): DRD1A: *idx2 = idx7; FN=0 init=0 WS=0 RS=0 */
20036 + 0x000001f8, /* 0074(:0): NOP */
20037 + 0xc202601b, /* 0078(:689): LCDEXT: idx0 = var4, idx1 = var4; ; idx0 += inc3, idx1 += inc3 */
20038 + 0xc002229c, /* 007C(:689): LCDEXT: idx2 = var0, idx3 = var4; idx3 == var10; idx2 += inc3, idx3 += inc4 */
20039 + 0x809a601b, /* 0080(:690): LCD: idx4 = var1; ; idx4 += inc3 */
20040 + 0xda9b001b, /* 0084(:693): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */
20041 + 0x9b9be01b, /* 0088(:693): LCD: idx7 = idx7; ; idx7 += inc3 */
20042 + 0x0000d3a0, /* 008C(:694): DRD1A: *idx4; FN=0 init=0 WS=0 RS=0 */
20043 + 0xc10420c2, /* 0090(:696): LCDEXT: idx5 = var2, idx6 = var8; idx6 < var3; idx5 += inc0, idx6 += inc2 */
20044 + 0x839be009, /* 0094(:696): LCD: idx7 = var7; ; idx7 += inc1 */
20045 + 0x0bfed7b8, /* 0098(:699): DRD1A: *idx7; FN=0 TFD init=31 WS=3 RS=3 */
20046 + 0xda9b001b, /* 009C(:701): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */
20047 + 0x9b9be01b, /* 00A0(:701): LCD: idx7 = idx7; ; idx7 += inc3 */
20048 + 0x70000006, /* 00A4(:703): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
20049 + 0x088cf889, /* 00A8(:703): DRD2B1: idx2 = EU3(); EU3(idx2,var9) */
20050 + 0x1000cb28, /* 00AC(:704): DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */
20051 + 0x70000006, /* 00B0(:705): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
20052 + 0x088cf889, /* 00B4(:705): DRD2B1: idx2 = EU3(); EU3(idx2,var9) */
20053 + 0x1000cb30, /* 00B8(:706): DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */
20054 + 0x70000006, /* 00BC(:707): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
20055 + 0x088cf889, /* 00C0(:707): DRD2B1: idx2 = EU3(); EU3(idx2,var9) */
20056 + 0x0000cb38, /* 00C4(:708): DRD1A: *idx2 = idx7; FN=0 init=0 WS=0 RS=0 */
20057 + 0x000001f8, /* 00C8(:0): NOP */
20058 + 0xc318022d, /* 00CC(:712): LCDEXT: idx0 = var6; idx0 > var8; idx0 += inc5 */
20059 + 0x8018801b, /* 00D0(:712): LCD: idx1 = var0; idx1 once var0; idx1 += inc3 */
20060 + 0x040001f8, /* 00D4(:713): DRD1A: FN=0 INT init=0 WS=0 RS=0 */
20061 +};
20062 +#ifdef MCD_INCLUDE_EU
20063 +u32 MCD_ChainEu_TDT[]=
20064 +{
20065 + 0x80004000, /* 0000(:947): LCDEXT: idx0 = 0x00000000; ; */
20066 + 0x8198801b, /* 0004(:947): LCD: idx1 = var3; idx1 once var0; idx1 += inc3 */
20067 + 0xb8c68018, /* 0008(:948): LCD: idx2 = *(idx1 + var13); idx2 once var0; idx2 += inc3 */
20068 + 0x10002f10, /* 000C(:949): DRD1A: var11 = idx2; FN=0 MORE init=0 WS=0 RS=0 */
20069 + 0x7000000d, /* 0010(:950): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */
20070 + 0x01ccf89f, /* 0014(:950): DRD2B1: var7 = EU3(); EU3(idx2) */
20071 + 0x6000000a, /* 0018(:951): DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT init=0 WS=0 RS=0 */
20072 + 0x080cf89f, /* 001C(:951): DRD2B1: idx0 = EU3(); EU3(idx2) */
20073 + 0x000001f8, /* 0020(:0): NOP */
20074 + 0x981803a4, /* 0024(:955): LCD: idx0 = idx0; idx0 == var14; idx0 += inc4 */
20075 + 0x8198801b, /* 0028(:957): LCD: idx1 = var3; idx1 once var0; idx1 += inc3 */
20076 + 0xf8c6801a, /* 002C(:958): LCDEXT: idx2 = *(idx1 + var13 + 8); idx2 once var0; idx2 += inc3 */
20077 + 0xb8c6e01b, /* 0030(:959): LCD: idx3 = *(idx1 + var13 + 12); ; idx3 += inc3 */
20078 + 0x10002b10, /* 0034(:961): DRD1A: var10 = idx2; FN=0 MORE init=0 WS=0 RS=0 */
20079 + 0x00001318, /* 0038(:962): DRD1A: var4 = idx3; FN=0 init=0 WS=0 RS=0 */
20080 + 0xb8c6801d, /* 003C(:964): LCD: idx2 = *(idx1 + var13 + 20); idx2 once var0; idx2 += inc3 */
20081 + 0x10001710, /* 0040(:965): DRD1A: var5 = idx2; FN=0 MORE init=0 WS=0 RS=0 */
20082 + 0x60000007, /* 0044(:966): DRD2A: EU0=0 EU1=0 EU2=0 EU3=7 EXT init=0 WS=0 RS=0 */
20083 + 0x018cf88c, /* 0048(:966): DRD2B1: var6 = EU3(); EU3(idx2,var12) */
20084 + 0x98c6801c, /* 004C(:968): LCD: idx2 = idx1 + var13 + 4; idx2 once var0; idx2 += inc3 */
20085 + 0x00000b10, /* 0050(:969): DRD1A: var2 = idx2; FN=0 init=0 WS=0 RS=0 */
20086 + 0x98c78018, /* 0054(:970): LCD: idx2 = idx1 + var15; idx2 once var0; idx2 += inc3 */
20087 + 0x10002310, /* 0058(:971): DRD1A: var8 = idx2; FN=0 MORE init=0 WS=0 RS=0 */
20088 + 0x0000c820, /* 005C(:972): DRD1A: *idx2 = var4; FN=0 init=0 WS=0 RS=0 */
20089 + 0x000001f8, /* 0060(:0): NOP */
20090 + 0x8698801b, /* 0064(:976): LCD: idx1 = var13; idx1 once var0; idx1 += inc3 */
20091 + 0x7000000f, /* 0068(:977): DRD2A: EU0=0 EU1=0 EU2=0 EU3=15 EXT MORE init=0 WS=0 RS=0 */
20092 + 0x084cf2df, /* 006C(:977): DRD2B1: idx1 = EU3(); EU3(var11) */
20093 + 0xd899042d, /* 0070(:978): LCDEXT: idx2 = idx1; idx2 >= var16; idx2 += inc5 */
20094 + 0x8019801b, /* 0074(:978): LCD: idx3 = var0; idx3 once var0; idx3 += inc3 */
20095 + 0x60000003, /* 0078(:979): DRD2A: EU0=0 EU1=0 EU2=0 EU3=3 EXT init=0 WS=0 RS=0 */
20096 + 0x2cd7c7df, /* 007C(:979): DRD2B2: EU3(var13) */
20097 + 0xd8990364, /* 0080(:980): LCDEXT: idx2 = idx1; idx2 == var13; idx2 += inc4 */
20098 + 0x8019801b, /* 0084(:980): LCD: idx3 = var0; idx3 once var0; idx3 += inc3 */
20099 + 0x60000003, /* 0088(:981): DRD2A: EU0=0 EU1=0 EU2=0 EU3=3 EXT init=0 WS=0 RS=0 */
20100 + 0x2c17c7df, /* 008C(:981): DRD2B2: EU3(var1) */
20101 + 0x000001f8, /* 0090(:0): NOP */
20102 + 0xc1c7e018, /* 0094(:984): LCDEXT: idx1 = var3 + var15; ; idx1 += inc3 */
20103 + 0xc003a35e, /* 0098(:984): LCDEXT: idx2 = var0, idx3 = var7; idx3 == var13; idx2 += inc3, idx3 += inc6 */
20104 + 0x819a601b, /* 009C(:985): LCD: idx4 = var3; ; idx4 += inc3 */
20105 + 0xc206a142, /* 00A0(:988): LCDEXT: idx5 = var4, idx6 = var13; idx6 < var5; idx5 += inc0, idx6 += inc2 */
20106 + 0x851be009, /* 00A4(:988): LCD: idx7 = var10; ; idx7 += inc1 */
20107 + 0x63fe0000, /* 00A8(:991): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=31 WS=3 RS=3 */
20108 + 0x0d4cfddf, /* 00AC(:991): DRD2B1: *idx5 = EU3(); EU3(*idx7) */
20109 + 0xda9b001b, /* 00B0(:993): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */
20110 + 0x9b9be01b, /* 00B4(:993): LCD: idx7 = idx7; ; idx7 += inc3 */
20111 + 0x70000002, /* 00B8(:994): DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT MORE init=0 WS=0 RS=0 */
20112 + 0x004cf81f, /* 00BC(:994): DRD2B1: var1 = EU3(); EU3(idx0) */
20113 + 0x1000cb20, /* 00C0(:995): DRD1A: *idx2 = idx4; FN=0 MORE init=0 WS=0 RS=0 */
20114 + 0x70000006, /* 00C4(:996): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
20115 + 0x088cf891, /* 00C8(:996): DRD2B1: idx2 = EU3(); EU3(idx2,var17) */
20116 + 0x1000cb28, /* 00CC(:997): DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */
20117 + 0x70000006, /* 00D0(:998): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
20118 + 0x088cf891, /* 00D4(:998): DRD2B1: idx2 = EU3(); EU3(idx2,var17) */
20119 + 0x1000cb30, /* 00D8(:999): DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */
20120 + 0x70000006, /* 00DC(:1000): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
20121 + 0x088cf891, /* 00E0(:1000): DRD2B1: idx2 = EU3(); EU3(idx2,var17) */
20122 + 0x1000cb38, /* 00E4(:1001): DRD1A: *idx2 = idx7; FN=0 MORE init=0 WS=0 RS=0 */
20123 + 0x0000c728, /* 00E8(:1002): DRD1A: *idx1 = idx5; FN=0 init=0 WS=0 RS=0 */
20124 + 0x000001f8, /* 00EC(:0): NOP */
20125 + 0xc1c7e018, /* 00F0(:1006): LCDEXT: idx1 = var3 + var15; ; idx1 += inc3 */
20126 + 0xc003a49e, /* 00F4(:1006): LCDEXT: idx2 = var0, idx3 = var7; idx3 == var18; idx2 += inc3, idx3 += inc6 */
20127 + 0x819a601b, /* 00F8(:1007): LCD: idx4 = var3; ; idx4 += inc3 */
20128 + 0xda9b001b, /* 00FC(:1010): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */
20129 + 0x9b9be01b, /* 0100(:1010): LCD: idx7 = idx7; ; idx7 += inc3 */
20130 + 0x0000d3a0, /* 0104(:1011): DRD1A: *idx4; FN=0 init=0 WS=0 RS=0 */
20131 + 0xc206a142, /* 0108(:1013): LCDEXT: idx5 = var4, idx6 = var13; idx6 < var5; idx5 += inc0, idx6 += inc2 */
20132 + 0x851be009, /* 010C(:1013): LCD: idx7 = var10; ; idx7 += inc1 */
20133 + 0x6bfe0000, /* 0110(:1016): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 TFD EXT init=31 WS=3 RS=3 */
20134 + 0x0d4cfddf, /* 0114(:1016): DRD2B1: *idx5 = EU3(); EU3(*idx7) */
20135 + 0xda9b001b, /* 0118(:1018): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */
20136 + 0x9b9be01b, /* 011C(:1018): LCD: idx7 = idx7; ; idx7 += inc3 */
20137 + 0x70000002, /* 0120(:1019): DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT MORE init=0 WS=0 RS=0 */
20138 + 0x004cf81f, /* 0124(:1019): DRD2B1: var1 = EU3(); EU3(idx0) */
20139 + 0x1000cb20, /* 0128(:1020): DRD1A: *idx2 = idx4; FN=0 MORE init=0 WS=0 RS=0 */
20140 + 0x70000006, /* 012C(:1021): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
20141 + 0x088cf891, /* 0130(:1021): DRD2B1: idx2 = EU3(); EU3(idx2,var17) */
20142 + 0x1000cb28, /* 0134(:1022): DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */
20143 + 0x70000006, /* 0138(:1023): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
20144 + 0x088cf891, /* 013C(:1023): DRD2B1: idx2 = EU3(); EU3(idx2,var17) */
20145 + 0x1000cb30, /* 0140(:1024): DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */
20146 + 0x70000006, /* 0144(:1025): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
20147 + 0x088cf891, /* 0148(:1025): DRD2B1: idx2 = EU3(); EU3(idx2,var17) */
20148 + 0x1000cb38, /* 014C(:1026): DRD1A: *idx2 = idx7; FN=0 MORE init=0 WS=0 RS=0 */
20149 + 0x0000c728, /* 0150(:1027): DRD1A: *idx1 = idx5; FN=0 init=0 WS=0 RS=0 */
20150 + 0x000001f8, /* 0154(:0): NOP */
20151 + 0x8198801b, /* 0158(:1031): LCD: idx1 = var3; idx1 once var0; idx1 += inc3 */
20152 + 0xd8c68018, /* 015C(:1033): LCDEXT: idx2 = idx1 + var13; idx2 once var0; idx2 += inc3 */
20153 + 0x98c6e01c, /* 0160(:1033): LCD: idx3 = idx1 + var13 + 4; ; idx3 += inc3 */
20154 + 0x6000000b, /* 0164(:1034): DRD2A: EU0=0 EU1=0 EU2=0 EU3=11 EXT init=0 WS=0 RS=0 */
20155 + 0x0c8cfc9f, /* 0168(:1034): DRD2B1: *idx2 = EU3(); EU3(*idx2) */
20156 + 0x0000cc08, /* 016C(:1035): DRD1A: *idx3 = var1; FN=0 init=0 WS=0 RS=0 */
20157 + 0xa1c6801e, /* 0170(:1038): LCD: idx1 = *(var3 + var13 + 24); idx1 once var0; idx1 += inc3 */
20158 + 0x10000f08, /* 0174(:1039): DRD1A: var3 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
20159 + 0x10002458, /* 0178(:1040): DRD1A: var9 = var11; FN=0 MORE init=0 WS=0 RS=0 */
20160 + 0xb8c68018, /* 017C(:1041): LCD: idx2 = *(idx1 + var13); idx2 once var0; idx2 += inc3 */
20161 + 0x10002f10, /* 0180(:1042): DRD1A: var11 = idx2; FN=0 MORE init=0 WS=0 RS=0 */
20162 + 0x7000000a, /* 0184(:1043): DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT MORE init=0 WS=0 RS=0 */
20163 + 0x080cf89f, /* 0188(:1043): DRD2B1: idx0 = EU3(); EU3(idx2) */
20164 + 0x6000000d, /* 018C(:1044): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT init=0 WS=0 RS=0 */
20165 + 0x01ccf89f, /* 0190(:1044): DRD2B1: var7 = EU3(); EU3(idx2) */
20166 + 0x000001f8, /* 0194(:0): NOP */
20167 + 0x8698801b, /* 0198(:1050): LCD: idx1 = var13; idx1 once var0; idx1 += inc3 */
20168 + 0x7000000e, /* 019C(:1051): DRD2A: EU0=0 EU1=0 EU2=0 EU3=14 EXT MORE init=0 WS=0 RS=0 */
20169 + 0x084cf25f, /* 01A0(:1051): DRD2B1: idx1 = EU3(); EU3(var9) */
20170 + 0xd899037f, /* 01A4(:1052): LCDEXT: idx2 = idx1; idx2 > var13; idx2 += inc7 */
20171 + 0x8019801b, /* 01A8(:1052): LCD: idx3 = var0; idx3 once var0; idx3 += inc3 */
20172 + 0x040001f8, /* 01AC(:1053): DRD1A: FN=0 INT init=0 WS=0 RS=0 */
20173 + 0x000001f8, /* 01B0(:0): NOP */
20174 + 0x000001f8, /* 01B4(:0): NOP */
20175 +};
20176 +u32 MCD_SingleEu_TDT[]=
20177 +{
20178 + 0x8218001b, /* 0000(:1248): LCD: idx0 = var4; idx0 once var0; idx0 += inc3 */
20179 + 0x7000000d, /* 0004(:1249): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */
20180 + 0x080cf81f, /* 0008(:1249): DRD2B1: idx0 = EU3(); EU3(idx0) */
20181 + 0x8218801b, /* 000C(:1250): LCD: idx1 = var4; idx1 once var0; idx1 += inc3 */
20182 + 0x6000000e, /* 0010(:1251): DRD2A: EU0=0 EU1=0 EU2=0 EU3=14 EXT init=0 WS=0 RS=0 */
20183 + 0x084cf85f, /* 0014(:1251): DRD2B1: idx1 = EU3(); EU3(idx1) */
20184 + 0x000001f8, /* 0018(:0): NOP */
20185 + 0x8318001b, /* 001C(:1255): LCD: idx0 = var6; idx0 once var0; idx0 += inc3 */
20186 + 0x7000000d, /* 0020(:1256): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */
20187 + 0x014cf81f, /* 0024(:1256): DRD2B1: var5 = EU3(); EU3(idx0) */
20188 + 0x6000000e, /* 0028(:1257): DRD2A: EU0=0 EU1=0 EU2=0 EU3=14 EXT init=0 WS=0 RS=0 */
20189 + 0x01ccf81f, /* 002C(:1257): DRD2B1: var7 = EU3(); EU3(idx0) */
20190 + 0x8498001b, /* 0030(:1260): LCD: idx0 = var9; idx0 once var0; idx0 += inc3 */
20191 + 0x7000000f, /* 0034(:1261): DRD2A: EU0=0 EU1=0 EU2=0 EU3=15 EXT MORE init=0 WS=0 RS=0 */
20192 + 0x080cf19f, /* 0038(:1261): DRD2B1: idx0 = EU3(); EU3(var6) */
20193 + 0xd81882a4, /* 003C(:1262): LCDEXT: idx1 = idx0; idx1 >= var10; idx1 += inc4 */
20194 + 0x8019001b, /* 0040(:1262): LCD: idx2 = var0; idx2 once var0; idx2 += inc3 */
20195 + 0x60000003, /* 0044(:1263): DRD2A: EU0=0 EU1=0 EU2=0 EU3=3 EXT init=0 WS=0 RS=0 */
20196 + 0x2c97c7df, /* 0048(:1263): DRD2B2: EU3(var9) */
20197 + 0xd818826d, /* 004C(:1264): LCDEXT: idx1 = idx0; idx1 == var9; idx1 += inc5 */
20198 + 0x8019001b, /* 0050(:1264): LCD: idx2 = var0; idx2 once var0; idx2 += inc3 */
20199 + 0x60000003, /* 0054(:1265): DRD2A: EU0=0 EU1=0 EU2=0 EU3=3 EXT init=0 WS=0 RS=0 */
20200 + 0x2c17c7df, /* 0058(:1265): DRD2B2: EU3(var1) */
20201 + 0x000001f8, /* 005C(:0): NOP */
20202 + 0xc282e01b, /* 0060(:1268): LCDEXT: idx0 = var5, idx1 = var5; ; idx0 += inc3, idx1 += inc3 */
20203 + 0xc002a25e, /* 0064(:1268): LCDEXT: idx2 = var0, idx3 = var5; idx3 == var9; idx2 += inc3, idx3 += inc6 */
20204 + 0x811a601b, /* 0068(:1269): LCD: idx4 = var2; ; idx4 += inc3 */
20205 + 0xc184a102, /* 006C(:1272): LCDEXT: idx5 = var3, idx6 = var9; idx6 < var4; idx5 += inc0, idx6 += inc2 */
20206 + 0x841be009, /* 0070(:1272): LCD: idx7 = var8; ; idx7 += inc1 */
20207 + 0x63fe0000, /* 0074(:1275): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=31 WS=3 RS=3 */
20208 + 0x0d4cfddf, /* 0078(:1275): DRD2B1: *idx5 = EU3(); EU3(*idx7) */
20209 + 0xda9b001b, /* 007C(:1277): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */
20210 + 0x9b9be01b, /* 0080(:1277): LCD: idx7 = idx7; ; idx7 += inc3 */
20211 + 0x70000002, /* 0084(:1279): DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT MORE init=0 WS=0 RS=0 */
20212 + 0x004cf99f, /* 0088(:1279): DRD2B1: var1 = EU3(); EU3(idx6) */
20213 + 0x70000006, /* 008C(:1280): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
20214 + 0x088cf88b, /* 0090(:1280): DRD2B1: idx2 = EU3(); EU3(idx2,var11) */
20215 + 0x1000cb28, /* 0094(:1281): DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */
20216 + 0x70000006, /* 0098(:1282): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
20217 + 0x088cf88b, /* 009C(:1282): DRD2B1: idx2 = EU3(); EU3(idx2,var11) */
20218 + 0x1000cb30, /* 00A0(:1283): DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */
20219 + 0x70000006, /* 00A4(:1284): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
20220 + 0x088cf88b, /* 00A8(:1284): DRD2B1: idx2 = EU3(); EU3(idx2,var11) */
20221 + 0x0000cb38, /* 00AC(:1285): DRD1A: *idx2 = idx7; FN=0 init=0 WS=0 RS=0 */
20222 + 0x000001f8, /* 00B0(:0): NOP */
20223 + 0xc282e01b, /* 00B4(:1289): LCDEXT: idx0 = var5, idx1 = var5; ; idx0 += inc3, idx1 += inc3 */
20224 + 0xc002a31e, /* 00B8(:1289): LCDEXT: idx2 = var0, idx3 = var5; idx3 == var12; idx2 += inc3, idx3 += inc6 */
20225 + 0x811a601b, /* 00BC(:1290): LCD: idx4 = var2; ; idx4 += inc3 */
20226 + 0xda9b001b, /* 00C0(:1293): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */
20227 + 0x9b9be01b, /* 00C4(:1293): LCD: idx7 = idx7; ; idx7 += inc3 */
20228 + 0x0000d3a0, /* 00C8(:1294): DRD1A: *idx4; FN=0 init=0 WS=0 RS=0 */
20229 + 0xc184a102, /* 00CC(:1296): LCDEXT: idx5 = var3, idx6 = var9; idx6 < var4; idx5 += inc0, idx6 += inc2 */
20230 + 0x841be009, /* 00D0(:1296): LCD: idx7 = var8; ; idx7 += inc1 */
20231 + 0x6bfe0000, /* 00D4(:1299): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 TFD EXT init=31 WS=3 RS=3 */
20232 + 0x0d4cfddf, /* 00D8(:1299): DRD2B1: *idx5 = EU3(); EU3(*idx7) */
20233 + 0xda9b001b, /* 00DC(:1301): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */
20234 + 0x9b9be01b, /* 00E0(:1301): LCD: idx7 = idx7; ; idx7 += inc3 */
20235 + 0x70000002, /* 00E4(:1303): DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT MORE init=0 WS=0 RS=0 */
20236 + 0x004cf99f, /* 00E8(:1303): DRD2B1: var1 = EU3(); EU3(idx6) */
20237 + 0x70000006, /* 00EC(:1304): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
20238 + 0x088cf88b, /* 00F0(:1304): DRD2B1: idx2 = EU3(); EU3(idx2,var11) */
20239 + 0x1000cb28, /* 00F4(:1305): DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */
20240 + 0x70000006, /* 00F8(:1306): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
20241 + 0x088cf88b, /* 00FC(:1306): DRD2B1: idx2 = EU3(); EU3(idx2,var11) */
20242 + 0x1000cb30, /* 0100(:1307): DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */
20243 + 0x70000006, /* 0104(:1308): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
20244 + 0x088cf88b, /* 0108(:1308): DRD2B1: idx2 = EU3(); EU3(idx2,var11) */
20245 + 0x0000cb38, /* 010C(:1309): DRD1A: *idx2 = idx7; FN=0 init=0 WS=0 RS=0 */
20246 + 0x000001f8, /* 0110(:0): NOP */
20247 + 0x8144801c, /* 0114(:1312): LCD: idx0 = var2 + var9 + 4; idx0 once var0; idx0 += inc3 */
20248 + 0x0000c008, /* 0118(:1313): DRD1A: *idx0 = var1; FN=0 init=0 WS=0 RS=0 */
20249 + 0xc398027f, /* 011C(:1315): LCDEXT: idx0 = var7; idx0 > var9; idx0 += inc7 */
20250 + 0x8018801b, /* 0120(:1315): LCD: idx1 = var0; idx1 once var0; idx1 += inc3 */
20251 + 0x040001f8, /* 0124(:1316): DRD1A: FN=0 INT init=0 WS=0 RS=0 */
20252 +};
20253 +#endif
20254 +u32 MCD_ENetRcv_TDT[]=
20255 +{
20256 + 0x80004000, /* 0000(:1389): LCDEXT: idx0 = 0x00000000; ; */
20257 + 0x81988000, /* 0004(:1389): LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
20258 + 0x10000788, /* 0008(:1390): DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
20259 + 0x6000000a, /* 000C(:1391): DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT init=0 WS=0 RS=0 */
20260 + 0x080cf05f, /* 0010(:1391): DRD2B1: idx0 = EU3(); EU3(var1) */
20261 + 0x98180209, /* 0014(:1394): LCD: idx0 = idx0; idx0 != var8; idx0 += inc1 */
20262 + 0x81c40004, /* 0018(:1396): LCD: idx1 = var3 + var8 + 4; idx1 once var0; idx1 += inc0 */
20263 + 0x7000000e, /* 001C(:1397): DRD2A: EU0=0 EU1=0 EU2=0 EU3=14 EXT MORE init=0 WS=0 RS=0 */
20264 + 0x010cf05f, /* 0020(:1397): DRD2B1: var4 = EU3(); EU3(var1) */
20265 + 0x7000000c, /* 0024(:1398): DRD2A: EU0=0 EU1=0 EU2=0 EU3=12 EXT MORE init=0 WS=0 RS=0 */
20266 + 0x01ccf05f, /* 0028(:1398): DRD2B1: var7 = EU3(); EU3(var1) */
20267 + 0x70000004, /* 002C(:1399): DRD2A: EU0=0 EU1=0 EU2=0 EU3=4 EXT MORE init=0 WS=0 RS=0 */
20268 + 0x014cf049, /* 0030(:1399): DRD2B1: var5 = EU3(); EU3(var1,var9) */
20269 + 0x70000004, /* 0034(:1400): DRD2A: EU0=0 EU1=0 EU2=0 EU3=4 EXT MORE init=0 WS=0 RS=0 */
20270 + 0x004cf04a, /* 0038(:1400): DRD2B1: var1 = EU3(); EU3(var1,var10) */
20271 + 0x00000b88, /* 003C(:1403): DRD1A: var2 = *idx1; FN=0 init=0 WS=0 RS=0 */
20272 + 0xc4030150, /* 0040(:1406): LCDEXT: idx1 = var8, idx2 = var6; idx1 < var5; idx1 += inc2, idx2 += inc0 */
20273 + 0x8119e012, /* 0044(:1406): LCD: idx3 = var2; ; idx3 += inc2 */
20274 + 0x03e0cf90, /* 0048(:1409): DRD1A: *idx3 = *idx2; FN=0 init=31 WS=0 RS=0 */
20275 + 0x81188000, /* 004C(:1412): LCD: idx1 = var2; idx1 once var0; idx1 += inc0 */
20276 + 0x000ac788, /* 0050(:1413): DRD1A: *idx1 = *idx1; FN=0 init=0 WS=1 RS=1 */
20277 + 0xc4030000, /* 0054(:1415): LCDEXT: idx1 = var8, idx2 = var6; idx1 once var0; idx1 += inc0, idx2 += inc0 */
20278 + 0x8199e000, /* 0058(:1415): LCD: idx3 = var3; ; idx3 += inc0 */
20279 + 0x63e00004, /* 005C(:1418): DRD2A: EU0=0 EU1=0 EU2=0 EU3=4 EXT init=31 WS=0 RS=0 */
20280 + 0x084cfc8b, /* 0060(:1418): DRD2B1: idx1 = EU3(); EU3(*idx2,var11) */
20281 + 0xd8990000, /* 0064(:1421): LCDEXT: idx1 = idx1, idx2 = idx2; idx1 once var0; idx1 += inc0, idx2 += inc0 */
20282 + 0x9999e000, /* 0068(:1421): LCD: idx3 = idx3; ; idx3 += inc0 */
20283 + 0x60000005, /* 006C(:1422): DRD2A: EU0=0 EU1=0 EU2=0 EU3=5 EXT init=0 WS=0 RS=0 */
20284 + 0x0cccf841, /* 0070(:1422): DRD2B1: *idx3 = EU3(); EU3(idx1,var1) */
20285 + 0x81c60000, /* 0074(:1427): LCD: idx1 = var3 + var12; idx1 once var0; idx1 += inc0 */
20286 + 0xc399021b, /* 0078(:1429): LCDEXT: idx2 = var7; idx2 > var8; idx2 += inc3 */
20287 + 0x80198000, /* 007C(:1429): LCD: idx3 = var0; idx3 once var0; idx3 += inc0 */
20288 + 0x00008400, /* 0080(:1430): DRD1A: idx1 = var0; FN=0 init=0 WS=0 RS=0 */
20289 + 0x00000f08, /* 0084(:1431): DRD1A: var3 = idx1; FN=0 init=0 WS=0 RS=0 */
20290 + 0x81988000, /* 0088(:1434): LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
20291 + 0x10000788, /* 008C(:1435): DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
20292 + 0x6000000a, /* 0090(:1436): DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT init=0 WS=0 RS=0 */
20293 + 0x080cf05f, /* 0094(:1436): DRD2B1: idx0 = EU3(); EU3(var1) */
20294 + 0xc2188209, /* 0098(:1439): LCDEXT: idx1 = var4; idx1 != var8; idx1 += inc1 */
20295 + 0x80190000, /* 009C(:1439): LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */
20296 + 0x040001f8, /* 00A0(:1440): DRD1A: FN=0 INT init=0 WS=0 RS=0 */
20297 + 0x000001f8, /* 00A4(:0): NOP */
20298 +};
20299 +u32 MCD_ENetXmit_TDT[]=
20300 +{
20301 + 0x80004000, /* 0000(:1515): LCDEXT: idx0 = 0x00000000; ; */
20302 + 0x81988000, /* 0004(:1515): LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
20303 + 0x10000788, /* 0008(:1516): DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
20304 + 0x6000000a, /* 000C(:1517): DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT init=0 WS=0 RS=0 */
20305 + 0x080cf05f, /* 0010(:1517): DRD2B1: idx0 = EU3(); EU3(var1) */
20306 + 0x98180309, /* 0014(:1520): LCD: idx0 = idx0; idx0 != var12; idx0 += inc1 */
20307 + 0x80004003, /* 0018(:1522): LCDEXT: idx1 = 0x00000003; ; */
20308 + 0x81c60004, /* 001C(:1522): LCD: idx2 = var3 + var12 + 4; idx2 once var0; idx2 += inc0 */
20309 + 0x7000000e, /* 0020(:1523): DRD2A: EU0=0 EU1=0 EU2=0 EU3=14 EXT MORE init=0 WS=0 RS=0 */
20310 + 0x014cf05f, /* 0024(:1523): DRD2B1: var5 = EU3(); EU3(var1) */
20311 + 0x7000000c, /* 0028(:1524): DRD2A: EU0=0 EU1=0 EU2=0 EU3=12 EXT MORE init=0 WS=0 RS=0 */
20312 + 0x028cf05f, /* 002C(:1524): DRD2B1: var10 = EU3(); EU3(var1) */
20313 + 0x7000000d, /* 0030(:1525): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */
20314 + 0x018cf05f, /* 0034(:1525): DRD2B1: var6 = EU3(); EU3(var1) */
20315 + 0x70000004, /* 0038(:1526): DRD2A: EU0=0 EU1=0 EU2=0 EU3=4 EXT MORE init=0 WS=0 RS=0 */
20316 + 0x01ccf04d, /* 003C(:1526): DRD2B1: var7 = EU3(); EU3(var1,var13) */
20317 + 0x10000b90, /* 0040(:1527): DRD1A: var2 = *idx2; FN=0 MORE init=0 WS=0 RS=0 */
20318 + 0x60000004, /* 0044(:1528): DRD2A: EU0=0 EU1=0 EU2=0 EU3=4 EXT init=0 WS=0 RS=0 */
20319 + 0x020cf0a1, /* 0048(:1528): DRD2B1: var8 = EU3(); EU3(var2,idx1) */
20320 + 0xc3188312, /* 004C(:1531): LCDEXT: idx1 = var6; idx1 > var12; idx1 += inc2 */
20321 + 0x83c70000, /* 0050(:1531): LCD: idx2 = var7 + var14; idx2 once var0; idx2 += inc0 */
20322 + 0x00001f10, /* 0054(:1532): DRD1A: var7 = idx2; FN=0 init=0 WS=0 RS=0 */
20323 + 0xc583a3c3, /* 0058(:1534): LCDEXT: idx1 = var11, idx2 = var7; idx2 >= var15; idx1 += inc0, idx2 += inc3 */
20324 + 0x81042325, /* 005C(:1534): LCD: idx3 = var2, idx4 = var8; idx4 == var12; idx3 += inc4, idx4 += inc5 */
20325 + 0x03e0c798, /* 0060(:1539): DRD1A: *idx1 = *idx3; FN=0 init=31 WS=0 RS=0 */
20326 + 0xd8990000, /* 0064(:1542): LCDEXT: idx1 = idx1, idx2 = idx2; idx1 once var0; idx1 += inc0, idx2 += inc0 */
20327 + 0x9999e000, /* 0068(:1542): LCD: idx3 = idx3; ; idx3 += inc0 */
20328 + 0x000acf98, /* 006C(:1543): DRD1A: *idx3 = *idx3; FN=0 init=0 WS=1 RS=1 */
20329 + 0xd8992306, /* 0070(:1545): LCDEXT: idx1 = idx1, idx2 = idx2; idx2 > var12; idx1 += inc0, idx2 += inc6 */
20330 + 0x9999e03f, /* 0074(:1545): LCD: idx3 = idx3; ; idx3 += inc7 */
20331 + 0x03eac798, /* 0078(:1548): DRD1A: *idx1 = *idx3; FN=0 init=31 WS=1 RS=1 */
20332 + 0xd8990000, /* 007C(:1551): LCDEXT: idx1 = idx1, idx2 = idx2; idx1 once var0; idx1 += inc0, idx2 += inc0 */
20333 + 0x9999e000, /* 0080(:1551): LCD: idx3 = idx3; ; idx3 += inc0 */
20334 + 0x000acf98, /* 0084(:1552): DRD1A: *idx3 = *idx3; FN=0 init=0 WS=1 RS=1 */
20335 + 0xd8990000, /* 0088(:1554): LCDEXT: idx1 = idx1, idx2 = idx2; idx1 once var0; idx1 += inc0, idx2 += inc0 */
20336 + 0x99832302, /* 008C(:1554): LCD: idx3 = idx3, idx4 = var6; idx4 > var12; idx3 += inc0, idx4 += inc2 */
20337 + 0x0beac798, /* 0090(:1557): DRD1A: *idx1 = *idx3; FN=0 TFD init=31 WS=1 RS=1 */
20338 + 0x81988000, /* 0094(:1559): LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
20339 + 0x6000000b, /* 0098(:1560): DRD2A: EU0=0 EU1=0 EU2=0 EU3=11 EXT init=0 WS=0 RS=0 */
20340 + 0x0c4cfc5f, /* 009C(:1560): DRD2B1: *idx1 = EU3(); EU3(*idx1) */
20341 + 0x81c80000, /* 00A0(:1562): LCD: idx1 = var3 + var16; idx1 once var0; idx1 += inc0 */
20342 + 0xc5190312, /* 00A4(:1564): LCDEXT: idx2 = var10; idx2 > var12; idx2 += inc2 */
20343 + 0x80198000, /* 00A8(:1564): LCD: idx3 = var0; idx3 once var0; idx3 += inc0 */
20344 + 0x00008400, /* 00AC(:1565): DRD1A: idx1 = var0; FN=0 init=0 WS=0 RS=0 */
20345 + 0x00000f08, /* 00B0(:1566): DRD1A: var3 = idx1; FN=0 init=0 WS=0 RS=0 */
20346 + 0x81988000, /* 00B4(:1569): LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
20347 + 0x10000788, /* 00B8(:1570): DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
20348 + 0x6000000a, /* 00BC(:1571): DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT init=0 WS=0 RS=0 */
20349 + 0x080cf05f, /* 00C0(:1571): DRD2B1: idx0 = EU3(); EU3(var1) */
20350 + 0xc2988309, /* 00C4(:1574): LCDEXT: idx1 = var5; idx1 != var12; idx1 += inc1 */
20351 + 0x80190000, /* 00C8(:1574): LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */
20352 + 0x040001f8, /* 00CC(:1575): DRD1A: FN=0 INT init=0 WS=0 RS=0 */
20353 + 0x000001f8, /* 00D0(:0): NOP */
20354 +};
20355 +
20356 +#ifdef MCD_INCLUDE_EU
20357 +MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
20358 +#endif
20359 --- /dev/null
20360 +++ b/drivers/dma/MCD_tasksInit.c
20361 @@ -0,0 +1,238 @@
20362 +/*
20363 + * drivers/dma/MCD_tasksInit.c
20364 + *
20365 + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
20366 + * Kurt Mahan <kmahan@freescale.com>
20367 + *
20368 + * This program is free software; you can redistribute it and/or
20369 + * modify it under the terms of the GNU General Public License as
20370 + * published by the Free Software Foundation; either version 2 of
20371 + * the License, or (at your option) any later version.
20372 + *
20373 + * This program is distributed in the hope that it will be useful,
20374 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
20375 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20376 + * GNU General Public License for more details.
20377 + *
20378 + * You should have received a copy of the GNU General Public License
20379 + * along with this program; if not, write to the Free Software
20380 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20381 + * MA 02111-1307 USA
20382 + */
20383 +
20384 +/*
20385 + * Autogenerated - Do not edit!
20386 + */
20387 +
20388 +#include "MCD_dma.h"
20389 +
20390 +extern dmaRegs *MCD_dmaBar;
20391 +
20392 +
20393 +/*
20394 + * Task 0
20395 + */
20396 +
20397 +void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel)
20398 +{
20399 +
20400 + MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */
20401 + MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
20402 + MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
20403 + MCD_SET_VAR(taskTable+channel, 11, (u32)xferSize); /* var[11] */
20404 + MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
20405 + MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
20406 + MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
20407 + MCD_SET_VAR(taskTable+channel, 3, (u32)0x00000000); /* var[3] */
20408 + MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
20409 + MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
20410 + MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
20411 + MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
20412 + MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
20413 + MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
20414 + MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */
20415 + MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000); /* var[12] */
20416 + MCD_SET_VAR(taskTable+channel, 13, (u32)0x80000000); /* var[13] */
20417 + MCD_SET_VAR(taskTable+channel, 14, (u32)0x00000010); /* var[14] */
20418 + MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004); /* var[15] */
20419 + MCD_SET_VAR(taskTable+channel, 16, (u32)0x08000000); /* var[16] */
20420 + MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
20421 + MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000); /* inc[4] */
20422 + MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000001); /* inc[5] */
20423 + MCD_SET_VAR(taskTable+channel, 30, (u32)0x40000000); /* inc[6] */
20424 +
20425 + /* Set the task's Enable bit in its Task Control Register */
20426 + MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
20427 +}
20428 +
20429 +
20430 +/*
20431 + * Task 1
20432 + */
20433 +
20434 +void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
20435 +{
20436 +
20437 + MCD_SET_VAR(taskTable+channel, 7, (u32)srcAddr); /* var[7] */
20438 + MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
20439 + MCD_SET_VAR(taskTable+channel, 2, (u32)destAddr); /* var[2] */
20440 + MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
20441 + MCD_SET_VAR(taskTable+channel, 3, (u32)dmaSize); /* var[3] */
20442 + MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
20443 + MCD_SET_VAR(taskTable+channel, 5, (u32)flags); /* var[5] */
20444 + MCD_SET_VAR(taskTable+channel, 1, (u32)currBD); /* var[1] */
20445 + MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
20446 + MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
20447 + MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
20448 + MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
20449 + MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000004); /* var[9] */
20450 + MCD_SET_VAR(taskTable+channel, 10, (u32)0x08000000); /* var[10] */
20451 + MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
20452 + MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000001); /* inc[4] */
20453 + MCD_SET_VAR(taskTable+channel, 29, (u32)0x40000000); /* inc[5] */
20454 +
20455 + /* Set the task's Enable bit in its Task Control Register */
20456 + MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
20457 +}
20458 +
20459 +
20460 +/*
20461 + * Task 2
20462 + */
20463 +
20464 +void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel)
20465 +{
20466 +
20467 + MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
20468 + MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
20469 + MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
20470 + MCD_SET_VAR(taskTable+channel, 12, (u32)xferSize); /* var[12] */
20471 + MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
20472 + MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
20473 + MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
20474 + MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
20475 + MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
20476 + MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
20477 + MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
20478 + MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
20479 + MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
20480 + MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
20481 + MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */
20482 + MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000000); /* var[11] */
20483 + MCD_SET_VAR(taskTable+channel, 13, (u32)0x00000000); /* var[13] */
20484 + MCD_SET_VAR(taskTable+channel, 14, (u32)0x80000000); /* var[14] */
20485 + MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000010); /* var[15] */
20486 + MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000001); /* var[16] */
20487 + MCD_SET_VAR(taskTable+channel, 17, (u32)0x00000004); /* var[17] */
20488 + MCD_SET_VAR(taskTable+channel, 18, (u32)0x08000000); /* var[18] */
20489 + MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
20490 + MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000); /* inc[4] */
20491 + MCD_SET_VAR(taskTable+channel, 29, (u32)0xc0000000); /* inc[5] */
20492 + MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001); /* inc[6] */
20493 + MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000); /* inc[7] */
20494 +
20495 + /* Set the task's Enable bit in its Task Control Register */
20496 + MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
20497 +}
20498 +
20499 +
20500 +/*
20501 + * Task 3
20502 + */
20503 +
20504 +void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
20505 +{
20506 +
20507 + MCD_SET_VAR(taskTable+channel, 8, (u32)srcAddr); /* var[8] */
20508 + MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
20509 + MCD_SET_VAR(taskTable+channel, 3, (u32)destAddr); /* var[3] */
20510 + MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
20511 + MCD_SET_VAR(taskTable+channel, 4, (u32)dmaSize); /* var[4] */
20512 + MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
20513 + MCD_SET_VAR(taskTable+channel, 6, (u32)flags); /* var[6] */
20514 + MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */
20515 + MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
20516 + MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
20517 + MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
20518 + MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
20519 + MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
20520 + MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000001); /* var[10] */
20521 + MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000004); /* var[11] */
20522 + MCD_SET_VAR(taskTable+channel, 12, (u32)0x08000000); /* var[12] */
20523 + MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
20524 + MCD_SET_VAR(taskTable+channel, 28, (u32)0xc0000000); /* inc[4] */
20525 + MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000); /* inc[5] */
20526 + MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001); /* inc[6] */
20527 + MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000); /* inc[7] */
20528 +
20529 + /* Set the task's Enable bit in its Task Control Register */
20530 + MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
20531 +}
20532 +
20533 +
20534 +/*
20535 + * Task 4
20536 + */
20537 +
20538 +void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel)
20539 +{
20540 +
20541 + MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */
20542 + MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
20543 + MCD_SET_VAR(taskTable+channel, 6, (u32)rcvFifoPtr); /* var[6] */
20544 + MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
20545 + MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
20546 + MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
20547 + MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
20548 + MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
20549 + MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
20550 + MCD_SET_VAR(taskTable+channel, 9, (u32)0x0000ffff); /* var[9] */
20551 + MCD_SET_VAR(taskTable+channel, 10, (u32)0x30000000); /* var[10] */
20552 + MCD_SET_VAR(taskTable+channel, 11, (u32)0x0fffffff); /* var[11] */
20553 + MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000008); /* var[12] */
20554 + MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000); /* inc[0] */
20555 + MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000); /* inc[1] */
20556 + MCD_SET_VAR(taskTable+channel, 26, (u32)0x20000004); /* inc[2] */
20557 + MCD_SET_VAR(taskTable+channel, 27, (u32)0x40000000); /* inc[3] */
20558 +
20559 + /* Set the task's Enable bit in its Task Control Register */
20560 + MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
20561 +}
20562 +
20563 +
20564 +/*
20565 + * Task 5
20566 + */
20567 +
20568 +void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel)
20569 +{
20570 +
20571 + MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */
20572 + MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
20573 + MCD_SET_VAR(taskTable+channel, 11, (u32)xmitFifoPtr); /* var[11] */
20574 + MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
20575 + MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
20576 + MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
20577 + MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
20578 + MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
20579 + MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
20580 + MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
20581 + MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
20582 + MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */
20583 + MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000); /* var[12] */
20584 + MCD_SET_VAR(taskTable+channel, 13, (u32)0x0000ffff); /* var[13] */
20585 + MCD_SET_VAR(taskTable+channel, 14, (u32)0xffffffff); /* var[14] */
20586 + MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004); /* var[15] */
20587 + MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000008); /* var[16] */
20588 + MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000); /* inc[0] */
20589 + MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000); /* inc[1] */
20590 + MCD_SET_VAR(taskTable+channel, 26, (u32)0x40000000); /* inc[2] */
20591 + MCD_SET_VAR(taskTable+channel, 27, (u32)0xc000fffc); /* inc[3] */
20592 + MCD_SET_VAR(taskTable+channel, 28, (u32)0xe0000004); /* inc[4] */
20593 + MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000); /* inc[5] */
20594 + MCD_SET_VAR(taskTable+channel, 30, (u32)0x4000ffff); /* inc[6] */
20595 + MCD_SET_VAR(taskTable+channel, 31, (u32)0xe0000001); /* inc[7] */
20596 +
20597 + /* Set the task's Enable bit in its Task Control Register */
20598 + MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
20599 +}
20600 --- /dev/null
20601 +++ b/drivers/dma/MCD_tasksInit.h
20602 @@ -0,0 +1,64 @@
20603 +/*
20604 + * drivers/dma/MCD_tasksInit.h
20605 + *
20606 + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
20607 + * Kurt Mahan <kmahan@freescale.com>
20608 + *
20609 + * This program is free software; you can redistribute it and/or
20610 + * modify it under the terms of the GNU General Public License as
20611 + * published by the Free Software Foundation; either version 2 of
20612 + * the License, or (at your option) any later version.
20613 + *
20614 + * This program is distributed in the hope that it will be useful,
20615 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
20616 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20617 + * GNU General Public License for more details.
20618 + *
20619 + * You should have received a copy of the GNU General Public License
20620 + * along with this program; if not, write to the Free Software
20621 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20622 + * MA 02111-1307 USA
20623 + */
20624 +#ifndef MCD_TSK_INIT_H
20625 +#define MCD_TSK_INIT_H 1
20626 +
20627 +/*
20628 + * Autogenerated - Do not edit!
20629 + */
20630 +
20631 +/*
20632 + * Task 0
20633 + */
20634 +void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel);
20635 +
20636 +
20637 +/*
20638 + * Task 1
20639 + */
20640 +void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel);
20641 +
20642 +
20643 +/*
20644 + * Task 2
20645 + */
20646 +void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel);
20647 +
20648 +
20649 +/*
20650 + * Task 3
20651 + */
20652 +void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel);
20653 +
20654 +
20655 +/*
20656 + * Task 4
20657 + */
20658 +void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel);
20659 +
20660 +
20661 +/*
20662 + * Task 5
20663 + */
20664 +void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel);
20665 +
20666 +#endif /* MCD_TSK_INIT_H */
20667 --- /dev/null
20668 +++ b/drivers/i2c/busses/i2c-algo-mcf.h
20669 @@ -0,0 +1,23 @@
20670 +#ifndef I2C_ALGO_MCF_H
20671 +#define I2C_ALGO_MCF_H 1
20672 +
20673 +/* --- Defines for pcf-adapters --------------------------------------- */
20674 +#include <linux/i2c.h>
20675 +
20676 +struct i2c_algo_mcf_data {
20677 + void *data; /* private data for lolevel routines */
20678 + void (*setmcf) (void *data, int ctl, int val);
20679 + int (*getmcf) (void *data, int ctl);
20680 + int (*getown) (void *data);
20681 + int (*getclock) (void *data);
20682 + void (*waitforpin) (void);
20683 + /* local settings */
20684 + int udelay;
20685 + int mdelay;
20686 + int timeout;
20687 +};
20688 +
20689 +int i2c_mcf_add_bus(struct i2c_adapter *);
20690 +int i2c_mcf_del_bus(struct i2c_adapter *);
20691 +
20692 +#endif /* I2C_ALGO_MCF_H */
20693 --- /dev/null
20694 +++ b/drivers/i2c/busses/i2c-mcf548x.c
20695 @@ -0,0 +1,595 @@
20696 +/*
20697 + * Performance and stability improvements: (C) Copyright 2008,
20698 + * Adrian Cox <adrian@humboldt.co.uk>
20699 + * ColdFire 547x/548x I2C master support
20700 + * Shrek Wu (b16972@freescale.com )moved the code driver/i2c/alg/mcf.c
20701 + * into driver/i2c/busses.And changed the driver to a platform driver.
20702 + */
20703 +#include <linux/i2c.h>
20704 +#include "i2c-algo-mcf.h"
20705 +
20706 +#include <linux/init.h>
20707 +#include <linux/kernel.h>
20708 +#include <linux/module.h>
20709 +#include <linux/delay.h>
20710 +#include <linux/platform_device.h>
20711 +#include <linux/sched.h>
20712 +#include <linux/interrupt.h>
20713 +#include <asm/io.h>
20714 +
20715 +#include <asm/coldfire.h>
20716 +#include <asm/m5485sim.h>
20717 +#include <asm/m5485i2c.h>
20718 +
20719 +#define get_clock(adap) (clock)
20720 +#define get_own(adap) (own)
20721 +
20722 +static int clock = 0x3b; /*50000 / 1024 ~ 49 KHz*/
20723 +module_param(clock, int, 0);
20724 +MODULE_PARM_DESC(clock,
20725 + "Set I2C clock in kHz: 400=fast mode (default == 49khz)");
20726 +
20727 +static int own = 0x78;
20728 +module_param(own, int, 0);
20729 +MODULE_PARM_DESC(clock, "Set I2C Master controller address(0x78)");
20730 +
20731 +static struct i2c_algo_mcf_data i2c_mcf_board_data = {
20732 + .timeout = 10000,
20733 +};
20734 +
20735 +static struct i2c_adapter i2c_mcf_board_adapter = {
20736 + .owner = THIS_MODULE,
20737 + .name = "MCF5485 adapter",
20738 + .id = I2C_HW_MPC107,
20739 + .algo_data = &i2c_mcf_board_data,
20740 + .class = I2C_CLASS_HWMON,
20741 + .timeout = 100,
20742 + .retries = 2
20743 +};
20744 +/*
20745 + * static void i2c_start()
20746 + *
20747 + * Generates START signal
20748 + */
20749 +static void
20750 +i2c_start(
20751 + struct i2c_algo_mcf_data *adap
20752 +) {
20753 + MCF_I2CR |= MCF_I2CR_MSTA;
20754 +}
20755 +
20756 +
20757 +/*
20758 + * static void i2c_stop()
20759 + *
20760 + * Generates STOP signal
20761 + */
20762 +static void
20763 +i2c_stop(
20764 + struct i2c_algo_mcf_data *adap
20765 +) {
20766 + MCF_I2CR &= ~MCF_I2CR_MSTA;
20767 +}
20768 +
20769 +static int
20770 +i2c_getack(
20771 + struct i2c_algo_mcf_data *adap
20772 +) {
20773 + return !(MCF_I2SR & MCF_I2SR_RXAK);
20774 +}
20775 +
20776 +/*
20777 + * static void i2c_repstart()
20778 + *
20779 + * Generates repeated start signal (without STOP while mastering the bus)
20780 + */
20781 +static void
20782 +i2c_repstart(
20783 + struct i2c_algo_mcf_data *adap
20784 +) {
20785 + MCF_I2CR |= MCF_I2CR_RSTA;
20786 + MCF_I2CR |= MCF_I2CR_MTX;
20787 +}
20788 +
20789 +
20790 +/*
20791 + * static void wait_for_bb()
20792 + *
20793 + * Wait for bus idle state
20794 + */
20795 +static int
20796 +wait_for_bb(
20797 + struct i2c_algo_mcf_data *adap
20798 +) {
20799 + int i;
20800 + for (i = 0; i < adap->timeout; i++) {
20801 + if (!(MCF_I2SR & MCF_I2SR_IBB))
20802 + return 0;
20803 + udelay(100);
20804 + }
20805 + printk(KERN_ERR "%s: timeout", __FUNCTION__);
20806 + return -ETIMEDOUT;
20807 +}
20808 +
20809 +/*
20810 + * static void wait_for_not_bb()
20811 + *
20812 + * Wait for bus busy state
20813 + */
20814 +static int
20815 +wait_for_not_bb(
20816 + struct i2c_algo_mcf_data *adap
20817 +) {
20818 + int i;
20819 + for (i = 0; i < adap->timeout; i++) {
20820 + if (MCF_I2SR & MCF_I2SR_IBB)
20821 + return 0;
20822 + udelay(100);
20823 + }
20824 + printk(KERN_ERR "%s: timeout", __FUNCTION__);
20825 + return -ETIMEDOUT;
20826 +}
20827 +
20828 +/*
20829 + * static void wait_xfer_done()
20830 + *
20831 + * Wait for transfer to complete
20832 + */
20833 +static int
20834 +wait_xfer_done(
20835 + struct i2c_algo_mcf_data *adap
20836 +) {
20837 + int i;
20838 +
20839 + for (i = 0; i < adap->timeout; i++) {
20840 + if (MCF_I2SR & MCF_I2SR_IIF) {
20841 + MCF_I2SR &= ~MCF_I2SR_IIF;
20842 + return 0;
20843 + }
20844 + udelay(10);
20845 + }
20846 + printk(KERN_ERR "%s: timeout", __FUNCTION__);
20847 + return -ETIMEDOUT;
20848 +}
20849 +
20850 +
20851 +/*
20852 + * static void i2c_set_addr()
20853 + *
20854 + * Sets slave address to communicate
20855 + */
20856 +static int
20857 +i2c_set_addr(
20858 + struct i2c_algo_mcf_data *adap,
20859 + struct i2c_msg *msg,
20860 + int retries
20861 +) {
20862 + unsigned short flags = msg->flags;
20863 + unsigned char addr;
20864 + MCF_I2CR |= MCF_I2CR_MTX;
20865 + if ((flags & I2C_M_TEN)) {
20866 + /* 10 bit address not supported yet */
20867 + return -EIO;
20868 + } else {
20869 + /* normal 7bit address */
20870 + addr = (msg->addr << 1);
20871 + if (flags & I2C_M_RD)
20872 + addr |= 1;
20873 + if (flags & I2C_M_REV_DIR_ADDR)
20874 + addr ^= 1;
20875 +
20876 + MCF_I2DR = addr;
20877 + }
20878 + return 0;
20879 +}
20880 +
20881 +
20882 +/*
20883 + * static void mcf_i2c_init()
20884 + *
20885 + * Perform ColdFire i2c initialization
20886 + */
20887 +static void
20888 +mcf_i2c_init(struct i2c_algo_mcf_data *adap)
20889 +{
20890 + u8 dummy;
20891 + /* Setup GPIO lines */
20892 + MCF_PAR_FECI2CIRQ |= MCF_PAR_SDA;
20893 + MCF_PAR_FECI2CIRQ |= MCF_PAR_SCL;
20894 +
20895 + /* Ensure slaves are in idle state */
20896 + if (MCF_I2SR & MCF_I2SR_IBB) {
20897 + MCF_I2ICR = 0x00;
20898 + MCF_I2CR = 0x00;
20899 + MCF_I2CR = 0x0A;
20900 + dummy = MCF_I2DR;
20901 + MCF_I2SR = 0x00;
20902 + MCF_I2CR = 0x00;
20903 + MCF_I2ICR = 0x01;
20904 + }
20905 +
20906 + /* setup SCL clock */
20907 + MCF_I2FDR = get_clock(adap);
20908 +
20909 + /* set slave address */
20910 + MCF_I2AR = get_own(adap);
20911 +
20912 + /* enable I2C module */
20913 + MCF_I2CR = MCF_I2CR_IEN;
20914 +}
20915 +
20916 +static int i2c_outb(
20917 + struct i2c_adapter *i2c_adap,
20918 + char c
20919 +) {
20920 +
20921 + struct i2c_algo_mcf_data *adap = i2c_adap->algo_data;
20922 + int timeout;
20923 + /* Put data to be sent */
20924 + MCF_I2DR = c;
20925 + /* Wait for xfer completed*/
20926 + timeout = wait_xfer_done(adap);
20927 + if (timeout) {
20928 + i2c_stop(adap);
20929 + wait_for_bb(adap);
20930 + printk(KERN_ERR "i2c-algo-mcf: %s i2c_write: "
20931 + "error - timeout.\n", i2c_adap->name);
20932 + return -EREMOTEIO; /* got a better one ?? */
20933 + }
20934 +
20935 + return 0;
20936 +}
20937 +
20938 +
20939 +/*
20940 + * static void mcf_sendbytes()
20941 + *
20942 + * Perform tx data transfer
20943 + */
20944 +static int
20945 +mcf_sendbytes(
20946 + struct i2c_adapter *i2c_adap,
20947 + const char *buf,
20948 + int count, int last
20949 +) {
20950 + struct i2c_algo_mcf_data *adap = i2c_adap->algo_data;
20951 + int ret, i;
20952 +
20953 + /* Set master TX mode */
20954 + MCF_I2CR |= MCF_I2CR_MTX;
20955 +
20956 + for (i = 0; i < count; ++i) {
20957 + printk(KERN_DEBUG "i2c-algo-mcf: %s i2c_write: writing %2.2X\n",
20958 + i2c_adap->name, buf[i]&0xff);
20959 + ret = i2c_outb(i2c_adap, buf[i]);
20960 + if (ret < 0)
20961 + return ret;
20962 + }
20963 + if (last) {
20964 + i2c_stop(adap);
20965 + wait_for_bb(adap);
20966 + } else {
20967 + /* i2c_repstart(adap);*/
20968 + }
20969 +
20970 + return (i);
20971 +}
20972 +
20973 +
20974 +/*
20975 + * static void mcf_readbytes()
20976 + *
20977 + * Perform rx data transfer
20978 + */
20979 +static int
20980 +mcf_readbytes(
20981 + struct i2c_adapter *i2c_adap,
20982 + char *buf,
20983 + int count, int last
20984 +) {
20985 + int i;
20986 + struct i2c_algo_mcf_data *adap = i2c_adap->algo_data;
20987 + u8 dummy;
20988 +
20989 + /* Set master RX mode */
20990 + MCF_I2CR &= ~MCF_I2CR_MTX;
20991 + MCF_I2CR &= ~MCF_I2CR_TXAK;
20992 + dummy = MCF_I2DR;
20993 +
20994 + for (i = 0; i < count-1; i++) {
20995 + if (wait_xfer_done(adap)) {
20996 + i2c_stop(adap);
20997 + wait_for_bb(adap);
20998 + printk(KERN_DEBUG
20999 + "i2c-algo-mcf: mcf_readbytes timed out.\n");
21000 + return (-1);
21001 + }
21002 +
21003 + /* store next data byte */
21004 + buf[i] = MCF_I2DR;
21005 + }
21006 +
21007 + if (wait_xfer_done(adap)) {
21008 + i2c_stop(adap);
21009 + wait_for_bb(adap);
21010 + printk(KERN_DEBUG "i2c-algo-mcf: mcf_readbytes timed out.\n");
21011 + return (-1);
21012 + }
21013 +
21014 + /* Disable acknowlege (set I2CR.TXAK) */
21015 + MCF_I2CR |= MCF_I2CR_TXAK;
21016 + buf[i] = MCF_I2DR;
21017 + if (wait_xfer_done(adap)) {
21018 + i2c_stop(adap);
21019 + wait_for_bb(adap);
21020 + printk(KERN_DEBUG "i2c-algo-mcf: mcf_readbytes timed out.\n");
21021 + return (-1);
21022 + }
21023 +
21024 + if (last) {
21025 + i2c_stop(adap);
21026 + wait_for_bb(adap);
21027 + } else {
21028 + /* i2c_repstart(adap);*/
21029 + }
21030 +
21031 + return (i+1);
21032 +}
21033 +
21034 +
21035 +/*
21036 + * static void mcf_xfer()
21037 + *
21038 + * Perform master data I/O transfer
21039 + */
21040 +static int
21041 +mcf_xfer(
21042 + struct i2c_adapter *i2c_adap,
21043 + struct i2c_msg *msgs,
21044 + int num
21045 +) {
21046 + struct i2c_algo_mcf_data *adap = i2c_adap->algo_data;
21047 + struct i2c_msg *pmsg;
21048 + int i;
21049 + int ret = 0, timeout;
21050 +
21051 + /* Skip own address */
21052 + if (get_own(adap) == (msgs[0].addr << 1))
21053 + return -EIO;
21054 +
21055 + /* Ensure slaves are in idle state */
21056 + if (MCF_I2SR & MCF_I2SR_IBB) {
21057 + MCF_I2ICR = 0x00;
21058 + MCF_I2CR = 0x00;
21059 + MCF_I2CR = 0x0A;
21060 + timeout = MCF_I2DR;
21061 + MCF_I2SR = 0x00;
21062 + MCF_I2CR = 0x00;
21063 + MCF_I2ICR = 0x01;
21064 + }
21065 + /* setup SCL clock */
21066 + MCF_I2FDR = get_clock(adap);
21067 + /* set slave address */
21068 + MCF_I2AR = get_own(adap);
21069 + /* enable I2C module */
21070 + MCF_I2CR = MCF_I2CR_IEN;
21071 +
21072 + MCF_I2CR |= MCF_I2CR_TXAK;
21073 +
21074 + /* Check for bus busy */
21075 + wait_for_bb(adap);
21076 +
21077 + for (i = 0; ret >= 0 && i < num; i++) {
21078 + if (MCF_I2SR & MCF_I2SR_IBB) {
21079 + MCF_I2ICR = 0x00;
21080 + MCF_I2CR = 0x00;
21081 + MCF_I2CR = 0x0A;
21082 + timeout = MCF_I2DR;
21083 + MCF_I2SR = 0x00;
21084 + MCF_I2CR = 0x00;
21085 + MCF_I2ICR = 0x01;
21086 + }
21087 + /* setup SCL clock */
21088 + MCF_I2FDR = get_clock(adap);
21089 + /* set slave address */
21090 + MCF_I2AR = get_own(adap);
21091 + /* enable I2C module */
21092 + MCF_I2CR = MCF_I2CR_IEN;
21093 +
21094 + MCF_I2CR |= MCF_I2CR_TXAK;
21095 +
21096 + /* Check for bus busy */
21097 + wait_for_bb(adap);
21098 +
21099 + pmsg = &msgs[i];
21100 +
21101 + printk(KERN_DEBUG "i2c-algo-mcf: Doing %s %d bytes "
21102 + "to 0x%02x - %d of %d messages\n",
21103 + pmsg->flags & I2C_M_RD ? "read" : "write",
21104 + pmsg->len, pmsg->addr, i + 1, num);
21105 +
21106 + /* Send START */
21107 + /*if (i == 0)*/
21108 + i2c_start(adap);
21109 +
21110 + /* Wait for Bus Busy */
21111 + wait_for_not_bb(adap);
21112 +
21113 + MCF_I2CR |= MCF_I2CR_MTX;
21114 +
21115 + ret = i2c_set_addr(adap, pmsg, i2c_adap->retries);
21116 + if (ret < 0)
21117 + return ret;
21118 +
21119 + /* Wait for address transfer completion */
21120 + wait_xfer_done(adap);
21121 +
21122 + /* Check for ACK */
21123 + if (!i2c_getack(adap)) {
21124 + i2c_stop(adap);
21125 + wait_for_bb(adap);
21126 + printk(KERN_DEBUG "i2c-algo-mcf: No ack after "
21127 + "send address in mcf_xfer\n");
21128 + return (-EREMOTEIO);
21129 + }
21130 +
21131 + printk(KERN_DEBUG "i2c-algo-mcf: Msg %d, "
21132 + "addr = 0x%x, flags = 0x%x, len = %d\n",
21133 + i, msgs[i].addr, msgs[i].flags, msgs[i].len);
21134 + /* Read */
21135 + if (pmsg->flags & I2C_M_RD) {
21136 + /* read bytes into buffer*/
21137 + ret = mcf_readbytes(i2c_adap, pmsg->buf, pmsg->len,
21138 + (i + 1 == num));
21139 +
21140 + if (ret != pmsg->len) {
21141 + printk(KERN_DEBUG "i2c-algo-mcf: fail: "
21142 + "only read %d bytes.\n", ret);
21143 + } else {
21144 + printk(KERN_DEBUG "i2c-algo-mcf: "
21145 + "read %d bytes.\n", ret);
21146 + }
21147 + } else {
21148 + /* write bytes into buffer*/
21149 + ret = mcf_sendbytes(i2c_adap, pmsg->buf, pmsg->len,
21150 + (i + 1 == num));
21151 + if (ret != pmsg->len) {
21152 + printk(KERN_DEBUG "i2c-algo-mcf: fail: "
21153 + "only wrote %d bytes.\n", ret);
21154 + } else {
21155 + printk(KERN_DEBUG "i2c-algo-mcf: wrote"
21156 + "%d bytes.\n", ret);
21157 + }
21158 + }
21159 + MCF_I2CR = 0;
21160 + }
21161 +
21162 + /* Disable I2C module */
21163 + MCF_I2CR = 0;
21164 + return (i);
21165 +}
21166 +
21167 +
21168 +/*
21169 + * static void mcf_func()
21170 + *
21171 + * Return algorithm funtionality
21172 + */
21173 +static u32
21174 +mcf_func(
21175 + struct i2c_adapter *i2c_adap
21176 +) {
21177 + return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C;
21178 +}
21179 +
21180 +/*
21181 + * ColdFire bus algorithm callbacks
21182 + */
21183 +static struct i2c_algorithm mcf_algo = {
21184 + .master_xfer = mcf_xfer,
21185 + .functionality = mcf_func,
21186 +};
21187 +
21188 +/***********************************************************/
21189 +struct coldfire_i2c {
21190 + void __iomem *base;
21191 + struct resource *irqarea;
21192 + struct resource *ioarea;
21193 + u32 irq;
21194 + struct i2c_adapter *adap;
21195 + u32 flags;
21196 +};
21197 +
21198 +/*
21199 + * registering functions to load algorithms at runtime
21200 + */
21201 +int i2c_mcf_add_bus(struct i2c_adapter *adap)
21202 +{
21203 + struct i2c_algo_mcf_data *mcf_adap = adap->algo_data;
21204 +
21205 + /*adap->id |= mcf_algo.id;*/
21206 + adap->algo = &mcf_algo;
21207 + adap->timeout = 100;
21208 +
21209 + mcf_i2c_init(mcf_adap);
21210 +
21211 +#ifdef MODULE
21212 + MOD_INC_USE_COUNT;
21213 +#endif
21214 +
21215 + i2c_add_adapter(adap);
21216 +
21217 + return 0;
21218 +}
21219 +
21220 +static int mcf548x_i2c_probe(struct platform_device *pdev)
21221 +{
21222 + struct coldfire_i2c *i2c;
21223 + int rc = 0;
21224 +
21225 + /************************************************************/
21226 + i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
21227 + if (!i2c) {
21228 + printk(KERN_ERR "%s kzalloc coldfire_i2c faile\n",
21229 + __FUNCTION__);
21230 + return -ENOMEM;
21231 + }
21232 + /****************************************************************/
21233 + platform_set_drvdata(pdev, i2c);
21234 +
21235 + i2c->adap = &i2c_mcf_board_adapter;
21236 + i2c->adap->dev.parent = &pdev->dev;
21237 + rc = i2c_mcf_add_bus(i2c->adap);
21238 + if (rc < 0) {
21239 + printk(KERN_ERR "%s - failed to add adapter\n", __FUNCTION__);
21240 + rc = -ENODEV;
21241 + goto fail_add;
21242 + }
21243 +
21244 + printk(KERN_INFO "i2c-algo-mcf.o: I2C ColdFire algorithm"
21245 + " module is loaded.\n");
21246 + return rc;
21247 +
21248 +fail_add:
21249 + kfree(i2c);
21250 + return rc;
21251 +};
21252 +
21253 +static int mcf548x_i2c_remove(struct platform_device *pdev)
21254 +{
21255 + struct coldfire_i2c *i2c = platform_get_drvdata(pdev);
21256 +
21257 + i2c_del_adapter(i2c->adap);
21258 + platform_set_drvdata(pdev, NULL);
21259 + iounmap(i2c->base);
21260 + kfree(i2c);
21261 + return 0;
21262 +};
21263 +
21264 +/* Structure for a device driver */
21265 +static struct platform_driver mcf548x_i2c_driver = {
21266 + .probe = mcf548x_i2c_probe,
21267 + .remove = mcf548x_i2c_remove,
21268 + .driver = {
21269 + .owner = THIS_MODULE,
21270 + .name = "MCF548X-i2c",
21271 + },
21272 +};
21273 +
21274 +static int __init coldfire_i2c_init(void)
21275 +{
21276 + return platform_driver_register(&mcf548x_i2c_driver);
21277 +}
21278 +
21279 +static void __exit coldfire_i2c_exit(void)
21280 +{
21281 + platform_driver_unregister(&mcf548x_i2c_driver);
21282 +}
21283 +
21284 +module_init(coldfire_i2c_init);
21285 +module_exit(coldfire_i2c_exit);
21286 +
21287 +MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
21288 +MODULE_DESCRIPTION
21289 + ("I2C-Bus adapter for MCF547x and MCF548x processors");
21290 +MODULE_LICENSE("GPL");
21291 --- /dev/null
21292 +++ b/drivers/i2c/busses/i2c-mcf.c
21293 @@ -0,0 +1,573 @@
21294 +/*
21295 + i2c-mcf.c - Part of lm_sensors, Linux kernel modules for hardware monitoring
21296 +
21297 + Copyright (c) 2005, Derek CL Cheung <derek.cheung@sympatico.ca>
21298 + <http://www3.sympatico.ca/derek.cheung>
21299 +
21300 + Copyright (c) 2006-2007, emlix
21301 + Sebastian Hess <sh@emlix.com>
21302 +
21303 + Copyright (c) 2006-2007 Freescale Semiconductor, Inc
21304 + Yaroslav Vinogradov <yaroslav.vinogradov@freescale.com>
21305 + Matt Waddel <Matt.Waddel@freescale.com>
21306 +
21307 + This program is free software; you can redistribute it and/or modify
21308 + it under the terms of the GNU General Public License as published by
21309 + the Free Software Foundation; either version 2 of the License, or
21310 + (at your option) any later version.
21311 +
21312 + This program is distributed in the hope that it will be useful,
21313 + but WITHOUT ANY WARRANTY; without even the implied warranty of
21314 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21315 + GNU General Public License for more details.
21316 +
21317 + You should have received a copy of the GNU General Public License
21318 + along with this program; if not, write to the Free Software
21319 + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21320 +
21321 + Changes:
21322 + v0.1 26 March 2005
21323 + Initial Release - developed on uClinux with 2.6.9 kernel
21324 +
21325 + v0.2 29 May 2006
21326 + Modified to be more generic and added support for
21327 + i2c_master_xfer
21328 +
21329 + This I2C adaptor supports the ColdFire CPU I2C module. Since most Coldfire
21330 + CPUs' I2C module use the same register set (e.g., MCF5249), the code is very
21331 + portable and re-usable to other Coldfire CPUs.
21332 +
21333 + The transmission frequency is set at about 100KHz for the CPU board with
21334 + 8MHz crystal. If the CPU board uses different system clock frequency, you
21335 + should change the following line:
21336 + static int __init i2c_coldfire_init(void)
21337 + {
21338 + .........
21339 + // Set transmission frequency 0x15 = ~100kHz
21340 + *MCF_I2C_I2FDR = 0x15;
21341 + ........
21342 + }
21343 +
21344 + Remember to perform a dummy read to set the ColdFire CPU's I2C module for
21345 + read before reading the actual byte from a device
21346 +
21347 + The I2C_SM_BUS_BLOCK_DATA function are not yet ready but most lm_senors
21348 + do not care
21349 +*/
21350 +
21351 +#include <linux/init.h>
21352 +#include <linux/module.h>
21353 +#include <linux/kernel.h>
21354 +#include <linux/errno.h>
21355 +#include <linux/i2c.h>
21356 +#include <linux/delay.h>
21357 +#include <linux/string.h>
21358 +#include <asm/coldfire.h>
21359 +#include <asm/mcfsim.h>
21360 +#include <asm/types.h>
21361 +#include <linux/platform_device.h>
21362 +#include "i2c-mcf.h"
21363 +
21364 +
21365 +static struct i2c_algorithm coldfire_algorithm = {
21366 + /*.name = "ColdFire I2C algorithm",
21367 + .id = I2C_ALGO_SMBUS,*/
21368 + .smbus_xfer = coldfire_i2c_access,
21369 + .master_xfer = coldfire_i2c_master,
21370 + .functionality = coldfire_func,
21371 +};
21372 +
21373 +
21374 +static struct i2c_adapter coldfire_adapter = {
21375 + .owner = THIS_MODULE,
21376 + .class = I2C_CLASS_HWMON,
21377 + .algo = &coldfire_algorithm,
21378 + .name = "ColdFire I2C adapter",
21379 +};
21380 +
21381 +
21382 +__u16 lastaddr;
21383 +__u16 lastop;
21384 +
21385 +static inline int coldfire_do_first_start(__u16 addr,__u16 flags)
21386 +{
21387 + int err;
21388 + /*
21389 + * Generate a stop and put the I2C module into slave mode
21390 + */
21391 + *MCF_I2C_I2CR &= ~MCF_I2C_I2CR_MSTA;
21392 +
21393 + /*
21394 + * Generate a new Start signal
21395 + */
21396 + err = coldfire_i2c_start(flags & I2C_M_RD ? I2C_SMBUS_READ : I2C_SMBUS_WRITE,
21397 + addr, FIRST_START);
21398 + if(err) return err;
21399 +
21400 + lastaddr = addr;
21401 + lastop = flags & I2C_M_RD; /* Ensure everything for new start */
21402 + return 0;
21403 +}
21404 +
21405 +
21406 +/*
21407 + * read one byte data from the I2C bus
21408 + */
21409 +static int coldfire_read_data(u8 * const rxData, const enum I2C_ACK_TYPE ackType) {
21410 +
21411 + int timeout;
21412 +
21413 + *MCF_I2C_I2CR &= ~MCF_I2C_I2CR_MTX; /* master receive mode*/
21414 +
21415 + if (ackType == NACK)
21416 + *MCF_I2C_I2CR |= MCF_I2C_I2CR_TXAK; /* generate NA */
21417 + else
21418 + *MCF_I2C_I2CR &= ~MCF_I2C_I2CR_TXAK; /* generate ACK */
21419 +
21420 +
21421 + /* read data from the I2C bus */
21422 + *rxData = *MCF_I2C_I2DR;
21423 +
21424 + /* printk(">>> %s I2DR data is %.2x \n", __FUNCTION__, *rxData); */
21425 +
21426 + /* wait for data transfer to complete */
21427 + timeout = 500;
21428 + while (timeout-- && !(*MCF_I2C_I2SR & MCF_I2C_I2SR_IIF))
21429 + udelay(1);
21430 + if (timeout <= 0)
21431 + printk("%s - I2C IIF never set. Timeout is %d \n", __FUNCTION__,
21432 + timeout);
21433 +
21434 +
21435 + /* reset the interrupt bit */
21436 + *MCF_I2C_I2SR &= ~MCF_I2C_I2SR_IIF;
21437 +
21438 + if (timeout <= 0 )
21439 + return -1;
21440 + else
21441 + return 0;
21442 +
21443 +};
21444 +
21445 +
21446 +/*
21447 + * write one byte data onto the I2C bus
21448 + */
21449 +static int coldfire_write_data(const u8 txData) {
21450 +
21451 + int timeout;
21452 +
21453 + timeout = 500;
21454 +
21455 + *MCF_I2C_I2CR |= MCF_I2C_I2CR_MTX; /* I2C module into TX mode */
21456 + *MCF_I2C_I2DR = txData; /* send the data */
21457 +
21458 + /* wait for data transfer to complete */
21459 + /* rely on the interrupt handling bit */
21460 + timeout = 500;
21461 + while (timeout-- && !(*MCF_I2C_I2SR & MCF_I2C_I2SR_IIF))
21462 + udelay(1);
21463 + if (timeout <=0)
21464 + printk("%s - I2C IIF never set. Timeout is %d \n", __FUNCTION__,
21465 + timeout);
21466 +
21467 +
21468 + /* reset the interrupt bit */
21469 + *MCF_I2C_I2SR &= ~MCF_I2C_I2SR_IIF;
21470 +
21471 + if (timeout <= 0 )
21472 + return -1;
21473 + else
21474 + return 0;
21475 +
21476 +};
21477 +
21478 +
21479 +
21480 +
21481 +/*
21482 + * Generate I2C start or repeat start signal
21483 + * Combine the 7 bit target_address and the R/W bit and put it onto the I2C bus
21484 + */
21485 +static int coldfire_i2c_start(const char read_write, const u16 target_address, const enum I2C_START_TYPE start_type) {
21486 +
21487 + int timeout;
21488 +
21489 + /* printk(">>> %s START TYPE %s \n", __FUNCTION__,
21490 + start_type == FIRST_START ? "FIRST_START":"REPEAT_START");*/
21491 +
21492 + *MCF_I2C_I2CR |= MCF_I2C_I2CR_IEN;
21493 +
21494 + if (start_type == FIRST_START) {
21495 + /* Make sure the I2C bus is idle */
21496 + timeout = 500; /* 500us timeout */
21497 + while (timeout-- && (*MCF_I2C_I2SR & MCF_I2C_I2SR_IBB))
21498 + udelay(1);
21499 + if (timeout <= 0) {
21500 + printk("%s - I2C bus always busy in the past 500us timeout is %d \n", __FUNCTION__, timeout);
21501 + goto check_rc;
21502 + }
21503 + /* generate a START and put the I2C module into MASTER TX mode*/
21504 + *MCF_I2C_I2CR |= (MCF_I2C_I2CR_MSTA | MCF_I2C_I2CR_MTX);
21505 +
21506 + /* wait for bus busy to be set */
21507 + timeout = 500;
21508 + while (timeout-- && !(*MCF_I2C_I2SR & MCF_I2C_I2SR_IBB))
21509 + udelay(1);
21510 + if (timeout <= 0) {
21511 + printk("%s - I2C bus is never busy after START. Timeout is %d \n", __FUNCTION__, timeout);
21512 + goto check_rc;
21513 + }
21514 +
21515 + } else {
21516 + /* this is repeat START */
21517 + udelay(500); /* need some delay before repeat start */
21518 + *MCF_I2C_I2CR |= (MCF_I2C_I2CR_MSTA | MCF_I2C_I2CR_RSTA);
21519 + }
21520 +
21521 +
21522 + /* combine the R/W bit and the 7 bit target address and put it onto
21523 + the I2C bus */
21524 + *MCF_I2C_I2DR = ((target_address & 0x7F) << 1) | (read_write == I2C_SMBUS_WRITE ? 0x00 : 0x01);
21525 +
21526 + /* wait for bus transfer to complete */
21527 + /* when one byte transfer is completed, IIF set at the faling edge of
21528 + the 9th clock */
21529 + timeout = 500;
21530 + while (timeout-- && !(*MCF_I2C_I2SR & MCF_I2C_I2SR_IIF))
21531 + udelay(1);
21532 + if (timeout <= 0)
21533 + printk("%s - I2C IIF never set. Timeout is %d \n", __FUNCTION__, timeout);
21534 +
21535 +
21536 +check_rc:
21537 + /* reset the interrupt bit */
21538 + *MCF_I2C_I2SR &= ~MCF_I2C_I2SR_IIF;
21539 +
21540 + if (timeout <= 0)
21541 + return -1;
21542 + else
21543 + return 0;
21544 +};
21545 +
21546 +
21547 +/*
21548 + * 5282 SMBUS supporting functions
21549 + */
21550 +
21551 +static s32 coldfire_i2c_access(struct i2c_adapter *adap, u16 addr,
21552 + unsigned short flags, char read_write,
21553 + u8 command, int size, union i2c_smbus_data *data)
21554 +{
21555 + int rc = 0;
21556 + u8 rxData, tempRxData[2];
21557 +
21558 + switch (size) {
21559 + case I2C_SMBUS_QUICK:
21560 + rc = coldfire_i2c_start(read_write, addr, FIRST_START); /* generate START */
21561 + break;
21562 + case I2C_SMBUS_BYTE:
21563 + rc = coldfire_i2c_start(read_write, addr, FIRST_START);
21564 + *MCF_I2C_I2CR |= MCF_I2C_I2CR_TXAK; /*generate NA */
21565 + if (read_write == I2C_SMBUS_WRITE)
21566 + rc += coldfire_write_data(command);
21567 + else {
21568 + coldfire_read_data(&rxData, NACK);/*dummy read*/
21569 + rc += coldfire_read_data(&rxData, NACK);
21570 + data->byte = rxData;
21571 + }
21572 + *MCF_I2C_I2CR &= ~MCF_I2C_I2CR_TXAK; /* reset ACK bit */
21573 + break;
21574 + case I2C_SMBUS_BYTE_DATA:
21575 + rc = coldfire_i2c_start(I2C_SMBUS_WRITE, addr, FIRST_START);
21576 + rc += coldfire_write_data(command);
21577 + if (read_write == I2C_SMBUS_WRITE)
21578 + rc += coldfire_write_data(data->byte);
21579 + else {
21580 + /* This is SMBus READ Byte Data Request.
21581 + Perform REPEAT START */
21582 + rc += coldfire_i2c_start(I2C_SMBUS_READ, addr,
21583 + REPEAT_START);
21584 + coldfire_read_data(&rxData, ACK);/* dummy read*/
21585 + /* Disable Acknowledge, generate STOP after
21586 + next byte transfer */
21587 + rc += coldfire_read_data(&rxData, NACK);
21588 + data->byte = rxData;
21589 + }
21590 + *MCF_I2C_I2CR &= ~MCF_I2C_I2CR_TXAK;/* reset to normal ACk */
21591 + break;
21592 + case I2C_SMBUS_PROC_CALL:
21593 + case I2C_SMBUS_WORD_DATA:
21594 + dev_info(&adap->dev, "size = I2C_SMBUS_WORD_DATA \n");
21595 + rc = coldfire_i2c_start(I2C_SMBUS_WRITE, addr,
21596 + FIRST_START);
21597 + rc += coldfire_write_data(command);
21598 + if (read_write == I2C_SMBUS_WRITE) {
21599 + rc += coldfire_write_data(data->word & 0x00FF);
21600 + rc += coldfire_write_data((data->word & 0x00FF) >> 8);
21601 + } else {
21602 + /* This is SMBUS READ WORD request.
21603 + Peform REPEAT START */
21604 + rc += coldfire_i2c_start(I2C_SMBUS_READ, addr,
21605 + REPEAT_START);
21606 + coldfire_read_data(&rxData, ACK);/* dummy read*/
21607 + /* Disable Acknowledge, generate STOP after
21608 + next byte transfer */
21609 + /* read the MS byte from the device */
21610 + rc += coldfire_read_data(&rxData, NACK);
21611 + tempRxData[1] = rxData;
21612 + /* read the LS byte from the device */
21613 + rc += coldfire_read_data(&rxData, NACK);
21614 + tempRxData[0] = rxData;
21615 + /* the host driver expect little endian
21616 + convention. Swap the byte */
21617 + data->word = (tempRxData[0] << 8)|tempRxData[1];
21618 + }
21619 + *MCF_I2C_I2CR &= ~MCF_I2C_I2CR_TXAK;
21620 + break;
21621 + case I2C_SMBUS_BLOCK_DATA:
21622 + /* Not done yet */
21623 + break;
21624 + default:
21625 + printk("Unsupported I2C size \n");
21626 + rc = -1;
21627 + break;
21628 + };
21629 +
21630 + /* Generate a STOP and put I2C module into slave mode */
21631 + *MCF_I2C_I2CR &= ~MCF_I2C_I2CR_MSTA;
21632 +
21633 + /* restore interrupt */
21634 + *MCF_I2C_I2CR |= MCF_I2C_I2CR_IIEN;
21635 +
21636 + if (rc < 0)
21637 + return -1;
21638 + else
21639 + return 0;
21640 +};
21641 +
21642 +
21643 +/*
21644 + * List the SMBUS functions supported by this I2C adaptor
21645 + * Also tell the I2C Subsystem that we are able of master_xfer()
21646 + */
21647 +static u32 coldfire_func(struct i2c_adapter *adapter)
21648 +{
21649 + return(I2C_FUNC_SMBUS_QUICK |
21650 + I2C_FUNC_SMBUS_BYTE |
21651 + I2C_FUNC_SMBUS_PROC_CALL |
21652 + I2C_FUNC_SMBUS_BYTE_DATA |
21653 + I2C_FUNC_SMBUS_WORD_DATA |
21654 + I2C_FUNC_I2C |
21655 + I2C_FUNC_SMBUS_BLOCK_DATA);
21656 +};
21657 +
21658 +static int coldfire_i2c_master(struct i2c_adapter *adap,struct i2c_msg *msgs,
21659 + int num)
21660 +{
21661 + u8 dummyRead;
21662 + struct i2c_msg *p;
21663 + int i, err = 0;
21664 + int ic=0;
21665 +
21666 + lastaddr = 0;
21667 + lastop = 8;
21668 +
21669 + /* disable the IRQ, we are doing polling */
21670 + *MCF_I2C_I2CR &= ~MCF_I2C_I2CR_IIEN;
21671 +
21672 + dev_dbg(&adap->dev,"Num of actions: %d\n", num);
21673 +
21674 + for (i = 0; !err && i < num; i++) {
21675 + p = &msgs[i];
21676 +
21677 +
21678 + if (!p->len)
21679 + {
21680 + dev_dbg(&adap->dev,"p->len == 0!\n");
21681 + continue;
21682 + }
21683 + /*
21684 + * Generate a new Start, if the target address differs from
21685 + * the last target, generate a stop in this case first
21686 + */
21687 + if(p->addr != lastaddr)
21688 + {
21689 + err = coldfire_do_first_start(p->addr,p->flags);
21690 + if(err)
21691 + {
21692 + dev_dbg(&adap->dev,"First Init failed!\n");
21693 + break;
21694 + }
21695 + }
21696 +
21697 + else if((p->flags & I2C_M_RD) != lastop)
21698 + {
21699 + /*
21700 + * If the Operational Mode changed, we need to do this
21701 + * here ...
21702 + */
21703 + dev_dbg(&adap->dev,"%s(): Direction changed, was: %d; is now: %d\n", __FUNCTION__, lastop, p->flags & I2C_M_RD);
21704 +
21705 + /* Last op was an read, now it's write: complete stop
21706 + and reinit */
21707 + if (lastop & I2C_M_RD)
21708 + {
21709 + dev_dbg(&adap->dev,"%s(): The device is in read state, we must reset!\n", __FUNCTION__);
21710 + if((err = coldfire_do_first_start(p->addr,p->flags)))
21711 + break;
21712 + }
21713 + else
21714 + {
21715 + dev_dbg(&adap->dev,"%s(): We switchted to read mode\n",__FUNCTION__);
21716 + if((err = coldfire_i2c_start((p->flags & I2C_M_RD) ? I2C_SMBUS_READ : I2C_SMBUS_WRITE,
21717 + p->addr, REPEAT_START)))
21718 + break;
21719 + }
21720 +
21721 + lastop = p->flags & I2C_M_RD; /* Save the last op */
21722 + }
21723 +
21724 + if (p->flags & I2C_M_RD)
21725 + {
21726 + /*
21727 + * When ever we get here, a new session was activated,
21728 + * so read a dummy byte
21729 + */
21730 + coldfire_read_data(&dummyRead, ACK);
21731 + /*
21732 + * read p->len -1 bytes with ACK to the slave,
21733 + * read the last byte without the ACK, to inform him
21734 + * about the stop afterwards
21735 + */
21736 + ic = 0;
21737 + while(!err && (ic < p->len-1 ))
21738 + {
21739 + err = coldfire_read_data(p->buf+ic, ACK );
21740 + ic++;
21741 + }
21742 + if(!err)
21743 + err = coldfire_read_data(p->buf+ic, NACK);
21744 + dev_dbg(&coldfire_adapter.dev,"read: %2x\n",p->buf[ic]);
21745 + }
21746 + else
21747 + {
21748 + if(p->len == 2)
21749 + dev_dbg(&coldfire_adapter.dev,"writing: 0x %2x %2x\n", p->buf[0], p->buf[1]);
21750 +
21751 + /*
21752 + * Write data to the slave
21753 + */
21754 + for(ic=0; !err && ic < p->len; ic++)
21755 + {
21756 + err = coldfire_write_data(p->buf[ic]);
21757 + if(err)
21758 + {
21759 + dev_dbg(&coldfire_adapter.dev, "Failed to write data\n");
21760 + }
21761 + }
21762 + }
21763 + }
21764 +
21765 + /*
21766 + * Put the device into slave mode to enable the STOP Generation
21767 + * (the RTC needs this)
21768 + */
21769 + *MCF_I2C_I2CR &= ~MCF_I2C_I2CR_MSTA;
21770 +
21771 + *MCF_I2C_I2CR &= ~MCF_I2C_I2CR_TXAK; /* reset the ACK bit */
21772 +
21773 + /* restore interrupt */
21774 + *MCF_I2C_I2CR |= MCF_I2C_I2CR_IIEN;
21775 +
21776 + /* Return the number of messages processed, or the error code. */
21777 + if (err == 0)
21778 + err = num;
21779 + return err;
21780 +}
21781 +
21782 +
21783 +/*
21784 + * Initalize the 5282 I2C module
21785 + * Disable the 5282 I2C interrupt capability. Just use callback
21786 + */
21787 +
21788 +static int __init i2c_coldfire_init(void)
21789 +{
21790 + int retval;
21791 + u8 dummyRead;
21792 +
21793 +#if defined(CONFIG_M532x) || defined(CONFIG_M5445X)
21794 + /*
21795 + * Initialize the GPIOs for I2C
21796 + */
21797 + MCF_GPIO_PAR_FECI2C |= (0
21798 + | MCF_GPIO_PAR_FECI2C_PAR_SDA(3)
21799 + | MCF_GPIO_PAR_FECI2C_PAR_SCL(3));
21800 +#elif defined(CONFIG_M5253)
21801 + {
21802 + volatile u32 *reg;
21803 + /* GPIO Bit 41 = SCL0, Bit 42 = SDA0 */
21804 + reg = (volatile u32 *)(MCF_MBAR2 + MCFSIM2_GPIO1FUNC);
21805 + *reg &= 0xFFFFF9FF;
21806 + }
21807 +#else
21808 + /* Initialize PASP0 and PASP1 to I2C functions, 5282 user guide 26-19 */
21809 + /* Port AS Pin Assignment Register (PASPAR) */
21810 + /* PASPA1 = 11 = AS1 pin is I2C SDA */
21811 + /* PASPA0 = 11 = AS0 pin is I2C SCL */
21812 + *MCF_GPIO_PASPAR |= 0x000F; /* u16 declaration */
21813 +#endif
21814 +
21815 +
21816 + /* Set transmission frequency 0x15 = ~100kHz */
21817 + *MCF_I2C_I2FDR = 0x15;
21818 +
21819 + /* set the 5282 I2C slave address though we never use it */
21820 + *MCF_I2C_I2ADR = 0x6A;
21821 +
21822 + /* Enable I2C module and if IBB is set, do the special initialzation */
21823 + /* procedures as are documented at the 5282 User Guide page 24-11 */
21824 + *MCF_I2C_I2CR |= MCF_I2C_I2CR_IEN;
21825 + if ((*MCF_I2C_I2SR & MCF_I2C_I2SR_IBB) == 1) {
21826 + printk("%s - do special 5282 I2C init procedures \n",
21827 + __FUNCTION__);
21828 + *MCF_I2C_I2CR = 0x00;
21829 + *MCF_I2C_I2CR = 0xA0;
21830 + dummyRead = *MCF_I2C_I2DR;
21831 + *MCF_I2C_I2SR = 0x00;
21832 + *MCF_I2C_I2CR = 0x00;
21833 + }
21834 +
21835 + /* default I2C mode is - slave and receive */
21836 + *MCF_I2C_I2CR &= ~(MCF_I2C_I2CR_MSTA | MCF_I2C_I2CR_MTX);
21837 +
21838 + coldfire_adapter.dev.parent = &platform_bus;
21839 + retval = i2c_add_adapter(&coldfire_adapter);
21840 +
21841 + if (retval < 0)
21842 + printk("%s - return code is: %d \n", __FUNCTION__, retval);
21843 +
21844 + return retval;
21845 +};
21846 +
21847 +
21848 +/*
21849 + * I2C module exit function
21850 + */
21851 +
21852 +static void __exit i2c_coldfire_exit(void)
21853 +{
21854 + /* disable I2C and Interrupt */
21855 + *MCF_I2C_I2CR &= ~(MCF_I2C_I2CR_IEN | MCF_I2C_I2CR_IIEN);
21856 + i2c_del_adapter(&coldfire_adapter);
21857 +
21858 +};
21859 +
21860 +
21861 +MODULE_AUTHOR("Derek CL Cheung <derek.cheung@sympatico.ca>");
21862 +MODULE_DESCRIPTION("MCF5282 I2C adaptor");
21863 +MODULE_LICENSE("GPL");
21864 +
21865 +module_init(i2c_coldfire_init);
21866 +module_exit(i2c_coldfire_exit);
21867 --- /dev/null
21868 +++ b/drivers/i2c/busses/i2c-mcf.h
21869 @@ -0,0 +1,75 @@
21870 +/*
21871 + i2c-mcf.h - header file for i2c-mcf.c
21872 +
21873 + Copyright (c) 2005, Derek CL Cheung <derek.cheung@sympatico.ca>
21874 + <http://www3.sympatico.ca/derek.cheung>
21875 +
21876 + Copyright (c) 2006-2007, emlix
21877 + Sebastian Hess <sh@emlix.com>
21878 +
21879 + Copyright (c) 2006-2007 Freescale Semiconductor, Inc
21880 + Yaroslav Vinogradov <yaroslav.vinogradov@freescale.com>
21881 + Matt Waddel <Matt.Waddel@freescale.com>
21882 +
21883 + This program is free software; you can redistribute it and/or modify
21884 + it under the terms of the GNU General Public License as published by
21885 + the Free Software Foundation; either version 2 of the License, or
21886 + (at your option) any later version.
21887 +
21888 + This program is distributed in the hope that it will be useful,
21889 + but WITHOUT ANY WARRANTY; without even the implied warranty of
21890 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21891 + GNU General Public License for more details.
21892 +
21893 + You should have received a copy of the GNU General Public License
21894 + along with this program; if not, write to the Free Software
21895 + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21896 +
21897 + Changes:
21898 + v0.1 26 March 2005
21899 + Initial Release - developed on uClinux with 2.6.9 kernel
21900 + v0.2 29 May 2006
21901 + Modified to be more generic and added support for
21902 + i2c_master_xfer
21903 +*/
21904 +
21905 +
21906 +#ifndef __I2C_MCF_H__
21907 +#define __I2C_MCF_H__
21908 +
21909 +enum I2C_START_TYPE { FIRST_START, REPEAT_START };
21910 +enum I2C_ACK_TYPE { ACK, NACK};
21911 +
21912 +/* Function prototypes */
21913 +static u32 coldfire_func(struct i2c_adapter *adapter);
21914 +static s32 coldfire_i2c_access(struct i2c_adapter *adap, u16 address,
21915 + unsigned short flags, char read_write,
21916 + u8 command, int size, union i2c_smbus_data *data);
21917 +static int coldfire_write_data(const u8 data);
21918 +static int coldfire_i2c_start(const char read_write, const u16 target_address, const enum I2C_START_TYPE i2c_start);
21919 +static int coldfire_read_data(u8 * const rxData, const enum I2C_ACK_TYPE ackType);
21920 +static int coldfire_i2c_master(struct i2c_adapter *adap,struct i2c_msg *msgs, int num);
21921 +void dumpReg(char *, u16 addr, u8 data);
21922 +
21923 +#define MCF_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01)
21924 +#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F))
21925 +
21926 +/* I2C Control Register */
21927 +#define MCF_I2C_I2CR_IEN (0x80) /* I2C enable */
21928 +#define MCF_I2C_I2CR_IIEN (0x40) /* interrupt enable */
21929 +#define MCF_I2C_I2CR_MSTA (0x20) /* master/slave mode */
21930 +#define MCF_I2C_I2CR_MTX (0x10) /* transmit/receive mode */
21931 +#define MCF_I2C_I2CR_TXAK (0x08) /* transmit acknowledge enable */
21932 +#define MCF_I2C_I2CR_RSTA (0x04) /* repeat start */
21933 +
21934 +/* I2C Status Register */
21935 +#define MCF_I2C_I2SR_ICF (0x80) /* data transfer bit */
21936 +#define MCF_I2C_I2SR_IAAS (0x40) /* I2C addressed as a slave */
21937 +#define MCF_I2C_I2SR_IBB (0x20) /* I2C bus busy */
21938 +#define MCF_I2C_I2SR_IAL (0x10) /* aribitration lost */
21939 +#define MCF_I2C_I2SR_SRW (0x04) /* slave read/write */
21940 +#define MCF_I2C_I2SR_IIF (0x02) /* I2C interrupt */
21941 +#define MCF_I2C_I2SR_RXAK (0x01) /* received acknowledge */
21942 +
21943 +/********************************************************************/
21944 +#endif /* __I2C_MCF_H__ */
21945 --- a/drivers/i2c/busses/Kconfig
21946 +++ b/drivers/i2c/busses/Kconfig
21947 @@ -4,6 +4,18 @@
21948
21949 menu "I2C Hardware Bus support"
21950
21951 +config I2C_MCF548x
21952 + tristate "I2C MCF547x/548x interfaces"
21953 + depends on I2C
21954 + help
21955 + This allows you to use the I2C adapters found on the Freescale
21956 + MCF547x/548x microcontrollers.
21957 + Say Y if you own an I2C adapter belonging to this class and then say
21958 + Y to the specific driver for you adapter below.
21959 +
21960 + This support is also available as a module. If so, the module
21961 + will be called i2c-algo-mcf.
21962 +
21963 config I2C_ALI1535
21964 tristate "ALI 1535"
21965 depends on PCI
21966 @@ -290,6 +302,16 @@ config I2C_POWERMAC
21967 This support is also available as a module. If so, the module
21968 will be called i2c-powermac.
21969
21970 +config I2C_MCF
21971 + tristate "MCF ColdFire"
21972 + depends on I2C && EXPERIMENTAL
21973 + help
21974 + If you say yes to this option, support will be included for the
21975 + I2C on most ColdFire CPUs
21976 +
21977 + This driver can also be built as a module. If so, the module
21978 + will be called i2c-mcf.
21979 +
21980 config I2C_MPC
21981 tristate "MPC107/824x/85xx/52xx/86xx"
21982 depends on PPC32
21983 --- a/drivers/i2c/busses/Makefile
21984 +++ b/drivers/i2c/busses/Makefile
21985 @@ -52,6 +52,8 @@ obj-$(CONFIG_I2C_VIAPRO) += i2c-viapro.o
21986 obj-$(CONFIG_I2C_VOODOO3) += i2c-voodoo3.o
21987 obj-$(CONFIG_SCx200_ACB) += scx200_acb.o
21988 obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o
21989 +obj-$(CONFIG_I2C_MCF548x) += i2c-mcf548x.o
21990 +obj-$(CONFIG_I2C_MCF) += i2c-mcf.o
21991
21992 ifeq ($(CONFIG_I2C_DEBUG_BUS),y)
21993 EXTRA_CFLAGS += -DDEBUG
21994 --- a/drivers/macintosh/Kconfig
21995 +++ b/drivers/macintosh/Kconfig
21996 @@ -118,7 +118,6 @@ config PMAC_SMU
21997
21998 config PMAC_APM_EMU
21999 tristate "APM emulation"
22000 - select APM_EMULATION
22001 depends on ADB_PMU && PM && PPC32
22002
22003 config PMAC_MEDIABAY
22004 --- a/drivers/Makefile
22005 +++ b/drivers/Makefile
22006 @@ -93,3 +93,5 @@ obj-$(CONFIG_PPC_PS3) += ps3/
22007 obj-$(CONFIG_OF) += of/
22008 obj-$(CONFIG_SSB) += ssb/
22009 obj-$(CONFIG_VIRTIO) += virtio/
22010 +
22011 +obj-$(CONFIG_MCD_DMA) += dma/
22012 --- /dev/null
22013 +++ b/drivers/net/can/flexcan/flexcan.c
22014 @@ -0,0 +1,378 @@
22015 +/*
22016 + * flexcan.c
22017 + *
22018 + * DESCRIPTION:
22019 + * CAN bus driver for the alone generic (as possible as) FLEXCAN controller.
22020 + *
22021 + * AUTHOR:
22022 + * Andrey Volkov <avolkov@varma-el.com>
22023 + *
22024 + * COPYRIGHT:
22025 + * 2005-2006, Varma Electronics Oy
22026 + *
22027 + * LICENCE:
22028 + * This program is free software; you can redistribute it and/or modify
22029 + * it under the terms of the GNU General Public License as published by
22030 + * the Free Software Foundation; either version 2 of the License, or
22031 + * (at your option) any later version.
22032 + *
22033 + * This program is distributed in the hope that it will be useful,
22034 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
22035 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22036 + * GNU General Public License for more details.
22037 + *
22038 + * You should have received a copy of the GNU General Public License
22039 + * along with this program; if not, write to the Free Software
22040 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22041 + *
22042 + * HISTORY:
22043 + * 2008-06-23 Support for MCF548x's FlexCAN
22044 + * Huan, Wang <b18965@freescale.com>
22045 + */
22046 +
22047 +
22048 +
22049 +#include <linux/kernel.h>
22050 +#include <linux/module.h>
22051 +#include <linux/interrupt.h>
22052 +#include <linux/delay.h>
22053 +#include <linux/netdevice.h>
22054 +#include <linux/if_arp.h>
22055 +#include <linux/if_ether.h>
22056 +#include <linux/can.h>
22057 +#include <linux/list.h>
22058 +#include <linux/io.h>
22059 +
22060 +#include <linux/can/dev.h>
22061 +#include <linux/can/error.h>
22062 +#include "flexcan.h"
22063 +#include <asm/coldfire.h>
22064 +#include <asm/m5485sim.h>
22065 +#include <linux/can/version.h> /* for RCSID. Removed by mkpatch script */
22066 +RCSID("$Id$");
22067 +
22068 +struct flexcan_priv {
22069 + struct can_priv can;
22070 + volatile unsigned long flags;
22071 + u8 shadow_statflg;
22072 + u8 shadow_canrier;
22073 + u8 cur_pri;
22074 + u8 tx_active;
22075 +
22076 + struct list_head tx_head;
22077 + struct napi_struct napi;
22078 + struct net_device *dev;
22079 +};
22080 +
22081 +
22082 +static int flexcan_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
22083 +{
22084 + struct can_frame *frame = (struct can_frame *)skb->data;
22085 + struct flexcan_regs *regs = (struct flexcan_regs *)dev->base_addr;
22086 + int i, len;
22087 + int txbuf = 0;
22088 + u32 can_id, can_ext, tmp, tmp1;
22089 +
22090 + /* Transmission inactive */
22091 + regs->cantxfg[txbuf].can_dlc = MB_CNT_CODE(0x08);
22092 +
22093 + can_ext = frame->can_id;
22094 + if (can_ext & CAN_EFF_FLAG) {
22095 + /* Frame format is extended */
22096 + regs->cantxfg[txbuf].can_dlc |= (1 << 21);
22097 + regs->cantxfg[txbuf].can_dlc |= (1 << 22);
22098 + can_id = frame->can_id & MB_ID_EXT;
22099 + if (frame->can_id & CAN_RTR_FLAG)
22100 + regs->cantxfg[txbuf].can_dlc |= (1 << 20);
22101 +
22102 + tmp = (can_id & CAN_SFF_MASK) << 18;
22103 + tmp1 = can_id >> 11;
22104 + can_id = tmp | tmp1;
22105 + regs->cantxfg[txbuf].can_id = can_id;
22106 + } else {
22107 + /* Frame format is standard */
22108 + can_id = frame->can_id & MB_ID_EXT;
22109 + if (frame->can_id & CAN_RTR_FLAG)
22110 + regs->cantxfg[txbuf].can_dlc |= (1 << 20);
22111 +
22112 + regs->cantxfg[txbuf].can_id = can_id << 18;
22113 + }
22114 +
22115 + len = 8;
22116 + for (i = 0; i < len; i++)
22117 + regs->cantxfg[txbuf].data[i] = frame->data[i];
22118 +
22119 + regs->cantxfg[txbuf].can_dlc |= len << 16;
22120 + /* Transmission active */
22121 + regs->cantxfg[txbuf].can_dlc |= MB_CNT_CODE(0x0c);
22122 + kfree_skb(skb);
22123 + return NETDEV_TX_OK;
22124 +}
22125 +
22126 +static void flexcan_tx_timeout(struct net_device *dev)
22127 +{
22128 + struct sk_buff *skb;
22129 + struct flexcan_regs *regs = (struct flexcan_regs *)dev->base_addr;
22130 + struct can_frame *frame;
22131 + int length = 8;
22132 +
22133 + /* Diable the interrupts */
22134 + regs->imask = IMASK_BUFF_DISABLE_ALL;
22135 +
22136 + skb = dev_alloc_skb(sizeof(struct can_frame));
22137 + if (!skb) {
22138 + if (printk_ratelimit())
22139 + dev_notice(ND2D(dev), "TIMEOUT packet dropped.\n");
22140 + return;
22141 + }
22142 + frame = (struct can_frame *)skb_put(skb, sizeof(struct can_frame));
22143 +
22144 + frame->can_dlc = length;
22145 +
22146 + skb->dev = dev;
22147 + skb->protocol = __constant_htons(ETH_P_CAN);
22148 + skb->pkt_type = PACKET_BROADCAST;
22149 + skb->ip_summed = CHECKSUM_UNNECESSARY;
22150 +
22151 + netif_rx(skb);
22152 +}
22153 +
22154 +static irqreturn_t flexcan_isr(int irq, void *dev_id)
22155 +{
22156 + struct net_device *dev = (struct net_device *)dev_id;
22157 + struct flexcan_regs *regs = (struct flexcan_regs *)dev->base_addr;
22158 + struct net_device_stats *stats = dev->get_stats(dev);
22159 + struct sk_buff *skb;
22160 + struct can_frame *frame;
22161 + u32 iflags, oflags;
22162 + int i, k;
22163 + int retval = 1;
22164 +
22165 + iflags = regs->iflag;
22166 + oflags = iflags;
22167 + for (i = 0; i < 16; i++) {
22168 + if (iflags & (0x01 << i)) {
22169 + struct flexcan_mb *mb = &regs->cantxfg[i];
22170 + int ctrl = mb->can_dlc;
22171 + int code = (ctrl >> 24) & 0x0f;
22172 + int length = (ctrl >> 16) & 0x0f;
22173 + u32 tmp, tmp1;
22174 +
22175 + if (code < 8 && (length > 0)) {
22176 + /* receive frame */
22177 + skb = dev_alloc_skb(sizeof(struct can_frame));
22178 + if (!skb)
22179 + dev_notice(ND2D(dev),
22180 + "Packets dropped.\n");
22181 + skb->dev = dev;
22182 + frame = (struct can_frame *)skb_put(skb,
22183 + sizeof(struct can_frame));
22184 +
22185 + frame->can_id &= 0x0;
22186 + frame->can_dlc = length;
22187 + tmp1 = mb->can_id & MB_ID_EXT;
22188 + if (ctrl & MB_CNT_IDE) {
22189 + tmp = tmp1;
22190 + tmp = (tmp >> 18) & CAN_SFF_MASK;
22191 + frame->can_id = (tmp1 << 11) | tmp;
22192 + frame->can_id &= CAN_EFF_MASK;
22193 + frame->can_id |= CAN_EFF_FLAG;
22194 + if (ctrl & MB_CNT_RTR)
22195 + frame->can_id |= CAN_RTR_FLAG;
22196 + } else {
22197 + frame->can_id = tmp1 >> 18;
22198 + if (ctrl & MB_CNT_RTR)
22199 + frame->can_id |= CAN_RTR_FLAG;
22200 + }
22201 +
22202 + for (k = 0; k < 8; k++)
22203 + frame->data[k] = mb->data[k];
22204 +
22205 + mb->can_dlc &= MB_CODE_MASK;
22206 + mb->can_dlc |= MB_CNT_CODE(0x04);
22207 +
22208 + stats->rx_packets++;
22209 + stats->rx_bytes += frame->can_dlc;
22210 + skb->dev = dev;
22211 + skb->protocol = __constant_htons(ETH_P_CAN);
22212 + skb->ip_summed = CHECKSUM_UNNECESSARY;
22213 +
22214 + retval = netif_rx(skb);
22215 + if (retval == NET_RX_DROP)
22216 + dev_notice(ND2D(dev),
22217 + "Packets dropped.\n");
22218 + } else {
22219 + /* transmit frame */
22220 + mb->can_dlc = MB_CNT_CODE(0x04);
22221 + }
22222 + }
22223 + }
22224 + regs->iflag = oflags;
22225 +
22226 + return IRQ_HANDLED;
22227 +}
22228 +
22229 +static int flexcan_do_set_bit_time(struct net_device *dev,
22230 + struct can_bittime *bt)
22231 +{
22232 + struct flexcan_priv *priv = netdev_priv(dev);
22233 + struct flexcan_regs *regs = (struct flexcan_regs *)dev->base_addr;
22234 + int ret = 0;
22235 + u32 reg;
22236 +
22237 + if (bt->type != CAN_BITTIME_STD)
22238 + return -EINVAL;
22239 +
22240 + spin_lock_irq(&priv->can.irq_lock);
22241 +
22242 + reg = CANCTRL_PRESDIV(bt->std.brp) | CANCTRL_PSEG1(bt->std.phase_seg1
22243 + - 1) | CANCTRL_PSEG2(bt->std.phase_seg2 - 1);
22244 + regs->canctrl &= CANCTRL_BITTIME;
22245 + regs->canctrl |= (reg | CANCTRL_SAMP(bt->std.sam) |
22246 + CANCTRL_PROPSEG(bt->std.prop_seg - 1));
22247 +
22248 + spin_unlock_irq(&priv->can.irq_lock);
22249 + return ret;
22250 +}
22251 +
22252 +
22253 +static int flexcan_open(struct net_device *dev)
22254 +{
22255 + int ret, i, j;
22256 + struct flexcan_regs *regs = (struct flexcan_regs *)dev->base_addr;
22257 +
22258 +#if defined(CONFIG_M547X_8X)
22259 + MCF_PAR_TIMER = MCF_PAR_TIMER | 0x28;
22260 + MCF_PAR_TIMER = MCF_PAR_TIMER & 0xf8;
22261 + MCF_PAR_DSPI = MCF_PAR_DSPI | 0x0a00;
22262 + MCF_PAR_FECI2CIRQ = MCF_PAR_FECI2CIRQ | 0x0283;
22263 + MCF_PAR_PSCn(2) = MCF_PAR_PSCn(2) & 0x0f;
22264 + MCF_PAR_PSCn(2) = MCF_PAR_PSCn(2) | 0x50;
22265 +#endif
22266 +
22267 + regs->canmcr |= CANMCR_SOFTRST;
22268 + regs->canmcr |= CANMCR_MDIS;
22269 + udelay(10);
22270 +
22271 + if ((regs->canmcr & CANMCR_SOFTRST) != 0x0) {
22272 + dev_err(ND2D(dev), "Failed to softreset can module.\n");
22273 + return -1;
22274 + }
22275 +
22276 + /* Enable error and bus off interrupt */
22277 + regs->canctrl |= (CANCTRL_RJW(3) | CANCTRL_ERRMSK |
22278 + CANCTRL_BOFFMSK);
22279 +
22280 + /* Set lowest buffer transmitted first */
22281 + regs->canctrl |= CANCTRL_LBUF;
22282 +
22283 + for (i = 0; i < 16; i++) {
22284 + regs->cantxfg[i].can_dlc = 0;
22285 + regs->cantxfg[i].can_id = 0;
22286 + for (j = 0; j < 8; j++)
22287 + regs->cantxfg[i].data[j] = 0;
22288 +
22289 + /* Put MB into rx queue */
22290 + regs->cantxfg[i].can_dlc = MB_CNT_CODE(0x04);
22291 + }
22292 +
22293 + /* acceptance mask/acceptance code (accept everything) */
22294 + regs->rxgmask = 0x00000000;
22295 + regs->rx14mask = 0x00000000;
22296 + regs->rx15mask = 0x00000000;
22297 + /* extended frame */
22298 + regs->cantxfg[14].can_dlc |= 0x600000;
22299 + /* Enable flexcan module */
22300 + regs->canmcr &= ~CANMCR_MDIS;
22301 + /* Synchronize with the can bus */
22302 + regs->canmcr &= ~CANMCR_HALT;
22303 +
22304 +#if defined(CONFIG_M547X_8X)
22305 + for (i = 0; i < 2; i++) {
22306 + MCF_ICR(ISC_CANn_MBOR(i)) = 0x33;
22307 + MCF_ICR(ISC_CANn_ERR(i)) = 0x33;
22308 + MCF_ICR(ISC_CANn_BUSOFF(i)) = 0x33;
22309 + }
22310 +
22311 + ret = request_irq(dev->irq + 64, flexcan_isr, IRQF_DISABLED,
22312 + dev->name, dev);
22313 + ret = request_irq(dev->irq + 1 + 64, flexcan_isr, IRQF_DISABLED,
22314 + dev->name, dev);
22315 + ret = request_irq(dev->irq + 2 + 64, flexcan_isr, IRQF_DISABLED,
22316 + dev->name, dev);
22317 + if (ret < 0) {
22318 + printk(KERN_ERR "%s - failed to attach interrupt.\n",
22319 + dev->name);
22320 + return ret;
22321 + }
22322 +#endif
22323 +
22324 + /* Enable all interrupts */
22325 + regs->imask = IMASK_BUFF_ENABLE_ALL;
22326 + netif_start_queue(dev);
22327 + return 0;
22328 +}
22329 +
22330 +static int flexcan_close(struct net_device *dev)
22331 +{
22332 + struct flexcan_regs *regs = (struct flexcan_regs *)dev->base_addr;
22333 +
22334 + netif_stop_queue(dev);
22335 +
22336 + /* Disable all interrupts */
22337 + regs->imask = IMASK_BUFF_DISABLE_ALL;
22338 + free_irq(dev->irq + 64, dev);
22339 + free_irq(dev->irq + 1 + 64, dev);
22340 + free_irq(dev->irq + 2 + 64, dev);
22341 +
22342 + /* Disable module */
22343 + regs->canmcr |= CANMCR_MDIS;
22344 + return 0;
22345 +}
22346 +
22347 +int register_flexcandev(struct net_device *dev, int clock_src)
22348 +{
22349 + struct flexcan_regs *regs = (struct flexcan_regs *)dev->base_addr;
22350 +
22351 + regs->canmcr &= ~CANMCR_MDIS;
22352 + udelay(100);
22353 + regs->canmcr |= (CANMCR_FRZ | CANMCR_HALT);
22354 + return register_netdev(dev);
22355 +}
22356 +EXPORT_SYMBOL(register_flexcandev);
22357 +
22358 +void unregister_flexcandev(struct net_device *dev)
22359 +{
22360 + struct flexcan_regs *regs = (struct flexcan_regs *)dev->base_addr;
22361 +
22362 + regs->canmcr |= (CANMCR_FRZ | CANMCR_HALT);
22363 + regs->canmcr |= CANMCR_MDIS;
22364 +
22365 + unregister_netdev(dev);
22366 +}
22367 +EXPORT_SYMBOL(unregister_flexcandev);
22368 +
22369 +struct net_device *alloc_flexcandev(void)
22370 +{
22371 + struct net_device *dev;
22372 + struct flexcan_priv *priv;
22373 +
22374 + dev = alloc_candev(sizeof(struct flexcan_priv));
22375 + if (!dev)
22376 + return NULL;
22377 +
22378 + priv = netdev_priv(dev);
22379 + priv->dev = dev;
22380 + dev->open = flexcan_open;
22381 + dev->stop = flexcan_close;
22382 + dev->hard_start_xmit = flexcan_hard_start_xmit;
22383 + dev->tx_timeout = flexcan_tx_timeout;
22384 + dev->flags |= IFF_NOARP;
22385 + priv->can.do_set_bit_time = flexcan_do_set_bit_time;
22386 + return dev;
22387 +}
22388 +EXPORT_SYMBOL(alloc_flexcandev);
22389 +
22390 +MODULE_AUTHOR("Andrey Volkov <avolkov@varma-el.com>");
22391 +MODULE_LICENSE("GPL v2");
22392 +MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
22393 --- /dev/null
22394 +++ b/drivers/net/can/flexcan/flexcan.h
22395 @@ -0,0 +1,148 @@
22396 +/*
22397 + * flexcan.h
22398 + *
22399 + * DESCRIPTION:
22400 + * Definitions of consts/structs to drive the Freescale FLEXCAN.
22401 + *
22402 + */
22403 +
22404 +#ifndef __FLEXCAN_H__
22405 +#define __FLEXCAN_H__
22406 +
22407 +#include <linux/autoconf.h>
22408 +#include <linux/types.h>
22409 +
22410 +/* FLEXCAN module configuration register (CANMCR) bits */
22411 +#define CANMCR_MDIS 0x80000000
22412 +#define CANMCR_FRZ 0x40000000
22413 +#define CANMCR_HALT 0x10000000
22414 +#define CANMCR_SOFTRST 0x02000000
22415 +#define CANMCR_FRZACK 0x01000000
22416 +#define CANMCR_SUPV 0x00800000
22417 +#define CANMCR_MAXMB(x) ((x)&0x0f)
22418 +
22419 +/* FLEXCAN control register (CANCTRL) bits */
22420 +#define CANCTRL_PRESDIV(x) (((x)&0xff)<<24)
22421 +#define CANCTRL_RJW(x) (((x)&0x03)<<22)
22422 +#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
22423 +#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
22424 +#define CANCTRL_BOFFMSK 0x00008000
22425 +#define CANCTRL_ERRMSK 0x00004000
22426 +#define CANCTRL_LPB 0x00001000
22427 +#define CANCTRL_SAMP(x) (((x)&0x1)<<7)
22428 +#define CANCTRL_BOFFREC 0x00000040
22429 +#define CANCTRL_TSYNC 0x00000020
22430 +#define CANCTRL_LBUF 0x00000010
22431 +#define CANCTRL_LOM 0x00000008
22432 +#define CANCTRL_PROPSEG(x) ((x)&0x07)
22433 +#define CANCTRL_BITTIME 0x00c0d078
22434 +
22435 +/* FLEXCAN error counter register (ERRCNT) bits */
22436 +#define ERRCNT_REXECTR(x) (((x)&0xff)<<8)
22437 +#define ERRCNT_TXECTR(x) ((x)&0xff)
22438 +
22439 +/* FLEXCAN error and status register (ERRSTAT) bits */
22440 +#define ERRSTAT_BITERR(x) (((x)&0x03)<<14)
22441 +#define ERRSTAT_ACKERR 0x00002000
22442 +#define ERRSTAT_CRCERR 0x00001000
22443 +#define ERRSTAT_FRMERR 0x00000800
22444 +#define ERRSTAT_STFERR 0x00000400
22445 +#define ERRSTAT_TXWRN 0x00000200
22446 +#define ERRSTAT_RXWRN 0x00000100
22447 +#define ERRSTAT_IDLE 0x00000080
22448 +#define ERRSTAT_TXRX 0x00000040
22449 +#define ERRSTAT_FLTCONF(x) (((x)&0x03)<<4)
22450 +#define ERRSTAT_BOFFINT 0x00000004
22451 +#define ERRSTAT_ERRINT 0x00000002
22452 +
22453 +/* FLEXCAN interrupt mask register (IMASK) bits */
22454 +#define IMASK_BUF15M 0x8000
22455 +#define IMASK_BUF14M 0x4000
22456 +#define IMASK_BUF13M 0x2000
22457 +#define IMASK_BUF12M 0x1000
22458 +#define IMASK_BUF11M 0x0800
22459 +#define IMASK_BUF10M 0x0400
22460 +#define IMASK_BUF9M 0x0200
22461 +#define IMASK_BUF8M 0x0100
22462 +#define IMASK_BUF7M 0x0080
22463 +#define IMASK_BUF6M 0x0040
22464 +#define IMASK_BUF5M 0x0020
22465 +#define IMASK_BUF4M 0x0010
22466 +#define IMASK_BUF3M 0x0008
22467 +#define IMASK_BUF2M 0x0004
22468 +#define IMASK_BUF1M 0x0002
22469 +#define IMASK_BUF0M 0x0001
22470 +#define IMASK_BUFnM(x) (0x1<<(x))
22471 +#define IMASK_BUFF_ENABLE_ALL 0xffff
22472 +#define IMASK_BUFF_DISABLE_ALL 0x0000
22473 +
22474 +/* FLEXCAN interrupt flag register (IFLAG) bits */
22475 +#define IFLAG_BUF15M 0x8000
22476 +#define IFLAG_BUF14M 0x4000
22477 +#define IFLAG_BUF13M 0x2000
22478 +#define IFLAG_BUF12M 0x1000
22479 +#define IFLAG_BUF11M 0x0800
22480 +#define IFLAG_BUF10M 0x0400
22481 +#define IFLAG_BUF9M 0x0200
22482 +#define IFLAG_BUF8M 0x0100
22483 +#define IFLAG_BUF7M 0x0080
22484 +#define IFLAG_BUF6M 0x0040
22485 +#define IFLAG_BUF5M 0x0020
22486 +#define IFLAG_BUF4M 0x0010
22487 +#define IFLAG_BUF3M 0x0008
22488 +#define IFLAG_BUF2M 0x0004
22489 +#define IFLAG_BUF1M 0x0002
22490 +#define IFLAG_BUF0M 0x0001
22491 +#define IFLAG_BUFnM(x) (0x1<<(x))
22492 +#define IFLAG_BUFF_SET_ALL 0xffff
22493 +#define IFLAG_BUFF_DISABLE_ALL 0x0000
22494 +
22495 +/* FLEXCAN message buffers */
22496 +#define MB_CNT_CODE(x) (((x)&0x0f)<<24)
22497 +#define MB_CNT_SRR 0x00400000
22498 +#define MB_CNT_IDE 0x00200000
22499 +#define MB_CNT_RTR 0x00100000
22500 +#define MB_CNT_LENGTH(x) (((x)&0x0f)<<16)
22501 +#define MB_CNT_TIMESTAMP(x) ((x)&0xffff)
22502 +
22503 +#define MB_ID_STD ((0x7ff)<<18)
22504 +#define MB_ID_EXT 0x1fffffff
22505 +#define MB_CODE_MASK 0xf0ffffff
22506 +
22507 +/* Structure of the message buffer */
22508 +struct flexcan_mb {
22509 + u32 can_dlc;
22510 + u32 can_id;
22511 + u8 data[8];
22512 +};
22513 +
22514 +/* Structure of the hardware registers */
22515 +struct flexcan_regs {
22516 + u32 canmcr;
22517 + u32 canctrl;
22518 + u32 timer;
22519 + u32 reserved1;
22520 + u32 rxgmask;
22521 + u32 rx14mask;
22522 + u32 rx15mask;
22523 + u32 errcnt;
22524 + u32 errstat;
22525 + u32 reserved2;
22526 + u32 imask;
22527 + u32 reserved3;
22528 + u32 iflag;
22529 + u32 reserved4[19];
22530 + struct flexcan_mb cantxfg[16];
22531 +};
22532 +
22533 +struct flexcan_platform_data {
22534 + u8 clock_src; /* FLEXCAN clock source CRIN or SYSCLK */
22535 + u32 clock_frq; /* can ref. clock, in Hz */
22536 +};
22537 +
22538 +struct net_device *alloc_flexcandev(void);
22539 +
22540 +extern int register_flexcandev(struct net_device *dev, int clock_src);
22541 +extern void unregister_flexcandev(struct net_device *dev);
22542 +
22543 +#endif /* __FLEXCAN_H__ */
22544 --- /dev/null
22545 +++ b/drivers/net/can/flexcan/Makefile
22546 @@ -0,0 +1,5 @@
22547 +
22548 +obj-$(CONFIG_CAN_MCF547X_8X) += flexcan-mcf548x.o
22549 +
22550 +flexcan-mcf548x-objs := flexcan.o mcf548x_can.o
22551 +
22552 --- /dev/null
22553 +++ b/drivers/net/can/flexcan/mcf548x_can.c
22554 @@ -0,0 +1,213 @@
22555 +/*
22556 + * DESCRIPTION:
22557 + * CAN bus driver for the Freescale MCF548x embedded CPU.
22558 + *
22559 + * AUTHOR:
22560 + * Andrey Volkov <avolkov@varma-el.com>
22561 + *
22562 + * COPYRIGHT:
22563 + * 2004-2005, Varma Electronics Oy
22564 + *
22565 + * LICENCE:
22566 + * This program is free software; you can redistribute it and/or modify
22567 + * it under the terms of the GNU General Public License as published by
22568 + * the Free Software Foundation; either version 2 of the License, or
22569 + * (at your option) any later version.
22570 + *
22571 + * This program is distributed in the hope that it will be useful,
22572 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
22573 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22574 + * GNU General Public License for more details.
22575 + *
22576 + * You should have received a copy of the GNU General Public License
22577 + * along with this program; if not, write to the Free Software
22578 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22579 + *
22580 + * HISTORY:
22581 + * 2008-06-23 support for MCF548x's FlexCAN
22582 + * Huan, Wang <b18965@freescale.com>
22583 + * 2005-02-03 created
22584 + *
22585 + */
22586 +
22587 +#include <linux/kernel.h>
22588 +#include <linux/module.h>
22589 +#include <linux/interrupt.h>
22590 +#include <linux/platform_device.h>
22591 +#include <linux/netdevice.h>
22592 +#include <linux/can.h>
22593 +#include <linux/can/dev.h>
22594 +#include <linux/io.h>
22595 +
22596 +#include "flexcan.h"
22597 +#include <asm/coldfire.h>
22598 +#include <asm/m5485sim.h>
22599 +#include <linux/can/version.h> /* for RCSID. Removed by mkpatch script */
22600 +
22601 +RCSID("$Id$");
22602 +
22603 +#define PDEV_MAX 2
22604 +
22605 +struct platform_device *pdev[PDEV_MAX];
22606 +
22607 +static int __devinit mcf548x_can_probe(struct platform_device *pdev)
22608 +{
22609 + struct resource *mem;
22610 + struct net_device *dev;
22611 + struct flexcan_platform_data *pdata = pdev->dev.platform_data;
22612 + struct can_priv *can;
22613 + u32 mem_size;
22614 + int ret = -ENODEV;
22615 +
22616 + if (!pdata)
22617 + return ret;
22618 +
22619 + dev = alloc_flexcandev();
22620 + if (!dev)
22621 + return -ENOMEM;
22622 + can = netdev_priv(dev);
22623 +
22624 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
22625 +
22626 + dev->irq = platform_get_irq(pdev, 0);
22627 + if (!mem || !dev->irq)
22628 + goto req_error;
22629 +
22630 + mem_size = mem->end - mem->start + 1;
22631 + if (!request_mem_region(mem->start, mem_size, pdev->dev.driver->name)) {
22632 + dev_err(&pdev->dev, "resource unavailable\n");
22633 + goto req_error;
22634 + }
22635 + SET_NETDEV_DEV(dev, &pdev->dev);
22636 +
22637 + dev->base_addr = (unsigned long)ioremap_nocache(mem->start, mem_size);
22638 + if (!dev->base_addr) {
22639 + dev_err(&pdev->dev, "failed to map can port\n");
22640 + ret = -ENOMEM;
22641 + goto fail_map;
22642 + }
22643 + can->can_sys_clock = pdata->clock_frq;
22644 + platform_set_drvdata(pdev, dev);
22645 + ret = register_flexcandev(dev, pdata->clock_src);
22646 + if (ret >= 0) {
22647 + dev_info(&pdev->dev, "probe for port 0x%lX done\n",
22648 + dev->base_addr);
22649 + return ret;
22650 + }
22651 +
22652 + iounmap((unsigned long *)dev->base_addr);
22653 +fail_map:
22654 + release_mem_region(mem->start, mem_size);
22655 +req_error:
22656 + free_candev(dev);
22657 + dev_err(&pdev->dev, "probe failed\n");
22658 + return ret;
22659 +}
22660 +
22661 +static int __devexit mcf548x_can_remove(struct platform_device *pdev)
22662 +{
22663 + struct net_device *dev = platform_get_drvdata(pdev);
22664 + struct resource *mem;
22665 +
22666 + platform_set_drvdata(pdev, NULL);
22667 + unregister_flexcandev(dev);
22668 + iounmap((unsigned long *)dev->base_addr);
22669 +
22670 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
22671 + release_mem_region(mem->start, mem->end - mem->start + 1);
22672 + free_candev(dev);
22673 + return 0;
22674 +}
22675 +
22676 +static struct platform_driver mcf548x_can_driver = {
22677 + .driver = {
22678 + .name = "mcf548x-flexcan",
22679 + },
22680 + .probe = mcf548x_can_probe,
22681 + .remove = __devexit_p(mcf548x_can_remove),
22682 +};
22683 +
22684 +static struct resource mcf548x_can0_resources[] = {
22685 + [0] = {
22686 + .start = MCF_MBAR + 0x0000A000,
22687 + .end = MCF_MBAR + 0x0000A7FF,
22688 + .flags = IORESOURCE_MEM,
22689 + },
22690 + [1] = {
22691 + .start = 49,
22692 + .end = 49,
22693 + .flags = IORESOURCE_IRQ,
22694 + },
22695 +};
22696 +
22697 +static struct resource mcf548x_can1_resources[] = {
22698 + [0] = {
22699 + .start = MCF_MBAR + 0x0000A800,
22700 + .end = MCF_MBAR + 0x0000AFFF,
22701 + .flags = IORESOURCE_MEM,
22702 + },
22703 + [1] = {
22704 + .start = 55,
22705 + .end = 55,
22706 + .flags = IORESOURCE_IRQ,
22707 + },
22708 +};
22709 +
22710 +
22711 +static int __init mcf548x_of_to_pdev(void)
22712 +{
22713 + unsigned int i;
22714 + int err = -ENODEV;
22715 + struct flexcan_platform_data pdata;
22716 +
22717 + pdev[0] = platform_device_register_simple("mcf548x-flexcan", 0,
22718 + mcf548x_can0_resources, 2);
22719 + if (IS_ERR(pdev[0])) {
22720 + err = PTR_ERR(pdev[0]);
22721 + return err;
22722 + }
22723 + pdev[1] = platform_device_register_simple("mcf548x-flexcan", 1,
22724 + mcf548x_can1_resources, 2);
22725 + if (IS_ERR(pdev[1])) {
22726 + err = PTR_ERR(pdev[1]);
22727 + return err;
22728 + }
22729 +
22730 + /* FlexCAN clock */
22731 + pdata.clock_frq = 100000000;
22732 +
22733 + for (i = 0; i < PDEV_MAX; i++) {
22734 + err = platform_device_add_data(pdev[i], &pdata, sizeof(pdata));
22735 + if (err)
22736 + return err;
22737 + }
22738 + return err;
22739 +}
22740 +
22741 +int __init mcf548x_can_init(void)
22742 +{
22743 + int err = mcf548x_of_to_pdev();
22744 +
22745 + if (err) {
22746 + printk(KERN_ERR "%s init failed with err=%d\n",
22747 + mcf548x_can_driver.driver.name, err);
22748 + return err;
22749 + }
22750 +
22751 + return platform_driver_register(&mcf548x_can_driver);
22752 +}
22753 +
22754 +void __exit mcf548x_can_exit(void)
22755 +{
22756 + int i;
22757 + platform_driver_unregister(&mcf548x_can_driver);
22758 + for (i = 0; i < PDEV_MAX; i++)
22759 + platform_device_unregister(pdev[i]);
22760 +}
22761 +
22762 +module_init(mcf548x_can_init);
22763 +module_exit(mcf548x_can_exit);
22764 +
22765 +MODULE_AUTHOR("Andrey Volkov <avolkov@varma-el.com>");
22766 +MODULE_DESCRIPTION("Freescale MCF548x CAN driver");
22767 +MODULE_LICENSE("GPL v2");
22768 --- a/drivers/net/can/Kconfig
22769 +++ b/drivers/net/can/Kconfig
22770 @@ -12,6 +12,19 @@ config CAN_VCAN
22771 This driver can also be built as a module. If so, the module
22772 will be called vcan.
22773
22774 +config CAN_FLEXCAN
22775 + tristate "Support for Freescale FLEXCAN based chips"
22776 + depends on CAN && (PPC || M68K || M68KNOMMU)
22777 + ---help---
22778 + Say Y here if you want to support for Freescale FlexCAN.
22779 +
22780 +config CAN_MCF547X_8X
22781 + tristate "Freescale MCF547X/MCF548X onboard CAN controller"
22782 + depends on CAN_FLEXCAN && (M547X || M548X)
22783 + ---help---
22784 + Say Y here if you want to support for Freescale MCF547x/MCF548x
22785 + onboard dualCAN controller.
22786 +
22787 config CAN_DEBUG_DEVICES
22788 bool "CAN devices debugging messages"
22789 depends on CAN
22790 --- a/drivers/net/can/Makefile
22791 +++ b/drivers/net/can/Makefile
22792 @@ -3,3 +3,4 @@
22793 #
22794
22795 obj-$(CONFIG_CAN_VCAN) += vcan.o
22796 +obj-$(CONFIG_CAN_FLEXCAN) += flexcan/
22797 --- /dev/null
22798 +++ b/drivers/net/fec/fec.c
22799 @@ -0,0 +1,1306 @@
22800 +/*
22801 + * Performance and stability improvements: (C) Copyright 2008,
22802 + * Daniel Krueger, SYSTEC electronic GmbH
22803 + *
22804 + * Code crunched to get it to work on 2.6.24 -- FEC cleanup coming
22805 + * soon -- Kurt Mahan
22806 + */
22807 +#include <linux/module.h>
22808 +#include <linux/kernel.h>
22809 +#include <linux/string.h>
22810 +#include <linux/ptrace.h>
22811 +#include <linux/errno.h>
22812 +#include <linux/ioport.h>
22813 +#include <linux/slab.h>
22814 +#include <linux/interrupt.h>
22815 +#include <linux/pci.h>
22816 +#include <linux/init.h>
22817 +#include <linux/delay.h>
22818 +#include <linux/netdevice.h>
22819 +#include <linux/etherdevice.h>
22820 +#include <linux/skbuff.h>
22821 +#include <linux/spinlock.h>
22822 +#include <linux/workqueue.h>
22823 +#include <linux/bitops.h>
22824 +
22825 +#include <asm/coldfire.h>
22826 +#include <asm/mcfsim.h>
22827 +
22828 +#include <asm/dma.h>
22829 +#include <asm/MCD_dma.h>
22830 +#include <asm/m5485sram.h>
22831 +#include <asm/virtconvert.h>
22832 +#include <asm/irq.h>
22833 +
22834 +#include "fec.h"
22835 +#include "ks8721.h"
22836 +
22837 +#ifdef CONFIG_FEC_548x_ENABLE_FEC2
22838 +#define FEC_MAX_PORTS 2
22839 +#define FEC_2
22840 +#else
22841 +#define FEC_MAX_PORTS 1
22842 +#undef FEC_2
22843 +#endif
22844 +
22845 +#define VERSION "0.20"
22846 +MODULE_DESCRIPTION( "DMA Fast Ethernet Controller driver ver " VERSION);
22847 +
22848 +/* fec private */
22849 +struct fec_priv {
22850 + struct net_device *netdev; /* owning net device */
22851 + void* fecpriv_txbuf[FEC_TX_BUF_NUMBER]; /* tx buffer ptrs */
22852 + MCD_bufDescFec *fecpriv_txdesc; /* tx descriptor ptrs */
22853 + volatile unsigned int fecpriv_current_tx; /* current tx desc index */
22854 + volatile unsigned int fecpriv_next_tx; /* next tx desc index */
22855 + unsigned int fecpriv_current_rx; /* current rx desc index */
22856 + MCD_bufDescFec *fecpriv_rxdesc; /* rx descriptor ptrs */
22857 + struct sk_buff *askb_rx[FEC_RX_BUF_NUMBER]; /* rx SKB ptrs */
22858 + unsigned int fecpriv_initiator_rx; /* rx dma initiator */
22859 + unsigned int fecpriv_initiator_tx; /* tx dma initiator */
22860 + int fecpriv_fec_rx_channel; /* rx dma channel */
22861 + int fecpriv_fec_tx_channel; /* tx dma channel */
22862 + int fecpriv_rx_requestor; /* rx dma requestor */
22863 + int fecpriv_tx_requestor; /* tx dma requestor */
22864 + void *fecpriv_interrupt_fec_rx_handler; /* dma rx handler */
22865 + void *fecpriv_interrupt_fec_tx_handler; /* dma tx handler */
22866 + unsigned char *fecpriv_mac_addr; /* private fec mac addr */
22867 + struct net_device_stats fecpriv_stat; /* stats ptr */
22868 + spinlock_t fecpriv_lock;
22869 + int fecpriv_rxflag;
22870 + struct tasklet_struct fecpriv_tasklet_reinit;
22871 + int index; /* fec hw number */
22872 +};
22873 +
22874 +struct net_device *fec_dev[FEC_MAX_PORTS];
22875 +
22876 +/* FEC functions */
22877 +int __init fec_init(void);
22878 +struct net_device_stats *fec_get_stat(struct net_device *dev);
22879 +int fec_open(struct net_device *dev);
22880 +int fec_close(struct net_device *nd);
22881 +int fec_tx(struct sk_buff *skb, struct net_device *dev);
22882 +void fec_set_multicast_list(struct net_device *nd);
22883 +int fec_set_mac_address(struct net_device *dev, void *p);
22884 +void fec_tx_timeout(struct net_device *dev);
22885 +void fec_interrupt_fec_tx_handler(struct net_device *dev);
22886 +void fec_interrupt_fec_rx_handler(struct net_device *dev);
22887 +irqreturn_t fec_interrupt_handler(int irq, void *dev_id);
22888 +void fec_interrupt_fec_tx_handler_fec0(void);
22889 +void fec_interrupt_fec_rx_handler_fec0(void);
22890 +void fec_interrupt_fec_reinit(unsigned long data);
22891 +
22892 +/* default fec0 address */
22893 +unsigned char fec_mac_addr_fec0[6] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x50 };
22894 +
22895 +#ifdef FEC_2
22896 +/* default fec1 address */
22897 +unsigned char fec_mac_addr_fec1[6] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x51 };
22898 +#endif
22899 +
22900 +extern unsigned char uboot_enet0[];
22901 +extern unsigned char uboot_enet1[];
22902 +
22903 +#ifndef MODULE
22904 +int fec_str_to_mac( char *str_mac, unsigned char* addr);
22905 +int __init fec_mac_setup0 (char *s);
22906 +#endif
22907 +
22908 +
22909 +#ifdef FEC_2
22910 +void fec_interrupt_fec_tx_handler_fec1(void);
22911 +void fec_interrupt_fec_rx_handler_fec1(void);
22912 +#endif
22913 +
22914 +#ifndef MODULE
22915 +int __init fec_mac_setup1 (char *s);
22916 +#endif
22917 +
22918 +int fec_read_mii(unsigned int base_addr, unsigned int pa, unsigned int ra, unsigned int *data);
22919 +int fec_write_mii(unsigned int base_addr, unsigned int pa, unsigned int ra, unsigned int data);
22920 +
22921 +module_init(fec_init);
22922 +/* module_exit(fec_cleanup); */
22923 +
22924 +__setup("mac0=", fec_mac_setup0);
22925 +
22926 +#ifdef FEC_2
22927 +__setup("mac1=", fec_mac_setup1);
22928 +#endif
22929 +
22930 +/*
22931 + * Initialize a FEC device
22932 + */
22933 +int fec_enet_init(struct net_device *dev)
22934 +{
22935 + static int index = 0;
22936 + struct fec_priv *fp = netdev_priv(dev);
22937 + int i;
22938 +
22939 + fp->index = index;
22940 + fp->netdev = dev;
22941 + fec_dev[ index ] = dev;
22942 +
22943 + if (index == 0) {
22944 + /* disable fec0 */
22945 + FEC_ECR(FEC_BASE_ADDR_FEC0) = FEC_ECR_DISABLE;
22946 +
22947 + /* setup the interrupt handler */
22948 + dev->irq = 64 + ISC_FEC0;
22949 +
22950 + if (request_irq(dev->irq, fec_interrupt_handler,
22951 + IRQF_DISABLED, "ColdFire FEC 0", dev)) {
22952 + dev->irq = 0;
22953 + printk("Cannot allocate FEC0 IRQ\n");
22954 + } else {
22955 + /* interrupt priority and level */
22956 + MCF_ICR(ISC_FEC0) = ILP_FEC0;
22957 + }
22958 +
22959 + /* fec base address */
22960 + dev->base_addr = FEC_BASE_ADDR_FEC0;
22961 +
22962 + /* requestor numbers */
22963 + fp->fecpriv_rx_requestor = DMA_FEC0_RX;
22964 + fp->fecpriv_tx_requestor = DMA_FEC0_TX;
22965 +
22966 + /* fec0 handlers */
22967 + fp->fecpriv_interrupt_fec_rx_handler = fec_interrupt_fec_rx_handler_fec0;
22968 + fp->fecpriv_interrupt_fec_tx_handler = fec_interrupt_fec_tx_handler_fec0;
22969 +
22970 + /* tx descriptors */
22971 + fp->fecpriv_txdesc = (void*)FEC_TX_DESC_FEC0;
22972 +
22973 + /* rx descriptors */
22974 + fp->fecpriv_rxdesc = (void*)FEC_RX_DESC_FEC0;
22975 +
22976 + /* mac addr */
22977 + if (uboot_enet0[0] || uboot_enet0[1] || uboot_enet0[2] ||
22978 + uboot_enet0[3] || uboot_enet0[4] || uboot_enet0[5]) {
22979 + /* use uboot enet 0 addr */
22980 + memcpy(fec_mac_addr_fec0, uboot_enet0, 6);
22981 + }
22982 +
22983 + fp->fecpriv_mac_addr = fec_mac_addr_fec0;
22984 + }
22985 + else {
22986 + /* disable fec1 */
22987 + FEC_ECR(FEC_BASE_ADDR_FEC1) = FEC_ECR_DISABLE;
22988 +#ifdef FEC_2
22989 + /* setup the interrupt handler */
22990 + dev->irq = 64 + ISC_FEC1;
22991 +
22992 + if (request_irq(dev->irq, fec_interrupt_handler,
22993 + IRQF_DISABLED, "ColdFire FEC 1", dev)) {
22994 + dev->irq = 0;
22995 + printk("Cannot allocate FEC1 IRQ\n");
22996 + } else {
22997 + /* interrupt priority and level */
22998 + MCF_ICR(ISC_FEC1) = ILP_FEC1;
22999 + }
23000 +
23001 + /* fec base address */
23002 + dev->base_addr = FEC_BASE_ADDR_FEC1;
23003 +
23004 + /* requestor numbers */
23005 + fp->fecpriv_rx_requestor = DMA_FEC1_RX;
23006 + fp->fecpriv_tx_requestor = DMA_FEC1_TX;
23007 +
23008 + /* fec1 handlers */
23009 + fp->fecpriv_interrupt_fec_rx_handler = fec_interrupt_fec_rx_handler_fec1;
23010 + fp->fecpriv_interrupt_fec_tx_handler = fec_interrupt_fec_tx_handler_fec1;
23011 +
23012 + /* tx descriptors */
23013 + fp->fecpriv_txdesc = (void*)FEC_TX_DESC_FEC1;
23014 +
23015 + /* rx descriptors */
23016 + fp->fecpriv_rxdesc = (void*)FEC_RX_DESC_FEC1;
23017 +
23018 + /* mac addr */
23019 + if (uboot_enet1[0] || uboot_enet1[1] || uboot_enet1[2] ||
23020 + uboot_enet1[3] || uboot_enet1[4] || uboot_enet1[5]) {
23021 + /* use uboot enet 1 addr */
23022 + memcpy(fec_mac_addr_fec1, uboot_enet1, 6);
23023 + }
23024 + fp->fecpriv_mac_addr = fec_mac_addr_fec1;
23025 +#endif
23026 + }
23027 +
23028 + /* clear MIB */
23029 + memset((void *) (dev->base_addr + 0x200), 0, FEC_MIB_LEN);
23030 +
23031 + /* clear the statistics structure */
23032 + memset((void *) &(fp->fecpriv_stat), 0,
23033 + sizeof(struct net_device_stats));
23034 +
23035 + /* grab the FEC initiators */
23036 + dma_set_initiator(fp->fecpriv_tx_requestor);
23037 + fp->fecpriv_initiator_tx = dma_get_initiator(fp->fecpriv_tx_requestor);
23038 + dma_set_initiator(fp->fecpriv_rx_requestor);
23039 + fp->fecpriv_initiator_rx = dma_get_initiator(fp->fecpriv_rx_requestor);
23040 +
23041 + /* reset the DMA channels */
23042 + fp->fecpriv_fec_rx_channel = -1;
23043 + fp->fecpriv_fec_tx_channel = -1;
23044 +
23045 + for (i = 0; i < FEC_RX_BUF_NUMBER; i++)
23046 + fp->askb_rx[i] = NULL;
23047 +
23048 + /* initialize the pointers to the socket buffers */
23049 + for (i = 0; i < FEC_TX_BUF_NUMBER; i++)
23050 + fp->fecpriv_txbuf[i] = NULL;
23051 +
23052 + ether_setup(dev);
23053 +
23054 + dev->open = fec_open;
23055 + dev->stop = fec_close;
23056 + dev->hard_start_xmit = fec_tx;
23057 + dev->get_stats = fec_get_stat;
23058 + dev->set_multicast_list = fec_set_multicast_list;
23059 + dev->set_mac_address = fec_set_mac_address;
23060 + dev->tx_timeout = fec_tx_timeout;
23061 + dev->watchdog_timeo = FEC_TX_TIMEOUT * HZ;
23062 +
23063 + memcpy(dev->dev_addr, fp->fecpriv_mac_addr, ETH_ALEN);
23064 +
23065 + spin_lock_init(&fp->fecpriv_lock);
23066 +
23067 + // Initialize FEC/I2C/IRQ Pin Assignment Register
23068 + FEC_GPIO_PAR_FECI2CIRQ &= 0xF;
23069 + FEC_GPIO_PAR_FECI2CIRQ |= FEC_FECI2CIRQ;
23070 +
23071 + index++;
23072 + return 0;
23073 +}
23074 +
23075 +/*
23076 + * Module Initialization
23077 + */
23078 +int __init fec_init(void)
23079 +{
23080 + struct net_device *dev;
23081 + int i;
23082 + int err;
23083 + DECLARE_MAC_BUF(mac);
23084 +
23085 + printk(KERN_INFO "FEC ENET (DMA) Version %s\n", VERSION);
23086 +
23087 + for (i = 0; i < FEC_MAX_PORTS; i++) {
23088 + dev = alloc_etherdev(sizeof(struct fec_priv));
23089 + if (!dev)
23090 + return -ENOMEM;
23091 + err = fec_enet_init(dev);
23092 + if (err) {
23093 + free_netdev(dev);
23094 + continue;
23095 + }
23096 + if (register_netdev(dev) != 0) {
23097 + free_netdev(dev);
23098 + return -EIO;
23099 + }
23100 +
23101 + printk(KERN_INFO "%s: ethernet %s\n",
23102 + dev->name, print_mac(mac, dev->dev_addr));
23103 + }
23104 + return 0;
23105 +}
23106 +
23107 +/*
23108 + * Stop a device
23109 + */
23110 +void fec_stop(struct net_device *dev)
23111 +{
23112 + struct fec_priv *fp = netdev_priv(dev);
23113 +
23114 + dma_remove_initiator(fp->fecpriv_initiator_tx);
23115 + dma_remove_initiator(fp->fecpriv_initiator_rx);
23116 +
23117 + if (dev->irq)
23118 + free_irq(dev->irq, dev);
23119 +}
23120 +
23121 +/************************************************************************
23122 +* NAME: fec_open
23123 +*
23124 +* DESCRIPTION: This function performs the initialization of
23125 +* of FEC and corresponding KS8721 transiver
23126 +*
23127 +* RETURNS: If no error occurs, this function returns zero.
23128 +*************************************************************************/
23129 +int fec_open(struct net_device *dev)
23130 +{
23131 + struct fec_priv *fp = netdev_priv(dev);
23132 + unsigned long base_addr = (unsigned long) dev->base_addr;
23133 + int fduplex;
23134 + int i;
23135 + int channel;
23136 + int error_code = -EBUSY;
23137 +
23138 + /* Receive the DMA channels */
23139 + channel = dma_set_channel_fec(fp->fecpriv_rx_requestor);
23140 +
23141 + if (channel == -1) {
23142 + printk("Dma channel cannot be reserved\n");
23143 + goto ERRORS;
23144 + }
23145 +
23146 + fp->fecpriv_fec_rx_channel = channel;
23147 +
23148 + dma_connect(channel, (int) fp->fecpriv_interrupt_fec_rx_handler);
23149 +
23150 + channel = dma_set_channel_fec(fp->fecpriv_tx_requestor);
23151 +
23152 + if (channel == -1) {
23153 + printk("Dma channel cannot be reserved\n");
23154 + goto ERRORS;
23155 + }
23156 +
23157 + fp->fecpriv_fec_tx_channel = channel;
23158 +
23159 + dma_connect(channel, (int) fp->fecpriv_interrupt_fec_tx_handler);
23160 +
23161 + /* init tasklet for controller reinitialization */
23162 + tasklet_init(&fp->fecpriv_tasklet_reinit, fec_interrupt_fec_reinit, (unsigned long) dev);
23163 +
23164 + /* Reset FIFOs */
23165 + FEC_FECFRST(base_addr) |= FEC_SW_RST | FEC_RST_CTL;
23166 + FEC_FECFRST(base_addr) &= ~FEC_SW_RST;
23167 +
23168 + /* Reset and disable FEC */
23169 + FEC_ECR(base_addr) = FEC_ECR_RESET;
23170 +
23171 + udelay(10);
23172 +
23173 + /* Clear all events */
23174 + FEC_EIR(base_addr) = FEC_EIR_CLEAR;
23175 +
23176 + /* Reset FIFO status */
23177 + FEC_FECTFSR(base_addr) = FEC_FECTFSR_MSK;
23178 + FEC_FECRFSR(base_addr) = FEC_FECRFSR_MSK;
23179 +
23180 + /* Set the default address */
23181 + FEC_PALR(base_addr) = (fp->fecpriv_mac_addr[0] << 24) |
23182 + (fp->fecpriv_mac_addr[1] << 16) |
23183 + (fp->fecpriv_mac_addr[2] << 8) |
23184 + fp->fecpriv_mac_addr[3];
23185 + FEC_PAUR(base_addr) = (fp->fecpriv_mac_addr[4] << 24) |
23186 + (fp->fecpriv_mac_addr[5] << 16) | 0x8808;
23187 +
23188 + /* Reset the group address descriptor */
23189 + FEC_GALR(base_addr) = 0x00000000;
23190 + FEC_GAUR(base_addr) = 0x00000000;
23191 +
23192 + /* Reset the individual address descriptor */
23193 + FEC_IALR(base_addr) = 0x00000000;
23194 + FEC_IAUR(base_addr) = 0x00000000;
23195 +
23196 + /* Set the receive control register */
23197 + FEC_RCR(base_addr) = FEC_RCR_MAX_FRM_SIZE | FEC_RCR_MII;
23198 +
23199 + /* Set the receive FIFO control register */
23200 +// FEC_FECRFCR(base_addr) = FEC_FECRFCR_FRM | FEC_FECRFCR_GR | FEC_FECRFCR_MSK;
23201 + FEC_FECRFCR(base_addr) = FEC_FECRFCR_FRM | FEC_FECRFCR_GR
23202 + | (FEC_FECRFCR_MSK // disable all but ...
23203 + & ~FEC_FECRFCR_FAE // enable frame accept error
23204 + & ~FEC_FECRFCR_RXW // enable receive wait condition
23205 +// & ~FEC_FECRFCR_UF // enable FIFO underflow
23206 + );
23207 +
23208 + /* Set the receive FIFO alarm register */
23209 + FEC_FECRFAR(base_addr) = FEC_FECRFAR_ALARM;
23210 +
23211 + /* Set the transmit FIFO control register */
23212 +// FEC_FECTFCR(base_addr) = FEC_FECTFCR_FRM | FEC_FECTFCR_GR | FEC_FECTFCR_MSK;
23213 + FEC_FECTFCR(base_addr) = FEC_FECTFCR_FRM | FEC_FECTFCR_GR
23214 + | (FEC_FECTFCR_MSK // disable all but ...
23215 + & ~FEC_FECTFCR_FAE // enable frame accept error
23216 +// & ~FEC_FECTFCR_TXW // enable transmit wait condition
23217 +// & ~FEC_FECTFCR_UF // enable FIFO underflow
23218 + & ~FEC_FECTFCR_OF); // enable FIFO overflow
23219 +
23220 + /* Set the transmit FIFO alarm register */
23221 + FEC_FECTFAR(base_addr) = FEC_FECTFAR_ALARM;
23222 +
23223 + /* Set the Tx FIFO watermark */
23224 + FEC_FECTFWR(base_addr) = FEC_FECTFWR_XWMRK;
23225 +
23226 + /* Enable the transmitter to append the CRC */
23227 + FEC_CTCWR(base_addr) = FEC_CTCWR_TFCW_CRC;
23228 +
23229 + /* Enable the ethernet interrupts */
23230 +// FEC_EIMR(base_addr) = FEC_EIMR_MASK;
23231 + FEC_EIMR(base_addr) = FEC_EIMR_DISABLE
23232 + | FEC_EIR_LC
23233 + | FEC_EIR_RL
23234 + | FEC_EIR_HBERR
23235 + | FEC_EIR_XFUN
23236 + | FEC_EIR_XFERR
23237 + | FEC_EIR_RFERR
23238 + ;
23239 +
23240 +/*
23241 + * JKM --
23242 + *
23243 + * There's a problem with the PHY initialization code --
23244 + * for now assume uboot left it in an initialized state.
23245 + */
23246 +// printk(KERN_INFO "FECOPEN: starting auto-negotiation\n");
23247 +// #ifdef CONFIG_FEC_548x_AUTO_NEGOTIATION
23248 +#if 0
23249 + if ((error_code = init_transceiver(base_addr, &fduplex)) != 0)
23250 + {
23251 + printk("Initialization of the transceiver is failed\n");
23252 + goto ERRORS;
23253 + }
23254 +#else
23255 + fduplex = 1;
23256 +#endif
23257 +// printk(KERN_INFO "FECOPEN: done with auto-negotiation\n");
23258 +
23259 + if (fduplex)
23260 + /* Enable the full duplex mode */
23261 + FEC_TCR(base_addr) = FEC_TCR_FDEN | FEC_TCR_HBC;
23262 + else
23263 + /* Disable reception of frames while transmitting */
23264 + FEC_RCR(base_addr) |= FEC_RCR_DRT;
23265 +
23266 + /* Enable MIB */
23267 + FEC_MIBC(base_addr) = FEC_MIBC_ENABLE;
23268 +
23269 + /* Enable FEC */
23270 + FEC_ECR(base_addr) |= FEC_ECR_ETHEREN;
23271 +
23272 + /* Initialize tx descriptors and start DMA for the transmission */
23273 + for (i = 0; i < FEC_TX_BUF_NUMBER; i++)
23274 + fp->fecpriv_txdesc[i].statCtrl = MCD_FEC_INTERRUPT;
23275 +
23276 + fp->fecpriv_txdesc[i - 1].statCtrl |= MCD_FEC_WRAP;
23277 +
23278 + fp->fecpriv_current_tx = fp->fecpriv_next_tx = 0;
23279 +
23280 + MCD_startDma(fp->fecpriv_fec_tx_channel, (char *) fp->fecpriv_txdesc, 0,
23281 + (unsigned char *) &(FEC_FECTFDR(base_addr)), 0,
23282 + FEC_MAX_FRM_SIZE, 0, fp->fecpriv_initiator_tx,
23283 + FEC_TX_DMA_PRI, MCD_FECTX_DMA | MCD_INTERRUPT,
23284 + MCD_NO_CSUM | MCD_NO_BYTE_SWAP);
23285 +
23286 + /* Initialize rx descriptors and start DMA for the reception */
23287 + for (i = 0; i < FEC_RX_BUF_NUMBER; i++) {
23288 + fp->askb_rx[i] = alloc_skb(FEC_MAXBUF_SIZE + 16, GFP_DMA);
23289 + if (!fp->askb_rx[i]) {
23290 + fp->fecpriv_rxdesc[i].dataPointer = 0;
23291 + fp->fecpriv_rxdesc[i].statCtrl = 0;
23292 + fp->fecpriv_rxdesc[i].length = 0;
23293 + }
23294 + else {
23295 + skb_reserve(fp->askb_rx[i], 16);
23296 + fp->askb_rx[i]->dev = dev;
23297 + fp->fecpriv_rxdesc[i].dataPointer = (unsigned int) virt_to_phys(fp->askb_rx[i]->tail);
23298 + fp->fecpriv_rxdesc[i].statCtrl = MCD_FEC_BUF_READY | MCD_FEC_INTERRUPT;
23299 + fp->fecpriv_rxdesc[i].length = FEC_MAXBUF_SIZE;
23300 + }
23301 + }
23302 +
23303 + fp->fecpriv_rxdesc[i - 1].statCtrl |= MCD_FEC_WRAP;
23304 + fp->fecpriv_current_rx = 0;
23305 +
23306 + /* flush entire data cache before restarting the DMA */
23307 +#if 0
23308 +/* JKM -- currently running with cache turned off */
23309 + DcacheFlushInvalidate();
23310 +#endif
23311 +
23312 + MCD_startDma(fp->fecpriv_fec_rx_channel, (char *) fp->fecpriv_rxdesc, 0,
23313 + (unsigned char *) &(FEC_FECRFDR(base_addr)), 0,
23314 + FEC_MAX_FRM_SIZE, 0, fp->fecpriv_initiator_rx,
23315 + FEC_RX_DMA_PRI, MCD_FECRX_DMA | MCD_INTERRUPT,
23316 + MCD_NO_CSUM | MCD_NO_BYTE_SWAP);
23317 +
23318 + netif_start_queue(dev);
23319 + return 0;
23320 +
23321 +ERRORS:
23322 +
23323 + /* Remove the channels and return with the error code */
23324 + if (fp->fecpriv_fec_rx_channel != -1) {
23325 + dma_disconnect(fp->fecpriv_fec_rx_channel);
23326 + dma_remove_channel_by_number(fp->fecpriv_fec_rx_channel);
23327 + fp->fecpriv_fec_rx_channel = -1;
23328 + }
23329 +
23330 + if (fp->fecpriv_fec_tx_channel != -1) {
23331 + dma_disconnect(fp->fecpriv_fec_tx_channel);
23332 + dma_remove_channel_by_number(fp->fecpriv_fec_tx_channel);
23333 + fp->fecpriv_fec_tx_channel = -1;
23334 + }
23335 +
23336 + return error_code;
23337 +}
23338 +
23339 +/************************************************************************
23340 +* NAME: fec_close
23341 +*
23342 +* DESCRIPTION: This function performs the graceful stop of the
23343 +* transmission and disables FEC
23344 +*
23345 +* RETURNS: This function always returns zero.
23346 +*************************************************************************/
23347 +int fec_close(struct net_device *dev)
23348 +{
23349 + struct fec_priv *fp = netdev_priv(dev);
23350 + unsigned long base_addr = (unsigned long) dev->base_addr;
23351 + unsigned long time;
23352 + int i;
23353 +
23354 + netif_stop_queue(dev);
23355 +
23356 + /* Perform the graceful stop */
23357 + FEC_TCR(base_addr) |= FEC_TCR_GTS;
23358 +
23359 + time = jiffies;
23360 +
23361 + /* Wait for the graceful stop */
23362 + while (!(FEC_EIR(base_addr) & FEC_EIR_GRA) && jiffies - time < FEC_GR_TIMEOUT * HZ)
23363 + schedule();
23364 +
23365 + /* Disable FEC */
23366 + FEC_ECR(base_addr) = FEC_ECR_DISABLE;
23367 +
23368 + /* Reset the DMA channels */
23369 + spin_lock_irq(&fp->fecpriv_lock);
23370 + MCD_killDma(fp->fecpriv_fec_tx_channel);
23371 + spin_unlock_irq(&fp->fecpriv_lock);
23372 + dma_remove_channel_by_number(fp->fecpriv_fec_tx_channel);
23373 + dma_disconnect(fp->fecpriv_fec_tx_channel);
23374 + fp->fecpriv_fec_tx_channel = -1;
23375 +
23376 + for (i = 0; i < FEC_TX_BUF_NUMBER; i++) {
23377 + if (fp->fecpriv_txbuf[i]) {
23378 + kfree(fp->fecpriv_txbuf[i]);
23379 + fp->fecpriv_txbuf[i] = NULL;
23380 + }
23381 + }
23382 +
23383 + spin_lock_irq(&fp->fecpriv_lock);
23384 + MCD_killDma(fp->fecpriv_fec_rx_channel);
23385 + spin_unlock_irq(&fp->fecpriv_lock);
23386 +
23387 + dma_remove_channel_by_number(fp->fecpriv_fec_rx_channel);
23388 + dma_disconnect(fp->fecpriv_fec_rx_channel);
23389 + fp->fecpriv_fec_rx_channel = -1;
23390 +
23391 + for (i = 0; i < FEC_RX_BUF_NUMBER; i++) {
23392 + if (fp->askb_rx[i]) {
23393 + kfree_skb(fp->askb_rx[i]);
23394 + fp->askb_rx[i] = NULL;
23395 + }
23396 + }
23397 +
23398 + return 0;
23399 +}
23400 +
23401 +/************************************************************************
23402 +* +NAME: fec_get_stat
23403 +*
23404 +* RETURNS: This function returns the statistical information.
23405 +*************************************************************************/
23406 +struct net_device_stats * fec_get_stat(struct net_device *dev)
23407 +{
23408 + struct fec_priv *fp = netdev_priv(dev);
23409 + unsigned long base_addr = dev->base_addr;
23410 +
23411 + /* Receive the statistical information */
23412 + fp->fecpriv_stat.rx_packets = FECSTAT_RMON_R_PACKETS(base_addr);
23413 + fp->fecpriv_stat.tx_packets = FECSTAT_RMON_T_PACKETS(base_addr);
23414 + fp->fecpriv_stat.rx_bytes = FECSTAT_RMON_R_OCTETS(base_addr);
23415 + fp->fecpriv_stat.tx_bytes = FECSTAT_RMON_T_OCTETS(base_addr);
23416 +
23417 + fp->fecpriv_stat.multicast = FECSTAT_RMON_R_MC_PKT(base_addr);
23418 + fp->fecpriv_stat.collisions = FECSTAT_RMON_T_COL(base_addr);
23419 +
23420 + fp->fecpriv_stat.rx_length_errors = FECSTAT_RMON_R_UNDERSIZE(base_addr) +
23421 + FECSTAT_RMON_R_OVERSIZE(base_addr) +
23422 + FECSTAT_RMON_R_FRAG(base_addr) +
23423 + FECSTAT_RMON_R_JAB(base_addr);
23424 + fp->fecpriv_stat.rx_crc_errors = FECSTAT_IEEE_R_CRC(base_addr);
23425 + fp->fecpriv_stat.rx_frame_errors = FECSTAT_IEEE_R_ALIGN(base_addr);
23426 + fp->fecpriv_stat.rx_over_errors = FECSTAT_IEEE_R_MACERR(base_addr);
23427 +
23428 + fp->fecpriv_stat.tx_carrier_errors = FECSTAT_IEEE_T_CSERR(base_addr);
23429 + fp->fecpriv_stat.tx_fifo_errors = FECSTAT_IEEE_T_MACERR(base_addr);
23430 + fp->fecpriv_stat.tx_window_errors = FECSTAT_IEEE_T_LCOL(base_addr);
23431 +
23432 + /* I hope that one frame doesn't have more than one error */
23433 + fp->fecpriv_stat.rx_errors = fp->fecpriv_stat.rx_length_errors +
23434 + fp->fecpriv_stat.rx_crc_errors +
23435 + fp->fecpriv_stat.rx_frame_errors +
23436 + fp->fecpriv_stat.rx_over_errors +
23437 + fp->fecpriv_stat.rx_dropped;
23438 + fp->fecpriv_stat.tx_errors = fp->fecpriv_stat.tx_carrier_errors +
23439 + fp->fecpriv_stat.tx_fifo_errors +
23440 + fp->fecpriv_stat.tx_window_errors +
23441 + fp->fecpriv_stat.tx_aborted_errors +
23442 + fp->fecpriv_stat.tx_heartbeat_errors +
23443 + fp->fecpriv_stat.tx_dropped;
23444 +
23445 + return &fp->fecpriv_stat;
23446 +}
23447 +
23448 +/************************************************************************
23449 +* NAME: fec_set_multicast_list
23450 +*
23451 +* DESCRIPTION: This function sets the frame filtering parameters
23452 +*************************************************************************/
23453 +void fec_set_multicast_list(struct net_device *dev)
23454 +{
23455 + struct dev_mc_list *dmi;
23456 + unsigned int crc, data;
23457 + int i, j, k;
23458 + unsigned long base_addr = (unsigned long) dev->base_addr;
23459 +
23460 + if (dev->flags & IFF_PROMISC || dev->flags & IFF_ALLMULTI) {
23461 + /* Allow all incoming frames */
23462 + FEC_GALR(base_addr) = 0xFFFFFFFF;
23463 + FEC_GAUR(base_addr) = 0xFFFFFFFF;
23464 + return;
23465 + }
23466 +
23467 + /* Reset the group address register */
23468 + FEC_GALR(base_addr) = 0x00000000;
23469 + FEC_GAUR(base_addr) = 0x00000000;
23470 +
23471 + /* Process all addresses */
23472 + for (i = 0, dmi = dev->mc_list; i < dev->mc_count; i++, dmi = dmi->next) {
23473 + /* Processing must be only for the group addresses */
23474 + if (!(dmi->dmi_addr[0] & 1))
23475 + continue;
23476 +
23477 + /* Calculate crc value for the current address */
23478 + crc = 0xFFFFFFFF;
23479 + for (j = 0; j < dmi->dmi_addrlen; j++) {
23480 + for (k = 0, data = dmi->dmi_addr[j]; k < 8; k++, data >>= 1) {
23481 + if ((crc ^ data) & 1)
23482 + crc = (crc >> 1) ^ FEC_CRCPOL;
23483 + else
23484 + crc >>= 1;
23485 + }
23486 + }
23487 +
23488 + /* Add this value */
23489 + crc >>= 26;
23490 + crc &= 0x3F;
23491 + if (crc > 31)
23492 + FEC_GAUR(base_addr) |= 0x1 << (crc - 32);
23493 + else
23494 + FEC_GALR(base_addr) |= 0x1 << crc;
23495 + }
23496 +}
23497 +
23498 +/************************************************************************
23499 +* NAME: fec_set_mac_address
23500 +*
23501 +* DESCRIPTION: This function sets the MAC address
23502 +*************************************************************************/
23503 +int fec_set_mac_address(struct net_device *dev, void *p)
23504 +{
23505 + struct fec_priv *fp = netdev_priv(dev);
23506 + unsigned long base_addr = (unsigned long) dev->base_addr;
23507 + struct sockaddr *addr = p;
23508 +
23509 + if (netif_running(dev))
23510 + return -EBUSY;
23511 +
23512 + /* Copy a new address to the device structure */
23513 + memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
23514 +
23515 + /* Copy a new address to the private structure */
23516 + memcpy(fp->fecpriv_mac_addr, addr->sa_data, 6);
23517 +
23518 + /* Set the address to the registers */
23519 + FEC_PALR(base_addr) = (fp->fecpriv_mac_addr[0] << 24) |
23520 + (fp->fecpriv_mac_addr[1] << 16) |
23521 + (fp->fecpriv_mac_addr[2] << 8) |
23522 + fp->fecpriv_mac_addr[3];
23523 + FEC_PAUR(base_addr) = (fp->fecpriv_mac_addr[4] << 24) |
23524 + (fp->fecpriv_mac_addr[5] << 16) |
23525 + 0x8808;
23526 +
23527 + return 0;
23528 +}
23529 +
23530 +/************************************************************************
23531 +* NAME: fec_tx
23532 +*
23533 +* DESCRIPTION: This function starts transmission of the frame using DMA
23534 +*
23535 +* RETURNS: This function always returns zero.
23536 +*************************************************************************/
23537 +int fec_tx(struct sk_buff *skb, struct net_device *dev)
23538 +{
23539 + struct fec_priv *fp = netdev_priv(dev);
23540 + void *data, *data_aligned;
23541 + int offset;
23542 +
23543 + data = kmalloc(skb->len + 15, GFP_DMA | GFP_ATOMIC);
23544 +
23545 + if (!data) {
23546 + fp->fecpriv_stat.tx_dropped++;
23547 + dev_kfree_skb(skb);
23548 + return 0;
23549 + }
23550 +
23551 + offset = (((unsigned long)virt_to_phys(data) + 15) & 0xFFFFFFF0) -
23552 + (unsigned long)virt_to_phys(data);
23553 + data_aligned = (void*)((unsigned long)data + offset);
23554 + memcpy(data_aligned, skb->data, skb->len);
23555 +
23556 + /* flush data cache before initializing the descriptor and starting DMA */
23557 +#if 0
23558 +/* JKM -- currently running with cache turned off */
23559 + DcacheFlushInvalidateCacheBlock((void*)virt_to_phys(data_aligned), skb->len);
23560 +#endif
23561 +
23562 + spin_lock_irq(&fp->fecpriv_lock);
23563 +
23564 + /* Initialize the descriptor */
23565 + fp->fecpriv_txbuf[fp->fecpriv_next_tx] = data;
23566 + fp->fecpriv_txdesc[fp->fecpriv_next_tx].dataPointer = (unsigned int) virt_to_phys(data_aligned);
23567 + fp->fecpriv_txdesc[fp->fecpriv_next_tx].length = skb->len;
23568 + fp->fecpriv_txdesc[fp->fecpriv_next_tx].statCtrl |= (MCD_FEC_END_FRAME | MCD_FEC_BUF_READY);
23569 + fp->fecpriv_next_tx = (fp->fecpriv_next_tx + 1) & FEC_TX_INDEX_MASK;
23570 +
23571 + if (fp->fecpriv_txbuf[fp->fecpriv_current_tx] && fp->fecpriv_current_tx == fp->fecpriv_next_tx)
23572 + netif_stop_queue(dev);
23573 +
23574 + spin_unlock_irq(&fp->fecpriv_lock);
23575 +
23576 + /* Tell the DMA to continue the transmission */
23577 + MCD_continDma(fp->fecpriv_fec_tx_channel);
23578 +
23579 + dev_kfree_skb(skb);
23580 +
23581 + dev->trans_start = jiffies;
23582 +
23583 + return 0;
23584 +}
23585 +
23586 +/************************************************************************
23587 +* NAME: fec_tx_timeout
23588 +*
23589 +* DESCRIPTION: If the interrupt processing of received frames was lost
23590 +* and DMA stopped the reception, this function clears
23591 +* the transmission descriptors and starts DMA
23592 +*
23593 +*************************************************************************/
23594 +void fec_tx_timeout(struct net_device *dev)
23595 +{
23596 + int i;
23597 + struct fec_priv *fp = netdev_priv(dev);
23598 + unsigned long base_addr = (unsigned long) dev->base_addr;
23599 +
23600 + spin_lock_irq(&fp->fecpriv_lock);
23601 + MCD_killDma(fp->fecpriv_fec_tx_channel);
23602 + for (i = 0; i < FEC_TX_BUF_NUMBER; i++) {
23603 + if (fp->fecpriv_txbuf[i]) {
23604 + kfree(fp->fecpriv_txbuf[i]);
23605 + fp->fecpriv_txbuf[i] = NULL;
23606 + }
23607 + fp->fecpriv_txdesc[i].statCtrl = MCD_FEC_INTERRUPT;
23608 + }
23609 + fp->fecpriv_txdesc[i - 1].statCtrl |= MCD_FEC_WRAP;
23610 +
23611 + fp->fecpriv_current_tx = fp->fecpriv_next_tx = 0;
23612 +
23613 + /* Reset FIFOs */
23614 + FEC_FECFRST(base_addr) |= FEC_SW_RST;
23615 + FEC_FECFRST(base_addr) &= ~FEC_SW_RST;
23616 +
23617 + /* Reset and disable FEC */
23618 +// FEC_ECR(base_addr) = FEC_ECR_RESET;
23619 +
23620 + /* Enable FEC */
23621 + FEC_ECR(base_addr) |= FEC_ECR_ETHEREN;
23622 +
23623 + MCD_startDma(fp->fecpriv_fec_tx_channel, (char *) fp->fecpriv_txdesc, 0,
23624 + (unsigned char *) &(FEC_FECTFDR(base_addr)), 0,
23625 + FEC_MAX_FRM_SIZE, 0, fp->fecpriv_initiator_tx,
23626 + FEC_TX_DMA_PRI, MCD_FECTX_DMA | MCD_INTERRUPT,
23627 + MCD_NO_CSUM | MCD_NO_BYTE_SWAP);
23628 +
23629 + spin_unlock_irq(&fp->fecpriv_lock);
23630 +
23631 + netif_wake_queue(dev);
23632 +
23633 +}
23634 +
23635 +/************************************************************************
23636 +* NAME: fec_read_mii
23637 +*
23638 +* DESCRIPTION: This function reads the value from the MII register
23639 +*
23640 +* RETURNS: If no error occurs, this function returns zero.
23641 +*************************************************************************/
23642 +int fec_read_mii(unsigned int base_addr, unsigned int pa, unsigned int ra, unsigned int *data)
23643 +{
23644 + unsigned long time;
23645 +
23646 + /* Clear the MII interrupt bit */
23647 + FEC_EIR(base_addr) = FEC_EIR_MII;
23648 +
23649 + /* Write to the MII management frame register */
23650 + FEC_MMFR(base_addr) = FEC_MMFR_READ | (pa << 23) | (ra << 18);
23651 +
23652 + time = jiffies;
23653 +
23654 + /* Wait for the reading */
23655 + while (!(FEC_EIR(base_addr) & FEC_EIR_MII)) {
23656 + if (jiffies - time > FEC_MII_TIMEOUT * HZ)
23657 + return -ETIME;
23658 + schedule();
23659 + }
23660 +
23661 + /* Clear the MII interrupt bit */
23662 + FEC_EIR(base_addr) = FEC_EIR_MII;
23663 +
23664 + *data = FEC_MMFR(base_addr) & 0x0000FFFF;
23665 +
23666 + return 0;
23667 +}
23668 +
23669 +/************************************************************************
23670 +* NAME: fec_write_mii
23671 +*
23672 +* DESCRIPTION: This function writes the value to the MII register
23673 +*
23674 +* RETURNS: If no error occurs, this function returns zero.
23675 +*************************************************************************/
23676 +int fec_write_mii(unsigned int base_addr, unsigned int pa, unsigned int ra, unsigned int data)
23677 +{
23678 + unsigned long time;
23679 +
23680 + /* Clear the MII interrupt bit */
23681 + FEC_EIR(base_addr) = FEC_EIR_MII;
23682 +
23683 + /* Write to the MII management frame register */
23684 + FEC_MMFR(base_addr) = FEC_MMFR_WRITE | (pa << 23) | (ra << 18) | data;
23685 +
23686 + time = jiffies;
23687 +
23688 + /* Wait for the writing */
23689 + while (!(FEC_EIR(base_addr) & FEC_EIR_MII)) {
23690 + if (jiffies - time > FEC_MII_TIMEOUT * HZ)
23691 + return -ETIME;
23692 + schedule();
23693 + }
23694 +
23695 + /* Clear the MII interrupt bit */
23696 + FEC_EIR(base_addr) = FEC_EIR_MII;
23697 +
23698 + return 0;
23699 +}
23700 +
23701 +/************************************************************************
23702 +* NAME: fec_interrupt_tx_handler
23703 +*
23704 +* DESCRIPTION: This function is called when the data
23705 +* transmission from the buffer to the FEC is completed.
23706 +*
23707 +*************************************************************************/
23708 +void fec_interrupt_fec_tx_handler(struct net_device *dev)
23709 +{
23710 + struct fec_priv *fp = netdev_priv(dev);
23711 +
23712 + /* Release the socket buffer */
23713 + if(fp->fecpriv_txbuf[fp->fecpriv_current_tx]) {
23714 + kfree(fp->fecpriv_txbuf[fp->fecpriv_current_tx]);
23715 + fp->fecpriv_txbuf[fp->fecpriv_current_tx] = NULL;
23716 + }
23717 + fp->fecpriv_current_tx = (fp->fecpriv_current_tx + 1) & FEC_TX_INDEX_MASK;
23718 +
23719 + if (MCD_dmaStatus(fp->fecpriv_fec_tx_channel) == MCD_DONE) {
23720 + for (; fp->fecpriv_current_tx != fp->fecpriv_next_tx; fp->fecpriv_current_tx = (fp->fecpriv_current_tx + 1) & FEC_TX_INDEX_MASK) {
23721 + if(fp->fecpriv_txbuf[fp->fecpriv_current_tx]) {
23722 + kfree(fp->fecpriv_txbuf[fp->fecpriv_current_tx]);
23723 + fp->fecpriv_txbuf[fp->fecpriv_current_tx] = NULL;
23724 + }
23725 + }
23726 + }
23727 +
23728 + if (netif_queue_stopped(dev))
23729 + netif_wake_queue(dev);
23730 +}
23731 +
23732 +/************************************************************************
23733 +* NAME: fec_interrupt_rx_handler
23734 +*
23735 +* DESCRIPTION: This function is called when the data
23736 +* reception from the FEC to the reception buffer is completed.
23737 +*
23738 +*************************************************************************/
23739 +void fec_interrupt_fec_rx_handler(struct net_device *dev)
23740 +{
23741 + struct fec_priv *fp = netdev_priv(dev);
23742 + struct sk_buff *skb;
23743 + int i;
23744 +
23745 + fp->fecpriv_rxflag = 1;
23746 + // Some buffers can be missed
23747 + if(!(fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl & MCD_FEC_END_FRAME))
23748 + {
23749 + // Find a valid index
23750 + for(i = 0; i < FEC_RX_BUF_NUMBER && !(fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl & MCD_FEC_END_FRAME); i++, fp->fecpriv_current_rx = (fp->fecpriv_current_rx + 1) & FEC_RX_INDEX_MASK);
23751 +
23752 + if(i == FEC_RX_BUF_NUMBER)
23753 + {
23754 + // There are no data to process
23755 + // Tell the DMA to continue the reception
23756 + MCD_continDma(fp->fecpriv_fec_rx_channel);
23757 +
23758 + fp->fecpriv_rxflag = 0;
23759 +
23760 + return;
23761 + }
23762 + }
23763 +
23764 + for (; fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl & MCD_FEC_END_FRAME; fp->fecpriv_current_rx = (fp->fecpriv_current_rx + 1) & FEC_RX_INDEX_MASK) {
23765 + if( (fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length <= FEC_MAXBUF_SIZE) &&
23766 + (fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length > 4)) { /* --tym-- */
23767 + skb = fp->askb_rx[fp->fecpriv_current_rx];
23768 + if (!skb)
23769 + fp->fecpriv_stat.rx_dropped++;
23770 + else {
23771 + /* flush data cache before initializing the descriptor and starting DMA */
23772 +// DcacheFlushInvalidateCacheBlock((void*)virt_to_phys(fp->askb_rx[fp->fecpriv_current_rx]->tail), fp->askb_rx[fp->fecpriv_current_rx]->len);
23773 +
23774 + skb_put(skb, fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length - 4);
23775 + skb->protocol = eth_type_trans(skb, dev);
23776 + netif_rx(skb);
23777 + }
23778 + fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl &= ~MCD_FEC_END_FRAME;
23779 + /* allocate new skbuff */
23780 + fp->askb_rx[fp->fecpriv_current_rx] = alloc_skb(FEC_MAXBUF_SIZE + 16, /*GFP_ATOMIC |*/ GFP_DMA);
23781 + if (!fp->askb_rx[fp->fecpriv_current_rx]) {
23782 + fp->fecpriv_rxdesc[fp->fecpriv_current_rx].dataPointer = 0;
23783 + fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length = 0;
23784 + fp->fecpriv_stat.rx_dropped++;
23785 + }
23786 + else {
23787 + skb_reserve(fp->askb_rx[fp->fecpriv_current_rx], 16);
23788 + fp->askb_rx[fp->fecpriv_current_rx]->dev = dev;
23789 +
23790 + /* flush data cache before initializing the descriptor and starting DMA */
23791 +#if 0
23792 +/* JKM -- currently running with cache turned off */
23793 + DcacheFlushInvalidateCacheBlock((void*)virt_to_phys(fp->askb_rx[fp->fecpriv_current_rx]->tail), FEC_MAXBUF_SIZE);
23794 +#endif
23795 +
23796 + fp->fecpriv_rxdesc[fp->fecpriv_current_rx].dataPointer = (unsigned int) virt_to_phys(fp->askb_rx[fp->fecpriv_current_rx]->tail);
23797 + fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length = FEC_MAXBUF_SIZE;
23798 + fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl |= MCD_FEC_BUF_READY;
23799 +
23800 + // flush data cache before initializing the descriptor and starting DMA
23801 +// DcacheFlushInvalidateCacheBlock((void*)virt_to_phys(fp->askb_rx[fp->fecpriv_current_rx]->tail), FEC_MAXBUF_SIZE);
23802 + }
23803 + }
23804 +
23805 + }
23806 +
23807 + /* Tell the DMA to continue the reception */
23808 + MCD_continDma(fp->fecpriv_fec_rx_channel);
23809 +
23810 + fp->fecpriv_rxflag = 0;
23811 +}
23812 +
23813 +/************************************************************************
23814 +* NAME: fec_interrupt_handler
23815 +*
23816 +* DESCRIPTION: This function is called when some special errors occur
23817 +*
23818 +*************************************************************************/
23819 +irqreturn_t fec_interrupt_handler(int irq, void *dev_id)
23820 +{
23821 +
23822 + struct net_device *dev = (struct net_device *)dev_id;
23823 + struct fec_priv *fp = netdev_priv(dev);
23824 + unsigned long base_addr = (unsigned long) dev->base_addr;
23825 + unsigned long events;
23826 +
23827 + /* Read and clear the events */
23828 + events = FEC_EIR(base_addr) & FEC_EIMR(base_addr);
23829 +
23830 + if (events & FEC_EIR_HBERR) {
23831 + fp->fecpriv_stat.tx_heartbeat_errors++;
23832 + FEC_EIR(base_addr) = FEC_EIR_HBERR;
23833 + }
23834 +
23835 + /* receive/transmit FIFO error */
23836 + if (((events & FEC_EIR_RFERR) != 0) || ((events & FEC_EIR_XFERR) != 0)) {
23837 + /* kill DMA receive channel */
23838 + MCD_killDma (fp->fecpriv_fec_rx_channel);
23839 +
23840 + /* kill running transmission by DMA */
23841 + MCD_killDma (fp->fecpriv_fec_tx_channel);
23842 +
23843 + /* Reset FIFOs */
23844 + FEC_FECFRST(base_addr) |= FEC_SW_RST;
23845 + FEC_FECFRST(base_addr) &= ~FEC_SW_RST;
23846 +
23847 + /* reset receive FIFO status register */
23848 + FEC_FECRFSR(base_addr) = FEC_FECRFSR_FAE |
23849 + FEC_FECRFSR_RXW |
23850 + FEC_FECRFSR_UF;
23851 +
23852 + /* reset transmit FIFO status register */
23853 + FEC_FECTFSR(base_addr) = FEC_FECTFSR_FAE |
23854 + FEC_FECTFSR_TXW |
23855 + FEC_FECTFSR_UF |
23856 + FEC_FECTFSR_OF;
23857 +
23858 + /* reset RFERR and XFERR event */
23859 + FEC_EIR(base_addr) = FEC_EIR_RFERR | FEC_EIR_XFERR;
23860 +
23861 + /* stop queue */
23862 + netif_stop_queue(dev);
23863 +
23864 + /* execute reinitialization as tasklet */
23865 + tasklet_schedule(&fp->fecpriv_tasklet_reinit);
23866 +
23867 + fp->fecpriv_stat.rx_dropped++;
23868 + }
23869 +
23870 + /* transmit FIFO underrun */
23871 + if ((events & FEC_EIR_XFUN) != 0) {
23872 + /* reset XFUN event */
23873 + FEC_EIR(base_addr) = FEC_EIR_XFUN;
23874 + fp->fecpriv_stat.tx_aborted_errors++;
23875 + }
23876 +
23877 + /* late collision */
23878 + if ((events & FEC_EIR_LC) != 0) {
23879 + /* reset LC event */
23880 + FEC_EIR(base_addr) = FEC_EIR_LC;
23881 + fp->fecpriv_stat.tx_aborted_errors++;
23882 + }
23883 +
23884 + /* collision retry limit */
23885 + if ((events & FEC_EIR_RL) != 0) {
23886 + /* reset RL event */
23887 + FEC_EIR(base_addr) = FEC_EIR_RL;
23888 + fp->fecpriv_stat.tx_aborted_errors++;
23889 + }
23890 + return 0;
23891 +}
23892 +
23893 +/************************************************************************
23894 +* NAME: fec_interrupt_reinit
23895 +*
23896 +* DESCRIPTION: This function is called from interrupt handler
23897 +* when controller must be reinitialized.
23898 +*
23899 +*************************************************************************/
23900 +void fec_interrupt_fec_reinit(unsigned long data)
23901 +{
23902 + int i;
23903 + struct net_device *dev = (struct net_device*)data;
23904 + struct fec_priv *fp = netdev_priv(dev);
23905 + unsigned long base_addr = (unsigned long) dev->base_addr;
23906 +
23907 + /* Initialize reception descriptors and start DMA for the reception */
23908 + for (i = 0; i < FEC_RX_BUF_NUMBER; i++) {
23909 + if (!fp->askb_rx[i]) {
23910 + fp->askb_rx[i] = alloc_skb(FEC_MAXBUF_SIZE + 16, GFP_ATOMIC | GFP_DMA);
23911 + if (!fp->askb_rx[i]) {
23912 + fp->fecpriv_rxdesc[i].dataPointer = 0;
23913 + fp->fecpriv_rxdesc[i].statCtrl = 0;
23914 + fp->fecpriv_rxdesc[i].length = 0;
23915 + continue;
23916 + }
23917 + fp->askb_rx[i]->dev = dev;
23918 + skb_reserve(fp->askb_rx[i], 16);
23919 + }
23920 + fp->fecpriv_rxdesc[i].dataPointer = (unsigned int) virt_to_phys(fp->askb_rx[i]->tail);
23921 + fp->fecpriv_rxdesc[i].statCtrl = MCD_FEC_BUF_READY | MCD_FEC_INTERRUPT;
23922 + fp->fecpriv_rxdesc[i].length = FEC_MAXBUF_SIZE;
23923 + }
23924 +
23925 + fp->fecpriv_rxdesc[i - 1].statCtrl |= MCD_FEC_WRAP;
23926 + fp->fecpriv_current_rx = 0;
23927 +
23928 + /* restart frame transmission */
23929 + for (i = 0; i < FEC_TX_BUF_NUMBER; i++) {
23930 + if (fp->fecpriv_txbuf[i]) {
23931 + kfree(fp->fecpriv_txbuf[i]);
23932 + fp->fecpriv_txbuf[i] = NULL;
23933 + fp->fecpriv_stat.tx_dropped++;
23934 + }
23935 + fp->fecpriv_txdesc[i].statCtrl = MCD_FEC_INTERRUPT;
23936 + }
23937 + fp->fecpriv_txdesc[i - 1].statCtrl |= MCD_FEC_WRAP;
23938 + fp->fecpriv_current_tx = fp->fecpriv_next_tx = 0;
23939 +
23940 + /* flush entire data cache before restarting the DMA */
23941 +#if 0
23942 +/* JKM -- currently running with cache turned off */
23943 + DcacheFlushInvalidate();
23944 +#endif
23945 +
23946 + /* restart DMA from beginning */
23947 + MCD_startDma(fp->fecpriv_fec_rx_channel,
23948 + (char *) fp->fecpriv_rxdesc, 0,
23949 + (unsigned char *) &(FEC_FECRFDR(base_addr)), 0,
23950 + FEC_MAX_FRM_SIZE, 0, fp->fecpriv_initiator_rx,
23951 + FEC_RX_DMA_PRI, MCD_FECRX_DMA | MCD_INTERRUPT,
23952 + MCD_NO_CSUM | MCD_NO_BYTE_SWAP);
23953 +
23954 + MCD_startDma(fp->fecpriv_fec_tx_channel, (char *) fp->fecpriv_txdesc, 0,
23955 + (unsigned char *) &(FEC_FECTFDR(base_addr)), 0,
23956 + FEC_MAX_FRM_SIZE, 0, fp->fecpriv_initiator_tx,
23957 + FEC_TX_DMA_PRI, MCD_FECTX_DMA | MCD_INTERRUPT,
23958 + MCD_NO_CSUM | MCD_NO_BYTE_SWAP);
23959 +
23960 + /* Enable FEC */
23961 + FEC_ECR(base_addr) |= FEC_ECR_ETHEREN;
23962 +
23963 + netif_wake_queue(dev);
23964 +}
23965 +
23966 +/************************************************************************
23967 +* NAME: fec_interrupt_tx_handler_fec0
23968 +*
23969 +* DESCRIPTION: This is the DMA interrupt handler using for FEC0
23970 +* transmission.
23971 +*
23972 +*************************************************************************/
23973 +void fec_interrupt_fec_tx_handler_fec0(void)
23974 +{
23975 + fec_interrupt_fec_tx_handler(fec_dev[0]);
23976 +}
23977 +
23978 +#ifdef FEC_2
23979 +/************************************************************************
23980 +* NAME: fec_interrupt_tx_handler_fec1
23981 +*
23982 +* DESCRIPTION: This is the DMA interrupt handler using for the FEC1
23983 +* transmission.
23984 +*
23985 +*************************************************************************/
23986 +void fec_interrupt_fec_tx_handler_fec1(void)
23987 +{
23988 + fec_interrupt_fec_tx_handler(fec_dev[1]);
23989 +}
23990 +#endif
23991 +
23992 +/************************************************************************
23993 +* NAME: fec_interrupt_rx_handler_fec0
23994 +*
23995 +* DESCRIPTION: This is the DMA interrupt handler using for the FEC0
23996 +* reception.
23997 +*
23998 +*************************************************************************/
23999 +void fec_interrupt_fec_rx_handler_fec0(void)
24000 +{
24001 + fec_interrupt_fec_rx_handler(fec_dev[0]);
24002 +}
24003 +
24004 +#ifdef FEC_2
24005 +/************************************************************************
24006 +* NAME: fec_interrupt_rx_handler_fec1
24007 +*
24008 +* DESCRIPTION: This is the DMA interrupt handler using for the FEC1
24009 +* reception.
24010 +*
24011 +*************************************************************************/
24012 +void fec_interrupt_fec_rx_handler_fec1(void)
24013 +{
24014 + fec_interrupt_fec_rx_handler(fec_dev[1]);
24015 +}
24016 +
24017 +#endif
24018 +
24019 +#ifndef MODULE
24020 +/************************************************************************
24021 +* NAME: fec_mac_setup0
24022 +*
24023 +* DESCRIPTION: This function sets the MAC address of FEC0 from command line
24024 +*
24025 +*************************************************************************/
24026 +int __init fec_mac_setup0(char *s)
24027 +{
24028 + if(!s || !*s)
24029 + return 1;
24030 +
24031 + if(fec_str_to_mac(s, fec_mac_addr_fec0))
24032 + printk("The MAC address of FEC0 cannot be set from command line");
24033 + return 1;
24034 +}
24035 +
24036 +#ifdef FEC_2
24037 +
24038 +/************************************************************************
24039 +* NAME: fec_mac_setup1
24040 +*
24041 +* DESCRIPTION: This function sets the MAC address of FEC1 from command line
24042 +*
24043 +*************************************************************************/
24044 +int __init fec_mac_setup1(char *s)
24045 +{
24046 + if(!s || !*s)
24047 + return 1;
24048 +
24049 + if(fec_str_to_mac(s, fec_mac_addr_fec1))
24050 + printk("The MAC address of FEC1 cannot be set from command line");
24051 + return 1;
24052 +}
24053 +#endif
24054 +
24055 +/************************************************************************
24056 +* NAME: fec_str_to_mac
24057 +*
24058 +* DESCRIPTION: This function interprets the character string into MAC addr
24059 +*
24060 +*************************************************************************/
24061 +int fec_str_to_mac( char *str_mac, unsigned char* addr)
24062 +{
24063 + unsigned long val;
24064 + char c;
24065 + unsigned long octet[6], *octetptr = octet;
24066 + int i;
24067 +
24068 +again:
24069 + val = 0;
24070 + while ((c = *str_mac) != '\0') {
24071 + if ((c>='0')&&(c<='9')) {
24072 + val = (val * 16) + (c - '0');
24073 + str_mac++;
24074 + continue;
24075 + }
24076 + else if (((c>='a')&&(c<='f'))||((c>='A')&&(c<='F'))) {
24077 + val = (val << 4) + (c + 10 - (((c>='a')&&(c<='f')) ? 'a' : 'A'));
24078 + str_mac++;
24079 + continue;
24080 + }
24081 + break;
24082 + }
24083 + if (*str_mac == ':') {
24084 + *octetptr++ = val, str_mac++;
24085 + if (octetptr >= octet + 6)
24086 + return 1;
24087 + goto again;
24088 + }
24089 +
24090 + /* Check for trailing characters */
24091 + if (*str_mac && !(*str_mac==' '))
24092 + return 1;
24093 +
24094 + *octetptr++ = val;
24095 +
24096 + if ((octetptr - octet)==6) {
24097 + for(i=0;i<=6;i++)
24098 + addr[i]=octet[i];
24099 + }
24100 + else
24101 + return 1;
24102 +
24103 + return 0;
24104 +}
24105 +#endif
24106 --- /dev/null
24107 +++ b/drivers/net/fec/fec.h
24108 @@ -0,0 +1,162 @@
24109 +
24110 +#define FEC_BASE_ADDR_FEC0 ((unsigned int)MCF_MBAR + 0x9000)
24111 +#define FEC_BASE_ADDR_FEC1 ((unsigned int)MCF_MBAR + 0x9800)
24112 +
24113 +//#define FEC_INTC_IMRH_INT_MASK38 (0x00000040)
24114 +//#define FEC_INTC_IMRH_INT_MASK39 (0x00000080)
24115 +//#define FEC_INTC_ICR_FEC0 (0x30)
24116 +//#define FEC_INTC_ICR_FEC1 (0x31)
24117 +#define FEC_FECI2CIRQ (0xFFC0)
24118 +#define FEC_GPIO_PAR_FECI2CIRQ *(volatile unsigned short*)((unsigned int)MCF_MBAR + 0xA44)
24119 +//#define FEC_INTC_ICRn(x) (*(volatile unsigned char *)(void*)((unsigned int) MCF_MBAR + 0x000740+((x)*0x001)))
24120 +//#define FEC_INTC_IMRH *(volatile unsigned int*)((unsigned int)MCF_MBAR + 0x000708)
24121 +
24122 +#define FEC_ECR_DISABLE (0x00000000)
24123 +
24124 +#define FEC_ECR(x) *(volatile unsigned int *)(x + 0x024)
24125 +#define FEC_EIR(x) *(volatile unsigned int*)(x + 0x004)
24126 +#define FEC_PALR(x) *(volatile unsigned int*)(x + 0x0E4)
24127 +#define FEC_PAUR(x) *(volatile unsigned int*)(x + 0x0E8)
24128 +#define FEC_IALR(x) *(volatile unsigned int*)(x + 0x11C)
24129 +#define FEC_IAUR(x) *(volatile unsigned int*)(x + 0x118)
24130 +#define FEC_GALR(x) *(volatile unsigned int*)(x + 0x124)
24131 +#define FEC_GAUR(x) *(volatile unsigned int*)(x + 0x120)
24132 +#define FEC_RCR(x) *(volatile unsigned int*)(x + 0x084)
24133 +#define FEC_FECRFCR(x) *(volatile unsigned int*)(x + 0x18C)
24134 +#define FEC_FECRFAR(x) *(volatile unsigned int*)(x + 0x198)
24135 +#define FEC_FECTFCR(x) *(volatile unsigned int*)(x + 0x1AC)
24136 +#define FEC_FECTFAR(x) *(volatile unsigned int*)(x + 0x1B8)
24137 +#define FEC_FECTFWR(x) *(volatile unsigned int*)(x + 0x144)
24138 +#define FEC_CTCWR(x) *(volatile unsigned int*)(x + 0x1C8)
24139 +#define FEC_EIMR(x) *(volatile unsigned int*)(x + 0x008)
24140 +#define FEC_TCR(x) *(volatile unsigned int*)(x + 0x0C4)
24141 +#define FEC_MIBC(x) *(volatile unsigned int*)(x + 0x064)
24142 +#define FEC_MSCR(x) *(volatile unsigned int*)(x + 0x044)
24143 +#define FEC_FECTFDR(x) *(volatile unsigned int*)(x + 0x1A4)
24144 +#define FEC_FECRFDR(x) *(volatile unsigned int*)(x + 0x184)
24145 +#define FEC_FECTFSR(x) *(volatile unsigned int*)(x + 0x1A8)
24146 +#define FEC_FECRFSR(x) *(volatile unsigned int*)(x + 0x188)
24147 +#define FECSTAT_RMON_R_PACKETS(x) *(volatile unsigned int*)(x + 0x284)
24148 +#define FECSTAT_RMON_T_PACKETS(x) *(volatile unsigned int*)(x + 0x204)
24149 +#define FECSTAT_RMON_R_OCTETS(x) *(volatile unsigned int*)(x + 0x2C4)
24150 +#define FECSTAT_RMON_T_OCTETS(x) *(volatile unsigned int*)(x + 0x244)
24151 +#define FECSTAT_RMON_R_UNDERSIZE(x) *(volatile unsigned int*)(x + 0x294)
24152 +#define FECSTAT_RMON_R_OVERSIZE(x) *(volatile unsigned int*)(x + 0x298)
24153 +#define FECSTAT_RMON_R_FRAG(x) *(volatile unsigned int*)(x + 0x29C)
24154 +#define FECSTAT_RMON_R_JAB(x) *(volatile unsigned int*)(x + 0x2A0)
24155 +#define FECSTAT_RMON_R_MC_PKT(x) *(volatile unsigned int*)(x + 0x28C)
24156 +#define FECSTAT_RMON_T_COL(x) *(volatile unsigned int*)(x + 0x224)
24157 +#define FECSTAT_IEEE_R_ALIGN(x) *(volatile unsigned int*)(x + 0x2D4)
24158 +#define FECSTAT_IEEE_R_CRC(x) *(volatile unsigned int*)(x + 0x2D0)
24159 +#define FECSTAT_IEEE_R_MACERR(x) *(volatile unsigned int*)(x + 0x2D8)
24160 +#define FECSTAT_IEEE_T_CSERR(x) *(volatile unsigned int*)(x + 0x268)
24161 +#define FECSTAT_IEEE_T_MACERR(x) *(volatile unsigned int*)(x + 0x264)
24162 +#define FECSTAT_IEEE_T_LCOL(x) *(volatile unsigned int*)(x + 0x25C)
24163 +#define FECSTAT_IEEE_R_OCTETS_OK(x) *(volatile unsigned int*)(x + 0x2E0)
24164 +#define FECSTAT_IEEE_T_OCTETS_OK(x) *(volatile unsigned int*)(x + 0x274)
24165 +#define FECSTAT_IEEE_R_DROP(x) *(volatile unsigned int*)(x + 0x2C8)
24166 +#define FECSTAT_IEEE_T_DROP(x) *(volatile unsigned int*)(x + 0x248)
24167 +#define FECSTAT_IEEE_R_FRAME_OK(x) *(volatile unsigned int*)(x + 0x2CC)
24168 +#define FECSTAT_IEEE_T_FRAME_OK(x) *(volatile unsigned int*)(x + 0x24C)
24169 +#define FEC_MMFR(x) *(volatile unsigned int*)(x + 0x040)
24170 +#define FEC_FECFRST(x) *(volatile unsigned int*)(x + 0x1C4)
24171 +
24172 +#define FEC_MAX_FRM_SIZE (1518)
24173 +#define FEC_MAXBUF_SIZE (1520)
24174 +
24175 +// Register values
24176 +#define FEC_ECR_RESET (0x00000001)
24177 +#define FEC_EIR_CLEAR (0xFFFFFFFF)
24178 +#define FEC_EIR_RL (0x00100000)
24179 +#define FEC_EIR_HBERR (0x80000000)
24180 +#define FEC_EIR_BABR (0x40000000) // babbling receive error
24181 +#define FEC_EIR_BABT (0x20000000) // babbling transmit error
24182 +#define FEC_EIR_TXF (0x08000000) // transmit frame interrupt
24183 +#define FEC_EIR_MII (0x00800000) // MII interrupt
24184 +#define FEC_EIR_LC (0x00200000) // late collision
24185 +#define FEC_EIR_XFUN (0x00080000) // transmit FIFO underrun
24186 +#define FEC_EIR_XFERR (0x00040000) // transmit FIFO error
24187 +#define FEC_EIR_RFERR (0x00020000) // receive FIFO error
24188 +#define FEC_RCR_MAX_FRM_SIZE (FEC_MAX_FRM_SIZE << 16)
24189 +#define FEC_RCR_MII (0x00000004)
24190 +#define FEC_FECRFCR_FAE (0x00400000) // frame accept error
24191 +#define FEC_FECRFCR_RXW (0x00200000) // receive wait condition
24192 +#define FEC_FECRFCR_UF (0x00100000) // receive FIFO underflow
24193 +#define FEC_FECRFCR_FRM (0x08000000)
24194 +#define FEC_FECRFCR_GR (0x7 << 24)
24195 +
24196 +#define FEC_EIMR_DISABLE (0x00000000)
24197 +
24198 +#define FEC_FECRFAR_ALARM (0x300)
24199 +#define FEC_FECTFCR_FRM (0x08000000)
24200 +#define FEC_FECTFCR_GR (0x7 << 24)
24201 +#define FEC_FECTFCR_FAE (0x00400000) // frame accept error
24202 +#define FEC_FECTFCR_TXW (0x00040000) // transmit wait condition
24203 +#define FEC_FECTFCR_UF (0x00100000) // transmit FIFO underflow
24204 +#define FEC_FECTFCR_OF (0x00080000) // transmit FIFO overflow
24205 +
24206 +#define FEC_FECTFAR_ALARM (0x100)
24207 +#define FEC_FECTFWR_XWMRK (0x00000000)
24208 +
24209 +#define FEC_FECTFSR_MSK (0xC0B00000)
24210 +#define FEC_FECTFSR_TXW (0x40000000) // transmit wait condition
24211 +#define FEC_FECTFSR_FAE (0x00800000) // frame accept error
24212 +#define FEC_FECTFSR_UF (0x00200000) // transmit FIFO underflow
24213 +#define FEC_FECTFSR_OF (0x00100000) // transmit FIFO overflow
24214 +
24215 +#define FEC_FECRFSR_MSK (0x80F00000)
24216 +#define FEC_FECRFSR_FAE (0x00800000) // frame accept error
24217 +#define FEC_FECRFSR_RXW (0x00400000) // receive wait condition
24218 +#define FEC_FECRFSR_UF (0x00200000) // receive FIFO underflow
24219 +
24220 +#define FEC_CTCWR_TFCW_CRC (0x03000000)
24221 +#define FEC_TCR_FDEN (0x00000004)
24222 +#define FEC_TCR_HBC (0x00000002)
24223 +#define FEC_RCR_DRT (0x00000002)
24224 +#define FEC_EIMR_MASK (FEC_EIR_RL | FEC_EIR_HBERR)
24225 +#define FEC_ECR_ETHEREN (0x00000002)
24226 +#define FEC_FECTFCR_MSK (0x00FC0000)
24227 +#define FEC_FECRFCR_MSK (0x00F80000)
24228 +#define FEC_EIR_GRA (0x10000000)
24229 +#define FEC_TCR_GTS (0x00000001)
24230 +#define FEC_MIBC_ENABLE (0x00000000)
24231 +#define FEC_MIB_LEN (228)
24232 +#define FEC_PHY_ADDR (0x01)
24233 +
24234 +#define FEC_RX_DMA_PRI (6)
24235 +#define FEC_TX_DMA_PRI (6)
24236 +
24237 +#define FEC_TX_BUF_NUMBER (8)
24238 +#define FEC_RX_BUF_NUMBER (64)
24239 +
24240 +#define FEC_TX_INDEX_MASK (0x7)
24241 +#define FEC_RX_INDEX_MASK (0x3f)
24242 +
24243 +#define FEC_RX_DESC_FEC0 SYS_SRAM_FEC_START
24244 +#define FEC_TX_DESC_FEC0 FEC_RX_DESC_FEC0 + FEC_RX_BUF_NUMBER * sizeof(MCD_bufDescFec)
24245 +
24246 +#define FEC_RX_DESC_FEC1 SYS_SRAM_FEC_START + SYS_SRAM_FEC_SIZE/2
24247 +#define FEC_TX_DESC_FEC1 FEC_RX_DESC_FEC1 + FEC_RX_BUF_NUMBER * sizeof(MCD_bufDescFec)
24248 +
24249 +#define FEC_EIR_MII (0x00800000)
24250 +#define FEC_MMFR_READ (0x60020000)
24251 +#define FEC_MMFR_WRITE (0x50020000)
24252 +
24253 +#define FEC_FLAGS_RX (0x00000001)
24254 +
24255 +#define FEC_CRCPOL (0xEDB88320)
24256 +
24257 +#define FEC_MII_TIMEOUT (2)
24258 +#define FEC_GR_TIMEOUT (1)
24259 +#define FEC_TX_TIMEOUT (1)
24260 +#define FEC_RX_TIMEOUT (1)
24261 +
24262 +#define FEC_SW_RST 0x2000000
24263 +#define FEC_RST_CTL 0x1000000
24264 +
24265 +int fec_read_mii(unsigned int base_addr, unsigned int pa, unsigned int ra,
24266 + unsigned int *data);
24267 +int fec_write_mii(unsigned int base_addr, unsigned int pa, unsigned int ra,
24268 + unsigned int data);
24269 +
24270 +#define init_transceiver ks8721_init_transceiver
24271 --- /dev/null
24272 +++ b/drivers/net/fec/Kconfig
24273 @@ -0,0 +1,25 @@
24274 +config FEC_548x
24275 + tristate "MCF547x/MCF548x Fast Ethernet Controller support"
24276 + depends on M547X_8X
24277 + help
24278 + The MCF547x and MCF548x have a built-in Fast Ethernet Controller.
24279 + Saying Y here will include support for this device in the kernel.
24280 +
24281 + To compile this driver as a module, choose M here: the module
24282 + will be called fecm.
24283 +
24284 +config FEC_548x_AUTO_NEGOTIATION
24285 + bool "Enable Auto-Negotiation"
24286 + depends on FEC_548x
24287 + help
24288 + This option enables the FEC to automatically detect the
24289 + half/full duplex mode and the network speed at initialization
24290 + If you want this, say Y.
24291 +
24292 +config FEC_548x_ENABLE_FEC2
24293 + bool "Enable the second FEC"
24294 + depends on FEC_548x
24295 + help
24296 + This enables the second FEC on the 547x/548x. If you want to use
24297 + it, say Y.
24298 +
24299 --- /dev/null
24300 +++ b/drivers/net/fec/ks8721.c
24301 @@ -0,0 +1,125 @@
24302 +#include <linux/module.h>
24303 +#include <linux/kernel.h>
24304 +#include <linux/string.h>
24305 +#include <linux/ptrace.h>
24306 +#include <linux/errno.h>
24307 +#include <linux/ioport.h>
24308 +#include <linux/slab.h>
24309 +#include <linux/interrupt.h>
24310 +#include <linux/pci.h>
24311 +#include <linux/init.h>
24312 +#include <linux/delay.h>
24313 +#include <linux/netdevice.h>
24314 +#include <linux/etherdevice.h>
24315 +#include <linux/skbuff.h>
24316 +#include <linux/spinlock.h>
24317 +#include <linux/workqueue.h>
24318 +#include <linux/bitops.h>
24319 +
24320 +#if 0
24321 +#include <linux/config.h>
24322 +#include <linux/sched.h>
24323 +#include <linux/errno.h>
24324 +#include <asm/coldfire.h>
24325 +#endif
24326 +#include <asm/coldfire.h>
24327 +#include <asm/mcfsim.h>
24328 +
24329 +#include "fec.h"
24330 +#include "ks8721.h"
24331 +
24332 +#ifdef CONFIG_FEC_548x_AUTO_NEGOTIATION
24333 +#define KS8721_AUTO_NEGOTIATION_ENABLE
24334 +#endif
24335 +
24336 +/************************************************************************
24337 +* +NAME: ks8721_init_transceiver
24338 +*
24339 +* DESCRIPTION: This function initializes the transceiver
24340 +*
24341 +* RETURNS: If no error occurs, this function returns zero.
24342 +* Otherwise, it returns 1
24343 +*************************************************************************/
24344 +
24345 +int ks8721_init_transceiver(unsigned long base_addr, int *fduplex)
24346 +{
24347 +
24348 + int data;
24349 + unsigned long time;
24350 + int flag = 1;
24351 +
24352 + int result;
24353 +
24354 + // Set the frequency of MII
24355 + FEC_MSCR(base_addr) = FEC_MII_SPEED;
24356 +
24357 + // Reset
24358 + if ((result = fec_write_mii(base_addr, FEC_PHY_ADDR, KS8721_CTRL, KS8721_CTRL_RESET)))
24359 + return result;
24360 +
24361 + // Read back
24362 + if ((result = fec_read_mii(base_addr, FEC_PHY_ADDR, KS8721_CTRL, &data)) != 0)
24363 + return result;
24364 +
24365 + // If reset bit is set, return
24366 + if (data & KS8721_CTRL_RESET)
24367 + return -ETIME;
24368 +
24369 +#ifdef KS8721_AUTO_NEGOTIATION_ENABLE
24370 +
24371 + // Disable the auto-negotiation
24372 + if ((result = fec_write_mii(base_addr, FEC_PHY_ADDR, KS8721_CTRL, 0)) != 0)
24373 + return result;
24374 +
24375 + // Set the auto-negotiation advertisement register
24376 + if ((result = fec_write_mii(base_addr, FEC_PHY_ADDR, KS8721_ANADV, KS8721_ANADV_ADV_ALL)) != 0)
24377 + return result;
24378 +
24379 + // Enable the auto-negotiation
24380 + if ((result = fec_write_mii(base_addr, FEC_PHY_ADDR, KS8721_CTRL, KS8721_CTRL_AN_ENABLE)) != 0)
24381 + return result;
24382 +
24383 + // Read PHY status register
24384 + if ((result = fec_read_mii(base_addr, FEC_PHY_ADDR, KS8721_STAT, &data)) != 0)
24385 + return result;
24386 + // Set the current time
24387 + time = jiffies;
24388 +
24389 + // Wait for the auto-negotiation completion
24390 + while (!(data & KS8721_STAT_ANCOMPLETE))
24391 + {
24392 +
24393 + if (jiffies - time > KS8721_TIMEOUT * HZ)
24394 + {
24395 + flag = 0;
24396 + break;
24397 + }
24398 +
24399 + schedule();
24400 +
24401 + // Read PHY status register
24402 + if ((result = fec_read_mii(base_addr, FEC_PHY_ADDR, KS8721_STAT, &data)) != 0)
24403 + return result;
24404 + }
24405 +
24406 + if (flag)
24407 + {
24408 + // Set the duplex flag
24409 + if (data & KS8721_STAT_FDUPLEX)
24410 + *fduplex = 1;
24411 + else
24412 + *fduplex = 0;
24413 +
24414 + return 0;
24415 + }
24416 +
24417 +#endif
24418 +
24419 + // Set the default mode (Full duplex, 100 Mbps)
24420 + if ((result = fec_write_mii(base_addr, FEC_PHY_ADDR, KS8721_CTRL, KS8721_CTRL_DEFAULT_MODE)) != 0)
24421 + return result;
24422 + *fduplex = KS8721_CTRL_DEFAULT_MODE & 0x100;
24423 +
24424 + return 0;
24425 +
24426 +}
24427 --- /dev/null
24428 +++ b/drivers/net/fec/ks8721.h
24429 @@ -0,0 +1,21 @@
24430 +
24431 +#define FEC_MII_SPEED (((unsigned int)(MCF_BUSCLK / 5000000)) << 1)
24432 +
24433 +// Numbers of the transceiver registers
24434 +#define KS8721_CTRL 0x00
24435 +#define KS8721_ANADV 0x04
24436 +#define KS8721_STAT 0x01
24437 +
24438 +// Register values
24439 +#define KS8721_CTRL_RESET 0x8000
24440 +#define KS8721_ANADV_ADV_ALL 0x01E1
24441 +#define KS8721_CTRL_AN_ENABLE 0x1280
24442 +#define KS8721_CTRL_DEFAULT_MODE 0x2100
24443 +#define KS8721_STAT_ANCOMPLETE 0x0020
24444 +#define KS8721_STAT_LINK 0x0004
24445 +#define KS8721_STAT_FDUPLEX 0x5000
24446 +
24447 +// Timeout for the auto-negotiation mode
24448 +#define KS8721_TIMEOUT 5
24449 +
24450 +int ks8721_init_transceiver(unsigned long base_addr, int *fduplex);
24451 --- /dev/null
24452 +++ b/drivers/net/fec/Makefile
24453 @@ -0,0 +1,7 @@
24454 +#
24455 +# Makefile for the FEC ethernet driver
24456 +#
24457 +
24458 +obj-$(CONFIG_FEC_548x) += fecm.o
24459 +
24460 +fecm-objs := fec.o ks8721.o
24461 --- a/drivers/net/fec.c
24462 +++ b/drivers/net/fec.c
24463 @@ -23,6 +23,9 @@
24464 *
24465 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
24466 * Copyright (c) 2004-2006 Macq Electronique SA.
24467 + *
24468 + * Coldfire bug fixes and cleanup by Kurt Mahan (kmahan@freescale.com)
24469 + * Copyright 2007-2008 Freescale Semiconductor, Inc. All Rights Reserved.
24470 */
24471
24472 #include <linux/module.h>
24473 @@ -51,7 +54,9 @@
24474
24475 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || \
24476 defined(CONFIG_M5272) || defined(CONFIG_M528x) || \
24477 - defined(CONFIG_M520x) || defined(CONFIG_M532x)
24478 + defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
24479 + defined(CONFIG_M5445X)
24480 +
24481 #include <asm/coldfire.h>
24482 #include <asm/mcfsim.h>
24483 #include "fec.h"
24484 @@ -82,6 +87,11 @@ static unsigned int fec_hw[] = {
24485 (MCF_MBAR+0x30000),
24486 #elif defined(CONFIG_M532x)
24487 (MCF_MBAR+0xfc030000),
24488 +#elif defined(CONFIG_M5445X)
24489 + (MCF_MBAR+0xfc030000),
24490 +#if defined(CONFIG_FEC2)
24491 + (MCF_MBAR+0xfc034000),
24492 +#endif
24493 #else
24494 &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec),
24495 #endif
24496 @@ -172,7 +182,7 @@ typedef struct {
24497 * account when setting it.
24498 */
24499 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
24500 - defined(CONFIG_M520x) || defined(CONFIG_M532x)
24501 + defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_M5445X)
24502 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
24503 #else
24504 #define OPT_FRAME_SIZE 0
24505 @@ -213,6 +223,7 @@ struct fec_enet_private {
24506 uint phy_speed;
24507 phy_info_t const *phy;
24508 struct work_struct phy_task;
24509 + volatile fec_t *phy_hwp;
24510
24511 uint sequence_done;
24512 uint mii_phy_task_queued;
24513 @@ -349,7 +360,8 @@ fec_enet_start_xmit(struct sk_buff *skb,
24514 if (bdp->cbd_bufaddr & 0x3) {
24515 unsigned int index;
24516 index = bdp - fep->tx_bd_base;
24517 - memcpy(fep->tx_bounce[index], (void *) bdp->cbd_bufaddr, bdp->cbd_datlen);
24518 + memcpy(fep->tx_bounce[index],
24519 + (void *)skb->data, bdp->cbd_datlen);
24520 bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]);
24521 }
24522
24523 @@ -702,7 +714,7 @@ fec_enet_mii(struct net_device *dev)
24524 uint mii_reg;
24525
24526 fep = netdev_priv(dev);
24527 - ep = fep->hwp;
24528 + ep = fep->phy_hwp;
24529 mii_reg = ep->fec_mii_data;
24530
24531 spin_lock(&fep->lock);
24532 @@ -753,7 +765,7 @@ mii_queue(struct net_device *dev, int re
24533 mii_tail = mip;
24534 } else {
24535 mii_head = mii_tail = mip;
24536 - fep->hwp->fec_mii_data = regval;
24537 + fep->phy_hwp->fec_mii_data = regval;
24538 }
24539 } else {
24540 retval = 1;
24541 @@ -1151,8 +1163,7 @@ static phy_info_t const phy_info_ks8721b
24542 };
24543
24544 /* ------------------------------------------------------------------------- */
24545 -/* register definitions for the DP83848 */
24546 -
24547 +/* register definitions for the DP83848 and DP83849 */
24548 #define MII_DP8384X_PHYSTST 16 /* PHY Status Register */
24549
24550 static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev)
24551 @@ -1186,27 +1197,50 @@ static void mii_parse_dp8384x_sr2(uint m
24552 *s |= PHY_STAT_FAULT;
24553 }
24554
24555 +static phy_cmd_t const phy_cmd_dp8384x_ack_int[] = {
24556 + { mk_mii_end, }
24557 + };
24558 +
24559 +static phy_cmd_t const phy_cmd_dp8384x_shutdown[] = {
24560 + { mk_mii_end, }
24561 + };
24562 +
24563 static phy_info_t phy_info_dp83848= {
24564 - 0x020005c9,
24565 - "DP83848",
24566 + .id = 0x020005c9,
24567 + .name = "DP83848",
24568
24569 - (const phy_cmd_t []) { /* config */
24570 + .config = (const phy_cmd_t []) { /* config */
24571 { mk_mii_read(MII_REG_CR), mii_parse_cr },
24572 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
24573 { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 },
24574 { mk_mii_end, }
24575 },
24576 - (const phy_cmd_t []) { /* startup - enable interrupts */
24577 + .startup = (const phy_cmd_t []) { /* startup - enable interrupts */
24578 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
24579 { mk_mii_read(MII_REG_SR), mii_parse_sr },
24580 { mk_mii_end, }
24581 },
24582 - (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */
24583 + .ack_int = phy_cmd_dp8384x_ack_int,
24584 + .shutdown = phy_cmd_dp8384x_shutdown,
24585 +};
24586 +
24587 +static phy_info_t phy_info_dp83849 = {
24588 + .id = 0x020005ca,
24589 + .name = "DP83849",
24590 +
24591 + .config = (const phy_cmd_t []) { /* config */
24592 + { mk_mii_read(MII_REG_CR), mii_parse_cr },
24593 + { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
24594 + { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 },
24595 { mk_mii_end, }
24596 },
24597 - (const phy_cmd_t []) { /* shutdown */
24598 + .startup = (const phy_cmd_t []) { /* startup - enable interrupts */
24599 + { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
24600 + { mk_mii_read(MII_REG_SR), mii_parse_sr },
24601 { mk_mii_end, }
24602 },
24603 + .ack_int = phy_cmd_dp8384x_ack_int,
24604 + .shutdown = phy_cmd_dp8384x_shutdown,
24605 };
24606
24607 /* ------------------------------------------------------------------------- */
24608 @@ -1218,6 +1252,7 @@ static phy_info_t const * const phy_info
24609 &phy_info_am79c874,
24610 &phy_info_ks8721bl,
24611 &phy_info_dp83848,
24612 + &phy_info_dp83849,
24613 NULL
24614 };
24615
24616 @@ -1799,6 +1834,138 @@ static void __inline__ fec_uncache(unsig
24617
24618 /* ------------------------------------------------------------------------- */
24619
24620 +#elif defined(CONFIG_M5445X)
24621 +/*
24622 + * Code specific for M5445X
24623 + */
24624 +
24625 +static void __inline__ fec_request_intrs(struct net_device *dev)
24626 +{
24627 + struct fec_enet_private *fep;
24628 + int b;
24629 + static const struct idesc {
24630 + char *name;
24631 + unsigned short irq;
24632 + } *idp, id[] = {
24633 + { "fec(TXF)", 36 },
24634 + { "fec(TXB)", 37 },
24635 + { "fec(TXFIFO)", 38 },
24636 + { "fec(TXCR)", 39 },
24637 + { "fec(RXF)", 40 },
24638 + { "fec(RXB)", 41 },
24639 + { "fec(MII)", 42 },
24640 + { "fec(LC)", 43 },
24641 + { "fec(HBERR)", 44 },
24642 + { "fec(GRA)", 45 },
24643 + { "fec(EBERR)", 46 },
24644 + { "fec(BABT)", 47 },
24645 + { "fec(BABR)", 48 },
24646 + { NULL },
24647 + };
24648 +
24649 + fep = netdev_priv(dev);
24650 + b = (fep->index) ? 77 : 64;
24651 +
24652 + /* Setup interrupt handlers. */
24653 + for (idp = id; idp->name; idp++) {
24654 + if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED,
24655 + idp->name, dev) != 0)
24656 + printk(KERN_ERR "FEC: Could not alloc %s IRQ(%d)!\n",
24657 + idp->name, b+idp->irq);
24658 + }
24659 +
24660 + if (fep->index) {
24661 + /* Configure RMII */
24662 + MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC &
24663 + MCF_GPIO_PAR_FEC_FEC1_MASK) |
24664 + MCF_GPIO_PAR_FEC_FEC1_RMII_GPIO;
24665 + } else {
24666 + /* Configure RMII */
24667 + MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC &
24668 + MCF_GPIO_PAR_FEC_FEC0_MASK) |
24669 + MCF_GPIO_PAR_FEC_FEC0_RMII_GPIO;
24670 + }
24671 +
24672 + /* Set up gpio outputs for MII lines on FEC0 */
24673 + MCF_GPIO_PAR_FECI2C |= (0 |
24674 + MCF_GPIO_PAR_FECI2C_MDIO0_MDIO0 |
24675 + MCF_GPIO_PAR_FECI2C_MDC0_MDC0);
24676 +}
24677 +
24678 +static void __inline__ fec_set_mii(struct net_device *dev,
24679 + struct fec_enet_private *fep)
24680 +{
24681 + volatile fec_t *fecp;
24682 +
24683 + fecp = fep->hwp;
24684 + fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
24685 + fecp->fec_x_cntrl = 0x00;
24686 +
24687 + /*
24688 + * Set MII speed to 2.5 MHz
24689 + */
24690 + fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
24691 + fecp->fec_mii_speed = fep->phy_speed;
24692 +
24693 + fec_restart(dev, 0);
24694 +}
24695 +
24696 +static void __inline__ fec_get_mac(struct net_device *dev)
24697 +{
24698 + struct fec_enet_private *fep = netdev_priv(dev);
24699 + volatile fec_t *fecp;
24700 + unsigned char *iap, tmpaddr[ETH_ALEN];
24701 +
24702 + fecp = fep->hwp;
24703 +
24704 + if (FEC_FLASHMAC) {
24705 + /*
24706 + * Get MAC address from FLASH.
24707 + * If it is all 1's or 0's, use the default.
24708 + */
24709 + iap = FEC_FLASHMAC;
24710 + if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
24711 + (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
24712 + iap = fec_mac_default;
24713 + if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
24714 + (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
24715 + iap = fec_mac_default;
24716 + } else {
24717 + *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
24718 + *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
24719 + iap = &tmpaddr[0];
24720 + }
24721 +
24722 + memcpy(dev->dev_addr, iap, ETH_ALEN);
24723 +
24724 + /* Adjust MAC if using default MAC address */
24725 + if (iap == fec_mac_default)
24726 + dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] +
24727 + fep->index;
24728 +}
24729 +
24730 +static void __inline__ fec_enable_phy_intr(void)
24731 +{
24732 +}
24733 +
24734 +static void __inline__ fec_disable_phy_intr(void)
24735 +{
24736 +}
24737 +
24738 +static void __inline__ fec_phy_ack_intr(void)
24739 +{
24740 +}
24741 +
24742 +static void __inline__ fec_localhw_setup(void)
24743 +{
24744 +}
24745 +
24746 +static void __inline__ fec_uncache(unsigned long addr)
24747 +{
24748 +}
24749 +
24750 +/* ------------------------------------------------------------------------- */
24751 +
24752
24753 #else
24754
24755 @@ -2305,7 +2472,7 @@ fec_set_mac_address(struct net_device *d
24756
24757 }
24758
24759 -/* Initialize the FEC Ethernet on 860T (or ColdFire 5272).
24760 +/* Initialize the FEC Ethernet.
24761 */
24762 /*
24763 * XXX: We need to clean up on failure exits here.
24764 @@ -2326,7 +2493,7 @@ int __init fec_enet_init(struct net_devi
24765
24766 /* Allocate memory for buffer descriptors.
24767 */
24768 - mem_addr = __get_free_page(GFP_KERNEL);
24769 + mem_addr = __get_free_page(GFP_DMA);
24770 if (mem_addr == 0) {
24771 printk("FEC: allocate descriptor memory failed?\n");
24772 return -ENOMEM;
24773 @@ -2339,6 +2506,11 @@ int __init fec_enet_init(struct net_devi
24774 fep->index = index;
24775 fep->hwp = fecp;
24776 fep->netdev = dev;
24777 +#ifdef CONFIG_FEC_SHARED_PHY
24778 + fep->phy_hwp = (volatile fec_t *) fec_hw[index & ~1];
24779 +#else
24780 + fep->phy_hwp = fecp;
24781 +#endif
24782
24783 /* Whack a reset. We should wait for this.
24784 */
24785 @@ -2375,7 +2547,7 @@ int __init fec_enet_init(struct net_devi
24786
24787 /* Allocate a page.
24788 */
24789 - mem_addr = __get_free_page(GFP_KERNEL);
24790 + mem_addr = __get_free_page(GFP_DMA);
24791 /* XXX: missing check for allocation failure */
24792
24793 fec_uncache(mem_addr);
24794 @@ -2400,7 +2572,7 @@ int __init fec_enet_init(struct net_devi
24795 bdp = fep->tx_bd_base;
24796 for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_RING_SIZE; i++) {
24797 if (j >= FEC_ENET_TX_FRPPG) {
24798 - mem_addr = __get_free_page(GFP_KERNEL);
24799 + mem_addr = __get_free_page(GFP_DMA);
24800 j = 1;
24801 } else {
24802 mem_addr += FEC_ENET_TX_FRSIZE;
24803 @@ -2462,7 +2634,11 @@ int __init fec_enet_init(struct net_devi
24804 * remainder of the interface.
24805 */
24806 fep->phy_id_done = 0;
24807 +#ifndef CONFIG_FEC_SHARED_PHY
24808 fep->phy_addr = 0;
24809 +#else
24810 + fep->phy_addr = fep->index;
24811 +#endif
24812 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
24813
24814 index++;
24815 --- a/drivers/net/fec.h
24816 +++ b/drivers/net/fec.h
24817 @@ -14,7 +14,7 @@
24818 /****************************************************************************/
24819
24820 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
24821 - defined(CONFIG_M520x) || defined(CONFIG_M532x)
24822 + defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_M5445X)
24823 /*
24824 * Just figures, Motorola would have to change the offsets for
24825 * registers in the same peripheral device on different models
24826 --- a/drivers/net/Kconfig
24827 +++ b/drivers/net/Kconfig
24828 @@ -351,6 +351,8 @@ config MACB
24829
24830 source "drivers/net/arm/Kconfig"
24831
24832 +source "drivers/net/fec/Kconfig"
24833 +
24834 config AX88796
24835 tristate "ASIX AX88796 NE2000 clone support"
24836 depends on ARM || MIPS || SUPERH
24837 @@ -1973,7 +1975,7 @@ config 68360_ENET
24838
24839 config FEC
24840 bool "FEC ethernet controller (of ColdFire CPUs)"
24841 - depends on M523x || M527x || M5272 || M528x || M520x
24842 + depends on M523x || M527x || M5272 || M528x || M520x || M5445X
24843 help
24844 Say Y here if you want to use the built-in 10/100 Fast ethernet
24845 controller on some Motorola ColdFire processors.
24846 @@ -1985,6 +1987,12 @@ config FEC2
24847 Say Y here if you want to use the second built-in 10/100 Fast
24848 ethernet controller on some Motorola ColdFire processors.
24849
24850 +config FEC_SHARED_PHY
24851 + bool "Shared PHY interface(on some ColdFire designs)"
24852 + depends on FEC2
24853 + help
24854 + Say Y here if both PHYs are controlled via a single channel.
24855 +
24856 config FEC_MPC52xx
24857 tristate "MPC52xx FEC driver"
24858 depends on PPC_MERGE && PPC_MPC52xx && PPC_BESTCOMM_FEC
24859 --- a/drivers/net/Makefile
24860 +++ b/drivers/net/Makefile
24861 @@ -226,6 +226,8 @@ obj-$(CONFIG_ENC28J60) += enc28j60.o
24862
24863 obj-$(CONFIG_MACB) += macb.o
24864
24865 +obj-$(CONFIG_FEC_548x) += fec/
24866 +
24867 obj-$(CONFIG_ARM) += arm/
24868 obj-$(CONFIG_DEV_APPLETALK) += appletalk/
24869 obj-$(CONFIG_TR) += tokenring/
24870 --- a/drivers/pci/access.c
24871 +++ b/drivers/pci/access.c
24872 @@ -23,6 +23,7 @@ static DEFINE_SPINLOCK(pci_lock);
24873 #define PCI_word_BAD (pos & 1)
24874 #define PCI_dword_BAD (pos & 3)
24875
24876 +#ifdef NL_ORIGINAL
24877 #define PCI_OP_READ(size,type,len) \
24878 int pci_bus_read_config_##size \
24879 (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
24880 @@ -37,7 +38,20 @@ int pci_bus_read_config_##size \
24881 spin_unlock_irqrestore(&pci_lock, flags); \
24882 return res; \
24883 }
24884 -
24885 +#else /* NL_ORIGINAL */
24886 +#define PCI_OP_READ(size,type,len) \
24887 +int pci_bus_read_config_##size \
24888 + (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
24889 +{ \
24890 + int res; \
24891 + unsigned long flags; \
24892 + if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
24893 + spin_lock_irqsave(&pci_lock, flags); \
24894 + res = bus->ops->read(bus, devfn, pos, len, (u32 *)value); \
24895 + spin_unlock_irqrestore(&pci_lock, flags); \
24896 + return res; \
24897 +}
24898 +#endif /* NL_ORIGINAL */
24899 #define PCI_OP_WRITE(size,type,len) \
24900 int pci_bus_write_config_##size \
24901 (struct pci_bus *bus, unsigned int devfn, int pos, type value) \
24902 --- a/drivers/pci/Makefile
24903 +++ b/drivers/pci/Makefile
24904 @@ -39,6 +39,7 @@ obj-$(CONFIG_PPC) += setup-bus.o
24905 obj-$(CONFIG_MIPS) += setup-bus.o setup-irq.o
24906 obj-$(CONFIG_X86_VISWS) += setup-irq.o
24907 obj-$(CONFIG_MN10300) += setup-bus.o
24908 +obj-$(CONFIG_M54455) += setup-bus.o setup-irq.o
24909
24910 #
24911 # ACPI Related PCI FW Functions
24912 --- a/drivers/rtc/rtc-rs5c372.c
24913 +++ b/drivers/rtc/rtc-rs5c372.c
24914 @@ -15,7 +15,6 @@
24915
24916 #define DRV_VERSION "0.5"
24917
24918 -
24919 /*
24920 * Ricoh has a family of I2C based RTCs, which differ only slightly from
24921 * each other. Differences center on pinout (e.g. how many interrupts,
24922 @@ -60,6 +59,15 @@
24923 /* to read (style 1) or write registers starting at R */
24924 #define RS5C_ADDR(R) (((R) << 4) | 0)
24925
24926 +#ifdef CONFIG_M547X_8X
24927 +#define DRV_NAME "rv5c387a"
24928 +/* i2c configuration */
24929 +#define RV5C387_I2C_ADDR 0x32
24930 +static unsigned short normal_i2c[] = {
24931 + RV5C387_I2C_ADDR, I2C_CLIENT_END
24932 +};
24933 +I2C_CLIENT_INSMOD; /* defines addr_data */
24934 +#endif
24935
24936 enum rtc_type {
24937 rtc_undef = 0,
24938 @@ -506,14 +514,14 @@ static int rs5c372_probe(struct i2c_clie
24939 err = -ENODEV;
24940 goto exit;
24941 }
24942 -
24943 - if (!(rs5c372 = kzalloc(sizeof(struct rs5c372), GFP_KERNEL))) {
24944 + rs5c372 = kzalloc(sizeof(struct rs5c372), GFP_KERNEL);
24945 + if (!rs5c372) {
24946 err = -ENOMEM;
24947 goto exit;
24948 }
24949
24950 /* we read registers 0x0f then 0x00-0x0f; skip the first one */
24951 - rs5c372->regs=&rs5c372->buf[1];
24952 + rs5c372->regs = &rs5c372->buf[1];
24953
24954 rs5c372->client = client;
24955 i2c_set_clientdata(client, rs5c372);
24956 @@ -605,7 +613,7 @@ static int rs5c372_probe(struct i2c_clie
24957 case rtc_rv5c386: s = "rv5c386"; break;
24958 case rtc_rv5c387a: s = "rv5c387a"; break;
24959 default: s = "chip"; break;
24960 - }; s;}),
24961 + }; s; }),
24962 rs5c372->time24 ? "24hr" : "am/pm"
24963 );
24964
24965 @@ -645,12 +653,61 @@ static int rs5c372_remove(struct i2c_cli
24966 return 0;
24967 }
24968
24969 +#ifdef CONFIG_M547X_8X
24970 +static int rv5c387_probe(struct i2c_adapter *adapter, int addr, int kind)
24971 +{
24972 + int rc = 0;
24973 + struct i2c_client *new_client = NULL;
24974 +
24975 + if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) {
24976 + rc = -ENODEV;
24977 + printk(KERN_DEBUG "%s i2c_check_functionality\n", __FUNCTION__);
24978 + goto failout;
24979 + }
24980 +
24981 + new_client = kzalloc(sizeof(struct i2c_client), GFP_KERNEL);
24982 + if (new_client == NULL) {
24983 + rc = -ENOMEM;
24984 + printk(KERN_DEBUG "%s kzalloc new_client\n", __FUNCTION__);
24985 + goto failout;
24986 + }
24987 +
24988 + new_client->addr = addr;
24989 + new_client->adapter = adapter;
24990 + new_client->driver = &rs5c372_driver;
24991 + new_client->flags = 0;
24992 + strcpy(new_client->name, DRV_NAME);
24993 +
24994 + rc = i2c_attach_client(new_client);
24995 + if (rc < 0) {
24996 + printk(KERN_DEBUG "%s i2c_attach_client\n", __FUNCTION__);
24997 + goto failout;
24998 + }
24999 +
25000 + rs5c372_probe(new_client);
25001 + return 0;
25002 +failout:
25003 + kfree(new_client);
25004 + return rc;
25005 +}
25006 +
25007 +static int
25008 +rv5c387_attach_adapter(struct i2c_adapter *adapter)
25009 +{
25010 + return i2c_probe(adapter, &addr_data, rv5c387_probe);
25011 +}
25012 +#endif
25013 +
25014 static struct i2c_driver rs5c372_driver = {
25015 .driver = {
25016 .name = "rtc-rs5c372",
25017 },
25018 +#ifdef CONFIG_M547X_8X
25019 + .attach_adapter = &rv5c387_attach_adapter,
25020 +#else
25021 .probe = rs5c372_probe,
25022 .remove = rs5c372_remove,
25023 +#endif
25024 };
25025
25026 static __init int rs5c372_init(void)
25027 --- a/drivers/serial/Kconfig
25028 +++ b/drivers/serial/Kconfig
25029 @@ -979,6 +979,12 @@ config SERIAL_COLDFIRE
25030 This driver supports the built-in serial ports of the Motorola ColdFire
25031 family of CPUs.
25032
25033 +config SERIAL_COLDFIRE_IRDA
25034 + bool "ColdFire IRDA support"
25035 + depends on SERIAL_COLDFIRE
25036 + help
25037 + This driver supports IRDA on the Motorola ColdFire.
25038 +
25039 config SERIAL_MCF
25040 bool "Coldfire serial support (new style driver)"
25041 depends on COLDFIRE
25042 --- a/drivers/serial/mcfserial.c
25043 +++ b/drivers/serial/mcfserial.c
25044 @@ -45,7 +45,14 @@
25045 #include <asm/coldfire.h>
25046 #include <asm/mcfsim.h>
25047 #include <asm/mcfuart.h>
25048 +#if defined(CONFIG_M547X_8X)
25049 +#include <asm/m5485sim.h>
25050 +#include <asm/m5485psc.h>
25051 +#include <asm/m5485gpio.h>
25052 +#endif
25053 +#ifdef CONFIG_NETtel
25054 #include <asm/nettel.h>
25055 +#endif
25056 #include <asm/uaccess.h>
25057 #include "mcfserial.h"
25058
25059 @@ -61,7 +68,8 @@ struct timer_list mcfrs_timer_struct;
25060 #define CONSOLE_BAUD_RATE 38400
25061 #define DEFAULT_CBAUD B38400
25062 #elif defined(CONFIG_MOD5272) || defined(CONFIG_M5208EVB) || \
25063 - defined(CONFIG_M5329EVB) || defined(CONFIG_GILBARCO)
25064 + defined(CONFIG_M5329EVB) || defined(CONFIG_GILBARCO) || \
25065 + defined(CONFIG_M5445X) || defined(CONFIG_M547X_8X)
25066 #define CONSOLE_BAUD_RATE 115200
25067 #define DEFAULT_CBAUD B115200
25068 #elif defined(CONFIG_ARNEWSH) || defined(CONFIG_FREESCALE) || \
25069 @@ -94,12 +102,17 @@ static struct tty_driver *mcfrs_serial_d
25070 #undef SERIAL_DEBUG_FLOW
25071
25072 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
25073 - defined(CONFIG_M520x) || defined(CONFIG_M532x)
25074 + defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_M5445X) || \
25075 + defined(CONFIG_M547X_8X)
25076 #define IRQBASE (MCFINT_VECBASE+MCFINT_UART0)
25077 #else
25078 #define IRQBASE 73
25079 #endif
25080
25081 +#ifdef CONFIG_SERIAL_COLDFIRE_IRDA
25082 +#define SERIAL_IRDA_LINE (2)
25083 +#endif
25084 +
25085 /*
25086 * Configuration table, UARTs to look for at startup.
25087 */
25088 @@ -114,7 +127,11 @@ static struct mcf_serial mcfrs_table[] =
25089 { /* ttyS1 */
25090 .magic = 0,
25091 .addr = (volatile unsigned char *) (MCF_MBAR+MCFUART_BASE2),
25092 +#if defined(CONFIG_M547X_8X)
25093 + .irq = IRQBASE-1,
25094 +#else
25095 .irq = IRQBASE+1,
25096 +#endif
25097 .flags = ASYNC_BOOT_AUTOCONF,
25098 },
25099 #endif
25100 @@ -122,7 +139,11 @@ static struct mcf_serial mcfrs_table[] =
25101 { /* ttyS2 */
25102 .magic = 0,
25103 .addr = (volatile unsigned char *) (MCF_MBAR+MCFUART_BASE3),
25104 +#if defined(CONFIG_M547X_8X)
25105 + .irq = IRQBASE-2,
25106 +#else
25107 .irq = IRQBASE+2,
25108 +#endif
25109 .flags = ASYNC_BOOT_AUTOCONF,
25110 },
25111 #endif
25112 @@ -130,7 +151,11 @@ static struct mcf_serial mcfrs_table[] =
25113 { /* ttyS3 */
25114 .magic = 0,
25115 .addr = (volatile unsigned char *) (MCF_MBAR+MCFUART_BASE4),
25116 +#if defined(CONFIG_M547X_8X)
25117 + .irq = IRQBASE-3,
25118 +#else
25119 .irq = IRQBASE+3,
25120 +#endif
25121 .flags = ASYNC_BOOT_AUTOCONF,
25122 },
25123 #endif
25124 @@ -372,6 +397,9 @@ static inline void receive_chars(struct
25125 static inline void transmit_chars(struct mcf_serial *info)
25126 {
25127 volatile unsigned char *uartp;
25128 +#ifdef CONFIG_SERIAL_COLDFIRE_IRDA
25129 + int i;
25130 +#endif
25131
25132 uartp = info->addr;
25133
25134 @@ -383,13 +411,36 @@ static inline void transmit_chars(struct
25135 }
25136
25137 if ((info->xmit_cnt <= 0) || info->tty->stopped) {
25138 +#ifdef CONFIG_SERIAL_COLDFIRE_IRDA
25139 + if (info->line == SERIAL_IRDA_LINE) {
25140 + /* Enable receiver for IRDA */
25141 + uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETRX;
25142 + /* reset RX */
25143 + uartp[MCFUART_UCR] = MCFUART_UCR_TXENABLE | MCFUART_UCR_RXENABLE;
25144 + }
25145 +#endif
25146 info->imr &= ~MCFUART_UIR_TXREADY;
25147 uartp[MCFUART_UIMR] = info->imr;
25148 return;
25149 }
25150
25151 while (uartp[MCFUART_USR] & MCFUART_USR_TXREADY) {
25152 +#ifdef CONFIG_SERIAL_COLDFIRE_IRDA
25153 + if (info->line == SERIAL_IRDA_LINE) {
25154 + while (!(uartp[MCFUART_USR] & MCFUART_USR_TXEMPTY));
25155 + i = 0;
25156 + /* delay for settle */
25157 +#if defined(CONFIG_M548X)
25158 + udelay(1);
25159 +#elif defined(CONFIG_M547X)
25160 + udelay(2);
25161 +#else
25162 + while (i++ < 25000) udelay(1);
25163 +#endif
25164 + }
25165 +#endif
25166 uartp[MCFUART_UTB] = info->xmit_buf[info->xmit_tail++];
25167 +
25168 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
25169 info->stats.tx++;
25170 if (--info->xmit_cnt <= 0)
25171 @@ -409,7 +460,12 @@ irqreturn_t mcfrs_interrupt(int irq, voi
25172 struct mcf_serial *info;
25173 unsigned char isr;
25174
25175 +/* JKM -- revisit! IRQ compute */
25176 +#if defined(CONFIG_M547X_8X)
25177 + info = &mcfrs_table[(IRQBASE - irq)];
25178 +#else
25179 info = &mcfrs_table[(irq - IRQBASE)];
25180 +#endif
25181 isr = info->addr[MCFUART_UISR] & info->imr;
25182
25183 if (isr & MCFUART_UIR_RXREADY)
25184 @@ -541,6 +597,28 @@ static int startup(struct mcf_serial * i
25185 */
25186 mcfrs_change_speed(info);
25187
25188 +#ifdef CONFIG_SERIAL_COLDFIRE_IRDA
25189 + if (info->line == SERIAL_IRDA_LINE) {
25190 + /* Put PSC in IrDA mode */
25191 + MCF_PSC_SICR(info->line) = MCF_PSC_SICR_SIM_SIR;
25192 +
25193 + /* Set pulse width to 1.6 uS */
25194 + MCF_PSC_IRSDR(info->line) = (uint8_t)
25195 + (16 * (CONFIG_MCFCLK / 10000000));
25196 + MCF_PSC_IRCR1(info->line) = MCF_PSC_IRCR1_SPUL;
25197 + MCF_PSC_IRCR2(info->line) = 0;
25198 +
25199 + /* Enable RTS to send */
25200 + MCF_PSC_OPSET(info->line) = MCF_PSC_OPSET_RTS;
25201 +
25202 + /* Setup FIFO Alarms */
25203 + MCF_PSC_RFAR(info->line) = MCF_PSC_RFAR_ALARM(248);
25204 + MCF_PSC_TFAR(info->line) = MCF_PSC_TFAR_ALARM(248);
25205 +
25206 + MCF_PSC_RFCR(info->line) = MCF_PSC_RFCR_FRMEN | MCF_PSC_RFCR_GR(4);
25207 + MCF_PSC_TFCR(info->line) = MCF_PSC_TFCR_FRMEN | MCF_PSC_RFCR_GR(4);
25208 + }
25209 +#endif
25210 /*
25211 * Lastly enable the UART transmitter and receiver, and
25212 * interrupt enables.
25213 @@ -562,10 +640,20 @@ static void shutdown(struct mcf_serial *
25214 {
25215 volatile unsigned char *uartp;
25216 unsigned long flags;
25217 +#ifdef CONFIG_SERIAL_COLDFIRE_IRDA
25218 + unsigned long delay_counter = 0;
25219 +#endif
25220
25221 if (!(info->flags & ASYNC_INITIALIZED))
25222 return;
25223 -
25224 +#ifdef CONFIG_SERIAL_COLDFIRE_IRDA
25225 + uartp = (volatile unsigned char *) info->addr;
25226 + while (!(uartp[MCFUART_USR] & MCFUART_USR_TXEMPTY)) {
25227 + if(delay_counter++ > 25000)
25228 + break;
25229 + udelay(10);
25230 + }
25231 +#endif
25232 #ifdef SERIAL_DEBUG_OPEN
25233 printk("Shutting down serial port %d (irq %d)....\n", info->line,
25234 info->irq);
25235 @@ -794,10 +882,19 @@ static int mcfrs_write(struct tty_struct
25236
25237 local_irq_disable();
25238 uartp = info->addr;
25239 +
25240 +#ifdef CONFIG_SERIAL_COLDFIRE_IRDA
25241 + if (info->line == SERIAL_IRDA_LINE) {
25242 + /* Disable IRDA receiver*/
25243 + uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETRX; /* reset RX */
25244 + uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETTX; /* reset TX */
25245 +
25246 + uartp[MCFUART_UCR] = MCFUART_UCR_TXENABLE;
25247 + }
25248 +#endif
25249 info->imr |= MCFUART_UIR_TXREADY;
25250 uartp[MCFUART_UIMR] = info->imr;
25251 local_irq_restore(flags);
25252 -
25253 return total;
25254 }
25255
25256 @@ -858,9 +955,21 @@ static void mcfrs_throttle(struct tty_st
25257
25258 if (serial_paranoia_check(info, tty->name, "mcfrs_throttle"))
25259 return;
25260 -
25261 +#ifdef CONFIG_SERIAL_COLDFIRE_IRDA
25262 + if (I_IXOFF(tty)) {
25263 + /* Force STOP_CHAR (xoff) out */
25264 + volatile unsigned char *uartp;
25265 + unsigned long flags;
25266 + uartp = (volatile unsigned char *) info->addr;
25267 + local_irq_save(flags);
25268 + info->imr |= MCFUART_UIR_TXREADY;
25269 + uartp[MCFUART_UIMR] = info->imr;
25270 + local_irq_restore(flags);
25271 + }
25272 +#else
25273 if (I_IXOFF(tty))
25274 info->x_char = STOP_CHAR(tty);
25275 +#endif
25276
25277 /* Turn off RTS line (do this atomic) */
25278 }
25279 @@ -881,8 +990,22 @@ static void mcfrs_unthrottle(struct tty_
25280 if (I_IXOFF(tty)) {
25281 if (info->x_char)
25282 info->x_char = 0;
25283 +#ifdef CONFIG_SERIAL_COLDFIRE_IRDA
25284 + else {
25285 + /* Force START_CHAR (xon) out */
25286 + volatile unsigned char *uartp;
25287 + unsigned long flags;
25288 + info->x_char = START_CHAR(tty);
25289 + uartp = (volatile unsigned char *) info->addr;
25290 + local_irq_save(flags);
25291 + info->imr |= MCFUART_UIR_TXREADY;
25292 + uartp[MCFUART_UIMR] = info->imr;
25293 + local_irq_restore(flags);
25294 + }
25295 +#else
25296 else
25297 info->x_char = START_CHAR(tty);
25298 +#endif
25299 }
25300
25301 /* Assert RTS line (do this atomic) */
25302 @@ -1130,12 +1253,17 @@ static int mcfrs_ioctl(struct tty_struct
25303 static void mcfrs_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
25304 {
25305 struct mcf_serial *info = (struct mcf_serial *)tty->driver_data;
25306 +#ifdef CONFIG_SERIAL_COLDFIRE_IRDA
25307 + int i = 0; /* hush GCC */
25308 +#endif
25309
25310 if (tty->termios->c_cflag == old_termios->c_cflag)
25311 return;
25312
25313 +#ifdef CONFIG_SERIAL_COLDFIRE_IRDA
25314 + while (i++ < 35000) udelay(1);
25315 +#endif
25316 mcfrs_change_speed(info);
25317 -
25318 if ((old_termios->c_cflag & CRTSCTS) &&
25319 !(tty->termios->c_cflag & CRTSCTS)) {
25320 tty->hw_stopped = 0;
25321 @@ -1604,6 +1732,36 @@ static void mcfrs_irqinit(struct mcf_ser
25322 /* GPIOs also must be initalized, depends on board */
25323 break;
25324 }
25325 +#elif defined(CONFIG_M5445X)
25326 + volatile unsigned char *uartp;
25327 + uartp = info->addr;
25328 + switch (info->line) {
25329 + case 0:
25330 + MCF_GPIO_PAR_UART |= 0x000F;
25331 + break;
25332 + case 1:
25333 + MCF_GPIO_PAR_UART |= 0x0FF0;
25334 + break;
25335 + case 2:
25336 + /* GPIOs also must be initalized, depends on board */
25337 + break;
25338 + }
25339 +#elif defined(CONFIG_M547X_8X)
25340 + volatile unsigned char *uartp;
25341 + uartp = (volatile unsigned char *)info->addr;
25342 +
25343 + if (info->line > 3) {
25344 + printk("SERIAL: don't know how to handle UART %d interrupt?\n",
25345 + info->line);
25346 + return;
25347 + }
25348 +
25349 + /* Set GPIO port register to enable PSC(port) signals */
25350 + MCF_PAR_PSCn(info->line) = (0
25351 + | MCF_PAR_PSC_TXD
25352 + | MCF_PAR_PSC_RXD);
25353 +
25354 + MCF_ICR(info->irq - 64) = ILP_PSCn(info->line);
25355 #else
25356 volatile unsigned char *icrp, *uartp;
25357
25358 @@ -1966,7 +2124,9 @@ struct console mcfrs_console = {
25359
25360 static int __init mcfrs_console_init(void)
25361 {
25362 +#if !(defined(CONFIG_M5445X) || defined(CONFIG_M547X_8X))
25363 register_console(&mcfrs_console);
25364 +#endif
25365 return 0;
25366 }
25367
25368 --- /dev/null
25369 +++ b/drivers/spi/coldfire_edma.c
25370 @@ -0,0 +1,446 @@
25371 +/*
25372 + *
25373 + * coldfire_edma.c - eDMA driver for Coldfire MCF5445x
25374 + *
25375 + * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
25376 + *
25377 + * Copyright Freescale Semiconductor, Inc. 2007
25378 + *
25379 + * This program is free software; you can redistribute it and/or modify it
25380 + * under the terms of the GNU General Public License as published by the
25381 + * Free Software Foundation; either version 2 of the License, or (at your
25382 + * option) any later version.
25383 + */
25384 +
25385 +#include <linux/init.h>
25386 +#include <linux/module.h>
25387 +#include <asm/virtconvert.h>
25388 +#include <asm/coldfire.h>
25389 +#include <linux/fs.h>
25390 +#include <linux/cdev.h>
25391 +#include <linux/seq_file.h>
25392 +#include <linux/proc_fs.h>
25393 +#ifdef CONFIG_M5445X
25394 +#include <asm/mcf5445x_edma.h>
25395 +#include <asm/mcf5445x_intc.h>
25396 +#endif /* CONFIG_M5445X */
25397 +#include <asm/coldfire_edma.h>
25398 +
25399 +/*
25400 + * Callback handler data for each TCD
25401 + */
25402 +struct edma_isr_record {
25403 + edma_irq_handler irq_handler; /* interrupt handler */
25404 + edma_error_handler error_handler; /* error interrupt handler */
25405 + void *arg; /* argument to pass back */
25406 + int allocated; /* busy flag */
25407 + spinlock_t *lock; /* spin lock (optional) */
25408 + const char *device_id; /* dev id string, used in procfs */
25409 +};
25410 +
25411 +/*
25412 + * Device structure
25413 + */
25414 +struct coldfire_edma_dev {
25415 + struct cdev cdev; /* character device */
25416 + struct edma_isr_record dma_interrupt_handlers[EDMA_CHANNELS];
25417 +};
25418 +
25419 +/* allocated major device number */
25420 +static int coldfire_dma_major;
25421 +
25422 +/* device driver structure */
25423 +static struct coldfire_edma_dev *devp = NULL;
25424 +
25425 +/* device driver file operations */
25426 +struct file_operations coldfire_edma_fops = {
25427 + .owner = THIS_MODULE,
25428 +};
25429 +
25430 +/**
25431 + * dmaisr - eDMA channel interrupt handler
25432 + * @irq: interrupt number
25433 + * @dev_id: argument
25434 + */
25435 +static int dmaisr(int irq, void *dev_id)
25436 +{
25437 + int channel = irq - EDMA_INT_CONTROLLER_BASE - EDMA_INT_CHANNEL_BASE;
25438 + int result = IRQ_HANDLED;
25439 +
25440 + if ((devp != NULL) &&
25441 + (devp->dma_interrupt_handlers[channel].irq_handler)) {
25442 + /* call user irq handler */
25443 + if (devp->dma_interrupt_handlers[channel].lock)
25444 + spin_lock(devp->dma_interrupt_handlers[channel].lock);
25445 +
25446 + result = devp->dma_interrupt_handlers[channel].irq_handler(
25447 + channel, devp->dma_interrupt_handlers[channel].arg);
25448 +
25449 + if (devp->dma_interrupt_handlers[channel].lock)
25450 + spin_unlock(devp->dma_interrupt_handlers[channel].lock);
25451 + } else {
25452 + /* no irq handler so just ack it */
25453 + confirm_edma_interrupt_handled(channel);
25454 + printk(EDMA_DRIVER_NAME ": No handler for DMA channel %d\n",
25455 + channel);
25456 + }
25457 +
25458 + return result;
25459 +}
25460 +
25461 +/**
25462 + * dma_error_isr - eDMA error interrupt handler
25463 + * @irq: interrupt number
25464 + * @dev_id: argument
25465 + */
25466 +static int dma_error_isr(int irq, void* dev_id)
25467 +{
25468 + u16 err;
25469 + int i;
25470 +
25471 + err = MCF_EDMA_ERR;
25472 + for (i=0; i<EDMA_CHANNELS; i++) {
25473 + if (err & (1<<i)) {
25474 + if (devp!=NULL && devp->dma_interrupt_handlers[i].error_handler)
25475 + devp->dma_interrupt_handlers[i].error_handler(i, devp->dma_interrupt_handlers[i].arg);
25476 + else
25477 + printk(KERN_WARNING EDMA_DRIVER_NAME ": DMA error on channel %d\n", i);
25478 + }
25479 + }
25480 +
25481 + MCF_EDMA_CERR = MCF_EDMA_CERR_CAER;
25482 + return IRQ_HANDLED;
25483 +}
25484 +
25485 +/**
25486 + * set_edma_params - Set transfer control descriptor (TCD)
25487 + * @channel: channel number
25488 + * @source: source address
25489 + * @dest: destination address
25490 + * @attr: attributes
25491 + * @soff: source offset
25492 + * @nbytes: number of bytes to be transfered in minor loop
25493 + * @slast: last source address adjustment
25494 + * @citer: major loop count
25495 + * @biter: beginning minor loop count
25496 + * @doff: destination offset
25497 + * @dlast_sga: last destination address adjustment
25498 + * @major_int: generate interrupt after each major loop
25499 + * @disable_req: disable DMA request after major loop
25500 + */
25501 +void set_edma_params(int channel, u32 source, u32 dest,
25502 + u32 attr, u32 soff, u32 nbytes, u32 slast,
25503 + u32 citer, u32 biter, u32 doff, u32 dlast_sga,
25504 + int major_int, int disable_req)
25505 +{
25506 +
25507 + if (channel<0 || channel>EDMA_CHANNELS)
25508 + return;
25509 +
25510 + MCF_EDMA_TCD_SADDR(channel) = source;
25511 + MCF_EDMA_TCD_DADDR(channel) = dest;
25512 + MCF_EDMA_TCD_ATTR(channel) = attr;
25513 + MCF_EDMA_TCD_SOFF(channel) = MCF_EDMA_TCD_SOFF_SOFF(soff);
25514 + MCF_EDMA_TCD_NBYTES(channel) = MCF_EDMA_TCD_NBYTES_NBYTES(nbytes);
25515 + MCF_EDMA_TCD_SLAST(channel) = MCF_EDMA_TCD_SLAST_SLAST(slast);
25516 + MCF_EDMA_TCD_CITER(channel) = MCF_EDMA_TCD_CITER_CITER(citer);
25517 + MCF_EDMA_TCD_BITER(channel)=MCF_EDMA_TCD_BITER_BITER(biter);
25518 + MCF_EDMA_TCD_DOFF(channel) = MCF_EDMA_TCD_DOFF_DOFF(doff);
25519 + MCF_EDMA_TCD_DLAST_SGA(channel) = MCF_EDMA_TCD_DLAST_SGA_DLAST_SGA(dlast_sga);
25520 +
25521 + /* interrupt at the end of major loop */
25522 + if (major_int)
25523 + MCF_EDMA_TCD_CSR(channel) |= MCF_EDMA_TCD_CSR_INT_MAJOR;
25524 + else
25525 + MCF_EDMA_TCD_CSR(channel) &= ~MCF_EDMA_TCD_CSR_INT_MAJOR;
25526 +
25527 + /* disable request at the end of major loop of transfer or not*/
25528 + if (disable_req)
25529 + MCF_EDMA_TCD_CSR(channel) |= MCF_EDMA_TCD_CSR_D_REQ;
25530 + else
25531 + MCF_EDMA_TCD_CSR(channel) &= ~MCF_EDMA_TCD_CSR_D_REQ;
25532 +}
25533 +EXPORT_SYMBOL(set_edma_params);
25534 +
25535 +/**
25536 + * init_edma - Initialize the eDMA controller
25537 + */
25538 +void init_edma(void)
25539 +{
25540 + MCF_EDMA_CR = 0;
25541 +}
25542 +EXPORT_SYMBOL(init_edma);
25543 +
25544 +/**
25545 + * request_edma_channel - Request an eDMA channel
25546 + * @channel: channel number
25547 + * @handler: dma handler
25548 + * @error_handler: dma error handler
25549 + * @arg: argument to pass back
25550 + * @lock: optional spinlock to hold over interrupt
25551 + * @device_id: device id
25552 + *
25553 + * Returns 0 if success or a negative value if failure
25554 + */
25555 +int request_edma_channel(int channel,
25556 + edma_irq_handler handler,
25557 + edma_error_handler error_handler,
25558 + void *arg,
25559 + spinlock_t *lock,
25560 + const char *device_id )
25561 +{
25562 + if (devp!=NULL && channel>=0 && channel<=EDMA_CHANNELS) {
25563 + if (devp->dma_interrupt_handlers[channel].allocated)
25564 + return -EBUSY;
25565 +
25566 + devp->dma_interrupt_handlers[channel].allocated = 1;
25567 + devp->dma_interrupt_handlers[channel].irq_handler = handler;
25568 + devp->dma_interrupt_handlers[channel].error_handler = error_handler;
25569 + devp->dma_interrupt_handlers[channel].arg = arg;
25570 + devp->dma_interrupt_handlers[channel].lock = lock;
25571 + devp->dma_interrupt_handlers[channel].device_id = device_id;
25572 + return 0;
25573 + }
25574 + return -EINVAL;
25575 +}
25576 +EXPORT_SYMBOL(request_edma_channel);
25577 +
25578 +/**
25579 + * set_edma_callback - Update the channel callback/arg
25580 + * @channel: channel number
25581 + * @handler: dma handler
25582 + * @error_handler: dma error handler
25583 + * @arg: argument to pass back
25584 + *
25585 + * Returns 0 if success or a negative value if failure
25586 + */
25587 +int set_edma_callback(int channel,
25588 + edma_irq_handler handler,
25589 + edma_error_handler error_handler,
25590 + void *arg )
25591 +{
25592 + if (devp!=NULL && channel>=0 && channel<=EDMA_CHANNELS &&
25593 + devp->dma_interrupt_handlers[channel].allocated) {
25594 + devp->dma_interrupt_handlers[channel].irq_handler = handler;
25595 + devp->dma_interrupt_handlers[channel].error_handler = error_handler;
25596 + devp->dma_interrupt_handlers[channel].arg = arg;
25597 + return 0;
25598 + }
25599 + return -EINVAL;
25600 +}
25601 +EXPORT_SYMBOL(set_edma_callback);
25602 +
25603 +/**
25604 + * free_edma_channel - Free the edma channel
25605 + * @channel: channel number
25606 + * @arg: argument created with
25607 + *
25608 + * Returns 0 if success or a negative value if failure
25609 + */
25610 +int free_edma_channel(int channel, void *arg)
25611 +{
25612 + if (devp!=NULL && channel>=0 && channel<=EDMA_CHANNELS) {
25613 + if (devp->dma_interrupt_handlers[channel].allocated) {
25614 +#if 0
25615 + if (devp->dma_interrupt_handlers[channel].arg != arg)
25616 + return -EBUSY;
25617 +#endif
25618 +
25619 + devp->dma_interrupt_handlers[channel].allocated = 0;
25620 + devp->dma_interrupt_handlers[channel].arg = NULL;
25621 + devp->dma_interrupt_handlers[channel].irq_handler = NULL;
25622 + devp->dma_interrupt_handlers[channel].error_handler = NULL;
25623 + devp->dma_interrupt_handlers[channel].lock = NULL;
25624 + }
25625 + return 0;
25626 + }
25627 + return -EINVAL;
25628 +}
25629 +EXPORT_SYMBOL(free_edma_channel);
25630 +
25631 +/**
25632 + * coldfire_edma_cleanup - cleanup driver allocated resources
25633 + */
25634 +static void coldfire_edma_cleanup(void)
25635 +{
25636 + dev_t devno;
25637 + int i;
25638 +
25639 + /* free interrupts/memory */
25640 + if (devp) {
25641 + for (i=0; i<EDMA_CHANNELS; i++)
25642 + free_irq(EDMA_INT_BASE+i, devp);
25643 +
25644 + free_irq(EDMA_INT_BASE+EDMA_INT_ERR, devp);
25645 + cdev_del(&devp->cdev);
25646 + kfree(devp);
25647 + }
25648 +
25649 + /* unregister character device */
25650 + devno = MKDEV(coldfire_dma_major, 0);
25651 + unregister_chrdev_region(devno, 1);
25652 +}
25653 +
25654 +#ifdef CONFIG_PROC_FS
25655 +/*
25656 + * proc file system support
25657 + */
25658 +
25659 +#define FREE_CHANNEL "free"
25660 +#define DEVICE_UNKNOWN "device unknown"
25661 +
25662 +/**
25663 + * proc_edma_show - print out proc info
25664 + * @m: seq_file
25665 + * @v:
25666 + */
25667 +static int proc_edma_show(struct seq_file *m, void *v)
25668 +{
25669 + int i;
25670 +
25671 + if (devp == NULL)
25672 + return 0;
25673 +
25674 + for (i = 0 ; i < EDMA_CHANNELS ; i++) {
25675 + if (devp->dma_interrupt_handlers[i].allocated) {
25676 + if (devp->dma_interrupt_handlers[i].device_id)
25677 + seq_printf(m, "%2d: %s\n", i, devp->dma_interrupt_handlers[i].device_id);
25678 + else
25679 + seq_printf(m, "%2d: %s\n", i, DEVICE_UNKNOWN);
25680 + } else
25681 + seq_printf(m, "%2d: %s\n", i, FREE_CHANNEL);
25682 + }
25683 + return 0;
25684 +}
25685 +
25686 +/**
25687 + * proc_edma_open - open the proc file
25688 + * @inode: inode ptr
25689 + * @file: file ptr
25690 + */
25691 +static int proc_edma_open(struct inode *inode, struct file *file)
25692 +{
25693 + return single_open(file, proc_edma_show, NULL);
25694 +}
25695 +
25696 +static const struct file_operations proc_edma_operations = {
25697 + .open = proc_edma_open,
25698 + .read = seq_read,
25699 + .llseek = seq_lseek,
25700 + .release = single_release,
25701 +};
25702 +
25703 +/**
25704 + * proc_edma_init - initialize proc filesystem
25705 + */
25706 +static int __init proc_edma_init(void)
25707 +{
25708 + struct proc_dir_entry *e;
25709 +
25710 + e = create_proc_entry("edma", 0, NULL);
25711 + if (e)
25712 + e->proc_fops = &proc_edma_operations;
25713 +
25714 + return 0;
25715 +}
25716 +
25717 +#endif
25718 +
25719 +/**
25720 + * coldfire_edma_init - eDMA module init
25721 + */
25722 +static int __init coldfire_edma_init(void)
25723 +{
25724 + dev_t dev;
25725 + int result;
25726 + int i;
25727 +
25728 + /* allocate free major number */
25729 + result = alloc_chrdev_region(&dev, DMA_DEV_MINOR, 1, EDMA_DRIVER_NAME);
25730 + if (result < 0) {
25731 + printk(KERN_WARNING EDMA_DRIVER_NAME": can't get major %d\n",
25732 + result);
25733 + return result;
25734 + }
25735 + coldfire_dma_major = MAJOR(dev);
25736 +
25737 + /* allocate device driver structure */
25738 + devp = kmalloc(sizeof(struct coldfire_edma_dev), GFP_KERNEL);
25739 + if (!devp) {
25740 + result = -ENOMEM;
25741 + goto fail;
25742 + }
25743 +
25744 + /* init handlers (no handlers for beginning) */
25745 + for (i = 0; i < EDMA_CHANNELS; i++) {
25746 + devp->dma_interrupt_handlers[i].irq_handler = NULL;
25747 + devp->dma_interrupt_handlers[i].error_handler = NULL;
25748 + devp->dma_interrupt_handlers[i].arg = NULL;
25749 + devp->dma_interrupt_handlers[i].allocated = 0;
25750 + devp->dma_interrupt_handlers[i].lock = NULL;
25751 + devp->dma_interrupt_handlers[i].device_id = NULL;
25752 + }
25753 +
25754 + /* register char device */
25755 + cdev_init(&devp->cdev, &coldfire_edma_fops);
25756 + devp->cdev.owner = THIS_MODULE;
25757 + devp->cdev.ops = &coldfire_edma_fops;
25758 + result = cdev_add(&devp->cdev, dev, 1);
25759 + if (result) {
25760 + printk(KERN_NOTICE EDMA_DRIVER_NAME
25761 + ": Error %d adding coldfire-dma device\n", result);
25762 + result = -ENODEV;
25763 + goto fail;
25764 + }
25765 +
25766 + /* request/enable irq for each eDMA channel */
25767 + for (i = 0; i < EDMA_CHANNELS;i++) {
25768 + result = request_irq(EDMA_INT_BASE + i,
25769 + dmaisr, IRQF_DISABLED,
25770 + EDMA_DRIVER_NAME, devp);
25771 + if (result) {
25772 + printk(KERN_WARNING EDMA_DRIVER_NAME
25773 + ": Cannot request irq %d\n",
25774 + (EDMA_INT_BASE + EDMA_INT_ERR+i));
25775 + result = -EBUSY;
25776 + goto fail;
25777 + }
25778 + }
25779 +
25780 + /* request error interrupt */
25781 + result = request_irq(EDMA_INT_BASE + EDMA_INT_ERR,
25782 + dma_error_isr, IRQF_DISABLED,
25783 + EDMA_DRIVER_NAME, devp);
25784 + if (result) {
25785 + printk(KERN_WARNING EDMA_DRIVER_NAME
25786 + ": Cannot request irq %d\n",
25787 + (EDMA_INT_BASE + EDMA_INT_ERR));
25788 + result = -EBUSY;
25789 + goto fail;
25790 + }
25791 +
25792 +#ifdef CONFIG_PROC_FS
25793 + proc_edma_init();
25794 +#endif
25795 +
25796 + printk(EDMA_DRIVER_NAME ": initialized successfully\n");
25797 + return 0;
25798 +fail:
25799 + coldfire_edma_cleanup();
25800 + return result;
25801 +}
25802 +
25803 +/**
25804 + * coldfire_edma_exit - eDMA module exit
25805 + */
25806 +static void __exit coldfire_edma_exit(void)
25807 +{
25808 + coldfire_edma_cleanup();
25809 +}
25810 +
25811 +module_init(coldfire_edma_init);
25812 +module_exit(coldfire_edma_exit);
25813 +
25814 +MODULE_LICENSE("GPL");
25815 +MODULE_AUTHOR("Freescale Semiconductor, Inc.");
25816 +MODULE_DESCRIPTION("eDMA library for Coldfire M5445x");
25817 --- /dev/null
25818 +++ b/drivers/spi/dspi_mcf.c
25819 @@ -0,0 +1,1217 @@
25820 +/*
25821 + * dspi_mcf.c - DSPI controller for ColdFire processors
25822 + *
25823 + *
25824 + * Matt Waddel Matt.Waddel@freescale.com
25825 + * Copyright Freescale Semiconductor, Inc. 2008
25826 + *
25827 + * M547x/M548x changes by Kurt Mahan kmahan@freescale.com
25828 + * Copyright Freescale Semiconductor, Inc. 2008
25829 + *
25830 + * Based on spi_coldfire.c done by:
25831 + * Andrey Butok
25832 + * Yaroslav Vinogradov
25833 + * Copyright Freescale Semiconductor, Inc. 2006-2007
25834 + * Mike Lavender (mike@steroidmicros)
25835 + * (C) Copyright 2005, Intec Automation,
25836 + *
25837 + * This program is free software; you can redistribute it and/or modify it
25838 + * under the terms of the GNU General Public License as published by the
25839 + * Free Software Foundation; either version 2 of the License, or (at your
25840 + * option) any later version.
25841 + *
25842 + * This program is distributed in the hope that it will be useful,
25843 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
25844 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25845 + * GNU General Public License for more details.
25846 + *
25847 + * You should have received a copy of the GNU General Public License
25848 + * along with this program; if not, write to the Free Software
25849 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25850 + *
25851 + ***************************************************************************
25852 + * Changes:
25853 + * v0.002 M547x/M548x support.
25854 + * v0.001 Initial version. Coldfire DSPI master driver.
25855 + ****************************************************************************/
25856 +
25857 +/*
25858 + * Includes
25859 + */
25860 +
25861 +#include <linux/autoconf.h>
25862 +#include <linux/init.h>
25863 +#include <linux/module.h>
25864 +#include <linux/device.h>
25865 +#include <linux/interrupt.h>
25866 +#include <linux/platform_device.h>
25867 +#include <linux/spi/spi.h>
25868 +#include <linux/workqueue.h>
25869 +#include <linux/delay.h>
25870 +#include <asm/mcfsim.h>
25871 +#include <asm/mcfqspi.h>
25872 +#include <asm/coldfire.h>
25873 +#include <linux/io.h>
25874 +#include <asm/mcfdspi.h>
25875 +#include <linux/dma-mapping.h>
25876 +
25877 +#undef DSPI_COLDFIRE_DEBUG
25878 +
25879 +#ifdef DSPI_COLDFIRE_DEBUG
25880 +#define DBG(fmt, args...) \
25881 + printk(KERN_INFO "[%s] " fmt , __FUNCTION__, ## args)
25882 +#else
25883 +#define DBG(fmt, args...) do {} while (0)
25884 +#endif
25885 +
25886 +#if defined(CONFIG_M54455)
25887 +#include <asm/mcf5445x_dspi.h>
25888 +#if defined(CONFIG_SPI_COLDFIRE_DSPI_EDMA)
25889 + #include <asm/mcf5445x_edma.h>
25890 +#endif
25891 +#endif
25892 +
25893 +#if defined(CONFIG_M547X_8X)
25894 +#include <asm/virtconvert.h>
25895 +#include <asm/m5485dspi.h>
25896 +#endif
25897 +
25898 +#if defined(CONFIG_SPI_COLDFIRE_DSPI_EDMA)
25899 +#include <asm/mcf_edma.h>
25900 +#define SPI_DSPI_EDMA
25901 +#define EDMA_BUFSIZE_KMALLOC (DSPI_FIFO_SIZE*4)
25902 +#define DSPI_DMA_RX_TCD MCF_EDMA_CHAN_DSPI_RX
25903 +#define DSPI_DMA_TX_TCD MCF_EDMA_CHAN_DSPI_TX
25904 +#endif
25905 +
25906 +#define DSPI_BITS MCF_DSPI_DCTAR_FMSZ(0xF)
25907 +#define DSPI_BITS_16 MCF_DSPI_DCTAR_FMSZ(0xF)
25908 +#define DSPI_BITS_8 MCF_DSPI_DCTAR_FMSZ(0x7)
25909 +#define DSPI_FIFO_SIZE 16
25910 +
25911 +#define DRIVER_NAME "Coldfire DSPI"
25912 +
25913 +/****************************************************************************/
25914 +
25915 +/*
25916 + * Local constants and macros
25917 + */
25918 +
25919 +#define START_STATE ((void *)0)
25920 +#define RUNNING_STATE ((void *)1)
25921 +#define DONE_STATE ((void *)2)
25922 +#define ERROR_STATE ((void *)-1)
25923 +
25924 +#define QUEUE_RUNNING 0
25925 +#define QUEUE_STOPPED 1
25926 +
25927 +/****************************************************************************/
25928 +
25929 +/*
25930 + * Local Data Structures
25931 + */
25932 +
25933 +struct DSPI_MCR {
25934 + unsigned master:1;
25935 + unsigned cont_scke:1;
25936 + unsigned dconf:2;
25937 + unsigned frz:1;
25938 + unsigned mtfe:1;
25939 + unsigned pcsse:1;
25940 + unsigned rooe:1;
25941 + unsigned pcsis:8;
25942 + unsigned reserved15:1;
25943 + unsigned mdis:1;
25944 + unsigned dis_tx:1;
25945 + unsigned dis_rxf:1;
25946 + unsigned clr_tx:1;
25947 + unsigned clr_rxf:1;
25948 + unsigned smpl_pt:2;
25949 + unsigned reserved71:7;
25950 + unsigned halt:1;
25951 +};
25952 +
25953 +struct DSPI_CTAR {
25954 + unsigned dbr:1;
25955 + unsigned fmsz:4;
25956 + unsigned cpol:1;
25957 + unsigned cpha:1;
25958 + unsigned lsbfe:1;
25959 + unsigned pcssck:2;
25960 + unsigned pasc:2;
25961 + unsigned pdt:2;
25962 + unsigned pbr:2;
25963 + unsigned cssck:4;
25964 + unsigned asc:4;
25965 + unsigned dt:4;
25966 + unsigned br:4;
25967 +};
25968 +
25969 +struct chip_data {
25970 + /* dspi data */
25971 + union {
25972 + u32 mcr_val;
25973 + struct DSPI_MCR mcr;
25974 + };
25975 + union {
25976 + u32 ctar_val;
25977 + struct DSPI_CTAR ctar;
25978 + };
25979 + u16 void_write_data;
25980 +};
25981 +
25982 +
25983 +struct driver_data {
25984 + /* Driver model hookup */
25985 + struct platform_device *pdev;
25986 +
25987 + /* SPI framework hookup */
25988 + struct spi_master *master;
25989 +
25990 + /* Driver message queue */
25991 + struct workqueue_struct *workqueue;
25992 + struct work_struct pump_messages;
25993 + spinlock_t lock; /* lock */
25994 + struct list_head queue;
25995 + int busy;
25996 + int run;
25997 +
25998 + /* Message Transfer pump */
25999 + struct tasklet_struct pump_transfers;
26000 +
26001 + /* Current message transfer state info */
26002 + struct spi_message *cur_msg;
26003 + struct spi_transfer *cur_transfer;
26004 + struct chip_data *cur_chip;
26005 + size_t len;
26006 + void *tx;
26007 + void *tx_end;
26008 + void *rx;
26009 + void *rx_end;
26010 + char flags;
26011 +#define TRAN_STATE_RX_VOID 0x01
26012 +#define TRAN_STATE_TX_VOID 0x02
26013 +#define TRAN_STATE_WORD_ODD_NUM 0x04
26014 + u8 cs;
26015 + u16 void_write_data;
26016 + unsigned cs_change:1;
26017 +
26018 + u32 trans_cnt;
26019 + u32 wce_cnt;
26020 + u32 abrt_cnt;
26021 + u32 *mcr; /* DSPI MCR register */
26022 + u32 *ctar; /* DSPI CTAR register */
26023 + u32 *dspi_dtfr; /* DSPI DTFR register */
26024 + u32 *dspi_drfr; /* DSPI DRFR register */
26025 + u32 *dspi_rser; /* DSPI RSER register */
26026 + u32 *dspi_sr; /* DSPI status register */
26027 +
26028 +#if defined(SPI_DSPI_EDMA)
26029 + void *edma_tx_buf;
26030 + void *edma_rx_buf;
26031 +#endif
26032 +
26033 +#if defined(CONFIG_M532x) || defined(CONFIG_M537x)
26034 + u16 *par; /* Pin assignment register */
26035 +#else
26036 + u8 *par; /* Pin assignment register */
26037 +#endif
26038 + u8 *int_icr; /* Interrupt level and priority register */
26039 + u32 *int_mr; /* Interrupt mask register */
26040 + void (*cs_control)(u8 cs, u8 command);
26041 +};
26042 +
26043 +#define DSPI_CS(cs) ((1<<(cs))<<16)
26044 +
26045 +/****************************************************************************/
26046 +
26047 +/*
26048 + * SPI local functions
26049 + */
26050 +
26051 +static void *next_transfer(struct driver_data *drv_data)
26052 +{
26053 + struct spi_message *msg = drv_data->cur_msg;
26054 + struct spi_transfer *trans = drv_data->cur_transfer;
26055 +
26056 + DBG("\n");
26057 + /* Move to next transfer */
26058 + if (trans->transfer_list.next != &msg->transfers) {
26059 + drv_data->cur_transfer = list_entry(trans->transfer_list.next,
26060 + struct spi_transfer,
26061 + transfer_list);
26062 +
26063 + if (drv_data->cur_transfer->transfer_list.next
26064 + == &msg->transfers) /* last transfer */
26065 + drv_data->cur_transfer->cs_change = 1;
26066 +
26067 + return RUNNING_STATE;
26068 + } else
26069 + return DONE_STATE;
26070 +}
26071 +
26072 +
26073 +static inline int is_word_transfer(struct driver_data *drv_data)
26074 +{
26075 + return ((*(drv_data->ctar+drv_data->cs) & DSPI_BITS_16) ==
26076 + DSPI_BITS_8) ? 0 : 1;
26077 +}
26078 +
26079 +static inline void set_8bit_transfer_mode(struct driver_data *drv_data)
26080 +{
26081 + DBG("\n");
26082 + *(drv_data->ctar+drv_data->cs) =
26083 + (*(drv_data->ctar + drv_data->cs) & ~DSPI_BITS) | DSPI_BITS_8;
26084 +}
26085 +
26086 +static inline void set_16bit_transfer_mode(struct driver_data *drv_data)
26087 +{
26088 + DBG("\n");
26089 + *(drv_data->ctar+drv_data->cs) =
26090 + (*(drv_data->ctar + drv_data->cs) & ~DSPI_BITS) | DSPI_BITS_16;
26091 +}
26092 +
26093 +static unsigned char hz_to_spi_baud(int pbr, int dbr, int speed_hz)
26094 +{
26095 + int pbr_tbl[4] = {2, 3, 5, 7}; /* Valid baud rate pre-scaler values */
26096 + int brs[16] = { 2, 4, 6, 8,
26097 + 16, 32, 64, 128,
26098 + 256, 512, 1024, 2048,
26099 + 4096, 8192, 16384, 32768 };
26100 + int temp, index = 0;
26101 +
26102 + if ((pbr < 0) || (pbr > 3) ||
26103 + (dbr < 0) || (dbr > 1))
26104 + return 15; /* table indexes out of range, go slow */
26105 +
26106 + temp = ((((MCF_CLK / 2) / pbr_tbl[pbr]) * (1 + dbr)) / speed_hz);
26107 +
26108 + while (temp >= brs[index])
26109 + if (index++ >= 15)
26110 + break;
26111 +
26112 + DBG("baud rate scaler = 0x%x - %d\n", index, brs[index]);
26113 + return(index);
26114 +}
26115 +
26116 +static int write(struct driver_data *drv_data)
26117 +{
26118 + int tx_count = 0;
26119 + int tx_word = is_word_transfer(drv_data);
26120 + u16 d16;
26121 + u8 d8;
26122 + u32 dspi_pushr = 0;
26123 + int first = 1;
26124 +#if defined(SPI_DSPI_EDMA)
26125 + u32 *edma_wr = (u32 *)(drv_data->edma_tx_buf);
26126 +#endif
26127 +
26128 + /* If we are in word mode, but only have a single byte to transfer
26129 + * then switch to byte mode temporarily. Will switch back at the
26130 + * end of the transfer. */
26131 + if (tx_word && ((drv_data->tx_end - drv_data->tx) == 1)) {
26132 + drv_data->flags |= TRAN_STATE_WORD_ODD_NUM;
26133 + set_8bit_transfer_mode(drv_data);
26134 + tx_word = 0;
26135 + }
26136 +
26137 + while ((drv_data->tx < drv_data->tx_end) && (tx_count < DSPI_FIFO_SIZE)) {
26138 +// DBG("while\n");
26139 + if (tx_word) {
26140 + if ((drv_data->tx_end - drv_data->tx) == 1)
26141 + break;
26142 +
26143 + if (!(drv_data->flags & TRAN_STATE_TX_VOID))
26144 + d16 = *(u16 *)drv_data->tx;
26145 + else
26146 + d16 = drv_data->void_write_data;
26147 +
26148 + dspi_pushr = MCF_DSPI_DTFR_TXDATA(d16) |
26149 + DSPI_CS(drv_data->cs) |
26150 + MCF_DSPI_DTFR_CTAS(drv_data->cs) |
26151 + MCF_DSPI_DTFR_CONT;
26152 +
26153 + drv_data->tx += 2;
26154 + } else {
26155 + if (!(drv_data->flags & TRAN_STATE_TX_VOID))
26156 + d8 = *(u8 *)drv_data->tx;
26157 + else
26158 + d8 = *(u8 *)&drv_data->void_write_data;
26159 +
26160 + dspi_pushr = MCF_DSPI_DTFR_TXDATA(d8) |
26161 + DSPI_CS(drv_data->cs) |
26162 + MCF_DSPI_DTFR_CTAS(drv_data->cs) |
26163 + MCF_DSPI_DTFR_CONT;
26164 +
26165 + drv_data->tx++;
26166 + }
26167 +
26168 + if (drv_data->tx == drv_data->tx_end
26169 + || tx_count == DSPI_FIFO_SIZE-1) {
26170 + /* last transfer in the queue */
26171 + dspi_pushr |= MCF_DSPI_DTFR_EOQ;
26172 + if ((drv_data->cs_change)
26173 + && (drv_data->tx == drv_data->tx_end))
26174 + dspi_pushr &= ~MCF_DSPI_DTFR_CONT;
26175 +#ifdef CONFIG_M547X_8X
26176 + /* EOQ gets missed if we don't delay */
26177 + udelay(100);
26178 +#endif
26179 + } else if (tx_word && ((drv_data->tx_end - drv_data->tx) == 1))
26180 + dspi_pushr |= MCF_DSPI_DTFR_EOQ;
26181 +
26182 + if (first) {
26183 + first = 0;
26184 + dspi_pushr |= MCF_DSPI_DTFR_CTCNT; /* clear counter */
26185 + }
26186 +#if defined(SPI_DSPI_EDMA)
26187 + *edma_wr = dspi_pushr;
26188 + edma_wr++;
26189 +#else
26190 + *drv_data->dspi_dtfr = dspi_pushr;
26191 +#endif
26192 + tx_count++;
26193 + }
26194 +
26195 +#if defined(SPI_DSPI_EDMA)
26196 + if (tx_count > 0) {
26197 +
26198 + mcf_edma_set_tcd_params(DSPI_DMA_TX_TCD,
26199 + virt_to_phys(drv_data->edma_tx_buf),
26200 + (u32)drv_data->dspi_dtfr,
26201 + MCF_EDMA_TCD_ATTR_SSIZE_32BIT
26202 + | MCF_EDMA_TCD_ATTR_DSIZE_32BIT,
26203 + 4, /* soff */
26204 + 4 * tx_count, /* nbytes */
26205 + 0, /* slast */
26206 + 1, /* citer */
26207 + 1, /* biter */
26208 + 0, /* doff */
26209 + 0, /* dlastsga */
26210 + 0, /* major_int */
26211 + 1); /* disable_req */
26212 +
26213 + mcf_edma_set_tcd_params(DSPI_DMA_RX_TCD,
26214 + (u32)drv_data->dspi_drfr,
26215 + virt_to_phys(drv_data->edma_rx_buf),
26216 + MCF_EDMA_TCD_ATTR_SSIZE_32BIT
26217 + | MCF_EDMA_TCD_ATTR_DSIZE_32BIT,
26218 + 0, /* soff */
26219 + 4 * tx_count, /* nbytes */
26220 + 0, /* slast */
26221 + 1, /* citer */
26222 + 1, /* biter */
26223 + 4, /* doff */
26224 + 0, /* dlastsga */
26225 + 0, /* major_int */
26226 + 1); /* disable_req */
26227 +
26228 + mcf_edma_start_transfer(DSPI_DMA_TX_TCD);
26229 + }
26230 +#endif
26231 + return (tx_count * (tx_word + 1));
26232 +}
26233 +
26234 +static int read(struct driver_data *drv_data)
26235 +{
26236 + int rx_count = 0;
26237 + int rx_word = is_word_transfer(drv_data);
26238 + u16 d;
26239 +#if defined(SPI_DSPI_EDMA)
26240 + u32 *rx_edma = (u32 *) drv_data->edma_rx_buf;
26241 +
26242 + /* receive SPI data */
26243 + mcf_edma_start_transfer(DSPI_DMA_RX_TCD);
26244 +#endif
26245 + while ((drv_data->rx < drv_data->rx_end)
26246 + && (rx_count < DSPI_FIFO_SIZE)) {
26247 +
26248 + if (rx_word) {
26249 + if ((drv_data->rx_end - drv_data->rx) == 1)
26250 + break;
26251 +#if defined(SPI_DSPI_EDMA)
26252 + d = MCF_DSPI_DRFR_RXDATA(*rx_edma);
26253 + rx_edma++;
26254 +#else
26255 + d = MCF_DSPI_DRFR_RXDATA(*drv_data->dspi_drfr);
26256 +#endif
26257 + if (!(drv_data->flags & TRAN_STATE_RX_VOID))
26258 + *(u16 *)drv_data->rx = d;
26259 + drv_data->rx += 2;
26260 +
26261 + } else {
26262 +#if defined(SPI_DSPI_EDMA)
26263 + d = MCF_DSPI_DRFR_RXDATA(*rx_edma);
26264 + rx_edma++;
26265 +#else
26266 + d = MCF_DSPI_DRFR_RXDATA(*drv_data->dspi_drfr);
26267 +#endif
26268 + if (!(drv_data->flags & TRAN_STATE_RX_VOID))
26269 + *(u8 *)drv_data->rx = d;
26270 + drv_data->rx++;
26271 + }
26272 + rx_count++;
26273 + DBG("rxd=0x%x\n", d);
26274 + }
26275 + return rx_count;
26276 +}
26277 +
26278 +
26279 +static inline void dspi_setup_chip(struct driver_data *drv_data)
26280 +{
26281 + struct chip_data *chip = drv_data->cur_chip;
26282 +
26283 + DBG("\n");
26284 + *drv_data->mcr = chip->mcr_val;
26285 + *(drv_data->ctar+drv_data->cs) = chip->ctar_val;
26286 + *drv_data->dspi_rser = MCF_DSPI_DRSER_EOQFE;
26287 +}
26288 +
26289 +#if defined(SPI_DSPI_EDMA)
26290 +static int edma_tx_handler(int channel, void *dev)
26291 +{
26292 + DBG("\n");
26293 + if (channel == DSPI_DMA_TX_TCD)
26294 + mcf_edma_stop_transfer(DSPI_DMA_TX_TCD);
26295 + return IRQ_HANDLED;
26296 +}
26297 +
26298 +static int edma_rx_handler(int channel, void *dev)
26299 +{
26300 + DBG("\n");
26301 + if (channel == DSPI_DMA_RX_TCD)
26302 + mcf_edma_stop_transfer(DSPI_DMA_RX_TCD);
26303 + return IRQ_HANDLED;
26304 +}
26305 +#endif
26306 +
26307 +static irqreturn_t dspi_interrupt(int irq, void *dev_id)
26308 +{
26309 + struct driver_data *drv_data = (struct driver_data *)dev_id;
26310 + struct spi_message *msg = drv_data->cur_msg;
26311 +
26312 + /* Clear all flags immediately */
26313 + *drv_data->dspi_sr = MCF_DSPI_DSR_EOQF;
26314 +
26315 + if (!drv_data->cur_msg || !drv_data->cur_msg->state) {
26316 +#if !defined(SPI_DSPI_EDMA)
26317 + u32 irq_status = *drv_data->dspi_sr;
26318 + /* if eDMA is used it happens some time (at least once)*/
26319 + printk(KERN_ERR "Bad message or transfer state handler. \
26320 + IRQ status = %x\n", irq_status);
26321 +#endif
26322 + return IRQ_NONE;
26323 + }
26324 +
26325 + DBG("\n");
26326 + /*
26327 + * Read the data into the buffer and reload and start
26328 + * queue with new data if not finished. If finished
26329 + * then setup the next transfer
26330 + */
26331 + read(drv_data);
26332 +
26333 + if (drv_data->rx == drv_data->rx_end) {
26334 + /*
26335 + * Finished now - fall through and schedule next
26336 + * transfer tasklet
26337 + */
26338 + if (drv_data->flags & TRAN_STATE_WORD_ODD_NUM)
26339 + set_16bit_transfer_mode(drv_data);
26340 +
26341 + msg->state = next_transfer(drv_data);
26342 + } else {
26343 + /* not finished yet - keep going */
26344 + msg->actual_length += write(drv_data);
26345 + return IRQ_HANDLED;
26346 + }
26347 +
26348 + tasklet_schedule(&drv_data->pump_transfers);
26349 +
26350 + return IRQ_HANDLED;
26351 +}
26352 +
26353 +/* caller already set message->status; dma and pio irqs are blocked */
26354 +static void giveback(struct driver_data *drv_data)
26355 +{
26356 + struct spi_transfer *last_transfer;
26357 + unsigned long flags;
26358 + struct spi_message *msg;
26359 + DBG("\n");
26360 +
26361 + spin_lock_irqsave(&drv_data->lock, flags);
26362 + msg = drv_data->cur_msg;
26363 + drv_data->cur_msg = NULL;
26364 + drv_data->cur_transfer = NULL;
26365 + drv_data->cur_chip = NULL;
26366 + queue_work(drv_data->workqueue, &drv_data->pump_messages);
26367 + spin_unlock_irqrestore(&drv_data->lock, flags);
26368 +
26369 + last_transfer = list_entry(msg->transfers.prev,
26370 + struct spi_transfer, transfer_list);
26371 +
26372 + if (!last_transfer->cs_change)
26373 + drv_data->cs_control(drv_data->cs, QSPI_CS_DROP);
26374 +
26375 + msg->state = NULL;
26376 + if (msg->complete)
26377 + msg->complete(msg->context);
26378 +}
26379 +
26380 +
26381 +static void pump_transfers(unsigned long data)
26382 +{
26383 + struct driver_data *drv_data = (struct driver_data *)data;
26384 + struct spi_message *message = NULL;
26385 + struct spi_transfer *transfer = NULL;
26386 + struct spi_transfer *previous = NULL;
26387 + struct chip_data *chip = NULL;
26388 + unsigned long flags;
26389 + DBG("\n");
26390 + /* Get current state information */
26391 + message = drv_data->cur_msg;
26392 + transfer = drv_data->cur_transfer;
26393 + chip = drv_data->cur_chip;
26394 +
26395 + /* Handle for abort */
26396 + if (message->state == ERROR_STATE) {
26397 + message->status = -EIO;
26398 + giveback(drv_data);
26399 + return;
26400 + }
26401 +
26402 + /* Handle end of message */
26403 + if (message->state == DONE_STATE) {
26404 + message->status = 0;
26405 + giveback(drv_data);
26406 + return;
26407 + }
26408 +
26409 + if (message->state == START_STATE) {
26410 + dspi_setup_chip(drv_data);
26411 +
26412 + if (drv_data->cs_control)
26413 + drv_data->cs_control(message->spi->chip_select,
26414 + QSPI_CS_ASSERT);
26415 + }
26416 +
26417 + /* Delay if requested at end of transfer*/
26418 + if (message->state == RUNNING_STATE) {
26419 + previous = list_entry(transfer->transfer_list.prev,
26420 + struct spi_transfer,
26421 + transfer_list);
26422 +
26423 + if (drv_data->cs_control && transfer->cs_change)
26424 + drv_data->cs_control(message->spi->chip_select,
26425 + QSPI_CS_DROP);
26426 +
26427 + if (previous->delay_usecs)
26428 + udelay(previous->delay_usecs);
26429 +
26430 + if (drv_data->cs_control && transfer->cs_change)
26431 + drv_data->cs_control(message->spi->chip_select,
26432 + QSPI_CS_ASSERT);
26433 + }
26434 +
26435 + drv_data->flags = 0;
26436 + drv_data->tx = (void *)transfer->tx_buf;
26437 + drv_data->tx_end = drv_data->tx + transfer->len;
26438 + drv_data->rx = transfer->rx_buf;
26439 + drv_data->rx_end = drv_data->rx + transfer->len;
26440 +
26441 + if (!drv_data->rx)
26442 + drv_data->flags |= TRAN_STATE_RX_VOID;
26443 + if (!drv_data->tx)
26444 + drv_data->flags |= TRAN_STATE_TX_VOID;
26445 + drv_data->cs = message->spi->chip_select;
26446 + drv_data->cs_change = transfer->cs_change;
26447 + drv_data->void_write_data = chip->void_write_data;
26448 + if (transfer->speed_hz) {
26449 + *(drv_data->ctar + drv_data->cs) = \
26450 + ((chip->ctar_val & ~0xF) | \
26451 + hz_to_spi_baud(chip->ctar.pbr, \
26452 + chip->ctar.dbr, \
26453 + transfer->speed_hz));
26454 + }
26455 +
26456 + message->state = RUNNING_STATE;
26457 + /* Go baby, go */
26458 + local_irq_save(flags);
26459 + message->actual_length += write(drv_data);
26460 + local_irq_restore(flags);
26461 +}
26462 +
26463 +
26464 +static void pump_messages(struct work_struct *work)
26465 +{
26466 + struct driver_data *drv_data;
26467 + unsigned long flags;
26468 + DBG("\n");
26469 +
26470 + drv_data = container_of(work, struct driver_data, pump_messages);
26471 +
26472 + /* Lock queue and check for queue work */
26473 + spin_lock_irqsave(&drv_data->lock, flags);
26474 + if (list_empty(&drv_data->queue)
26475 + || drv_data->run == QUEUE_STOPPED) {
26476 + drv_data->busy = 0;
26477 + spin_unlock_irqrestore(&drv_data->lock, flags);
26478 + return;
26479 + }
26480 +
26481 + /* Make sure we are not already running a message */
26482 + if (drv_data->cur_msg) {
26483 + spin_unlock_irqrestore(&drv_data->lock, flags);
26484 + return;
26485 + }
26486 +
26487 + /* Extract head of queue */
26488 + drv_data->cur_msg = list_entry(drv_data->queue.next,
26489 + struct spi_message, queue);
26490 + list_del_init(&drv_data->cur_msg->queue);
26491 +
26492 + /* Initial message state*/
26493 + drv_data->cur_msg->state = START_STATE;
26494 + drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
26495 + struct spi_transfer,
26496 + transfer_list);
26497 +
26498 + if (drv_data->cur_transfer->transfer_list.next
26499 + == &drv_data->cur_msg->transfers)
26500 + drv_data->cur_transfer->cs_change = 1; /* last */
26501 +
26502 +
26503 + /* Setup the SPI Registers using the per chip configuration */
26504 + drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
26505 +
26506 + /* Mark as busy and launch transfers */
26507 + tasklet_schedule(&drv_data->pump_transfers);
26508 +
26509 + drv_data->busy = 1;
26510 + spin_unlock_irqrestore(&drv_data->lock, flags);
26511 +}
26512 +
26513 +/****************************************************************************/
26514 +
26515 +/*
26516 + * SPI master implementation
26517 + */
26518 +
26519 +static int transfer(struct spi_device *spi, struct spi_message *msg)
26520 +{
26521 + struct driver_data *drv_data = spi_master_get_devdata(spi->master);
26522 + unsigned long flags;
26523 +
26524 + DBG("\n");
26525 + spin_lock_irqsave(&drv_data->lock, flags);
26526 +
26527 + if (drv_data->run == QUEUE_STOPPED) {
26528 + spin_unlock_irqrestore(&drv_data->lock, flags);
26529 + return -ESHUTDOWN;
26530 + }
26531 +
26532 + msg->actual_length = 0;
26533 + msg->status = -EINPROGRESS;
26534 + msg->state = START_STATE;
26535 +
26536 + list_add_tail(&msg->queue, &drv_data->queue);
26537 +
26538 + if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
26539 + queue_work(drv_data->workqueue, &drv_data->pump_messages);
26540 +
26541 + spin_unlock_irqrestore(&drv_data->lock, flags);
26542 +
26543 + return 0;
26544 +}
26545 +
26546 +
26547 +static int setup(struct spi_device *spi)
26548 +{
26549 +
26550 + struct chip_data *chip;
26551 + struct coldfire_dspi_chip *chip_info
26552 + = (struct coldfire_dspi_chip *)spi->controller_data;
26553 + DBG("\n");
26554 +
26555 + /* Only alloc on first setup */
26556 + chip = spi_get_ctldata(spi);
26557 + if (chip == NULL) {
26558 + chip = kcalloc(1, sizeof(struct chip_data), GFP_KERNEL);
26559 + if (!chip)
26560 + return -ENOMEM;
26561 + spi->mode = chip_info->mode;
26562 + spi->bits_per_word = chip_info->bits_per_word;
26563 + }
26564 +
26565 + chip->mcr.master = 1;
26566 + chip->mcr.cont_scke = 0;
26567 + chip->mcr.dconf = 0;
26568 + chip->mcr.frz = 0;
26569 + chip->mcr.mtfe = 0;
26570 + chip->mcr.pcsse = 0;
26571 + chip->mcr.rooe = 0;
26572 + chip->mcr.pcsis = 0xFF;
26573 + chip->mcr.reserved15 = 0;
26574 + chip->mcr.mdis = 0;
26575 + chip->mcr.dis_tx = 0;
26576 + chip->mcr.dis_rxf = 0;
26577 + chip->mcr.clr_tx = 1;
26578 + chip->mcr.clr_rxf = 1;
26579 + chip->mcr.smpl_pt = 0;
26580 + chip->mcr.reserved71 = 0;
26581 + chip->mcr.halt = 0;
26582 +
26583 + if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
26584 + chip->ctar.fmsz = spi->bits_per_word-1;
26585 + } else {
26586 + printk(KERN_ERR "Invalid wordsize\n");
26587 + kfree(chip);
26588 + return -ENODEV;
26589 + }
26590 +
26591 + chip->void_write_data = chip_info->void_write_data;
26592 +
26593 + if (spi->max_speed_hz != 0)
26594 + chip_info->br = hz_to_spi_baud(chip_info->pbr, chip_info->dbr, \
26595 + spi->max_speed_hz);
26596 +
26597 + chip->ctar.cpha = (spi->mode & SPI_CPHA) ? 1 : 0;
26598 + chip->ctar.cpol = (spi->mode & SPI_CPOL) ? 1 : 0;
26599 + chip->ctar.lsbfe = (spi->mode & SPI_LSB_FIRST) ? 1 : 0;
26600 + chip->ctar.dbr = chip_info->dbr;
26601 + chip->ctar.pbr = chip_info->pbr;
26602 + chip->ctar.br = chip_info->br;
26603 + chip->ctar.pcssck = chip_info->pcssck;
26604 + chip->ctar.pasc = chip_info->pasc;
26605 + chip->ctar.pdt = chip_info->pdt;
26606 + chip->ctar.cssck = chip_info->cssck;
26607 + chip->ctar.asc = chip_info->asc;
26608 + chip->ctar.dt = chip_info->dt;
26609 +
26610 + spi_set_ctldata(spi, chip);
26611 +
26612 + return 0;
26613 +}
26614 +
26615 +static int init_queue(struct driver_data *drv_data)
26616 +{
26617 + INIT_LIST_HEAD(&drv_data->queue);
26618 + spin_lock_init(&drv_data->lock);
26619 +
26620 + drv_data->run = QUEUE_STOPPED;
26621 + drv_data->busy = 0;
26622 +
26623 + tasklet_init(&drv_data->pump_transfers,
26624 + pump_transfers, (unsigned long)drv_data);
26625 +
26626 + INIT_WORK(&drv_data->pump_messages, pump_messages);
26627 +
26628 + drv_data->workqueue = create_singlethread_workqueue(
26629 + drv_data->master->dev.parent->bus_id);
26630 + if (drv_data->workqueue == NULL)
26631 + return -EBUSY;
26632 +
26633 + return 0;
26634 +}
26635 +
26636 +static int start_queue(struct driver_data *drv_data)
26637 +{
26638 + unsigned long flags;
26639 +
26640 + spin_lock_irqsave(&drv_data->lock, flags);
26641 +
26642 + if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
26643 + spin_unlock_irqrestore(&drv_data->lock, flags);
26644 + return -EBUSY;
26645 + }
26646 +
26647 + drv_data->run = QUEUE_RUNNING;
26648 + drv_data->cur_msg = NULL;
26649 + drv_data->cur_transfer = NULL;
26650 + drv_data->cur_chip = NULL;
26651 + spin_unlock_irqrestore(&drv_data->lock, flags);
26652 +
26653 + queue_work(drv_data->workqueue, &drv_data->pump_messages);
26654 +
26655 + return 0;
26656 +}
26657 +
26658 +static int stop_queue(struct driver_data *drv_data)
26659 +{
26660 + unsigned long flags;
26661 + unsigned limit = 500;
26662 + int status = 0;
26663 +
26664 + spin_lock_irqsave(&drv_data->lock, flags);
26665 +
26666 + /* This is a bit lame, but is optimized for the common execution path.
26667 + * A wait_queue on the drv_data->busy could be used, but then the common
26668 + * execution path (pump_messages) would be required to call wake_up or
26669 + * friends on every SPI message. Do this instead */
26670 + drv_data->run = QUEUE_STOPPED;
26671 + while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
26672 + spin_unlock_irqrestore(&drv_data->lock, flags);
26673 + msleep(10);
26674 + spin_lock_irqsave(&drv_data->lock, flags);
26675 + }
26676 +
26677 + if (!list_empty(&drv_data->queue) || drv_data->busy)
26678 + status = -EBUSY;
26679 +
26680 + spin_unlock_irqrestore(&drv_data->lock, flags);
26681 +
26682 + return status;
26683 +}
26684 +
26685 +static int destroy_queue(struct driver_data *drv_data)
26686 +{
26687 + int status;
26688 +
26689 + status = stop_queue(drv_data);
26690 + if (status != 0)
26691 + return status;
26692 +
26693 + destroy_workqueue(drv_data->workqueue);
26694 +
26695 + return 0;
26696 +}
26697 +
26698 +
26699 +static void cleanup(struct spi_device *spi)
26700 +{
26701 + struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
26702 +
26703 + dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
26704 + spi->master->bus_num, spi->chip_select);
26705 +
26706 + kfree(chip);
26707 +}
26708 +
26709 +
26710 +/****************************************************************************/
26711 +
26712 +/*
26713 + * Generic Device driver routines and interface implementation
26714 + */
26715 +
26716 +static int coldfire_spi_probe(struct platform_device *pdev)
26717 +{
26718 + struct device *dev = &pdev->dev;
26719 + struct coldfire_spi_master *platform_info;
26720 + struct spi_master *master;
26721 + struct driver_data *drv_data = 0;
26722 + struct resource *memory_resource;
26723 + int irq;
26724 + int status = 0;
26725 + int i;
26726 +#if defined(SPI_DSPI_EDMA)
26727 + dma_addr_t dma_handle;
26728 +#endif
26729 +
26730 + platform_info = (struct coldfire_spi_master *)dev->platform_data;
26731 +
26732 + master = spi_alloc_master(dev, sizeof(struct driver_data));
26733 + if (!master)
26734 + return -ENOMEM;
26735 +
26736 + drv_data = spi_master_get_devdata(master);
26737 + drv_data->master = master;
26738 +
26739 + INIT_LIST_HEAD(&drv_data->queue);
26740 + spin_lock_init(&drv_data->lock);
26741 +
26742 + master->bus_num = platform_info->bus_num;
26743 + master->num_chipselect = platform_info->num_chipselect;
26744 + master->cleanup = cleanup;
26745 + master->setup = setup;
26746 + master->transfer = transfer;
26747 +
26748 + drv_data->cs_control = platform_info->cs_control;
26749 + if (drv_data->cs_control)
26750 + for (i = 0; i < master->num_chipselect; i++)
26751 + drv_data->cs_control(i, QSPI_CS_INIT | QSPI_CS_DROP);
26752 +
26753 + /* Setup register addresses */
26754 + memory_resource = platform_get_resource_byname(pdev,
26755 + IORESOURCE_MEM, "spi-module");
26756 + if (!memory_resource) {
26757 + dev_dbg(dev, "can not find platform module memory\n");
26758 + goto out_error_master_alloc;
26759 + }
26760 +
26761 +#if defined(SPI_DSPI_EDMA)
26762 + drv_data->edma_tx_buf = dma_alloc_coherent(NULL, EDMA_BUFSIZE_KMALLOC, \
26763 + &dma_handle, GFP_DMA);
26764 + if (!drv_data->edma_tx_buf) {
26765 + dev_dbg(dev, "cannot allocate eDMA TX memory\n");
26766 + goto out_error_master_alloc;
26767 + }
26768 + drv_data->edma_rx_buf = dma_alloc_coherent(NULL, EDMA_BUFSIZE_KMALLOC, \
26769 + &dma_handle, GFP_DMA);
26770 + if (!drv_data->edma_rx_buf) {
26771 + dma_free_coherent(NULL, EDMA_BUFSIZE_KMALLOC, \
26772 + drv_data->edma_tx_buf, dma_handle);
26773 + kfree(drv_data->edma_tx_buf);
26774 + dev_dbg(dev, "cannot allocate eDMA RX memory\n");
26775 + goto out_error_master_alloc;
26776 + }
26777 +#endif
26778 +
26779 + drv_data->mcr = (void *)&MCF_DSPI_DMCR;
26780 + drv_data->ctar = (void *)&MCF_DSPI_DCTAR0;
26781 + drv_data->dspi_sr = (void *)&MCF_DSPI_DSR;
26782 + drv_data->dspi_rser = (void *)&MCF_DSPI_DRSER;
26783 + drv_data->dspi_dtfr = (void *)&MCF_DSPI_DTFR;
26784 + drv_data->dspi_drfr = (void *)&MCF_DSPI_DRFR;
26785 +
26786 + memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
26787 + "spi-par");
26788 + if (!memory_resource) {
26789 + dev_dbg(dev, "No spi-par memory\n");
26790 + goto out_error_master_alloc;
26791 + }
26792 + drv_data->par = (void *)memory_resource->start;
26793 +
26794 + memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
26795 + "spi-int-level");
26796 + if (!memory_resource) {
26797 + dev_dbg(dev, "No spi-int-level memory\n");
26798 + goto out_error_master_alloc;
26799 + }
26800 + drv_data->int_icr = (void *)memory_resource->start;
26801 +
26802 + memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
26803 + "spi-int-mask");
26804 + if (!memory_resource) {
26805 + dev_dbg(dev, "No spi-int-mask memory\n");
26806 + goto out_error_master_alloc;
26807 + }
26808 + drv_data->int_mr = (void *)memory_resource->start;
26809 +
26810 + if (platform_info->irq_list) {
26811 + /* multiple IRQs */
26812 + int *irqlist = platform_info->irq_list;
26813 + while ((irq = *irqlist++)) {
26814 + int off = *irqlist++;
26815 + int lvl = *irqlist++;
26816 + int msk = *irqlist++;
26817 + status = request_irq(irq, dspi_interrupt, IRQF_DISABLED,
26818 + dev->bus_id, drv_data);
26819 + if (status < 0) {
26820 + dev_err(&pdev->dev,
26821 + "Unable to attach ColdFire DSPI interrupt\n");
26822 + goto out_error_master_alloc;
26823 + }
26824 +
26825 + if (lvl)
26826 + *(drv_data->int_icr + off) = lvl;
26827 +
26828 + if (msk)
26829 + *drv_data->int_mr &= ~msk;
26830 + }
26831 + }
26832 + else {
26833 + irq = platform_info->irq_vector;
26834 +
26835 + status = request_irq(platform_info->irq_vector, dspi_interrupt,
26836 + IRQF_DISABLED, dev->bus_id, drv_data);
26837 + if (status < 0) {
26838 + dev_err(&pdev->dev, "Unable to attach ColdFire DSPI interrupt\n");
26839 + goto out_error_master_alloc;
26840 + }
26841 +
26842 + *drv_data->int_icr = platform_info->irq_lp;
26843 + *drv_data->int_mr &= ~platform_info->irq_mask;
26844 + }
26845 +
26846 + /* Now that we have all the addresses etc. Let's set it up */
26847 + if (platform_info->par_val)
26848 + *drv_data->par = platform_info->par_val;
26849 +
26850 + /* Initial and start queue */
26851 + status = init_queue(drv_data);
26852 + if (status != 0) {
26853 + dev_err(&pdev->dev, "Problem initializing DSPI queue\n");
26854 + goto out_error_irq_alloc;
26855 + }
26856 + status = start_queue(drv_data);
26857 + if (status != 0) {
26858 + dev_err(&pdev->dev, "Problem starting DSPI queue\n");
26859 + goto out_error_irq_alloc;
26860 + }
26861 +
26862 + /* Register with the SPI framework */
26863 + platform_set_drvdata(pdev, drv_data);
26864 + status = spi_register_master(master);
26865 + if (status != 0) {
26866 + dev_err(&pdev->dev, "Problem registering DSPI master\n");
26867 + status = -EINVAL;
26868 + goto out_error_queue_alloc;
26869 + }
26870 +
26871 +#if defined(SPI_DSPI_EDMA)
26872 + if (mcf_edma_request_channel(DSPI_DMA_TX_TCD,
26873 + edma_tx_handler,
26874 + NULL,
26875 + 0x0,
26876 + pdev,
26877 + NULL, /* spinlock */
26878 + DRIVER_NAME) < 0){
26879 + dev_err(&pdev->dev, "eDMA transmit channel request\n");
26880 + status = -EINVAL;
26881 + goto out_error_queue_alloc;
26882 + }
26883 +
26884 + if (mcf_edma_request_channel(DSPI_DMA_RX_TCD,
26885 + edma_rx_handler,
26886 + NULL,
26887 + 0x0,
26888 + pdev,
26889 + NULL, /* spinlock */
26890 + DRIVER_NAME) < 0){
26891 + dev_err(&pdev->dev, "eDAM receive channel request\n");
26892 + status = -EINVAL;
26893 + mcf_edma_free_channel(DSPI_DMA_TX_TCD, pdev);
26894 + goto out_error_queue_alloc;
26895 + }
26896 +#endif
26897 +
26898 + printk(KERN_INFO "DSPI: Coldfire master initialized\n");
26899 + return status;
26900 +
26901 +out_error_queue_alloc:
26902 + destroy_queue(drv_data);
26903 +
26904 +out_error_irq_alloc:
26905 + free_irq(platform_info->irq_vector, drv_data);
26906 +
26907 +out_error_master_alloc:
26908 + spi_master_put(master);
26909 + return status;
26910 +
26911 +}
26912 +
26913 +static int coldfire_spi_remove(struct platform_device *pdev)
26914 +{
26915 + struct driver_data *drv_data = platform_get_drvdata(pdev);
26916 + int irq;
26917 + int status = 0;
26918 +
26919 + if (!drv_data)
26920 + return 0;
26921 +
26922 +#if defined(SPI_DSPI_EDMA)
26923 + mcf_edma_free_channel(DSPI_DMA_TX_TCD, pdev);
26924 + mcf_edma_free_channel(DSPI_DMA_RX_TCD, pdev);
26925 +#endif
26926 +
26927 + /* Remove the queue */
26928 + status = destroy_queue(drv_data);
26929 + if (status != 0)
26930 + return status;
26931 +
26932 + /* Release IRQ */
26933 + irq = platform_get_irq(pdev, 0);
26934 + if (irq >= 0)
26935 + free_irq(irq, drv_data);
26936 +
26937 + /* Disconnect from the SPI framework */
26938 + spi_unregister_master(drv_data->master);
26939 +
26940 + /* Prevent double remove */
26941 + platform_set_drvdata(pdev, NULL);
26942 +
26943 + return 0;
26944 +}
26945 +
26946 +static void coldfire_spi_shutdown(struct platform_device *pdev)
26947 +{
26948 + int status = coldfire_spi_remove(pdev);
26949 +
26950 + if (status != 0)
26951 + dev_err(&pdev->dev, "shutdown failed with %d\n", status);
26952 +}
26953 +
26954 +
26955 +#ifdef CONFIG_PM
26956 +static int suspend_devices(struct device *dev, void *pm_message)
26957 +{
26958 + pm_message_t *state = pm_message;
26959 +
26960 + if (dev->power.power_state.event != state->event) {
26961 + dev_warn(dev, "pm state does not match request\n");
26962 + return -1;
26963 + }
26964 +
26965 + return 0;
26966 +}
26967 +
26968 +static int coldfire_spi_suspend(struct platform_device *pdev,
26969 + pm_message_t state)
26970 +{
26971 + struct driver_data *drv_data = platform_get_drvdata(pdev);
26972 + int status = 0;
26973 +
26974 + /* Check all childern for current power state */
26975 + if (device_for_each_child(&pdev->dev,
26976 + &state, suspend_devices) != 0) {
26977 + dev_warn(&pdev->dev, "suspend aborted\n");
26978 + return -1;
26979 + }
26980 +
26981 + status = stop_queue(drv_data);
26982 + if (status != 0)
26983 + return status;
26984 +
26985 + return 0;
26986 +}
26987 +
26988 +static int coldfire_spi_resume(struct platform_device *pdev)
26989 +{
26990 + struct driver_data *drv_data = platform_get_drvdata(pdev);
26991 + int status = 0;
26992 +
26993 + /* Start the queue running */
26994 + status = start_queue(drv_data);
26995 + if (status != 0) {
26996 + dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
26997 + return status;
26998 + }
26999 +
27000 + return 0;
27001 +}
27002 +#else
27003 +#define coldfire_spi_suspend NULL
27004 +#define coldfire_spi_resume NULL
27005 +#endif /* CONFIG_PM */
27006 +
27007 +static struct platform_driver driver = {
27008 + .driver = {
27009 + .name = "spi_coldfire",
27010 + .bus = &platform_bus_type,
27011 + .owner = THIS_MODULE,
27012 + },
27013 + .probe = coldfire_spi_probe,
27014 + .remove = __devexit_p(coldfire_spi_remove),
27015 + .shutdown = coldfire_spi_shutdown,
27016 + .suspend = coldfire_spi_suspend,
27017 + .resume = coldfire_spi_resume,
27018 +};
27019 +
27020 +static int __init coldfire_spi_init(void)
27021 +{
27022 + platform_driver_register(&driver);
27023 +
27024 + return 0;
27025 +}
27026 +module_init(coldfire_spi_init);
27027 +
27028 +static void __exit coldfire_spi_exit(void)
27029 +{
27030 + platform_driver_unregister(&driver);
27031 +}
27032 +module_exit(coldfire_spi_exit);
27033 +
27034 +MODULE_AUTHOR("Matt Waddel");
27035 +MODULE_DESCRIPTION("ColdFire DSPI Contoller");
27036 +MODULE_LICENSE("GPL");
27037 --- a/drivers/spi/Kconfig
27038 +++ b/drivers/spi/Kconfig
27039 @@ -35,6 +35,15 @@ config SPI_DEBUG
27040 Say "yes" to enable debug messaging (like dev_dbg and pr_debug),
27041 sysfs, and debugfs support in SPI controller and protocol drivers.
27042
27043 +config COLDFIRE_EDMA
27044 + tristate "Coldfire eDMA"
27045 + depends on COLDFIRE && EXPERIMENTAL
27046 + help
27047 + Support for Coldfire eDMA controller. Required for example
27048 + by SSI audio device driver.
27049 +
27050 +
27051 +
27052 #
27053 # MASTER side ... talking to discrete SPI slave chips including microcontrollers
27054 #
27055 @@ -113,6 +122,27 @@ config SPI_GPIO
27056
27057 If unsure, say N.
27058
27059 +config SPI_COLDFIRE
27060 + tristate "Coldfire QSPI/DSPI SPI Master"
27061 + depends on SPI_MASTER && COLDFIRE && EXPERIMENTAL
27062 + help
27063 + SPI driver for Freescale Coldfire QSPI module in master mode.
27064 + Tested with the 5282 processor, but should also work with other
27065 + Coldfire variants.
27066 +
27067 +config SPI_DSPI
27068 + tristate "Coldfire DSPI"
27069 + depends on SPI_MASTER && COLDFIRE
27070 + help
27071 + SPI driver for Coldfire DSPI driver only.
27072 +
27073 +config SPI_COLDFIRE_DSPI_EDMA
27074 + boolean "Coldfire DSPI master driver uses eDMA"
27075 + depends on SPI_MASTER && COLDFIRE && SPI_COLDFIRE && EXPERIMENTAL && COLDFIRE_EDMA
27076 + default n
27077 + help
27078 + Say "yes" if you want DSPI master driver to use eDMA for transfers.
27079 +
27080 config SPI_IMX
27081 tristate "Freescale iMX SPI controller"
27082 depends on SPI_MASTER && ARCH_IMX && EXPERIMENTAL
27083 @@ -255,6 +285,18 @@ config SPI_TLE62X0
27084 #
27085 # Add new SPI protocol masters in alphabetical order above this line
27086 #
27087 +config SPI_COLDFIRE_SSI_AUDIO
27088 + tristate "Coldfire SSI AUDIO"
27089 + depends on SPI_MASTER && SPI_COLDFIRE && EXPERIMENTAL
27090 + help
27091 + SSI audio device driver
27092 +
27093 +config SSIAUDIO_USE_EDMA
27094 + boolean "Coldfire DSPI master driver uses eDMA"
27095 + default y
27096 + depends on EXPERIMENTAL && COLDFIRE_EDMA && SPI_COLDFIRE_SSI_AUDIO
27097 + help
27098 + Say "yes" if you want SSI audio driver to use eDMA for SSI transfers.
27099
27100 # (slave support would go here)
27101
27102 --- a/drivers/spi/Makefile
27103 +++ b/drivers/spi/Makefile
27104 @@ -6,6 +6,8 @@ ifeq ($(CONFIG_SPI_DEBUG),y)
27105 EXTRA_CFLAGS += -DDEBUG
27106 endif
27107
27108 +obj-$(CONFIG_COLDFIRE_EDMA) += coldfire_edma.o
27109 +
27110 # small core, mostly translating board-specific
27111 # config declarations into driver model code
27112 obj-$(CONFIG_SPI_MASTER) += spi.o
27113 @@ -16,6 +18,8 @@ obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.
27114 obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o
27115 obj-$(CONFIG_SPI_AU1550) += au1550_spi.o
27116 obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o
27117 +# obj-$(CONFIG_SPI_COLDFIRE) += spi_coldfire.o spi-m5445x.o
27118 +obj-$(CONFIG_SPI_DSPI) += dspi_mcf.o
27119 obj-$(CONFIG_SPI_GPIO) += spi_gpio.o
27120 obj-$(CONFIG_SPI_IMX) += spi_imx.o
27121 obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o
27122 @@ -35,6 +39,7 @@ obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci.
27123 obj-$(CONFIG_SPI_AT25) += at25.o
27124 obj-$(CONFIG_SPI_SPIDEV) += spidev.o
27125 obj-$(CONFIG_SPI_TLE62X0) += tle62x0.o
27126 +obj-$(CONFIG_SPI_COLDFIRE_SSI_AUDIO) += ssi_audio.o
27127 # ... add above this line ...
27128
27129 # SPI slave controller drivers (upstream link)
27130 --- /dev/null
27131 +++ b/drivers/spi/spi_coldfire.c
27132 @@ -0,0 +1,1542 @@
27133 +/*
27134 + * spi_coldfire.c - Master QSPI/DSPI controller for the ColdFire processors
27135 + *
27136 + *
27137 + * (C) Copyright 2005, Intec Automation,
27138 + * Mike Lavender (mike@steroidmicros)
27139 + *
27140 + * (C) Copyright 2007-2008, Freescale Inc,
27141 + * Yaroslav Vinogradov
27142 + * Andrey Butok
27143 + * Kurt Mahan
27144 + *
27145 + * This program is free software; you can redistribute it and/or modify it
27146 + * under the terms of the GNU General Public License as published by the
27147 + * Free Software Foundation; either version 2 of the License, or (at your
27148 + * option) any later version.
27149 + *
27150 + * This program is distributed in the hope that it will be useful,
27151 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
27152 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27153 + * GNU General Public License for more details.
27154 + *
27155 + * You should have received a copy of the GNU General Public License
27156 + * along with this program; if not, write to the Free Software
27157 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27158 + *
27159 + ***************************************************************************
27160 + * Changes:
27161 + * v0.003 12 February 2008 Andrey Butok, Freescale Semiconductor
27162 + * Added suport of MCF5227x DSPI module.
27163 + * v0.002 2007 Yaroslav Vinogradov, Freescale Semiconductor
27164 + * Added suport of MCF5445x DSPI module.
27165 + * v0.001 2005 Mike Lavender, Intec Automation,
27166 + * Intial version. Coldfire QSPI master driver.
27167 + *
27168 + */
27169 +
27170 +
27171 +/****************************************************************************/
27172 +
27173 +/*
27174 + * Includes
27175 + */
27176 +
27177 +#include <linux/autoconf.h>
27178 +#include <linux/init.h>
27179 +#include <linux/module.h>
27180 +#include <linux/device.h>
27181 +#include <linux/interrupt.h>
27182 +#include <linux/platform_device.h>
27183 +#include <linux/spi/spi.h>
27184 +#include <linux/workqueue.h>
27185 +#include <linux/delay.h>
27186 +
27187 +#include <asm/delay.h>
27188 +#include <asm/mcfsim.h>
27189 +#include <asm/mcfqspi.h>
27190 +#include <asm/coldfire.h>
27191 +
27192 +#if defined(CONFIG_M5445X)
27193 + #include <asm/virtconvert.h>
27194 +
27195 + #define SPI_DSPI
27196 + #if defined(CONFIG_SPI_COLDFIRE_DSPI_EDMA)
27197 + #define SPI_DSPI_EDMA
27198 + #ifdef CONFIG_MMU
27199 + #define SPI_USE_MMU
27200 + #endif
27201 + #include <asm/mcf5445x_edma.h>
27202 + #endif
27203 +
27204 + #include <asm/mcf5445x_dspi.h>
27205 +#endif
27206 +
27207 +#if defined(CONFIG_M547X_8X)
27208 + #define SPI_DSPI
27209 +
27210 + #include <asm/virtconvert.h>
27211 + #include <asm/m5485dspi.h>
27212 +#endif
27213 +
27214 +#ifdef CONFIG_M5227x
27215 + #define SPI_DSPI
27216 +
27217 + #if defined(CONFIG_SPI_COLDFIRE_DSPI_EDMA)
27218 + #define SPI_DSPI_EDMA
27219 + #endif
27220 +#endif
27221 +
27222 +
27223 +#if defined(SPI_DSPI_EDMA)
27224 +
27225 +/* edma buffer size in transfer units (32bits) */
27226 +#define EDMA_BUFFER_SIZE (PAGE_SIZE/4)
27227 +#define EDMA_BUFSIZE_KMALLOC (EDMA_BUFFER_SIZE*4)
27228 +
27229 +#define DSPI_DMA_RX_TCD MCF_EDMA_CHAN_DSPI_RX
27230 +#define DSPI_DMA_TX_TCD MCF_EDMA_CHAN_DSPI_TX
27231 +
27232 +#include <asm/mcf_edma.h>
27233 +#endif
27234 +
27235 +MODULE_AUTHOR("Mike Lavender");
27236 +MODULE_DESCRIPTION("ColdFire SPI Contoller");
27237 +MODULE_LICENSE("GPL");
27238 +
27239 +#define DRIVER_NAME "Coldfire QSPI/DSPI"
27240 +
27241 +/****************************************************************************/
27242 +
27243 +/*
27244 + * Local constants and macros
27245 + */
27246 +
27247 +#define QSPI_RAM_SIZE 0x10 /* 16 word table */
27248 +#define QSPI_TRANSMIT_RAM 0x00
27249 +#define QSPI_RECEIVE_RAM 0x10
27250 +#define QSPI_COMMAND_RAM 0x20
27251 +
27252 +#define QSPI_COMMAND 0x7000 /* 15: X = Continuous CS
27253 + * 14: 1 = Get BITSE from QMR[BITS]
27254 + * 13: 1 = Get DT from QDLYR[DTL]
27255 + * 12: 1 = Get DSK from QDLYR[QCD]
27256 + * 8-11: XXXX = next 4 bytes for CS
27257 + * 0-7: 0000 0000 Reserved
27258 + */
27259 +
27260 +#define QIR_WCEF 0x0008 /* write collison */
27261 +#define QIR_ABRT 0x0004 /* abort */
27262 +#define QIR_SPIF 0x0001 /* finished */
27263 +
27264 +#define QIR_WCEFE 0x0800
27265 +#define QIR_ABRTE 0x0400
27266 +#define QIR_SPIFE 0x0100
27267 +
27268 +#define QIR_WCEFB 0x8000
27269 +#define QIR_ABRTB 0x4000
27270 +#define QIR_ABRTL 0x1000
27271 +
27272 +#define QMR_BITS 0x3C00
27273 +#define QMR_BITS_8 0x2000
27274 +
27275 +#define QCR_CONT 0x8000
27276 +
27277 +#define QDLYR_SPE 0x8000
27278 +
27279 +#define QWR_ENDQP_MASK 0x0F00
27280 +#define QWR_CSIV 0x1000 /* 1 = active low chip selects */
27281 +
27282 +
27283 +#define START_STATE ((void*)0)
27284 +#define RUNNING_STATE ((void*)1)
27285 +#define DONE_STATE ((void*)2)
27286 +#define ERROR_STATE ((void*)-1)
27287 +
27288 +#define QUEUE_RUNNING 0
27289 +#define QUEUE_STOPPED 1
27290 +
27291 +/****************************************************************************/
27292 +
27293 +/*
27294 + * Local Data Structures
27295 + */
27296 +
27297 +struct transfer_state {
27298 + u32 index;
27299 + u32 len;
27300 + void *tx;
27301 + void *tx_end;
27302 + void *rx;
27303 + void *rx_end;
27304 + char flags;
27305 +#define TRAN_STATE_RX_VOID 0x01
27306 +#define TRAN_STATE_TX_VOID 0x02
27307 +#define TRAN_STATE_WORD_ODD_NUM 0x04
27308 + u8 cs;
27309 + u16 void_write_data;
27310 + unsigned cs_change:1;
27311 +};
27312 +
27313 +typedef struct {
27314 + unsigned master:1;
27315 + unsigned dohie:1;
27316 + unsigned bits:4;
27317 + unsigned cpol:1;
27318 + unsigned cpha:1;
27319 + unsigned baud:8;
27320 +} QMR;
27321 +
27322 +typedef struct {
27323 + unsigned spe:1;
27324 + unsigned qcd:7;
27325 + unsigned dtl:8;
27326 +} QDLYR;
27327 +
27328 +typedef struct {
27329 + unsigned halt:1;
27330 + unsigned wren:1;
27331 + unsigned wrto:1;
27332 + unsigned csiv:1;
27333 + unsigned endqp:4;
27334 + unsigned cptqp:4;
27335 + unsigned newqp:4;
27336 +} QWR;
27337 +
27338 +
27339 +typedef struct {
27340 + unsigned master:1;
27341 + unsigned cont_scke:1;
27342 + unsigned dconf:2;
27343 + unsigned frz:1;
27344 + unsigned mtfe:1;
27345 + unsigned pcsse:1;
27346 + unsigned rooe:1;
27347 + unsigned pcsis:8;
27348 + unsigned reserved15:1;
27349 + unsigned mdis:1;
27350 + unsigned dis_tx:1;
27351 + unsigned dis_rxf:1;
27352 + unsigned clr_tx:1;
27353 + unsigned clr_rxf:1;
27354 + unsigned smpl_pt:2;
27355 + unsigned reserved71:7;
27356 + unsigned halt:1;
27357 +} DSPI_MCR;
27358 +
27359 +typedef struct {
27360 + unsigned dbr:1;
27361 + unsigned fmsz:4;
27362 + unsigned cpol:1;
27363 + unsigned cpha:1;
27364 + unsigned lsbfe:1;
27365 + unsigned pcssck:2;
27366 + unsigned pasc:2;
27367 + unsigned pdt:2;
27368 + unsigned pbr:2;
27369 + unsigned cssck:4;
27370 + unsigned asc:4;
27371 + unsigned dt:4;
27372 + unsigned br:4;
27373 +} DSPI_CTAR;
27374 +
27375 +struct chip_data {
27376 +#if defined(SPI_DSPI)
27377 + /* dspi data */
27378 + union {
27379 + u32 mcr_val;
27380 + DSPI_MCR mcr;
27381 + };
27382 + union {
27383 + u32 ctar_val;
27384 + DSPI_CTAR ctar;
27385 + };
27386 +#else
27387 + union {
27388 + u16 qmr_val;
27389 + QMR qmr;
27390 + };
27391 + union {
27392 + u16 qdlyr_val;
27393 + QDLYR qdlyr;
27394 + };
27395 + union {
27396 + u16 qwr_val;
27397 + QWR qwr;
27398 + };
27399 +#endif
27400 +
27401 + u16 void_write_data;
27402 +};
27403 +
27404 +
27405 +struct driver_data {
27406 + /* Driver model hookup */
27407 + struct platform_device *pdev;
27408 +
27409 + /* SPI framework hookup */
27410 + struct spi_master *master;
27411 +
27412 + /* Driver message queue */
27413 + struct workqueue_struct *workqueue;
27414 + struct work_struct pump_messages;
27415 + spinlock_t lock;
27416 + struct list_head queue;
27417 + int busy;
27418 + int run;
27419 +
27420 + /* Message Transfer pump */
27421 + struct tasklet_struct pump_transfers;
27422 +
27423 + /* Current message transfer state info */
27424 + struct spi_message* cur_msg;
27425 + struct spi_transfer* cur_transfer;
27426 + struct chip_data *cur_chip;
27427 + size_t len;
27428 + void *tx;
27429 + void *tx_end;
27430 + void *rx;
27431 + void *rx_end;
27432 + char flags;
27433 +#define TRAN_STATE_RX_VOID 0x01
27434 +#define TRAN_STATE_TX_VOID 0x02
27435 +#define TRAN_STATE_WORD_ODD_NUM 0x04
27436 + u8 cs;
27437 + u16 void_write_data;
27438 + unsigned cs_change:1;
27439 +
27440 + u32 trans_cnt;
27441 + u32 wce_cnt;
27442 + u32 abrt_cnt;
27443 +#if defined(SPI_DSPI)
27444 + u32 *mcr; /* DSPI MCR register */
27445 + u32 *ctar; /* DSPI CTAR register */
27446 + u32 *dspi_dtfr; /* DSPI DTFR register */
27447 + u32 *dspi_drfr; /* DSPI DRFR register */
27448 + u32 *dspi_rser; /* DSPI RSER register */
27449 + u32 *dspi_sr; /* DSPI status register */
27450 + u8 dspi_ctas; /* DSPI CTAS value*/
27451 +#if defined(SPI_DSPI_EDMA)
27452 + void* edma_tx_buf;
27453 + void* edma_rx_buf;
27454 +#endif
27455 +#else
27456 + u16 *qmr; /* QSPI mode register */
27457 + u16 *qdlyr; /* QSPI delay register */
27458 + u16 *qwr; /* QSPI wrap register */
27459 + u16 *qir; /* QSPI interrupt register */
27460 + u16 *qar; /* QSPI address register */
27461 + u16 *qdr; /* QSPI data register */
27462 + u16 *qcr; /* QSPI command register */
27463 +#endif
27464 +#if defined(CONFIG_M532x) || defined(CONFIG_M537x)
27465 + u16 *par; /* Pin assignment register */
27466 +#else
27467 + u8 *par; /* Pin assignment register */
27468 +#endif
27469 + u8 *int_icr; /* Interrupt level and priority register */
27470 + u32 *int_mr; /* Interrupt mask register */
27471 + void (*cs_control)(u8 cs, u8 command);
27472 +};
27473 +
27474 +#define DSPI_CS(cs) ((1<<(cs))<<16)
27475 +
27476 +
27477 +/****************************************************************************/
27478 +
27479 +/*
27480 + * SPI local functions
27481 + */
27482 +
27483 +static void *next_transfer(struct driver_data *drv_data)
27484 +{
27485 + struct spi_message *msg = drv_data->cur_msg;
27486 + struct spi_transfer *trans = drv_data->cur_transfer;
27487 +
27488 + /* Move to next transfer */
27489 + if (trans->transfer_list.next != &msg->transfers) {
27490 + drv_data->cur_transfer =
27491 + list_entry(trans->transfer_list.next,
27492 + struct spi_transfer,
27493 + transfer_list);
27494 + return RUNNING_STATE;
27495 + } else
27496 + return DONE_STATE;
27497 +}
27498 +
27499 +
27500 +#define DSPI_BITS MCF_DSPI_DCTAR_FMSZ(15)
27501 +#define DSPI_BITS_16 MCF_DSPI_DCTAR_FMSZ(15)
27502 +#define DSPI_BITS_8 MCF_DSPI_DCTAR_FMSZ(7)
27503 +#define DSPI_FIFO_SIZE 16
27504 +
27505 +static inline int is_word_transfer(struct driver_data *drv_data)
27506 +{
27507 +#if defined(SPI_DSPI)
27508 + return ((*drv_data->ctar & DSPI_BITS_16) == DSPI_BITS_8) ? 0 : 1;
27509 +#else
27510 + return ((*drv_data->qmr & QMR_BITS) == QMR_BITS_8) ? 0 : 1;
27511 +#endif
27512 +}
27513 +
27514 +static void inline set_8bit_transfer_mode(struct driver_data *drv_data)
27515 +{
27516 +#if defined(SPI_DSPI)
27517 + *drv_data->ctar |= (*drv_data->ctar & ~DSPI_BITS) | DSPI_BITS_8;
27518 +#else
27519 + *drv_data->qmr |= (*drv_data->qmr & ~QMR_BITS) | QMR_BITS_8;
27520 +#endif
27521 +}
27522 +
27523 +static void inline set_16bit_transfer_mode(struct driver_data *drv_data)
27524 +{
27525 +#if defined(SPI_DSPI)
27526 + *drv_data->ctar |= (*drv_data->ctar & ~DSPI_BITS) | DSPI_BITS_16;
27527 +#else
27528 + *drv_data->qmr |= (*drv_data->qmr & ~QMR_BITS);
27529 +#endif
27530 +}
27531 +
27532 +static int write(struct driver_data *drv_data)
27533 +{
27534 + int tx_count = 0;
27535 +#ifndef SPI_DSPI
27536 + int cmd_count = 0;
27537 +#endif
27538 + int tx_word;
27539 +
27540 +#if defined(SPI_DSPI)
27541 +#if defined(SPI_DSPI_EDMA)
27542 + u32* edma_wr;
27543 +#endif
27544 + u16 d16;
27545 + u8 d8;
27546 + u32 dspi_pushr;
27547 + int first = 1;
27548 +#endif
27549 +
27550 + tx_word = is_word_transfer(drv_data);
27551 +
27552 + /* If we are in word mode, but only have a single byte to transfer
27553 + * then switch to byte mode temporarily. Will switch back at the
27554 + * end of the transfer. */
27555 + if (tx_word && ((drv_data->tx_end - drv_data->tx) == 1)) {
27556 + drv_data->flags |= TRAN_STATE_WORD_ODD_NUM;
27557 + set_8bit_transfer_mode(drv_data);
27558 + tx_word = 0;
27559 + }
27560 +
27561 +
27562 +#if defined(SPI_DSPI)
27563 +#if defined(SPI_DSPI_EDMA)
27564 + edma_wr = (u32*)(drv_data->edma_tx_buf);
27565 +#endif
27566 +
27567 +#if defined(SPI_DSPI_EDMA)
27568 + while ((drv_data->tx < drv_data->tx_end) && (tx_count < EDMA_BUFFER_SIZE)) {
27569 +#else
27570 + while ((drv_data->tx < drv_data->tx_end) && (tx_count < DSPI_FIFO_SIZE)) {
27571 +#endif
27572 + if (tx_word) {
27573 + if ((drv_data->tx_end - drv_data->tx) == 1)
27574 + break;
27575 + if (!(drv_data->flags & TRAN_STATE_TX_VOID)) {
27576 + d16 = *(u16 *)drv_data->tx;
27577 + } else {
27578 + d16 = drv_data->void_write_data;
27579 + }
27580 +
27581 + dspi_pushr = MCF_DSPI_DTFR_TXDATA(d16)
27582 + | DSPI_CS(drv_data->cs)
27583 + | MCF_DSPI_DTFR_CTAS(drv_data->dspi_ctas);
27584 + drv_data->tx += 2;
27585 +
27586 +#if defined(SPI_DSPI_EDMA)
27587 + if (drv_data->tx == drv_data->tx_end || tx_count==EDMA_BUFFER_SIZE-1) {
27588 +#else
27589 + if (drv_data->tx == drv_data->tx_end || tx_count==DSPI_FIFO_SIZE-1) {
27590 +#endif
27591 + /* last transfer in the queue */
27592 + dspi_pushr |= MCF_DSPI_DTFR_EOQ;
27593 + if (drv_data->cs_change) {
27594 + dspi_pushr &= ~MCF_DSPI_DTFR_CONT;
27595 + }
27596 + }
27597 +
27598 + if (first) {
27599 + first = 0;
27600 + dspi_pushr |= MCF_DSPI_DTFR_CTCNT; /* clear counter */
27601 + }
27602 +#if defined(SPI_DSPI_EDMA)
27603 + *edma_wr = dspi_pushr;
27604 + edma_wr++;
27605 +#else
27606 + *drv_data->dspi_dtfr = dspi_pushr;
27607 +#endif
27608 +
27609 +
27610 + } else {
27611 + if (!(drv_data->flags & TRAN_STATE_TX_VOID)) {
27612 + d8 = *(u8 *)drv_data->tx;
27613 + } else {
27614 + d8 = *(u8 *)&drv_data->void_write_data;
27615 + }
27616 +
27617 + dspi_pushr = MCF_DSPI_DTFR_TXDATA(d8)
27618 + | DSPI_CS(drv_data->cs)
27619 + | MCF_DSPI_DTFR_CTAS(drv_data->dspi_ctas)
27620 + | MCF_DSPI_DTFR_CONT;
27621 +
27622 + drv_data->tx++;
27623 +
27624 + if (drv_data->tx == drv_data->tx_end || tx_count==DSPI_FIFO_SIZE-1) {
27625 + /* last transfer in the queue */
27626 + dspi_pushr |= MCF_DSPI_DTFR_EOQ;
27627 + if (drv_data->cs_change) {
27628 + dspi_pushr &= ~MCF_DSPI_DTFR_CONT;
27629 + }
27630 + }
27631 +
27632 + if (first) {
27633 + first = 0;
27634 + dspi_pushr |= MCF_DSPI_DTFR_CTCNT; /* clear counter */
27635 + }
27636 +
27637 +#if defined(SPI_DSPI_EDMA)
27638 + *edma_wr = dspi_pushr;
27639 + edma_wr++;
27640 +#else
27641 + *drv_data->dspi_dtfr = dspi_pushr;
27642 +#endif
27643 +
27644 + }
27645 + tx_count++;
27646 + }
27647 +
27648 +#if defined(SPI_DSPI_EDMA)
27649 +
27650 + if (tx_count>0) {
27651 +
27652 + /* TBD: initiate eDMA transfer */
27653 + mcf_edma_set_tcd_params(DSPI_DMA_TX_TCD,
27654 +#ifdef SPI_USE_MMU
27655 + virt_to_phys(drv_data->edma_tx_buf),
27656 +#else
27657 + drv_data->edma_tx_buf,
27658 +#endif
27659 + (u32)drv_data->dspi_dtfr,
27660 + MCF_EDMA_TCD_ATTR_SSIZE_32BIT | MCF_EDMA_TCD_ATTR_DSIZE_32BIT,
27661 + 4, /* soff */
27662 + 4, /* nbytes */
27663 + 0, /* slast */
27664 + tx_count, /* citer */
27665 + tx_count, /* biter */
27666 + 0, /* doff */
27667 + 0, /* dlastsga */
27668 + 0, /* major_int */
27669 + 1 /* disable_req */
27670 + );
27671 +
27672 + mcf_edma_set_tcd_params(DSPI_DMA_RX_TCD,
27673 + (u32)drv_data->dspi_drfr,
27674 +#ifdef SPI_USE_MMU
27675 + virt_to_phys(drv_data->edma_rx_buf),
27676 +#else
27677 + drv_data->edma_rx_buf,
27678 +#endif
27679 + MCF_EDMA_TCD_ATTR_SSIZE_32BIT | MCF_EDMA_TCD_ATTR_DSIZE_32BIT,
27680 + 0, /* soff */
27681 + 4, /* nbytes */
27682 + 0, /* slast */
27683 + tx_count, /* citer */
27684 + tx_count, /* biter */
27685 + 4, /* doff */
27686 + 0, /* dlastsga */
27687 + 0, /* major_int */
27688 + 1 /* disable_req */
27689 + );
27690 +
27691 +
27692 + start_edma_transfer(DSPI_DMA_TX_TCD); /* transmit SPI data */
27693 + start_edma_transfer(DSPI_DMA_RX_TCD); /* receive SPI data */
27694 + }
27695 +#endif
27696 +
27697 +#else
27698 +
27699 + *drv_data->qar = QSPI_TRANSMIT_RAM;
27700 + while ((drv_data->tx < drv_data->tx_end) && (tx_count < QSPI_RAM_SIZE)) {
27701 + if (tx_word) {
27702 + if ((drv_data->tx_end - drv_data->tx) == 1)
27703 + break;
27704 +
27705 + if (!(drv_data->flags & TRAN_STATE_TX_VOID))
27706 + *drv_data->qdr = *(u16 *)drv_data->tx;
27707 + else
27708 + *drv_data->qdr = drv_data->void_write_data;
27709 + drv_data->tx += 2;
27710 + } else {
27711 + if (!(drv_data->flags & TRAN_STATE_TX_VOID))
27712 + *drv_data->qdr = *(u8 *)drv_data->tx;
27713 + else
27714 + *drv_data->qdr = *(u8 *)&drv_data->void_write_data;
27715 + drv_data->tx++;
27716 + }
27717 + tx_count++;
27718 + }
27719 +
27720 +
27721 + *drv_data->qar = QSPI_COMMAND_RAM;
27722 + while (cmd_count < tx_count) {
27723 + u16 qcr = QSPI_COMMAND
27724 + | QCR_CONT
27725 + | (~((0x01 << drv_data->cs) << 8) & 0x0F00);
27726 +
27727 + if ( (cmd_count == tx_count - 1)
27728 + && (drv_data->tx == drv_data->tx_end)
27729 + && (drv_data->cs_change) ) {
27730 + qcr &= ~QCR_CONT;
27731 + }
27732 + *drv_data->qcr = qcr;
27733 + cmd_count++;
27734 + }
27735 +
27736 + *drv_data->qwr = (*drv_data->qwr & ~QWR_ENDQP_MASK) | ((cmd_count - 1) << 8);
27737 +
27738 + /* Fire it up! */
27739 + *drv_data->qdlyr |= QDLYR_SPE;
27740 +#endif
27741 +
27742 + return tx_count;
27743 +}
27744 +
27745 +
27746 +static int read(struct driver_data *drv_data)
27747 +{
27748 + int rx_count = 0;
27749 + int rx_word;
27750 +#if defined(SPI_DSPI_EDMA)
27751 + u32* rx_edma;
27752 +#endif
27753 + u16 d;
27754 + rx_word = is_word_transfer(drv_data);
27755 +
27756 +#if defined(SPI_DSPI)
27757 +#if defined(SPI_DSPI_EDMA)
27758 + rx_edma = (u32*) drv_data->edma_tx_buf;
27759 + while ((drv_data->rx < drv_data->rx_end) && (rx_count < EDMA_BUFFER_SIZE)) {
27760 +#else
27761 + while ((drv_data->rx < drv_data->rx_end) && (rx_count < DSPI_FIFO_SIZE)) {
27762 +#endif
27763 + if (rx_word) {
27764 + if ((drv_data->rx_end - drv_data->rx) == 1)
27765 + break;
27766 +#if defined(SPI_DSPI_EDMA)
27767 + d = MCF_DSPI_DRFR_RXDATA(*rx_edma);
27768 + rx_edma++;
27769 +#else
27770 + d = MCF_DSPI_DRFR_RXDATA(*drv_data->dspi_drfr);
27771 +#endif
27772 +
27773 + if (!(drv_data->flags & TRAN_STATE_RX_VOID))
27774 + *(u16 *)drv_data->rx = d;
27775 + drv_data->rx += 2;
27776 + } else {
27777 +#if defined(SPI_DSPI_EDMA)
27778 + d = MCF_DSPI_DRFR_RXDATA(*rx_edma);
27779 + rx_edma++;
27780 +#else
27781 + d = MCF_DSPI_DRFR_RXDATA(*drv_data->dspi_drfr);
27782 +#endif
27783 + if (!(drv_data->flags & TRAN_STATE_RX_VOID))
27784 + *(u8 *)drv_data->rx = d;
27785 + drv_data->rx++;
27786 + }
27787 + rx_count++;
27788 + }
27789 +#else
27790 + *drv_data->qar = QSPI_RECEIVE_RAM;
27791 + while ((drv_data->rx < drv_data->rx_end) && (rx_count < QSPI_RAM_SIZE)) {
27792 + if (rx_word) {
27793 + if ((drv_data->rx_end - drv_data->rx) == 1)
27794 + break;
27795 +
27796 + if (!(drv_data->flags & TRAN_STATE_RX_VOID))
27797 + *(u16 *)drv_data->rx = *drv_data->qdr;
27798 + drv_data->rx += 2;
27799 + } else {
27800 + if (!(drv_data->flags & TRAN_STATE_RX_VOID))
27801 + *(u8 *)drv_data->rx = *drv_data->qdr;
27802 + drv_data->rx++;
27803 + }
27804 + rx_count++;
27805 + }
27806 +#endif
27807 +
27808 + return rx_count;
27809 +}
27810 +
27811 +
27812 +static inline void qspi_setup_chip(struct driver_data *drv_data)
27813 +{
27814 + struct chip_data *chip = drv_data->cur_chip;
27815 +
27816 +#if defined(SPI_DSPI)
27817 +
27818 + *drv_data->mcr = chip->mcr_val;
27819 +
27820 + /* TBD: remove later */
27821 +/* JKM -- validate */
27822 + chip->ctar_val = 0x78560118;
27823 +
27824 + *drv_data->ctar = chip->ctar_val;
27825 + *drv_data->dspi_rser = 0
27826 + | MCF_DSPI_DRSER_EOQFE
27827 +#if defined(SPI_DSPI_EDMA)
27828 + | MCF_DSPI_DRSER_TFFFE
27829 + | MCF_DSPI_DRSER_TFFFS
27830 +#endif
27831 + ;
27832 +#else
27833 + *drv_data->qmr = chip->qmr_val;
27834 + *drv_data->qdlyr = chip->qdlyr_val;
27835 + *drv_data->qwr = chip->qwr_val;
27836 +
27837 + /*
27838 + * Enable all the interrupts and clear all the flags
27839 + */
27840 + *drv_data->qir = (QIR_SPIFE | QIR_ABRTE | QIR_WCEFE)
27841 + | (QIR_WCEFB | QIR_ABRTB | QIR_ABRTL)
27842 + | (QIR_SPIF | QIR_ABRT | QIR_WCEF);
27843 +#endif
27844 +}
27845 +
27846 +#if defined(SPI_DSPI_EDMA)
27847 +static int edma_tx_handler(int channel, void* dev)
27848 +{
27849 + if (channel == DSPI_DMA_TX_TCD) {
27850 + stop_edma_transfer(DSPI_DMA_TX_TCD);
27851 + }
27852 + return IRQ_HANDLED;
27853 +}
27854 +
27855 +static int edma_rx_handler(int channel, void* dev)
27856 +{
27857 + if (channel == DSPI_DMA_RX_TCD) {
27858 + stop_edma_transfer(DSPI_DMA_RX_TCD);
27859 + }
27860 +
27861 + return IRQ_HANDLED;
27862 +}
27863 +#endif
27864 +
27865 +static irqreturn_t qspi_interrupt(int irq, void *dev_id)
27866 +{
27867 + struct driver_data *drv_data = (struct driver_data *)dev_id;
27868 + struct spi_message *msg = drv_data->cur_msg;
27869 +#if defined(SPI_DSPI)
27870 +#if !defined(SPI_DSPI_EDMA)
27871 + u32 irq_status = *drv_data->dspi_sr;
27872 +#endif
27873 +#else
27874 + u16 irq_status = *drv_data->qir;
27875 +#endif
27876 +
27877 + /* Clear all flags immediately */
27878 +#if defined(SPI_DSPI)
27879 + *drv_data->dspi_sr = MCF_DSPI_DSR_EOQF;
27880 +#else
27881 + *drv_data->qir |= (QIR_SPIF | QIR_ABRT | QIR_WCEF);
27882 +#endif
27883 +
27884 + if (!drv_data->cur_msg || !drv_data->cur_msg->state) {
27885 +#if !defined(SPI_DSPI_EDMA)
27886 + /* if eDMA is used it happens some time (at least once)*/
27887 + printk(KERN_ERR "coldfire-qspi: bad message or transfer "
27888 + "state in interrupt handler. IRQ status=%x\n", irq_status);
27889 +#endif
27890 + return IRQ_NONE;
27891 + }
27892 +
27893 +#if !defined(SPI_DSPI)
27894 + if (irq_status & QIR_SPIF) {
27895 +#endif
27896 + /*
27897 + * Read the data into the buffer and reload and start
27898 + * queue with new data if not finished. If finished
27899 + * then setup the next transfer
27900 + */
27901 + read(drv_data);
27902 +
27903 + if (drv_data->rx == drv_data->rx_end) {
27904 + /*
27905 + * Finished now - fall through and schedule next
27906 + * transfer tasklet
27907 + */
27908 + if (drv_data->flags & TRAN_STATE_WORD_ODD_NUM) {
27909 + set_16bit_transfer_mode(drv_data);
27910 + }
27911 +
27912 + msg->state = next_transfer(drv_data);
27913 + msg->actual_length += drv_data->len;
27914 + } else {
27915 + /* not finished yet - keep going */
27916 + write(drv_data);
27917 + return IRQ_HANDLED;
27918 + }
27919 +#if !defined(SPI_DSPI)
27920 + } else {
27921 + if (irq_status & QIR_WCEF)
27922 + drv_data->wce_cnt++;
27923 +
27924 + if (irq_status & QIR_ABRT)
27925 + drv_data->abrt_cnt++;
27926 +
27927 + msg->state = ERROR_STATE;
27928 + }
27929 +#endif
27930 +
27931 + tasklet_schedule(&drv_data->pump_transfers);
27932 +
27933 + return IRQ_HANDLED;
27934 +}
27935 +
27936 +/* caller already set message->status; dma and pio irqs are blocked */
27937 +static void giveback(struct driver_data *drv_data)
27938 +{
27939 + struct spi_transfer* last_transfer;
27940 + unsigned long flags;
27941 + struct spi_message *msg;
27942 +
27943 + spin_lock_irqsave(&drv_data->lock, flags);
27944 + msg = drv_data->cur_msg;
27945 + drv_data->cur_msg = NULL;
27946 + drv_data->cur_transfer = NULL;
27947 + drv_data->cur_chip = NULL;
27948 + queue_work(drv_data->workqueue, &drv_data->pump_messages);
27949 + spin_unlock_irqrestore(&drv_data->lock, flags);
27950 +
27951 + last_transfer = list_entry(msg->transfers.prev,
27952 + struct spi_transfer,
27953 + transfer_list);
27954 +
27955 + if (!last_transfer->cs_change)
27956 + drv_data->cs_control(drv_data->cs, QSPI_CS_DROP);
27957 +
27958 + msg->state = NULL;
27959 + if (msg->complete)
27960 + msg->complete(msg->context);
27961 +}
27962 +
27963 +
27964 +static void pump_transfers(unsigned long data)
27965 +{
27966 + struct driver_data *drv_data = (struct driver_data *)data;
27967 + struct spi_message *message = NULL;
27968 + struct spi_transfer *transfer = NULL;
27969 + struct spi_transfer *previous = NULL;
27970 + struct chip_data *chip = NULL;
27971 + unsigned long flags;
27972 +
27973 + /* Get current state information */
27974 + message = drv_data->cur_msg;
27975 + transfer = drv_data->cur_transfer;
27976 + chip = drv_data->cur_chip;
27977 +
27978 + /* Handle for abort */
27979 + if (message->state == ERROR_STATE) {
27980 + message->status = -EIO;
27981 + giveback(drv_data);
27982 + return;
27983 + }
27984 +
27985 + /* Handle end of message */
27986 + if (message->state == DONE_STATE) {
27987 + message->status = 0;
27988 + giveback(drv_data);
27989 + return;
27990 + }
27991 +
27992 + if (message->state == START_STATE) {
27993 + qspi_setup_chip(drv_data);
27994 +
27995 + if (drv_data->cs_control)
27996 + drv_data->cs_control(message->spi->chip_select, QSPI_CS_ASSERT);
27997 + }
27998 +
27999 + /* Delay if requested at end of transfer*/
28000 + if (message->state == RUNNING_STATE) {
28001 + previous = list_entry(transfer->transfer_list.prev,
28002 + struct spi_transfer,
28003 + transfer_list);
28004 +
28005 + if (drv_data->cs_control && transfer->cs_change)
28006 + drv_data->cs_control(message->spi->chip_select, QSPI_CS_DROP);
28007 +
28008 + if (previous->delay_usecs)
28009 + udelay(previous->delay_usecs);
28010 +
28011 + if (drv_data->cs_control && transfer->cs_change)
28012 + drv_data->cs_control(message->spi->chip_select, QSPI_CS_ASSERT);
28013 + }
28014 +
28015 + drv_data->flags = 0;
28016 + drv_data->tx = (void *)transfer->tx_buf;
28017 + drv_data->tx_end = drv_data->tx + transfer->len;
28018 + drv_data->rx = transfer->rx_buf;
28019 + drv_data->rx_end = drv_data->rx + transfer->len;
28020 + drv_data->len = transfer->len;
28021 + if (!drv_data->rx)
28022 + drv_data->flags |= TRAN_STATE_RX_VOID;
28023 + if (!drv_data->tx)
28024 + drv_data->flags |= TRAN_STATE_TX_VOID;
28025 + drv_data->cs = message->spi->chip_select;
28026 + drv_data->cs_change = transfer->cs_change;
28027 + drv_data->void_write_data = chip->void_write_data;
28028 +
28029 + message->state = RUNNING_STATE;
28030 +
28031 + /* Go baby, go */
28032 + local_irq_save(flags);
28033 + write(drv_data);
28034 + local_irq_restore(flags);
28035 +}
28036 +
28037 +
28038 +static void pump_messages(struct work_struct *work)
28039 +{
28040 + struct driver_data *drv_data;
28041 + unsigned long flags;
28042 +
28043 + drv_data = container_of(work, struct driver_data, pump_messages);
28044 +
28045 + /* Lock queue and check for queue work */
28046 + spin_lock_irqsave(&drv_data->lock, flags);
28047 + if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
28048 + drv_data->busy = 0;
28049 + spin_unlock_irqrestore(&drv_data->lock, flags);
28050 + return;
28051 + }
28052 +
28053 + /* Make sure we are not already running a message */
28054 + if (drv_data->cur_msg) {
28055 + spin_unlock_irqrestore(&drv_data->lock, flags);
28056 + return;
28057 + }
28058 +
28059 + /* Extract head of queue */
28060 + drv_data->cur_msg = list_entry(drv_data->queue.next,
28061 + struct spi_message, queue);
28062 + list_del_init(&drv_data->cur_msg->queue);
28063 +
28064 + /* Initial message state*/
28065 + drv_data->cur_msg->state = START_STATE;
28066 + drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
28067 + struct spi_transfer,
28068 + transfer_list);
28069 +
28070 + /* Setup the SPI Registers using the per chip configuration */
28071 + drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
28072 +
28073 + /* Mark as busy and launch transfers */
28074 + tasklet_schedule(&drv_data->pump_transfers);
28075 +
28076 + drv_data->busy = 1;
28077 + spin_unlock_irqrestore(&drv_data->lock, flags);
28078 +}
28079 +
28080 +/****************************************************************************/
28081 +
28082 +/*
28083 + * SPI master implementation
28084 + */
28085 +
28086 +static int transfer(struct spi_device *spi, struct spi_message *msg)
28087 +{
28088 + struct driver_data *drv_data = spi_master_get_devdata(spi->master);
28089 + unsigned long flags;
28090 +
28091 + spin_lock_irqsave(&drv_data->lock, flags);
28092 +
28093 + if (drv_data->run == QUEUE_STOPPED) {
28094 + spin_unlock_irqrestore(&drv_data->lock, flags);
28095 + return -ESHUTDOWN;
28096 + }
28097 +
28098 + msg->actual_length = 0;
28099 + msg->status = -EINPROGRESS;
28100 + msg->state = START_STATE;
28101 +
28102 + list_add_tail(&msg->queue, &drv_data->queue);
28103 +
28104 + if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
28105 + queue_work(drv_data->workqueue, &drv_data->pump_messages);
28106 +
28107 + spin_unlock_irqrestore(&drv_data->lock, flags);
28108 +
28109 + return 0;
28110 +}
28111 +
28112 +
28113 +static int setup(struct spi_device *spi)
28114 +{
28115 + struct coldfire_spi_chip *chip_info;
28116 + struct chip_data *chip;
28117 +#ifndef SPI_DSPI
28118 + u32 baud_divisor = 255;
28119 +#endif
28120 +
28121 + chip_info = (struct coldfire_spi_chip *)spi->controller_data;
28122 +
28123 + /* Only alloc on first setup */
28124 + chip = spi_get_ctldata(spi);
28125 + if (chip == NULL) {
28126 + chip = kcalloc(1, sizeof(struct chip_data), GFP_KERNEL);
28127 + if (!chip)
28128 + return -ENOMEM;
28129 + spi->mode = chip_info->mode;
28130 + spi->bits_per_word = chip_info->bits_per_word;
28131 + }
28132 +
28133 +#if defined(SPI_DSPI)
28134 + chip->mcr.master = 1;
28135 + chip->mcr.cont_scke = 0;
28136 + chip->mcr.dconf = 0;
28137 + chip->mcr.frz = 0;
28138 + chip->mcr.mtfe = 0;
28139 + chip->mcr.pcsse = 0;
28140 + chip->mcr.rooe = 0;
28141 + chip->mcr.pcsis = 0xFF;
28142 + chip->mcr.reserved15 = 0;
28143 + chip->mcr.mdis = 0;
28144 + chip->mcr.dis_tx = 0;
28145 + chip->mcr.dis_rxf = 0;
28146 + chip->mcr.clr_tx = 1;
28147 + chip->mcr.clr_rxf = 1;
28148 + chip->mcr.smpl_pt = 0;
28149 + chip->mcr.reserved71 = 0;
28150 + chip->mcr.halt = 0;
28151 +
28152 + if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
28153 + chip->ctar.fmsz = spi->bits_per_word-1;
28154 + } else {
28155 + printk(KERN_ERR "coldfire-spi: invalid wordsize\n");
28156 + kfree(chip);
28157 + return -ENODEV;
28158 + }
28159 +
28160 + if (spi->mode & SPI_CPHA)
28161 + chip->ctar.cpha = 1;
28162 + else
28163 + chip->ctar.cpha = 0;
28164 +
28165 + if (spi->mode & SPI_CPOL)
28166 + chip->ctar.cpol = 1;
28167 + else
28168 + chip->ctar.cpol = 0;
28169 +
28170 + if (spi->mode & SPI_LSB_FIRST)
28171 + chip->ctar.lsbfe = 1;
28172 + else
28173 + chip->ctar.lsbfe = 0;
28174 +
28175 + /* This values are default for audio device */
28176 + chip->ctar.dbr = 0;
28177 + chip->ctar.pbr = 2;
28178 + chip->ctar.br = 8;
28179 +
28180 + /* This values are default for audio device */
28181 + chip->ctar.pcssck = 1;
28182 + chip->ctar.pasc = 1;
28183 + chip->ctar.pdt = 1;
28184 + chip->ctar.cssck = 0;
28185 + chip->ctar.asc = 1;
28186 + chip->ctar.dt = 1;
28187 +
28188 + chip->void_write_data = chip_info->void_write_data;
28189 +
28190 +#else
28191 +
28192 + chip->qwr.csiv = 1; /* Chip selects are active low */
28193 + chip->qmr.master = 1; /* Must set to master mode */
28194 + chip->qmr.dohie = 1; /* Data output high impediance enabled */
28195 + chip->void_write_data = chip_info->void_write_data;
28196 +
28197 + chip->qdlyr.qcd = chip_info->del_cs_to_clk;
28198 + chip->qdlyr.dtl = chip_info->del_after_trans;
28199 +
28200 + if (spi->max_speed_hz != 0)
28201 + baud_divisor = (MCF_CLK/(2*spi->max_speed_hz));
28202 +
28203 + if (baud_divisor < 2)
28204 + baud_divisor = 2;
28205 +
28206 + if (baud_divisor > 255)
28207 + baud_divisor = 255;
28208 +
28209 + chip->qmr.baud = baud_divisor;
28210 +
28211 + /*printk( "SPI: spi->max_speed_hz %d\n", spi->max_speed_hz );*/
28212 + /*printk( "SPI: Baud set to %d\n", chip->qmr.baud );*/
28213 +
28214 + if (spi->mode & SPI_CPHA)
28215 + chip->qmr.cpha = 1;
28216 +
28217 + if (spi->mode & SPI_CPOL)
28218 + chip->qmr.cpol = 1;
28219 +
28220 + if (spi->bits_per_word == 16) {
28221 + chip->qmr.bits = 0;
28222 + } else if ((spi->bits_per_word >= 8) && (spi->bits_per_word <= 15)) {
28223 + chip->qmr.bits = spi->bits_per_word;
28224 + } else {
28225 + printk(KERN_ERR "coldfire-spi: invalid wordsize\n");
28226 + kfree(chip);
28227 + return -ENODEV;
28228 + }
28229 +
28230 +#endif
28231 +
28232 + spi_set_ctldata(spi, chip);
28233 +
28234 + return 0;
28235 +}
28236 +
28237 +static int init_queue(struct driver_data *drv_data)
28238 +{
28239 + INIT_LIST_HEAD(&drv_data->queue);
28240 + spin_lock_init(&drv_data->lock);
28241 +
28242 + drv_data->run = QUEUE_STOPPED;
28243 + drv_data->busy = 0;
28244 +
28245 + tasklet_init(&drv_data->pump_transfers,
28246 + pump_transfers, (unsigned long)drv_data);
28247 +
28248 + INIT_WORK(&drv_data->pump_messages, pump_messages);
28249 +
28250 + drv_data->workqueue = create_singlethread_workqueue(
28251 + drv_data->master->dev.parent->bus_id);
28252 + if (drv_data->workqueue == NULL)
28253 + return -EBUSY;
28254 +
28255 + return 0;
28256 +}
28257 +
28258 +static int start_queue(struct driver_data *drv_data)
28259 +{
28260 + unsigned long flags;
28261 +
28262 + spin_lock_irqsave(&drv_data->lock, flags);
28263 +
28264 + if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
28265 + spin_unlock_irqrestore(&drv_data->lock, flags);
28266 + return -EBUSY;
28267 + }
28268 +
28269 + drv_data->run = QUEUE_RUNNING;
28270 + drv_data->cur_msg = NULL;
28271 + drv_data->cur_transfer = NULL;
28272 + drv_data->cur_chip = NULL;
28273 + spin_unlock_irqrestore(&drv_data->lock, flags);
28274 +
28275 + queue_work(drv_data->workqueue, &drv_data->pump_messages);
28276 +
28277 + return 0;
28278 +}
28279 +
28280 +static int stop_queue(struct driver_data *drv_data)
28281 +{
28282 + unsigned long flags;
28283 + unsigned limit = 500;
28284 + int status = 0;
28285 +
28286 + spin_lock_irqsave(&drv_data->lock, flags);
28287 +
28288 + /* This is a bit lame, but is optimized for the common execution path.
28289 + * A wait_queue on the drv_data->busy could be used, but then the common
28290 + * execution path (pump_messages) would be required to call wake_up or
28291 + * friends on every SPI message. Do this instead */
28292 + drv_data->run = QUEUE_STOPPED;
28293 + while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
28294 + spin_unlock_irqrestore(&drv_data->lock, flags);
28295 + msleep(10);
28296 + spin_lock_irqsave(&drv_data->lock, flags);
28297 + }
28298 +
28299 + if (!list_empty(&drv_data->queue) || drv_data->busy)
28300 + status = -EBUSY;
28301 +
28302 + spin_unlock_irqrestore(&drv_data->lock, flags);
28303 +
28304 + return status;
28305 +}
28306 +
28307 +static int destroy_queue(struct driver_data *drv_data)
28308 +{
28309 + int status;
28310 +
28311 + status = stop_queue(drv_data);
28312 + if (status != 0)
28313 + return status;
28314 +
28315 + destroy_workqueue(drv_data->workqueue);
28316 +
28317 + return 0;
28318 +}
28319 +
28320 +
28321 +static void cleanup(struct spi_device *spi)
28322 +{
28323 + struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
28324 +
28325 + dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
28326 + spi->master->bus_num, spi->chip_select);
28327 +
28328 + kfree(chip);
28329 +}
28330 +
28331 +
28332 +/****************************************************************************/
28333 +
28334 +/*
28335 + * Generic Device driver routines and interface implementation
28336 + */
28337 +
28338 +static int coldfire_spi_probe(struct platform_device *pdev)
28339 +{
28340 + struct device *dev = &pdev->dev;
28341 + struct coldfire_spi_master *platform_info;
28342 + struct spi_master *master;
28343 + struct driver_data *drv_data = 0;
28344 + struct resource *memory_resource;
28345 + int irq;
28346 + int status = 0;
28347 + int i;
28348 +
28349 + platform_info = (struct coldfire_spi_master *)pdev->dev.platform_data;
28350 +
28351 + master = spi_alloc_master(dev, sizeof(struct driver_data));
28352 + if (!master)
28353 + return -ENOMEM;
28354 +
28355 + drv_data = spi_master_get_devdata(master);
28356 + drv_data->master = master;
28357 +
28358 + INIT_LIST_HEAD(&drv_data->queue);
28359 + spin_lock_init(&drv_data->lock);
28360 +
28361 + master->bus_num = platform_info->bus_num;
28362 + master->num_chipselect = platform_info->num_chipselect;
28363 + master->cleanup = cleanup;
28364 + master->setup = setup;
28365 + master->transfer = transfer;
28366 +
28367 + drv_data->cs_control = platform_info->cs_control;
28368 + if (drv_data->cs_control)
28369 + for(i = 0; i < master->num_chipselect; i++)
28370 + drv_data->cs_control(i, QSPI_CS_INIT | QSPI_CS_DROP);
28371 +
28372 + /* Setup register addresses */
28373 + memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spi-module");
28374 + if (!memory_resource) {
28375 + dev_dbg(dev, "can not find platform module memory\n");
28376 + goto out_error_master_alloc;
28377 + }
28378 +
28379 +#if defined(SPI_DSPI_EDMA)
28380 + drv_data->edma_tx_buf = kmalloc(EDMA_BUFSIZE_KMALLOC, GFP_DMA);
28381 + if (!drv_data->edma_tx_buf) {
28382 + dev_dbg(dev, "cannot allocate eDMA TX memory\n");
28383 + goto out_error_master_alloc;
28384 + }
28385 + drv_data->edma_rx_buf = kmalloc(EDMA_BUFSIZE_KMALLOC, GFP_DMA);
28386 + if (!drv_data->edma_rx_buf) {
28387 + kfree(drv_data->edma_tx_buf);
28388 + dev_dbg(dev, "cannot allocate eDMA RX memory\n");
28389 + goto out_error_master_alloc;
28390 + }
28391 +#endif
28392 +
28393 +#if defined(SPI_DSPI)
28394 +
28395 + drv_data->mcr = (void *)(memory_resource->start + 0x00000000);
28396 + drv_data->ctar = (void *)(memory_resource->start + 0x0000000C);
28397 + drv_data->dspi_sr = (void *)(memory_resource->start + 0x0000002C);
28398 + drv_data->dspi_rser = (void *)(memory_resource->start + 0x00000030);
28399 + drv_data->dspi_dtfr = (void *)(memory_resource->start + 0x00000034);
28400 + drv_data->dspi_drfr = (void *)(memory_resource->start + 0x00000038);
28401 +
28402 +#else
28403 +
28404 + drv_data->qmr = (void *)(memory_resource->start + 0x00000000);
28405 + drv_data->qdlyr = (void *)(memory_resource->start + 0x00000004);
28406 + drv_data->qwr = (void *)(memory_resource->start + 0x00000008);
28407 + drv_data->qir = (void *)(memory_resource->start + 0x0000000c);
28408 + drv_data->qar = (void *)(memory_resource->start + 0x00000010);
28409 + drv_data->qdr = (void *)(memory_resource->start + 0x00000014);
28410 + drv_data->qcr = (void *)(memory_resource->start + 0x00000014);
28411 +
28412 +#endif
28413 +
28414 + /* Setup register addresses */
28415 + memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spi-par");
28416 + if (!memory_resource) {
28417 + dev_dbg(dev, "can not find platform par memory\n");
28418 + goto out_error_master_alloc;
28419 + }
28420 +
28421 + drv_data->par = (void *)memory_resource->start;
28422 +
28423 + /* Setup register addresses */
28424 + memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spi-int-level");
28425 + if (!memory_resource) {
28426 + dev_dbg(dev, "can not find platform par memory\n");
28427 + goto out_error_master_alloc;
28428 + }
28429 +
28430 + drv_data->int_icr = (void *)memory_resource->start;
28431 +
28432 + /* Setup register addresses */
28433 + memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spi-int-mask");
28434 + if (!memory_resource) {
28435 + dev_dbg(dev, "can not find platform par memory\n");
28436 + goto out_error_master_alloc;
28437 + }
28438 +
28439 + drv_data->int_mr = (void *)memory_resource->start;
28440 +
28441 + if (platform_info->irq_list) {
28442 + /* multiple IRQs */
28443 + int *irqlist = platform_info->irq_list;
28444 + while ((irq = *irqlist++)) {
28445 + int off = *irqlist++;
28446 + int lvl = *irqlist++;
28447 + int msk = *irqlist++;
28448 + status = request_irq(irq, qspi_interrupt, IRQF_DISABLED,
28449 + dev->bus_id, drv_data);
28450 + if (status < 0) {
28451 + dev_err(&pdev->dev,
28452 + "unable to attach ColdFire DSPI interrupt\n");
28453 + goto out_error_master_alloc;
28454 + }
28455 +
28456 + if (lvl)
28457 + *(drv_data->int_icr + off) = lvl;
28458 +
28459 + if (msk)
28460 + *drv_data->int_mr &= ~msk;
28461 + }
28462 + }
28463 + else {
28464 + irq = platform_info->irq_vector;
28465 +
28466 + status = request_irq(platform_info->irq_vector, qspi_interrupt,
28467 + IRQF_DISABLED, dev->bus_id, drv_data);
28468 + if (status < 0) {
28469 + dev_err(&pdev->dev, "unable to attach ColdFire QSPI interrupt\n");
28470 + goto out_error_master_alloc;
28471 + }
28472 +
28473 + *drv_data->int_icr = platform_info->irq_lp;
28474 + *drv_data->int_mr &= ~platform_info->irq_mask;
28475 + }
28476 +
28477 + /* Now that we have all the addresses etc. Let's set it up */
28478 + if (platform_info->par_val)
28479 + *drv_data->par = platform_info->par_val;
28480 +
28481 +#ifdef CONFIG_M5227x
28482 + MCF_GPIO_PAR_IRQ = 0x04; /* Mistake in RM documentation */
28483 +#endif
28484 +
28485 +#ifdef SPI_DSPI
28486 + drv_data->dspi_ctas = 0; /* TBD: change later */
28487 +#endif
28488 +
28489 + /* Initial and start queue */
28490 + status = init_queue(drv_data);
28491 + if (status != 0) {
28492 + dev_err(&pdev->dev, "problem initializing queue\n");
28493 + goto out_error_irq_alloc;
28494 + }
28495 + status = start_queue(drv_data);
28496 + if (status != 0) {
28497 + dev_err(&pdev->dev, "problem starting queue\n");
28498 + goto out_error_irq_alloc;
28499 + }
28500 +
28501 + /* Register with the SPI framework */
28502 + platform_set_drvdata(pdev, drv_data);
28503 + status = spi_register_master(master);
28504 + if (status != 0) {
28505 + dev_err(&pdev->dev, "problem registering spi master\n");
28506 + status = -EINVAL;
28507 + goto out_error_queue_alloc;
28508 + }
28509 +
28510 +#if defined(SPI_DSPI_EDMA)
28511 + if (mcf_edma_request_channel(DSPI_DMA_TX_TCD,
28512 + edma_tx_handler,
28513 + NULL,
28514 + pdev,
28515 + NULL, /* spinlock */
28516 + DRIVER_NAME
28517 + )!=0) {
28518 + dev_err(&pdev->dev, "problem requesting edma transmit channel\n");
28519 + status = -EINVAL;
28520 + goto out_error_queue_alloc;
28521 + }
28522 +
28523 + if (mcf_edma_request_channel(DSPI_DMA_RX_TCD,
28524 + edma_rx_handler,
28525 + NULL,
28526 + pdev,
28527 + NULL, /* spinlock */
28528 + DRIVER_NAME
28529 + )!=0) {
28530 + dev_err(&pdev->dev, "problem requesting edma receive channel\n");
28531 + status = -EINVAL;
28532 + goto out_edma_transmit;
28533 + }
28534 +#endif
28535 +
28536 + printk(KERN_INFO "SPI: Coldfire master initialized\n" );
28537 + return status;
28538 +
28539 +#if defined(SPI_DSPI_EDMA)
28540 +out_edma_transmit:
28541 + mcf_edma_free_channel(DSPI_DMA_TX_TCD, pdev);
28542 +#endif
28543 +
28544 +out_error_queue_alloc:
28545 + destroy_queue(drv_data);
28546 +
28547 +out_error_irq_alloc:
28548 + free_irq(irq, drv_data);
28549 +
28550 +out_error_master_alloc:
28551 + spi_master_put(master);
28552 + return status;
28553 +
28554 +}
28555 +
28556 +static int coldfire_spi_remove(struct platform_device *pdev)
28557 +{
28558 + struct driver_data *drv_data = platform_get_drvdata(pdev);
28559 + int irq;
28560 + int status = 0;
28561 +
28562 + if (!drv_data)
28563 + return 0;
28564 +
28565 +#if defined(SPI_DSPI_EDMA)
28566 + mcf_edma_free_channel(DSPI_DMA_TX_TCD, pdev);
28567 + mcf_edma_free_channel(DSPI_DMA_RX_TCD, pdev);
28568 +#endif
28569 +
28570 + /* Remove the queue */
28571 + status = destroy_queue(drv_data);
28572 + if (status != 0)
28573 + return status;
28574 +
28575 + /* Release IRQ */
28576 +/* JKM -- check for list and remove list */
28577 + irq = platform_get_irq(pdev, 0);
28578 + if (irq >= 0)
28579 + free_irq(irq, drv_data);
28580 +
28581 + /* Disconnect from the SPI framework */
28582 + spi_unregister_master(drv_data->master);
28583 +
28584 + /* Prevent double remove */
28585 + platform_set_drvdata(pdev, NULL);
28586 +
28587 + return 0;
28588 +}
28589 +
28590 +static void coldfire_spi_shutdown(struct platform_device *pdev)
28591 +{
28592 + int status = 0;
28593 +
28594 + if ((status = coldfire_spi_remove(pdev)) != 0)
28595 + dev_err(&pdev->dev, "shutdown failed with %d\n", status);
28596 +}
28597 +
28598 +
28599 +#ifdef CONFIG_PM
28600 +static int suspend_devices(struct device *dev, void *pm_message)
28601 +{
28602 + pm_message_t *state = pm_message;
28603 +
28604 + if (dev->power.power_state.event != state->event) {
28605 + dev_warn(dev, "pm state does not match request\n");
28606 + return -1;
28607 + }
28608 +
28609 + return 0;
28610 +}
28611 +
28612 +static int coldfire_spi_suspend(struct platform_device *pdev, pm_message_t state)
28613 +{
28614 + struct driver_data *drv_data = platform_get_drvdata(pdev);
28615 + int status = 0;
28616 +
28617 + /* Check all childern for current power state */
28618 + if (device_for_each_child(&pdev->dev, &state, suspend_devices) != 0) {
28619 + dev_warn(&pdev->dev, "suspend aborted\n");
28620 + return -1;
28621 + }
28622 +
28623 + status = stop_queue(drv_data);
28624 + if (status != 0)
28625 + return status;
28626 +
28627 + return 0;
28628 +}
28629 +
28630 +static int coldfire_spi_resume(struct platform_device *pdev)
28631 +{
28632 + struct driver_data *drv_data = platform_get_drvdata(pdev);
28633 + int status = 0;
28634 +
28635 + /* Start the queue running */
28636 + status = start_queue(drv_data);
28637 + if (status != 0) {
28638 + dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
28639 + return status;
28640 + }
28641 +
28642 + return 0;
28643 +}
28644 +#else
28645 +#define coldfire_spi_suspend NULL
28646 +#define coldfire_spi_resume NULL
28647 +#endif /* CONFIG_PM */
28648 +
28649 +static struct platform_driver driver = {
28650 + .driver = {
28651 + .name = "spi_coldfire",
28652 + .bus = &platform_bus_type,
28653 + .owner = THIS_MODULE,
28654 + },
28655 + .probe = coldfire_spi_probe,
28656 + .remove = __devexit_p(coldfire_spi_remove),
28657 + .shutdown = coldfire_spi_shutdown,
28658 + .suspend = coldfire_spi_suspend,
28659 + .resume = coldfire_spi_resume,
28660 +};
28661 +
28662 +static int __init coldfire_spi_init(void)
28663 +{
28664 + platform_driver_register(&driver);
28665 +
28666 + return 0;
28667 +}
28668 +module_init(coldfire_spi_init);
28669 +
28670 +static void __exit coldfire_spi_exit(void)
28671 +{
28672 + platform_driver_unregister(&driver);
28673 +}
28674 +module_exit(coldfire_spi_exit);
28675 --- /dev/null
28676 +++ b/drivers/spi/spi-m5445x.c
28677 @@ -0,0 +1,156 @@
28678 +/***************************************************************************/
28679 +/*
28680 + * linux/arch/m68k/coldfire/spi-m5445x.c
28681 + *
28682 + * Sub-architcture dependant initialization code for the Freescale
28683 + * 5445x SPI module
28684 + *
28685 + * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
28686 + * Copyright Freescale Semiconductor, Inc 2007
28687 + *
28688 + * This program is free software; you can redistribute it and/or modify
28689 + * it under the terms of the GNU General Public License as published by
28690 + * the Free Software Foundation; either version 2 of the License, or
28691 + * (at your option) any later version.
28692 + */
28693 +/***************************************************************************/
28694 +
28695 +
28696 +#include <linux/kernel.h>
28697 +#include <linux/sched.h>
28698 +#include <linux/param.h>
28699 +#include <linux/init.h>
28700 +#include <linux/interrupt.h>
28701 +#include <linux/device.h>
28702 +#include <linux/platform_device.h>
28703 +#include <linux/spi/spi.h>
28704 +
28705 +#include <asm/dma.h>
28706 +#include <asm/traps.h>
28707 +#include <asm/machdep.h>
28708 +#include <asm/coldfire.h>
28709 +#include <asm/mcfsim.h>
28710 +#include <asm/mcfqspi.h>
28711 +#include <asm/mcf5445x_gpio.h>
28712 +
28713 +#define SPI_NUM_CHIPSELECTS 0x10
28714 +#define SPI_PAR_VAL (0 | MCF_GPIO_PAR_DSPI_PCS5_PCS5 | MCF_GPIO_PAR_DSPI_PCS2_PCS2 \
28715 + | MCF_GPIO_PAR_DSPI_PCS1_PCS1 | MCF_GPIO_PAR_DSPI_PCS0_PCS0 | MCF_GPIO_PAR_DSPI_SIN_SIN \
28716 + | MCF_GPIO_PAR_DSPI_SOUT_SOUT | MCF_GPIO_PAR_DSPI_SCK_SCK)
28717 +
28718 +#define MCF5445x_DSPI_IRQ_SOURCE (31)
28719 +#define MCF5445x_DSPI_IRQ_VECTOR (64 + MCF5445x_DSPI_IRQ_SOURCE)
28720 +
28721 +#define MCF5445x_DSPI_PAR (0xFC0A4063)
28722 +#define MCF5445x_DSPI_MCR (0xFC05C000)
28723 +#define MCF5445x_INTC0_ICR (0xFC048040)
28724 +#define MCF5445x_INTC0_IMRL (0xFC04800C)
28725 +
28726 +
28727 +#define M5445x_AUDIO_IRQ_SOURCE 49
28728 +#define M5445x_AUDIO_IRQ_VECTOR (128+M5445x_AUDIO_IRQ_SOURCE)
28729 +#define M5445x_AUDIO_IRQ_LEVEL 4
28730 +
28731 +void coldfire_qspi_cs_control(u8 cs, u8 command)
28732 +{
28733 +}
28734 +
28735 +#if defined(CONFIG_SPI_COLDFIRE_SSI_AUDIO)
28736 +static struct coldfire_spi_chip ssi_audio_chip_info = {
28737 + .mode = SPI_MODE_0,
28738 + .bits_per_word = 16,
28739 + .del_cs_to_clk = 16,
28740 + .del_after_trans = 16,
28741 + .void_write_data = 0
28742 +};
28743 +
28744 +#endif
28745 +
28746 +static struct spi_board_info spi_board_info[] = {
28747 +
28748 +#if defined(CONFIG_SPI_COLDFIRE_SSI_AUDIO)
28749 + {
28750 + .modalias = "ssi_audio",
28751 + .max_speed_hz = 300000,
28752 + .bus_num = 1,
28753 + .chip_select = 5,
28754 + .irq = M5445x_AUDIO_IRQ_VECTOR,
28755 + .platform_data = NULL,
28756 + .controller_data = &ssi_audio_chip_info
28757 + }
28758 +#endif
28759 +
28760 +};
28761 +
28762 +static struct coldfire_spi_master coldfire_master_info = {
28763 + .bus_num = 1,
28764 + .num_chipselect = SPI_NUM_CHIPSELECTS,
28765 + .irq_source = MCF5445x_DSPI_IRQ_SOURCE,
28766 + .irq_vector = MCF5445x_DSPI_IRQ_VECTOR,
28767 + .irq_mask = (0x01 << MCF5445x_DSPI_IRQ_SOURCE),
28768 + .irq_lp = 0x2, /* Level */
28769 + .par_val = SPI_PAR_VAL,
28770 +// .par_val16 = SPI_PAR_VAL,
28771 + .cs_control = coldfire_qspi_cs_control,
28772 +};
28773 +
28774 +static struct resource coldfire_spi_resources[] = {
28775 + [0] = {
28776 + .name = "qspi-par",
28777 + .start = MCF5445x_DSPI_PAR,
28778 + .end = MCF5445x_DSPI_PAR,
28779 + .flags = IORESOURCE_MEM
28780 + },
28781 +
28782 + [1] = {
28783 + .name = "qspi-module",
28784 + .start = MCF5445x_DSPI_MCR,
28785 + .end = MCF5445x_DSPI_MCR + 0xB8,
28786 + .flags = IORESOURCE_MEM
28787 + },
28788 +
28789 + [2] = {
28790 + .name = "qspi-int-level",
28791 + .start = MCF5445x_INTC0_ICR + MCF5445x_DSPI_IRQ_SOURCE,
28792 + .end = MCF5445x_INTC0_ICR + MCF5445x_DSPI_IRQ_SOURCE,
28793 + .flags = IORESOURCE_MEM
28794 + },
28795 +
28796 + [3] = {
28797 + .name = "qspi-int-mask",
28798 + .start = MCF5445x_INTC0_IMRL,
28799 + .end = MCF5445x_INTC0_IMRL,
28800 + .flags = IORESOURCE_MEM
28801 + }
28802 +};
28803 +
28804 +static struct platform_device coldfire_spi = {
28805 + .name = "spi_coldfire", //"coldfire-qspi",
28806 + .id = -1,
28807 + .resource = coldfire_spi_resources,
28808 + .num_resources = ARRAY_SIZE(coldfire_spi_resources),
28809 + .dev = {
28810 + .platform_data = &coldfire_master_info,
28811 + }
28812 +};
28813 +
28814 +static int __init spi_dev_init(void)
28815 +{
28816 + int retval = 0;
28817 +
28818 + retval = platform_device_register(&coldfire_spi);
28819 +
28820 + if (retval < 0) {
28821 + printk(KERN_ERR "SPI-m5445x: platform_device_register failed with code=%d\n", retval);
28822 + goto out;
28823 + }
28824 +
28825 + if (ARRAY_SIZE(spi_board_info))
28826 + retval = spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
28827 +
28828 +
28829 +out:
28830 + return retval;
28831 +}
28832 +
28833 +arch_initcall(spi_dev_init);
28834 --- /dev/null
28835 +++ b/drivers/spi/ssi_audio.c
28836 @@ -0,0 +1,921 @@
28837 +/*
28838 + * MCF5445x audio driver.
28839 + *
28840 + * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
28841 + * Copyright Freescale Semiconductor, Inc. 2006, 2007
28842 + *
28843 + * This program is free software; you can redistribute it and/or modify
28844 + * it under the terms of the GNU General Public License as published by
28845 + * the Free Software Foundation; either version 2 of the License, or
28846 + * (at your option) any later version.
28847 + */
28848 +
28849 +#include <linux/device.h>
28850 +#include <linux/init.h>
28851 +#include <linux/delay.h>
28852 +#include <linux/spi/spi.h>
28853 +#include <linux/fs.h>
28854 +#include <linux/kernel.h>
28855 +#include <linux/major.h>
28856 +#include <asm/mcfsim.h>
28857 +#include <linux/interrupt.h>
28858 +#include <linux/soundcard.h>
28859 +#include <asm/uaccess.h>
28860 +#include <asm/virtconvert.h>
28861 +
28862 +#include <asm/coldfire.h>
28863 +#include <asm/coldfire_edma.h>
28864 +#ifdef CONFIG_M5445X
28865 +#include <asm/mcf5445x_ssi.h>
28866 +#include <asm/mcf5445x_ccm.h>
28867 +#include <asm/mcf5445x_gpio.h>
28868 +#endif
28869 +
28870 +#define SOUND_DEVICE_NAME "sound"
28871 +#define DRIVER_NAME "ssi_audio"
28872 +
28873 +/* #define AUDIO_DEBUG */
28874 +
28875 +#ifdef CONFIG_MMU
28876 +#define USE_MMU
28877 +#endif
28878 +
28879 +#define MAX_SPEED_HZ 12000000
28880 +
28881 +#define M5445x_AUDIO_IRQ_SOURCE 49
28882 +#define M5445x_AUDIO_IRQ_VECTOR (128+M5445x_AUDIO_IRQ_SOURCE)
28883 +#define M5445x_AUDIO_IRQ_LEVEL 5
28884 +
28885 +/* TLV320DAC23 audio chip registers */
28886 +
28887 +#define CODEC_LEFT_IN_REG (0x00)
28888 +#define CODEC_RIGHT_IN_REG (0x01)
28889 +#define CODEC_LEFT_HP_VOL_REG (0x02)
28890 +#define CODEC_RIGHT_HP_VOL_REG (0x03)
28891 +#define CODEC_ANALOG_APATH_REG (0x04)
28892 +#define CODEC_DIGITAL_APATH_REG (0x05)
28893 +#define CODEC_POWER_DOWN_REG (0x06)
28894 +#define CODEC_DIGITAL_IF_FMT_REG (0x07)
28895 +#define CODEC_SAMPLE_RATE_REG (0x08)
28896 +#define CODEC_DIGITAL_IF_ACT_REG (0x09)
28897 +#define CODEC_RESET_REG (0x0f)
28898 +
28899 +#define CODEC_SAMPLE_8KHZ (0x0C)
28900 +#define CODEC_SAMPLE_16KHZ (0x58)
28901 +#define CODEC_SAMPLE_22KHZ (0x62)
28902 +#define CODEC_SAMPLE_32KHZ (0x18)
28903 +#define CODEC_SAMPLE_44KHZ (0x22)
28904 +#define CODEC_SAMPLE_48KHZ (0x00)
28905 +
28906 +/* Audio buffer data size */
28907 +#define BUFSIZE (64*1024)
28908 +/* DMA transfer size */
28909 +#define DMASIZE (16*1024)
28910 +
28911 +/* eDMA channel for SSI channel 0 TX */
28912 +#define DMA_TCD MCF_EDMA_CHAN_TIMER2
28913 +/* eDMA channel for SSI channel 1 TX */
28914 +#define DMA_TCD2 MCF_EDMA_CHAN_TIMER3
28915 +
28916 +struct ssi_audio {
28917 + struct spi_device *spi;
28918 + u32 speed;
28919 + u32 stereo;
28920 + u32 bits;
28921 + u32 format;
28922 + u8 isopen;
28923 + u8 dmaing;
28924 + u8 ssi_enabled;
28925 + u8 channel;
28926 + spinlock_t lock;
28927 + u8* audio_buf;
28928 +};
28929 +
28930 +static struct ssi_audio* audio_device = NULL;
28931 +volatile u32 audio_start;
28932 +volatile u32 audio_count;
28933 +volatile u32 audio_append;
28934 +volatile u32 audio_appstart;
28935 +volatile u32 audio_txbusy;
28936 +
28937 +struct ssi_audio_format {
28938 + unsigned int format;
28939 + unsigned int bits;
28940 +} ssi_audio_formattable[] = {
28941 + { AFMT_MU_LAW, 8 },
28942 + { AFMT_A_LAW, 8 },
28943 + { AFMT_IMA_ADPCM, 8 },
28944 + { AFMT_U8, 8 },
28945 + { AFMT_S16_LE, 16 },
28946 + { AFMT_S16_BE, 16 },
28947 + { AFMT_S8, 8 },
28948 + { AFMT_U16_LE, 16 },
28949 + { AFMT_U16_BE, 16 },
28950 +};
28951 +
28952 +#define FORMATSIZE (sizeof(ssi_audio_formattable) / sizeof(struct ssi_audio_format))
28953 +
28954 +static void ssi_audio_setsamplesize(int val)
28955 +{
28956 + int i;
28957 +
28958 + if (audio_device == NULL) return;
28959 +
28960 + for (i = 0; (i < FORMATSIZE); i++) {
28961 + if (ssi_audio_formattable[i].format == val) {
28962 + audio_device->format = ssi_audio_formattable[i].format;
28963 + audio_device->bits = ssi_audio_formattable[i].bits;
28964 + break;
28965 + }
28966 + }
28967 +
28968 +#ifdef AUDIO_DEBUG
28969 + printk(DRIVER_NAME ":ssi_audio_setsamplesize %d %d\n",
28970 + audio_device->format, audio_device->bits);
28971 +#endif
28972 +}
28973 +
28974 +static void ssi_audio_txdrain(void)
28975 +{
28976 +#ifdef AUDIO_DEBUG
28977 + printk(DRIVER_NAME ":ssi_audio_txdrain()\n");
28978 +#endif
28979 +
28980 + if (audio_device == NULL) return;
28981 +
28982 + while (!signal_pending(current)) {
28983 + if (audio_txbusy == 0)
28984 + break;
28985 + current->state = TASK_INTERRUPTIBLE;
28986 + schedule_timeout(1);
28987 + }
28988 +}
28989 +
28990 +#ifdef CONFIG_SSIAUDIO_USE_EDMA
28991 +/*
28992 + * Configure and start DMA engine.
28993 + */
28994 +void __inline__ ssi_audio_dmarun(void)
28995 +{
28996 + set_edma_params(DMA_TCD,
28997 +#ifdef USE_MMU
28998 + virt_to_phys(&(audio_device->audio_buf[audio_start])),
28999 +#else
29000 + (u32)&(audio_device->audio_buf[audio_start]),
29001 +#endif
29002 + (u32)&MCF_SSI_TX0,
29003 + MCF_EDMA_TCD_ATTR_SSIZE_32BIT | MCF_EDMA_TCD_ATTR_DSIZE_32BIT,
29004 + 8,
29005 + 4,
29006 + 0,
29007 + audio_count/8,
29008 + audio_count/8,
29009 + 0,
29010 + 0,
29011 + 0, // major_int
29012 + 0 // disable_req
29013 + );
29014 +
29015 + set_edma_params(DMA_TCD2,
29016 +#ifdef USE_MMU
29017 + virt_to_phys(&(audio_device->audio_buf[audio_start+4])),
29018 +#else
29019 + (u32)&(audio_device->audio_buf[audio_start+4]),
29020 +#endif
29021 + (u32)&MCF_SSI_TX1,
29022 + MCF_EDMA_TCD_ATTR_SSIZE_32BIT | MCF_EDMA_TCD_ATTR_DSIZE_32BIT,
29023 + 8,
29024 + 4,
29025 + 0,
29026 + audio_count/8,
29027 + audio_count/8,
29028 + 0,
29029 + 0,
29030 + 1, // major_int
29031 + 0 // disable_req
29032 + );
29033 +
29034 + audio_device->dmaing = 1;
29035 + audio_txbusy = 1;
29036 +
29037 + start_edma_transfer(DMA_TCD);
29038 + start_edma_transfer(DMA_TCD2);
29039 +}
29040 +
29041 +/**
29042 + * ssi_audio_dmabuf - Start DMA'ing a new buffer of data if any available.
29043 + */
29044 +static void ssi_audio_dmabuf(void)
29045 +{
29046 +#ifdef AUDIO_DEBUG
29047 + printk(DRIVER_NAME ":ssi_audio_dmabuf(): append=%x start=%x\n",
29048 + audio_append, audio_appstart);
29049 +#endif
29050 +
29051 + /* If already running then nothing to do... */
29052 + if (audio_device->dmaing)
29053 + return;
29054 +
29055 + /* Set DMA buffer size */
29056 + audio_count = (audio_append >= audio_appstart) ?
29057 + (audio_append - audio_appstart) :
29058 + (BUFSIZE - audio_appstart);
29059 + if (audio_count > DMASIZE)
29060 + audio_count = DMASIZE;
29061 +
29062 + /* Adjust pointers and counters accordingly */
29063 + audio_appstart += audio_count;
29064 + if (audio_appstart >= BUFSIZE)
29065 + audio_appstart = 0;
29066 +
29067 + if (audio_count > 0)
29068 + ssi_audio_dmarun();
29069 + else {
29070 + audio_txbusy = 0;
29071 +#ifdef AUDIO_DEBUG
29072 + printk(DRIVER_NAME ":DMA buffer is empty!\n");
29073 +#endif
29074 + }
29075 +}
29076 +
29077 +void __inline__ stop_dma(void)
29078 +{
29079 + stop_edma_transfer(DMA_TCD);
29080 + stop_edma_transfer(DMA_TCD2);
29081 +}
29082 +
29083 +static int ssi_audio_dma_handler_empty(int channel, void *dev_id)
29084 +{
29085 + return IRQ_HANDLED;
29086 +}
29087 +
29088 +static int ssi_audio_dma_handler(int channel, void *dev_id)
29089 +{
29090 +#ifdef AUDIO_DEBUG
29091 + printk(DRIVER_NAME ":ssi_audio_dma_handler(channel=%d)\n", channel);
29092 +#endif
29093 +
29094 + /* Clear DMA interrupt */
29095 + stop_dma();
29096 +
29097 + audio_device->dmaing = 0;
29098 +
29099 + /* Update data pointers and counts */
29100 + audio_start += audio_count;
29101 + if (audio_start >= BUFSIZE)
29102 + audio_start = 0;
29103 + audio_count = 0;
29104 +
29105 + /* Start new DMA buffer if we can */
29106 + ssi_audio_dmabuf();
29107 +
29108 + return IRQ_HANDLED;
29109 +}
29110 +
29111 +static void init_dma(void)
29112 +{
29113 + /* SSI DMA Signals mapped to DMA request */
29114 + MCF_CCM_MISCCR &= ~MCF_CCM_MISCCR_TIMDMA;
29115 + init_edma();
29116 +}
29117 +
29118 +#endif /* CONFIG_SSIAUDIO_USE_EDMA */
29119 +
29120 +/* Write CODEC register using SPI
29121 + * address - CODEC register address
29122 + * data - data to be written into register
29123 + */
29124 +static int codec_write(u8 addr, u16 data)
29125 +{
29126 + u16 spi_word;
29127 +
29128 + if (audio_device==NULL || audio_device->spi==NULL)
29129 + return -ENODEV;
29130 +
29131 + spi_word = ((addr & 0x7F)<<9)|(data & 0x1FF);
29132 + return spi_write(audio_device->spi, (const u8*)&spi_word,
29133 + sizeof(spi_word));
29134 +}
29135 +
29136 +static inline void enable_ssi(void)
29137 +{
29138 + if (audio_device==NULL || audio_device->ssi_enabled) return;
29139 + audio_device->ssi_enabled = 1;
29140 + MCF_SSI_CR |= MCF_SSI_CR_SSI_EN; /* enable SSI module */
29141 + MCF_SSI_CR |= MCF_SSI_CR_TE; /* enable tranmitter */
29142 +}
29143 +
29144 +static inline void disable_ssi(void)
29145 +{
29146 + if (audio_device==NULL || audio_device->ssi_enabled==0) return;
29147 + MCF_SSI_CR &= ~MCF_SSI_CR_TE; /* disable transmitter */
29148 + MCF_SSI_CR &= ~MCF_SSI_CR_SSI_EN; /* disable SSI module */
29149 + audio_device->ssi_enabled = 0;
29150 +}
29151 +
29152 +/* Audio CODEC initialization */
29153 +static void adjust_codec_speed(void) {
29154 +#ifdef AUDIO_DEBUG
29155 + printk(DRIVER_NAME ":adjust_codec_speed: %d\n", audio_device->speed);
29156 +#endif
29157 + disable_ssi();
29158 + switch (audio_device->speed) {
29159 + case 8000:
29160 + MCF_CCM_CDR = MCF_CCM_CDR_SSIDIV(255);
29161 + codec_write(CODEC_SAMPLE_RATE_REG,CODEC_SAMPLE_8KHZ);
29162 + break;
29163 + case 16000:
29164 + MCF_CCM_CDR = MCF_CCM_CDR_SSIDIV(129);
29165 + codec_write(CODEC_SAMPLE_RATE_REG,CODEC_SAMPLE_16KHZ);
29166 + break;
29167 + case 22000:
29168 + case 22050:
29169 + MCF_CCM_CDR = MCF_CCM_CDR_SSIDIV(94);
29170 + codec_write(CODEC_SAMPLE_RATE_REG,CODEC_SAMPLE_22KHZ);
29171 + break;
29172 + case 44000:
29173 + case 44100:
29174 + MCF_CCM_CDR = MCF_CCM_CDR_SSIDIV(47);
29175 + codec_write(CODEC_SAMPLE_RATE_REG,CODEC_SAMPLE_44KHZ);
29176 + break;
29177 + case 48000:
29178 + MCF_CCM_CDR = MCF_CCM_CDR_SSIDIV(42);
29179 + codec_write(CODEC_SAMPLE_RATE_REG,CODEC_SAMPLE_48KHZ);
29180 + break;
29181 + default:
29182 + MCF_CCM_CDR = MCF_CCM_CDR_SSIDIV(47);
29183 + codec_write(CODEC_SAMPLE_RATE_REG,CODEC_SAMPLE_44KHZ);
29184 + }
29185 +}
29186 +
29187 +static void codec_reset(void)
29188 +{
29189 + codec_write(CODEC_RESET_REG, 0); /* reset the audio chip */
29190 + udelay(1500); /* wait for reset */
29191 +}
29192 +
29193 +static void init_audio_codec(void)
29194 +{
29195 +#ifdef AUDIO_DEBUG
29196 + printk(DRIVER_NAME ":init_audio_codec()\n");
29197 +#endif
29198 + codec_reset();
29199 +
29200 + codec_write(CODEC_LEFT_IN_REG, 0x017);
29201 + codec_write(CODEC_RIGHT_IN_REG, 0x017);
29202 + codec_write(CODEC_POWER_DOWN_REG, 0x000); /* Turn off line input */
29203 + codec_write(CODEC_DIGITAL_IF_FMT_REG, 0x00A); /* I2S slave mode */
29204 + /* codec_write(CODEC_DIGITAL_IF_FMT_REG, 0x042); // I2S master mode */
29205 + codec_write(CODEC_DIGITAL_APATH_REG, 0x007); /* Set A path */
29206 +
29207 + /* set sample rate */
29208 + adjust_codec_speed();
29209 +
29210 + codec_write(CODEC_LEFT_HP_VOL_REG, 0x075); /* set volume */
29211 + codec_write(CODEC_RIGHT_HP_VOL_REG, 0x075); /* set volume */
29212 + codec_write(CODEC_DIGITAL_IF_ACT_REG, 1); /* Activate digital interface */
29213 + codec_write(CODEC_ANALOG_APATH_REG, 0x0F2);
29214 +}
29215 +
29216 +
29217 +static void chip_init(void)
29218 +{
29219 +#ifdef CONFIG_SSIAUDIO_USE_EDMA
29220 + init_dma();
29221 +#endif
29222 +
29223 + /* Enable the SSI pins */
29224 + MCF_GPIO_PAR_SSI = (0
29225 + | MCF_GPIO_PAR_SSI_MCLK
29226 + | MCF_GPIO_PAR_SSI_STXD(3)
29227 + | MCF_GPIO_PAR_SSI_SRXD(3)
29228 + | MCF_GPIO_PAR_SSI_FS(3)
29229 + | MCF_GPIO_PAR_SSI_BCLK(3) );
29230 +}
29231 +
29232 +static void init_ssi(void)
29233 +{
29234 +#ifdef AUDIO_DEBUG
29235 + printk(DRIVER_NAME ":init_ssi()\n");
29236 +#endif
29237 +
29238 + /* Dividers are for MCF54445 on 266Mhz, the output is 44.1Khz*/
29239 + /* Enable SSI clock in CCM */
29240 + MCF_CCM_CDR = MCF_CCM_CDR_SSIDIV(47);
29241 +
29242 + /* Issue a SSI reset */
29243 + MCF_SSI_CR &= ~MCF_SSI_CR_SSI_EN; /* disable SSI module */
29244 +
29245 + /* SSI module uses internal CPU clock */
29246 + MCF_CCM_MISCCR |= MCF_CCM_MISCCR_SSISRC;
29247 +
29248 + MCF_CCM_MISCCR |= MCF_CCM_MISCCR_SSIPUE;
29249 + MCF_CCM_MISCCR |= MCF_CCM_MISCCR_SSIPUS_UP;
29250 +
29251 + MCF_SSI_CR = 0
29252 + | MCF_SSI_CR_CIS
29253 + | MCF_SSI_CR_TCH /* Enable two channel mode */
29254 + | MCF_SSI_CR_MCE /* Set clock out on SSI_MCLK pin */
29255 + | MCF_SSI_CR_I2S_MASTER /* Set I2S master mode */
29256 + | MCF_SSI_CR_SYN /* Enable synchronous mode */
29257 + | MCF_SSI_CR_NET
29258 + ;
29259 +
29260 + MCF_SSI_TCR = 0
29261 + | MCF_SSI_TCR_TXDIR /* internally generated bit clock */
29262 + | MCF_SSI_TCR_TFDIR /* internally generated frame sync */
29263 + | MCF_SSI_TCR_TSCKP /* Clock data on falling edge of bit clock */
29264 + | MCF_SSI_TCR_TFSI /* Frame sync active low */
29265 + | MCF_SSI_TCR_TEFS /* TX frame sync 1 bit before data */
29266 + | MCF_SSI_TCR_TFEN0 /* TX FIFO 0 enabled */
29267 + | MCF_SSI_TCR_TFEN1 /* TX FIFO 1 enabled */
29268 + | MCF_SSI_TCR_TXBIT0
29269 + ;
29270 +
29271 + MCF_SSI_CCR = MCF_SSI_CCR_WL(7) /* 16 bit word length */
29272 + | MCF_SSI_CCR_DC(1) /* Frame rate divider */
29273 + | MCF_SSI_CCR_PM(0)
29274 + | MCF_SSI_CCR_DIV2
29275 + ;
29276 +
29277 + MCF_SSI_FCSR = 0
29278 + | MCF_SSI_FCSR_TFWM0(2)
29279 + | MCF_SSI_FCSR_TFWM1(2)
29280 + ;
29281 +
29282 + MCF_SSI_IER = 0 // interrupts
29283 +#ifndef CONFIG_SSIAUDIO_USE_EDMA
29284 + | MCF_SSI_IER_TIE /* transmit interrupts */
29285 + | MCF_SSI_IER_TFE0 /* transmit FIFO 0 empty */
29286 + | MCF_SSI_IER_TFE1 /* transmit FIFO 1 empty */
29287 +#else
29288 + | MCF_SSI_IER_TDMAE /* DMA request enabled */
29289 + | MCF_SSI_IER_TFE0 /* transmit FIFO 0 empty */
29290 + | MCF_SSI_IER_TFE1 /* transmit FIFO 1 empty */
29291 +#endif
29292 + ;
29293 +
29294 +#ifndef CONFIG_SSIAUDIO_USE_EDMA
29295 + /* enable IRQ: SSI interrupt */
29296 + MCF_INTC1_ICR(M5445x_AUDIO_IRQ_SOURCE) = M5445x_AUDIO_IRQ_LEVEL;
29297 + MCF_INTC1_CIMR = M5445x_AUDIO_IRQ_SOURCE;
29298 +#endif
29299 +}
29300 +
29301 +#ifndef CONFIG_SSIAUDIO_USE_EDMA
29302 +/* interrupt for SSI */
29303 +static int ssi_audio_isr(int irq, void *dev_id)
29304 +{
29305 + unsigned long *bp;
29306 +
29307 + if (audio_txbusy==0)
29308 + return IRQ_HANDLED;
29309 +
29310 + spin_lock(&(audio_device->lock));
29311 +
29312 + if (audio_start == audio_append) {
29313 + disable_ssi();
29314 + audio_txbusy = 0;
29315 + } else {
29316 + if (MCF_SSI_ISR & (MCF_SSI_ISR_TFE0|MCF_SSI_ISR_TFE1)) {
29317 + bp = (unsigned long *) &audio_device->audio_buf[audio_start];
29318 + if (audio_device->channel) {
29319 + MCF_SSI_TX1 = *bp;
29320 + audio_device->channel = 0;
29321 + } else {
29322 + MCF_SSI_TX0 = *bp;
29323 + audio_device->channel = 1;
29324 + }
29325 + audio_start += 4;
29326 + if (audio_start >= BUFSIZE)
29327 + audio_start = 0;
29328 + }
29329 + }
29330 +
29331 + spin_unlock(&(audio_device->lock));
29332 +
29333 + return IRQ_HANDLED;
29334 +}
29335 +#endif
29336 +
29337 +/* Set initial driver playback defaults. */
29338 +static void init_driver_variables(void)
29339 +{
29340 + audio_device->speed = 44100;
29341 + audio_device->format = AFMT_S16_LE;
29342 + audio_device->bits = 16;
29343 + audio_device->stereo = 1;
29344 + audio_device->ssi_enabled = 0;
29345 +
29346 + audio_start = 0;
29347 + audio_count = 0;
29348 + audio_append = 0;
29349 + audio_appstart = 0;
29350 + audio_txbusy = 0;
29351 + audio_device->dmaing = 0;
29352 +}
29353 +
29354 +/* open audio device */
29355 +static int ssi_audio_open(struct inode *inode, struct file *filp)
29356 +{
29357 +#ifdef AUDIO_DEBUG
29358 + printk(DRIVER_NAME ":ssi_audio_open()\n");
29359 +#endif
29360 +
29361 + if (audio_device==NULL) return (-ENODEV);
29362 +
29363 + if (audio_device->isopen)
29364 + return(-EBUSY);
29365 +
29366 + spin_lock(&(audio_device->lock));
29367 +
29368 + audio_device->isopen = 1;
29369 +
29370 + init_driver_variables();
29371 + init_ssi();
29372 + init_audio_codec();
29373 +
29374 + spin_unlock(&(audio_device->lock));
29375 +
29376 + udelay(100);
29377 +
29378 + return 0;
29379 +}
29380 +
29381 +/* close audio device */
29382 +static int ssi_audio_close(struct inode *inode, struct file *filp)
29383 +{
29384 +#ifdef AUDIO_DEBUG
29385 + printk(DRIVER_NAME ":ssi_audio_close()\n");
29386 +#endif
29387 +
29388 + if (audio_device==NULL) return (-ENODEV);
29389 +
29390 + ssi_audio_txdrain();
29391 +
29392 + spin_lock(&(audio_device->lock));
29393 +
29394 +#ifdef CONFIG_SSIAUDIO_USE_EDMA
29395 + stop_dma();
29396 +#endif
29397 + disable_ssi();
29398 + codec_reset();
29399 + init_driver_variables();
29400 + audio_device->isopen = 0;
29401 +
29402 + spin_unlock(&(audio_device->lock));
29403 + return 0;
29404 +}
29405 +
29406 +/* write to audio device */
29407 +static ssize_t ssi_audio_write(struct file *filp, const char *buf,
29408 + size_t count, loff_t *ppos)
29409 +{
29410 + unsigned long *dp, *buflp;
29411 + unsigned short *bufwp;
29412 + unsigned char *bufbp;
29413 + unsigned int slen, bufcnt, i, s, e;
29414 +
29415 +#ifdef AUDIO_DEBUG
29416 + printk(DRIVER_NAME ":ssi_audio_write(buf=%x,count=%d)\n",
29417 + (int)buf, count);
29418 +#endif
29419 +
29420 + if (audio_device==NULL)
29421 + return (-ENODEV);
29422 +
29423 + if (count <= 0)
29424 + return 0;
29425 +
29426 + spin_lock(&(audio_device->lock));
29427 +
29428 + buflp = (unsigned long *) buf;
29429 + bufwp = (unsigned short *) buf;
29430 + bufbp = (unsigned char *) buf;
29431 +
29432 + bufcnt = count & ~0x3;
29433 +
29434 + bufcnt <<= 1;
29435 + if (audio_device->stereo == 0)
29436 + bufcnt <<= 1;
29437 + if (audio_device->bits == 8)
29438 + bufcnt <<= 1;
29439 +
29440 +tryagain:
29441 + /*
29442 + * Get a snapshot of buffer, so we can figure out how
29443 + * much data we can fit in...
29444 + */
29445 + s = audio_start;
29446 + e = audio_append;
29447 + dp = (unsigned long *) &(audio_device->audio_buf[e]);
29448 +
29449 + slen = ((s > e) ? (s - e) : (BUFSIZE - (e - s))) - 4;
29450 + if (slen > bufcnt)
29451 + slen = bufcnt;
29452 + if ((BUFSIZE - e) < slen)
29453 + slen = BUFSIZE - e;
29454 +
29455 + if (slen == 0) {
29456 + if (signal_pending(current))
29457 + return(-ERESTARTSYS);
29458 + set_current_state(TASK_INTERRUPTIBLE);
29459 + schedule_timeout(1);
29460 + goto tryagain;
29461 + }
29462 +
29463 + /*
29464 + * For DMA we need to have data as 32 bit
29465 + * values (since SSI TX register is 32 bit).
29466 + * So, the incoming 16 bit data must be put to buffer as 32 bit values.
29467 + * Also, the endianess is converted if needed
29468 + */
29469 + if (audio_device->stereo) {
29470 + if (audio_device->bits == 16) {
29471 + if (audio_device->format==AFMT_S16_LE) {
29472 + /*- convert endianess, probably could be done by SSI also */
29473 + for (i = 0; (i < slen); i += 4) {
29474 + unsigned short val = le16_to_cpu((*bufwp++));
29475 + *dp++ = val;
29476 + }
29477 + } else {
29478 + for (i = 0; (i < slen); i += 4) {
29479 + *dp++ = *bufwp++;
29480 + }
29481 + }
29482 + } else {
29483 + for (i = 0; (i < slen); i += 4) {
29484 + *dp = (((unsigned long) *bufbp++) << 24);
29485 + *dp++ |= (((unsigned long) *bufbp++) << 8);
29486 + }
29487 + }
29488 + } else {
29489 + if (audio_device->bits == 16) {
29490 + for (i = 0; (i < slen); i += 4) {
29491 + *dp++ = (((unsigned long)*bufwp)<<16) | *bufwp;
29492 + bufwp++;
29493 + }
29494 + } else {
29495 + for (i = 0; (i < slen); i += 4) {
29496 + *dp++ = (((unsigned long) *bufbp) << 24) |
29497 + (((unsigned long) *bufbp) << 8);
29498 + bufbp++;
29499 + }
29500 + }
29501 + }
29502 +
29503 + e += slen;
29504 + if (e >= BUFSIZE)
29505 + e = 0;
29506 + audio_append = e;
29507 +
29508 + /* If not outputing audio, then start now */
29509 + if (audio_txbusy == 0) {
29510 + audio_txbusy++;
29511 + audio_device->channel = 0;
29512 + enable_ssi();
29513 +#ifdef CONFIG_SSIAUDIO_USE_EDMA
29514 + ssi_audio_dmabuf(); /* start first DMA transfer */
29515 +#endif
29516 + }
29517 +
29518 + bufcnt -= slen;
29519 +
29520 + if (bufcnt > 0)
29521 + goto tryagain;
29522 +
29523 + spin_unlock(&(audio_device->lock));
29524 +
29525 + return count;
29526 +}
29527 +
29528 +/* ioctl: control the driver */
29529 +static int ssi_audio_ioctl(struct inode *inode, struct file *filp,
29530 + unsigned int cmd, unsigned long arg)
29531 +{
29532 + long val;
29533 + int rc = 0;
29534 +
29535 +#ifdef AUDIO_DEBUG
29536 + printk(DRIVER_NAME ":ssi_audio_ioctl(cmd=%x,arg=%x)\n",
29537 + (int)cmd, (int)arg);
29538 +#endif
29539 +
29540 + if (audio_device==NULL)
29541 + return (-ENODEV);
29542 +
29543 + switch (cmd) {
29544 +
29545 + case SNDCTL_DSP_SPEED:
29546 + if (access_ok(VERIFY_READ, (void *) arg, sizeof(val))) {
29547 + get_user(val, (unsigned long *) arg);
29548 +#ifdef AUDIO_DEBUG
29549 + printk(DRIVER_NAME ":ssi_audio_ioctl: SNDCTL_DSP_SPEED: %ld\n", val);
29550 +#endif
29551 + ssi_audio_txdrain();
29552 + audio_device->speed = val;
29553 + init_audio_codec();
29554 + } else {
29555 + rc = -EINVAL;
29556 + }
29557 + break;
29558 +
29559 + case SNDCTL_DSP_SAMPLESIZE:
29560 + if (access_ok(VERIFY_READ, (void *) arg, sizeof(val))) {
29561 + get_user(val, (unsigned long *) arg);
29562 +#ifdef AUDIO_DEBUG
29563 + printk(DRIVER_NAME ":ssi_audio_ioctl: SNDCTL_DSP_SAMPLESIZE: %d\n", val);
29564 +#endif
29565 + ssi_audio_txdrain();
29566 + ssi_audio_setsamplesize(val);
29567 + } else {
29568 + rc = -EINVAL;
29569 + }
29570 + break;
29571 +
29572 + case SNDCTL_DSP_STEREO:
29573 + if (access_ok(VERIFY_READ, (void *) arg, sizeof(val))) {
29574 + get_user(val, (unsigned long *) arg);
29575 + ssi_audio_txdrain();
29576 + audio_device->stereo = val;
29577 + } else {
29578 + rc = -EINVAL;
29579 + }
29580 + break;
29581 +
29582 + case SNDCTL_DSP_GETBLKSIZE:
29583 + if (access_ok(VERIFY_WRITE, (void *) arg, sizeof(long)))
29584 + put_user(BUFSIZE, (long *) arg);
29585 + else
29586 + rc = -EINVAL;
29587 + break;
29588 +
29589 + case SNDCTL_DSP_SYNC:
29590 + ssi_audio_txdrain();
29591 + break;
29592 +
29593 + default:
29594 + rc = -EINVAL;
29595 + break;
29596 + }
29597 +
29598 + return rc;
29599 +}
29600 +
29601 +struct file_operations ssi_audio_fops = {
29602 + open: ssi_audio_open, /* open */
29603 + release: ssi_audio_close, /* close */
29604 + write: ssi_audio_write, /* write */
29605 + ioctl: ssi_audio_ioctl, /* ioctl */
29606 +};
29607 +
29608 +/* initialize audio driver */
29609 +static int __devinit ssi_audio_probe(struct spi_device *spi)
29610 +{
29611 + struct ssi_audio *audio;
29612 + int err;
29613 +
29614 +#ifdef AUDIO_DEBUG
29615 + printk(DRIVER_NAME": probe\n");
29616 +#endif
29617 +
29618 + if (!spi->irq) {
29619 + dev_dbg(&spi->dev, "no IRQ?\n");
29620 + return -ENODEV;
29621 + }
29622 +
29623 + /* don't exceed max specified sample rate */
29624 + if (spi->max_speed_hz > MAX_SPEED_HZ) {
29625 + dev_dbg(&spi->dev, "f(sample) %d KHz?\n",
29626 + (spi->max_speed_hz)/1000);
29627 + return -EINVAL;
29628 + }
29629 +
29630 + /* register charcter device */
29631 + if (register_chrdev(SOUND_MAJOR, SOUND_DEVICE_NAME, &ssi_audio_fops) < 0) {
29632 + printk(KERN_WARNING DRIVER_NAME ": failed to register major %d\n", SOUND_MAJOR);
29633 + dev_dbg(&spi->dev, DRIVER_NAME ": failed to register major %d\n", SOUND_MAJOR);
29634 + return -ENODEV;
29635 + }
29636 +
29637 + audio = kzalloc(sizeof(struct ssi_audio), GFP_KERNEL);
29638 + if (!audio) {
29639 + err = -ENOMEM;
29640 + goto err_out;
29641 + }
29642 +
29643 + /* DMA buffer must be from GFP_DMA zone, so it will not be cached */
29644 + audio->audio_buf = kmalloc(BUFSIZE, GFP_DMA);
29645 + if (audio->audio_buf == NULL) {
29646 + dev_dbg(&spi->dev, DRIVER_NAME ": failed to allocate DMA[%d] buffer\n", BUFSIZE);
29647 + err = -ENOMEM;
29648 + goto err_free_mem;
29649 + }
29650 +
29651 + audio_device = audio;
29652 +
29653 + dev_set_drvdata(&spi->dev, audio);
29654 + spi->dev.power.power_state = PMSG_ON;
29655 +
29656 + audio->spi = spi;
29657 +
29658 +#ifndef CONFIG_SSIAUDIO_USE_EDMA
29659 + if (request_irq(spi->irq, ssi_audio_isr, IRQF_DISABLED, spi->dev.bus_id, audio)) {
29660 + dev_dbg(&spi->dev, "irq %d busy?\n", spi->irq);
29661 + err = -EBUSY;
29662 + goto err_free_mem;
29663 + }
29664 +
29665 +#else
29666 + /* request 2 eDMA channels since two channel output mode is used */
29667 + if (request_edma_channel(DMA_TCD,
29668 + ssi_audio_dma_handler_empty,
29669 + NULL,
29670 + audio,
29671 + &(audio_device->lock),
29672 + DRIVER_NAME)!=0) {
29673 + dev_dbg(&spi->dev, "DMA channel %d busy?\n", DMA_TCD);
29674 + err = -EBUSY;
29675 + goto err_free_mem;
29676 + }
29677 + if (request_edma_channel(DMA_TCD2,
29678 + ssi_audio_dma_handler,
29679 + NULL,
29680 + audio,
29681 + &(audio_device->lock),
29682 + DRIVER_NAME)!=0) {
29683 + dev_dbg(&spi->dev, "DMA channel %d busy?\n", DMA_TCD2);
29684 + err = -EBUSY;
29685 + goto err_free_mem;
29686 + }
29687 +
29688 +#endif
29689 + chip_init();
29690 + printk(DRIVER_NAME ": Probed successfully\n");
29691 +
29692 + return 0;
29693 +
29694 + err_free_mem:
29695 + kfree(audio);
29696 + audio_device = NULL;
29697 + err_out:
29698 + unregister_chrdev(SOUND_MAJOR, SOUND_DEVICE_NAME);
29699 + return err;
29700 +}
29701 +
29702 +static int __devexit ssi_audio_remove(struct spi_device *spi)
29703 +{
29704 + struct ssi_audio *audio = dev_get_drvdata(&spi->dev);
29705 +
29706 + ssi_audio_txdrain();
29707 +#ifndef CONFIG_SSIAUDIO_USE_EDMA
29708 + free_irq(spi->irq, audio);
29709 +#else
29710 + free_edma_channel(DMA_TCD, audio);
29711 + free_edma_channel(DMA_TCD2, audio);
29712 +#endif
29713 + kfree(audio->audio_buf);
29714 + kfree(audio);
29715 + audio_device = NULL;
29716 + unregister_chrdev(SOUND_MAJOR, SOUND_DEVICE_NAME);
29717 + dev_dbg(&spi->dev, "unregistered audio\n");
29718 + return 0;
29719 +}
29720 +
29721 +static int ssi_audio_suspend(struct spi_device *spi, pm_message_t message)
29722 +{
29723 + return 0;
29724 +}
29725 +
29726 +static int ssi_audio_resume(struct spi_device *spi)
29727 +{
29728 + return 0;
29729 +}
29730 +
29731 +static struct spi_driver ssi_audio_driver = {
29732 + .driver = {
29733 + .name = DRIVER_NAME,
29734 + .bus = &spi_bus_type,
29735 + .owner = THIS_MODULE,
29736 + },
29737 + .probe = ssi_audio_probe,
29738 + .remove = __devexit_p(ssi_audio_remove),
29739 + .suspend = ssi_audio_suspend,
29740 + .resume = ssi_audio_resume,
29741 +};
29742 +
29743 +static int __init ssi_audio_init(void)
29744 +{
29745 + return spi_register_driver(&ssi_audio_driver);
29746 +}
29747 +module_init(ssi_audio_init);
29748 +
29749 +static void __exit ssi_audio_exit(void)
29750 +{
29751 + spi_unregister_driver(&ssi_audio_driver);
29752 +}
29753 +module_exit(ssi_audio_exit);
29754 +
29755 +MODULE_LICENSE("GPL");
29756 +MODULE_AUTHOR("Freescale Semiconductor, Inc.");
29757 +MODULE_DESCRIPTION("SSI/I2S Audio Driver");
29758 --- a/drivers/usb/gadget/ether.c
29759 +++ b/drivers/usb/gadget/ether.c
29760 @@ -287,6 +287,9 @@ MODULE_PARM_DESC(host_addr, "Host Ethern
29761 #define DEV_CONFIG_CDC
29762 #endif
29763
29764 +#ifdef CONFIG_USB_GADGET_MCF5445X
29765 +#define DEV_CONFIG_CDC
29766 +#endif
29767
29768 /*-------------------------------------------------------------------------*/
29769
29770 --- a/drivers/usb/gadget/fsl_usb2_udc.h
29771 +++ b/drivers/usb/gadget/fsl_usb2_udc.h
29772 @@ -83,16 +83,6 @@ struct usb_dr_host {
29773 u32 endptctrl[6]; /* Endpoint Control Registers */
29774 };
29775
29776 - /* non-EHCI USB system interface registers (Big Endian) */
29777 -struct usb_sys_interface {
29778 - u32 snoop1;
29779 - u32 snoop2;
29780 - u32 age_cnt_thresh; /* Age Count Threshold Register */
29781 - u32 pri_ctrl; /* Priority Control Register */
29782 - u32 si_ctrl; /* System Interface Control Register */
29783 - u8 res[236];
29784 - u32 control; /* General Purpose Control Register */
29785 -};
29786
29787 /* ep0 transfer state */
29788 #define WAIT_FOR_SETUP 0
29789 @@ -101,10 +91,6 @@ struct usb_sys_interface {
29790 #define WAIT_FOR_OUT_STATUS 3
29791 #define DATA_STATE_RECV 4
29792
29793 -/* Device Controller Capability Parameter register */
29794 -#define DCCPARAMS_DC 0x00000080
29795 -#define DCCPARAMS_DEN_MASK 0x0000001f
29796 -
29797 /* Frame Index Register Bit Masks */
29798 #define USB_FRINDEX_MASKS 0x3fff
29799 /* USB CMD Register Bit Masks */
29800 @@ -180,172 +166,6 @@ struct usb_sys_interface {
29801 /* endpoint list address bit masks */
29802 #define USB_EP_LIST_ADDRESS_MASK 0xfffff800
29803
29804 -/* PORTSCX Register Bit Masks */
29805 -#define PORTSCX_CURRENT_CONNECT_STATUS 0x00000001
29806 -#define PORTSCX_CONNECT_STATUS_CHANGE 0x00000002
29807 -#define PORTSCX_PORT_ENABLE 0x00000004
29808 -#define PORTSCX_PORT_EN_DIS_CHANGE 0x00000008
29809 -#define PORTSCX_OVER_CURRENT_ACT 0x00000010
29810 -#define PORTSCX_OVER_CURRENT_CHG 0x00000020
29811 -#define PORTSCX_PORT_FORCE_RESUME 0x00000040
29812 -#define PORTSCX_PORT_SUSPEND 0x00000080
29813 -#define PORTSCX_PORT_RESET 0x00000100
29814 -#define PORTSCX_LINE_STATUS_BITS 0x00000C00
29815 -#define PORTSCX_PORT_POWER 0x00001000
29816 -#define PORTSCX_PORT_INDICTOR_CTRL 0x0000C000
29817 -#define PORTSCX_PORT_TEST_CTRL 0x000F0000
29818 -#define PORTSCX_WAKE_ON_CONNECT_EN 0x00100000
29819 -#define PORTSCX_WAKE_ON_CONNECT_DIS 0x00200000
29820 -#define PORTSCX_WAKE_ON_OVER_CURRENT 0x00400000
29821 -#define PORTSCX_PHY_LOW_POWER_SPD 0x00800000
29822 -#define PORTSCX_PORT_FORCE_FULL_SPEED 0x01000000
29823 -#define PORTSCX_PORT_SPEED_MASK 0x0C000000
29824 -#define PORTSCX_PORT_WIDTH 0x10000000
29825 -#define PORTSCX_PHY_TYPE_SEL 0xC0000000
29826 -
29827 -/* bit 11-10 are line status */
29828 -#define PORTSCX_LINE_STATUS_SE0 0x00000000
29829 -#define PORTSCX_LINE_STATUS_JSTATE 0x00000400
29830 -#define PORTSCX_LINE_STATUS_KSTATE 0x00000800
29831 -#define PORTSCX_LINE_STATUS_UNDEF 0x00000C00
29832 -#define PORTSCX_LINE_STATUS_BIT_POS 10
29833 -
29834 -/* bit 15-14 are port indicator control */
29835 -#define PORTSCX_PIC_OFF 0x00000000
29836 -#define PORTSCX_PIC_AMBER 0x00004000
29837 -#define PORTSCX_PIC_GREEN 0x00008000
29838 -#define PORTSCX_PIC_UNDEF 0x0000C000
29839 -#define PORTSCX_PIC_BIT_POS 14
29840 -
29841 -/* bit 19-16 are port test control */
29842 -#define PORTSCX_PTC_DISABLE 0x00000000
29843 -#define PORTSCX_PTC_JSTATE 0x00010000
29844 -#define PORTSCX_PTC_KSTATE 0x00020000
29845 -#define PORTSCX_PTC_SEQNAK 0x00030000
29846 -#define PORTSCX_PTC_PACKET 0x00040000
29847 -#define PORTSCX_PTC_FORCE_EN 0x00050000
29848 -#define PORTSCX_PTC_BIT_POS 16
29849 -
29850 -/* bit 27-26 are port speed */
29851 -#define PORTSCX_PORT_SPEED_FULL 0x00000000
29852 -#define PORTSCX_PORT_SPEED_LOW 0x04000000
29853 -#define PORTSCX_PORT_SPEED_HIGH 0x08000000
29854 -#define PORTSCX_PORT_SPEED_UNDEF 0x0C000000
29855 -#define PORTSCX_SPEED_BIT_POS 26
29856 -
29857 -/* bit 28 is parallel transceiver width for UTMI interface */
29858 -#define PORTSCX_PTW 0x10000000
29859 -#define PORTSCX_PTW_8BIT 0x00000000
29860 -#define PORTSCX_PTW_16BIT 0x10000000
29861 -
29862 -/* bit 31-30 are port transceiver select */
29863 -#define PORTSCX_PTS_UTMI 0x00000000
29864 -#define PORTSCX_PTS_ULPI 0x80000000
29865 -#define PORTSCX_PTS_FSLS 0xC0000000
29866 -#define PORTSCX_PTS_BIT_POS 30
29867 -
29868 -/* otgsc Register Bit Masks */
29869 -#define OTGSC_CTRL_VUSB_DISCHARGE 0x00000001
29870 -#define OTGSC_CTRL_VUSB_CHARGE 0x00000002
29871 -#define OTGSC_CTRL_OTG_TERM 0x00000008
29872 -#define OTGSC_CTRL_DATA_PULSING 0x00000010
29873 -#define OTGSC_STS_USB_ID 0x00000100
29874 -#define OTGSC_STS_A_VBUS_VALID 0x00000200
29875 -#define OTGSC_STS_A_SESSION_VALID 0x00000400
29876 -#define OTGSC_STS_B_SESSION_VALID 0x00000800
29877 -#define OTGSC_STS_B_SESSION_END 0x00001000
29878 -#define OTGSC_STS_1MS_TOGGLE 0x00002000
29879 -#define OTGSC_STS_DATA_PULSING 0x00004000
29880 -#define OTGSC_INTSTS_USB_ID 0x00010000
29881 -#define OTGSC_INTSTS_A_VBUS_VALID 0x00020000
29882 -#define OTGSC_INTSTS_A_SESSION_VALID 0x00040000
29883 -#define OTGSC_INTSTS_B_SESSION_VALID 0x00080000
29884 -#define OTGSC_INTSTS_B_SESSION_END 0x00100000
29885 -#define OTGSC_INTSTS_1MS 0x00200000
29886 -#define OTGSC_INTSTS_DATA_PULSING 0x00400000
29887 -#define OTGSC_INTR_USB_ID 0x01000000
29888 -#define OTGSC_INTR_A_VBUS_VALID 0x02000000
29889 -#define OTGSC_INTR_A_SESSION_VALID 0x04000000
29890 -#define OTGSC_INTR_B_SESSION_VALID 0x08000000
29891 -#define OTGSC_INTR_B_SESSION_END 0x10000000
29892 -#define OTGSC_INTR_1MS_TIMER 0x20000000
29893 -#define OTGSC_INTR_DATA_PULSING 0x40000000
29894 -
29895 -/* USB MODE Register Bit Masks */
29896 -#define USB_MODE_CTRL_MODE_IDLE 0x00000000
29897 -#define USB_MODE_CTRL_MODE_DEVICE 0x00000002
29898 -#define USB_MODE_CTRL_MODE_HOST 0x00000003
29899 -#define USB_MODE_CTRL_MODE_RSV 0x00000001
29900 -#define USB_MODE_SETUP_LOCK_OFF 0x00000008
29901 -#define USB_MODE_STREAM_DISABLE 0x00000010
29902 -/* Endpoint Flush Register */
29903 -#define EPFLUSH_TX_OFFSET 0x00010000
29904 -#define EPFLUSH_RX_OFFSET 0x00000000
29905 -
29906 -/* Endpoint Setup Status bit masks */
29907 -#define EP_SETUP_STATUS_MASK 0x0000003F
29908 -#define EP_SETUP_STATUS_EP0 0x00000001
29909 -
29910 -/* ENDPOINTCTRLx Register Bit Masks */
29911 -#define EPCTRL_TX_ENABLE 0x00800000
29912 -#define EPCTRL_TX_DATA_TOGGLE_RST 0x00400000 /* Not EP0 */
29913 -#define EPCTRL_TX_DATA_TOGGLE_INH 0x00200000 /* Not EP0 */
29914 -#define EPCTRL_TX_TYPE 0x000C0000
29915 -#define EPCTRL_TX_DATA_SOURCE 0x00020000 /* Not EP0 */
29916 -#define EPCTRL_TX_EP_STALL 0x00010000
29917 -#define EPCTRL_RX_ENABLE 0x00000080
29918 -#define EPCTRL_RX_DATA_TOGGLE_RST 0x00000040 /* Not EP0 */
29919 -#define EPCTRL_RX_DATA_TOGGLE_INH 0x00000020 /* Not EP0 */
29920 -#define EPCTRL_RX_TYPE 0x0000000C
29921 -#define EPCTRL_RX_DATA_SINK 0x00000002 /* Not EP0 */
29922 -#define EPCTRL_RX_EP_STALL 0x00000001
29923 -
29924 -/* bit 19-18 and 3-2 are endpoint type */
29925 -#define EPCTRL_EP_TYPE_CONTROL 0
29926 -#define EPCTRL_EP_TYPE_ISO 1
29927 -#define EPCTRL_EP_TYPE_BULK 2
29928 -#define EPCTRL_EP_TYPE_INTERRUPT 3
29929 -#define EPCTRL_TX_EP_TYPE_SHIFT 18
29930 -#define EPCTRL_RX_EP_TYPE_SHIFT 2
29931 -
29932 -/* SNOOPn Register Bit Masks */
29933 -#define SNOOP_ADDRESS_MASK 0xFFFFF000
29934 -#define SNOOP_SIZE_ZERO 0x00 /* snooping disable */
29935 -#define SNOOP_SIZE_4KB 0x0B /* 4KB snoop size */
29936 -#define SNOOP_SIZE_8KB 0x0C
29937 -#define SNOOP_SIZE_16KB 0x0D
29938 -#define SNOOP_SIZE_32KB 0x0E
29939 -#define SNOOP_SIZE_64KB 0x0F
29940 -#define SNOOP_SIZE_128KB 0x10
29941 -#define SNOOP_SIZE_256KB 0x11
29942 -#define SNOOP_SIZE_512KB 0x12
29943 -#define SNOOP_SIZE_1MB 0x13
29944 -#define SNOOP_SIZE_2MB 0x14
29945 -#define SNOOP_SIZE_4MB 0x15
29946 -#define SNOOP_SIZE_8MB 0x16
29947 -#define SNOOP_SIZE_16MB 0x17
29948 -#define SNOOP_SIZE_32MB 0x18
29949 -#define SNOOP_SIZE_64MB 0x19
29950 -#define SNOOP_SIZE_128MB 0x1A
29951 -#define SNOOP_SIZE_256MB 0x1B
29952 -#define SNOOP_SIZE_512MB 0x1C
29953 -#define SNOOP_SIZE_1GB 0x1D
29954 -#define SNOOP_SIZE_2GB 0x1E /* 2GB snoop size */
29955 -
29956 -/* pri_ctrl Register Bit Masks */
29957 -#define PRI_CTRL_PRI_LVL1 0x0000000C
29958 -#define PRI_CTRL_PRI_LVL0 0x00000003
29959 -
29960 -/* si_ctrl Register Bit Masks */
29961 -#define SI_CTRL_ERR_DISABLE 0x00000010
29962 -#define SI_CTRL_IDRC_DISABLE 0x00000008
29963 -#define SI_CTRL_RD_SAFE_EN 0x00000004
29964 -#define SI_CTRL_RD_PREFETCH_DISABLE 0x00000002
29965 -#define SI_CTRL_RD_PREFEFETCH_VAL 0x00000001
29966 -
29967 -/* control Register Bit Masks */
29968 -#define USB_CTRL_IOENB 0x00000004
29969 -#define USB_CTRL_ULPI_INT0EN 0x00000001
29970
29971 /* Endpoint Queue Head data struct
29972 * Rem: all the variables of qh are LittleEndian Mode
29973 @@ -477,7 +297,10 @@ struct fsl_udc {
29974 unsigned int irq;
29975
29976 struct usb_ctrlrequest local_setup_buff;
29977 - spinlock_t lock;
29978 + spinlock_t lock; /* udc lock */
29979 + struct fsl_usb2_platform_data *pdata;
29980 + u32 xcvr_type;
29981 +
29982 struct otg_transceiver *transceiver;
29983 unsigned softconnect:1;
29984 unsigned vbus_active:1;
29985 @@ -514,7 +337,7 @@ struct fsl_udc {
29986 #define DBG(fmt, args...) printk(KERN_DEBUG "[%s] " fmt "\n", \
29987 __FUNCTION__, ## args)
29988 #else
29989 -#define DBG(fmt, args...) do{}while(0)
29990 +#define DBG(fmt, args...) do {} while (0)
29991 #endif
29992
29993 #if 0
29994 @@ -548,7 +371,7 @@ static void dump_msg(const char *label,
29995 #ifdef VERBOSE
29996 #define VDBG DBG
29997 #else
29998 -#define VDBG(stuff...) do{}while(0)
29999 +#define VDBG(stuff...) do {} while (0)
30000 #endif
30001
30002 #define ERR(stuff...) pr_err("udc: " stuff)
30003 @@ -573,11 +396,14 @@ static void dump_msg(const char *label,
30004 #define ep_maxpacket(EP) ((EP)->ep.maxpacket)
30005 #define ep_is_in(EP) ( (ep_index(EP) == 0) ? (EP->udc->ep0_dir == \
30006 USB_DIR_IN ):((EP)->desc->bEndpointAddress \
30007 - & USB_DIR_IN)==USB_DIR_IN)
30008 + & USB_DIR_IN) == USB_DIR_IN)
30009 #define get_ep_by_pipe(udc, pipe) ((pipe == 1)? &udc->eps[0]: \
30010 &udc->eps[pipe])
30011 #define get_pipe_by_windex(windex) ((windex & USB_ENDPOINT_NUMBER_MASK) \
30012 * 2 + ((windex & USB_DIR_IN) ? 1 : 0))
30013 #define get_pipe_by_ep(EP) (ep_index(EP) * 2 + ep_is_in(EP))
30014
30015 +/* Bulk only class request */
30016 +#define USB_BULK_RESET_REQUEST 0xff
30017 +
30018 #endif
30019 --- a/drivers/usb/gadget/gadget_chips.h
30020 +++ b/drivers/usb/gadget/gadget_chips.h
30021 @@ -147,6 +147,11 @@
30022 #define gadget_is_m66592(g) 0
30023 #endif
30024
30025 +#ifdef CONFIG_USB_GADGET_MCF5445X
30026 +#define gadget_is_mcf5445x(g) !strcmp("fsl-usb2-udc", (g)->name)
30027 +#else
30028 +#define gadget_is_mcf5445x(g) 0
30029 +#endif
30030
30031 // CONFIG_USB_GADGET_SX2
30032 // CONFIG_USB_GADGET_AU1X00
30033 @@ -212,5 +217,7 @@ static inline int usb_gadget_controller_
30034 return 0x20;
30035 else if (gadget_is_m66592(gadget))
30036 return 0x21;
30037 + else if (gadget_is_mcf5445x(gadget))
30038 + return 0x22;
30039 return -ENOENT;
30040 }
30041 --- a/drivers/usb/gadget/Kconfig
30042 +++ b/drivers/usb/gadget/Kconfig
30043 @@ -231,6 +231,26 @@ config SUPERH_BUILT_IN_M66592
30044 However, this problem is improved if change a value of
30045 NET_IP_ALIGN to 4.
30046
30047 +config USB_GADGET_MCF5445X
30048 + boolean "MCF5445X USB Device Controller"
30049 + depends on M54455 && USB_M5445X_ULPI
30050 + select USB_GADGET_DUALSPEED
30051 + help
30052 + Freescale's MCF5445X processors include
30053 + an integrated device controller (as part of the OTG module).
30054 + It has four programmable, bidirectional endpoints,
30055 + including endpoint 0.
30056 +
30057 + Say "y" to link the driver statically, or "m" to build a
30058 + dynamically linked module called "mcf5445_udc" and force all
30059 + gadget drivers to also be dynamically linked.
30060 +
30061 +config USB_MCF5445X
30062 + tristate
30063 + depends on USB_GADGET_MCF5445X
30064 + default USB_GADGET
30065 + select USB_GADGET_SELECTED
30066 +
30067 config USB_GADGET_GOKU
30068 boolean "Toshiba TC86C001 'Goku-S'"
30069 depends on PCI
30070 @@ -285,17 +305,6 @@ config USB_OMAP
30071 default USB_GADGET
30072 select USB_GADGET_SELECTED
30073
30074 -config USB_OTG
30075 - boolean "OTG Support"
30076 - depends on USB_GADGET_OMAP && ARCH_OMAP_OTG && USB_OHCI_HCD
30077 - help
30078 - The most notable feature of USB OTG is support for a
30079 - "Dual-Role" device, which can act as either a device
30080 - or a host. The initial role choice can be changed
30081 - later, when two dual-role devices talk to each other.
30082 -
30083 - Select this only if your OMAP board has a Mini-AB connector.
30084 -
30085 config USB_GADGET_S3C2410
30086 boolean "S3C2410 USB Device Controller"
30087 depends on ARCH_S3C2410
30088 @@ -369,6 +378,18 @@ config USB_DUMMY_HCD
30089
30090 endchoice
30091
30092 +config USB_OTG
30093 + boolean "OTG Support"
30094 + depends on (USB_GADGET_OMAP && ARCH_OMAP_OTG && USB_OHCI_HCD) || \
30095 + (USB_GADGET_MCF5445X && USB_M5445X_ULPI)
30096 + help
30097 + The most notable feature of USB OTG is support for a
30098 + "Dual-Role" device, which can act as either a device
30099 + or a host. The initial role choice can be changed
30100 + later, when two dual-role devices talk to each other.
30101 +
30102 + Select this only if your OMAP board has a Mini-AB connector.
30103 +
30104 config USB_GADGET_DUALSPEED
30105 bool
30106 depends on USB_GADGET
30107 --- a/drivers/usb/gadget/Makefile
30108 +++ b/drivers/usb/gadget/Makefile
30109 @@ -17,6 +17,7 @@ obj-$(CONFIG_USB_AT91) += at91_udc.o
30110 obj-$(CONFIG_USB_ATMEL_USBA) += atmel_usba_udc.o
30111 obj-$(CONFIG_USB_FSL_USB2) += fsl_usb2_udc.o
30112 obj-$(CONFIG_USB_M66592) += m66592-udc.o
30113 +obj-$(CONFIG_USB_MCF5445X) += mcf5445x_udc.o
30114
30115 #
30116 # USB gadget drivers
30117 --- /dev/null
30118 +++ b/drivers/usb/gadget/mcf5445x_udc.c
30119 @@ -0,0 +1,2745 @@
30120 +/*
30121 + * Copyright Freescale Semiconductor, Inc. 2006-2007
30122 + *
30123 + * Based on mpc_udc.c code
30124 + * of Li Yang and Jiang Bo (Freescale Semiconductor, Inc.)
30125 + *
30126 + *
30127 + * This program is free software; you can redistribute it and/or modify it
30128 + * under the terms of the GNU General Public License as published by the
30129 + * Free Software Foundation; either version 2 of the License, or (at your
30130 + * option) any later version.
30131 + *
30132 + * This program is distributed in the hope that it will be useful,
30133 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
30134 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30135 + * GNU General Public License for more details.
30136 + *
30137 + * You should have received a copy of the GNU General Public License
30138 + * along with this program; if not, write to the Free Software
30139 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30140 + *
30141 + ***************************************************************************
30142 + * Changes:
30143 + * v0.004 30 July 2007 Duck
30144 + * mcf5445x port
30145 + * v0.003 27 October 2006 Andrey Butok
30146 + * Added M5329EVB support (without external transceiver).
30147 + * v0.002 29 September 2006 Andrey Butok
30148 + * Some little changes. Added OTG support.
30149 + * v0.001 12 July 2006 Andrey Butok
30150 + * Initial Release - developed on uClinux with 2.6.17.1 kernel.
30151 + * Based on mpc_udc.c code
30152 + * of Li Yang and Jiang Bo (Freescale Semiconductor, Inc.)
30153 + *
30154 + */
30155 +
30156 +#undef DEBUG
30157 +#undef VERBOSE
30158 +
30159 +#include <linux/module.h>
30160 +#include <linux/kernel.h>
30161 +#include <linux/ioport.h>
30162 +#include <linux/types.h>
30163 +#include <linux/errno.h>
30164 +#include <linux/delay.h>
30165 +#include <linux/sched.h>
30166 +#include <linux/slab.h>
30167 +#include <linux/init.h>
30168 +#include <linux/io.h>
30169 +#include <linux/irq.h>
30170 +#include <linux/timer.h>
30171 +#include <linux/list.h>
30172 +#include <linux/interrupt.h>
30173 +#include <linux/proc_fs.h>
30174 +#include <linux/mm.h>
30175 +#include <linux/platform_device.h>
30176 +#include <linux/moduleparam.h>
30177 +#include <linux/device.h>
30178 +#include <linux/usb/ch9.h>
30179 +#include <linux/usb/gadget.h>
30180 +#include <linux/usb/otg.h>
30181 +#include <linux/dma-mapping.h>
30182 +#include <linux/dmapool.h>
30183 +#include <linux/fsl_devices.h>
30184 +#include <linux/usb/fsl_xcvr.h>
30185 +#include <linux/usb/fsl_usb2.h>
30186 +#include <linux/pm.h>
30187 +
30188 +#include <asm/byteorder.h>
30189 +#include <asm/system.h>
30190 +#include <asm/unaligned.h>
30191 +#include <asm/dma.h>
30192 +
30193 +#include <asm/mcfsim.h>
30194 +#include <asm/cacheflush.h>
30195 +
30196 +#include "fsl_usb2_udc.h"
30197 +
30198 +#define DRIVER_DESC "Freescale High-Speed USB SoC Device Controller driver"
30199 +#define DRIVER_AUTHOR "Freescale Semiconductor Inc."
30200 +#define DRIVER_VERSION "30 July 2007"
30201 +
30202 +#define cpu_to_hc32(x) (x)
30203 +#define hc32_to_cpu(x) (x)
30204 +
30205 +static int udc_suspend(struct fsl_udc *udc);
30206 +
30207 +#define DMA_ADDR_INVALID (~(dma_addr_t)0)
30208 +
30209 +static const char driver_name[] = "fsl-usb2-udc";
30210 +static const char driver_desc[] = DRIVER_DESC;
30211 +
30212 +volatile static struct fsl_usb_device_regs *dr_regs;
30213 +volatile static struct usb_sys_interface *usb_sys_regs;
30214 +
30215 +/* it is initialized in probe() */
30216 +static struct fsl_udc *udc_controller;
30217 +
30218 +static const struct usb_endpoint_descriptor
30219 +fsl_ep0_desc = {
30220 + .bLength = USB_DT_ENDPOINT_SIZE,
30221 + .bDescriptorType = USB_DT_ENDPOINT,
30222 + .bEndpointAddress = 0,
30223 + .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
30224 + .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD,
30225 +};
30226 +
30227 +static int fsl_udc_suspend(struct device *dev, pm_message_t state);
30228 +static int fsl_udc_resume(struct device *dev);
30229 +static void fsl_ep_fifo_flush(struct usb_ep *_ep);
30230 +
30231 +/********************************************************************
30232 + * Internal Used Function
30233 +********************************************************************/
30234 +/*-----------------------------------------------------------------
30235 + * done() - retire a request; caller blocked irqs
30236 + * @status : request status to be set, only works when
30237 + * request is still in progress.
30238 + *--------------------------------------------------------------*/
30239 +static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
30240 +{
30241 + struct fsl_udc *udc = NULL;
30242 + unsigned char stopped = ep->stopped;
30243 +
30244 + udc = (struct fsl_udc *)ep->udc;
30245 +
30246 + pr_debug("udc: req=0x%p\n", req);
30247 + if (req->head) {
30248 + pr_debug("udc: freeing head=0x%p\n", req->head);
30249 + dma_pool_free(udc->td_pool, req->head, req->head->td_dma);
30250 + }
30251 +
30252 + /* the req->queue pointer is used by ep_queue() func, in which
30253 + * the request will be added into a udc_ep->queue 'd tail
30254 + * so here the req will be dropped from the ep->queue
30255 + */
30256 + list_del_init(&req->queue);
30257 +
30258 + /* req.status should be set as -EINPROGRESS in ep_queue() */
30259 + if (req->req.status == -EINPROGRESS)
30260 + req->req.status = status;
30261 + else
30262 + status = req->req.status;
30263 +
30264 + pr_debug("udc: req=0x%p mapped=%x\n", req, req->mapped);
30265 +
30266 + if (req->mapped) {
30267 + pr_debug("udc: calling dma_unmap_single(buf,%s) req=0x%p "
30268 + "a=0x%x len=%d\n",
30269 + ep_is_in(ep) ? "to_dvc" : "from_dvc",
30270 + req, req->req.dma, req->req.length);
30271 +
30272 + dma_unmap_single(ep->udc->gadget.dev.parent,
30273 + req->req.dma, req->req.length, ep_is_in(ep) ?
30274 + DMA_TO_DEVICE : DMA_FROM_DEVICE);
30275 +
30276 + req->req.dma = DMA_ADDR_INVALID;
30277 + req->mapped = 0;
30278 + pr_debug("udc: req=0x%p set req.dma=0x%x\n", req, req->req.dma);
30279 + } else {
30280 + if ((req->req.length != 0)
30281 + && (req->req.dma != DMA_ADDR_INVALID)) {
30282 + pr_debug("udc: calling dma_sync_single_for_cpu(buf,%s) "
30283 + "req=0x%p dma=0x%x len=%d\n",
30284 + ep_is_in(ep) ? "to_dvc" : "from_dvc", req,
30285 + req->req.dma, req->req.length);
30286 +
30287 + dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
30288 + req->req.dma, req->req.length,
30289 + ep_is_in(ep) ? DMA_TO_DEVICE :
30290 + DMA_FROM_DEVICE);
30291 + }
30292 + }
30293 +
30294 + if (status && (status != -ESHUTDOWN)) {
30295 + pr_debug("udc: complete %s req 0c%p stat %d len %u/%u\n",
30296 + ep->ep.name, &req->req, status,
30297 + req->req.actual, req->req.length);
30298 + }
30299 +
30300 + /* don't modify queue heads during completion callback */
30301 + ep->stopped = 1;
30302 +
30303 + spin_unlock(&ep->udc->lock);
30304 +
30305 + /* this complete() should a func implemented by gadget layer,
30306 + * eg fsg->bulk_in_complete() */
30307 + if (req->req.complete) {
30308 + pr_debug("udc: calling gadget's complete() req=0x%p\n", req);
30309 + req->req.complete(&ep->ep, &req->req);
30310 + pr_debug("udc: back from gadget's complete()\n");
30311 + }
30312 +
30313 + spin_lock(&ep->udc->lock);
30314 + ep->stopped = stopped;
30315 +}
30316 +
30317 +/*
30318 + * nuke(): delete all requests related to this ep
30319 + * called with spinlock held
30320 + *--------------------------------------------------------------*/
30321 +static void nuke(struct fsl_ep *ep, int status)
30322 +{
30323 + ep->stopped = 1;
30324 +
30325 + /* Flush fifo */
30326 + fsl_ep_fifo_flush(&ep->ep);
30327 +
30328 + /* Whether this eq has request linked */
30329 + while (!list_empty(&ep->queue)) {
30330 + struct fsl_req *req = NULL;
30331 +
30332 + req = list_entry(ep->queue.next, struct fsl_req, queue);
30333 + done(ep, req, status);
30334 + }
30335 +}
30336 +
30337 +/*------------------------------------------------------------------
30338 + Internal Hardware related function
30339 + ------------------------------------------------------------------*/
30340 +
30341 +static int dr_controller_setup(struct fsl_udc *udc)
30342 +{
30343 + unsigned int tmp;
30344 + unsigned int __attribute((unused)) ctrl = 0;
30345 + unsigned long timeout;
30346 + struct fsl_usb2_platform_data *pdata;
30347 +
30348 +#define FSL_UDC_RESET_TIMEOUT 1000
30349 +
30350 + /* before here, make sure dr_regs has been initialized */
30351 + if (!udc)
30352 + return -EINVAL;
30353 + pdata = udc->pdata;
30354 +
30355 + /* Stop and reset the usb controller */
30356 + tmp = fsl_readl(&dr_regs->usbcmd);
30357 + tmp &= ~USB_CMD_RUN_STOP;
30358 + fsl_writel(tmp, &dr_regs->usbcmd);
30359 +
30360 + tmp = fsl_readl(&dr_regs->usbcmd);
30361 + tmp |= USB_CMD_CTRL_RESET;
30362 + fsl_writel(tmp, &dr_regs->usbcmd);
30363 +
30364 + /* Wait for reset to complete */
30365 + timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
30366 + while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
30367 + if (time_after(jiffies, timeout)) {
30368 + ERR("udc reset timeout! \n");
30369 + return -ETIMEDOUT;
30370 + }
30371 + cpu_relax();
30372 + }
30373 +
30374 + tmp = fsl_readl(&dr_regs->usbmode);
30375 + tmp &= ~0x3; /* clear mode bits */
30376 + tmp |= USB_MODE_CTRL_MODE_DEVICE;
30377 + /* Disable Setup Lockout */
30378 + tmp |= USB_MODE_SETUP_LOCK_OFF;
30379 + if (pdata->es)
30380 + tmp |= USBMODE_ES;
30381 + fsl_writel(tmp, &dr_regs->usbmode);
30382 +
30383 + if (pdata->xcvr_ops && pdata->xcvr_ops->set_device)
30384 + pdata->xcvr_ops->set_device();
30385 +
30386 + /* Clear the setup status */
30387 + fsl_writel(0, &dr_regs->usbsts);
30388 +
30389 + tmp = udc->ep_qh_dma;
30390 + tmp &= USB_EP_LIST_ADDRESS_MASK;
30391 + fsl_writel(tmp, &dr_regs->endpointlistaddr);
30392 +
30393 + /*
30394 + VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
30395 + (int)udc->ep_qh, (int)tmp,
30396 + fsl_readl(&dr_regs->endpointlistaddr));
30397 + */
30398 +
30399 +
30400 + if (pdata->have_sysif_regs) {
30401 + /* Config control enable i/o output, cpu endian register */
30402 + ctrl = __raw_readl(&usb_sys_regs->control);
30403 + ctrl |= USB_CTRL_IOENB;
30404 + __raw_writel(ctrl, &usb_sys_regs->control);
30405 + }
30406 +
30407 +#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
30408 + /* Turn on cache snooping hardware, since some PowerPC platforms
30409 + * wholly rely on hardware to deal with cache coherent. */
30410 +
30411 + if (pdata->have_sysif_regs) {
30412 + /* Setup Snooping for all the 4GB space */
30413 + tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
30414 + __raw_writel(tmp, &usb_sys_regs->snoop1);
30415 + tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
30416 + __raw_writel(tmp, &usb_sys_regs->snoop2);
30417 + }
30418 +#endif
30419 +
30420 + return 0;
30421 +}
30422 +
30423 +static void pullup_enable(struct fsl_udc *udc)
30424 +{
30425 + u32 temp;
30426 +
30427 + unsigned short ccm = fsl_readw(&MCF_CCM_UOCSR);
30428 + ccm |= MCF_CCM_UOCSR_BVLD;
30429 + ccm &= ~MCF_CCM_UOCSR_SEND;
30430 + fsl_writew(ccm, &MCF_CCM_UOCSR);
30431 +
30432 + /* Enable DR irq reg */
30433 + temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
30434 + | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
30435 + | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
30436 +
30437 + fsl_writel(temp, &dr_regs->usbintr);
30438 +
30439 + /* Set controller to Run */
30440 + temp = fsl_readl(&dr_regs->usbcmd);
30441 + temp |= USB_CMD_RUN_STOP;
30442 + fsl_writel(temp, &dr_regs->usbcmd);
30443 +}
30444 +
30445 +static void pullup_disable(struct fsl_udc *udc)
30446 +{
30447 + unsigned int tmp;
30448 + unsigned short ccm;
30449 +
30450 + VDBG();
30451 + /* disable all INTRs */
30452 + fsl_writel(0, &dr_regs->usbintr);
30453 +
30454 + ccm = fsl_readw(&MCF_CCM_UOCSR);
30455 + ccm &= ~MCF_CCM_UOCSR_BVLD;
30456 + fsl_writew(ccm, &MCF_CCM_UOCSR);
30457 +
30458 + /* set controller to Stop */
30459 + tmp = fsl_readl(&dr_regs->usbcmd);
30460 + tmp &= ~USB_CMD_RUN_STOP;
30461 + fsl_writel(tmp, &dr_regs->usbcmd);
30462 +}
30463 +
30464 +static void dr_controller_run(struct fsl_udc *udc)
30465 +{
30466 + VDBG();
30467 + pullup_enable(udc);
30468 + udc->stopped = 0;
30469 +}
30470 +
30471 +static void dr_controller_stop(struct fsl_udc *udc)
30472 +{
30473 + pullup_disable(udc);
30474 + udc->stopped = 1;
30475 + udc->gadget.b_hnp_enable = 0;
30476 + udc->gadget.a_hnp_support = 0;
30477 + udc->gadget.a_alt_hnp_support = 0;
30478 +}
30479 +
30480 +void dr_ep_setup(unsigned char ep_num, unsigned char dir, unsigned char ep_type)
30481 +{
30482 + unsigned int tmp_epctrl = 0;
30483 +
30484 + tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
30485 + if (dir) {
30486 + if (ep_num)
30487 + tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
30488 + tmp_epctrl |= EPCTRL_TX_ENABLE;
30489 + tmp_epctrl |= ((unsigned int)(ep_type)
30490 + << EPCTRL_TX_EP_TYPE_SHIFT);
30491 + } else {
30492 + if (ep_num)
30493 + tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
30494 + tmp_epctrl |= EPCTRL_RX_ENABLE;
30495 + tmp_epctrl |= ((unsigned int)(ep_type)
30496 + << EPCTRL_RX_EP_TYPE_SHIFT);
30497 + }
30498 +
30499 + fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
30500 +}
30501 +
30502 +static void dr_ep_change_stall(unsigned char ep_num, unsigned char dir,
30503 + int value)
30504 +{
30505 + u32 tmp_epctrl = 0;
30506 +
30507 + tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
30508 +
30509 + if (value) {
30510 + /* set the stall bit */
30511 + if (dir)
30512 + tmp_epctrl |= EPCTRL_TX_EP_STALL;
30513 + else
30514 + tmp_epctrl |= EPCTRL_RX_EP_STALL;
30515 + } else {
30516 + /* clear the stall bit and reset data toggle */
30517 + if (dir) {
30518 + tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
30519 + tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
30520 + } else {
30521 + tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
30522 + tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
30523 + }
30524 + }
30525 + fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
30526 +}
30527 +
30528 +/* Get stall status of a specific ep
30529 + Return: 0: not stalled; 1:stalled */
30530 +static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
30531 +{
30532 + u32 epctrl;
30533 +
30534 + epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
30535 + if (dir)
30536 + return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
30537 + else
30538 + return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
30539 +}
30540 +
30541 +/********************************************************************
30542 + Internal Structure Build up functions
30543 +********************************************************************/
30544 +
30545 +/*------------------------------------------------------------------
30546 +* struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
30547 + * @zlt: Zero Length Termination Select (1: disable; 0: enable)
30548 + * @mult: Mult field
30549 + ------------------------------------------------------------------*/
30550 +static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
30551 + unsigned char dir, unsigned char ep_type,
30552 + unsigned int max_pkt_len,
30553 + unsigned int zlt, unsigned char mult)
30554 +{
30555 + struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
30556 + unsigned int tmp = 0;
30557 +
30558 + /* set the Endpoint Capabilites in QH */
30559 + switch (ep_type) {
30560 + case USB_ENDPOINT_XFER_CONTROL:
30561 + /* Interrupt On Setup (IOS). for control ep */
30562 + tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
30563 + | EP_QUEUE_HEAD_IOS;
30564 + break;
30565 + case USB_ENDPOINT_XFER_ISOC:
30566 + tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
30567 + | (mult << EP_QUEUE_HEAD_MULT_POS);
30568 + break;
30569 + case USB_ENDPOINT_XFER_BULK:
30570 + case USB_ENDPOINT_XFER_INT:
30571 + tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
30572 + break;
30573 + default:
30574 + VDBG("error ep type is %d", ep_type);
30575 + return;
30576 + }
30577 + if (zlt)
30578 + tmp |= EP_QUEUE_HEAD_ZLT_SEL;
30579 + p_QH->max_pkt_length = cpu_to_hc32(tmp);
30580 +
30581 + return;
30582 +}
30583 +
30584 +/* Setup qh structure and ep register for ep0. */
30585 +static void ep0_setup(struct fsl_udc *udc)
30586 +{
30587 + /* the intialization of an ep includes: fields in QH, Regs,
30588 + * fsl_ep struct */
30589 + struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
30590 + USB_MAX_CTRL_PAYLOAD, 0, 0);
30591 + struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
30592 + USB_MAX_CTRL_PAYLOAD, 0, 0);
30593 + dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
30594 + dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
30595 +
30596 + return;
30597 +
30598 +}
30599 +
30600 +/***********************************************************************
30601 + Endpoint Management Functions
30602 +***********************************************************************/
30603 +
30604 +/*-------------------------------------------------------------------------
30605 + * when configurations are set, or when interface settings change
30606 + * for example the do_set_interface() in gadget layer,
30607 + * the driver will enable or disable the relevant endpoints
30608 + * ep0 doesn't use this routine. It is always enabled.
30609 +-------------------------------------------------------------------------*/
30610 +static int fsl_ep_enable(struct usb_ep *_ep,
30611 + const struct usb_endpoint_descriptor *desc)
30612 +{
30613 + struct fsl_udc *udc = NULL;
30614 + struct fsl_ep *ep = NULL;
30615 + unsigned short max = 0;
30616 + unsigned char mult = 0, zlt;
30617 + int retval = -EINVAL;
30618 + unsigned long flags = 0;
30619 +
30620 + ep = container_of(_ep, struct fsl_ep, ep);
30621 +
30622 + /* catch various bogus parameters */
30623 + if (!_ep || !desc || ep->desc
30624 + || (desc->bDescriptorType != USB_DT_ENDPOINT))
30625 + return -EINVAL;
30626 +
30627 + udc = ep->udc;
30628 +
30629 + if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
30630 + return -ESHUTDOWN;
30631 +
30632 + max = le16_to_cpu(desc->wMaxPacketSize);
30633 +
30634 + /* Disable automatic zlp generation. Driver is reponsible to indicate
30635 + * explicitly through req->req.zero. This is needed to enable multi-td
30636 + * request. */
30637 + zlt = 1;
30638 +
30639 + /* Assume the max packet size from gadget is always correct */
30640 + switch (desc->bmAttributes & 0x03) {
30641 + case USB_ENDPOINT_XFER_CONTROL:
30642 + case USB_ENDPOINT_XFER_BULK:
30643 + case USB_ENDPOINT_XFER_INT:
30644 + /* mult = 0. Execute N Transactions as demonstrated by
30645 + * the USB variable length packet protocol where N is
30646 + * computed using the Maximum Packet Length (dQH) and
30647 + * the Total Bytes field (dTD) */
30648 + mult = 0;
30649 + break;
30650 + case USB_ENDPOINT_XFER_ISOC:
30651 + /* Calculate transactions needed for high bandwidth iso */
30652 + mult = (unsigned char)(1 + ((max >> 11) & 0x03));
30653 + max = max & 0x8ff; /* bit 0~10 */
30654 + /* 3 transactions at most */
30655 + if (mult > 3)
30656 + goto en_done;
30657 + break;
30658 + default:
30659 + goto en_done;
30660 + }
30661 +
30662 + spin_lock_irqsave(&udc->lock, flags);
30663 + ep->ep.maxpacket = max;
30664 + ep->desc = desc;
30665 + ep->stopped = 0;
30666 +
30667 + /* Controller related setup */
30668 + /* Init EPx Queue Head (Ep Capabilites field in QH
30669 + * according to max, zlt, mult) */
30670 + struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
30671 + (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
30672 + ? USB_SEND : USB_RECV),
30673 + (unsigned char) (desc->bmAttributes
30674 + & USB_ENDPOINT_XFERTYPE_MASK),
30675 + max, zlt, mult);
30676 +
30677 + /* Init endpoint ctrl register */
30678 + dr_ep_setup((unsigned char) ep_index(ep),
30679 + (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
30680 + ? USB_SEND : USB_RECV),
30681 + (unsigned char) (desc->bmAttributes
30682 + & USB_ENDPOINT_XFERTYPE_MASK));
30683 +
30684 + spin_unlock_irqrestore(&udc->lock, flags);
30685 + retval = 0;
30686 +
30687 + VDBG("enabled %s (ep%d%s) maxpacket %d", ep->ep.name,
30688 + ep->desc->bEndpointAddress & 0x0f,
30689 + (desc->bEndpointAddress & USB_DIR_IN)
30690 + ? "in" : "out", max);
30691 +en_done:
30692 + return retval;
30693 +}
30694 +
30695 +/*---------------------------------------------------------------------
30696 + * @ep : the ep being unconfigured. May not be ep0
30697 + * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
30698 +*---------------------------------------------------------------------*/
30699 +static int fsl_ep_disable(struct usb_ep *_ep)
30700 +{
30701 + struct fsl_udc *udc = NULL;
30702 + struct fsl_ep *ep = NULL;
30703 + unsigned long flags = 0;
30704 + u32 epctrl;
30705 + int ep_num;
30706 +
30707 + ep = container_of(_ep, struct fsl_ep, ep);
30708 + if (!_ep || !ep->desc) {
30709 + pr_debug("udc: %s not enabled\n", _ep ? ep->ep.name : NULL);
30710 + return -EINVAL;
30711 + }
30712 +
30713 + /* disable ep on controller */
30714 + ep_num = ep_index(ep);
30715 + epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
30716 + if (ep_is_in(ep))
30717 + epctrl &= ~EPCTRL_TX_ENABLE;
30718 + else
30719 + epctrl &= ~EPCTRL_RX_ENABLE;
30720 + fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
30721 +
30722 + udc = (struct fsl_udc *)ep->udc;
30723 + spin_lock_irqsave(&udc->lock, flags);
30724 +
30725 + /* nuke all pending requests (does flush) */
30726 + nuke(ep, -ESHUTDOWN);
30727 +
30728 + ep->desc = 0;
30729 + ep->stopped = 1;
30730 + spin_unlock_irqrestore(&udc->lock, flags);
30731 +
30732 + pr_debug("udc: disabled %s OK\n", _ep->name);
30733 + return 0;
30734 +}
30735 +
30736 +/*---------------------------------------------------------------------
30737 + * allocate a request object used by this endpoint
30738 + * the main operation is to insert the req->queue to the eq->queue
30739 + * Returns the request, or null if one could not be allocated
30740 +*---------------------------------------------------------------------*/
30741 +static struct usb_request *
30742 +fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
30743 +{
30744 + struct fsl_req *req = NULL;
30745 +
30746 + req = kzalloc(sizeof *req, gfp_flags);
30747 + if (!req)
30748 + return NULL;
30749 +
30750 + req->req.dma = DMA_ADDR_INVALID;
30751 + pr_debug("udc: req=0x%p set req.dma=0x%x\n", req, req->req.dma);
30752 + INIT_LIST_HEAD(&req->queue);
30753 +
30754 + return &req->req;
30755 +}
30756 +
30757 +static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
30758 +{
30759 + struct fsl_req *req;
30760 +
30761 + req = container_of(_req, struct fsl_req, req);
30762 + pr_debug("udc: req=0x%p\n", req);
30763 +
30764 + if (_req)
30765 + kfree(req);
30766 +}
30767 +
30768 +/*-------------------------------------------------------------------------*/
30769 +static int fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
30770 +{
30771 + int i = ep_index(ep) * 2 + ep_is_in(ep);
30772 + u32 temp, bitmask, tmp_stat;
30773 + struct ep_queue_head *dQH = &ep->udc->ep_qh[i];
30774 +
30775 + pr_debug("udc: queue req=0x%p to ep index %d\n", req, i);
30776 +
30777 + bitmask = ep_is_in(ep)
30778 + ? (1 << (ep_index(ep) + 16))
30779 + : (1 << (ep_index(ep)));
30780 +
30781 + /* check if the pipe is empty */
30782 + if (!(list_empty(&ep->queue))) {
30783 + /* Add td to the end */
30784 + struct fsl_req *lastreq;
30785 + lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
30786 + lastreq->tail->next_td_ptr =
30787 + cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
30788 + /* Read prime bit, if 1 goto done */
30789 + if (fsl_readl(&dr_regs->endpointprime) & bitmask)
30790 + goto out;
30791 +
30792 + do {
30793 + /* Set ATDTW bit in USBCMD */
30794 + temp = fsl_readl(&dr_regs->usbcmd);
30795 + fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
30796 +
30797 + /* Read correct status bit */
30798 + tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
30799 +
30800 + } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
30801 +
30802 + /* Write ATDTW bit to 0 */
30803 + temp = fsl_readl(&dr_regs->usbcmd);
30804 + fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
30805 +
30806 + if (tmp_stat)
30807 + goto out;
30808 + }
30809 +
30810 + /* Write dQH next pointer and terminate bit to 0 */
30811 + temp = req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
30812 + dQH->next_dtd_ptr = cpu_to_hc32(temp);
30813 +
30814 + /* Clear active and halt bit */
30815 + temp = cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
30816 + | EP_QUEUE_HEAD_STATUS_HALT));
30817 + dQH->size_ioc_int_sts &= temp;
30818 +
30819 + /* Prime endpoint by writing 1 to ENDPTPRIME */
30820 + temp = ep_is_in(ep)
30821 + ? (1 << (ep_index(ep) + 16))
30822 + : (1 << (ep_index(ep)));
30823 + fsl_writel(temp, &dr_regs->endpointprime);
30824 +out:
30825 + return 0;
30826 +}
30827 +
30828 +/* Fill in the dTD structure
30829 + * @req: request that the transfer belongs to
30830 + * @length: return actually data length of the dTD
30831 + * @dma: return dma address of the dTD
30832 + * @is_last: return flag if it is the last dTD of the request
30833 + * return: pointer to the built dTD */
30834 +static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
30835 + dma_addr_t *dma, int *is_last)
30836 +{
30837 + u32 swap_temp;
30838 + struct ep_td_struct *dtd;
30839 +
30840 + /* how big will this transfer be? */
30841 + *length = min(req->req.length - req->req.actual,
30842 + (unsigned)EP_MAX_LENGTH_TRANSFER);
30843 +
30844 + dtd = dma_pool_alloc(udc_controller->td_pool, GFP_KERNEL, dma);
30845 + if (dtd == NULL)
30846 + return dtd;
30847 +
30848 + dtd->td_dma = *dma;
30849 + /* Clear reserved field */
30850 + swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
30851 + swap_temp &= ~DTD_RESERVED_FIELDS;
30852 + dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
30853 +
30854 + /* Init all of buffer page pointers */
30855 + swap_temp = (u32) (req->req.dma + req->req.actual);
30856 + dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
30857 + dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
30858 + dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
30859 + dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
30860 + dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
30861 +
30862 + req->req.actual += *length;
30863 +
30864 + /* zlp is needed if req->req.zero is set */
30865 + if (req->req.zero) {
30866 + if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
30867 + *is_last = 1;
30868 + else
30869 + *is_last = 0;
30870 + } else if (req->req.length == req->req.actual)
30871 + *is_last = 1;
30872 + else
30873 + *is_last = 0;
30874 +
30875 + if ((*is_last) == 0)
30876 + VDBG("multi-dtd request!\n");
30877 + /* Fill in the transfer size; set active bit */
30878 + swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
30879 +
30880 + /* Enable interrupt for the last dtd of a request */
30881 + if (*is_last && !req->req.no_interrupt)
30882 + swap_temp |= DTD_IOC;
30883 +
30884 + dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
30885 +
30886 + mb();
30887 +
30888 + VDBG("length = %d address= 0x%x", *length, (int)*dma);
30889 +
30890 + return dtd;
30891 +}
30892 +
30893 +/* Generate dtd chain for a request */
30894 +static int fsl_req_to_dtd(struct fsl_req *req)
30895 +{
30896 + unsigned count;
30897 + int is_last;
30898 + int is_first = 1;
30899 + struct ep_td_struct *last_dtd = NULL, *dtd;
30900 + dma_addr_t dma;
30901 +
30902 + do {
30903 + dtd = fsl_build_dtd(req, &count, &dma, &is_last);
30904 + if (dtd == NULL)
30905 + return -ENOMEM;
30906 +
30907 + if (is_first) {
30908 + is_first = 0;
30909 + req->head = dtd;
30910 + } else {
30911 + last_dtd->next_td_ptr = hc32_to_cpu(dma);
30912 + last_dtd->next_td_virt = dtd;
30913 + }
30914 + last_dtd = dtd;
30915 +
30916 + req->dtd_count++;
30917 + } while (!is_last);
30918 +
30919 + dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
30920 +
30921 + req->tail = dtd;
30922 +
30923 + return 0;
30924 +}
30925 +
30926 +/* queues (submits) an I/O request to an endpoint */
30927 +static int
30928 +fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
30929 +{
30930 + struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
30931 + struct fsl_req *req = container_of(_req, struct fsl_req, req);
30932 + struct fsl_udc *udc;
30933 + unsigned long flags;
30934 + int is_iso = 0;
30935 +
30936 + /* catch various bogus parameters */
30937 + if (!_req || !req->req.complete || !req->req.buf
30938 + || !list_empty(&req->queue)) {
30939 + VDBG("%s, bad params\n", __FUNCTION__);
30940 + return -EINVAL;
30941 + }
30942 + if (!_ep || (!ep->desc && ep_index(ep))) {
30943 + VDBG("%s, bad ep\n", __FUNCTION__);
30944 + return -EINVAL;
30945 + }
30946 + if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
30947 + if (req->req.length > ep->ep.maxpacket)
30948 + return -EMSGSIZE;
30949 + is_iso = 1;
30950 + }
30951 +
30952 + udc = ep->udc;
30953 + if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
30954 + return -ESHUTDOWN;
30955 +
30956 + req->ep = ep;
30957 +
30958 + /* map virtual address to hardware */
30959 + if (req->req.dma == DMA_ADDR_INVALID) {
30960 + req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
30961 + req->req.buf,
30962 + req->req.length, ep_is_in(ep)
30963 + ? DMA_TO_DEVICE
30964 + : DMA_FROM_DEVICE);
30965 + req->mapped = 1;
30966 + } else {
30967 + dma_sync_single_for_device(ep->udc->gadget.dev.parent,
30968 + req->req.dma, req->req.length,
30969 + ep_is_in(ep)
30970 + ? DMA_TO_DEVICE
30971 + : DMA_FROM_DEVICE);
30972 + req->mapped = 0;
30973 + }
30974 +
30975 + req->req.status = -EINPROGRESS;
30976 + req->req.actual = 0;
30977 + req->dtd_count = 0;
30978 +
30979 + spin_lock_irqsave(&udc->lock, flags);
30980 +
30981 + /* build dtds and push them to device queue */
30982 + if (!fsl_req_to_dtd(req)) {
30983 + fsl_queue_td(ep, req);
30984 + } else {
30985 + spin_unlock_irqrestore(&udc->lock, flags);
30986 + return -ENOMEM;
30987 + }
30988 +
30989 + /* Update ep0 state */
30990 + if ((ep_index(ep) == 0))
30991 + udc->ep0_state = DATA_STATE_XMIT;
30992 +
30993 + /* irq handler advances the queue */
30994 + if (req != NULL)
30995 + list_add_tail(&req->queue, &ep->queue);
30996 + spin_unlock_irqrestore(&udc->lock, flags);
30997 +
30998 + return 0;
30999 +}
31000 +
31001 +/* dequeues (cancels, unlinks) an I/O request from an endpoint */
31002 +static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
31003 +{
31004 + struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
31005 + struct fsl_req *req;
31006 + unsigned long flags;
31007 + int ep_num, stopped, ret = 0;
31008 + u32 epctrl;
31009 +
31010 + if (!_ep || !_req)
31011 + return -EINVAL;
31012 +
31013 + spin_lock_irqsave(&ep->udc->lock, flags);
31014 + stopped = ep->stopped;
31015 +
31016 + /* Stop the ep before we deal with the queue */
31017 + ep->stopped = 1;
31018 + ep_num = ep_index(ep);
31019 + epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
31020 + if (ep_is_in(ep))
31021 + epctrl &= ~EPCTRL_TX_ENABLE;
31022 + else
31023 + epctrl &= ~EPCTRL_RX_ENABLE;
31024 + fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
31025 +
31026 + /* make sure it's actually queued on this endpoint */
31027 + list_for_each_entry(req, &ep->queue, queue) {
31028 + if (&req->req == _req)
31029 + break;
31030 + }
31031 + if (&req->req != _req) {
31032 + ret = -EINVAL;
31033 + goto out;
31034 + }
31035 +
31036 + /* The request is in progress, or completed but not dequeued */
31037 + if (ep->queue.next == &req->queue) {
31038 + _req->status = -ECONNRESET;
31039 + fsl_ep_fifo_flush(_ep); /* flush current transfer */
31040 +
31041 + /* The request isn't the last request in this ep queue */
31042 + if (req->queue.next != &ep->queue) {
31043 + struct ep_queue_head *qh;
31044 + struct fsl_req *next_req;
31045 +
31046 + qh = ep->qh;
31047 + next_req = list_entry(req->queue.next, struct fsl_req,
31048 + queue);
31049 +
31050 + /* Point the QH to the first TD of next request */
31051 + fsl_writel((u32) next_req->head, &qh->curr_dtd_ptr);
31052 + }
31053 +
31054 + /* The request hasn't been processed, patch up the TD chain */
31055 + } else {
31056 + struct fsl_req *prev_req;
31057 +
31058 + prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
31059 + fsl_writel(fsl_readl(&req->tail->next_td_ptr),
31060 + &prev_req->tail->next_td_ptr);
31061 +
31062 + }
31063 +
31064 + done(ep, req, -ECONNRESET);
31065 +
31066 + /* Enable EP */
31067 +out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
31068 + if (ep_is_in(ep))
31069 + epctrl |= EPCTRL_TX_ENABLE;
31070 + else
31071 + epctrl |= EPCTRL_RX_ENABLE;
31072 + fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
31073 + ep->stopped = stopped;
31074 +
31075 + spin_unlock_irqrestore(&ep->udc->lock, flags);
31076 + return ret;
31077 +}
31078 +
31079 +/*-------------------------------------------------------------------------*/
31080 +
31081 +/*-----------------------------------------------------------------
31082 + * modify the endpoint halt feature
31083 + * @ep: the non-isochronous endpoint being stalled
31084 + * @value: 1--set halt 0--clear halt
31085 + * Returns zero, or a negative error code.
31086 +*----------------------------------------------------------------*/
31087 +static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
31088 +{
31089 + struct fsl_ep *ep = NULL;
31090 + unsigned long flags = 0;
31091 + int status = -EOPNOTSUPP; /* operation not supported */
31092 + unsigned char ep_dir = 0, ep_num = 0;
31093 + struct fsl_udc *udc = NULL;
31094 +
31095 + ep = container_of(_ep, struct fsl_ep, ep);
31096 + udc = ep->udc;
31097 + if (!_ep || !ep->desc) {
31098 + status = -EINVAL;
31099 + goto out;
31100 + }
31101 +
31102 + if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
31103 + status = -EOPNOTSUPP;
31104 + goto out;
31105 + }
31106 +
31107 + /* Attempt to halt IN ep will fail if any transfer requests
31108 + * are still queue */
31109 + if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
31110 + status = -EAGAIN;
31111 + goto out;
31112 + }
31113 +
31114 + status = 0;
31115 + ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
31116 + ep_num = (unsigned char)(ep_index(ep));
31117 + spin_lock_irqsave(&ep->udc->lock, flags);
31118 + dr_ep_change_stall(ep_num, ep_dir, value);
31119 + spin_unlock_irqrestore(&ep->udc->lock, flags);
31120 +
31121 + if (ep_index(ep) == 0) {
31122 + udc->ep0_state = WAIT_FOR_SETUP;
31123 + udc->ep0_dir = 0;
31124 + }
31125 +out:
31126 + VDBG(" %s %s halt stat %d", ep->ep.name,
31127 + value ? "set" : "clear", status);
31128 +
31129 + return status;
31130 +}
31131 +
31132 +static void fsl_ep_fifo_flush(struct usb_ep *_ep)
31133 +{
31134 + struct fsl_ep *ep;
31135 + int ep_num, ep_dir;
31136 + u32 bits;
31137 + unsigned long timeout;
31138 +#define FSL_UDC_FLUSH_TIMEOUT 1000
31139 +
31140 + if (!_ep) {
31141 + return;
31142 + } else {
31143 + ep = container_of(_ep, struct fsl_ep, ep);
31144 + if (!ep->desc)
31145 + return;
31146 + }
31147 + ep_num = ep_index(ep);
31148 + ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
31149 +
31150 + if (ep_num == 0)
31151 + bits = (1 << 16) | 1;
31152 + else if (ep_dir == USB_SEND)
31153 + bits = 1 << (16 + ep_num);
31154 + else
31155 + bits = 1 << ep_num;
31156 +
31157 + timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
31158 + do {
31159 + fsl_writel(bits, &dr_regs->endptflush);
31160 +
31161 + /* Wait until flush complete */
31162 + while (fsl_readl(&dr_regs->endptflush)) {
31163 + if (time_after(jiffies, timeout)) {
31164 + ERR("ep flush timeout\n");
31165 + return;
31166 + }
31167 + cpu_relax();
31168 + }
31169 + /* See if we need to flush again */
31170 + } while (fsl_readl(&dr_regs->endptstatus) & bits);
31171 +}
31172 +
31173 +static struct usb_ep_ops fsl_ep_ops = {
31174 + .enable = fsl_ep_enable,
31175 + .disable = fsl_ep_disable,
31176 +
31177 + .alloc_request = fsl_alloc_request,
31178 + .free_request = fsl_free_request,
31179 +
31180 + .queue = fsl_ep_queue,
31181 + .dequeue = fsl_ep_dequeue,
31182 +
31183 + .set_halt = fsl_ep_set_halt,
31184 + .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */
31185 +};
31186 +
31187 +/*-------------------------------------------------------------------------
31188 + Gadget Driver Layer Operations
31189 +-------------------------------------------------------------------------*/
31190 +
31191 +/*----------------------------------------------------------------------
31192 + * Get the current frame number (from DR frame_index Reg )
31193 + *----------------------------------------------------------------------*/
31194 +static int fsl_get_frame(struct usb_gadget *gadget)
31195 +{
31196 + return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
31197 +}
31198 +
31199 +/*-----------------------------------------------------------------------
31200 + * Tries to wake up the host connected to this gadget
31201 + -----------------------------------------------------------------------*/
31202 +static int fsl_wakeup(struct usb_gadget *gadget)
31203 +{
31204 + struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
31205 + u32 portsc;
31206 +
31207 + /* Remote wakeup feature not enabled by host */
31208 + if (!udc->remote_wakeup)
31209 + return -ENOTSUPP;
31210 +
31211 + portsc = fsl_readl(&dr_regs->portsc1);
31212 + /* not suspended? */
31213 + if (!(portsc & PORTSCX_PORT_SUSPEND))
31214 + return 0;
31215 + /* trigger force resume */
31216 + portsc |= PORTSCX_PORT_FORCE_RESUME;
31217 + fsl_writel(portsc, &dr_regs->portsc1);
31218 + return 0;
31219 +}
31220 +
31221 +static int can_pullup(struct fsl_udc *udc)
31222 +{
31223 + return udc->driver && udc->softconnect && udc->vbus_active;
31224 +}
31225 +
31226 +/*
31227 + * Notify controller that VBUS is powered, Called by whatever
31228 + * detects VBUS sessions
31229 + * @param gadger gadger pointer
31230 + * @param is_active is active?
31231 + * @return Returns zero on success , or a negative error code
31232 + */
31233 +static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
31234 +{
31235 + struct fsl_udc *udc;
31236 + unsigned long flags;
31237 +
31238 + udc = container_of(gadget, struct fsl_udc, gadget);
31239 + spin_lock_irqsave(&udc->lock, flags);
31240 +
31241 + pr_debug("udc: VBUS %s\n", is_active ? "on" : "off");
31242 + udc->vbus_active = (is_active != 0);
31243 +
31244 + if (can_pullup(udc)) {
31245 + pullup_enable(udc);
31246 + udc_controller->usb_state = USB_STATE_ATTACHED;
31247 + } else {
31248 + pullup_disable(udc);
31249 + udc_controller->usb_state = USB_STATE_NOTATTACHED;
31250 + }
31251 + udc_controller->ep0_state = WAIT_FOR_SETUP;
31252 + udc_controller->ep0_dir = 0;
31253 +
31254 + spin_unlock_irqrestore(&udc->lock, flags);
31255 + return 0;
31256 +}
31257 +
31258 +/* constrain controller's VBUS power usage
31259 + * This call is used by gadget drivers during SET_CONFIGURATION calls,
31260 + * reporting how much power the device may consume. For example, this
31261 + * could affect how quickly batteries are recharged.
31262 + *
31263 + * Returns zero on success, else negative errno.
31264 + */
31265 +static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
31266 +{
31267 +#ifdef CONFIG_USB_OTG
31268 + struct fsl_udc *udc;
31269 +
31270 + udc = container_of(gadget, struct fsl_udc, gadget);
31271 +
31272 + if (udc->transceiver)
31273 + return otg_set_power(udc->transceiver, mA);
31274 +#endif
31275 + return -ENOTSUPP;
31276 +}
31277 +
31278 +/*
31279 + * Change Data+ pullup status
31280 + * this func is used by usb_gadget_connect/disconnet
31281 + */
31282 +static int fsl_pullup(struct usb_gadget *gadget, int is_on)
31283 +{
31284 + struct fsl_udc *udc;
31285 +
31286 + udc = container_of(gadget, struct fsl_udc, gadget);
31287 + udc->softconnect = (is_on != 0);
31288 + if (can_pullup(udc))
31289 + fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
31290 + &dr_regs->usbcmd);
31291 + else
31292 + fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
31293 + &dr_regs->usbcmd);
31294 +
31295 + return 0;
31296 +}
31297 +
31298 +/* defined in usb_gadget.h */
31299 +static struct usb_gadget_ops fsl_gadget_ops = {
31300 + .get_frame = fsl_get_frame,
31301 + .wakeup = fsl_wakeup,
31302 + .vbus_session = fsl_vbus_session,
31303 + .vbus_draw = fsl_vbus_draw,
31304 + .pullup = fsl_pullup,
31305 +};
31306 +
31307 +/* Set protocol stall on ep0, protocol stall will automatically be cleared
31308 + on new transaction */
31309 +static void ep0stall(struct fsl_udc *udc)
31310 +{
31311 + u32 tmp;
31312 +
31313 + /* must set tx and rx to stall at the same time */
31314 + tmp = fsl_readl(&dr_regs->endptctrl[0]);
31315 + tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
31316 + fsl_writel(tmp, &dr_regs->endptctrl[0]);
31317 + udc->ep0_state = WAIT_FOR_SETUP;
31318 + udc->ep0_dir = 0;
31319 +}
31320 +
31321 +/* Prime a status phase for ep0 */
31322 +static int ep0_prime_status(struct fsl_udc *udc, int direction)
31323 +{
31324 + struct fsl_req *req = udc->status_req;
31325 + struct fsl_ep *ep;
31326 + int status = 0;
31327 +
31328 + if (direction == EP_DIR_IN)
31329 + udc->ep0_dir = USB_DIR_IN;
31330 + else
31331 + udc->ep0_dir = USB_DIR_OUT;
31332 +
31333 + ep = &udc->eps[0];
31334 + udc->ep0_state = WAIT_FOR_OUT_STATUS;
31335 +
31336 + req->ep = ep;
31337 + req->req.length = 0;
31338 + req->req.status = -EINPROGRESS;
31339 + req->req.actual = 0;
31340 + req->req.complete = NULL;
31341 + req->dtd_count = 0;
31342 +
31343 + if (fsl_req_to_dtd(req) == 0)
31344 + status = fsl_queue_td(ep, req);
31345 + else
31346 + return -ENOMEM;
31347 +
31348 + if (status)
31349 + ERR("Can't queue ep0 status request \n");
31350 + list_add_tail(&req->queue, &ep->queue);
31351 +
31352 + return status;
31353 +}
31354 +
31355 +static inline int udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
31356 +{
31357 + struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
31358 +
31359 + if (!ep->name)
31360 + return 0;
31361 +
31362 + nuke(ep, -ESHUTDOWN);
31363 +
31364 + return 0;
31365 +}
31366 +
31367 +/*
31368 + * ch9 Set address
31369 + */
31370 +static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
31371 +{
31372 + /* Save the new address to device struct */
31373 + udc->device_address = (u8) value;
31374 + /* Update usb state */
31375 + udc->usb_state = USB_STATE_ADDRESS;
31376 + /* Status phase */
31377 + if (ep0_prime_status(udc, EP_DIR_IN))
31378 + ep0stall(udc);
31379 +}
31380 +
31381 +/*
31382 + * ch9 Get status
31383 + */
31384 +static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
31385 + u16 index, u16 length)
31386 +{
31387 + u16 tmp = 0; /* Status, cpu endian */
31388 +
31389 + struct fsl_req *req;
31390 + struct fsl_ep *ep;
31391 + int status = 0;
31392 +
31393 + ep = &udc->eps[0];
31394 +
31395 + if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
31396 + /* Get device status */
31397 + tmp = 1 << USB_DEVICE_SELF_POWERED;
31398 + tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
31399 + } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
31400 + /* Get interface status */
31401 + /* We don't have interface information in udc driver */
31402 + tmp = 0;
31403 + } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
31404 + /* Get endpoint status */
31405 + struct fsl_ep *target_ep;
31406 +
31407 + target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
31408 +
31409 + /* stall if endpoint doesn't exist */
31410 + if (!target_ep->desc)
31411 + goto stall;
31412 + tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
31413 + << USB_ENDPOINT_HALT;
31414 + }
31415 +
31416 + udc->ep0_dir = USB_DIR_IN;
31417 + /* Borrow the per device status_req */
31418 + req = udc->status_req;
31419 + /* Fill in the reqest structure */
31420 + *((u16 *) req->req.buf) = cpu_to_le16(tmp);
31421 + req->ep = ep;
31422 + req->req.length = 2;
31423 + req->req.status = -EINPROGRESS;
31424 + req->req.actual = 0;
31425 + req->req.complete = NULL;
31426 + req->dtd_count = 0;
31427 +
31428 + /* prime the data phase */
31429 + if ((fsl_req_to_dtd(req) == 0))
31430 + status = fsl_queue_td(ep, req);
31431 + else /* no mem */
31432 + goto stall;
31433 +
31434 + if (status) {
31435 + ERR("Can't respond to getstatus request \n");
31436 + goto stall;
31437 + }
31438 + list_add_tail(&req->queue, &ep->queue);
31439 + udc->ep0_state = DATA_STATE_XMIT;
31440 + return;
31441 +stall:
31442 + ep0stall(udc);
31443 +}
31444 +
31445 +static void ch9setconfig(struct fsl_udc *udc, u16 value, u16 index,
31446 + u16 length)
31447 +{
31448 + pr_debug("udc: 1 calling gadget driver->setup\n");
31449 + udc->ep0_dir = USB_DIR_IN;
31450 + if (udc->driver->setup(&udc->gadget, &udc->local_setup_buff) >= 0) {
31451 + /* gadget layer deal with the status phase */
31452 + udc->usb_state = USB_STATE_CONFIGURED;
31453 + udc->ep0_state = WAIT_FOR_OUT_STATUS;
31454 + pr_debug("udc: ep0_state now WAIT_FOR_OUT_STATUS\n");
31455 + }
31456 +}
31457 +
31458 +static void setup_received_irq(struct fsl_udc *udc,
31459 + struct usb_ctrlrequest *setup)
31460 +{
31461 + u32 tmp;
31462 + u16 ptc = 0; /* port test control */
31463 + int handled = 1; /* set to zero if we do not handle the message,
31464 + and should pass it to the gadget driver */
31465 +
31466 + /*
31467 + * gadget drivers expect the setup pkt to be in wire format,
31468 + * so leave it alone and make local copies of stuff we need.
31469 + */
31470 + u16 wValue = le16_to_cpu(setup->wValue);
31471 + u16 wIndex = le16_to_cpu(setup->wIndex);
31472 + u16 wLength = le16_to_cpu(setup->wLength);
31473 +
31474 +
31475 + pr_debug("udc: request=0x%x\n", setup->bRequest);
31476 +
31477 + udc_reset_ep_queue(udc, 0);
31478 +
31479 + /* We asume setup only occurs on EP0 */
31480 + if (setup->bRequestType & USB_DIR_IN)
31481 + udc->ep0_dir = USB_DIR_IN;
31482 + else
31483 + udc->ep0_dir = USB_DIR_OUT;
31484 +
31485 + if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_CLASS) {
31486 + /* handle class requests */
31487 + switch (setup->bRequest) {
31488 +
31489 + case USB_BULK_RESET_REQUEST:
31490 + udc->ep0_dir = USB_DIR_IN;
31491 + if (udc->driver->setup(&udc->gadget,
31492 + &udc->local_setup_buff) >= 0) {
31493 + udc->ep0_state = WAIT_FOR_SETUP;
31494 + pr_debug("udc: ep0_state now WAIT_FOR_SETUP\n");
31495 + }
31496 + break;
31497 +
31498 + default:
31499 + handled = 0;
31500 + break;
31501 + }
31502 + } else if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
31503 + /* handle standard requests */
31504 + switch (setup->bRequest) {
31505 +
31506 + case USB_REQ_GET_STATUS:
31507 + if ((setup->
31508 + bRequestType & (USB_DIR_IN | USB_TYPE_STANDARD))
31509 + != (USB_DIR_IN | USB_TYPE_STANDARD))
31510 + break;
31511 + ch9getstatus(udc, setup->bRequestType, wValue, wIndex,
31512 + wLength);
31513 + break;
31514 +
31515 + case USB_REQ_SET_ADDRESS:
31516 + if (setup->bRequestType !=
31517 + (USB_DIR_OUT | USB_TYPE_STANDARD |
31518 + USB_RECIP_DEVICE))
31519 + break;
31520 + ch9setaddress(udc, wValue, wIndex, wLength);
31521 + break;
31522 +
31523 + case USB_REQ_SET_CONFIGURATION:
31524 + if (setup->bRequestType !=
31525 + (USB_DIR_OUT | USB_TYPE_STANDARD |
31526 + USB_RECIP_DEVICE))
31527 + break;
31528 + /* gadget layer take over the status phase */
31529 + ch9setconfig(udc, wValue, wIndex, wLength);
31530 + break;
31531 + case USB_REQ_SET_INTERFACE:
31532 + if (setup->bRequestType !=
31533 + (USB_DIR_OUT | USB_TYPE_STANDARD |
31534 + USB_RECIP_INTERFACE))
31535 + break;
31536 + udc->ep0_dir = USB_DIR_IN;
31537 + if (udc->driver->setup(&udc->gadget,
31538 + &udc->local_setup_buff) >= 0)
31539 + /* gadget layer take over the status phase */
31540 + break;
31541 + /* Requests with no data phase */
31542 + case USB_REQ_CLEAR_FEATURE:
31543 + case USB_REQ_SET_FEATURE:
31544 + { /* status transaction */
31545 + int rc = -EOPNOTSUPP;
31546 +
31547 + if ((setup->bRequestType & USB_TYPE_MASK) !=
31548 + USB_TYPE_STANDARD)
31549 + break;
31550 +
31551 + /* we only support set/clear feature for
31552 + * endpoint */
31553 + if (setup->bRequestType == USB_RECIP_ENDPOINT) {
31554 + int dir = (wIndex & 0x0080) ?
31555 + EP_DIR_IN : EP_DIR_OUT;
31556 + int num = (wIndex & 0x000f);
31557 + struct fsl_ep *ep;
31558 +
31559 + if (wValue != 0
31560 + || wLength != 0
31561 + || (num * 2 + dir) > udc->max_ep)
31562 + break;
31563 + ep = &udc->eps[num * 2 + dir];
31564 +
31565 + if (setup->bRequest ==
31566 + USB_REQ_SET_FEATURE) {
31567 + pr_debug("udc: udc: SET_FEATURE"
31568 + " doing set_halt\n");
31569 + rc = fsl_ep_set_halt(&ep-> ep,
31570 + 1);
31571 + } else {
31572 + pr_debug("udc: CLEAR_FEATURE"
31573 + " doing clear_halt\n");
31574 + rc = fsl_ep_set_halt(&ep-> ep,
31575 + 0);
31576 + }
31577 +
31578 + } else if (setup->bRequestType ==
31579 + USB_RECIP_DEVICE) {
31580 + if (setup->bRequest ==
31581 + USB_REQ_SET_FEATURE) {
31582 + ptc = wIndex >> 8;
31583 + rc = 0;
31584 + }
31585 + if (!udc->gadget.is_otg)
31586 + break;
31587 + else if (setup->bRequest ==
31588 + USB_DEVICE_B_HNP_ENABLE)
31589 + udc->gadget.b_hnp_enable = 1;
31590 + else if (setup->bRequest ==
31591 + USB_DEVICE_A_HNP_SUPPORT)
31592 + udc->gadget.a_hnp_support = 1;
31593 + else if (setup->bRequest ==
31594 + USB_DEVICE_A_ALT_HNP_SUPPORT)
31595 + udc->gadget.a_alt_hnp_support =
31596 + 1;
31597 + rc = 0;
31598 + }
31599 + if (rc == 0) {
31600 + /* send status only if
31601 + * fsl_ep_set_halt success */
31602 + if (ep0_prime_status(udc, EP_DIR_IN))
31603 + ep0stall(udc);
31604 + }
31605 + break;
31606 + }
31607 + default:
31608 + handled = 0;
31609 + break;
31610 + }
31611 + } else {
31612 + /* vendor requests */
31613 + handled = 0;
31614 + }
31615 +
31616 + if (!handled) {
31617 + if (udc->driver->setup(&udc->gadget, &udc->local_setup_buff)
31618 + != 0) {
31619 + ep0stall(udc);
31620 + } else if (setup->bRequestType & USB_DIR_IN) {
31621 + udc->ep0_state = DATA_STATE_XMIT;
31622 + pr_debug("udc: ep0_state now DATA_STATE_XMIT\n");
31623 + } else {
31624 + udc->ep0_state = DATA_STATE_RECV;
31625 + pr_debug("udc: ep0_state now DATA_STATE_RECV\n");
31626 + }
31627 + }
31628 +
31629 + if (ptc) {
31630 + tmp =fsl_readl(&dr_regs->portsc1) | ptc << 16;
31631 + fsl_writel(tmp, &dr_regs->portsc1);
31632 + pr_debug("udc: switch to test mode.\n");
31633 + }
31634 +}
31635 +
31636 +/* Process request for Data or Status phase of ep0
31637 + * prime status phase if needed */
31638 +static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
31639 + struct fsl_req *req)
31640 +{
31641 + if (udc->usb_state == USB_STATE_ADDRESS) {
31642 + /* Set the new address */
31643 + u32 new_address = (u32) udc->device_address;
31644 + fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
31645 + &dr_regs->deviceaddr);
31646 + }
31647 +
31648 + done(ep0, req, 0);
31649 +
31650 + switch (udc->ep0_state) {
31651 + case DATA_STATE_XMIT:
31652 + /* receive status phase */
31653 + if (ep0_prime_status(udc, EP_DIR_OUT))
31654 + ep0stall(udc);
31655 + break;
31656 + case DATA_STATE_RECV:
31657 + /* send status phase */
31658 + if (ep0_prime_status(udc, EP_DIR_IN))
31659 + ep0stall(udc);
31660 + break;
31661 + case WAIT_FOR_OUT_STATUS:
31662 + udc->ep0_state = WAIT_FOR_SETUP;
31663 + break;
31664 + case WAIT_FOR_SETUP:
31665 + ERR("Unexpect ep0 packets \n");
31666 + break;
31667 + default:
31668 + ep0stall(udc);
31669 + break;
31670 + }
31671 +}
31672 +
31673 +/* Tripwire mechanism to ensure a setup packet payload is extracted without
31674 + * being corrupted by another incoming setup packet */
31675 +static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
31676 +{
31677 + u32 temp;
31678 + struct ep_queue_head *qh;
31679 + struct fsl_usb2_platform_data *pdata = udc->pdata;
31680 +
31681 + qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
31682 +
31683 + /* Clear bit in ENDPTSETUPSTAT */
31684 + temp = fsl_readl(&dr_regs->endptsetupstat);
31685 + fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
31686 +
31687 + /* while a hazard exists when setup package arrives */
31688 + do {
31689 + /* Set Setup Tripwire */
31690 + temp = fsl_readl(&dr_regs->usbcmd);
31691 + fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
31692 +
31693 + /* Copy the setup packet to local buffer */
31694 + if (pdata->le_setup_buf) {
31695 + u32 *p = (u32 *)buffer_ptr;
31696 + u32 *s = (u32 *)qh->setup_buffer;
31697 +
31698 + /* Convert little endian setup buffer to CPU endian */
31699 + *p++ = le32_to_cpu(*s++);
31700 + *p = le32_to_cpu(*s);
31701 + } else {
31702 + memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
31703 + }
31704 + } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
31705 +
31706 + /* Clear Setup Tripwire */
31707 + temp = fsl_readl(&dr_regs->usbcmd);
31708 + fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
31709 +}
31710 +
31711 +/* process-ep_req(): free the completed Tds for this req */
31712 +static int process_ep_req(struct fsl_udc *udc, int pipe,
31713 + struct fsl_req *curr_req)
31714 +{
31715 + struct ep_td_struct *curr_td;
31716 + int td_complete, actual, remaining_length, j, tmp;
31717 + int status = 0;
31718 + int errors = 0;
31719 + struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
31720 + int direction = pipe % 2;
31721 +
31722 + curr_td = curr_req->head;
31723 + td_complete = 0;
31724 + actual = curr_req->req.length;
31725 +
31726 + for (j = 0; j < curr_req->dtd_count; j++) {
31727 + remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
31728 + & DTD_PACKET_SIZE)
31729 + >> DTD_LENGTH_BIT_POS;
31730 + actual -= remaining_length;
31731 +
31732 + (errors = hc32_to_cpu(curr_td->size_ioc_sts) & DTD_ERROR_MASK);
31733 + if (errors) {
31734 + if (errors & DTD_STATUS_HALTED) {
31735 + ERR("dTD error %08x QH=%d\n", errors, pipe);
31736 + /* Clear the errors and Halt condition */
31737 + tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
31738 + tmp &= ~errors;
31739 + curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
31740 + status = -EPIPE;
31741 + /* FIXME: continue with next queued TD? */
31742 +
31743 + break;
31744 + }
31745 + if (errors & DTD_STATUS_DATA_BUFF_ERR) {
31746 + VDBG("Transfer overflow");
31747 + status = -EPROTO;
31748 + break;
31749 + } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
31750 + VDBG("ISO error");
31751 + status = -EILSEQ;
31752 + break;
31753 + } else
31754 + ERR("Unknown error has occured (0x%x)!\r\n",
31755 + errors);
31756 +
31757 + } else if (hc32_to_cpu(curr_td->size_ioc_sts) &
31758 + DTD_STATUS_ACTIVE) {
31759 + VDBG("Request not complete");
31760 + status = REQ_UNCOMPLETE;
31761 + return status;
31762 + } else if (remaining_length) {
31763 + if (direction) {
31764 + VDBG("Transmit dTD remaining length not zero");
31765 + status = -EPROTO;
31766 + break;
31767 + } else {
31768 + td_complete++;
31769 + break;
31770 + }
31771 + } else {
31772 + td_complete++;
31773 + VDBG("dTD transmitted successful ");
31774 + }
31775 +
31776 + if (j != curr_req->dtd_count - 1)
31777 + curr_td = curr_td->next_td_virt;
31778 + }
31779 +
31780 + if (status)
31781 + return status;
31782 +
31783 + curr_req->req.actual = actual;
31784 +
31785 + return 0;
31786 +}
31787 +
31788 +/* Process a DTD completion interrupt */
31789 +static void dtd_complete_irq(struct fsl_udc *udc)
31790 +{
31791 + u32 bit_pos;
31792 + int i, ep_num, direction, bit_mask, status;
31793 + struct fsl_ep *curr_ep;
31794 + struct fsl_req *curr_req, *temp_req;
31795 +
31796 + /* Clear the bits in the register */
31797 + bit_pos = fsl_readl(&dr_regs->endptcomplete);
31798 + fsl_writel(bit_pos, &dr_regs->endptcomplete);
31799 +
31800 + if (!bit_pos)
31801 + return;
31802 +
31803 + for (i = 0; i < udc->max_ep * 2; i++) {
31804 + ep_num = i >> 1;
31805 + direction = i % 2;
31806 +
31807 + bit_mask = 1 << (ep_num + 16 * direction);
31808 +
31809 + if (!(bit_pos & bit_mask))
31810 + continue;
31811 +
31812 + curr_ep = get_ep_by_pipe(udc, i);
31813 +
31814 + /* If the ep is configured */
31815 + if (curr_ep->name == NULL) {
31816 + WARN("Invalid EP?");
31817 + continue;
31818 + }
31819 +
31820 + /* process the req queue until an uncomplete request */
31821 + list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
31822 + queue) {
31823 + status = process_ep_req(udc, i, curr_req);
31824 +
31825 + VDBG("status of process_ep_req= %d, ep = %d",
31826 + status, ep_num);
31827 + if (status == REQ_UNCOMPLETE)
31828 + break;
31829 + /* write back status to req */
31830 + curr_req->req.status = status;
31831 +
31832 + if (ep_num == 0) {
31833 + ep0_req_complete(udc, curr_ep, curr_req);
31834 + break;
31835 + } else {
31836 + done(curr_ep, curr_req, status);
31837 + }
31838 + }
31839 + }
31840 +}
31841 +
31842 +/* Process a port change interrupt */
31843 +static void port_change_irq(struct fsl_udc *udc)
31844 +{
31845 + u32 speed;
31846 +
31847 + VDBG("portsc=0x%x", fsl_readl(&dr_regs->portsc1) );
31848 + if (udc->bus_reset)
31849 + udc->bus_reset = 0;
31850 +
31851 + /* Bus resetting is finished */
31852 + if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET)) {
31853 + /* Get the speed */
31854 + speed = fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SPEED_MASK;
31855 + switch (speed) {
31856 + case PORTSCX_PORT_SPEED_HIGH:
31857 + udc->gadget.speed = USB_SPEED_HIGH;
31858 + break;
31859 + case PORTSCX_PORT_SPEED_FULL:
31860 + udc->gadget.speed = USB_SPEED_FULL;
31861 + break;
31862 + case PORTSCX_PORT_SPEED_LOW:
31863 + udc->gadget.speed = USB_SPEED_LOW;
31864 + break;
31865 + default:
31866 + udc->gadget.speed = USB_SPEED_UNKNOWN;
31867 + break;
31868 + }
31869 + }
31870 +
31871 + /* Update USB state */
31872 + if (!udc->resume_state)
31873 + udc->usb_state = USB_STATE_DEFAULT;
31874 +}
31875 +
31876 +/* Process suspend interrupt */
31877 +static void suspend_irq(struct fsl_udc *udc)
31878 +{
31879 + udc->resume_state = udc->usb_state;
31880 + udc->usb_state = USB_STATE_SUSPENDED;
31881 +
31882 + /* report suspend to the driver, serial.c does not support this */
31883 + if (udc->driver->suspend)
31884 + udc->driver->suspend(&udc->gadget);
31885 +}
31886 +
31887 +static void bus_resume(struct fsl_udc *udc)
31888 +{
31889 + udc->usb_state = udc->resume_state;
31890 + udc->resume_state = 0;
31891 +
31892 + /* report resume to the driver, serial.c does not support this */
31893 + if (udc->driver->resume)
31894 + udc->driver->resume(&udc->gadget);
31895 +}
31896 +
31897 +/* Clear up all ep queues */
31898 +static int reset_queues(struct fsl_udc *udc)
31899 +{
31900 + u8 pipe;
31901 +
31902 + for (pipe = 0; pipe < udc->max_pipes; pipe++)
31903 + udc_reset_ep_queue(udc, pipe);
31904 +
31905 + /* report disconnect; the driver is already quiesced */
31906 + udc->driver->disconnect(&udc->gadget);
31907 +
31908 + return 0;
31909 +}
31910 +
31911 +/* Process reset interrupt */
31912 +static void reset_irq(struct fsl_udc *udc)
31913 +{
31914 + u32 temp;
31915 + unsigned long timeout;
31916 +
31917 + /* Clear the device address */
31918 + temp = fsl_readl(&dr_regs->deviceaddr);
31919 + fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
31920 +
31921 + udc->device_address = 0;
31922 +
31923 + /* Clear usb state */
31924 + udc->resume_state = 0;
31925 + udc->ep0_dir = 0;
31926 + udc->ep0_state = WAIT_FOR_SETUP;
31927 + udc->remote_wakeup = 0; /* default to 0 on reset */
31928 + udc->gadget.b_hnp_enable = 0;
31929 + udc->gadget.a_hnp_support = 0;
31930 + udc->gadget.a_alt_hnp_support = 0;
31931 +
31932 + /* Clear all the setup token semaphores */
31933 + temp = fsl_readl(&dr_regs->endptsetupstat);
31934 + fsl_writel(temp, &dr_regs->endptsetupstat);
31935 +
31936 + /* Clear all the endpoint complete status bits */
31937 + temp = fsl_readl(&dr_regs->endptcomplete);
31938 + fsl_writel(temp, &dr_regs->endptcomplete);
31939 +
31940 + timeout = jiffies + 100;
31941 + while (fsl_readl(&dr_regs->endpointprime)) {
31942 + /* Wait until all endptprime bits cleared */
31943 + if (time_after(jiffies, timeout)) {
31944 + ERR("Timeout for reset\n");
31945 + break;
31946 + }
31947 + cpu_relax();
31948 + }
31949 +
31950 + /* Write 1s to the flush register */
31951 + fsl_writel(0xffffffff, &dr_regs->endptflush);
31952 +
31953 + if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
31954 + VDBG("Bus reset");
31955 + /* Bus is reseting */
31956 + udc->bus_reset = 1;
31957 + /* Reset all the queues, include XD, dTD, EP queue
31958 + * head and TR Queue */
31959 + reset_queues(udc);
31960 + udc->usb_state = USB_STATE_DEFAULT;
31961 + } else {
31962 + VDBG("Controller reset");
31963 + /* initialize usb hw reg except for regs for EP, not
31964 + * touch usbintr reg */
31965 + dr_controller_setup(udc);
31966 +
31967 + /* Reset all internal used Queues */
31968 + reset_queues(udc);
31969 +
31970 + ep0_setup(udc);
31971 +
31972 + /* Enable DR IRQ reg, Set Run bit, change udc state */
31973 + dr_controller_run(udc);
31974 + udc->usb_state = USB_STATE_ATTACHED;
31975 + }
31976 +}
31977 +
31978 +/*
31979 + * USB device controller interrupt handler
31980 + */
31981 +static irqreturn_t fsl_udc_irq(int irq, void *_udc)
31982 +{
31983 + struct fsl_udc *udc = _udc;
31984 + u32 irq_src;
31985 + irqreturn_t status = IRQ_NONE;
31986 + unsigned long flags;
31987 +
31988 + /* Disable ISR for OTG host mode */
31989 + if (udc->stopped)
31990 + return IRQ_NONE;
31991 + spin_lock_irqsave(&udc->lock, flags);
31992 + irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
31993 + /* Clear notification bits */
31994 + fsl_writel(irq_src, &dr_regs->usbsts);
31995 +
31996 + VDBG("irq_src [0x%8x] portsc=0x%x", irq_src,
31997 + fsl_readl(&dr_regs->portsc1));
31998 +
31999 + /* Need to resume? */
32000 + if (udc->usb_state == USB_STATE_SUSPENDED)
32001 + if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
32002 + bus_resume(udc);
32003 +
32004 + /* USB Interrupt */
32005 + if (irq_src & USB_STS_INT) {
32006 + VDBG("Packet int");
32007 + /* Setup package, we only support ep0 as control ep */
32008 + if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
32009 + tripwire_handler(udc, 0,
32010 + (u8 *) (&udc->local_setup_buff));
32011 + setup_received_irq(udc, &udc->local_setup_buff);
32012 + status = IRQ_HANDLED;
32013 + }
32014 +
32015 + /* completion of dtd */
32016 + if (fsl_readl(&dr_regs->endptcomplete)) {
32017 + dtd_complete_irq(udc);
32018 + status = IRQ_HANDLED;
32019 + }
32020 + }
32021 +
32022 + /* SOF (for ISO transfer) */
32023 + if (irq_src & USB_STS_SOF) {
32024 + status = IRQ_HANDLED;
32025 + }
32026 +
32027 + /* Port Change */
32028 + if (irq_src & USB_STS_PORT_CHANGE) {
32029 + port_change_irq(udc);
32030 + status = IRQ_HANDLED;
32031 + }
32032 +
32033 + /* Reset Received */
32034 + if (irq_src & USB_STS_RESET) {
32035 + reset_irq(udc);
32036 + status = IRQ_HANDLED;
32037 + }
32038 +
32039 + /* Sleep Enable (Suspend) */
32040 + if (irq_src & USB_STS_SUSPEND) {
32041 + suspend_irq(udc);
32042 + status = IRQ_HANDLED;
32043 + }
32044 +
32045 + if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
32046 + VDBG("Error IRQ %x ", irq_src);
32047 + }
32048 +
32049 + spin_unlock_irqrestore(&udc->lock, flags);
32050 + return status;
32051 +}
32052 +
32053 +/*----------------------------------------------------------------*
32054 + * Hook to gadget drivers
32055 + * Called by initialization code of gadget drivers
32056 +*----------------------------------------------------------------*/
32057 +int usb_gadget_register_driver(struct usb_gadget_driver *driver)
32058 +{
32059 + int retval = -ENODEV;
32060 + unsigned long flags = 0;
32061 + struct fsl_udc *udc = udc_controller;
32062 +
32063 + pr_debug("udc: udc=0x%p\n", udc);
32064 +
32065 + if (!udc)
32066 + return -ENODEV;
32067 +
32068 + if (!driver || (driver->speed != USB_SPEED_FULL
32069 + && driver->speed != USB_SPEED_HIGH)
32070 + || !driver->bind || !driver->disconnect
32071 + || !driver->setup)
32072 + return -EINVAL;
32073 +
32074 + if (udc->driver)
32075 + return -EBUSY;
32076 +
32077 + /* lock is needed but whether should use this lock or another */
32078 + spin_lock_irqsave(&udc->lock, flags);
32079 +
32080 + driver->driver.bus = 0;
32081 + udc->softconnect = 1;
32082 + /* hook up the driver */
32083 + udc->driver = driver;
32084 + udc->gadget.dev.driver = &driver->driver;
32085 + spin_unlock_irqrestore(&udc->lock, flags);
32086 +
32087 + /* bind udc driver to gadget driver */
32088 + retval = driver->bind(&udc->gadget);
32089 + if (retval) {
32090 + pr_debug("bind to %s --> %d\n", driver->driver.name, retval);
32091 + udc->gadget.dev.driver = 0;
32092 + udc->driver = 0;
32093 + goto out;
32094 + }
32095 +
32096 + /* Enable DR IRQ reg and Set usbcmd reg Run bit */
32097 + if (udc->transceiver) {
32098 + /* Suspend the controller until OTG enables it */
32099 + udc_suspend(udc);
32100 + pr_debug("udc: suspend udc for OTG auto detect \n");
32101 +
32102 + /* Export udc suspend/resume call to OTG */
32103 + udc->gadget.dev.parent->driver->suspend = fsl_udc_suspend;
32104 + udc->gadget.dev.parent->driver->resume = fsl_udc_resume;
32105 +
32106 + retval = otg_set_peripheral(udc->transceiver, &udc->gadget);
32107 + if (retval < 0) {
32108 + printk(KERN_ERR "can't bind to transceiver\n");
32109 + driver->unbind(&udc->gadget);
32110 + udc->gadget.dev.driver = 0;
32111 + udc->driver = 0;
32112 + return retval;
32113 + }
32114 + } else {
32115 + /* Enable DR IRQ reg and Set usbcmd reg Run bit */
32116 + dr_controller_run(udc);
32117 + udc->usb_state = USB_STATE_ATTACHED;
32118 + udc->ep0_state = WAIT_FOR_SETUP;
32119 + pr_debug("udc: ep0_state now WAIT_FOR_SETUP\n");
32120 + udc->ep0_dir = 0;
32121 + }
32122 +
32123 + printk(KERN_INFO "%s: bind to driver %s \n", udc->gadget.name,
32124 + driver->driver.name);
32125 +
32126 +out:
32127 + return retval;
32128 +}
32129 +EXPORT_SYMBOL(usb_gadget_register_driver);
32130 +
32131 +/* Disconnect from gadget driver */
32132 +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
32133 +{
32134 + struct fsl_ep *loop_ep;
32135 + unsigned long flags;
32136 +
32137 + if (!udc_controller)
32138 + return -ENODEV;
32139 +
32140 + if (!driver || driver != udc_controller->driver || !driver->unbind)
32141 + return -EINVAL;
32142 +
32143 +#ifdef CONFIG_USB_OTG
32144 + if (udc_controller->transceiver)
32145 + (void)otg_set_peripheral(udc_controller->transceiver, 0);
32146 +#endif
32147 +
32148 + /* stop DR, disable intr */
32149 + dr_controller_stop(udc_controller);
32150 +
32151 + /* in fact, no needed */
32152 + udc_controller->usb_state = USB_STATE_ATTACHED;
32153 + udc_controller->ep0_state = WAIT_FOR_SETUP;
32154 + udc_controller->ep0_dir = 0;
32155 +
32156 + /* stand operation */
32157 + spin_lock_irqsave(&udc_controller->lock, flags);
32158 + udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
32159 + nuke(&udc_controller->eps[0], -ESHUTDOWN);
32160 + list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
32161 + ep.ep_list)
32162 + nuke(loop_ep, -ESHUTDOWN);
32163 + spin_unlock_irqrestore(&udc_controller->lock, flags);
32164 +
32165 + /* unbind gadget and unhook driver. */
32166 + driver->unbind(&udc_controller->gadget);
32167 + udc_controller->gadget.dev.driver = 0;
32168 + udc_controller->driver = 0;
32169 +
32170 + printk(KERN_INFO "unregistered gadget '%s'\n", driver->driver.name);
32171 + return 0;
32172 +}
32173 +EXPORT_SYMBOL(usb_gadget_unregister_driver);
32174 +
32175 +/*-------------------------------------------------------------------------
32176 + PROC File System Support
32177 +-------------------------------------------------------------------------*/
32178 +#ifdef CONFIG_USB_GADGET_DEBUG_FILES
32179 +
32180 +#include <linux/seq_file.h>
32181 +
32182 +static const char proc_filename[] = "driver/fsl_usb2_udc";
32183 +
32184 +static int fsl_proc_read(char *page, char **start, off_t off, int count,
32185 + int *eof, void *_dev)
32186 +{
32187 + char *buf = page;
32188 + char *next = buf;
32189 + unsigned size = count;
32190 + unsigned long flags;
32191 + int t, i;
32192 + u32 tmp_reg;
32193 + struct fsl_ep *ep = NULL;
32194 + struct fsl_req *req;
32195 +
32196 + struct fsl_udc *udc = udc_controller;
32197 + if (off != 0)
32198 + return 0;
32199 +
32200 + spin_lock_irqsave(&udc->lock, flags);
32201 +
32202 + /* ------basic driver infomation ---- */
32203 + t = scnprintf(next, size,
32204 + DRIVER_DESC "\n"
32205 + "%s version: %s\n"
32206 + "Gadget driver: %s\n\n",
32207 + driver_name, DRIVER_VERSION,
32208 + udc->driver ? udc->driver->driver.name : "(none)");
32209 + size -= t;
32210 + next += t;
32211 +
32212 + /* ------ DR Registers ----- */
32213 + tmp_reg = fsl_readl(&dr_regs->usbcmd);
32214 + t = scnprintf(next, size,
32215 + "USBCMD reg: 0x%08x\n"
32216 + "\tSetupTW: %d\n"
32217 + "\tRun/Stop: %s\n\n",
32218 + tmp_reg,
32219 + (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
32220 + (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
32221 + size -= t;
32222 + next += t;
32223 +
32224 + tmp_reg = fsl_readl(&dr_regs->usbsts);
32225 + t = scnprintf(next, size,
32226 + "USB Status Reg: 0x%08x\n"
32227 + "\tDr Suspend: %d Reset Received: %d "
32228 + "System Error: %s USB Error Interrupt: %s\n\n",
32229 + tmp_reg,
32230 + (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
32231 + (tmp_reg & USB_STS_RESET) ? 1 : 0,
32232 + (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
32233 + (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
32234 + size -= t;
32235 + next += t;
32236 +
32237 + tmp_reg = fsl_readl(&dr_regs->usbintr);
32238 + t = scnprintf(next, size,
32239 + "USB Interrupt Enable Reg: 0x%08x\n"
32240 + "\tSleep Enable: %d SOF Received Enable: %d "
32241 + "Reset Enable: %d\n"
32242 + "\tSystem Error Enable: %d "
32243 + "Port Change Dectected Enable: %d\n"
32244 + "\tUSB Error Intr Enable: %d USB Intr Enable: %d\n\n",
32245 + tmp_reg,
32246 + (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
32247 + (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
32248 + (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
32249 + (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
32250 + (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
32251 + (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
32252 + (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
32253 + size -= t;
32254 + next += t;
32255 +
32256 + tmp_reg = fsl_readl(&dr_regs->frindex);
32257 + t = scnprintf(next, size,
32258 + "USB Frame Index Reg: Frame Number is 0x%x\n\n",
32259 + (tmp_reg & USB_FRINDEX_MASKS));
32260 + size -= t;
32261 + next += t;
32262 +
32263 + tmp_reg = fsl_readl(&dr_regs->deviceaddr);
32264 + t = scnprintf(next, size,
32265 + "USB Device Address Reg: Device Addr is 0x%x\n\n",
32266 + (tmp_reg & USB_DEVICE_ADDRESS_MASK));
32267 + size -= t;
32268 + next += t;
32269 +
32270 + tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
32271 + t = scnprintf(next, size,
32272 + "USB Endpoint List Address Reg:"
32273 + "Device Addr is 0x%x\n\n",
32274 + (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
32275 + size -= t;
32276 + next += t;
32277 +
32278 + tmp_reg = fsl_readl(&dr_regs->portsc1);
32279 + t = scnprintf(next, size,
32280 + "USB Port Status&Control Reg:\n"
32281 + "\tPort Transceiver Type : %s" "Port Speed: %s \n"
32282 + "\tPHY Low Power Suspend: %s" "Port Reset: %s "
32283 + "Port Suspend Mode: %s \n" "\tOver-current Change: %s "
32284 + "Port Enable/Disable Change: %s\n"
32285 + "\tPort Enabled/Disabled: %s"
32286 + "Current Connect Status: %s\n\n", ( {
32287 + char *s;
32288 + switch (tmp_reg & PORTSCX_PTS_FSLS) {
32289 + case PORTSCX_PTS_UTMI:
32290 + s = "UTMI"; break;
32291 + case PORTSCX_PTS_ULPI:
32292 + s = "ULPI "; break;
32293 + case PORTSCX_PTS_FSLS:
32294 + s = "FS/LS Serial"; break;
32295 + default:
32296 + s = "None"; break;
32297 + }
32298 + s; } ), ( {
32299 + char *s;
32300 + switch (tmp_reg & PORTSCX_PORT_SPEED_UNDEF) {
32301 + case PORTSCX_PORT_SPEED_FULL:
32302 + s = "Full Speed"; break;
32303 + case PORTSCX_PORT_SPEED_LOW:
32304 + s = "Low Speed"; break;
32305 + case PORTSCX_PORT_SPEED_HIGH:
32306 + s = "High Speed"; break;
32307 + default:
32308 + s = "Undefined"; break;
32309 + }
32310 + s;
32311 + } ),
32312 + (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
32313 + "Normal PHY mode" : "Low power mode",
32314 + (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
32315 + "Not in Reset",
32316 + (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
32317 + (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
32318 + "No",
32319 + (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
32320 + "Not change",
32321 + (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
32322 + "Not correct",
32323 + (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
32324 + "Attached" : "Not-Att");
32325 + size -= t;
32326 + next += t;
32327 +
32328 + tmp_reg = fsl_readl(&dr_regs->usbmode);
32329 + t = scnprintf(next, size,
32330 + "USB Mode Reg:" "Controller Mode is : %s\n\n", ( {
32331 + char *s;
32332 + switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
32333 + case USB_MODE_CTRL_MODE_IDLE:
32334 + s = "Idle"; break;
32335 + case USB_MODE_CTRL_MODE_DEVICE:
32336 + s = "Device Controller"; break;
32337 + case USB_MODE_CTRL_MODE_HOST:
32338 + s = "Host Controller"; break;
32339 + default:
32340 + s = "None"; break;
32341 + }
32342 + s;
32343 + } ));
32344 + size -= t;
32345 + next += t;
32346 +
32347 + tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
32348 + t = scnprintf(next, size,
32349 + "Endpoint Setup Status Reg:" "SETUP on ep 0x%x\n\n",
32350 + (tmp_reg & EP_SETUP_STATUS_MASK));
32351 + size -= t;
32352 + next += t;
32353 +
32354 + for (i = 0; i < udc->max_ep / 2; i++) {
32355 + tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
32356 + t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n",
32357 + i, tmp_reg);
32358 + size -= t;
32359 + next += t;
32360 + }
32361 + tmp_reg = fsl_readl(&dr_regs->endpointprime);
32362 + t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n", tmp_reg);
32363 + size -= t;
32364 + next += t;
32365 +
32366 +#ifdef HAVE_SYS_REGS
32367 + tmp_reg = usb_sys_regs->snoop1;
32368 + t = scnprintf(next, size, "\nSnoop1 Reg : = [0x%x]\n\n", tmp_reg);
32369 + size -= t;
32370 + next += t;
32371 +
32372 + tmp_reg = usb_sys_regs->control;
32373 + t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n",
32374 + tmp_reg);
32375 + size -= t;
32376 + next += t;
32377 +#endif
32378 +
32379 + /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
32380 + ep = &udc->eps[0];
32381 + t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n",
32382 + ep->ep.name, ep_maxpacket(ep), ep_index(ep));
32383 + size -= t;
32384 + next += t;
32385 +
32386 + if (list_empty(&ep->queue)) {
32387 + t = scnprintf(next, size, "its req queue is empty\n\n");
32388 + size -= t;
32389 + next += t;
32390 + } else {
32391 + list_for_each_entry(req, &ep->queue, queue) {
32392 + t = scnprintf(next, size,
32393 + "req %p actual 0x%x length 0x%x buf %p\n",
32394 + &req->req, req->req.actual,
32395 + req->req.length, req->req.buf);
32396 + size -= t;
32397 + next += t;
32398 + }
32399 + }
32400 + /* other gadget->eplist ep */
32401 + list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
32402 + if (ep->desc) {
32403 + t = scnprintf(next, size,
32404 + "\nFor %s Maxpkt is 0x%x "
32405 + "index is 0x%x\n",
32406 + ep->ep.name, ep_maxpacket(ep),
32407 + ep_index(ep));
32408 + size -= t;
32409 + next += t;
32410 +
32411 + if (list_empty(&ep->queue)) {
32412 + t = scnprintf(next, size,
32413 + "its req queue is empty\n\n");
32414 + size -= t;
32415 + next += t;
32416 + } else {
32417 + list_for_each_entry(req, &ep->queue, queue) {
32418 + t = scnprintf(next, size,
32419 + "req %p actual 0x%x length"
32420 + "0x%x buf %p\n",
32421 + &req->req, req->req.actual,
32422 + req->req.length, req->req.buf);
32423 + size -= t;
32424 + next += t;
32425 + } /* end for each_entry of ep req */
32426 + } /* end for else */
32427 + } /* end for if(ep->queue) */
32428 + } /* end (ep->desc) */
32429 +
32430 + spin_unlock_irqrestore(&udc->lock, flags);
32431 +
32432 + *eof = 1;
32433 + return count - size;
32434 +}
32435 +
32436 +#define create_proc_file() create_proc_read_entry(proc_filename, \
32437 + 0, NULL, fsl_proc_read, NULL)
32438 +
32439 +#define remove_proc_file() remove_proc_entry(proc_filename, NULL)
32440 +
32441 +#else /* !CONFIG_USB_GADGET_DEBUG_FILES */
32442 +
32443 +#define create_proc_file() do {} while (0)
32444 +#define remove_proc_file() do {} while (0)
32445 +
32446 +#endif /* CONFIG_USB_GADGET_DEBUG_FILES */
32447 +
32448 +/*-------------------------------------------------------------------------*/
32449 +
32450 +/* Release udc structures */
32451 +static void fsl_udc_release(struct device *dev)
32452 +{
32453 + complete(udc_controller->done);
32454 + dma_free_coherent(dev, udc_controller->ep_qh_size,
32455 + udc_controller->ep_qh, udc_controller->ep_qh_dma);
32456 + kfree(udc_controller);
32457 +}
32458 +
32459 +/******************************************************************
32460 + Internal structure setup functions
32461 +*******************************************************************/
32462 +/*------------------------------------------------------------------
32463 + * init resource for globle controller
32464 + * Return the udc handle on success or NULL on failure
32465 + ------------------------------------------------------------------*/
32466 +static struct fsl_udc *__init struct_udc_setup(struct platform_device *pdev)
32467 +{
32468 + struct fsl_udc *udc;
32469 + struct fsl_usb2_platform_data *pdata;
32470 + size_t size;
32471 +
32472 + udc = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
32473 + if (udc == NULL) {
32474 + ERR("malloc udc failed\n");
32475 + return NULL;
32476 + }
32477 +
32478 + pdata = pdev->dev.platform_data;
32479 + udc->phy_mode = pdata->phy_mode; /* DDD FIXME */
32480 +
32481 + /* max_ep_nr is bidirectional ep number, max_ep doubles the number */
32482 + udc->max_ep = pdata->max_ep_nr * 2;
32483 +
32484 + udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL);
32485 + if (!udc->eps) {
32486 + ERR("malloc fsl_ep failed\n");
32487 + goto cleanup;
32488 + }
32489 +
32490 + /* initialized QHs, take care of alignment */
32491 + size = udc->max_ep * sizeof(struct ep_queue_head);
32492 + if (size < QH_ALIGNMENT)
32493 + size = QH_ALIGNMENT;
32494 + else if ((size % QH_ALIGNMENT) != 0) {
32495 + size += QH_ALIGNMENT + 1;
32496 + size &= ~(QH_ALIGNMENT - 1);
32497 + }
32498 + udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
32499 + &udc->ep_qh_dma, GFP_KERNEL);
32500 + if (!udc->ep_qh) {
32501 + ERR("malloc QHs for udc failed\n");
32502 + kfree(udc->eps);
32503 + goto cleanup;
32504 + }
32505 +
32506 + udc->ep_qh_size = size;
32507 +
32508 + /* Initialize ep0 status request structure */
32509 + udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
32510 + struct fsl_req, req);
32511 + /* allocate a small amount of memory to get valid address */
32512 + udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
32513 + udc->status_req->req.dma = virt_to_phys(udc->status_req->req.buf);
32514 +
32515 + udc->resume_state = USB_STATE_NOTATTACHED;
32516 + udc->usb_state = USB_STATE_POWERED;
32517 + udc->ep0_dir = 0;
32518 + udc->remote_wakeup = 0; /* default to 0 on reset */
32519 + spin_lock_init(&udc->lock);
32520 +
32521 + return udc;
32522 +
32523 +cleanup:
32524 + kfree(udc);
32525 + return NULL;
32526 +}
32527 +
32528 +/*----------------------------------------------------------------
32529 + * Setup the fsl_ep struct for eps
32530 + * Link fsl_ep->ep to gadget->ep_list
32531 + * ep0out is not used so do nothing here
32532 + * ep0in should be taken care
32533 + *--------------------------------------------------------------*/
32534 +static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index,
32535 + char *name, int link)
32536 +{
32537 + struct fsl_ep *ep = &udc->eps[index];
32538 +
32539 + ep->udc = udc;
32540 + strcpy(ep->name, name);
32541 + ep->ep.name = ep->name;
32542 +
32543 + ep->ep.ops = &fsl_ep_ops;
32544 + ep->stopped = 0;
32545 +
32546 + /* for ep0: maxP defined in desc
32547 + * for other eps, maxP is set by epautoconfig() called by gadget layer
32548 + */
32549 + ep->ep.maxpacket = (unsigned short) ~0;
32550 +
32551 + /* the queue lists any req for this ep */
32552 + INIT_LIST_HEAD(&ep->queue);
32553 +
32554 + /* gagdet.ep_list used for ep_autoconfig so no ep0 */
32555 + if (link)
32556 + list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
32557 + ep->gadget = &udc->gadget;
32558 + ep->qh = &udc->ep_qh[index];
32559 +
32560 + return 0;
32561 +}
32562 +
32563 +static int board_init(struct platform_device *pdev)
32564 +{
32565 + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
32566 +
32567 + pr_debug("udc: pdev=0x%p pdata=0x%p\n", pdev, pdata);
32568 +
32569 + /*
32570 + * do platform specific init: check the clock, grab/config pins, etc.
32571 + */
32572 + if (pdata->platform_init && pdata->platform_init(pdev) != 0)
32573 + return -EINVAL;
32574 +
32575 + return 0;
32576 +}
32577 +
32578 +/* Driver probe functions */
32579 +
32580 +static int __init fsl_udc_probe(struct platform_device *pdev)
32581 +{
32582 + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
32583 + struct fsl_udc *udc;
32584 + unsigned int i;
32585 + struct otg_transceiver *transceiver = NULL;
32586 + int status = -ENODEV;
32587 + u32 id;
32588 + int irq_number;
32589 + u64 rsrc_start, rsrc_len;
32590 + int ret = -ENODEV;
32591 +
32592 + pr_debug("udc: pdev=0x%p pdata=0x%p\n", pdev, pdata);
32593 +
32594 + if (board_init(pdev) != 0)
32595 + return -EINVAL;
32596 +
32597 + /* Initialize the udc structure including QH member and other member */
32598 + udc = (struct fsl_udc *) struct_udc_setup(pdev);
32599 + udc_controller = udc;
32600 +
32601 + if (!udc) {
32602 + ERR("udc is NULL \n");
32603 + return -ENOMEM;
32604 + }
32605 + dev_set_drvdata(&pdev->dev, udc);
32606 + pr_debug("udc_controller=0x%p", udc_controller);
32607 +
32608 + udc->pdata = pdata;
32609 + udc->xcvr_type = pdata->xcvr_type;
32610 +
32611 +#ifdef CONFIG_USB_OTG
32612 + udc->transceiver = otg_get_transceiver();
32613 + pr_debug("udc: otg_get_transceiver returns 0x%p", udc->transceiver);
32614 +#endif
32615 +
32616 + if (pdev->resource[1].flags != IORESOURCE_IRQ)
32617 + return -ENODEV;
32618 +
32619 + rsrc_start = pdev->resource[0].start;
32620 + rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1;
32621 +
32622 + pr_debug(" start=0x%ux end=0x%ux\n",
32623 + pdev->resource[0].start, pdev->resource[0].end);
32624 + pr_debug("rsrc_start=0x%llx rsrc_len=0x%llx\n", rsrc_start, rsrc_len);
32625 +
32626 + dr_regs = (struct fsl_usb_device_regs *)pdata->regs;
32627 +
32628 + pr_debug("udc: pdate=0x%p dr_regs=0x%p\n", pdata, dr_regs);
32629 + pr_debug("udc: hci_version=0x%x\n", dr_regs->hciversion);
32630 + pr_debug("udc: otgsc at 0x%p\n", &dr_regs->otgsc);
32631 +
32632 + id = fsl_readl(&dr_regs->id);
32633 + printk(KERN_INFO "FSL2 USBOTG h/w ID=0x%x revision=0x%x\n",
32634 + id & 0x3f, id >> 16);
32635 +
32636 + /* USB OTG module IRQ */
32637 + irq_number = platform_get_irq(pdev, 0);
32638 + if (irq_number > 128) {
32639 + status = request_irq(irq_number, fsl_udc_irq, IRQF_SHARED,
32640 + driver_name, udc);
32641 + if (status) {
32642 + ERR("can't get irq %d, err=%d\n", irq_number, status);
32643 + goto err2;
32644 + }
32645 + } else {
32646 + status = -ENODEV;
32647 + goto err2;
32648 + }
32649 +
32650 + if (!udc->transceiver) {
32651 + /* initialize usb hw reg except for regs for EP,
32652 + * leave usbintr reg untouched*/
32653 + dr_controller_setup(udc);
32654 + }
32655 +
32656 + /* here comes the stand operations for probe
32657 + * set the fsl_udc->gadget.xxx
32658 + */
32659 + udc->gadget.ops = &fsl_gadget_ops;
32660 + udc->gadget.is_dualspeed = 1;
32661 +
32662 + /* gadget.ep0 is a pointer */
32663 + udc->gadget.ep0 = &udc->eps[0].ep;
32664 + INIT_LIST_HEAD(&udc->gadget.ep_list);
32665 + udc->gadget.speed = USB_SPEED_UNKNOWN;
32666 + udc->gadget.name = driver_name;
32667 +
32668 + /* Setup gadget.dev and register with kernel */
32669 + strcpy(udc->gadget.dev.bus_id, "gadget");
32670 + udc->gadget.dev.release = fsl_udc_release;
32671 + udc->gadget.dev.parent = &pdev->dev;
32672 +
32673 + ret = device_register(&udc->gadget.dev);
32674 + if (ret < 0)
32675 + goto err3;
32676 +
32677 + if (udc->transceiver)
32678 + udc->gadget.is_otg = 1;
32679 +
32680 + /* setup QH and epctrl for ep0 */
32681 + ep0_setup(udc);
32682 +
32683 + /* setup udc->eps[] for ep0 */
32684 + struct_ep_setup(udc_controller, 0, "ep0", 0);
32685 + /* for ep0: the desc defined here;
32686 + * for other eps, gadget layer called ep_enable with defined desc
32687 + */
32688 + udc->eps[0].desc = &fsl_ep0_desc;
32689 + udc->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
32690 +
32691 + /* setup the udc->eps[] for non-control endpoints and link
32692 + * to gadget.ep_list */
32693 + for (i = 1; i < (int)(udc->max_ep / 2); i++) {
32694 + char name[14];
32695 +
32696 + sprintf(name, "ep%dout", i);
32697 + struct_ep_setup(udc, i * 2, name, 1);
32698 + sprintf(name, "ep%din", i);
32699 + struct_ep_setup(udc, i * 2 + 1, name, 1);
32700 + }
32701 +
32702 + /* use dma_pool for TD management */
32703 + udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
32704 + sizeof(struct ep_td_struct),
32705 + DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
32706 + if (udc->td_pool == NULL) {
32707 + ret = -ENOMEM;
32708 + goto err4;
32709 + }
32710 +
32711 + create_proc_file();
32712 + return 0;
32713 +
32714 +err4:
32715 + device_unregister(&udc_controller->gadget.dev);
32716 +err3:
32717 + free_irq(udc_controller->irq, udc_controller);
32718 +err2:
32719 + kfree(udc);
32720 + if (transceiver)
32721 + put_device(transceiver->dev);
32722 + release_mem_region(pdev->resource[0].start,
32723 + pdev->resource[0].end - pdev->resource[0].start + 1);
32724 + return status;
32725 +
32726 +}
32727 +
32728 +/* Driver removal functions
32729 + * Free resources
32730 + * Finish pending transaction
32731 + */
32732 +static int __exit fsl_udc_remove(struct platform_device *pdev)
32733 +{
32734 + struct device *dev = &pdev->dev;
32735 + struct fsl_udc *udc = (struct fsl_udc *)dev_get_drvdata(dev);
32736 + struct fsl_usb2_platform_data *pdata;
32737 + int irq_number;
32738 +
32739 + DECLARE_COMPLETION(done);
32740 +
32741 + pdata = pdev->dev.platform_data;
32742 +
32743 + if (!udc)
32744 + return -ENODEV;
32745 +
32746 + udc->done = &done;
32747 +
32748 + /* DR has been stopped in usb_gadget_unregister_driver() */
32749 +
32750 + if (udc->transceiver) {
32751 + put_device(udc->transceiver->dev);
32752 + udc->transceiver = NULL;
32753 + }
32754 +
32755 + /* remove proc */
32756 + remove_proc_file();
32757 +
32758 + /* free irq */
32759 + irq_number = udc->irq;
32760 + free_irq(pdev->resource[1].start, udc);
32761 + udc->irq = 0;
32762 +
32763 + /* Free allocated memory */
32764 + kfree(udc->status_req->req.buf);
32765 + kfree(udc->status_req);
32766 + kfree(udc_controller->eps);
32767 +
32768 + dma_pool_destroy(udc_controller->td_pool);
32769 + /* deinitlaize all ep: strcut */
32770 + /* deinitialize ep0: reg and QH */
32771 +
32772 + device_unregister(&udc->gadget.dev);
32773 + /* free udc --wait for the release() finished */
32774 + wait_for_completion(&done);
32775 +
32776 + /*
32777 + * do platform specific un-initialization:
32778 + * release iomux pins, etc.
32779 + */
32780 + if (pdata->platform_uninit)
32781 + pdata->platform_uninit(pdev);
32782 +
32783 + return 0;
32784 +}
32785 +
32786 +static int udc_suspend(struct fsl_udc *udc)
32787 +{
32788 + udc->stopped = 1;
32789 + return 0;
32790 +}
32791 +
32792 +/*
32793 + * Modify Power management attributes
32794 + * Used by OTG statemachine to disable gadget temporarily
32795 + * Here we stop the DR controller and disable the irq
32796 + * @param dev device controller pointer
32797 + * @param state current state
32798 + * @return The function returns 0 on success or -1 if failed
32799 + */
32800 +static int fsl_udc_suspend(struct device *dev, pm_message_t state)
32801 +{
32802 + struct fsl_udc *udc = (struct fsl_udc *)dev_get_drvdata(dev);
32803 + pr_debug("udc: Suspend. state=%d\n", state.event);
32804 + return udc_suspend(udc);
32805 +}
32806 +
32807 +static int udc_resume(struct fsl_udc *udc)
32808 +{
32809 + /*Enable DR irq reg and set controller Run */
32810 + if (udc->stopped) {
32811 + dr_controller_setup(udc);
32812 + dr_controller_run(udc);
32813 + }
32814 + udc->usb_state = USB_STATE_ATTACHED;
32815 + udc->ep0_state = WAIT_FOR_SETUP;
32816 + udc->ep0_dir = 0;
32817 + return 0;
32818 +}
32819 +
32820 +/*
32821 + * Invoked on USB resume. May be called in_interrupt.
32822 + * Here we start the DR controller and enable the irq
32823 + * @param dev device controller pointer
32824 + * @return The function returns 0 on success or -1 if failed
32825 + */
32826 +static int fsl_udc_resume(struct device *dev)
32827 +{
32828 + struct fsl_udc *udc = (struct fsl_udc *)dev_get_drvdata(dev);
32829 + pr_debug("udc: Resume dev=0x%p udc=0x%p\n", dev, udc);
32830 +
32831 + return udc_resume(udc);
32832 +}
32833 +
32834 +/*-------------------------------------------------------------------------
32835 + Register entry point for the peripheral controller driver
32836 +--------------------------------------------------------------------------*/
32837 +static struct platform_driver udc_driver = {
32838 + .probe = fsl_udc_probe,
32839 + .remove = __exit_p(fsl_udc_remove),
32840 + .driver = {
32841 + .name = (char *)driver_name,
32842 + .owner = THIS_MODULE,
32843 + },
32844 +};
32845 +
32846 +static int __init udc_init(void)
32847 +{
32848 + printk(KERN_INFO "%s version %s init \n", driver_desc, DRIVER_VERSION);
32849 + return platform_driver_register(&udc_driver);
32850 +}
32851 +
32852 +module_init(udc_init);
32853 +
32854 +static void __exit udc_exit(void)
32855 +{
32856 + platform_driver_unregister(&udc_driver);
32857 + printk(KERN_INFO "%s unregistered \n", driver_desc);
32858 +}
32859 +
32860 +module_exit(udc_exit);
32861 +
32862 +MODULE_DESCRIPTION(DRIVER_DESC);
32863 +MODULE_AUTHOR(DRIVER_AUTHOR);
32864 +MODULE_LICENSE("GPL");
32865 --- /dev/null
32866 +++ b/drivers/usb/host/ehci-arc.c
32867 @@ -0,0 +1,436 @@
32868 +/*
32869 + * drivers/usb/host/ehci-arc.c
32870 + *
32871 + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
32872 + */
32873 +
32874 +/*
32875 + * The code contained herein is licensed under the GNU General Public
32876 + * License. You may obtain a copy of the GNU General Public License
32877 + * Version 2 or later at the following locations:
32878 + *
32879 + * http://www.opensource.org/licenses/gpl-license.html
32880 + * http://www.gnu.org/copyleft/gpl.html
32881 + */
32882 +
32883 +/* Note: this file is #included by ehci-hcd.c */
32884 +
32885 +#include <linux/platform_device.h>
32886 +#include <linux/usb/fsl_usb2.h>
32887 +#include <linux/fsl_devices.h>
32888 +#include <linux/usb/otg.h>
32889 +
32890 +#include "ehci-fsl.h"
32891 +
32892 +
32893 +/* FIXME: Power Managment is un-ported so temporarily disable it */
32894 +#undef CONFIG_PM
32895 +
32896 +/* PCI-based HCs are common, but plenty of non-PCI HCs are used too */
32897 +
32898 +/* configure so an HC device and id are always provided */
32899 +/* always called with process context; sleeping is OK */
32900 +
32901 +/**
32902 + * usb_hcd_fsl_probe - initialize FSL-based HCDs
32903 + * @drvier: Driver to be used for this HCD
32904 + * @pdev: USB Host Controller being probed
32905 + * Context: !in_interrupt()
32906 + *
32907 + * Allocates basic resources for this USB host controller.
32908 + *
32909 + */
32910 +static int usb_hcd_fsl_probe(const struct hc_driver *driver,
32911 + struct platform_device *pdev)
32912 +{
32913 + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
32914 + struct usb_hcd *hcd;
32915 + struct resource *res;
32916 + int irq;
32917 + int retval;
32918 +
32919 + pr_debug("initializing FSL-SOC USB Controller\n");
32920 +
32921 + /* Need platform data for setup */
32922 + if (!pdata) {
32923 + dev_err(&pdev->dev,
32924 + "No platform data for %s.\n", pdev->dev.bus_id);
32925 + return -ENODEV;
32926 + }
32927 +
32928 + retval = fsl_platform_verify(pdev);
32929 + if (retval)
32930 + return retval;
32931 +
32932 + /*
32933 + * do platform specific init: check the clock, grab/config pins, etc.
32934 + */
32935 + if (pdata->platform_init && pdata->platform_init(pdev)) {
32936 + retval = -ENODEV;
32937 + goto err1;
32938 + }
32939 +
32940 + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
32941 + if (!res) {
32942 + dev_err(&pdev->dev,
32943 + "Found HC with no IRQ. Check %s setup!\n",
32944 + pdev->dev.bus_id);
32945 + return -ENODEV;
32946 + }
32947 + irq = res->start;
32948 +
32949 + fsl_platform_set_vbus_power(pdev, 1);
32950 +
32951 + hcd = usb_create_hcd(driver, &pdev->dev, pdev->dev.bus_id);
32952 + if (!hcd) {
32953 + retval = -ENOMEM;
32954 + goto err1;
32955 + }
32956 +
32957 + if (pdata->regs) {
32958 + pr_debug("REGS: using pdata->regs (0x%p)\n", pdata->regs);
32959 + hcd->regs = pdata->regs;
32960 + hcd->rsrc_start = pdata->r_start;
32961 + hcd->rsrc_len = pdata->r_len;
32962 + } else {
32963 + pr_debug("REGS: NO pdata->regs\n");
32964 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
32965 + if (!res) {
32966 + dev_err(&pdev->dev, "Found HC with no register addr. "
32967 + "Check %s setup!\n", pdev->dev.bus_id);
32968 + retval = -ENODEV;
32969 + goto err2;
32970 + }
32971 + hcd->rsrc_start = res->start;
32972 + hcd->rsrc_len = res->end - res->start + 1;
32973 +
32974 + /*
32975 + printk("DDD %s(): rsrc_start=0x%llx rsrc_len=0x%llx "
32976 + "pdata=0x%p\n", __FUNCTION__,
32977 + hcd->rsrc_start, hcd->rsrc_len, pdata);
32978 + */
32979 +
32980 + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
32981 + driver->description)) {
32982 + dev_dbg(&pdev->dev, "request_mem_region failed\n");
32983 + retval = -EBUSY;
32984 + goto err2;
32985 + }
32986 + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
32987 +
32988 + if (hcd->regs == NULL) {
32989 + dev_dbg(&pdev->dev, "error mapping memory\n");
32990 + retval = -EFAULT;
32991 + goto err3;
32992 + }
32993 + }
32994 + hcd->power_budget = pdata->power_budget;
32995 +
32996 + /* DDD
32997 + * the following must be done by this point, otherwise the OTG
32998 + * host port doesn't make it thru initializtion.
32999 + * ehci_halt(), called by ehci_fsl_setup() returns -ETIMEDOUT
33000 + */
33001 + fsl_platform_set_host_mode(hcd);
33002 +
33003 + retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
33004 + if (retval != 0)
33005 + goto err4;
33006 +
33007 +#if defined(CONFIG_USB_OTG)
33008 + if (pdata->does_otg) {
33009 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
33010 +
33011 + ehci->transceiver = otg_get_transceiver();
33012 +
33013 + if (ehci->transceiver) {
33014 + retval = otg_set_host(ehci->transceiver,
33015 + &ehci_to_hcd(ehci)->self);
33016 + if (retval) {
33017 + if (ehci->transceiver)
33018 + put_device(ehci->transceiver->dev);
33019 + goto err3;
33020 + }
33021 + } else {
33022 + printk(KERN_ERR "can't find transceiver\n");
33023 + retval = -ENODEV;
33024 + goto err3;
33025 + }
33026 + }
33027 +#endif
33028 +
33029 + return retval;
33030 +
33031 +err4:
33032 + /* DDD only if we did the iomap() iounmap(hcd->regs); */
33033 +err3:
33034 + /* DDD only if we did a request_
33035 + * release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
33036 + */
33037 +err2:
33038 + usb_put_hcd(hcd);
33039 +err1:
33040 + dev_err(&pdev->dev, "init %s fail, %d\n", pdev->dev.bus_id, retval);
33041 + if (pdata->platform_uninit)
33042 + pdata->platform_uninit(pdev);
33043 + return retval;
33044 +}
33045 +
33046 +/* may be called without controller electrically present */
33047 +/* may be called with controller, bus, and devices active */
33048 +
33049 +/**
33050 + * usb_hcd_fsl_remove - shutdown processing for FSL-based HCDs
33051 + * @dev: USB Host Controller being removed
33052 + * Context: !in_interrupt()
33053 + *
33054 + * Reverses the effect of usb_hcd_fsl_probe().
33055 + *
33056 + */
33057 +static void usb_hcd_fsl_remove(struct usb_hcd *hcd,
33058 + struct platform_device *pdev)
33059 +{
33060 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
33061 + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
33062 +
33063 + /* DDD shouldn't we turn off the power here? */
33064 + fsl_platform_set_vbus_power(pdev, 0);
33065 +
33066 + usb_remove_hcd(hcd);
33067 +
33068 + if (ehci->transceiver) {
33069 + (void)otg_set_host(ehci->transceiver, 0);
33070 + put_device(ehci->transceiver->dev);
33071 + }
33072 + usb_put_hcd(hcd);
33073 +
33074 + /*
33075 + * do platform specific un-initialization:
33076 + * release iomux pins, etc.
33077 + */
33078 + if (pdata->platform_uninit)
33079 + pdata->platform_uninit(pdev);
33080 +}
33081 +
33082 +/* called after powerup, by probe or system-pm "wakeup" */
33083 +static int ehci_fsl_reinit(struct ehci_hcd *ehci)
33084 +{
33085 + fsl_platform_usb_setup(ehci_to_hcd(ehci));
33086 + ehci_port_power(ehci, 0);
33087 +
33088 + return 0;
33089 +}
33090 +
33091 +/* called during probe() after chip reset completes */
33092 +static int ehci_fsl_setup(struct usb_hcd *hcd)
33093 +{
33094 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
33095 + int retval;
33096 + struct fsl_usb2_platform_data *pdata;
33097 + pdata = hcd->self.controller-> platform_data;
33098 +
33099 + ehci->big_endian_desc = pdata->big_endian_desc;
33100 + ehci->big_endian_mmio = pdata->big_endian_mmio;
33101 +
33102 + /* EHCI registers start at offset 0x100 */
33103 + ehci->caps = hcd->regs + 0x100;
33104 + ehci->regs = hcd->regs + 0x100 +
33105 + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
33106 +
33107 + pr_debug("%s(): ehci->caps=0x%p ehci->regs=0x%p\n", __FUNCTION__,
33108 + ehci->caps, ehci->regs);
33109 +
33110 + dbg_hcs_params(ehci, "reset");
33111 + dbg_hcc_params(ehci, "reset");
33112 +
33113 + /* cache this readonly data; minimize chip reads */
33114 + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
33115 +
33116 + retval = ehci_halt(ehci);
33117 + if (retval)
33118 + return retval;
33119 +
33120 + /* data structure init */
33121 + retval = ehci_init(hcd);
33122 + if (retval)
33123 + return retval;
33124 +
33125 + ehci->is_tdi_rh_tt = 1;
33126 +
33127 + ehci->sbrn = 0x20;
33128 +
33129 + ehci_reset(ehci);
33130 +
33131 + retval = ehci_fsl_reinit(ehci);
33132 + return retval;
33133 +}
33134 +
33135 +static const struct hc_driver ehci_fsl_hc_driver = {
33136 + .description = hcd_name,
33137 + .product_desc = "Freescale On-Chip EHCI Host Controller",
33138 + .hcd_priv_size = sizeof(struct ehci_hcd),
33139 +
33140 + /*
33141 + * generic hardware linkage
33142 + */
33143 + .irq = ehci_irq,
33144 + .flags = FSL_PLATFORM_HC_FLAGS,
33145 +
33146 + /*
33147 + * basic lifecycle operations
33148 + */
33149 + .reset = ehci_fsl_setup,
33150 + .start = ehci_run,
33151 + .stop = ehci_stop,
33152 + .shutdown = ehci_shutdown,
33153 +
33154 + /*
33155 + * managing i/o requests and associated device resources
33156 + */
33157 + .urb_enqueue = ehci_urb_enqueue,
33158 + .urb_dequeue = ehci_urb_dequeue,
33159 + .endpoint_disable = ehci_endpoint_disable,
33160 +
33161 + /*
33162 + * scheduling support
33163 + */
33164 + .get_frame_number = ehci_get_frame,
33165 +
33166 + /*
33167 + * root hub support
33168 + */
33169 + .hub_status_data = ehci_hub_status_data,
33170 + .hub_control = ehci_hub_control,
33171 + .bus_suspend = ehci_bus_suspend,
33172 + .bus_resume = ehci_bus_resume,
33173 +};
33174 +
33175 +#ifdef CONFIG_USB_OTG
33176 +/*
33177 + * Holding pen for all the EHCI registers except port_status,
33178 + * which is a zero element array and hence takes no space.
33179 + * The port_status register is saved in usb_ehci_portsc.
33180 + */
33181 +volatile static struct ehci_regs usb_ehci_regs;
33182 +static u32 usb_ehci_portsc;
33183 +
33184 +/* suspend/resume, section 4.3 */
33185 +
33186 +/* These routines rely on the bus (pci, platform, etc)
33187 + * to handle powerdown and wakeup, and currently also on
33188 + * transceivers that don't need any software attention to set up
33189 + * the right sort of wakeup.
33190 + *
33191 + * They're also used for turning on/off the port when doing OTG.
33192 + */
33193 +static int ehci_fsl_drv_suspend(struct platform_device *pdev,
33194 + pm_message_t message)
33195 +{
33196 + struct usb_hcd *hcd = platform_get_drvdata(pdev);
33197 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
33198 + u32 tmp;
33199 +
33200 + pr_debug("%s pdev=0x%p ehci=0x%p hcd=0x%p\n",
33201 + __FUNCTION__, pdev, ehci, hcd);
33202 + pr_debug("%s ehci->regs=0x%p hcd->regs=0x%p hcd->state=%d\n",
33203 + __FUNCTION__, ehci->regs, hcd->regs, hcd->state);
33204 +
33205 + hcd->state = HC_STATE_SUSPENDED;
33206 + pdev->dev.power.power_state = PMSG_SUSPEND;
33207 +
33208 + if (hcd->driver->suspend)
33209 + return hcd->driver->suspend(hcd, message);
33210 +
33211 + /* ignore non-host interrupts */
33212 + clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
33213 +
33214 + tmp = ehci_readl(ehci, &ehci->regs->command);
33215 + tmp &= ~CMD_RUN;
33216 + ehci_writel(ehci, tmp, &ehci->regs->command);
33217 +
33218 + memcpy((void *)&usb_ehci_regs, ehci->regs, sizeof(struct ehci_regs));
33219 + usb_ehci_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
33220 +
33221 + /* clear the W1C bits */
33222 + usb_ehci_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS);
33223 +
33224 + fsl_platform_set_vbus_power(pdev, 0);
33225 + /* clear PP to cut power to the port */
33226 + tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
33227 + tmp &= ~PORT_POWER;
33228 + ehci_writel(ehci, tmp, &ehci->regs->port_status[0]);
33229 +
33230 + return 0;
33231 +}
33232 +
33233 +static int ehci_fsl_drv_resume(struct platform_device *pdev)
33234 +{
33235 + struct usb_hcd *hcd = platform_get_drvdata(pdev);
33236 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
33237 + u32 tmp;
33238 + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
33239 +
33240 + pr_debug("%s pdev=0x%p pdata=0x%p ehci=0x%p hcd=0x%p\n",
33241 + __FUNCTION__, pdev, pdata, ehci, hcd);
33242 +
33243 + pr_debug("%s ehci->regs=0x%p hcd->regs=0x%p\n",
33244 + __FUNCTION__, ehci->regs, hcd->regs);
33245 +
33246 + memcpy(ehci->regs, (void *)&usb_ehci_regs, sizeof(struct ehci_regs));
33247 +
33248 + tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
33249 + ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE);
33250 + pr_debug("tmp %08x set usbmode %08x\n", tmp,
33251 + ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE));
33252 +
33253 + ehci_writel(ehci, usb_ehci_portsc, &ehci->regs->port_status[0]);
33254 + pr_debug("set portsc %08x %08x\n", usb_ehci_portsc,
33255 + ehci_readl(ehci, &ehci->regs->port_status[0]));
33256 +
33257 + set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
33258 + hcd->state = HC_STATE_RUNNING;
33259 + pdev->dev.power.power_state = PMSG_ON;
33260 +
33261 + tmp = ehci_readl(ehci, &ehci->regs->command);
33262 + tmp |= CMD_RUN;
33263 + ehci_writel(ehci, tmp, &ehci->regs->command);
33264 +
33265 + fsl_platform_set_vbus_power(pdev, 1);
33266 +
33267 + usb_hcd_resume_root_hub(hcd);
33268 +
33269 + return 0;
33270 +}
33271 +#endif /* CONFIG_USB_OTG */
33272 +
33273 +static int ehci_fsl_drv_probe(struct platform_device *pdev)
33274 +{
33275 + if (usb_disabled())
33276 + return -ENODEV;
33277 +
33278 + return usb_hcd_fsl_probe(&ehci_fsl_hc_driver, pdev);
33279 +}
33280 +
33281 +static int ehci_fsl_drv_remove(struct platform_device *pdev)
33282 +{
33283 + struct usb_hcd *hcd = platform_get_drvdata(pdev);
33284 +
33285 + usb_hcd_fsl_remove(hcd, pdev);
33286 +
33287 + return 0;
33288 +}
33289 +
33290 +MODULE_ALIAS("fsl-ehci");
33291 +
33292 +static struct platform_driver ehci_fsl_driver = {
33293 + .probe = ehci_fsl_drv_probe,
33294 + .remove = ehci_fsl_drv_remove,
33295 + .shutdown = usb_hcd_platform_shutdown,
33296 +#ifdef CONFIG_USB_OTG
33297 + .suspend = ehci_fsl_drv_suspend,
33298 + .resume = ehci_fsl_drv_resume,
33299 +#endif
33300 + .driver = {
33301 + .name = "fsl-ehci",
33302 + },
33303 +};
33304 --- a/drivers/usb/host/ehci-fsl.h
33305 +++ b/drivers/usb/host/ehci-fsl.h
33306 @@ -18,6 +18,8 @@
33307 #ifndef _EHCI_FSL_H
33308 #define _EHCI_FSL_H
33309
33310 +#include <linux/usb/fsl_xcvr.h>
33311 +
33312 /* offsets for the non-ehci registers in the FSL SOC USB controller */
33313 #define FSL_SOC_USB_ULPIVP 0x170
33314 #define FSL_SOC_USB_PORTSC1 0x184
33315 @@ -34,5 +36,29 @@
33316 #define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */
33317 #define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
33318 #define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
33319 -#define SNOOP_SIZE_2GB 0x1e
33320 +
33321 +#ifdef CONFIG_MPC834x
33322 +#include <sysdev/fsl_usb.h>
33323 +#endif
33324 +
33325 +#ifdef CONFIG_ARCH_MX3
33326 +#include <asm/arch/mx31_usb.h>
33327 +#endif
33328 +
33329 +#ifdef CONFIG_ARCH_MX27
33330 +#include <asm/arch/mx27_usb.h>
33331 +#endif
33332 +
33333 +#ifdef CONFIG_M54455
33334 +#include <asm-m68k/mcf5445x_usb.h>
33335 +#endif
33336 +
33337 +
33338 +static void fsl_platform_set_vbus_power(struct platform_device *pdev, int on)
33339 +{
33340 + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
33341 +
33342 + if (pdata->xcvr_ops && pdata->xcvr_ops->set_vbus_power)
33343 + pdata->xcvr_ops->set_vbus_power(pdata, on);
33344 +}
33345 #endif /* _EHCI_FSL_H */
33346 --- a/drivers/usb/host/ehci.h
33347 +++ b/drivers/usb/host/ehci.h
33348 @@ -122,6 +122,12 @@ struct ehci_hcd { /* one per controlle
33349
33350 u8 sbrn; /* packed release number */
33351
33352 + /*
33353 + * OTG controllers and transceivers need software interaction;
33354 + * other external transceivers should be software-transparent
33355 + */
33356 + struct otg_transceiver *transceiver;
33357 +
33358 /* irq statistics */
33359 #ifdef EHCI_STATS
33360 struct ehci_stats stats;
33361 @@ -753,6 +759,22 @@ ehci_port_speed(struct ehci_hcd *ehci, u
33362 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
33363 #endif
33364
33365 +#if defined(CONFIG_COLDFIRE)
33366 +/*
33367 + * Sorry, include/asm-m68k/io.h is messed up. It will give you a
33368 + * BE readl or a LE readl depending on whether or not CONFIG_PCI is set.
33369 + * how broken is that? Do the right thing here.
33370 + */
33371 +#undef readl
33372 +#undef writel
33373 +
33374 +#define readl(addr) in_le32((__force unsigned *)(addr))
33375 +#define writel(val,addr) out_le32((__force unsigned *)(addr),(val))
33376 +
33377 +#define readl_be(addr) in_be32((__force unsigned *)(addr))
33378 +#define writel_be(val, addr) out_be32((__force unsigned *)(addr), (val))
33379 +#endif
33380 +
33381 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
33382 __u32 __iomem * regs)
33383 {
33384 --- a/drivers/usb/host/ehci-hcd.c
33385 +++ b/drivers/usb/host/ehci-hcd.c
33386 @@ -1043,6 +1043,11 @@ MODULE_LICENSE ("GPL");
33387 #define PLATFORM_DRIVER ixp4xx_ehci_driver
33388 #endif
33389
33390 +#ifdef CONFIG_M54455
33391 +#include "ehci-arc.c"
33392 +#define PLATFORM_DRIVER ehci_fsl_driver
33393 +#endif
33394 +
33395 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
33396 !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER)
33397 #error "missing bus glue for ehci-hcd"
33398 --- a/drivers/usb/host/ehci-mem.c
33399 +++ b/drivers/usb/host/ehci-mem.c
33400 @@ -40,7 +40,8 @@ static inline void ehci_qtd_init(struct
33401 {
33402 memset (qtd, 0, sizeof *qtd);
33403 qtd->qtd_dma = dma;
33404 - qtd->hw_token = cpu_to_le32 (QTD_STS_HALT);
33405 + // DDD official code` has: qtd->hw_token = cpu_to_le32 (QTD_STS_HALT);
33406 + qtd->hw_token = cpu_to_hc32 (ehci, QTD_STS_HALT);
33407 qtd->hw_next = EHCI_LIST_END(ehci);
33408 qtd->hw_alt_next = EHCI_LIST_END(ehci);
33409 INIT_LIST_HEAD (&qtd->qtd_list);
33410 @@ -211,9 +212,11 @@ static int ehci_mem_init (struct ehci_hc
33411 }
33412
33413 /* Hardware periodic table */
33414 - ehci->periodic = (__le32 *)
33415 + // DDD official code has: ehci->periodic = (__le32 *)
33416 + ehci->periodic = (__hc32 *)
33417 dma_alloc_coherent (ehci_to_hcd(ehci)->self.controller,
33418 - ehci->periodic_size * sizeof(__le32),
33419 + // DDD official: ehci->periodic_size * sizeof(__le32),
33420 + ehci->periodic_size * sizeof(__hc32),
33421 &ehci->periodic_dma, 0);
33422 if (ehci->periodic == NULL) {
33423 goto fail;
33424 --- a/drivers/usb/host/Kconfig
33425 +++ b/drivers/usb/host/Kconfig
33426 @@ -32,6 +32,7 @@ config USB_EHCI_HCD
33427 config USB_EHCI_ROOT_HUB_TT
33428 bool "Root Hub Transaction Translators (EXPERIMENTAL)"
33429 depends on USB_EHCI_HCD && EXPERIMENTAL
33430 + default y if M54455
33431 ---help---
33432 Some EHCI chips have vendor-specific extensions to integrate
33433 transaction translators, so that no OHCI or UHCI companion
33434 @@ -60,12 +61,12 @@ config USB_EHCI_TT_NEWSCHED
33435
33436 config USB_EHCI_BIG_ENDIAN_MMIO
33437 bool
33438 - depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || ARCH_IXP4XX)
33439 + depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || ARCH_IXP4XX || M54455)
33440 default y
33441
33442 config USB_EHCI_BIG_ENDIAN_DESC
33443 bool
33444 - depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX)
33445 + depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX || M54455)
33446 default y
33447
33448 config USB_EHCI_FSL
33449 @@ -260,3 +261,19 @@ config USB_R8A66597_HCD
33450 To compile this driver as a module, choose M here: the
33451 module will be called r8a66597-hcd.
33452
33453 +choice
33454 + prompt "Select transceiver"
33455 + depends on M54455
33456 + default USB_M5445X_ULPI
33457 +
33458 +config USB_M5445X_ULPI
33459 + bool "External ULPI"
33460 + ---help---
33461 + Enable support for the external HS ULPI transceiver.
33462 +
33463 +config USB_M5445X_FSLS
33464 + bool "On-chip (FL/LS only)"
33465 + ---help---
33466 + Enable support for the on-chip FL/LS transceiver.
33467 +endchoice
33468 +
33469 --- a/drivers/usb/host/Makefile
33470 +++ b/drivers/usb/host/Makefile
33471 @@ -6,7 +6,7 @@ ifeq ($(CONFIG_USB_DEBUG),y)
33472 EXTRA_CFLAGS += -DDEBUG
33473 endif
33474
33475 -obj-$(CONFIG_PCI) += pci-quirks.o
33476 +#obj-$(CONFIG_PCI) += pci-quirks.o
33477
33478 obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
33479 obj-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o
33480 --- a/drivers/usb/Kconfig
33481 +++ b/drivers/usb/Kconfig
33482 @@ -55,6 +55,7 @@ config USB_ARCH_HAS_EHCI
33483 default y if PPC_83xx
33484 default y if SOC_AU1200
33485 default y if ARCH_IXP4XX
33486 + default y if M54455
33487 default PCI
33488
33489 # ARM SA1111 chips have a non-PCI based "OHCI-compatible" USB host interface.
33490 --- a/drivers/usb/Makefile
33491 +++ b/drivers/usb/Makefile
33492 @@ -32,3 +32,5 @@ obj-$(CONFIG_USB) += misc/
33493
33494 obj-$(CONFIG_USB_ATM) += atm/
33495 obj-$(CONFIG_USB_SPEEDTOUCH) += atm/
33496 +
33497 +obj-$(CONFIG_USB_OTG) += otg/
33498 --- /dev/null
33499 +++ b/drivers/usb/otg/fsl_otg.c
33500 @@ -0,0 +1,1306 @@
33501 +/*
33502 + * Copyright (c) Freescale Semiconductor, Inc. 2006-2007
33503 + *
33504 + * USB OTG ULPI driver
33505 + *
33506 + * Based on code for MPC from:
33507 + * Leo Li<LeoLi@freescale.com>
33508 + * Jerry Huang<Chang-Ming.Huang@freescale.com>
33509 + *
33510 + * and M5329 code from
33511 + * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
33512 + * Andrey Butok
33513 + *
33514 + * Initialization based on code from Shlomi Gridish.
33515 + *
33516 + * This program is free software; you can redistribute it and/or modify
33517 + * it under the terms of the GNU General Public License as published by
33518 + * the Free Software Foundation; either version 2 of the License, or
33519 + * (at your option) any later version.
33520 + *
33521 + * This program is distributed in the hope that it will be useful, but
33522 + * WITHOUT ANY WARRANTY; without even the implied warranty of
33523 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
33524 + * General Public License for more details.
33525 + *
33526 + * You should have received a copy of the GNU General Public License along
33527 + * with this program; if not, write to the Free Software Foundation, Inc.,
33528 + * 675 Mass Ave, Cambridge, MA 02139, USA.
33529 + ***************************************************************************
33530 + * Changes:
33531 + * v0.3 08 August 2007 Duck
33532 + * v0.2 20 October 2006 Andrey Butok
33533 + * Issues fixing and some changes.
33534 + * v0.1 September 2006 Yaroslav Vinogradov
33535 + * Initial version.
33536 + *
33537 + */
33538 +
33539 +#include <linux/module.h>
33540 +#include <linux/moduleparam.h>
33541 +#include <linux/kernel.h>
33542 +#include <linux/delay.h>
33543 +#include <linux/ioport.h>
33544 +#include <linux/sched.h>
33545 +#include <linux/slab.h>
33546 +#include <linux/smp_lock.h>
33547 +#include <linux/proc_fs.h>
33548 +#include <linux/errno.h>
33549 +#include <linux/init.h>
33550 +#include <linux/reboot.h>
33551 +#include <linux/timer.h>
33552 +#include <linux/list.h>
33553 +#include <linux/interrupt.h>
33554 +#include <linux/usb.h>
33555 +#include <linux/device.h>
33556 +#include <linux/platform_device.h>
33557 +#include <linux/usb/ch9.h>
33558 +#include <linux/usb_gadget.h>
33559 +#include <linux/workqueue.h>
33560 +#include <linux/time.h>
33561 +#include <linux/fsl_devices.h>
33562 +#include <linux/usb/fsl_usb2.h>
33563 +
33564 +#include <linux/io.h>
33565 +
33566 +#if defined CONFIG_M54455
33567 +#include <asm/mcfsim.h>
33568 +#endif
33569 +
33570 +#define USE_WORK_QUEUES
33571 +#include "fsl_otg.h"
33572 +
33573 +#define CONFIG_USB_OTG_DEBUG_FILES
33574 +#define DRIVER_VERSION "Revision: 1.56"
33575 +#define DRIVER_AUTHOR "Freescale Semiconductor Inc."
33576 +#define DRIVER_DESC "Freescale USB OTG ULPI Driver"
33577 +#define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
33578 +
33579 +MODULE_DESCRIPTION("Freescale USB OTG Controller Driver");
33580 +
33581 +static const char driver_name[] = "fsl-usb2-otg";
33582 +
33583 +static spinlock_t usb_dr_regs_lock;
33584 +
33585 +/*#define HA_DATA_PULSE 1*/
33586 +
33587 +volatile static struct fsl_usb_device_regs *usb_dr_regs;
33588 +static struct fsl_otg *fsl_otg_dev;
33589 +static int srp_wait_done;
33590 +
33591 +/* Driver specific timers */
33592 +struct fsl_otg_timer *b_data_pulse_tmr, *b_vbus_pulse_tmr, *b_srp_fail_tmr,
33593 + *b_srp_wait_tmr, *a_wait_enum_tmr;
33594 +
33595 +static struct list_head active_timers;
33596 +
33597 +static struct fsl_otg_config fsl_otg_initdata = {
33598 + .otg_port = 1,
33599 +};
33600 +
33601 +#if 0
33602 +static void dump_state(const char *string, struct otg_fsm *fsm)
33603 +{
33604 + printk(KERN_DEBUG "%s\n\tOTG state: %s\n", string,
33605 + state_string(fsl_otg_dev->otg.state));
33606 + printk(KERN_DEBUG "\tFSM protocol=%s\n", fsm->protocol ?
33607 + (fsm->protocol == PROTO_HOST ? "Host" : "Gadget")
33608 + : "None");
33609 +
33610 + /* regs */
33611 + printk(KERN_DEBUG "\t OTGSC 0x%08x\n",
33612 + fsl_readl(&usb_dr_regs->otgsc));
33613 + printk(KERN_DEBUG "\tPORTSC1 0x%08x\n",
33614 + fsl_readl(&usb_dr_regs->portsc1));
33615 + printk(KERN_DEBUG "\tUSBMODE 0x%08x\n",
33616 + fsl_readl(&usb_dr_regs->usbmode));
33617 + printk(KERN_DEBUG "\t USBCMD 0x%08x\n",
33618 + fsl_readl(&usb_dr_regs->usbcmd));
33619 + printk(KERN_DEBUG "\t USBSTS 0x%08x\n",
33620 + fsl_readl(&usb_dr_regs->usbsts));
33621 +
33622 + /* ------ State Machine Variables ----- */
33623 + printk(KERN_DEBUG "\ta_bus_req: %d\n", fsm->a_bus_req);
33624 + printk(KERN_DEBUG "\tb_bus_req: %d\n", fsm->b_bus_req);
33625 + printk(KERN_DEBUG "\ta_bus_resume: %d\n", fsm->a_bus_resume);
33626 + printk(KERN_DEBUG "\ta_bus_suspend: %d\n", fsm->a_bus_suspend);
33627 + printk(KERN_DEBUG "\ta_conn: %d\n", fsm->a_conn);
33628 + printk(KERN_DEBUG "\ta_sess_vld: %d\n", fsm->a_sess_vld);
33629 + printk(KERN_DEBUG "\ta_srp_det: %d\n", fsm->a_srp_det);
33630 + printk(KERN_DEBUG "\ta_vbus_vld: %d\n", fsm->a_vbus_vld);
33631 + printk(KERN_DEBUG "\tb_bus_resume: %d\n", fsm->b_bus_resume);
33632 + printk(KERN_DEBUG "\tb_bus_suspend: %d\n", fsm->b_bus_suspend);
33633 + printk(KERN_DEBUG "\tb_conn: %d\n", fsm->b_conn);
33634 + printk(KERN_DEBUG "\tb_se0_srp: %d\n", fsm->b_se0_srp);
33635 + printk(KERN_DEBUG "\tb_sess_end: %d\n", fsm->b_sess_end);
33636 + printk(KERN_DEBUG "\tb_sess_vld: %d\n", fsm->b_sess_vld);
33637 + printk(KERN_DEBUG "\tid: %d\n", fsm->id);
33638 +}
33639 +#endif
33640 +
33641 +
33642 +/* Routines to access transceiver ULPI registers */
33643 +u8 view_ulpi(u8 addr)
33644 +{
33645 + u32 temp;
33646 +
33647 + temp = 0x40000000 | (addr << 16);
33648 + fsl_writel(temp, &usb_dr_regs->ulpiview);
33649 +
33650 + udelay(1000);
33651 +
33652 + /* DDD timeout this loop: */
33653 + do {
33654 + temp = fsl_readl(&usb_dr_regs->ulpiview);
33655 + } while (temp & 0x40000000);
33656 +
33657 + return (temp & 0x0000ff00) >> 8;
33658 +}
33659 +
33660 +int write_ulpi(u8 addr, u8 data)
33661 +{
33662 + u32 temp;
33663 +
33664 + temp = 0x60000000 | (addr << 16) | data;
33665 + fsl_writel(temp, &usb_dr_regs->ulpiview);
33666 + return 0;
33667 +}
33668 +
33669 +/* prototype declaration */
33670 +void fsl_otg_add_timer(void *timer);
33671 +void fsl_otg_del_timer(void *timer);
33672 +
33673 +/* -------------------------------------------------------------*/
33674 +/* Operations that will be called from OTG Finite State Machine */
33675 +
33676 +/* Charge vbus for vbus pulsing in SRP */
33677 +void fsl_otg_chrg_vbus(int on)
33678 +{
33679 + u32 tmp;
33680 +
33681 + VDBG(" %d\n", on);
33682 +
33683 + tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
33684 +
33685 + if (on) {
33686 + tmp &= ~OTGSC_CTRL_VBUS_DISCHARGE;
33687 + tmp |= OTGSC_CTRL_VBUS_CHARGE;
33688 + } else {
33689 + tmp &= ~OTGSC_CTRL_VBUS_CHARGE;
33690 + }
33691 + fsl_writel(tmp, &usb_dr_regs->otgsc);
33692 +}
33693 +
33694 +/* Discharge vbus through a resistor to ground */
33695 +void fsl_otg_dischrg_vbus(int on)
33696 +{
33697 + u32 tmp;
33698 +
33699 + VDBG(" %d\n", on);
33700 +
33701 + tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
33702 +
33703 + if (on)
33704 + tmp |= OTGSC_CTRL_VBUS_DISCHARGE;
33705 + else
33706 + tmp &= ~OTGSC_CTRL_VBUS_DISCHARGE;
33707 +
33708 + fsl_writel(tmp, &usb_dr_regs->otgsc);
33709 +}
33710 +
33711 +/* A-device driver vbus, controlled through PP bit in PORTSC */
33712 +void fsl_otg_drv_vbus(int on)
33713 +{
33714 + u32 tmp;
33715 +
33716 + VDBG(" %d\n", on);
33717 +
33718 + tmp = fsl_readl(&usb_dr_regs->portsc1) & ~PORTSCX_W1C_BITS;
33719 +
33720 + if (on)
33721 + tmp |= PORTSCX_PORT_POWER;
33722 + else
33723 + tmp &= ~PORTSCX_PORT_POWER;
33724 +
33725 + fsl_writel(tmp, &usb_dr_regs->portsc1);
33726 +}
33727 +
33728 +/* Pull-up D+, signalling connect by periperal. Also used in
33729 + * data-line pulsing in SRP */
33730 +void fsl_otg_loc_conn(int on)
33731 +{
33732 + u32 tmp;
33733 +
33734 + VDBG(" %d\n", on);
33735 +
33736 + tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
33737 +
33738 + if (on)
33739 + tmp |= OTGSC_CTRL_DATA_PULSING;
33740 + else
33741 + tmp &= ~OTGSC_CTRL_DATA_PULSING;
33742 +
33743 + fsl_writel(tmp, &usb_dr_regs->otgsc);
33744 +}
33745 +
33746 +/* Generate SOF by host. This is controlled through suspend/resume the
33747 + * port. In host mode, controller will automatically send SOF.
33748 + * Suspend will block the data on the port.
33749 + */
33750 +void fsl_otg_loc_sof(int on)
33751 +{
33752 + u32 tmp;
33753 +
33754 + VDBG(" %d\n", on);
33755 +
33756 + tmp = fsl_readl(&usb_dr_regs->portsc1) & ~PORTSCX_W1C_BITS;
33757 +
33758 + if (on)
33759 + tmp |= PORTSCX_PORT_FORCE_RESUME;
33760 + else
33761 + tmp |= PORTSCX_PORT_SUSPEND;
33762 +
33763 + fsl_writel(tmp, &usb_dr_regs->portsc1);
33764 +}
33765 +
33766 +/* Start SRP pulsing by data-line pulsing, followed with v-bus pulsing. */
33767 +void fsl_otg_start_pulse(void)
33768 +{
33769 + u32 __attribute__ ((unused)) tmp;
33770 +
33771 + VDBG("\n");
33772 + srp_wait_done = 0;
33773 +
33774 +#ifdef HA_DATA_PULSE
33775 + tmp = fsl_readl(&usb_dr_regs->otgsc) &= ~OTGSC_INTSTS_MASK;
33776 + tmp |= OTGSC_HA_DATA_PULSE;
33777 + fsl_writel(tmp, &usb_dr_regs->otgsc);
33778 +#else
33779 + fsl_otg_loc_conn(1);
33780 +#endif
33781 +
33782 + fsl_otg_add_timer(b_data_pulse_tmr);
33783 +}
33784 +
33785 +void fsl_otg_pulse_vbus(void);
33786 +
33787 +void b_data_pulse_end(unsigned long foo)
33788 +{
33789 +#ifdef HA_DATA_PULSE
33790 +#else
33791 + fsl_otg_loc_conn(0);
33792 +#endif
33793 +
33794 + /* Do VBUS pulse after data pulse */
33795 + fsl_otg_pulse_vbus();
33796 +}
33797 +
33798 +void fsl_otg_pulse_vbus(void)
33799 +{
33800 + srp_wait_done = 0;
33801 + fsl_otg_chrg_vbus(1);
33802 + /* start the timer to end vbus charge */
33803 + fsl_otg_add_timer(b_vbus_pulse_tmr);
33804 +}
33805 +
33806 +void b_vbus_pulse_end(unsigned long foo)
33807 +{
33808 + fsl_otg_chrg_vbus(0);
33809 +
33810 + /* As USB3300 using the same a_sess_vld and b_sess_vld voltage
33811 + * we need to discharge the bus for a while to distinguish
33812 + * residual voltage of vbus pulsing and A device pull up */
33813 + fsl_otg_dischrg_vbus(1);
33814 + fsl_otg_add_timer(b_srp_wait_tmr);
33815 +}
33816 +
33817 +void b_srp_end(unsigned long foo)
33818 +{
33819 + fsl_otg_dischrg_vbus(0);
33820 + srp_wait_done = 1;
33821 +
33822 + if ((fsl_otg_dev->otg.state == OTG_STATE_B_SRP_INIT) &&
33823 + fsl_otg_dev->fsm.b_sess_vld)
33824 + fsl_otg_dev->fsm.b_srp_done = 1;
33825 +}
33826 +
33827 +/* Workaround for a_host suspending too fast. When a_bus_req=0,
33828 + * a_host will start by SRP. It needs to set b_hnp_enable before
33829 + * actually suspending to start HNP
33830 + */
33831 +void a_wait_enum(unsigned long foo)
33832 +{
33833 + VDBG("a_wait_enum timeout\n");
33834 + if (!fsl_otg_dev->otg.host->b_hnp_enable)
33835 + fsl_otg_add_timer(a_wait_enum_tmr);
33836 + else
33837 + otg_statemachine(&fsl_otg_dev->fsm);
33838 +}
33839 +
33840 +/* ------------------------------------------------------*/
33841 +
33842 +/* The timeout callback function to set time out bit */
33843 +void set_tmout(unsigned long indicator)
33844 +{
33845 + *(int *)indicator = 1;
33846 +}
33847 +
33848 +/* Initialize timers */
33849 +void fsl_otg_init_timers(struct otg_fsm *fsm)
33850 +{
33851 + /* FSM used timers */
33852 + fsm->a_wait_vrise_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_VRISE,
33853 + (unsigned long)&fsm->a_wait_vrise_tmout);
33854 + fsm->a_wait_bcon_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_BCON,
33855 + (unsigned long)&fsm->a_wait_bcon_tmout);
33856 + fsm->a_aidl_bdis_tmr = otg_timer_initializer(&set_tmout, TA_AIDL_BDIS,
33857 + (unsigned long)&fsm->a_aidl_bdis_tmout);
33858 + fsm->b_ase0_brst_tmr = otg_timer_initializer(&set_tmout, TB_ASE0_BRST,
33859 + (unsigned long)&fsm->b_ase0_brst_tmout);
33860 + fsm->b_se0_srp_tmr = otg_timer_initializer(&set_tmout, TB_SE0_SRP,
33861 + (unsigned long)&fsm->b_se0_srp);
33862 + fsm->b_srp_fail_tmr = otg_timer_initializer(&set_tmout, TB_SRP_FAIL,
33863 + (unsigned long)&fsm->b_srp_done);
33864 + fsm->a_wait_enum_tmr = otg_timer_initializer(&a_wait_enum, 10,
33865 + (unsigned long)&fsm);
33866 +
33867 + /* device driver used timers */
33868 + b_srp_wait_tmr = otg_timer_initializer(&b_srp_end, TB_SRP_WAIT, 0);
33869 + b_data_pulse_tmr = otg_timer_initializer(&b_data_pulse_end,
33870 + TB_DATA_PLS, 0);
33871 + b_vbus_pulse_tmr = otg_timer_initializer(&b_vbus_pulse_end,
33872 + TB_VBUS_PLS, 0);
33873 +
33874 +}
33875 +
33876 +/* Add timer to timer list */
33877 +void fsl_otg_add_timer(void *gtimer)
33878 +{
33879 + struct fsl_otg_timer *timer = (struct fsl_otg_timer *)gtimer;
33880 + struct fsl_otg_timer *tmp_timer;
33881 +
33882 + /* Check if the timer is already in the active list,
33883 + * if so update timer count
33884 + */
33885 + list_for_each_entry(tmp_timer, &active_timers, list)
33886 + if (tmp_timer == timer) {
33887 + timer->count = timer->expires;
33888 + return;
33889 + }
33890 + timer->count = timer->expires;
33891 + list_add_tail(&timer->list, &active_timers);
33892 +}
33893 +
33894 +/* Remove timer from the timer list; clear timeout status */
33895 +void fsl_otg_del_timer(void *gtimer)
33896 +{
33897 + struct fsl_otg_timer *timer = (struct fsl_otg_timer *)gtimer;
33898 + struct fsl_otg_timer *tmp_timer, *del_tmp;
33899 +
33900 + list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list)
33901 + if (tmp_timer == timer)
33902 + list_del(&timer->list);
33903 +}
33904 +
33905 +/*
33906 + * Reduce timer count by 1, and find timeout conditions.
33907 + * Called by fsl_otg 1ms timer interrupt
33908 + */
33909 +int fsl_otg_tick_timer(void)
33910 +{
33911 + struct fsl_otg_timer *tmp_timer, *del_tmp;
33912 + int expired = 0;
33913 +
33914 + list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list) {
33915 + tmp_timer->count--;
33916 + /* check if timer expires */
33917 + if (!tmp_timer->count) {
33918 + list_del(&tmp_timer->list);
33919 + tmp_timer->function(tmp_timer->data);
33920 + expired = 1;
33921 + }
33922 + }
33923 +
33924 + return expired;
33925 +}
33926 +
33927 +/* Reset controller, not reset the bus */
33928 +void otg_reset_controller(void)
33929 +{
33930 + u32 command;
33931 + unsigned long flags;
33932 + int timeout;
33933 +
33934 + VDBG("\n");
33935 +
33936 + spin_lock_irqsave(&usb_dr_regs_lock, flags);
33937 +
33938 + command = fsl_readl(&usb_dr_regs->usbcmd);
33939 + command |= USB_CMD_CTRL_RESET;
33940 + fsl_writel(command, &usb_dr_regs->usbcmd);
33941 + spin_unlock_irqrestore(&usb_dr_regs_lock, flags);
33942 +
33943 + /* Wait reset completed */
33944 + timeout = 500;
33945 + while (fsl_readl(&usb_dr_regs->usbcmd) & USB_CMD_CTRL_RESET)
33946 + udelay(1);
33947 + if (timeout <= 0)
33948 + ERR("%s - USBCMD_RST never clear. Timeout is %d \n",
33949 + __FUNCTION__, timeout);
33950 +}
33951 +
33952 +/* Call suspend/resume routines in host driver */
33953 +int fsl_otg_start_host(struct otg_fsm *fsm, int on)
33954 +{
33955 + struct otg_transceiver *xceiv = fsm->transceiver;
33956 + struct device *dev;
33957 + struct fsl_otg *otg_dev = container_of(xceiv, struct fsl_otg, otg);
33958 + u32 retval = 0;
33959 +
33960 + if (!xceiv->host)
33961 + return -ENODEV;
33962 +
33963 + dev = xceiv->host->controller;
33964 +
33965 + /*
33966 + * Update a_vbus_vld state as a_vbus_vld int is disabled
33967 + * in device mode
33968 + */
33969 + fsm->a_vbus_vld =
33970 + !!(fsl_readl(&usb_dr_regs->otgsc) & OTGSC_STS_A_VBUS_VALID);
33971 + if (on) {
33972 + /* start fsl usb host controller */
33973 + if (otg_dev->host_working)
33974 + goto end;
33975 + else {
33976 + otg_reset_controller();
33977 + VDBG("host on......\n");
33978 + if (dev->driver->resume) {
33979 + retval = dev->driver->resume(dev);
33980 + if (fsm->id) {
33981 + /* default-b */
33982 + fsl_otg_drv_vbus(1);
33983 + /* Workaround: b_host can't driver
33984 + * vbus, but PP in PORTSC needs to
33985 + * be 1 for host to work.
33986 + * So we set drv_vbus bit in
33987 + * transceiver to 0 thru ULPI. */
33988 + write_ulpi(0x0c, 0x20);
33989 + }
33990 + }
33991 +
33992 + otg_dev->host_working = 1;
33993 + }
33994 + } else {
33995 + /* stop fsl usb host controller */
33996 + if (!otg_dev->host_working)
33997 + goto end;
33998 + else {
33999 + VDBG("host off......\n");
34000 + if (dev && dev->driver) {
34001 + retval = dev->driver->suspend(dev, PMSG_SUSPEND);
34002 + if (fsm->id)
34003 + /* default-b */
34004 + fsl_otg_drv_vbus(0);
34005 + }
34006 + otg_dev->host_working = 0;
34007 + }
34008 + }
34009 +end:
34010 + return retval;
34011 +}
34012 +
34013 +/*
34014 + * Call suspend and resume function in udc driver
34015 + * to stop and start udc driver.
34016 + */
34017 +int fsl_otg_start_gadget(struct otg_fsm *fsm, int on)
34018 +{
34019 + struct otg_transceiver *xceiv = fsm->transceiver;
34020 + struct device *dev;
34021 +
34022 + VDBG("DDD fsm=%p xceiv=%p\n", fsm, xceiv);
34023 + if (!xceiv->gadget || !xceiv->gadget->dev.parent)
34024 + return -ENODEV;
34025 +
34026 + VDBG("DDD xceiv=%p xceiv->gadget=%p parent=%p\n", xceiv, xceiv->gadget,
34027 + xceiv->gadget->dev.parent);
34028 +
34029 + VDBG("gadget %s\n", on ? "on" : "off");
34030 + /* DDD dump_state("starting gadget", fsm); */
34031 +
34032 + dev = xceiv->gadget->dev.parent;
34033 +
34034 + if (on)
34035 + dev->driver->resume(dev);
34036 + else
34037 + dev->driver->suspend(dev, PMSG_SUSPEND);
34038 +
34039 + return 0;
34040 +}
34041 +
34042 +#if 0
34043 +static void fsl_otg_enable(struct otg_transceiver *otg_p)
34044 +{
34045 + struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg);
34046 + struct otg_fsm *fsm = &(otg_dev)->fsm;
34047 + u32 otg_sc;
34048 +
34049 + /* DDD VDBG(""); */
34050 + /* enable OTG interrupt */
34051 + otg_sc = fsl_readl(&usb_dr_regs->otgsc);
34052 + otg_sc |= OTGSC_INTERRUPT_ENABLE_BITS_MASK;
34053 + otg_sc &= ~OTGSC_IE_1ms_TIMER;
34054 + otg_sc &= ~OTGSC_CTRL_VBUS_DISCHARGE;
34055 + otg_sc |= OTGSC_IE_USB_ID;
34056 + fsl_writel(otg_sc, &usb_dr_regs->otgsc);
34057 +
34058 + fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0;
34059 +
34060 + if (fsm->id) {
34061 + otg_p->state = OTG_STATE_UNDEFINED;
34062 + } else {
34063 + otg_p->state = OTG_STATE_A_IDLE;
34064 + }
34065 +
34066 + otg_p->default_a = (fsm->id == 0);
34067 + otg_p->host->is_b_host = fsm->id;
34068 + otg_p->gadget->is_a_peripheral = !fsm->id;
34069 +
34070 + fsm->a_vbus_vld = 1;
34071 +
34072 + fsm->b_sess_vld = (otg_sc & OTGSC_STS_B_SESSION_VALID) ? 1 : 0;
34073 + fsm->a_sess_vld = (otg_sc & OTGSC_STS_A_SESSION_VALID) ? 1 : 0;
34074 + fsm->b_sess_end = (otg_sc & OTGSC_STS_B_SESSION_END) ? 1 : 0;
34075 +}
34076 +#endif
34077 +
34078 +/*
34079 + * Called by initialization code of host driver. Register host controller
34080 + * to the OTG. Suspend host for OTG role detection.
34081 + */
34082 +static int fsl_otg_set_host(struct otg_transceiver *otg_p, struct usb_bus *host)
34083 +{
34084 + struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg);
34085 +
34086 + if (!otg_p || otg_dev != fsl_otg_dev)
34087 + return -ENODEV;
34088 +
34089 + otg_p->host = host;
34090 +
34091 + otg_dev->fsm.a_bus_drop = 0;
34092 + otg_dev->fsm.a_bus_req = 1;
34093 +
34094 + if (host) {
34095 + VDBG("host off......\n");
34096 +
34097 + otg_p->host->otg_port = fsl_otg_initdata.otg_port;
34098 + otg_p->host->is_b_host = otg_dev->fsm.id;
34099 + /* must leave time for khubd to finish its thing
34100 + * before yanking the host driver out from under it,
34101 + * so suspend the host after a short delay.
34102 + */
34103 + otg_dev->host_working = 1;
34104 + schedule_delayed_work(&otg_dev->otg_event, 100);
34105 + return 0;
34106 + } else { /* host driver going away */
34107 +
34108 + if (!(le32_to_cpu(otg_dev->dr_mem_map->otgsc) &
34109 + OTGSC_STS_USB_ID)) {
34110 + /* Mini-A cable connected */
34111 + struct otg_fsm *fsm = &otg_dev->fsm;
34112 +
34113 + otg_p->state = OTG_STATE_UNDEFINED;
34114 + fsm->protocol = PROTO_UNDEF;
34115 + }
34116 + }
34117 +
34118 + otg_dev->host_working = 0;
34119 +
34120 + otg_statemachine(&otg_dev->fsm);
34121 +
34122 + return 0;
34123 +}
34124 +
34125 +/* Called by initialization code of udc. Register udc to OTG.*/
34126 +static int fsl_otg_set_peripheral(struct otg_transceiver *otg_p,
34127 + struct usb_gadget *gadget)
34128 +{
34129 + struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg);
34130 +
34131 + VDBG("\n");
34132 +
34133 + if (!otg_p || otg_dev != fsl_otg_dev)
34134 + return -ENODEV;
34135 +
34136 + if (!gadget) {
34137 + if (!otg_dev->otg.default_a)
34138 + otg_p->gadget->ops->vbus_draw(otg_p->gadget, 0);
34139 + usb_gadget_vbus_disconnect(otg_dev->otg.gadget);
34140 + otg_dev->otg.gadget = 0;
34141 + otg_dev->fsm.b_bus_req = 0;
34142 + otg_statemachine(&otg_dev->fsm);
34143 + return 0;
34144 + }
34145 +
34146 + otg_p->gadget = gadget;
34147 + otg_p->gadget->is_a_peripheral = !otg_dev->fsm.id;
34148 +
34149 + otg_dev->fsm.b_bus_req = 1;
34150 +
34151 + /* start the gadget right away if the ID pin says Mini-B */
34152 + DBG("ID pin=%d\n", otg_dev->fsm.id);
34153 + if (otg_dev->fsm.id == 1) {
34154 + fsl_otg_start_host(&otg_dev->fsm, 0);
34155 + fsl_otg_drv_vbus(0);
34156 + fsl_otg_start_gadget(&otg_dev->fsm, 1);
34157 + }
34158 +
34159 + return 0;
34160 +}
34161 +
34162 +/* Set OTG port power, only for B-device */
34163 +static int fsl_otg_set_power(struct otg_transceiver *otg_p, unsigned mA)
34164 +{
34165 + if (!fsl_otg_dev)
34166 + return -ENODEV;
34167 + if (otg_p->state == OTG_STATE_B_PERIPHERAL)
34168 + printk(KERN_DEBUG "FSL OTG:Draw %d mA\n", mA);
34169 +
34170 + return 0;
34171 +}
34172 +
34173 +/* Delayed pin detect interrupt processing.
34174 + *
34175 + * When the Mini-A cable is disconnected from the board,
34176 + * the pin-detect interrupt happens before the disconnnect
34177 + * interrupts for the connected device(s). In order to
34178 + * process the disconnect interrupt(s) prior to switching
34179 + * roles, the pin-detect interrupts are delayed, and handled
34180 + * by this routine.
34181 + */
34182 +static void fsl_otg_event(struct work_struct *work)
34183 +{
34184 + struct fsl_otg *og = container_of(work, struct fsl_otg, otg_event.work);
34185 + struct otg_fsm *fsm = &og->fsm;
34186 +
34187 + VDBG("DDD fsm->id=%d\n", fsm->id);
34188 + if (fsm->id) { /* switch to gadget */
34189 + fsl_otg_start_host(fsm, 0);
34190 + fsl_otg_drv_vbus(0);
34191 + fsl_otg_start_gadget(fsm, 1);
34192 + }
34193 +}
34194 +
34195 +/* B-device start SRP */
34196 +static int fsl_otg_start_srp(struct otg_transceiver *otg_p)
34197 +{
34198 + struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg);
34199 +
34200 + if (!otg_p || otg_dev != fsl_otg_dev
34201 + || otg_p->state != OTG_STATE_B_IDLE)
34202 + return -ENODEV;
34203 +
34204 + otg_dev->fsm.b_bus_req = 1;
34205 + otg_statemachine(&otg_dev->fsm);
34206 +
34207 + return 0;
34208 +}
34209 +
34210 +/* A_host suspend will call this function to start hnp */
34211 +static int fsl_otg_start_hnp(struct otg_transceiver *otg_p)
34212 +{
34213 + struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg);
34214 +
34215 + if (!otg_p || otg_dev != fsl_otg_dev)
34216 + return -ENODEV;
34217 +
34218 + VDBG("start_hnp.............\n");
34219 + /* clear a_bus_req to enter a_suspend state */
34220 + otg_dev->fsm.a_bus_req = 0;
34221 + otg_statemachine(&otg_dev->fsm);
34222 +
34223 + return 0;
34224 +}
34225 +
34226 +/*
34227 + * Interrupt handler. OTG/host/peripheral share the same int line.
34228 + * OTG driver clears OTGSC interrupts and leaves USB interrupts
34229 + * intact. It needs to have knowledge of some USB interrupts
34230 + * such as port change.
34231 + */
34232 +irqreturn_t fsl_otg_isr(int irq, void *dev_id)
34233 +{
34234 + struct otg_fsm *fsm = &((struct fsl_otg *)dev_id)->fsm;
34235 + struct otg_transceiver *otg = &((struct fsl_otg *)dev_id)->otg;
34236 + u32 otg_int_src, otg_sc;
34237 +
34238 + otg_sc = fsl_readl(&usb_dr_regs->otgsc);
34239 + otg_int_src = otg_sc & OTGSC_INTSTS_MASK & (otg_sc >> 8);
34240 +
34241 + /* Only clear otg interrupts */
34242 + fsl_writel(otg_sc, &usb_dr_regs->otgsc);
34243 +
34244 + /*FIXME: ID change not generate when init to 0 */
34245 + fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0;
34246 + otg->default_a = (fsm->id == 0);
34247 +
34248 + /* process OTG interrupts */
34249 + if (otg_int_src) {
34250 + VDBG("\nOTG irq 0x%08x\n", otg_int_src);
34251 +
34252 + if (otg_int_src & OTGSC_INTSTS_USB_ID) {
34253 + fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0;
34254 + otg->default_a = (fsm->id == 0);
34255 + /* clear conn information */
34256 + if (fsm->id)
34257 + fsm->b_conn = 0;
34258 + else
34259 + fsm->a_conn = 0;
34260 +
34261 + if (otg->host)
34262 + otg->host->is_b_host = fsm->id;
34263 + if (otg->gadget)
34264 + otg->gadget->is_a_peripheral = !fsm->id;
34265 + VDBG("ID int (ID is %d)\n", fsm->id);
34266 +
34267 + if (fsm->id) { /* switch to gadget */
34268 + schedule_delayed_work(&((struct fsl_otg *)
34269 + dev_id)->otg_event, 25);
34270 + } else { /* switch to host */
34271 + cancel_delayed_work(&
34272 + ((struct fsl_otg *)dev_id)->
34273 + otg_event);
34274 + fsl_otg_start_gadget(fsm, 0);
34275 + fsl_otg_drv_vbus(1);
34276 + fsl_otg_start_host(fsm, 1);
34277 + }
34278 +
34279 + return IRQ_HANDLED;
34280 + }
34281 + }
34282 +
34283 + return IRQ_NONE;
34284 +}
34285 +
34286 +
34287 +static struct otg_fsm_ops fsl_otg_ops = {
34288 + .chrg_vbus = fsl_otg_chrg_vbus,
34289 + .drv_vbus = fsl_otg_drv_vbus,
34290 + .loc_conn = fsl_otg_loc_conn,
34291 + .loc_sof = fsl_otg_loc_sof,
34292 + .start_pulse = fsl_otg_start_pulse,
34293 +
34294 + .add_timer = fsl_otg_add_timer,
34295 + .del_timer = fsl_otg_del_timer,
34296 +
34297 + .start_host = fsl_otg_start_host,
34298 + .start_gadget = fsl_otg_start_gadget,
34299 +};
34300 +
34301 +/* Initialize the global variable fsl_otg_dev and request IRQ for OTG */
34302 +int fsl_otg_cfg(struct platform_device *pdev)
34303 +{
34304 + int status;
34305 + struct fsl_otg *fsl_otg_tc;
34306 + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
34307 + struct resource *res;
34308 +
34309 + DBG("\n");
34310 +
34311 + if (fsl_otg_dev)
34312 + return 0;
34313 +
34314 + /* allocate space to fsl otg device */
34315 + fsl_otg_tc = kzalloc(sizeof(struct fsl_otg), GFP_KERNEL);
34316 + if (!fsl_otg_tc)
34317 + return -ENODEV;
34318 +
34319 + if (pdata->regs) {
34320 + fsl_otg_tc->dr_mem_map = pdata->regs;
34321 + } else {
34322 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
34323 + if (!res) {
34324 + dev_err(&pdev->dev, "no register addr.\n");
34325 + return -ENODEV;
34326 + }
34327 +
34328 + /*
34329 + printk("DDD %s(): rsrc_start=0x%x rsrc_len=0x%x\n",
34330 + __FUNCTION__, res->start, res->end - res->start + 1);
34331 + */
34332 +
34333 + if (!request_mem_region(res->start, res->end - res->start + 1,
34334 + "OTG")) {
34335 + dev_dbg(&pdev->dev, "request_mem_region failed\n");
34336 + return -EBUSY;
34337 + }
34338 + fsl_otg_tc->dr_mem_map = ioremap(res->start,
34339 + res->end - res->start + 1);
34340 + }
34341 + DBG("set dr_mem_map to 0x%p\n", fsl_otg_tc->dr_mem_map);
34342 +
34343 + INIT_DELAYED_WORK(&fsl_otg_tc->otg_event, fsl_otg_event);
34344 +
34345 + INIT_LIST_HEAD(&active_timers);
34346 + fsl_otg_init_timers(&fsl_otg_tc->fsm);
34347 +
34348 + /* Set OTG state machine operations */
34349 + fsl_otg_tc->fsm.ops = &fsl_otg_ops;
34350 +
34351 + /* record initial state of ID pin */
34352 + fsl_otg_tc->fsm.id = (fsl_otg_tc->dr_mem_map->otgsc & OTGSC_STS_USB_ID)
34353 + ? 1 : 0;
34354 + DBG("initial ID pin=%d\n", fsl_otg_tc->fsm.id);
34355 +
34356 + /* initialize the otg structure */
34357 + fsl_otg_tc->otg.label = DRIVER_DESC;
34358 + fsl_otg_tc->otg.set_host = fsl_otg_set_host;
34359 + fsl_otg_tc->otg.set_peripheral = fsl_otg_set_peripheral;
34360 + fsl_otg_tc->otg.set_power = fsl_otg_set_power;
34361 + fsl_otg_tc->otg.start_hnp = fsl_otg_start_hnp;
34362 + fsl_otg_tc->otg.start_srp = fsl_otg_start_srp;
34363 +
34364 + fsl_otg_dev = fsl_otg_tc;
34365 +
34366 + /* Store the otg transceiver */
34367 + status = otg_set_transceiver(&fsl_otg_tc->otg);
34368 + if (status) {
34369 + printk(KERN_WARNING ": unable to register OTG transceiver.\n");
34370 + return status;
34371 + }
34372 +
34373 + return 0;
34374 +}
34375 +
34376 +/* OTG Initialization*/
34377 +int usb_otg_start(struct platform_device *pdev)
34378 +{
34379 + struct fsl_otg *p_otg;
34380 + struct otg_transceiver *otg_trans = otg_get_transceiver();
34381 + struct otg_fsm *fsm;
34382 + int status;
34383 + u32 temp;
34384 + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
34385 + int timeout;
34386 +
34387 + DBG("\n");
34388 +
34389 + p_otg = container_of(otg_trans, struct fsl_otg, otg);
34390 + fsm = &p_otg->fsm;
34391 +
34392 + /* Initialize the state machine structure with default values */
34393 + SET_OTG_STATE(otg_trans, OTG_STATE_UNDEFINED);
34394 + fsm->transceiver = &p_otg->otg;
34395 +
34396 + usb_dr_regs = p_otg->dr_mem_map;
34397 + DBG("set usb_dr_regs to 0x%p\n", usb_dr_regs);
34398 +
34399 + /* request irq */
34400 + p_otg->irq = platform_get_irq(pdev, 0);
34401 + status = request_irq(p_otg->irq, fsl_otg_isr,
34402 + IRQF_SHARED, driver_name, p_otg);
34403 + if (status) {
34404 + dev_dbg(p_otg->otg.dev, "can't get IRQ %d, error %d\n",
34405 + p_otg->irq, status);
34406 + kfree(p_otg);
34407 + return status;
34408 + }
34409 +
34410 +
34411 + /* stop the controller */
34412 + temp = fsl_readl(&usb_dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
34413 + fsl_writel(temp, &usb_dr_regs->usbcmd);
34414 +
34415 + /* reset the controller */
34416 + temp = fsl_readl(&usb_dr_regs->usbcmd);
34417 + temp |= USB_CMD_CTRL_RESET;
34418 + fsl_writel(temp, &usb_dr_regs->usbcmd);
34419 +
34420 + /* wait reset completed */
34421 + timeout = 500;
34422 + while (timeout-- &&
34423 + fsl_readl(&usb_dr_regs->usbcmd) & USB_CMD_CTRL_RESET)
34424 + udelay(1);
34425 + if (timeout <= 0)
34426 + ERR("%s - USBCMD_RST never clear. Timeout is %d \n",
34427 + __FUNCTION__, timeout);
34428 +
34429 + /* configure the VBUSHS as IDLE(both host and device) */
34430 + temp = USB_MODE_STREAM_DISABLE | (pdata->es ? USBMODE_ES : 0);
34431 + fsl_writel(temp, &usb_dr_regs->usbmode);
34432 +
34433 + /* configure PHY interface */
34434 + temp = fsl_readl(&usb_dr_regs->portsc1);
34435 + temp &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PTW_8BIT);
34436 +
34437 + /* DDD wrong xcvr setting stuff follows */
34438 + temp |= PORTSCX_PTS_ULPI;
34439 + fsl_writel(temp, &usb_dr_regs->portsc1);
34440 +
34441 +
34442 + /* disable all interrupt and clear all OTGSC status */
34443 + temp = fsl_readl(&usb_dr_regs->otgsc);
34444 + temp &= ~OTGSC_INTERRUPT_ENABLE_BITS_MASK;
34445 + temp |= OTGSC_INTERRUPT_STATUS_BITS_MASK | OTGSC_CTRL_VBUS_DISCHARGE;
34446 + fsl_writel(temp, &usb_dr_regs->otgsc);
34447 +
34448 + fsl_otg_drv_vbus(0);
34449 +
34450 + /*
34451 + * The identification (id) input is FALSE when a Mini-A plug is inserted
34452 + * in the devices Mini-AB receptacle. Otherwise, this input is TRUE.
34453 + * Also: record initial state of ID pin
34454 + */
34455 + if (fsl_readl(&usb_dr_regs->otgsc) & OTGSC_STS_USB_ID) {
34456 + p_otg->otg.state = OTG_STATE_UNDEFINED;
34457 + p_otg->fsm.id = 1;
34458 + } else {
34459 + p_otg->otg.state = OTG_STATE_A_IDLE;
34460 + p_otg->fsm.id = 0;
34461 + }
34462 +
34463 + DBG("initial ID pin=%d\n", p_otg->fsm.id);
34464 +
34465 + /* enable OTG ID pin interrupt */
34466 + temp = fsl_readl(&usb_dr_regs->otgsc);
34467 + temp |= OTGSC_IE_USB_ID;
34468 + temp &= ~(OTGSC_CTRL_VBUS_DISCHARGE | OTGSC_IE_1ms_TIMER);
34469 + fsl_writel(temp, &usb_dr_regs->otgsc);
34470 +
34471 + return 0;
34472 +}
34473 +
34474 +/* Initialize board specific registers,PIB board,clock and pin multiplexing */
34475 +static int board_init(struct platform_device *pdev)
34476 +{
34477 + struct fsl_usb2_platform_data *pdata;
34478 + pdata = (struct fsl_usb2_platform_data *)pdev->dev.platform_data;
34479 +
34480 + /*
34481 + * do platform specific init: check the clock, grab/config pins, etc.
34482 + */
34483 + if (pdata->platform_init(pdev) != 0)
34484 + return -EINVAL;
34485 +
34486 + return 0;
34487 +}
34488 +
34489 +/*-------------------------------------------------------------------------
34490 + PROC File System Support
34491 +-------------------------------------------------------------------------*/
34492 +#ifdef CONFIG_USB_OTG_DEBUG_FILES
34493 +
34494 +#include <linux/seq_file.h>
34495 +
34496 +static const char proc_filename[] = "driver/fsl_usb2_otg";
34497 +
34498 +static int otg_proc_read(char *page, char **start, off_t off, int count,
34499 + int *eof, void *_dev)
34500 +{
34501 + struct otg_fsm *fsm = &fsl_otg_dev->fsm;
34502 + char *buf = page;
34503 + char *next = buf;
34504 + unsigned size = count;
34505 + unsigned long flags;
34506 + int t;
34507 + u32 tmp_reg;
34508 +
34509 + if (off != 0)
34510 + return 0;
34511 +
34512 + spin_lock_irqsave(&fsm->lock, flags);
34513 +
34514 + /* ------basic driver infomation ---- */
34515 + t = scnprintf(next, size,
34516 + DRIVER_DESC "\n" "fsl_usb2_otg version: %s\n\n",
34517 + DRIVER_VERSION);
34518 + size -= t;
34519 + next += t;
34520 +
34521 + /* ------ Registers ----- */
34522 + /* tmp_reg = le32_to_cpu(usb_dr_regs->otgsc); */
34523 + tmp_reg = fsl_readl(&usb_dr_regs->otgsc);
34524 + t = scnprintf(next, size, "OTGSC reg: 0x%08x\n", tmp_reg);
34525 + size -= t;
34526 + next += t;
34527 +
34528 + /* tmp_reg = le32_to_cpu(usb_dr_regs->portsc); */
34529 + tmp_reg = fsl_readl(&usb_dr_regs->portsc1);
34530 + t = scnprintf(next, size, "PORTSC reg: 0x%08x\n", tmp_reg);
34531 + size -= t;
34532 + next += t;
34533 +
34534 + /* tmp_reg = le32_to_cpu(usb_dr_regs->usbmode); */
34535 + tmp_reg = fsl_readl(&usb_dr_regs->usbmode);
34536 + t = scnprintf(next, size, "USBMODE reg: 0x%08x\n", tmp_reg);
34537 + size -= t;
34538 + next += t;
34539 +
34540 + /* tmp_reg = le32_to_cpu(usb_dr_regs->usbcmd); */
34541 + tmp_reg = fsl_readl(&usb_dr_regs->usbcmd);
34542 + t = scnprintf(next, size, "USBCMD reg: 0x%08x\n", tmp_reg);
34543 + size -= t;
34544 + next += t;
34545 +
34546 + /* tmp_reg = le32_to_cpu(usb_dr_regs->usbsts); */
34547 + tmp_reg = fsl_readl(&usb_dr_regs->usbsts);
34548 + t = scnprintf(next, size, "USBSTS reg: 0x%08x\n", tmp_reg);
34549 + size -= t;
34550 + next += t;
34551 +
34552 + /* ------ State ----- */
34553 + t = scnprintf(next, size, "FSM protocol=%d %s\n", fsm->protocol,
34554 + fsm->protocol ?
34555 + (fsm->protocol == PROTO_HOST ? "Host" : "Gadget")
34556 + : "None");
34557 + size -= t;
34558 + next += t;
34559 +
34560 + t = scnprintf(next, size,
34561 + "OTG state: %s\n\n",
34562 + state_string(fsl_otg_dev->otg.state));
34563 + size -= t;
34564 + next += t;
34565 +
34566 + /* ------ State Machine Variables ----- */
34567 + t = scnprintf(next, size, "a_bus_req: %d\n", fsm->a_bus_req);
34568 + size -= t;
34569 + next += t;
34570 +
34571 + t = scnprintf(next, size, "b_bus_req: %d\n", fsm->b_bus_req);
34572 + size -= t;
34573 + next += t;
34574 +
34575 + t = scnprintf(next, size, "a_bus_resume: %d\n", fsm->a_bus_resume);
34576 + size -= t;
34577 + next += t;
34578 +
34579 + t = scnprintf(next, size, "a_bus_suspend: %d\n", fsm->a_bus_suspend);
34580 + size -= t;
34581 + next += t;
34582 +
34583 + t = scnprintf(next, size, "a_conn: %d\n", fsm->a_conn);
34584 + size -= t;
34585 + next += t;
34586 +
34587 + t = scnprintf(next, size, "a_sess_vld: %d\n", fsm->a_sess_vld);
34588 + size -= t;
34589 + next += t;
34590 +
34591 + t = scnprintf(next, size, "a_srp_det: %d\n", fsm->a_srp_det);
34592 + size -= t;
34593 + next += t;
34594 +
34595 + t = scnprintf(next, size, "a_vbus_vld: %d\n", fsm->a_vbus_vld);
34596 + size -= t;
34597 + next += t;
34598 +
34599 + t = scnprintf(next, size, "b_bus_resume: %d\n", fsm->b_bus_resume);
34600 + size -= t;
34601 + next += t;
34602 +
34603 + t = scnprintf(next, size, "b_bus_suspend: %d\n", fsm->b_bus_suspend);
34604 + size -= t;
34605 + next += t;
34606 +
34607 + t = scnprintf(next, size, "b_conn: %d\n", fsm->b_conn);
34608 + size -= t;
34609 + next += t;
34610 +
34611 + t = scnprintf(next, size, "b_se0_srp: %d\n", fsm->b_se0_srp);
34612 + size -= t;
34613 + next += t;
34614 +
34615 + t = scnprintf(next, size, "b_sess_end: %d\n", fsm->b_sess_end);
34616 + size -= t;
34617 + next += t;
34618 +
34619 + t = scnprintf(next, size, "b_sess_vld: %d\n", fsm->b_sess_vld);
34620 + size -= t;
34621 + next += t;
34622 +
34623 + t = scnprintf(next, size, "id: %d\n", fsm->id);
34624 + size -= t;
34625 + next += t;
34626 +
34627 + spin_unlock_irqrestore(&fsm->lock, flags);
34628 +
34629 + *eof = 1;
34630 + return count - size;
34631 +}
34632 +
34633 +#define create_proc_file() create_proc_read_entry(proc_filename, \
34634 + 0, NULL, otg_proc_read, NULL)
34635 +
34636 +#define remove_proc_file() remove_proc_entry(proc_filename, NULL)
34637 +
34638 +#else /* !CONFIG_USB_OTG_DEBUG_FILES */
34639 +
34640 +#define create_proc_file() do {} while (0)
34641 +#define remove_proc_file() do {} while (0)
34642 +
34643 +#endif /*CONFIG_USB_OTG_DEBUG_FILES */
34644 +
34645 +/*----------------------------------------------------------*/
34646 +/* Char driver interface to control some OTG input */
34647 +
34648 +/*
34649 + * This function handle some ioctl command,such as get otg
34650 + * status and set host suspend
34651 + */
34652 +static int fsl_otg_ioctl(struct inode *inode, struct file *file,
34653 + unsigned int cmd, unsigned long arg)
34654 +{
34655 + u32 retval = 0;
34656 +
34657 + switch (cmd) {
34658 + case GET_OTG_STATUS:
34659 + retval = fsl_otg_dev->host_working;
34660 + break;
34661 +
34662 + case SET_A_SUSPEND_REQ:
34663 + fsl_otg_dev->fsm.a_suspend_req = arg;
34664 + break;
34665 +
34666 + case SET_A_BUS_DROP:
34667 + fsl_otg_dev->fsm.a_bus_drop = arg;
34668 + break;
34669 +
34670 + case SET_A_BUS_REQ:
34671 + fsl_otg_dev->fsm.a_bus_req = arg;
34672 + break;
34673 +
34674 + case SET_B_BUS_REQ:
34675 + fsl_otg_dev->fsm.b_bus_req = arg;
34676 + break;
34677 +
34678 + default:
34679 + break;
34680 + }
34681 +
34682 + otg_statemachine(&fsl_otg_dev->fsm);
34683 +
34684 + return retval;
34685 +}
34686 +
34687 +static int fsl_otg_open(struct inode *inode, struct file *file)
34688 +{
34689 +
34690 + return 0;
34691 +}
34692 +
34693 +static int fsl_otg_release(struct inode *inode, struct file *file)
34694 +{
34695 +
34696 + return 0;
34697 +}
34698 +
34699 +static struct file_operations otg_fops = {
34700 + .owner = THIS_MODULE,
34701 + .llseek = NULL,
34702 + .read = NULL,
34703 + .write = NULL,
34704 + .ioctl = fsl_otg_ioctl,
34705 + .open = fsl_otg_open,
34706 + .release = fsl_otg_release,
34707 +};
34708 +
34709 +static int __init fsl_otg_probe(struct platform_device *pdev)
34710 +{
34711 + int status;
34712 + struct fsl_usb2_platform_data *pdata;
34713 +
34714 + DBG("pdev=0x%p\n", pdev);
34715 +
34716 + if (!pdev)
34717 + return -ENODEV;
34718 +
34719 + if (!pdev->dev.platform_data)
34720 + return -ENOMEM;
34721 +
34722 + pdata = pdev->dev.platform_data;
34723 + /* Initialize the clock, multiplexing pin and PHY interface */
34724 + board_init(pdev);
34725 +
34726 + /* configure the OTG */
34727 + status = fsl_otg_cfg(pdev);
34728 + if (status) {
34729 + printk(KERN_INFO "Couldn't init OTG module\n");
34730 + return -status;
34731 + }
34732 +
34733 + /* start OTG */
34734 + status = usb_otg_start(pdev);
34735 +
34736 + if (register_chrdev(FSL_OTG_MAJOR, FSL_OTG_NAME, &otg_fops)) {
34737 + printk(KERN_WARNING FSL_OTG_NAME
34738 + ": unable to register FSL OTG device\n");
34739 + return -EIO;
34740 + }
34741 +
34742 + create_proc_file();
34743 + return status;
34744 +}
34745 +
34746 +static int fsl_otg_remove(struct platform_device *pdev)
34747 +{
34748 + u32 ie;
34749 + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
34750 + unsigned long flags;
34751 +
34752 + DBG("pdev=0x%p pdata=0x%p\n", pdev, pdata);
34753 +
34754 + otg_set_transceiver(NULL);
34755 +
34756 + /* disable and clear OTGSC interrupts */
34757 + spin_lock_irqsave(&usb_dr_regs_lock, flags);
34758 + ie = fsl_readl(&usb_dr_regs->otgsc);
34759 + ie &= ~OTGSC_INTERRUPT_ENABLE_BITS_MASK;
34760 + ie |= OTGSC_INTERRUPT_STATUS_BITS_MASK;
34761 + fsl_writel(ie, &usb_dr_regs->otgsc);
34762 + spin_unlock_irqrestore(&usb_dr_regs_lock, flags);
34763 +
34764 + free_irq(fsl_otg_dev->irq, fsl_otg_dev);
34765 +
34766 + kfree(fsl_otg_dev);
34767 +
34768 + remove_proc_file();
34769 +
34770 + unregister_chrdev(FSL_OTG_MAJOR, FSL_OTG_NAME);
34771 +
34772 + if (pdata->platform_uninit)
34773 + pdata->platform_uninit(pdev);
34774 +
34775 + fsl_otg_dev = NULL;
34776 + return 0;
34777 +}
34778 +
34779 +struct platform_driver fsl_otg_driver = {
34780 + .probe = fsl_otg_probe,
34781 + .remove = fsl_otg_remove,
34782 + .driver = {
34783 + .name = driver_name,
34784 + .owner = THIS_MODULE,
34785 + },
34786 +};
34787 +
34788 +/*-------------------------------------------------------------------------*/
34789 +
34790 +static int __init fsl_usb_otg_init(void)
34791 +{
34792 + printk(KERN_INFO DRIVER_DESC " loaded, %s\n", DRIVER_VERSION);
34793 + return platform_driver_register(&fsl_otg_driver);
34794 +}
34795 +
34796 +static void __exit fsl_usb_otg_exit(void)
34797 +{
34798 + platform_driver_unregister(&fsl_otg_driver);
34799 +}
34800 +
34801 +module_init(fsl_usb_otg_init);
34802 +module_exit(fsl_usb_otg_exit);
34803 +
34804 +MODULE_DESCRIPTION(DRIVER_INFO);
34805 +MODULE_AUTHOR(DRIVER_AUTHOR);
34806 +MODULE_LICENSE("GPL");
34807 --- /dev/null
34808 +++ b/drivers/usb/otg/fsl_otg.h
34809 @@ -0,0 +1,139 @@
34810 +/*
34811 + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
34812 + */
34813 +
34814 +/*
34815 + * The code contained herein is licensed under the GNU General Public
34816 + * License. You may obtain a copy of the GNU General Public License
34817 + * Version 2 or later at the following locations:
34818 + *
34819 + * http://www.opensource.org/licenses/gpl-license.html
34820 + * http://www.gnu.org/copyleft/gpl.html
34821 + */
34822 +
34823 +#ifndef FSL_OTG_H
34824 +#define FSL_OTG_H
34825 +#include <linux/usb/otg.h>
34826 +#include "otg_fsm.h"
34827 +#include <linux/ioctl.h>
34828 +
34829 +#define ERR(format, arg...) \
34830 +printk(KERN_ERR "%s:%s: " format "\n" , __FILE__, __FUNCTION__ , ## arg)
34831 +
34832 +/*
34833 + * A-DEVICE timing constants
34834 + */
34835 +
34836 +/* Wait for VBUS Rise */
34837 +#define TA_WAIT_VRISE (100) /* a_wait_vrise 100 ms, section: 6.6.5.1 */
34838 +
34839 +/* Wait for B-Connect */
34840 +#define TA_WAIT_BCON (10000) /* a_wait_bcon > 1 sec, section: 6.6.5.2
34841 + * This is only used to get out of
34842 + * OTG_STATE_A_WAIT_BCON state if there was
34843 + * no connection for these many milliseconds
34844 + */
34845 +
34846 +/* A-Idle to B-Disconnect */
34847 +/* It is necessary for this timer to be more than 750 ms because of a bug in OPT
34848 + * test 5.4 in which B OPT disconnects after 750 ms instead of 75ms as stated
34849 + * in the test description
34850 + */
34851 +#define TA_AIDL_BDIS (5000) /* a_suspend minimum 200 ms, section: 6.6.5.3 */
34852 +
34853 +/* B-Idle to A-Disconnect */
34854 +#define TA_BIDL_ADIS (12) /* 3 to 200 ms */
34855 +
34856 +/* B-device timing constants */
34857 +
34858 +/* Data-Line Pulse Time*/
34859 +#define TB_DATA_PLS (10) /* b_srp_init,continue 5~10ms, section:5.3.3 */
34860 +#define TB_DATA_PLS_MIN (5) /* minimum 5 ms */
34861 +#define TB_DATA_PLS_MAX (10) /* maximum 10 ms */
34862 +
34863 +/* SRP Initiate Time */
34864 +#define TB_SRP_INIT (100) /* b_srp_init,maximum 100 ms, section:5.3.8 */
34865 +
34866 +/* SRP Fail Time */
34867 +#define TB_SRP_FAIL (7000) /* b_srp_init,Fail time 5~30s, section:6.8.2.2 */
34868 +
34869 +/* SRP result wait time */
34870 +#define TB_SRP_WAIT (60)
34871 +
34872 +/* VBus time */
34873 +#define TB_VBUS_PLS (30) /* time to keep vbus pulsing asserted */
34874 +
34875 +/* Discharge time */
34876 +/* This time should be less than 10ms. It varies from system to system. */
34877 +#define TB_VBUS_DSCHRG (8)
34878 +
34879 +/* A-SE0 to B-Reset */
34880 +#define TB_ASE0_BRST (20) /* b_wait_acon, mini 3.125 ms,section:6.8.2.4 */
34881 +
34882 +/* A bus suspend timer before we can switch to b_wait_aconn */
34883 +#define TB_A_SUSPEND (7)
34884 +#define TB_BUS_RESUME (12)
34885 +
34886 +/* SE0 Time Before SRP */
34887 +#define TB_SE0_SRP (2) /* b_idle,minimum 2 ms, section:5.3.2 */
34888 +
34889 +#define SET_OTG_STATE(otg_ptr, newstate) ((otg_ptr)->state = newstate)
34890 +
34891 +
34892 +struct fsl_otg_timer {
34893 + unsigned long expires; /* Number of count increase to timeout */
34894 + unsigned long count; /* Tick counter */
34895 + void (*function) (unsigned long); /* Timeout function */
34896 + unsigned long data; /* Data passed to function */
34897 + struct list_head list;
34898 +};
34899 +
34900 +struct fsl_otg_timer inline *otg_timer_initializer
34901 + (void (*function) (unsigned long), unsigned long expires,
34902 + unsigned long data) {
34903 + struct fsl_otg_timer *timer;
34904 + timer = kmalloc(sizeof(struct fsl_otg_timer), GFP_KERNEL);
34905 + if (timer == NULL)
34906 + return NULL;
34907 + timer->function = function;
34908 + timer->expires = expires;
34909 + timer->data = data;
34910 + return timer;
34911 +}
34912 +
34913 +struct fsl_otg {
34914 + struct otg_transceiver otg;
34915 + struct otg_fsm fsm;
34916 + struct fsl_usb_device_regs *dr_mem_map;
34917 + struct delayed_work otg_event;
34918 +
34919 + /*used for usb host */
34920 + u8 host_working;
34921 + u8 on_off;
34922 +
34923 + int irq;
34924 +};
34925 +
34926 +struct fsl_otg_config {
34927 + u8 otg_port;
34928 +};
34929 +
34930 +/*For SRP and HNP handle*/
34931 +#define FSL_OTG_MAJOR 66
34932 +#define FSL_OTG_NAME "fsl-otg"
34933 +/*Command to OTG driver(ioctl)*/
34934 +#define OTG_IOCTL_MAGIC FSL_OTG_MAJOR
34935 +/*if otg work as host,it should return 1,otherwise it return 0*/
34936 +#define GET_OTG_STATUS _IOR(OTG_IOCTL_MAGIC, 1, int)
34937 +#define SET_A_SUSPEND_REQ _IOW(OTG_IOCTL_MAGIC, 2, int)
34938 +#define SET_A_BUS_DROP _IOW(OTG_IOCTL_MAGIC, 3, int)
34939 +#define SET_A_BUS_REQ _IOW(OTG_IOCTL_MAGIC, 4, int)
34940 +#define SET_B_BUS_REQ _IOW(OTG_IOCTL_MAGIC, 5, int)
34941 +#define GET_A_SUSPEND_REQ _IOR(OTG_IOCTL_MAGIC, 6, int)
34942 +#define GET_A_BUS_DROP _IOR(OTG_IOCTL_MAGIC, 7, int)
34943 +#define GET_A_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 8, int)
34944 +#define GET_B_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 9, int)
34945 +
34946 +
34947 +/********************************************************************/
34948 +#endif
34949 --- /dev/null
34950 +++ b/drivers/usb/otg/Makefile
34951 @@ -0,0 +1,5 @@
34952 +#
34953 +# Makefile for USB OTG controller driver
34954 +#
34955 +fsl_usb2_otg-objs := fsl_otg.o otg_fsm.o
34956 +obj-y += fsl_usb2_otg.o
34957 --- /dev/null
34958 +++ b/drivers/usb/otg/otg_fsm.c
34959 @@ -0,0 +1,381 @@
34960 +/* OTG Finite State Machine from OTG spec
34961 + *
34962 + * Copyright (C) 2007 Freescale Semiconductor, Inc.
34963 + *
34964 + * Author: Li Yang <LeoLi@freescale.com>
34965 + * Jerry Huang <Chang-Ming.Huang@freescale.com>
34966 + *
34967 + * This program is free software; you can redistribute it and/or modify it
34968 + * under the terms of the GNU General Public License as published by the
34969 + * Free Software Foundation; either version 2 of the License, or (at your
34970 + * option) any later version.
34971 + *
34972 + * This program is distributed in the hope that it will be useful, but
34973 + * WITHOUT ANY WARRANTY; without even the implied warranty of
34974 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
34975 + * General Public License for more details.
34976 + *
34977 + * You should have received a copy of the GNU General Public License along
34978 + * with this program; if not, write to the Free Software Foundation, Inc.,
34979 + * 675 Mass Ave, Cambridge, MA 02139, USA.
34980 + */
34981 +
34982 +#include <linux/kernel.h>
34983 +#include <linux/types.h>
34984 +#include <linux/usb/otg.h>
34985 +#include <linux/spinlock.h>
34986 +#include <linux/delay.h>
34987 +#include <linux/usb.h>
34988 +#include <linux/usb_gadget.h>
34989 +
34990 +#include "otg_fsm.h"
34991 +
34992 +
34993 +/* Defined by device specific driver, for different timer implementation */
34994 +extern void *a_wait_vrise_tmr, *a_wait_bcon_tmr, *a_aidl_bdis_tmr,
34995 + *b_ase0_brst_tmr, *b_se0_srp_tmr, *b_srp_fail_tmr, *a_wait_enum_tmr;
34996 +
34997 +const char *state_string(enum usb_otg_state state)
34998 +{
34999 + switch (state) {
35000 + case OTG_STATE_A_IDLE: return "a_idle";
35001 + case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
35002 + case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
35003 + case OTG_STATE_A_HOST: return "a_host";
35004 + case OTG_STATE_A_SUSPEND: return "a_suspend";
35005 + case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
35006 + case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
35007 + case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
35008 + case OTG_STATE_B_IDLE: return "b_idle";
35009 + case OTG_STATE_B_SRP_INIT: return "b_srp_init";
35010 + case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
35011 + case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
35012 + case OTG_STATE_B_HOST: return "b_host";
35013 + default: return "UNDEFINED";
35014 + }
35015 +}
35016 +EXPORT_SYMBOL(state_string);
35017 +
35018 +/* Change USB protocol when there is a protocol change */
35019 +static int otg_set_protocol(struct otg_fsm *fsm, int protocol)
35020 +{
35021 + int ret = 0;
35022 +
35023 + VDBG("DDD old fsm->protocol= %d; new protocol= %d\n",
35024 + fsm->protocol, protocol);
35025 + if (fsm->protocol != protocol) {
35026 + VDBG("Changing role fsm->protocol= %d; new protocol= %d\n",
35027 + fsm->protocol, protocol);
35028 + /* stop old protocol */
35029 + if (fsm->protocol == PROTO_HOST)
35030 + ret = fsm->ops->start_host(fsm, 0);
35031 + else if (fsm->protocol == PROTO_GADGET)
35032 + ret = fsm->ops->start_gadget(fsm, 0);
35033 + if (ret)
35034 + return ret;
35035 +
35036 + /* start new protocol */
35037 + if (protocol == PROTO_HOST)
35038 + ret = fsm->ops->start_host(fsm, 1);
35039 + else if (protocol == PROTO_GADGET)
35040 + ret = fsm->ops->start_gadget(fsm, 1);
35041 + if (ret)
35042 + return ret;
35043 +
35044 + fsm->protocol = protocol;
35045 + return 0;
35046 + }
35047 +
35048 + return 0;
35049 +}
35050 +
35051 +static int state_changed;
35052 +
35053 +/* Called when leaving a state. Do state clean up jobs here */
35054 +static void otg_leave_state(struct otg_fsm *fsm, enum usb_otg_state old_state)
35055 +{
35056 + switch (old_state) {
35057 + case OTG_STATE_B_IDLE:
35058 + otg_del_timer(fsm, fsm->b_se0_srp_tmr);
35059 + fsm->b_se0_srp = 0;
35060 + break;
35061 + case OTG_STATE_B_SRP_INIT:
35062 + fsm->b_srp_done = 0;
35063 + break;
35064 + case OTG_STATE_B_PERIPHERAL:
35065 + break;
35066 + case OTG_STATE_B_WAIT_ACON:
35067 + otg_del_timer(fsm, fsm->b_ase0_brst_tmr);
35068 + fsm->b_ase0_brst_tmout = 0;
35069 + break;
35070 + case OTG_STATE_B_HOST:
35071 + break;
35072 + case OTG_STATE_A_IDLE:
35073 + break;
35074 + case OTG_STATE_A_WAIT_VRISE:
35075 + otg_del_timer(fsm, fsm->a_wait_vrise_tmr);
35076 + fsm->a_wait_vrise_tmout = 0;
35077 + break;
35078 + case OTG_STATE_A_WAIT_BCON:
35079 + otg_del_timer(fsm, fsm->a_wait_bcon_tmr);
35080 + fsm->a_wait_bcon_tmout = 0;
35081 + break;
35082 + case OTG_STATE_A_HOST:
35083 + otg_del_timer(fsm, fsm->a_wait_enum_tmr);
35084 + break;
35085 + case OTG_STATE_A_SUSPEND:
35086 + otg_del_timer(fsm, fsm->a_aidl_bdis_tmr);
35087 + fsm->a_aidl_bdis_tmout = 0;
35088 + fsm->a_suspend_req = 0;
35089 + fsm->a_bus_req = 1; /* FIXME */
35090 + break;
35091 + case OTG_STATE_A_PERIPHERAL:
35092 + break;
35093 + case OTG_STATE_A_WAIT_VFALL:
35094 + otg_del_timer(fsm, fsm->a_wait_vrise_tmr);
35095 + break;
35096 + case OTG_STATE_A_VBUS_ERR:
35097 + break;
35098 + default:
35099 + break;
35100 + }
35101 +}
35102 +
35103 +/* Called when entering a state */
35104 +static int otg_set_state(struct otg_fsm *fsm, enum usb_otg_state new_state)
35105 +{
35106 + state_changed = 1;
35107 + VDBG("State: old=%s new=%s \n",
35108 + state_string(fsm->transceiver->state), state_string(new_state));
35109 +
35110 + if (fsm->transceiver->state == new_state)
35111 + return 0;
35112 +
35113 + otg_leave_state(fsm, fsm->transceiver->state);
35114 + switch (new_state) {
35115 + case OTG_STATE_B_IDLE:
35116 + otg_drv_vbus(fsm, 0);
35117 + otg_chrg_vbus(fsm, 0);
35118 + otg_loc_conn(fsm, 0);
35119 + otg_loc_sof(fsm, 0);
35120 + otg_set_protocol(fsm, PROTO_UNDEF);
35121 + otg_add_timer(fsm, fsm->b_se0_srp_tmr);
35122 + break;
35123 + case OTG_STATE_B_SRP_INIT:
35124 + otg_start_pulse(fsm);
35125 + otg_loc_sof(fsm, 0);
35126 + otg_set_protocol(fsm, PROTO_UNDEF);
35127 + otg_add_timer(fsm, fsm->b_srp_fail_tmr);
35128 + break;
35129 + case OTG_STATE_B_PERIPHERAL:
35130 + otg_chrg_vbus(fsm, 0);
35131 + otg_loc_conn(fsm, 1);
35132 + otg_loc_sof(fsm, 0);
35133 + otg_set_protocol(fsm, PROTO_GADGET);
35134 + break;
35135 + case OTG_STATE_B_WAIT_ACON:
35136 + otg_chrg_vbus(fsm, 0);
35137 + otg_loc_conn(fsm, 0);
35138 + otg_loc_sof(fsm, 0);
35139 + otg_set_protocol(fsm, PROTO_HOST);
35140 + otg_add_timer(fsm, fsm->b_ase0_brst_tmr);
35141 + fsm->a_bus_suspend = 0;
35142 + break;
35143 + case OTG_STATE_B_HOST:
35144 + otg_chrg_vbus(fsm, 0);
35145 + otg_loc_conn(fsm, 0);
35146 + otg_loc_sof(fsm, 1);
35147 + otg_set_protocol(fsm, PROTO_HOST);
35148 + usb_bus_start_enum(fsm->transceiver->host,
35149 + fsm->transceiver->host->otg_port);
35150 + break;
35151 + case OTG_STATE_A_IDLE:
35152 + otg_drv_vbus(fsm, 0);
35153 + otg_chrg_vbus(fsm, 0);
35154 + otg_loc_conn(fsm, 0);
35155 + otg_loc_sof(fsm, 0);
35156 + otg_set_protocol(fsm, PROTO_HOST);
35157 + break;
35158 + case OTG_STATE_A_WAIT_VRISE:
35159 + otg_drv_vbus(fsm, 1);
35160 + otg_loc_conn(fsm, 0);
35161 + otg_loc_sof(fsm, 0);
35162 + otg_set_protocol(fsm, PROTO_HOST);
35163 + otg_add_timer(fsm, fsm->a_wait_vrise_tmr);
35164 + break;
35165 + case OTG_STATE_A_WAIT_BCON:
35166 + otg_drv_vbus(fsm, 1);
35167 + otg_loc_conn(fsm, 0);
35168 + otg_loc_sof(fsm, 0);
35169 + otg_set_protocol(fsm, PROTO_HOST);
35170 + otg_add_timer(fsm, fsm->a_wait_bcon_tmr);
35171 + break;
35172 + case OTG_STATE_A_HOST:
35173 + otg_drv_vbus(fsm, 1);
35174 + otg_loc_conn(fsm, 0);
35175 + otg_loc_sof(fsm, 1);
35176 + otg_set_protocol(fsm, PROTO_HOST);
35177 + /*
35178 + * When HNP is triggered while a_bus_req = 0, a_host will
35179 + * suspend too fast to complete a_set_b_hnp_en
35180 + */
35181 + if (!fsm->a_bus_req || fsm->a_suspend_req)
35182 + otg_add_timer(fsm, fsm->a_wait_enum_tmr);
35183 + break;
35184 + case OTG_STATE_A_SUSPEND:
35185 + otg_drv_vbus(fsm, 1);
35186 + otg_loc_conn(fsm, 0);
35187 + otg_loc_sof(fsm, 0);
35188 + otg_set_protocol(fsm, PROTO_HOST);
35189 + otg_add_timer(fsm, fsm->a_aidl_bdis_tmr);
35190 +
35191 + break;
35192 + case OTG_STATE_A_PERIPHERAL:
35193 + otg_loc_conn(fsm, 1);
35194 + otg_loc_sof(fsm, 0);
35195 + otg_set_protocol(fsm, PROTO_GADGET);
35196 + otg_drv_vbus(fsm, 1);
35197 + break;
35198 + case OTG_STATE_A_WAIT_VFALL:
35199 + otg_drv_vbus(fsm, 0);
35200 + otg_loc_conn(fsm, 0);
35201 + otg_loc_sof(fsm, 0);
35202 + otg_set_protocol(fsm, PROTO_HOST);
35203 + break;
35204 + case OTG_STATE_A_VBUS_ERR:
35205 + otg_drv_vbus(fsm, 0);
35206 + otg_loc_conn(fsm, 0);
35207 + otg_loc_sof(fsm, 0);
35208 + otg_set_protocol(fsm, PROTO_UNDEF);
35209 + break;
35210 + default:
35211 + break;
35212 + }
35213 +
35214 + fsm->transceiver->state = new_state;
35215 + return 0;
35216 +}
35217 +
35218 +/* State change judgement */
35219 +int otg_statemachine(struct otg_fsm *fsm)
35220 +{
35221 + enum usb_otg_state state;
35222 + unsigned long flags;
35223 +
35224 + spin_lock_irqsave(&fsm->lock, flags);
35225 +
35226 + state = fsm->transceiver->state;
35227 + state_changed = 0;
35228 + /* State machine state change judgement */
35229 +
35230 + VDBG(" State: %s \n", state_string(state));
35231 +
35232 + switch (state) {
35233 + case OTG_STATE_UNDEFINED:
35234 + if (fsm->id)
35235 + otg_set_state(fsm, OTG_STATE_B_IDLE);
35236 + else
35237 + otg_set_state(fsm, OTG_STATE_A_IDLE);
35238 + break;
35239 + case OTG_STATE_B_IDLE:
35240 + if (!fsm->id)
35241 + otg_set_state(fsm, OTG_STATE_A_IDLE);
35242 + else if (fsm->b_sess_vld && fsm->transceiver->gadget)
35243 + otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
35244 + else if (fsm->b_bus_req && fsm->b_sess_end && fsm->b_se0_srp)
35245 + otg_set_state(fsm, OTG_STATE_B_SRP_INIT);
35246 + break;
35247 + case OTG_STATE_B_SRP_INIT:
35248 + if (!fsm->id || fsm->b_srp_done)
35249 + otg_set_state(fsm, OTG_STATE_B_IDLE);
35250 + break;
35251 + case OTG_STATE_B_PERIPHERAL:
35252 + if (!fsm->id || !fsm->b_sess_vld)
35253 + otg_set_state(fsm, OTG_STATE_B_IDLE);
35254 + else if (fsm->b_bus_req &&
35255 + fsm->transceiver->
35256 + gadget->b_hnp_enable && fsm->a_bus_suspend)
35257 + otg_set_state(fsm, OTG_STATE_B_WAIT_ACON);
35258 + break;
35259 + case OTG_STATE_B_WAIT_ACON:
35260 + if (fsm->a_conn)
35261 + otg_set_state(fsm, OTG_STATE_B_HOST);
35262 + else if (!fsm->id || !fsm->b_sess_vld)
35263 + otg_set_state(fsm, OTG_STATE_B_IDLE);
35264 + else if (fsm->a_bus_resume || fsm->b_ase0_brst_tmout) {
35265 + fsm->b_ase0_brst_tmout = 0;
35266 + otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
35267 + }
35268 + break;
35269 + case OTG_STATE_B_HOST:
35270 + if (!fsm->id || !fsm->b_sess_vld)
35271 + otg_set_state(fsm, OTG_STATE_B_IDLE);
35272 + else if (!fsm->b_bus_req || !fsm->a_conn)
35273 + otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
35274 + break;
35275 + case OTG_STATE_A_IDLE:
35276 + if (fsm->id)
35277 + otg_set_state(fsm, OTG_STATE_B_IDLE);
35278 + else if (!fsm->a_bus_drop && (fsm->a_bus_req || fsm->a_srp_det))
35279 + otg_set_state(fsm, OTG_STATE_A_WAIT_VRISE);
35280 + break;
35281 + case OTG_STATE_A_WAIT_VRISE:
35282 + if (fsm->id || fsm->a_bus_drop || fsm->a_vbus_vld ||
35283 + fsm->a_wait_vrise_tmout) {
35284 + otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
35285 + }
35286 + break;
35287 + case OTG_STATE_A_WAIT_BCON:
35288 + if (!fsm->a_vbus_vld)
35289 + otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
35290 + else if (fsm->id | fsm->a_bus_drop | fsm->a_wait_bcon_tmout)
35291 + otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
35292 + else if (fsm->b_conn)
35293 + otg_set_state(fsm, OTG_STATE_A_HOST);
35294 + break;
35295 + case OTG_STATE_A_HOST:
35296 + if ((!fsm->a_bus_req || fsm->a_suspend_req) &&
35297 + fsm->transceiver->host->b_hnp_enable)
35298 + otg_set_state(fsm, OTG_STATE_A_SUSPEND);
35299 + else if (fsm->id || !fsm->b_conn || fsm->a_bus_drop)
35300 + otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
35301 + else if (!fsm->a_vbus_vld)
35302 + otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
35303 + break;
35304 + case OTG_STATE_A_SUSPEND:
35305 + if (!fsm->b_conn && fsm->transceiver->host->b_hnp_enable)
35306 + otg_set_state(fsm, OTG_STATE_A_PERIPHERAL);
35307 + else if (!fsm->b_conn && !fsm->transceiver->host->b_hnp_enable)
35308 + otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
35309 + else if (fsm->a_bus_req || fsm->b_bus_resume)
35310 + otg_set_state(fsm, OTG_STATE_A_HOST);
35311 + else if (fsm->id || fsm->a_bus_drop || fsm->a_aidl_bdis_tmout)
35312 + otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
35313 + else if (!fsm->a_vbus_vld)
35314 + otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
35315 + break;
35316 + case OTG_STATE_A_PERIPHERAL:
35317 + if (fsm->id || fsm->a_bus_drop)
35318 + otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
35319 + else if (fsm->b_bus_suspend)
35320 + otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
35321 + else if (!fsm->a_vbus_vld)
35322 + otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
35323 + break;
35324 + case OTG_STATE_A_WAIT_VFALL:
35325 + if (fsm->id || fsm->a_bus_req || (!fsm->a_sess_vld &&
35326 + !fsm->b_conn))
35327 + otg_set_state(fsm, OTG_STATE_A_IDLE);
35328 + break;
35329 + case OTG_STATE_A_VBUS_ERR:
35330 + if (fsm->id || fsm->a_bus_drop || fsm->a_clr_err)
35331 + otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
35332 + break;
35333 + default:
35334 + break;
35335 + }
35336 + spin_unlock_irqrestore(&fsm->lock, flags);
35337 +
35338 + return state_changed;
35339 +}
35340 +EXPORT_SYMBOL(otg_statemachine);
35341 --- /dev/null
35342 +++ b/drivers/usb/otg/otg_fsm.h
35343 @@ -0,0 +1,170 @@
35344 +/* Copyright (C) 2006-2007 Freescale Semiconductor, Inc.
35345 + *
35346 + * This program is free software; you can redistribute it and/or modify it
35347 + * under the terms of the GNU General Public License as published by the
35348 + * Free Software Foundation; either version 2 of the License, or (at your
35349 + * option) any later version.
35350 + *
35351 + * This program is distributed in the hope that it will be useful, but
35352 + * WITHOUT ANY WARRANTY; without even the implied warranty of
35353 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
35354 + * General Public License for more details.
35355 + *
35356 + * You should have received a copy of the GNU General Public License along
35357 + * with this program; if not, write to the Free Software Foundation, Inc.,
35358 + * 675 Mass Ave, Cambridge, MA 02139, USA.
35359 + */
35360 +
35361 +#ifndef OTG_FSM_H
35362 +#define OTG_FSM_H
35363 +
35364 +#if 0
35365 +#define DEBUG 1
35366 +#define VERBOSE 1
35367 +#endif
35368 +
35369 +#ifdef DEBUG
35370 +#define DBG(fmt, args...) printk(KERN_DEBUG "[%s] " fmt , \
35371 + __FUNCTION__, ## args)
35372 +#else
35373 +#define DBG(fmt, args...) do {} while (0)
35374 +#endif
35375 +
35376 +#ifdef VERBOSE
35377 +#define VDBG DBG
35378 +#else
35379 +#define VDBG(stuff...) do {} while (0)
35380 +#endif
35381 +
35382 +#ifdef VERBOSE
35383 +#define MPC_LOC printk("Current Location [%s]:[%d]\n", __FILE__, __LINE__)
35384 +#else
35385 +#define MPC_LOC do {} while (0)
35386 +#endif
35387 +
35388 +#define PROTO_UNDEF 0
35389 +#define PROTO_HOST 1
35390 +#define PROTO_GADGET 2
35391 +
35392 +
35393 +
35394 +
35395 +
35396 +/* OTG state machine according to the OTG spec */
35397 +struct otg_fsm {
35398 + /* Input */
35399 + int a_bus_resume;
35400 + int a_bus_suspend;
35401 + int a_conn;
35402 + int a_sess_vld;
35403 + int a_srp_det;
35404 + int a_vbus_vld;
35405 + int b_bus_resume;
35406 + int b_bus_suspend;
35407 + int b_conn;
35408 + int b_se0_srp;
35409 + int b_sess_end;
35410 + int b_sess_vld;
35411 + int id;
35412 +
35413 + /* Internal variables */
35414 + int a_set_b_hnp_en;
35415 + int b_srp_done;
35416 + int b_hnp_enable;
35417 +
35418 + /* Timeout indicator for timers */
35419 + int a_wait_vrise_tmout;
35420 + int a_wait_bcon_tmout;
35421 + int a_aidl_bdis_tmout;
35422 + int b_ase0_brst_tmout;
35423 +
35424 + /* Informative variables */
35425 + int a_bus_drop;
35426 + int a_bus_req;
35427 + int a_clr_err;
35428 + int a_suspend_req;
35429 + int b_bus_req;
35430 +
35431 + /* Output */
35432 + int drv_vbus;
35433 + int loc_conn;
35434 + int loc_sof;
35435 +
35436 + struct otg_fsm_ops *ops;
35437 + struct otg_transceiver *transceiver;
35438 +
35439 + void *a_wait_vrise_tmr;
35440 + void *a_wait_bcon_tmr;
35441 + void *a_aidl_bdis_tmr;
35442 + void *b_ase0_brst_tmr;
35443 + void *b_se0_srp_tmr;
35444 + void *b_srp_fail_tmr;
35445 + void *a_wait_enum_tmr;
35446 +
35447 + /* Current usb protocol used: 0:undefine; 1:host; 2:client */
35448 + int protocol;
35449 + spinlock_t lock; /* fsm lock */
35450 +};
35451 +
35452 +struct otg_fsm_ops {
35453 + void (*chrg_vbus)(int on);
35454 + void (*drv_vbus)(int on);
35455 + void (*loc_conn)(int on);
35456 + void (*loc_sof)(int on);
35457 + void (*start_pulse)(void);
35458 + void (*add_timer)(void *timer);
35459 + void (*del_timer)(void *timer);
35460 + int (*start_host)(struct otg_fsm *fsm, int on);
35461 + int (*start_gadget)(struct otg_fsm *fsm, int on);
35462 +};
35463 +
35464 +
35465 +static inline void otg_chrg_vbus(struct otg_fsm *fsm, int on)
35466 +{
35467 + fsm->ops->chrg_vbus(on);
35468 +}
35469 +
35470 +static inline void otg_drv_vbus(struct otg_fsm *fsm, int on)
35471 +{
35472 + if (fsm->drv_vbus != on) {
35473 + fsm->drv_vbus = on;
35474 + fsm->ops->drv_vbus(on);
35475 + }
35476 +}
35477 +
35478 +static inline void otg_loc_conn(struct otg_fsm *fsm, int on)
35479 +{
35480 + if (fsm->loc_conn != on) {
35481 + fsm->loc_conn = on;
35482 + fsm->ops->loc_conn(on);
35483 + }
35484 +}
35485 +
35486 +static inline void otg_loc_sof(struct otg_fsm *fsm, int on)
35487 +{
35488 + if (fsm->loc_sof != on) {
35489 + fsm->loc_sof = on;
35490 + fsm->ops->loc_sof(on);
35491 + }
35492 +}
35493 +
35494 +static inline void otg_start_pulse(struct otg_fsm *fsm)
35495 +{
35496 + fsm->ops->start_pulse();
35497 +}
35498 +
35499 +static inline void otg_add_timer(struct otg_fsm *fsm, void *timer)
35500 +{
35501 + fsm->ops->add_timer(timer);
35502 +}
35503 +
35504 +static inline void otg_del_timer(struct otg_fsm *fsm, void *timer)
35505 +{
35506 + fsm->ops->del_timer(timer);
35507 +}
35508 +
35509 +extern int otg_statemachine(struct otg_fsm *fsm);
35510 +
35511 +extern const char *state_string(enum usb_otg_state state);
35512 +
35513 +#endif
35514 --- a/drivers/video/cfbimgblt.c
35515 +++ b/drivers/video/cfbimgblt.c
35516 @@ -44,12 +44,12 @@
35517 #endif
35518
35519 static const u32 cfb_tab8[] = {
35520 -#if defined(__BIG_ENDIAN)
35521 +#if defined(__BIG_ENDIAN) && !defined(CONFIG_COLDFIRE)
35522 0x00000000,0x000000ff,0x0000ff00,0x0000ffff,
35523 0x00ff0000,0x00ff00ff,0x00ffff00,0x00ffffff,
35524 0xff000000,0xff0000ff,0xff00ff00,0xff00ffff,
35525 0xffff0000,0xffff00ff,0xffffff00,0xffffffff
35526 -#elif defined(__LITTLE_ENDIAN)
35527 +#elif defined(__LITTLE_ENDIAN) || defined(CONFIG_COLDFIRE)
35528 0x00000000,0xff000000,0x00ff0000,0xffff0000,
35529 0x0000ff00,0xff00ff00,0x00ffff00,0xffffff00,
35530 0x000000ff,0xff0000ff,0x00ff00ff,0xffff00ff,
35531 @@ -60,9 +60,9 @@ static const u32 cfb_tab8[] = {
35532 };
35533
35534 static const u32 cfb_tab16[] = {
35535 -#if defined(__BIG_ENDIAN)
35536 +#if defined(__BIG_ENDIAN) && !defined(CONFIG_COLDFIRE)
35537 0x00000000, 0x0000ffff, 0xffff0000, 0xffffffff
35538 -#elif defined(__LITTLE_ENDIAN)
35539 +#elif defined(__LITTLE_ENDIAN) || defined(CONFIG_COLDFIRE)
35540 0x00000000, 0xffff0000, 0x0000ffff, 0xffffffff
35541 #else
35542 #error FIXME: No endianness??
35543 --- a/drivers/video/console/bitblit.c
35544 +++ b/drivers/video/console/bitblit.c
35545 @@ -78,7 +78,11 @@ static inline void bit_putcs_aligned(str
35546 u32 d_pitch, u32 s_pitch, u32 cellsize,
35547 struct fb_image *image, u8 *buf, u8 *dst)
35548 {
35549 +#ifndef CONFIG_COLDFIRE
35550 u16 charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff;
35551 +#else
35552 + u32 charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff;
35553 +#endif
35554 u32 idx = vc->vc_font.width >> 3;
35555 u8 *src;
35556
35557 @@ -111,7 +115,11 @@ static inline void bit_putcs_unaligned(s
35558 struct fb_image *image, u8 *buf,
35559 u8 *dst)
35560 {
35561 +#ifndef CONFIG_COLDFIRE
35562 u16 charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff;
35563 +#else
35564 + u32 charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff;
35565 +#endif
35566 u32 shift_low = 0, mod = vc->vc_font.width % 8;
35567 u32 shift_high = 8;
35568 u32 idx = vc->vc_font.width >> 3;
35569 @@ -238,7 +246,11 @@ static void bit_cursor(struct vc_data *v
35570 {
35571 struct fb_cursor cursor;
35572 struct fbcon_ops *ops = info->fbcon_par;
35573 +#ifndef CONFIG_COLDFIRE
35574 unsigned short charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff;
35575 +#else
35576 + unsigned long charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff;
35577 +#endif
35578 int w = (vc->vc_font.width + 7) >> 3, c;
35579 int y = real_y(ops->p, vc->vc_y);
35580 int attribute, use_sw = (vc->vc_cursor_type & 0x10);
35581 --- a/drivers/video/console/fbcon.c
35582 +++ b/drivers/video/console/fbcon.c
35583 @@ -2679,8 +2679,11 @@ static int fbcon_set_palette(struct vc_d
35584 {
35585 struct fb_info *info = registered_fb[con2fb_map[vc->vc_num]];
35586 int i, j, k, depth;
35587 - u8 val;
35588 -
35589 +#ifndef CONFIG_COLDFIRE
35590 + u8 val;
35591 +#else
35592 + u32 val;
35593 +#endif
35594 if (fbcon_is_inactive(vc, info))
35595 return -EINVAL;
35596
35597 --- a/drivers/video/Kconfig
35598 +++ b/drivers/video/Kconfig
35599 @@ -201,6 +201,16 @@ config FB_TILEBLITTING
35600 comment "Frame buffer hardware drivers"
35601 depends on FB
35602
35603 +config FB_SMI
35604 + tristate "SiliconMotion Lynx support"
35605 + depends on FB && PCI
35606 + select FB_CFB_FILLRECT
35607 + select FB_CFB_COPYAREA
35608 + select FB_CFB_IMAGEBLIT
35609 + ---help---
35610 + This enables support for the Silicon Motion Lynx family of graphic
35611 + chips. It has been tested on ColdFire.
35612 +
35613 config FB_CIRRUS
35614 tristate "Cirrus Logic support"
35615 depends on FB && (ZORRO || PCI)
35616 --- a/drivers/video/Makefile
35617 +++ b/drivers/video/Makefile
35618 @@ -28,6 +28,7 @@ obj-$(CONFIG_FB_DDC) += fb_ddc
35619 obj-$(CONFIG_FB_DEFERRED_IO) += fb_defio.o
35620
35621 # Hardware specific drivers go first
35622 +obj-$(CONFIG_FB_SMI) += smifb.o
35623 obj-$(CONFIG_FB_AMIGA) += amifb.o c2p.o
35624 obj-$(CONFIG_FB_ARC) += arcfb.o
35625 obj-$(CONFIG_FB_CLPS711X) += clps711xfb.o
35626 --- /dev/null
35627 +++ b/drivers/video/smifb.c
35628 @@ -0,0 +1,949 @@
35629 +/***************************************************************************
35630 + smifb.c - Silicon Motion, Inc. LynxEM+ frame buffer device
35631 + -------------------
35632 + begin : Thu Aug 9 2001
35633 + copyright : (C) 2001 by Szu-Tao Huang
35634 + email : johuang@siliconmotion.com
35635 + ***************************************************************************/
35636 +
35637 +/***************************************************************************
35638 + * *
35639 + * This program is free software; you can redistribute it and/or modify *
35640 + * it under the terms of the GNU General Public License as published by *
35641 + * the Free Software Foundation; either version 2 of the License, or *
35642 + * (at your option) any later version. *
35643 + * *
35644 + ***************************************************************************/
35645 +
35646 +#include <linux/module.h>
35647 +#include <linux/kernel.h>
35648 +#include <linux/errno.h>
35649 +#include <linux/string.h>
35650 +#include <linux/mm.h>
35651 +#include <linux/tty.h>
35652 +#include <linux/slab.h>
35653 +#include <linux/delay.h>
35654 +#include <linux/fb.h>
35655 +#include <linux/pci.h>
35656 +#include <linux/init.h>
35657 +
35658 +#include <asm/io.h>
35659 +#include <asm/irq.h>
35660 +#include <asm/pgtable.h>
35661 +#include <asm/system.h>
35662 +#include <asm/uaccess.h>
35663 +
35664 +#include "console/fbcon.h"
35665 +
35666 +/*
35667 +#include <video/fbcon.h>
35668 +#include <video/fbcon-cfb8.h>
35669 +#include <video/fbcon-cfb16.h>
35670 +#include <video/fbcon-cfb24.h>
35671 +*/
35672 +
35673 +#include <linux/fb.h>
35674 +
35675 +static char *SMIRegs; // point to virtual Memory Map IO starting address
35676 +static char *SMILFB; // point to virtual video memory starting address
35677 +static struct par_info hw; // used to record hardware information
35678 +
35679 +#include "smifb.h"
35680 +
35681 +struct ModeInit VGAMode[numVGAModes] =
35682 +{
35683 + {
35684 + /* mode#0: 640 x 480 8Bpp 60Hz */
35685 + 640, 480, 8, 60,
35686 + /* Init_MISC */
35687 + 0xE3,
35688 + { /* Init_SR0_SR4 */
35689 + 0x03, 0x01, 0x0F, 0x00, 0x0E,
35690 + },
35691 + { /* Init_SR10_SR24 */
35692 + 0xFF, 0xBE, 0xEF, 0xFF, 0x00, 0x0E, 0x17, 0x2C,
35693 + 0x99, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
35694 + 0xC4, 0x30, 0x02, 0x01, 0x01,
35695 + },
35696 + { /* Init_SR30_SR75 */
35697 + 0x32, 0x03, 0xA0, 0x09, 0xC0, 0x32, 0x32, 0x32,
35698 + 0x32, 0x32, 0x32, 0x32, 0x00, 0x00, 0x03, 0xFF,
35699 + 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC,
35700 + 0x20, 0x0C, 0x44, 0x20, 0x00, 0x32, 0x32, 0x32,
35701 + 0x04, 0x24, 0x63, 0x4F, 0x52, 0x0B, 0xDF, 0xEA,
35702 + 0x04, 0x50, 0x19, 0x32, 0x32, 0x00, 0x00, 0x32,
35703 + 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00,
35704 + 0x50, 0x03, 0x74, 0x14, 0x07, 0x82, 0x07, 0x04,
35705 + 0x00, 0x45, 0x30, 0x30, 0x40, 0x30,
35706 + },
35707 + { /* Init_SR80_SR93 */
35708 + 0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x32,
35709 + 0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x32, 0x32,
35710 + 0x00, 0x00, 0x00, 0x00,
35711 + },
35712 + { /* Init_SRA0_SRAF */
35713 + 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED,
35714 + 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xFF, 0xDF,
35715 + },
35716 + { /* Init_GR00_GR08 */
35717 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
35718 + 0xFF,
35719 + },
35720 + { /* Init_AR00_AR14 */
35721 + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
35722 + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
35723 + 0x41, 0x00, 0x0F, 0x00, 0x00,
35724 + },
35725 + { /* Init_CR00_CR18 */
35726 + 0x5F, 0x4F, 0x4F, 0x00, 0x53, 0x1F, 0x0B, 0x3E,
35727 + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
35728 + 0xEA, 0x0C, 0xDF, 0x50, 0x40, 0xDF, 0x00, 0xE3,
35729 + 0xFF,
35730 + },
35731 + { /* Init_CR30_CR4D */
35732 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x03, 0x20,
35733 + 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xFF, 0xFD,
35734 + 0x5F, 0x4F, 0x00, 0x54, 0x00, 0x0B, 0xDF, 0x00,
35735 + 0xEA, 0x0C, 0x2E, 0x00, 0x4F, 0xDF,
35736 + },
35737 + { /* Init_CR90_CRA7 */
35738 + 0x56, 0xDD, 0x5E, 0xEA, 0x87, 0x44, 0x8F, 0x55,
35739 + 0x0A, 0x8F, 0x55, 0x0A, 0x00, 0x00, 0x18, 0x00,
35740 + 0x11, 0x10, 0x0B, 0x0A, 0x0A, 0x0A, 0x0A, 0x00,
35741 + },
35742 + },
35743 + {
35744 + /* mode#1: 640 x 480 16Bpp 60Hz */
35745 + 640, 480, 16, 60,
35746 + /* Init_MISC */
35747 + 0xE3,
35748 + { /* Init_SR0_SR4 */
35749 + 0x03, 0x01, 0x0F, 0x00, 0x0E,
35750 + },
35751 + { /* Init_SR10_SR24 */
35752 + 0xFF, 0xBE, 0xEF, 0xFF, 0x00, 0x0E, 0x17, 0x2C,
35753 + 0x99, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
35754 + 0xC4, 0x30, 0x02, 0x01, 0x01,
35755 + },
35756 + { /* Init_SR30_SR75 */
35757 + 0x32, 0x03, 0xA0, 0x09, 0xC0, 0x32, 0x32, 0x32,
35758 + 0x32, 0x32, 0x32, 0x32, 0x00, 0x00, 0x03, 0xFF,
35759 + 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC,
35760 + 0x20, 0x0C, 0x44, 0x20, 0x00, 0x32, 0x32, 0x32,
35761 + 0x04, 0x24, 0x63, 0x4F, 0x52, 0x0B, 0xDF, 0xEA,
35762 + 0x04, 0x50, 0x19, 0x32, 0x32, 0x00, 0x00, 0x32,
35763 + 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00,
35764 + 0x50, 0x03, 0x74, 0x14, 0x07, 0x82, 0x07, 0x04,
35765 + 0x00, 0x45, 0x30, 0x30, 0x40, 0x30,
35766 + },
35767 + { /* Init_SR80_SR93 */
35768 + 0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x32,
35769 + 0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x32, 0x32,
35770 + 0x00, 0x00, 0x00, 0x00,
35771 + },
35772 + { /* Init_SRA0_SRAF */
35773 + 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED,
35774 + 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xFF, 0xDF,
35775 + },
35776 + { /* Init_GR00_GR08 */
35777 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
35778 + 0xFF,
35779 + },
35780 + { /* Init_AR00_AR14 */
35781 + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
35782 + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
35783 + 0x41, 0x00, 0x0F, 0x00, 0x00,
35784 + },
35785 + { /* Init_CR00_CR18 */
35786 + 0x5F, 0x4F, 0x4F, 0x00, 0x53, 0x1F, 0x0B, 0x3E,
35787 + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
35788 + 0xEA, 0x0C, 0xDF, 0x50, 0x40, 0xDF, 0x00, 0xE3,
35789 + 0xFF,
35790 + },
35791 + { /* Init_CR30_CR4D */
35792 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x03, 0x20,
35793 + 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xFF, 0xFD,
35794 + 0x5F, 0x4F, 0x00, 0x54, 0x00, 0x0B, 0xDF, 0x00,
35795 + 0xEA, 0x0C, 0x2E, 0x00, 0x4F, 0xDF,
35796 + },
35797 + { /* Init_CR90_CRA7 */
35798 + 0x56, 0xDD, 0x5E, 0xEA, 0x87, 0x44, 0x8F, 0x55,
35799 + 0x0A, 0x8F, 0x55, 0x0A, 0x00, 0x00, 0x18, 0x00,
35800 + 0x11, 0x10, 0x0B, 0x0A, 0x0A, 0x0A, 0x0A, 0x00,
35801 + },
35802 + },
35803 + {
35804 + /* mode#2: 640 x 480 24Bpp 60Hz */
35805 + 640, 480, 24, 60,
35806 + /* Init_MISC */
35807 + 0xE3,
35808 + { /* Init_SR0_SR4 */
35809 + 0x03, 0x01, 0x0F, 0x00, 0x0E,
35810 + },
35811 + { /* Init_SR10_SR24 */
35812 + 0xFF, 0xBE, 0xEF, 0xFF, 0x00, 0x0E, 0x17, 0x2C,
35813 + 0x99, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
35814 + 0xC4, 0x30, 0x02, 0x01, 0x01,
35815 + },
35816 + { /* Init_SR30_SR75 */
35817 + 0x32, 0x03, 0xA0, 0x09, 0xC0, 0x32, 0x32, 0x32,
35818 + 0x32, 0x32, 0x32, 0x32, 0x00, 0x00, 0x03, 0xFF,
35819 + 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC,
35820 + 0x20, 0x0C, 0x44, 0x20, 0x00, 0x32, 0x32, 0x32,
35821 + 0x04, 0x24, 0x63, 0x4F, 0x52, 0x0B, 0xDF, 0xEA,
35822 + 0x04, 0x50, 0x19, 0x32, 0x32, 0x00, 0x00, 0x32,
35823 + 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00,
35824 + 0x50, 0x03, 0x74, 0x14, 0x07, 0x82, 0x07, 0x04,
35825 + 0x00, 0x45, 0x30, 0x30, 0x40, 0x30,
35826 + },
35827 + { /* Init_SR80_SR93 */
35828 + 0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x32,
35829 + 0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x32, 0x32,
35830 + 0x00, 0x00, 0x00, 0x00,
35831 + },
35832 + { /* Init_SRA0_SRAF */
35833 + 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED,
35834 + 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xFF, 0xDF,
35835 + },
35836 + { /* Init_GR00_GR08 */
35837 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
35838 + 0xFF,
35839 + },
35840 + { /* Init_AR00_AR14 */
35841 + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
35842 + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
35843 + 0x41, 0x00, 0x0F, 0x00, 0x00,
35844 + },
35845 + { /* Init_CR00_CR18 */
35846 + 0x5F, 0x4F, 0x4F, 0x00, 0x53, 0x1F, 0x0B, 0x3E,
35847 + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
35848 + 0xEA, 0x0C, 0xDF, 0x50, 0x40, 0xDF, 0x00, 0xE3,
35849 + 0xFF,
35850 + },
35851 + { /* Init_CR30_CR4D */
35852 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x03, 0x20,
35853 + 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xFF, 0xFD,
35854 + 0x5F, 0x4F, 0x00, 0x54, 0x00, 0x0B, 0xDF, 0x00,
35855 + 0xEA, 0x0C, 0x2E, 0x00, 0x4F, 0xDF,
35856 + },
35857 + { /* Init_CR90_CRA7 */
35858 + 0x56, 0xDD, 0x5E, 0xEA, 0x87, 0x44, 0x8F, 0x55,
35859 + 0x0A, 0x8F, 0x55, 0x0A, 0x00, 0x00, 0x18, 0x00,
35860 + 0x11, 0x10, 0x0B, 0x0A, 0x0A, 0x0A, 0x0A, 0x00,
35861 + },
35862 + },
35863 + {/* mode#3: 800 x 600 8Bpp 60Hz */
35864 + 800,600,8,60,
35865 + 0x2B, /* Init_MISC */
35866 + { /* Init_SR0_SR4 */
35867 + 0x03, 0x01, 0x0F, 0x03, 0x0E,
35868 + },
35869 + { /* Init_SR10_SR24 */
35870 + 0xFF, 0xBE, 0xEE, 0xFF, 0x00, 0x0E, 0x17, 0x2C,
35871 + 0x99, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
35872 + 0xC4, 0x30, 0x02, 0x01, 0x01,
35873 + },
35874 + { /* Init_SR30_SR75 */
35875 + 0x24, 0x03, 0x20, 0x09, 0xC0, 0x24, 0x24, 0x24,
35876 + 0x24, 0x24, 0x24, 0x24, 0x00, 0x00, 0x03, 0xFF,
35877 + 0x00, 0xFC, 0x00, 0x00, 0x20, 0x38, 0x00, 0xFC,
35878 + 0x20, 0x0C, 0x44, 0x20, 0x00, 0x24, 0x24, 0x24,
35879 + 0x04, 0x48, 0x83, 0x63, 0x68, 0x72, 0x57, 0x58,
35880 + 0x04, 0x55, 0x59, 0x24, 0x24, 0x00, 0x00, 0x24,
35881 + 0x01, 0x80, 0x7A, 0x1A, 0x1A, 0x00, 0x00, 0x00,
35882 + 0x50, 0x03, 0x74, 0x14, 0x1C, 0x85, 0x35, 0x13,
35883 + 0x02, 0x45, 0x30, 0x35, 0x40, 0x20,
35884 + },
35885 + { /* Init_SR80_SR93 */
35886 + 0xFF, 0x87, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x24,
35887 + 0x90, 0x01, 0x2C, 0x01, 0xFF, 0x00, 0x24, 0x24,
35888 + 0x00, 0x00, 0x00, 0x00,
35889 + },
35890 + { /* Init_SRA0_SRAF */
35891 + 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED,
35892 + 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xBF, 0xDF,
35893 + },
35894 + { /* Init_GR00_GR08 */
35895 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
35896 + 0xFF,
35897 + },
35898 + { /* Init_AR00_AR14 */
35899 + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
35900 + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
35901 + 0x41, 0x00, 0x0F, 0x00, 0x00,
35902 + },
35903 + { /* Init_CR00_CR18 */
35904 + 0x7F, 0x63, 0x63, 0x00, 0x68, 0x18, 0x72, 0xF0,
35905 + 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
35906 + 0x58, 0x0C, 0x57, 0x64, 0x40, 0x57, 0x00, 0xE3,
35907 + 0xFF,
35908 + },
35909 + { /* Init_CR30_CR4D */
35910 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x03, 0x20,
35911 + 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xBF, 0xFD,
35912 + 0x7F, 0x63, 0x00, 0x69, 0x18, 0x72, 0x57, 0x00,
35913 + 0x58, 0x0C, 0xE0, 0x20, 0x63, 0x57,
35914 + },
35915 + { /* Init_CR90_CRA7 */
35916 + 0x56, 0x4B, 0x5E, 0x55, 0x86, 0x9D, 0x8E, 0xAA,
35917 + 0xDB, 0x2A, 0xDF, 0x33, 0x00, 0x00, 0x18, 0x00,
35918 + 0x20, 0x1F, 0x1A, 0x19, 0x0F, 0x0F, 0x0F, 0x00,
35919 + },
35920 + },
35921 + {/* mode#4: 800 x 600 16Bpp 60Hz */
35922 + 800, 600, 16, 60,
35923 + /* Init_MISC */
35924 + 0x2B,
35925 + { /* Init_SR0_SR4 */
35926 + 0x03, 0x01, 0x0F, 0x03, 0x0E,
35927 + },
35928 + { /* Init_SR10_SR24 */
35929 + 0xFF, 0xBE, 0xEE, 0xFF, 0x00, 0x0E, 0x17, 0x2C,
35930 + 0x99, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
35931 + 0xC4, 0x30, 0x02, 0x01, 0x01,
35932 + },
35933 + { /* Init_SR30_SR75 */
35934 + 0x24, 0x03, 0x20, 0x09, 0xC0, 0x24, 0x24, 0x24,
35935 + 0x24, 0x24, 0x24, 0x24, 0x00, 0x00, 0x03, 0xFF,
35936 + 0x00, 0xFC, 0x00, 0x00, 0x20, 0x38, 0x00, 0xFC,
35937 + 0x20, 0x0C, 0x44, 0x20, 0x00, 0x24, 0x24, 0x24,
35938 + 0x04, 0x48, 0x83, 0x63, 0x68, 0x72, 0x57, 0x58,
35939 + 0x04, 0x55, 0x59, 0x24, 0x24, 0x00, 0x00, 0x24,
35940 + 0x01, 0x80, 0x7A, 0x1A, 0x1A, 0x00, 0x00, 0x00,
35941 + 0x50, 0x03, 0x74, 0x14, 0x1C, 0x85, 0x35, 0x13,
35942 + 0x02, 0x45, 0x30, 0x35, 0x40, 0x20,
35943 + },
35944 + { /* Init_SR80_SR93 */
35945 + 0x00, 0x00, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x24,
35946 + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x24, 0x24,
35947 + 0x00, 0x00, 0x00, 0x00,
35948 + },
35949 + { /* Init_SRA0_SRAF */
35950 + 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED,
35951 + 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xBF, 0xDF,
35952 + },
35953 + { /* Init_GR00_GR08 */
35954 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
35955 + 0xFF,
35956 + },
35957 + { /* Init_AR00_AR14 */
35958 + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
35959 + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
35960 + 0x41, 0x00, 0x0F, 0x00, 0x00,
35961 + },
35962 + { /* Init_CR00_CR18 */
35963 + 0x7F, 0x63, 0x63, 0x00, 0x68, 0x18, 0x72, 0xF0,
35964 + 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
35965 + 0x58, 0x0C, 0x57, 0x64, 0x40, 0x57, 0x00, 0xE3,
35966 + 0xFF,
35967 + },
35968 + { /* Init_CR30_CR4D */
35969 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x03, 0x20,
35970 + 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xBF, 0xFD,
35971 + 0x7F, 0x63, 0x00, 0x69, 0x18, 0x72, 0x57, 0x00,
35972 + 0x58, 0x0C, 0xE0, 0x20, 0x63, 0x57,
35973 + },
35974 + { /* Init_CR90_CRA7 */
35975 + 0x56, 0x4B, 0x5E, 0x55, 0x86, 0x9D, 0x8E, 0xAA,
35976 + 0xDB, 0x2A, 0xDF, 0x33, 0x00, 0x00, 0x18, 0x00,
35977 + 0x20, 0x1F, 0x1A, 0x19, 0x0F, 0x0F, 0x0F, 0x00,
35978 + },
35979 + },
35980 + {/* mode#5: 800 x 600 24Bpp 60Hz */
35981 + 800,600,24,60,
35982 + 0x2B,
35983 + { /* Init_SR0_SR4 */
35984 + 0x03, 0x01, 0x0F, 0x03, 0x0E,
35985 + },
35986 + { /* Init_SR10_SR24 */
35987 + 0xFF, 0xBE, 0xEE, 0xFF, 0x00, 0x0E, 0x17, 0x2C,
35988 + 0x99, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
35989 + 0xC4, 0x30, 0x02, 0x01, 0x01,
35990 + },
35991 + { /* Init_SR30_SR75 */
35992 + 0x36, 0x03, 0x20, 0x09, 0xC0, 0x36, 0x36, 0x36,
35993 + 0x36, 0x36, 0x36, 0x36, 0x00, 0x00, 0x03, 0xFF,
35994 + 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC,
35995 + 0x20, 0x0C, 0x44, 0x20, 0x00, 0x36, 0x36, 0x36,
35996 + 0x04, 0x48, 0x83, 0x63, 0x68, 0x72, 0x57, 0x58,
35997 + 0x04, 0x55, 0x59, 0x36, 0x36, 0x00, 0x00, 0x36,
35998 + 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00,
35999 + 0x50, 0x03, 0x74, 0x14, 0x1C, 0x85, 0x35, 0x13,
36000 + 0x02, 0x45, 0x30, 0x30, 0x40, 0x20,
36001 + },
36002 + { /* Init_SR80_SR93 */
36003 + 0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x36,
36004 + 0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x36, 0x36,
36005 + 0x00, 0x00, 0x00, 0x00,
36006 + },
36007 + { /* Init_SRA0_SRAF */
36008 + 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED,
36009 + 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xBF, 0xDF,
36010 + },
36011 + { /* Init_GR00_GR08 */
36012 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
36013 + 0xFF,
36014 + },
36015 + { /* Init_AR00_AR14 */
36016 + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
36017 + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
36018 + 0x41, 0x00, 0x0F, 0x00, 0x00,
36019 + },
36020 + { /* Init_CR00_CR18 */
36021 + 0x7F, 0x63, 0x63, 0x00, 0x68, 0x18, 0x72, 0xF0,
36022 + 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
36023 + 0x58, 0x0C, 0x57, 0x64, 0x40, 0x57, 0x00, 0xE3,
36024 + 0xFF,
36025 + },
36026 + { /* Init_CR30_CR4D */
36027 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x03, 0x20,
36028 + 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xBF, 0xFD,
36029 + 0x7F, 0x63, 0x00, 0x69, 0x18, 0x72, 0x57, 0x00,
36030 + 0x58, 0x0C, 0xE0, 0x20, 0x63, 0x57,
36031 + },
36032 + { /* Init_CR90_CRA7 */
36033 + 0x56, 0x4B, 0x5E, 0x55, 0x86, 0x9D, 0x8E, 0xAA,
36034 + 0xDB, 0x2A, 0xDF, 0x33, 0x00, 0x00, 0x18, 0x00,
36035 + 0x20, 0x1F, 0x1A, 0x19, 0x0F, 0x0F, 0x0F, 0x00,
36036 + },
36037 + },
36038 +};
36039 +
36040 +static void smi_set_timing(struct smifb_info *sfb,struct par_info *hw)
36041 +{
36042 + int i=0,j=0;
36043 + u32 m_nScreenStride;
36044 +
36045 +
36046 + for (j=0;j < numVGAModes;j++) {
36047 + if (VGAMode[j].mmSizeX == hw->width &&
36048 + VGAMode[j].mmSizeY == hw->height &&
36049 + VGAMode[j].bpp == sfb->fb.var.bits_per_pixel &&
36050 + VGAMode[j].hz == hw->hz)
36051 + {
36052 +
36053 + smi_mmiowb(0x0,0x3c6);
36054 +
36055 + smi_seqw(0,0x1);
36056 +
36057 + smi_mmiowb(VGAMode[j].Init_MISC,0x3c2);
36058 +
36059 + for (i=0;i<SIZE_SR00_SR04;i++) // init SEQ register SR00 - SR04
36060 + {
36061 + smi_seqw(i,VGAMode[j].Init_SR00_SR04[i]);
36062 + }
36063 +
36064 + for (i=0;i<SIZE_SR10_SR24;i++) // init SEQ register SR10 - SR24
36065 + {
36066 + smi_seqw(i+0x10,VGAMode[j].Init_SR10_SR24[i]);
36067 + }
36068 +
36069 + for (i=0;i<SIZE_SR30_SR75;i++) // init SEQ register SR30 - SR75
36070 + {
36071 + if (((i+0x30) != 0x62) && ((i+0x30) != 0x6a) && ((i+0x30) != 0x6b))
36072 + smi_seqw(i+0x30,VGAMode[j].Init_SR30_SR75[i]);
36073 + }
36074 + for (i=0;i<SIZE_SR80_SR93;i++) // init SEQ register SR80 - SR93
36075 + {
36076 + smi_seqw(i+0x80,VGAMode[j].Init_SR80_SR93[i]);
36077 + }
36078 + for (i=0;i<SIZE_SRA0_SRAF;i++) // init SEQ register SRA0 - SRAF
36079 + {
36080 + smi_seqw(i+0xa0,VGAMode[j].Init_SRA0_SRAF[i]);
36081 + }
36082 +
36083 + for (i=0;i<SIZE_GR00_GR08;i++) // init Graphic register GR00 - GR08
36084 + {
36085 + smi_grphw(i,VGAMode[j].Init_GR00_GR08[i]);
36086 + }
36087 +
36088 + for (i=0;i<SIZE_AR00_AR14;i++) // init Attribute register AR00 - AR14
36089 + {
36090 +
36091 + smi_attrw(i,VGAMode[j].Init_AR00_AR14[i]);
36092 + }
36093 +
36094 + for (i=0;i<SIZE_CR00_CR18;i++) // init CRTC register CR00 - CR18
36095 + {
36096 + smi_crtcw(i,VGAMode[j].Init_CR00_CR18[i]);
36097 + }
36098 +
36099 + for (i=0;i<SIZE_CR30_CR4D;i++) // init CRTC register CR30 - CR4D
36100 + {
36101 + smi_crtcw(i+0x30,VGAMode[j].Init_CR30_CR4D[i]);
36102 + }
36103 +
36104 + for (i=0;i<SIZE_CR90_CRA7;i++) // init CRTC register CR90 - CRA7
36105 + {
36106 + smi_crtcw(i+0x90,VGAMode[j].Init_CR90_CRA7[i]);
36107 + }
36108 + }
36109 + }
36110 + smi_mmiowb(0x67,0x3c2);
36111 + // set VPR registers
36112 + writel(0x0,hw->m_pVPR+0x0C);
36113 + writel(0x0,hw->m_pVPR+0x40);
36114 + // set data width
36115 + m_nScreenStride = (hw->width * sfb->fb.var.bits_per_pixel) / 64;
36116 + switch (sfb->fb.var.bits_per_pixel)
36117 + {
36118 + case 8:
36119 + writel(0x0,hw->m_pVPR+0x0);
36120 + break;
36121 + case 16:
36122 + writel(0x00020000,hw->m_pVPR+0x0);
36123 + break;
36124 + case 24:
36125 + writel(0x00040000,hw->m_pVPR+0x0);
36126 + break;
36127 + }
36128 + writel((u32)(((m_nScreenStride + 2) << 16) | m_nScreenStride),hw->m_pVPR+0x10);
36129 +}
36130 +
36131 +/*
36132 + * Set the color palette
36133 + */
36134 +static int
36135 +smifb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
36136 + u_int trans, struct fb_info *info)
36137 +{
36138 +
36139 + struct smifb_info *sfb = (struct smifbinfo *)info;
36140 + u32 *pal;
36141 +
36142 + switch (sfb->fb.fix.visual) {
36143 + case FB_VISUAL_TRUECOLOR: /* RGB 5:6:5 True Colour */
36144 + pal = sfb->fb.pseudo_palette; // System has 16 default color
36145 + if (regno >= 16)
36146 + return 1;
36147 +
36148 + pal[regno] = (red & 0xf800) |
36149 + ((green & 0xfc00) >> 5) | ((blue & 0xf800) >> 11);
36150 + break;
36151 + }
36152 +
36153 + return 0;
36154 +}
36155 +
36156 +/*
36157 + * smifb_decode_var():
36158 + * Get the video params out of 'var'. If a value doesn't fit, round it up,
36159 + * if it's too big, return -EINVAL.
36160 + *
36161 + * Suggestion: Round up in the following order: bits_per_pixel, xres,
36162 + * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
36163 + * bitfields, horizontal timing, vertical timing.
36164 + */
36165 +static int smifb_decode_var(struct fb_var_screeninfo *var, struct smifb_info *sfb, struct par_info *hw)
36166 +{
36167 + hw->width = var->xres;
36168 + hw->height = var->yres;
36169 + hw->hz = 60;
36170 +
36171 + return 0;
36172 +}
36173 +
36174 +static int smifb_set_par (struct fb_info *info)
36175 +{
36176 + struct smifb_info *sfb = (struct smifb_info *)info;
36177 + int err, chgvar = 0;
36178 + struct fb_var_screeninfo *var = &info->var;
36179 + struct fb_cmap *cmap;
36180 +
36181 +
36182 + /*
36183 + * Decode var contents into a par structure, adjusting any
36184 + * out of range values.
36185 + */
36186 + err = smifb_decode_var(var, sfb, &hw);
36187 + if (err) {
36188 + return err;
36189 + }
36190 +
36191 + if (hw.width != var->xres)
36192 + chgvar = 1;
36193 + if (hw.height != var->yres)
36194 + chgvar = 1;
36195 +
36196 + var->activate &= ~FB_ACTIVATE_ALL;
36197 +
36198 + smi_set_timing(sfb, &hw);
36199 +
36200 + sfb->palette_size = var->bits_per_pixel == 8 ? 256 : 16;
36201 + cmap = fb_default_cmap(sfb->palette_size);
36202 + fb_set_cmap(cmap, &sfb->fb);
36203 +
36204 + return 0;
36205 +}
36206 +
36207 +static int smifb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
36208 +{
36209 + var->bits_per_pixel += 7;
36210 + var->bits_per_pixel &= ~7;
36211 +
36212 + var->xres_virtual =
36213 + var->xres_virtual < var->xres ? var->xres : var->xres_virtual;
36214 + var->yres_virtual =
36215 + var->yres_virtual < var->yres ? var->yres : var->yres_virtual;
36216 +
36217 + switch (var->bits_per_pixel) {
36218 + case 8:
36219 + case 16: /* RGB 565 */
36220 + case 24:
36221 + break;
36222 + default:
36223 + return -EINVAL;
36224 + }
36225 +
36226 + switch (var->bits_per_pixel) {
36227 + case 16:
36228 + var->red.offset = 11;
36229 + var->red.length = 5;
36230 + var->green.offset = 5;
36231 + var->green.length = 6;
36232 + var->blue.offset = 0;
36233 + var->blue.length = 5;
36234 +
36235 + info->fix.visual = FB_VISUAL_TRUECOLOR;
36236 + info->fix.line_length= var->xres * 2;
36237 +
36238 + break;
36239 + default:
36240 + return -EINVAL; /* We don't support anything other than 16bpp for now. --NL */
36241 + break;
36242 + }
36243 + return 0;
36244 +
36245 +// smifb_set_color_bitfields(var);
36246 +
36247 + return 0;
36248 +}
36249 +
36250 +/*
36251 + * Formal definition of the VESA spec:
36252 + * On
36253 + * This refers to the state of the display when it is in full operation
36254 + * Stand-By
36255 + * This defines an optional operating state of minimal power reduction with
36256 + * the shortest recovery time
36257 + * Suspend
36258 + * This refers to a level of power management in which substantial power
36259 + * reduction is achieved by the display. The display can have a longer
36260 + * recovery time from this state than from the Stand-by state
36261 + * Off
36262 + * This indicates that the display is consuming the lowest level of power
36263 + * and is non-operational. Recovery from this state may optionally require
36264 + * the user to manually power on the monitor
36265 + *
36266 + * Now, the fbdev driver adds an additional state, (blank), where they
36267 + * turn off the video (maybe by colormap tricks), but don't mess with the
36268 + * video itself: think of it semantically between on and Stand-By.
36269 + *
36270 + * So here's what we should do in our fbdev blank routine:
36271 + *
36272 + * VESA_NO_BLANKING (mode 0) Video on, front/back light on
36273 + * VESA_VSYNC_SUSPEND (mode 1) Video on, front/back light off
36274 + * VESA_HSYNC_SUSPEND (mode 2) Video on, front/back light off
36275 + * VESA_POWERDOWN (mode 3) Video off, front/back light off
36276 + *
36277 + * This will match the matrox implementation.
36278 + */
36279 +/*
36280 + * smifb_blank():
36281 + * Blank the display by setting all palette values to zero. Note, the
36282 + * 12 and 16 bpp modes don't really use the palette, so this will not
36283 + * blank the display in all modes.
36284 + */
36285 +static int smifb_blank(int blank, struct fb_info *info)
36286 +{
36287 +// struct smifb_info *sfb = (struct smifb_info *)info;
36288 +#if 0
36289 + switch (blank) {
36290 + case VESA_POWERDOWN:
36291 + case VESA_VSYNC_SUSPEND:
36292 + case VESA_HSYNC_SUSPEND:
36293 + case VESA_NO_BLANKING:
36294 + }
36295 +#endif
36296 + return 1;
36297 +}
36298 +
36299 +static struct fb_ops smifb_ops = {
36300 + .owner = THIS_MODULE,
36301 + .fb_check_var = smifb_check_var,
36302 + .fb_set_par = smifb_set_par,
36303 + .fb_setcolreg = smifb_setcolreg,
36304 + .fb_blank = smifb_blank,
36305 +
36306 + /* Accelerated functions, using softversions, per se */
36307 + .fb_fillrect = cfb_fillrect,
36308 + .fb_copyarea = cfb_copyarea,
36309 + .fb_imageblit = cfb_imageblit,
36310 + .fb_cursor = soft_cursor,
36311 +};
36312 +
36313 +/*
36314 + * Alloc struct smifb_info and assign the default value
36315 + */
36316 +static struct smifb_info * __devinit
36317 +smi_alloc_fb_info(struct pci_dev *dev, char *name)
36318 +{
36319 + struct smifb_info *sfb;
36320 +
36321 + sfb = kmalloc(sizeof(struct smifb_info) + sizeof(u32) * 16, GFP_KERNEL);
36322 +
36323 + if (!sfb)
36324 + return NULL;
36325 +
36326 + memset(sfb, 0, sizeof(struct smifb_info));
36327 +
36328 + sfb->currcon = -1;
36329 + sfb->dev = dev;
36330 +
36331 + strcpy(sfb->fb.fix.id, name);
36332 +
36333 + sfb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
36334 + sfb->fb.fix.type_aux = 0;
36335 + sfb->fb.fix.xpanstep = 0;
36336 + sfb->fb.fix.ypanstep = 0;
36337 + sfb->fb.fix.ywrapstep = 0;
36338 + sfb->fb.fix.accel = FB_ACCEL_NONE;
36339 +
36340 + sfb->fb.var.nonstd = 0;
36341 + sfb->fb.var.activate = FB_ACTIVATE_NOW;
36342 + sfb->fb.var.height = -1;
36343 + sfb->fb.var.width = -1;
36344 + sfb->fb.var.accel_flags = 0;
36345 + sfb->fb.var.vmode = FB_VMODE_NONINTERLACED;
36346 +
36347 + sfb->fb.fbops = &smifb_ops;
36348 + sfb->fb.flags = FBINFO_FLAG_DEFAULT;
36349 + sfb->fb.node = -1;
36350 + sfb->fb.pseudo_palette = (void *)(&sfb->palette_size + 1);
36351 +
36352 + return sfb;
36353 +}
36354 +
36355 +/*
36356 + * Unmap in the memory mapped IO registers
36357 + *
36358 + */
36359 +
36360 +static void __devinit
36361 +smi_unmap_mmio(struct smifb_info *sfb)
36362 +{
36363 + if (sfb && SMILFB)
36364 + {
36365 + iounmap(SMILFB);
36366 + SMIRegs = NULL;
36367 + }
36368 +}
36369 +
36370 +/*
36371 + * Map in the screen memory
36372 + *
36373 + */
36374 +static int __devinit
36375 +smi_map_smem(struct smifb_info *sfb, struct pci_dev *dev, u_long smem_len)
36376 +{
36377 +
36378 + sfb->fb.fix.smem_start = pci_resource_start(dev, 0);
36379 + sfb->fb.fix.smem_len = smem_len;
36380 + printk("%s:smem %x,len %x\n",sfb->fb.fix.smem_start,sfb->fb.fix.smem_len);
36381 + sfb->fb.screen_base = SMILFB;
36382 +
36383 + if (!sfb->fb.screen_base)
36384 + {
36385 + printk("%s: unable to map screen memory\n",sfb->fb.fix.id);
36386 + return -ENOMEM;
36387 + }
36388 +
36389 + return 0;
36390 +}
36391 +
36392 +
36393 +/*
36394 + * Unmap in the screen memory
36395 + *
36396 + */
36397 +static void __devinit
36398 +smi_unmap_smem(struct smifb_info *sfb)
36399 +{
36400 + if (sfb && sfb->fb.screen_base)
36401 + {
36402 + iounmap(sfb->fb.screen_base);
36403 + sfb->fb.screen_base = NULL;
36404 + }
36405 +}
36406 +
36407 +/*
36408 + * We need to wake up the LynxEM+, and make sure its in linear memory mode.
36409 + */
36410 +static inline void __devinit
36411 +smi_init_hw(void)
36412 +{
36413 + /* The delays prevent the ColdFire PCI host from locking up. :/ --NL */
36414 + udelay(1000);
36415 + outb(0x18, 0x3c4);
36416 + udelay(1000);
36417 + outb(0x11, 0x3c5);
36418 + udelay(1000);
36419 + printk("%s: 0x3c4 =%x 0x3c5 %x\n",__FUNCTION__,inw(0x3c4),inw(0x3c5));
36420 +}
36421 +
36422 +static void __devinit
36423 +smi_free_fb_info(struct smifb_info *sfb)
36424 +{
36425 + if (sfb) {
36426 + fb_alloc_cmap(&sfb->fb.cmap, 0, 0);
36427 + kfree(sfb);
36428 + }
36429 +}
36430 +
36431 +
36432 +u16 SMI_ChipIDs[numChipIDs] = {0x710, 0x712, 0x720};
36433 +
36434 +int __init smifb_init(struct pci_dev *pdev, const struct pci_device_id *ent)
36435 +{
36436 + struct smifb_info *sfb;
36437 + u_long smem_size;
36438 + char name[16];
36439 + int err;
36440 + char *m_pLAW;
36441 + ulong m_pLAWPhysical;
36442 +
36443 + printk("%s start\n",__FUNCTION__);
36444 + sprintf(name, "smifb");
36445 +
36446 + hw.chipID = pdev->device;
36447 +
36448 + err = -ENOMEM;
36449 + sfb = smi_alloc_fb_info(pdev, name);
36450 + if (!sfb) {
36451 + goto failed;
36452 + }
36453 +
36454 + smi_init_hw();
36455 +
36456 + // Map address and memory detection
36457 + m_pLAWPhysical = pci_resource_start(pdev,0);
36458 + printk("%s:m_pLAWPhysical %x,hw.chipID %x\n",__FUNCTION__,m_pLAWPhysical,hw.chipID);
36459 + switch (hw.chipID) {
36460 + case 0x710:
36461 + case 0x712:
36462 + sfb->fb.fix.mmio_start = m_pLAWPhysical + 0x00700000;
36463 + sfb->fb.fix.mmio_len = 0x00100000;
36464 +
36465 + hw.m_pLFB = SMILFB = ioremap(m_pLAWPhysical, 0x00800000);
36466 + printk("%s:SMILFB%x\n",__FUNCTION__,SMILFB);
36467 + hw.m_pMMIO = SMIRegs = SMILFB + 0x00700000;
36468 + hw.m_pDPR = hw.m_pLFB + 0x00408000;
36469 + hw.m_pVPR = hw.m_pLFB + 0x0040c000;
36470 +
36471 + if (!SMIRegs)
36472 + {
36473 + printk("%s: unable to map memory mapped IO\n",sfb->fb.fix.id);
36474 + return -ENOMEM;
36475 + }
36476 +
36477 + smi_seqw(0x62,0x7A);
36478 + smi_seqw(0x6a,0x0c);
36479 + smi_seqw(0x6b,0x02);
36480 + smem_size = 0x00400000;
36481 +
36482 + //LynxEM+ memory dection
36483 + *(u32 *)(SMILFB + 4) = 0xAA551133;
36484 + if (*(u32 *)(SMILFB + 4) != 0xAA551133)
36485 + {
36486 + smem_size = 0x00200000;
36487 + // Program the MCLK to 130 MHz
36488 + smi_seqw(0x6a,0x12);
36489 + smi_seqw(0x6b,0x02);
36490 + smi_seqw(0x62,0x3e);
36491 + }
36492 + break;
36493 + case 0x720:
36494 + sfb->fb.fix.mmio_start = m_pLAWPhysical + 0x000c0000;
36495 + sfb->fb.fix.mmio_len = 0x00040000;
36496 +
36497 + m_pLAW = ioremap(m_pLAWPhysical, 0x00a00000);
36498 + hw.m_pLFB = SMILFB = m_pLAW + 0x00200000;
36499 + hw.m_pMMIO = SMIRegs = m_pLAW + 0x000c0000;
36500 + hw.m_pDPR = m_pLAW;
36501 + hw.m_pVPR = m_pLAW + 0x800;
36502 +
36503 + smi_seqw(0x62,0xff);
36504 + smi_seqw(0x6a,0x0d);
36505 + smi_seqw(0x6b,0x02);
36506 + smem_size = 0x00400000;
36507 +
36508 + break;
36509 + }
36510 +
36511 + sfb->fb.var.xres = 640;
36512 + sfb->fb.var.yres = 480;
36513 + sfb->fb.var.bits_per_pixel = 16;
36514 +
36515 + sfb->fb.var.xres_virtual = sfb->fb.var.xres;
36516 +
36517 + sfb->fb.var.yres_virtual = sfb->fb.var.yres;
36518 +
36519 + sfb->fb.flags = FBINFO_FLAG_DEFAULT;
36520 +
36521 + printk("%s:smem_size %x\n",__FUNCTION__,smem_size);
36522 + err = smi_map_smem(sfb, pdev, smem_size);
36523 + printk("%s:smi_map_smem error %x\n",__FUNCTION__,err);
36524 + if (err) {
36525 + goto failed;
36526 + }
36527 +
36528 +
36529 +
36530 + fb_set_var(&sfb->fb, &sfb->fb.var);
36531 + smifb_check_var(&sfb->fb.var, &sfb->fb);
36532 + smifb_set_par(sfb);
36533 + printk("%s:register_framebuffer \n",__FUNCTION__);
36534 + err = register_framebuffer(&sfb->fb);
36535 + if (err < 0) {
36536 + goto failed;
36537 + }
36538 +
36539 + printk("Silicon Motion, Inc. LynxEM+ Init complete.\n");
36540 +
36541 + return 0;
36542 +
36543 +failed:
36544 + smi_unmap_smem(sfb);
36545 + smi_unmap_mmio(sfb);
36546 + smi_free_fb_info(sfb);
36547 + printk("Silicon Motion, Inc. LynxEM+ Init FAILED.n");
36548 +
36549 + return err;
36550 +}
36551 +
36552 +struct pci_device_id smifb_pci_tbl[] = {
36553 + { 0x126f, 0x710, PCI_ANY_ID, PCI_ANY_ID },
36554 + { 0x126f, 0x712, PCI_ANY_ID, PCI_ANY_ID },
36555 + { 0x126f, 0x720, PCI_ANY_ID, PCI_ANY_ID },
36556 + { 0 }
36557 +};
36558 +
36559 +MODULE_DEVICE_TABLE(pci, smifb_pci_tbl);
36560 +
36561 +struct pci_driver smifb_driver = {
36562 + .name = "smifb",
36563 + .id_table = smifb_pci_tbl,
36564 + .probe = smifb_init,
36565 +};
36566 +
36567 +int __init smi_init(void)
36568 +{
36569 + /*return pci_module_init(&smifb_driver);*/
36570 + return pci_register_driver(&smifb_driver);
36571 +}
36572 +
36573 +module_init(smi_init);
36574 +MODULE_LICENSE("GPL");
36575 +
36576 +
36577 +
36578 --- /dev/null
36579 +++ b/drivers/video/smifb.h
36580 @@ -0,0 +1,149 @@
36581 +/***************************************************************************
36582 + smifb.h - SiliconMotion LynxEM+ frame buffer device
36583 + -------------------
36584 + begin : Thu Aug 9 2001
36585 + copyright : (C) 2001 by Szu-Tao Huang
36586 + email : johuang@siliconmotion.com
36587 + ***************************************************************************/
36588 +
36589 +/***************************************************************************
36590 + * *
36591 + * This program is free software; you can redistribute it and/or modify *
36592 + * it under the terms of the GNU General Public License as published by *
36593 + * the Free Software Foundation; either version 2 of the License, or *
36594 + * (at your option) any later version. *
36595 + * *
36596 + ***************************************************************************/
36597 +
36598 +#define smi_mmiowb(dat,reg) writeb(dat, SMIRegs + reg)
36599 +#define smi_mmioww(dat,reg) writew(dat, SMIRegs + reg)
36600 +#define smi_mmiowl(dat,reg) writel(dat, SMIRegs + reg)
36601 +
36602 +#define smi_mmiorb(reg) readb(SMIRegs + reg)
36603 +#define smi_mmiorw(reg) readw(SMIRegs + reg)
36604 +#define smi_mmiorl(reg) readl(SMIRegs + reg)
36605 +
36606 +#define SIZE_SR00_SR04 (0x04 - 0x00 + 1)
36607 +#define SIZE_SR10_SR24 (0x24 - 0x10 + 1)
36608 +#define SIZE_SR30_SR75 (0x75 - 0x30 + 1)
36609 +#define SIZE_SR80_SR93 (0x93 - 0x80 + 1)
36610 +#define SIZE_SRA0_SRAF (0xAF - 0xA0 + 1)
36611 +#define SIZE_GR00_GR08 (0x08 - 0x00 + 1)
36612 +#define SIZE_AR00_AR14 (0x14 - 0x00 + 1)
36613 +#define SIZE_CR00_CR18 (0x18 - 0x00 + 1)
36614 +#define SIZE_CR30_CR4D (0x4D - 0x30 + 1)
36615 +#define SIZE_CR90_CRA7 (0xA7 - 0x90 + 1)
36616 +#define SIZE_VPR (0x6C + 1)
36617 +#define SIZE_DPR (0x44 + 1)
36618 +
36619 +#define numVGAModes 6
36620 +#define numChipIDs 3
36621 +
36622 +#define NR_PALETTE 256
36623 +#define NR_RGB 2
36624 +
36625 +/*
36626 + * Minimum X and Y resolutions
36627 + */
36628 +#define MIN_XRES 640
36629 +#define MIN_YRES 480
36630 +
36631 +static inline void smi_crtcw(int reg, int val)
36632 +{
36633 + smi_mmiowb(reg, 0x3d4);
36634 + smi_mmiowb(val, 0x3d5);
36635 +}
36636 +
36637 +static inline unsigned int smi_crtcr(int reg)
36638 +{
36639 + smi_mmiowb(reg, 0x3d4);
36640 + return smi_mmiorb(0x3d5);
36641 +}
36642 +
36643 +static inline void smi_grphw(int reg, int val)
36644 +{
36645 + smi_mmiowb(reg, 0x3ce);
36646 + smi_mmiowb(val, 0x3cf);
36647 +}
36648 +
36649 +static inline unsigned int smi_grphr(int reg)
36650 +{
36651 + smi_mmiowb(reg, 0x3ce);
36652 + return smi_mmiorb(0x3cf);
36653 +}
36654 +
36655 +static inline void smi_attrw(int reg, int val)
36656 +{
36657 + smi_mmiorb(0x3da);
36658 + smi_mmiowb(reg, 0x3c0);
36659 + smi_mmiorb(0x3c1);
36660 + smi_mmiowb(val, 0x3c0);
36661 +}
36662 +
36663 +static inline void smi_seqw(int reg, int val)
36664 +{
36665 + smi_mmiowb(reg, 0x3c4);
36666 + smi_mmiowb(val, 0x3c5);
36667 +}
36668 +
36669 +static inline unsigned int smi_seqr(int reg)
36670 +{
36671 + smi_mmiowb(reg, 0x3c4);
36672 + return smi_mmiorb(0x3c5);
36673 +}
36674 +/*
36675 +* Private structure
36676 +*/
36677 +struct smifb_info {
36678 + /*
36679 + * The following is a pointer to be passed into the
36680 + * functions below. The modules outside the main
36681 + * smifb.c driver have no knowledge as to what
36682 + * is within this structure.
36683 + */
36684 + struct fb_info fb;
36685 + struct display_switch *dispsw;
36686 + struct pci_dev *dev;
36687 + signed int currcon;
36688 +
36689 + struct {
36690 + u8 red, green, blue;
36691 + } palette[NR_RGB];
36692 +
36693 + u_int palette_size;
36694 +};
36695 +
36696 +struct par_info {
36697 + /*
36698 + * Hardware
36699 + */
36700 + u16 chipID;
36701 + char *m_pLFB;
36702 + char *m_pMMIO;
36703 + char *m_pDPR;
36704 + char *m_pVPR;
36705 +
36706 + u_int width;
36707 + u_int height;
36708 + u_int hz;
36709 +};
36710 +
36711 +// The next structure holds all information relevant for a specific video mode.
36712 +struct ModeInit
36713 +{
36714 + int mmSizeX;
36715 + int mmSizeY;
36716 + int bpp;
36717 + int hz;
36718 + unsigned char Init_MISC;
36719 + unsigned char Init_SR00_SR04[SIZE_SR00_SR04];
36720 + unsigned char Init_SR10_SR24[SIZE_SR10_SR24];
36721 + unsigned char Init_SR30_SR75[SIZE_SR30_SR75];
36722 + unsigned char Init_SR80_SR93[SIZE_SR80_SR93];
36723 + unsigned char Init_SRA0_SRAF[SIZE_SRA0_SRAF];
36724 + unsigned char Init_GR00_GR08[SIZE_GR00_GR08];
36725 + unsigned char Init_AR00_AR14[SIZE_AR00_AR14];
36726 + unsigned char Init_CR00_CR18[SIZE_CR00_CR18];
36727 + unsigned char Init_CR30_CR4D[SIZE_CR30_CR4D];
36728 + unsigned char Init_CR90_CRA7[SIZE_CR90_CRA7];
36729 +};
36730 --- a/drivers/watchdog/Kconfig
36731 +++ b/drivers/watchdog/Kconfig
36732 @@ -672,6 +672,15 @@ config TXX9_WDT
36733
36734 # PARISC Architecture
36735
36736 +# ColdFire Architecture
36737 +
36738 +config COLDFIRE_WATCHDOG
36739 + tristate "ColdFire watchdog support"
36740 + depends on WATCHDOG
36741 + help
36742 + To compile this driver as a module, choose M here: the
36743 + module will be called softdog.
36744 +
36745 # POWERPC Architecture
36746
36747 config MPC5200_WDT
36748 --- a/drivers/watchdog/Makefile
36749 +++ b/drivers/watchdog/Makefile
36750 @@ -86,6 +86,7 @@ obj-$(CONFIG_SBC_EPX_C3_WATCHDOG) += sbc
36751 # M32R Architecture
36752
36753 # M68K Architecture
36754 +obj-$(CONFIG_COLDFIRE_WATCHDOG) += mcf_wdt.o
36755
36756 # M68KNOMMU Architecture
36757
36758 --- /dev/null
36759 +++ b/drivers/watchdog/mcf_wdt.c
36760 @@ -0,0 +1,220 @@
36761 +/*
36762 + * drivers/watchdog/mcf_wdt.c
36763 + *
36764 + * Watchdog driver for ColdFire processors
36765 + *
36766 + * Adapted from the IXP4xx watchdog driver.
36767 + * The original version carries these notices:
36768 + *
36769 + * Author: Deepak Saxena <dsaxena@plexity.net>
36770 + *
36771 + * Copyright 2004 (c) MontaVista, Software, Inc.
36772 + * Based on sa1100 driver, Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
36773 + *
36774 + * This file is licensed under the terms of the GNU General Public
36775 + * License version 2. This program is licensed "as is" without any
36776 + * warranty of any kind, whether express or implied.
36777 + */
36778 +
36779 +#include <linux/module.h>
36780 +#include <linux/moduleparam.h>
36781 +#include <linux/types.h>
36782 +#include <linux/kernel.h>
36783 +#include <linux/fs.h>
36784 +#include <linux/miscdevice.h>
36785 +#include <linux/watchdog.h>
36786 +#include <linux/init.h>
36787 +#include <linux/bitops.h>
36788 +
36789 +#include <asm-m68k/uaccess.h>
36790 +#include <asm-m68k/coldfire.h>
36791 +#include <asm-m68k/m5485gpt.h>
36792 +
36793 +static int nowayout;
36794 +static unsigned int heartbeat = 30; /* (secs) Default is 0.5 minute */
36795 +static unsigned long wdt_status;
36796 +
36797 +#define WDT_IN_USE 0
36798 +#define WDT_OK_TO_CLOSE 1
36799 +
36800 +static unsigned long wdt_tick_rate;
36801 +
36802 +static void
36803 +wdt_enable(void)
36804 +{
36805 + MCF_GPT_GMS0 = 0;
36806 + MCF_GPT_GCIR0 = MCF_GPT_GCIR_PRE(heartbeat*wdt_tick_rate) |
36807 + MCF_GPT_GCIR_CNT(0xffff);
36808 + MCF_GPT_GMS0 = MCF_GPT_GMS_OCPW(0xA5) | MCF_GPT_GMS_WDEN |
36809 + MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS_GPIO;
36810 +}
36811 +
36812 +static void
36813 +wdt_disable(void)
36814 +{
36815 + MCF_GPT_GMS0 = 0;
36816 +}
36817 +
36818 +static void
36819 +wdt_keepalive(void)
36820 +{
36821 + MCF_GPT_GMS0 = MCF_GPT_GMS_OCPW(0xA5) | MCF_GPT_GMS0;
36822 +}
36823 +
36824 +static int
36825 +mcf_wdt_open(struct inode *inode, struct file *file)
36826 +{
36827 + if (test_and_set_bit(WDT_IN_USE, &wdt_status))
36828 + return -EBUSY;
36829 +
36830 + clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
36831 +
36832 + wdt_enable();
36833 +
36834 + return nonseekable_open(inode, file);
36835 +}
36836 +
36837 +static ssize_t
36838 +mcf_wdt_write(struct file *file, const char *data, size_t len, loff_t *ppos)
36839 +{
36840 + if (len) {
36841 + if (!nowayout) {
36842 + size_t i;
36843 +
36844 + clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
36845 +
36846 + for (i = 0; i != len; i++) {
36847 + char c;
36848 +
36849 + if (get_user(c, data + i))
36850 + return -EFAULT;
36851 + if (c == 'V')
36852 + set_bit(WDT_OK_TO_CLOSE, &wdt_status);
36853 + }
36854 + }
36855 + wdt_keepalive();
36856 + }
36857 +
36858 + return len;
36859 +}
36860 +
36861 +
36862 +static struct watchdog_info ident = {
36863 + .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT |
36864 + WDIOF_KEEPALIVEPING,
36865 + .identity = "Coldfire Watchdog",
36866 +};
36867 +
36868 +static int
36869 +mcf_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
36870 + unsigned long arg)
36871 +{
36872 + int ret = -ENOIOCTLCMD;
36873 + int time;
36874 +
36875 + switch (cmd) {
36876 + case WDIOC_GETSUPPORT:
36877 + ret = copy_to_user((struct watchdog_info *)arg, &ident,
36878 + sizeof(ident)) ? -EFAULT : 0;
36879 + break;
36880 +
36881 + case WDIOC_GETSTATUS:
36882 + ret = put_user(0, (int *)arg);
36883 + break;
36884 +
36885 + case WDIOC_GETBOOTSTATUS:
36886 + ret = put_user(0, (int *)arg);
36887 + break;
36888 +
36889 + case WDIOC_SETTIMEOUT:
36890 + ret = get_user(time, (int *)arg);
36891 + if (ret)
36892 + break;
36893 +
36894 + if (time <= 0 || time > 30) {
36895 + ret = -EINVAL;
36896 + break;
36897 + }
36898 +
36899 + heartbeat = time;
36900 + wdt_enable();
36901 + /* Fall through */
36902 +
36903 + case WDIOC_GETTIMEOUT:
36904 + ret = put_user(heartbeat, (int *)arg);
36905 + break;
36906 +
36907 + case WDIOC_KEEPALIVE:
36908 + wdt_keepalive();
36909 + ret = 0;
36910 + break;
36911 + }
36912 +
36913 + return ret;
36914 +}
36915 +
36916 +static int
36917 +mcf_wdt_release(struct inode *inode, struct file *file)
36918 +{
36919 + if (test_bit(WDT_OK_TO_CLOSE, &wdt_status)) {
36920 + wdt_disable();
36921 + } else {
36922 + printk(KERN_CRIT "WATCHDOG: Device closed unexpectdly - "
36923 + "timer will not stop\n");
36924 + }
36925 +
36926 + clear_bit(WDT_IN_USE, &wdt_status);
36927 + clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
36928 +
36929 + return 0;
36930 +}
36931 +
36932 +
36933 +static struct file_operations mcf_wdt_fops = {
36934 + .owner = THIS_MODULE,
36935 + .llseek = no_llseek,
36936 + .write = mcf_wdt_write,
36937 + .ioctl = mcf_wdt_ioctl,
36938 + .open = mcf_wdt_open,
36939 + .release = mcf_wdt_release,
36940 +};
36941 +
36942 +static struct miscdevice mcf_wdt_miscdev = {
36943 + .minor = WATCHDOG_MINOR,
36944 + .name = "watchdog",
36945 + .fops = &mcf_wdt_fops,
36946 +};
36947 +
36948 +static int __init mcf_wdt_init(void)
36949 +{
36950 + wdt_tick_rate = MCF_BUSCLK/0xffff;
36951 +#ifdef CONFIG_WATCHDOG_NOWAYOUT
36952 + nowayout = 1;
36953 +#else
36954 + nowayout = 0;
36955 +#endif
36956 + printk("ColdFire watchdog driver is loaded.\n");
36957 +
36958 + return misc_register(&mcf_wdt_miscdev);
36959 +}
36960 +
36961 +static void __exit mcf_wdt_exit(void)
36962 +{
36963 + misc_deregister(&mcf_wdt_miscdev);
36964 +}
36965 +
36966 +module_init(mcf_wdt_init);
36967 +module_exit(mcf_wdt_exit);
36968 +
36969 +MODULE_AUTHOR("Deepak Saxena");
36970 +MODULE_DESCRIPTION("ColdFire Watchdog");
36971 +
36972 +module_param(heartbeat, int, 0);
36973 +MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds (default 60s)");
36974 +
36975 +module_param(nowayout, int, 0);
36976 +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
36977 +
36978 +MODULE_LICENSE("GPL");
36979 +MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
36980 +
36981 --- a/fs/namespace.c
36982 +++ b/fs/namespace.c
36983 @@ -1364,7 +1364,11 @@ int copy_mount_options(const void __user
36984 /* copy_from_user cannot cross TASK_SIZE ! */
36985 size = TASK_SIZE - (unsigned long)data;
36986 if (size > PAGE_SIZE)
36987 +#ifndef CONFIG_COLDFIRE
36988 size = PAGE_SIZE;
36989 +#else
36990 + size = PAGE_SIZE - ((unsigned long)data & ~PAGE_MASK);
36991 +#endif
36992
36993 i = size - exact_copy_from_user((void *)page, data, size);
36994 if (!i) {
36995 --- /dev/null
36996 +++ b/include/asm-m68k/5445x_pci.h
36997 @@ -0,0 +1,94 @@
36998 +/*
36999 + * asm-m68k/pci.h - m68k specific PCI declarations.
37000 + *
37001 + * Coldfire Implementation Copyright (c) 2007 Freescale Semiconductor, Inc.
37002 + * Kurt Mahan <kmahan@freescale.com>
37003 + */
37004 +#ifndef _ASM_M68K_5445X_PCI_H
37005 +#define _ASM_M68K_5445x_PCI_H
37006 +
37007 +#ifndef CONFIG_PCI
37008 +/*
37009 + * The PCI address space does equal the physical memory
37010 + * address space. The networking and block device layers use
37011 + * this boolean for bounce buffer decisions.
37012 + */
37013 +#define PCI_DMA_BUS_IS_PHYS (1)
37014 +#else
37015 +#include <asm-generic/pci-dma-compat.h>
37016 +
37017 +/*
37018 + * The PCI address space does equal the physical memory
37019 + * address space. The networking and block device layers use
37020 + * this boolean for bounce buffer decisions.
37021 + */
37022 +#define PCI_DMA_BUS_IS_PHYS (1)
37023 +
37024 +#define PCIBIOS_MIN_IO 0x00004000
37025 +#define PCIBIOS_MIN_MEM 0x02000000
37026 +
37027 +#define pcibios_assign_all_busses() 0
37028 +#define pcibios_scan_all_fns(a, b) 0
37029 +
37030 +static inline void
37031 +pcibios_set_master(struct pci_dev *dev)
37032 +{
37033 + /* no special bus mastering setup handling */
37034 +}
37035 +
37036 +static inline void
37037 +pcibios_penalize_isa_irq(int irq, int active)
37038 +{
37039 + /* no dynamic PCI IRQ allocation */
37040 +}
37041 +
37042 +#if 0
37043 +static inline void
37044 +pcibios_add_platform_entries(struct pci_dev *dev)
37045 +{
37046 + /* no special handling */
37047 +}
37048 +#endif
37049 +
37050 +static inline void
37051 +pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
37052 + struct resource *res)
37053 +{
37054 +#ifdef CONFIG_M54455
37055 + if ((res->start == 0xa0000000) || (res->start == 0xa8000000)) {
37056 + /* HACK! FIX! kludge to fix bridge mapping */
37057 + region->start = res->start & 0x0fffffff;
37058 + region->end = res->end & 0x0fffffff;
37059 + } else {
37060 + region->start = res->start;
37061 + region->end = res->end;
37062 + }
37063 +#else
37064 + region->start = res->start;
37065 + region->end = res->end;
37066 +#endif
37067 +}
37068 +
37069 +static inline void
37070 +pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
37071 + struct pci_bus_region *region)
37072 +{
37073 + res->start = region->start;
37074 + res->end = region->end;
37075 +}
37076 +
37077 +static inline struct resource *
37078 +pcibios_select_root(struct pci_dev *pdev, struct resource *res)
37079 +{
37080 + struct resource *root = NULL;
37081 +
37082 + if (res->flags & IORESOURCE_IO)
37083 + root = &ioport_resource;
37084 + if (res->flags & IORESOURCE_MEM)
37085 + root = &iomem_resource;
37086 +
37087 + return root;
37088 +}
37089 +
37090 +#endif /* CONFIG_PCI */
37091 +#endif /* _ASM_M68K_5445X_PCI_H */
37092 --- /dev/null
37093 +++ b/include/asm-m68k/548x_pci.h
37094 @@ -0,0 +1,99 @@
37095 +#ifndef _ASM_M68K_548X_PCI_H
37096 +#define _ASM_M68K_548X_PCI_H
37097 +
37098 +/*
37099 + * asm-m68k/pci_m68k.h - m68k specific PCI declarations.
37100 + *
37101 + * Written by Wout Klaren.
37102 + */
37103 +#include <linux/mm.h>
37104 +#include <asm/scatterlist.h>
37105 +
37106 +#include <asm-generic/pci.h>
37107 +
37108 +struct pci_ops;
37109 +
37110 +/*
37111 + * Structure with hardware dependent information and functions of the
37112 + * PCI bus.
37113 + */
37114 +
37115 +struct pci_bus_info
37116 +{
37117 + /*
37118 + * Resources of the PCI bus.
37119 + */
37120 +
37121 + struct resource mem_space;
37122 + struct resource io_space;
37123 +
37124 + /*
37125 + * System dependent functions.
37126 + */
37127 +
37128 + struct pci_ops *m68k_pci_ops;
37129 +
37130 + void (*fixup)(int pci_modify);
37131 + void (*conf_device)(struct pci_dev *dev);
37132 +};
37133 +
37134 +#define pcibios_assign_all_busses() 0
37135 +#define pcibios_scan_all_fns(a, b) 0
37136 +
37137 +static inline void pcibios_set_master(struct pci_dev *dev)
37138 +{
37139 + /* No special bus mastering setup handling */
37140 +}
37141 +
37142 +static inline void pcibios_penalize_isa_irq(int irq)
37143 +{
37144 + /* We don't do dynamic PCI IRQ allocation */
37145 +}
37146 +
37147 +#ifndef CONFIG_COLDFIRE
37148 +/* The PCI address space does equal the physical memory
37149 + * address space. The networking and block device layers use
37150 + * this boolean for bounce buffer decisions.
37151 + */
37152 +#define PCI_DMA_BUS_IS_PHYS (1)
37153 +
37154 +#define PCIBIOS_MIN_IO 0x00004000
37155 +#define PCIBIOS_MIN_MEM 0x04000000
37156 +
37157 +#else /* !CONFIG_COLDFIRE */
37158 +#include <asm-generic/pci-dma-compat.h>
37159 +#define PCI_DMA_BASE /*0x40000000*/0 /* PCI-DMA window base */
37160 +
37161 +extern struct pci_bus_info *__init init_coldfire_pci(void);
37162 +extern void * pci_alloc_son(struct pci_dev *, size_t,
37163 + dma_addr_t *, int);
37164 +/*
37165 + * The PCI address space equal the virtual memory
37166 + * address space on m547X/m548X.
37167 + */
37168 +#define PCI_DMA_BUS_IS_PHYS (1)
37169 +
37170 +#define PCIBIOS_MIN_IO 0x00000100
37171 +#define PCIBIOS_MIN_MEM 0x02000000
37172 +
37173 +struct scatterlist;
37174 +
37175 +
37176 +/* This is always fine. */
37177 +#define pci_dac_dma_supported(pci_dev, mask) (1)
37178 +
37179 +
37180 +/* These macros should be used after a pci_map_sg call has been done
37181 + * to get bus addresses of each of the SG entries and their lengths.
37182 + * You should only work with the number of sg entries pci_map_sg
37183 + * returns.
37184 + */
37185 +#define sg_dma_address(sg) ((sg)->dma_address)
37186 +#define sg_dma_len(sg) ((sg)->length)
37187 +
37188 +static inline void pcibios_align_resource(void *data, struct resource *res, unsigned long size, unsigned long align)
37189 +{
37190 +}
37191 +
37192 +#endif /* !CONFIG_COLDFIRE*/
37193 +#endif /* _ASM_M68K_548X_PCI_H */
37194 --- a/include/asm-m68k/atomic.h
37195 +++ b/include/asm-m68k/atomic.h
37196 @@ -2,7 +2,7 @@
37197 #define __ARCH_M68K_ATOMIC__
37198
37199
37200 -#include <asm/system.h>
37201 +#include <asm/system.h> /* local_irq_XXX() */
37202
37203 /*
37204 * Atomic operations that C can't guarantee us. Useful for
37205 @@ -21,12 +21,20 @@ typedef struct { int counter; } atomic_t
37206
37207 static inline void atomic_add(int i, atomic_t *v)
37208 {
37209 +#ifndef CONFIG_COLDFIRE
37210 __asm__ __volatile__("addl %1,%0" : "+m" (*v) : "id" (i));
37211 +#else
37212 + __asm__ __volatile__("addl %1,%0" : "=m" (*v) : "d" (i), "m" (*v));
37213 +#endif
37214 }
37215
37216 static inline void atomic_sub(int i, atomic_t *v)
37217 {
37218 +#ifndef CONFIG_COLDFIRE
37219 __asm__ __volatile__("subl %1,%0" : "+m" (*v) : "id" (i));
37220 +#else
37221 + __asm__ __volatile__("subl %1,%0" : "=m" (*v) : "d" (i), "m" (*v));
37222 +#endif
37223 }
37224
37225 static inline void atomic_inc(atomic_t *v)
37226 @@ -46,6 +54,14 @@ static inline int atomic_dec_and_test(at
37227 return c != 0;
37228 }
37229
37230 +static __inline__ int atomic_dec_and_test_lt(volatile atomic_t *v)
37231 +{
37232 + char c;
37233 + __asm__ __volatile__("subql #1,%1; slt %0" : "=d" (c), "=m" (*v)
37234 + : "m" (*v));
37235 + return c != 0 ;
37236 +}
37237 +
37238 static inline int atomic_inc_and_test(atomic_t *v)
37239 {
37240 char c;
37241 @@ -156,7 +172,12 @@ static inline int atomic_sub_and_test(in
37242 static inline int atomic_add_negative(int i, atomic_t *v)
37243 {
37244 char c;
37245 +#ifndef CONFIG_COLDFIRE
37246 __asm__ __volatile__("addl %2,%1; smi %0" : "=d" (c), "+m" (*v): "g" (i));
37247 +#else
37248 + __asm__ __volatile__("addl %2,%1; smi %0" : "=d" (c), "=m" (*v)
37249 + : "d" (i) , "m" (*v));
37250 +#endif
37251 return c != 0;
37252 }
37253
37254 --- a/include/asm-m68k/auxvec.h
37255 +++ b/include/asm-m68k/auxvec.h
37256 @@ -1,4 +1,13 @@
37257 #ifndef __ASMm68k_AUXVEC_H
37258 #define __ASMm68k_AUXVEC_H
37259 +/*
37260 + * Architecture-neutral AT_ values in 0-17, leave some room
37261 + * for more of them.
37262 + */
37263 +
37264 +#ifdef CONFIG_VSYSCALL
37265 +/* Entry point to the vsyscall page */
37266 +#define AT_SYSINFO_EHDR 33
37267 +#endif
37268
37269 #endif
37270 --- a/include/asm-m68k/bitops.h
37271 +++ b/include/asm-m68k/bitops.h
37272 @@ -19,6 +19,7 @@
37273 *
37274 * They use the standard big-endian m680x0 bit ordering.
37275 */
37276 +#ifndef CONFIG_COLDFIRE
37277
37278 #define test_and_set_bit(nr,vaddr) \
37279 (__builtin_constant_p(nr) ? \
37280 @@ -457,4 +458,503 @@ static inline int ext2_find_next_bit(con
37281
37282 #endif /* __KERNEL__ */
37283
37284 +#else /* CONFIG_COLDFIRE */
37285 +
37286 +#define test_and_set_bit(nr,vaddr) \
37287 + (__builtin_constant_p(nr) ? \
37288 + __constant_coldfire_test_and_set_bit(nr, vaddr) : \
37289 + __generic_coldfire_test_and_set_bit(nr, vaddr))
37290 +
37291 +#if 0
37292 +static __inline__ int __constant_coldfire_test_and_set_bit(int nr,
37293 + volatile void *vaddr)
37294 +{
37295 + char retval;
37296 + volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
37297 +
37298 + __asm__ __volatile__ ("bset %2,%1; sne %0"
37299 + : "=d" (retval), "+QUd" (*p)
37300 + : "di" (nr & 7));
37301 + return retval;
37302 +}
37303 +#else
37304 +static __inline__ int __constant_coldfire_test_and_set_bit(int nr,
37305 + volatile void *vaddr)
37306 +{
37307 + char retval;
37308 + volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
37309 + __asm__ __volatile__ ("bset %2,(%4); sne %0"
37310 + : "=d" (retval), "=m" (*p)
37311 + : "di" (nr & 7), "m" (*p), "a" (p));
37312 + return retval;
37313 +}
37314 +#endif
37315 +
37316 +static __inline__ int __generic_coldfire_test_and_set_bit(int nr,
37317 + volatile void *vaddr)
37318 +{
37319 + char retval;
37320 +
37321 + __asm__ __volatile__ ("bset %2,%1; sne %0"
37322 + : "=d" (retval), "=m" (((volatile char *)vaddr)[(nr^31) >> 3])
37323 + : "d" (nr)
37324 + : "memory");
37325 + return retval;
37326 +}
37327 +#define __test_and_set_bit(nr, vaddr) test_and_set_bit(nr, vaddr)
37328 +
37329 +#define set_bit(nr,vaddr) \
37330 + (__builtin_constant_p(nr) ? \
37331 + __constant_coldfire_set_bit(nr, vaddr) : \
37332 + __generic_coldfire_set_bit(nr, vaddr))
37333 +
37334 +#if 0
37335 +static __inline__ void __constant_coldfire_set_bit(int nr,
37336 + volatile void *vaddr)
37337 +{
37338 + volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
37339 + __asm__ __volatile__ ("bset %1,%0"
37340 + : "+QUd" (*p) : "di" (nr & 7));
37341 +}
37342 +#else
37343 +static __inline__ void __constant_coldfire_set_bit(int nr,
37344 + volatile void *vaddr)
37345 +{
37346 + volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
37347 + __asm__ __volatile__ ("bset %1,(%3)"
37348 + : "=m" (*p) : "di" (nr & 7), "m" (*p), "a" (p));
37349 +}
37350 +#endif
37351 +
37352 +static __inline__ void __generic_coldfire_set_bit(int nr,
37353 + volatile void *vaddr)
37354 +{
37355 + __asm__ __volatile__ ("bset %1,%0"
37356 + : "=m" (((volatile char *)vaddr)[(nr^31) >> 3])
37357 + : "d" (nr)
37358 + : "memory");
37359 +}
37360 +#define __set_bit(nr, vaddr) set_bit(nr, vaddr)
37361 +
37362 +#define test_and_clear_bit(nr, vaddr) \
37363 + (__builtin_constant_p(nr) ? \
37364 + __constant_coldfire_test_and_clear_bit(nr, vaddr) : \
37365 + __generic_coldfire_test_and_clear_bit(nr, vaddr))
37366 +
37367 +#if 0
37368 +static __inline__ int __constant_coldfire_test_and_clear_bit(int nr,
37369 + volatile void *vaddr)
37370 +{
37371 + char retval;
37372 + volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
37373 +
37374 + __asm__ __volatile__ ("bclr %2,%1; sne %0"
37375 + : "=d" (retval), "+QUd" (*p)
37376 + : "id" (nr & 7));
37377 +
37378 + return retval;
37379 +}
37380 +#else
37381 +static __inline__ int __constant_coldfire_test_and_clear_bit(int nr,
37382 + volatile void *vaddr)
37383 +{
37384 + char retval;
37385 + volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
37386 +
37387 + __asm__ __volatile__ ("bclr %2,(%4); sne %0"
37388 + : "=d" (retval), "=m" (*p)
37389 + : "id" (nr & 7), "m" (*p), "a" (p));
37390 +
37391 + return retval;
37392 +}
37393 +#endif
37394 +
37395 +static __inline__ int __generic_coldfire_test_and_clear_bit(int nr,
37396 + volatile void *vaddr)
37397 +{
37398 + char retval;
37399 +
37400 + __asm__ __volatile__ ("bclr %2,%1; sne %0"
37401 + : "=d" (retval), "=m" (((volatile char *)vaddr)[(nr^31) >> 3])
37402 + : "d" (nr & 7)
37403 + : "memory");
37404 +
37405 + return retval;
37406 +}
37407 +#define __test_and_clear_bit(nr, vaddr) test_and_clear_bit(nr, vaddr)
37408 +
37409 +/*
37410 + * clear_bit() doesn't provide any barrier for the compiler.
37411 + */
37412 +#define smp_mb__before_clear_bit() barrier()
37413 +#define smp_mb__after_clear_bit() barrier()
37414 +
37415 +#define clear_bit(nr,vaddr) \
37416 + (__builtin_constant_p(nr) ? \
37417 + __constant_coldfire_clear_bit(nr, vaddr) : \
37418 + __generic_coldfire_clear_bit(nr, vaddr))
37419 +
37420 +#if 0
37421 +static __inline__ void __constant_coldfire_clear_bit(int nr,
37422 + volatile void *vaddr)
37423 +{
37424 + volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
37425 + __asm__ __volatile__ ("bclr %1,%0"
37426 + : "+QUd" (*p) : "id" (nr & 7));
37427 +}
37428 +#else
37429 +static __inline__ void __constant_coldfire_clear_bit(int nr,
37430 + volatile void *vaddr)
37431 +{
37432 + volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
37433 + __asm__ __volatile__ ("bclr %1,(%3)"
37434 + : "=m" (*p) : "id" (nr & 7), "m" (*p), "a" (p));
37435 +}
37436 +#endif
37437 +
37438 +static __inline__ void __generic_coldfire_clear_bit(int nr,
37439 + volatile void *vaddr)
37440 +{
37441 + __asm__ __volatile__ ("bclr %1,%0"
37442 + : "=m" (((volatile char *)vaddr)[(nr^31) >> 3])
37443 + : "d" (nr)
37444 + : "memory");
37445 +}
37446 +#define __clear_bit(nr, vaddr) clear_bit(nr, vaddr)
37447 +
37448 +#define test_and_change_bit(nr, vaddr) \
37449 + (__builtin_constant_p(nr) ? \
37450 + __constant_coldfire_test_and_change_bit(nr, vaddr) : \
37451 + __generic_coldfire_test_and_change_bit(nr, vaddr))
37452 +
37453 +#if 0
37454 +static __inline__ int __constant_coldfire_test_and_change_bit(int nr,
37455 + volatile void *vaddr)
37456 +{
37457 + char retval;
37458 + volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
37459 +
37460 + __asm__ __volatile__ ("bchg %2,%1; sne %0"
37461 + : "=d" (retval), "+QUd" (*p)
37462 + : "id" (nr & 7));
37463 +
37464 + return retval;
37465 +}
37466 +#else
37467 +static __inline__ int __constant_coldfire_test_and_change_bit(int nr,
37468 + volatile void *vaddr)
37469 +{
37470 + char retval;
37471 + volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
37472 +
37473 + __asm__ __volatile__ ("bchg %2,(%4); sne %0"
37474 + : "=d" (retval), "=m" (*p)
37475 + : "id" (nr & 7), "m" (*p), "a" (p));
37476 +
37477 + return retval;
37478 +}
37479 +#endif
37480 +
37481 +static __inline__ int __generic_coldfire_test_and_change_bit(int nr,
37482 + volatile void *vaddr)
37483 +{
37484 + char retval;
37485 +
37486 + __asm__ __volatile__ ("bchg %2,%1; sne %0"
37487 + : "=d" (retval), "=m" (((volatile char *)vaddr)[(nr^31) >> 3])
37488 + : "id" (nr)
37489 + : "memory");
37490 +
37491 + return retval;
37492 +}
37493 +#define __test_and_change_bit(nr, vaddr) test_and_change_bit(nr, vaddr)
37494 +#define __change_bit(nr, vaddr) change_bit(nr, vaddr)
37495 +
37496 +#define change_bit(nr,vaddr) \
37497 + (__builtin_constant_p(nr) ? \
37498 + __constant_coldfire_change_bit(nr, vaddr) : \
37499 + __generic_coldfire_change_bit(nr, vaddr))
37500 +
37501 +#if 0
37502 +static __inline__ void __constant_coldfire_change_bit(int nr,
37503 + volatile void *vaddr)
37504 +{
37505 + volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
37506 + __asm__ __volatile__ ("bchg %1,%0"
37507 + : "+QUd" (*p) : "id" (nr & 7));
37508 +}
37509 +#else
37510 +static __inline__ void __constant_coldfire_change_bit(int nr,
37511 + volatile void *vaddr)
37512 +{
37513 + volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
37514 + __asm__ __volatile__ ("bchg %1,(%3)"
37515 + : "=m" (*p) : "id" (nr & 7), "m" (*p), "a" (p));
37516 +}
37517 +#endif
37518 +
37519 +static __inline__ void __generic_coldfire_change_bit(int nr,
37520 + volatile void *vaddr)
37521 +{
37522 + __asm__ __volatile__ ("bchg %1,%0"
37523 + : "=m" (((volatile char *)vaddr)[(nr^31) >> 3])
37524 + : "d" (nr)
37525 + : "memory");
37526 +}
37527 +
37528 +static inline int test_bit(int nr, const unsigned long *vaddr)
37529 +{
37530 + return (vaddr[nr >> 5] & (1UL << (nr & 31))) != 0;
37531 +}
37532 +
37533 +static __inline__ unsigned long ffz(unsigned long word)
37534 +{
37535 + unsigned long result = 0;
37536 +
37537 + while (word & 1) {
37538 + result++;
37539 + word >>= 1;
37540 + }
37541 + return result;
37542 +}
37543 +
37544 +/* find_next_zero_bit() finds the first zero bit in a bit string of length
37545 + * 'size' bits, starting the search at bit 'offset'. This is largely based
37546 + * on Linus's ALPHA routines.
37547 + */
37548 +static __inline__ unsigned long find_next_zero_bit(void *addr,
37549 + unsigned long size, unsigned long offset)
37550 +{
37551 + unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
37552 + unsigned long result = offset & ~31UL;
37553 + unsigned long tmp;
37554 +
37555 + if (offset >= size)
37556 + return size;
37557 + size -= result;
37558 + offset &= 31UL;
37559 + if (offset) {
37560 + tmp = *(p++);
37561 + tmp |= ~0UL >> (32-offset);
37562 + if (size < 32)
37563 + goto found_first;
37564 + if (~tmp)
37565 + goto found_middle;
37566 + size -= 32;
37567 + result += 32;
37568 + }
37569 + while (size & ~31UL) {
37570 + tmp = *(p++);
37571 + if (~tmp)
37572 + goto found_middle;
37573 + result += 32;
37574 + size -= 32;
37575 + }
37576 + if (!size)
37577 + return result;
37578 + tmp = *p;
37579 +
37580 +found_first:
37581 + tmp |= ~0UL >> size;
37582 +found_middle:
37583 + return result + ffz(tmp);
37584 +}
37585 +
37586 +#define find_first_zero_bit(addr, size) find_next_zero_bit(((void *)addr), \
37587 + (size), 0)
37588 +
37589 +/* Ported from included/linux/bitops.h */
37590 +static __inline__ int ffs(int x)
37591 +{
37592 + int r = 1;
37593 +
37594 + if (!x)
37595 + return 0;
37596 + if (!(x & 0xffff)) {
37597 + x >>= 16;
37598 + r += 16;
37599 + }
37600 + if (!(x & 0xff)) {
37601 + x >>= 8;
37602 + r += 8;
37603 + }
37604 + if (!(x & 0xf)) {
37605 + x >>= 4;
37606 + r += 4;
37607 + }
37608 + if (!(x & 3)) {
37609 + x >>= 2;
37610 + r += 2;
37611 + }
37612 + if (!(x & 1)) {
37613 + x >>= 1;
37614 + r += 1;
37615 + }
37616 + return r;
37617 +}
37618 +#define __ffs(x) (ffs(x) - 1)
37619 +
37620 +/* find_next_bit - find the next set bit in a memory region
37621 + * (from asm-ppc/bitops.h)
37622 + */
37623 +static __inline__ unsigned long find_next_bit(const unsigned long *addr,
37624 + unsigned long size, unsigned long offset)
37625 +{
37626 + unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
37627 + unsigned int result = offset & ~31UL;
37628 + unsigned int tmp;
37629 +
37630 + if (offset >= size)
37631 + return size;
37632 + size -= result;
37633 + offset &= 31UL;
37634 + if (offset) {
37635 + tmp = *p++;
37636 + tmp &= ~0UL << offset;
37637 + if (size < 32)
37638 + goto found_first;
37639 + if (tmp)
37640 + goto found_middle;
37641 + size -= 32;
37642 + result += 32;
37643 + }
37644 + while (size >= 32) {
37645 + tmp = *p++;
37646 + if (tmp != 0)
37647 + goto found_middle;
37648 + result += 32;
37649 + size -= 32;
37650 + }
37651 + if (!size)
37652 + return result;
37653 + tmp = *p;
37654 +
37655 +found_first:
37656 + tmp &= ~0UL >> (32 - size);
37657 + if (tmp == 0UL) /* Are any bits set? */
37658 + return result + size; /* Nope. */
37659 +found_middle:
37660 + return result + __ffs(tmp);
37661 +}
37662 +
37663 +#define find_first_bit(addr, size) find_next_bit((addr), (size), 0)
37664 +
37665 +#ifdef __KERNEL__
37666 +
37667 +/* Ported from include/linux/bitops.h */
37668 +static __inline__ int fls(int x)
37669 +{
37670 + int r = 32;
37671 +
37672 + if (!x)
37673 + return 0;
37674 + if (!(x & 0xffff0000u)) {
37675 + x <<= 16;
37676 + r -= 16;
37677 + }
37678 + if (!(x & 0xff000000u)) {
37679 + x <<= 8;
37680 + r -= 8;
37681 + }
37682 + if (!(x & 0xf0000000u)) {
37683 + x <<= 4;
37684 + r -= 4;
37685 + }
37686 + if (!(x & 0xc0000000u)) {
37687 + x <<= 2;
37688 + r -= 2;
37689 + }
37690 + if (!(x & 0x80000000u)) {
37691 + x <<= 1;
37692 + r -= 1;
37693 + }
37694 + return r;
37695 +}
37696 +
37697 +#include <asm-generic/bitops/fls64.h>
37698 +#include <asm-generic/bitops/sched.h>
37699 +#include <asm-generic/bitops/hweight.h>
37700 +#include <asm-generic/bitops/lock.h>
37701 +
37702 +#define minix_find_first_zero_bit(addr, size) find_next_zero_bit((addr), \
37703 + (size), 0)
37704 +#define minix_test_and_set_bit(nr, addr) test_and_set_bit((nr), \
37705 + (unsigned long *)(addr))
37706 +#define minix_set_bit(nr, addr) set_bit((nr), \
37707 + (unsigned long *)(addr))
37708 +#define minix_test_and_clear_bit(nr, addr) test_and_clear_bit((nr), \
37709 + (unsigned long *)(addr))
37710 +
37711 +static inline int minix_test_bit(int nr, const volatile unsigned long *vaddr)
37712 +{
37713 + int *a = (int *)vaddr;
37714 + int mask;
37715 +
37716 + a += nr >> 5;
37717 + mask = 1 << (nr & 0x1f);
37718 + return ((mask & *a) != 0);
37719 +}
37720 +
37721 +#define ext2_set_bit(nr, addr) test_and_set_bit((nr) ^ 24, \
37722 + (unsigned long *)(addr))
37723 +#define ext2_set_bit_atomic(lock, nr, addr) test_and_set_bit((nr) ^ 24, \
37724 + (unsigned long *)(addr))
37725 +#define ext2_clear_bit(nr, addr) test_and_clear_bit((nr) ^ 24, \
37726 + (unsigned long *)(addr))
37727 +#define ext2_clear_bit_atomic(lock, nr, addr) test_and_clear_bit((nr) ^ 24, \
37728 + (unsigned long *)(addr))
37729 +
37730 +static inline int ext2_test_bit(int nr, const void *vaddr)
37731 +{
37732 + const unsigned char *p = vaddr;
37733 + return (p[nr >> 3] & (1U << (nr & 7))) != 0;
37734 +}
37735 +
37736 +static inline int ext2_find_first_zero_bit(const void *vaddr, unsigned size)
37737 +{
37738 + const unsigned long *p = vaddr, *addr = vaddr;
37739 + int res;
37740 +
37741 + if (!size)
37742 + return 0;
37743 +
37744 + size = (size >> 5) + ((size & 31) > 0);
37745 + while (*p++ == ~0UL) {
37746 + if (--size == 0)
37747 + return (p - addr) << 5;
37748 + }
37749 +
37750 + --p;
37751 + for (res = 0; res < 32; res++)
37752 + if (!ext2_test_bit (res, p))
37753 + break;
37754 + return (p - addr) * 32 + res;
37755 +}
37756 +
37757 +static inline int ext2_find_next_zero_bit(const void *vaddr, unsigned size,
37758 + unsigned offset)
37759 +{
37760 + const unsigned long *addr = vaddr;
37761 + const unsigned long *p = addr + (offset >> 5);
37762 + int bit = offset & 31UL, res;
37763 +
37764 + if (offset >= size)
37765 + return size;
37766 +
37767 + if (bit) {
37768 + /* Look for zero in first longword */
37769 + for (res = bit; res < 32; res++)
37770 + if (!ext2_test_bit (res, p))
37771 + return (p - addr) * 32 + res;
37772 + p++;
37773 + }
37774 + /* No zero yet, search remaining full bytes for a zero */
37775 + res = ext2_find_first_zero_bit(p, size - 32 * (p - addr));
37776 + return (p - addr) * 32 + res;
37777 +}
37778 +
37779 +#endif /* KERNEL */
37780 +
37781 +#endif /* CONFIG_COLDFIRE */
37782 +
37783 #endif /* _M68K_BITOPS_H */
37784 --- a/include/asm-m68k/bootinfo.h
37785 +++ b/include/asm-m68k/bootinfo.h
37786 @@ -19,11 +19,59 @@
37787 ** Redesign of the boot information structure; renamed to bootinfo.h again
37788 ** 27/11/96 Geert Uytterhoeven:
37789 ** Backwards compatibility with bootinfo interface version 1.0
37790 +** 12/03/08 Kurt Mahan
37791 +** Copy the bd_info structure from uboot1.3.2/include/asm-m68k/u-boot.h
37792 +** into this file. The original author is Wolfgang Denk,
37793 +** DENX Software Engineering, wd@denx.de.
37794 */
37795
37796 #ifndef _M68K_BOOTINFO_H
37797 #define _M68K_BOOTINFO_H
37798
37799 +#ifndef __ASSEMBLY__
37800 +/*
37801 + * UBoot Support
37802 + *
37803 + * bd_info structure from uboot1.3.2/include/asm-m68k/u-boot.h
37804 + */
37805 +struct bd_info {
37806 + unsigned long bi_memstart; /* start of DRAM memory */
37807 + unsigned long bi_memsize; /* size of DRAM memory in bytes */
37808 + unsigned long bi_flashstart; /* start of FLASH memory */
37809 + unsigned long bi_flashsize; /* size of FLASH memory */
37810 + unsigned long bi_flashoffset; /* reserved area for startup monitor */
37811 + unsigned long bi_sramstart; /* start of SRAM memory */
37812 + unsigned long bi_sramsize; /* size of SRAM memory */
37813 + unsigned long bi_mbar_base; /* base of internal registers */
37814 + unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */
37815 + unsigned long bi_boot_params; /* where this board expects params */
37816 + unsigned long bi_ip_addr; /* IP Address */
37817 + unsigned char bi_enet0addr[6]; /* Ethernet 0 mac address */
37818 + unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
37819 + unsigned long bi_intfreq; /* Internal Freq, in MHz */
37820 + unsigned long bi_busfreq; /* Bus Freq, in MHz */
37821 +#ifdef UBOOT_PCI
37822 + unsigned long bi_pcifreq; /* pci Freq in MHz */
37823 +#endif
37824 +#ifdef UBOOT_EXTRA_CLOCK
37825 + unsigned long bi_inpfreq; /* input Freq in MHz */
37826 + unsigned long bi_vcofreq; /* vco Freq in MHz */
37827 + unsigned long bi_flbfreq; /* Flexbus Freq in MHz */
37828 +#endif
37829 + unsigned long bi_baudrate; /* Console Baudrate */
37830 + unsigned char bi_enet1addr[6]; /* eth1 mac address */
37831 + unsigned char bi_enet2addr[6]; /* eth2 mac address */
37832 + unsigned char bi_enet3addr[6]; /* eth3 mac address */
37833 +};
37834 +
37835 +struct uboot_record {
37836 + struct bd_info *bdi;
37837 + unsigned long initrd_start;
37838 + unsigned long initrd_end;
37839 + unsigned long cmd_line_start;
37840 + unsigned long cmd_line_stop;
37841 +};
37842 +#endif /* __ASSEMBLY__ */
37843
37844 /*
37845 * Bootinfo definitions
37846 @@ -49,6 +97,8 @@ struct bi_record {
37847 #endif /* __ASSEMBLY__ */
37848
37849
37850 +
37851 +
37852 /*
37853 * Tag Definitions
37854 *
37855 --- a/include/asm-m68k/byteorder.h
37856 +++ b/include/asm-m68k/byteorder.h
37857 @@ -4,8 +4,15 @@
37858 #include <asm/types.h>
37859 #include <linux/compiler.h>
37860
37861 -#ifdef __GNUC__
37862 -
37863 +#if defined(__GNUC__)
37864 +#if defined(__mcfisaaplus__) || defined(__mcfisac__)
37865 +static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 val)
37866 +{
37867 + __asm__ ("byterev %0" : "=d" (val) : "0" (val));
37868 + return val;
37869 +}
37870 +#define __arch__swab32(x) ___arch__swab32(x)
37871 +#elif !defined(__mcoldfire__)
37872 static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 val)
37873 {
37874 __asm__("rolw #8,%0; swap %0; rolw #8,%0" : "=d" (val) : "0" (val));
37875 @@ -14,6 +21,7 @@ static __inline__ __attribute_const__ __
37876 #define __arch__swab32(x) ___arch__swab32(x)
37877
37878 #endif
37879 +#endif
37880
37881 #if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__)
37882 # define __BYTEORDER_HAS_U64__
37883 --- a/include/asm-m68k/cacheflush.h
37884 +++ b/include/asm-m68k/cacheflush.h
37885 @@ -6,6 +6,9 @@
37886 /* cache code */
37887 #define FLUSH_I_AND_D (0x00000808)
37888 #define FLUSH_I (0x00000008)
37889 +#ifdef CONFIG_COLDFIRE
37890 +#include <asm/cf_cacheflush.h>
37891 +#else /* !CONFIG_COLDFIRE */
37892
37893 /*
37894 * Cache handling functions
37895 @@ -153,4 +156,5 @@ static inline void copy_from_user_page(s
37896 memcpy(dst, src, len);
37897 }
37898
37899 +#endif /* !CONFIG_COLDFIRE */
37900 #endif /* _M68K_CACHEFLUSH_H */
37901 --- /dev/null
37902 +++ b/include/asm-m68k/cf_5445x_cacheflush.h
37903 @@ -0,0 +1,447 @@
37904 +/*
37905 + * include/asm-m68k/cf_5445x_cacheflush.h - Coldfire 5445x Cache
37906 + *
37907 + * Based on include/asm-m68k/cacheflush.h
37908 + *
37909 + * Coldfire pieces by:
37910 + * Kurt Mahan kmahan@freescale.com
37911 + *
37912 + * Copyright Freescale Semiconductor, Inc. 2007, 2008
37913 + *
37914 + * This program is free software; you can redistribute it and/or modify it
37915 + * under the terms of the GNU General Public License as published by the
37916 + * Free Software Foundation; either version 2 of the License, or (at your
37917 + * option) any later version.
37918 + */
37919 +#ifndef M68K_CF_5445x_CACHEFLUSH_H
37920 +#define M68K_CF_5445x_CACHEFLUSH_H
37921 +
37922 +#include <asm/cfcache.h>
37923 +
37924 +/*
37925 + * Coldfire Cache Model
37926 + *
37927 + * The Coldfire processors use a Harvard architecture cache configured
37928 + * as four-way set associative. The cache does not implement bus snooping
37929 + * so cache coherency with other masters must be maintained in software.
37930 + *
37931 + * The cache is managed via the CPUSHL instruction in conjunction with
37932 + * bits set in the CACR (cache control register). Currently the code
37933 + * uses the CPUSHL enhancement which adds the ability to
37934 + * invalidate/clear/push a cacheline by physical address. This feature
37935 + * is designated in the Hardware Configuration Register [D1-CPES].
37936 + *
37937 + * CACR Bits:
37938 + * DPI[28] cpushl invalidate disable for d-cache
37939 + * IDPI[12] cpushl invalidate disable for i-cache
37940 + * SPA[14] cpushl search by physical address
37941 + * IVO[20] cpushl invalidate only
37942 + *
37943 + * Random Terminology:
37944 + * * invalidate = reset the cache line's valid bit
37945 + * * push = generate a line-sized store of the data if its contents are marked
37946 + * as modifed (the modified flag is cleared after the store)
37947 + * * clear = push + invalidate
37948 + */
37949 +
37950 +/**
37951 + * flush_icache - Flush all of the instruction cache
37952 + */
37953 +static inline void flush_icache(void)
37954 +{
37955 + asm volatile("nop\n"
37956 + "moveq%.l #0,%%d0\n"
37957 + "moveq%.l #0,%%d1\n"
37958 + "move%.l %%d0,%%a0\n"
37959 + "1:\n"
37960 + "cpushl %%ic,(%%a0)\n"
37961 + "add%.l #0x0010,%%a0\n"
37962 + "addq%.l #1,%%d1\n"
37963 + "cmpi%.l %0,%%d1\n"
37964 + "bne 1b\n"
37965 + "moveq%.l #0,%%d1\n"
37966 + "addq%.l #1,%%d0\n"
37967 + "move%.l %%d0,%%a0\n"
37968 + "cmpi%.l #4,%%d0\n"
37969 + "bne 1b\n"
37970 + : : "i" (CACHE_SETS)
37971 + : "a0", "d0", "d1");
37972 +}
37973 +
37974 +/**
37975 + * flush_dcache - Flush all of the data cache
37976 + */
37977 +static inline void flush_dcache(void)
37978 +{
37979 + asm volatile("nop\n"
37980 + "moveq%.l #0,%%d0\n"
37981 + "moveq%.l #0,%%d1\n"
37982 + "move%.l %%d0,%%a0\n"
37983 + "1:\n"
37984 + "cpushl %%dc,(%%a0)\n"
37985 + "add%.l #0x0010,%%a0\n"
37986 + "addq%.l #1,%%d1\n"
37987 + "cmpi%.l %0,%%d1\n"
37988 + "bne 1b\n"
37989 + "moveq%.l #0,%%d1\n"
37990 + "addq%.l #1,%%d0\n"
37991 + "move%.l %%d0,%%a0\n"
37992 + "cmpi%.l #4,%%d0\n"
37993 + "bne 1b\n"
37994 + : : "i" (CACHE_SETS)
37995 + : "a0", "d0", "d1");
37996 +}
37997 +
37998 +/**
37999 + * flush_bcache - Flush all of both caches
38000 + */
38001 +static inline void flush_bcache(void)
38002 +{
38003 + asm volatile("nop\n"
38004 + "moveq%.l #0,%%d0\n"
38005 + "moveq%.l #0,%%d1\n"
38006 + "move%.l %%d0,%%a0\n"
38007 + "1:\n"
38008 + "cpushl %%bc,(%%a0)\n"
38009 + "add%.l #0x0010,%%a0\n"
38010 + "addq%.l #1,%%d1\n"
38011 + "cmpi%.l %0,%%d1\n"
38012 + "bne 1b\n"
38013 + "moveq%.l #0,%%d1\n"
38014 + "addq%.l #1,%%d0\n"
38015 + "move%.l %%d0,%%a0\n"
38016 + "cmpi%.l #4,%%d0\n"
38017 + "bne 1b\n"
38018 + : : "i" (CACHE_SETS)
38019 + : "a0", "d0", "d1");
38020 +}
38021 +
38022 +/**
38023 + * cf_cache_clear - invalidate cache
38024 + * @paddr: starting physical address
38025 + * @len: number of bytes
38026 + *
38027 + * Invalidate cache lines starting at paddr for len bytes.
38028 + * Those lines are not pushed.
38029 + */
38030 +static inline void cf_cache_clear(unsigned long paddr, int len)
38031 +{
38032 + /* number of lines */
38033 + len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE;
38034 + if (len == 0)
38035 + return;
38036 +
38037 + /* align on set boundary */
38038 + paddr &= 0xfffffff0;
38039 +
38040 + asm volatile("nop\n"
38041 + "move%.l %2,%%d0\n"
38042 + "or%.l %3,%%d0\n"
38043 + "movec %%d0,%%cacr\n"
38044 + "move%.l %0,%%a0\n"
38045 + "move%.l %1,%%d0\n"
38046 + "1:\n"
38047 + "cpushl %%bc,(%%a0)\n"
38048 + "lea 0x10(%%a0),%%a0\n"
38049 + "subq%.l #1,%%d0\n"
38050 + "bne%.b 1b\n"
38051 + "movec %2,%%cacr\n"
38052 + : : "a" (paddr), "r" (len),
38053 + "r" (shadow_cacr),
38054 + "i" (CF_CACR_SPA+CF_CACR_IVO)
38055 + : "a0", "d0");
38056 +}
38057 +
38058 +/**
38059 + * cf_cache_push - Push dirty cache out with no invalidate
38060 + * @paddr: starting physical address
38061 + * @len: number of bytes
38062 + *
38063 + * Push the any dirty lines starting at paddr for len bytes.
38064 + * Those lines are not invalidated.
38065 + */
38066 +static inline void cf_cache_push(unsigned long paddr, int len)
38067 +{
38068 + /* number of lines */
38069 + len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE;
38070 + if (len == 0)
38071 + return;
38072 +
38073 + /* align on set boundary */
38074 + paddr &= 0xfffffff0;
38075 +
38076 + asm volatile("nop\n"
38077 + "move%.l %2,%%d0\n"
38078 + "or%.l %3,%%d0\n"
38079 + "movec %%d0,%%cacr\n"
38080 + "move%.l %0,%%a0\n"
38081 + "move%.l %1,%%d0\n"
38082 + "1:\n"
38083 + "cpushl %%bc,(%%a0)\n"
38084 + "lea 0x10(%%a0),%%a0\n"
38085 + "subq%.l #1,%%d0\n"
38086 + "bne.b 1b\n"
38087 + "movec %2,%%cacr\n"
38088 + : : "a" (paddr), "r" (len),
38089 + "r" (shadow_cacr),
38090 + "i" (CF_CACR_SPA+CF_CACR_DPI+CF_CACR_IDPI)
38091 + : "a0", "d0");
38092 +}
38093 +
38094 +/**
38095 + * cf_cache_flush - Push dirty cache out and invalidate
38096 + * @paddr: starting physical address
38097 + * @len: number of bytes
38098 + *
38099 + * Push the any dirty lines starting at paddr for len bytes and
38100 + * invalidate those lines.
38101 + */
38102 +static inline void cf_cache_flush(unsigned long paddr, int len)
38103 +{
38104 + /* number of lines */
38105 + len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE;
38106 + if (len == 0)
38107 + return;
38108 +
38109 + /* align on set boundary */
38110 + paddr &= 0xfffffff0;
38111 +
38112 + asm volatile("nop\n"
38113 + "move%.l %2,%%d0\n"
38114 + "or%.l %3,%%d0\n"
38115 + "movec %%d0,%%cacr\n"
38116 + "move%.l %0,%%a0\n"
38117 + "move%.l %1,%%d0\n"
38118 + "1:\n"
38119 + "cpushl %%bc,(%%a0)\n"
38120 + "lea 0x10(%%a0),%%a0\n"
38121 + "subq%.l #1,%%d0\n"
38122 + "bne.b 1b\n"
38123 + "movec %2,%%cacr\n"
38124 + : : "a" (paddr), "r" (len),
38125 + "r" (shadow_cacr),
38126 + "i" (CF_CACR_SPA)
38127 + : "a0", "d0");
38128 +}
38129 +
38130 +/**
38131 + * cf_cache_flush_range - Push dirty data/inst cache in range out and invalidate
38132 + * @vstart - starting virtual address
38133 + * @vend: ending virtual address
38134 + *
38135 + * Push the any dirty data/instr lines starting at paddr for len bytes and
38136 + * invalidate those lines.
38137 + */
38138 +static inline void cf_cache_flush_range(unsigned long vstart, unsigned long vend)
38139 +{
38140 + int len;
38141 +
38142 + /* align on set boundary */
38143 + vstart &= 0xfffffff0;
38144 + vend = PAGE_ALIGN((vend + (CACHE_LINE_SIZE-1))) & 0xfffffff0;
38145 + len = vend - vstart;
38146 + if (len == 0)
38147 + return;
38148 + vstart = __pa(vstart);
38149 + vend = vstart + len;
38150 +
38151 + asm volatile("nop\n"
38152 + "move%.l %2,%%d0\n"
38153 + "or%.l %3,%%d0\n"
38154 + "movec %%d0,%%cacr\n"
38155 + "move%.l %0,%%a0\n"
38156 + "move%.l %1,%%a1\n"
38157 + "1:\n"
38158 + "cpushl %%bc,(%%a0)\n"
38159 + "lea 0x10(%%a0),%%a0\n"
38160 + "cmpa%.l %%a0,%%a1\n"
38161 + "bne.b 1b\n"
38162 + "movec %2,%%cacr\n"
38163 + : /* no return */
38164 + : "a" (vstart), "a" (vend),
38165 + "r" (shadow_cacr),
38166 + "i" (CF_CACR_SPA)
38167 + : "a0", "a1", "d0");
38168 +}
38169 +
38170 +/**
38171 + * cf_dcache_flush_range - Push dirty data cache in range out and invalidate
38172 + * @vstart - starting virtual address
38173 + * @vend: ending virtual address
38174 + *
38175 + * Push the any dirty data lines starting at paddr for len bytes and
38176 + * invalidate those lines.
38177 + */
38178 +static inline void cf_dcache_flush_range(unsigned long vstart, unsigned long vend)
38179 +{
38180 + /* align on set boundary */
38181 + vstart &= 0xfffffff0;
38182 + vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0;
38183 +
38184 + asm volatile("nop\n"
38185 + "move%.l %2,%%d0\n"
38186 + "or%.l %3,%%d0\n"
38187 + "movec %%d0,%%cacr\n"
38188 + "move%.l %0,%%a0\n"
38189 + "move%.l %1,%%a1\n"
38190 + "1:\n"
38191 + "cpushl %%dc,(%%a0)\n"
38192 + "lea 0x10(%%a0),%%a0\n"
38193 + "cmpa%.l %%a0,%%a1\n"
38194 + "bne.b 1b\n"
38195 + "movec %2,%%cacr\n"
38196 + : /* no return */
38197 + : "a" (__pa(vstart)), "a" (__pa(vend)),
38198 + "r" (shadow_cacr),
38199 + "i" (CF_CACR_SPA)
38200 + : "a0", "a1", "d0");
38201 +}
38202 +
38203 +/**
38204 + * cf_icache_flush_range - Push dirty inst cache in range out and invalidate
38205 + * @vstart - starting virtual address
38206 + * @vend: ending virtual address
38207 + *
38208 + * Push the any dirty instr lines starting at paddr for len bytes and
38209 + * invalidate those lines. This should just be an invalidate since you
38210 + * shouldn't be able to have dirty instruction cache.
38211 + */
38212 +static inline void cf_icache_flush_range(unsigned long vstart, unsigned long vend)
38213 +{
38214 + /* align on set boundary */
38215 + vstart &= 0xfffffff0;
38216 + vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0;
38217 +
38218 + asm volatile("nop\n"
38219 + "move%.l %2,%%d0\n"
38220 + "or%.l %3,%%d0\n"
38221 + "movec %%d0,%%cacr\n"
38222 + "move%.l %0,%%a0\n"
38223 + "move%.l %1,%%a1\n"
38224 + "1:\n"
38225 + "cpushl %%ic,(%%a0)\n"
38226 + "lea 0x10(%%a0),%%a0\n"
38227 + "cmpa%.l %%a0,%%a1\n"
38228 + "bne.b 1b\n"
38229 + "movec %2,%%cacr\n"
38230 + : /* no return */
38231 + : "a" (__pa(vstart)), "a" (__pa(vend)),
38232 + "r" (shadow_cacr),
38233 + "i" (CF_CACR_SPA)
38234 + : "a0", "a1", "d0");
38235 +}
38236 +
38237 +/**
38238 + * flush_cache_mm - Flush an mm_struct
38239 + * @mm: mm_struct to flush
38240 + */
38241 +static inline void flush_cache_mm(struct mm_struct *mm)
38242 +{
38243 + if (mm == current->mm)
38244 + flush_bcache();
38245 +}
38246 +
38247 +#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
38248 +
38249 +/**
38250 + * flush_cache_range - Flush a cache range
38251 + * @vma: vma struct
38252 + * @start: Starting address
38253 + * @end: Ending address
38254 + *
38255 + * flush_cache_range must be a macro to avoid a dependency on
38256 + * linux/mm.h which includes this file.
38257 + */
38258 +static inline void flush_cache_range(struct vm_area_struct *vma,
38259 + unsigned long start, unsigned long end)
38260 +{
38261 + if (vma->vm_mm == current->mm)
38262 + cf_cache_flush_range(start, end);
38263 +}
38264 +
38265 +/**
38266 + * flush_cache_page - Flush a page of the cache
38267 + * @vma: vma struct
38268 + * @vmaddr:
38269 + * @pfn: page numer
38270 + *
38271 + * flush_cache_page must be a macro to avoid a dependency on
38272 + * linux/mm.h which includes this file.
38273 + */
38274 +static inline void flush_cache_page(struct vm_area_struct *vma,
38275 + unsigned long vmaddr, unsigned long pfn)
38276 +{
38277 + if (vma->vm_mm == current->mm)
38278 + cf_cache_flush_range(vmaddr, vmaddr+PAGE_SIZE);
38279 +}
38280 +
38281 +/**
38282 + * __flush_page_to_ram - Push a page out of the cache
38283 + * @vaddr: Virtual address at start of page
38284 + *
38285 + * Push the page at kernel virtual address *vaddr* and clear
38286 + * the icache.
38287 + */
38288 +static inline void __flush_page_to_ram(void *vaddr)
38289 +{
38290 + asm volatile("nop\n"
38291 + "move%.l %2,%%d0\n"
38292 + "or%.l %3,%%d0\n"
38293 + "movec %%d0,%%cacr\n"
38294 + "move%.l %0,%%d0\n"
38295 + "and%.l #0xfffffff0,%%d0\n"
38296 + "move%.l %%d0,%%a0\n"
38297 + "move%.l %1,%%d0\n"
38298 + "1:\n"
38299 + "cpushl %%bc,(%%a0)\n"
38300 + "lea 0x10(%%a0),%%a0\n"
38301 + "subq%.l #1,%%d0\n"
38302 + "bne.b 1b\n"
38303 + "movec %2,%%cacr\n"
38304 + : : "a" (__pa(vaddr)), "i" (PAGE_SIZE / CACHE_LINE_SIZE),
38305 + "r" (shadow_cacr), "i" (CF_CACR_SPA)
38306 + : "a0", "d0");
38307 +}
38308 +
38309 +/*
38310 + * Various defines for the kernel.
38311 + */
38312 +
38313 +extern void cache_clear(unsigned long paddr, int len);
38314 +extern void cache_push(unsigned long paddr, int len);
38315 +extern void flush_icache_range(unsigned long address, unsigned long endaddr);
38316 +
38317 +#define flush_cache_all() flush_bcache()
38318 +#define flush_cache_vmap(start, end) flush_bcache()
38319 +#define flush_cache_vunmap(start, end) flush_bcache()
38320 +
38321 +#define flush_dcache_range(vstart, vend) cf_dcache_flush_range(vstart, vend)
38322 +#define flush_dcache_page(page) __flush_page_to_ram(page_address(page))
38323 +#define flush_dcache_mmap_lock(mapping) do { } while (0)
38324 +#define flush_dcache_mmap_unlock(mapping) do { } while (0)
38325 +
38326 +#define flush_icache_page(vma, page) __flush_page_to_ram(page_address(page))
38327 +
38328 +/**
38329 + * copy_to_user_page - Copy memory to user page
38330 + */
38331 +static inline void copy_to_user_page(struct vm_area_struct *vma,
38332 + struct page *page, unsigned long vaddr,
38333 + void *dst, void *src, int len)
38334 +{
38335 + memcpy(dst, src, len);
38336 + cf_cache_flush(page_to_phys(page), PAGE_SIZE);
38337 +}
38338 +
38339 +/**
38340 + * copy_from_user_page - Copy memory from user page
38341 + */
38342 +static inline void copy_from_user_page(struct vm_area_struct *vma,
38343 + struct page *page, unsigned long vaddr,
38344 + void *dst, void *src, int len)
38345 +{
38346 + cf_cache_flush(page_to_phys(page), PAGE_SIZE);
38347 + memcpy(dst, src, len);
38348 +}
38349 +
38350 +#endif /* M68K_CF_5445x_CACHEFLUSH_H */
38351 --- /dev/null
38352 +++ b/include/asm-m68k/cf_548x_cacheflush.h
38353 @@ -0,0 +1,259 @@
38354 +/*
38355 + * include/asm-m68k/cf_548x_cacheflush.h - Coldfire 547x/548x Cache
38356 + *
38357 + * Based on include/asm-m68k/cacheflush.h
38358 + *
38359 + * Coldfire pieces by:
38360 + * Kurt Mahan kmahan@freescale.com
38361 + *
38362 + * Copyright Freescale Semiconductor, Inc. 2007, 2008
38363 + *
38364 + * This program is free software; you can redistribute it and/or modify it
38365 + * under the terms of the GNU General Public License as published by the
38366 + * Free Software Foundation; either version 2 of the License, or (at your
38367 + * option) any later version.
38368 + */
38369 +#ifndef M68K_CF_548x_CACHEFLUSH_H
38370 +#define M68K_CF_548x_CACHEFLUSH_H
38371 +
38372 +#include <asm/cfcache.h>
38373 +/*
38374 + * Cache handling functions
38375 + */
38376 +
38377 +#define flush_icache() \
38378 +({ \
38379 + unsigned long set; \
38380 + unsigned long start_set; \
38381 + unsigned long end_set; \
38382 + \
38383 + start_set = 0; \
38384 + end_set = (unsigned long)LAST_DCACHE_ADDR; \
38385 + \
38386 + for (set = start_set; set <= end_set; set += (0x10 - 3)) { \
38387 + asm volatile("cpushl %%ic,(%0)\n" \
38388 + "\taddq%.l #1,%0\n" \
38389 + "\tcpushl %%ic,(%0)\n" \
38390 + "\taddq%.l #1,%0\n" \
38391 + "\tcpushl %%ic,(%0)\n" \
38392 + "\taddq%.l #1,%0\n" \
38393 + "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set)); \
38394 + } \
38395 +})
38396 +
38397 +#define flush_dcache() \
38398 +({ \
38399 + unsigned long set; \
38400 + unsigned long start_set; \
38401 + unsigned long end_set; \
38402 + \
38403 + start_set = 0; \
38404 + end_set = (unsigned long)LAST_DCACHE_ADDR; \
38405 + \
38406 + for (set = start_set; set <= end_set; set += (0x10 - 3)) { \
38407 + asm volatile("cpushl %%dc,(%0)\n" \
38408 + "\taddq%.l #1,%0\n" \
38409 + "\tcpushl %%dc,(%0)\n" \
38410 + "\taddq%.l #1,%0\n" \
38411 + "\tcpushl %%dc,(%0)\n" \
38412 + "\taddq%.l #1,%0\n" \
38413 + "\tcpushl %%dc,(%0)" : "=a" (set) : "a" (set)); \
38414 + } \
38415 +})
38416 +
38417 +#define flush_bcache() \
38418 +({ \
38419 + unsigned long set; \
38420 + unsigned long start_set; \
38421 + unsigned long end_set; \
38422 + \
38423 + start_set = 0; \
38424 + end_set = (unsigned long)LAST_DCACHE_ADDR; \
38425 + \
38426 + for (set = start_set; set <= end_set; set += (0x10 - 3)) { \
38427 + asm volatile("cpushl %%bc,(%0)\n" \
38428 + "\taddq%.l #1,%0\n" \
38429 + "\tcpushl %%bc,(%0)\n" \
38430 + "\taddq%.l #1,%0\n" \
38431 + "\tcpushl %%bc,(%0)\n" \
38432 + "\taddq%.l #1,%0\n" \
38433 + "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set)); \
38434 + } \
38435 +})
38436 +
38437 +/*
38438 + * invalidate the cache for the specified memory range.
38439 + * It starts at the physical address specified for
38440 + * the given number of bytes.
38441 + */
38442 +extern void cache_clear(unsigned long paddr, int len);
38443 +/*
38444 + * push any dirty cache in the specified memory range.
38445 + * It starts at the physical address specified for
38446 + * the given number of bytes.
38447 + */
38448 +extern void cache_push(unsigned long paddr, int len);
38449 +
38450 +/*
38451 + * push and invalidate pages in the specified user virtual
38452 + * memory range.
38453 + */
38454 +extern void cache_push_v(unsigned long vaddr, int len);
38455 +
38456 +/* This is needed whenever the virtual mapping of the current
38457 + process changes. */
38458 +
38459 +/**
38460 + * flush_cache_mm - Flush an mm_struct
38461 + * @mm: mm_struct to flush
38462 + */
38463 +static inline void flush_cache_mm(struct mm_struct *mm)
38464 +{
38465 + if (mm == current->mm)
38466 + flush_bcache();
38467 +}
38468 +
38469 +#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
38470 +
38471 +#define flush_cache_all() flush_bcache()
38472 +
38473 +/**
38474 + * flush_cache_range - Flush a cache range
38475 + * @vma: vma struct
38476 + * @start: Starting address
38477 + * @end: Ending address
38478 + *
38479 + * flush_cache_range must be a macro to avoid a dependency on
38480 + * linux/mm.h which includes this file.
38481 + */
38482 +static inline void flush_cache_range(struct vm_area_struct *vma,
38483 + unsigned long start, unsigned long end)
38484 +{
38485 + if (vma->vm_mm == current->mm)
38486 + flush_bcache();
38487 +// cf_cache_flush_range(start, end);
38488 +}
38489 +
38490 +/**
38491 + * flush_cache_page - Flush a page of the cache
38492 + * @vma: vma struct
38493 + * @vmaddr:
38494 + * @pfn: page numer
38495 + *
38496 + * flush_cache_page must be a macro to avoid a dependency on
38497 + * linux/mm.h which includes this file.
38498 + */
38499 +static inline void flush_cache_page(struct vm_area_struct *vma,
38500 + unsigned long vmaddr, unsigned long pfn)
38501 +{
38502 + if (vma->vm_mm == current->mm)
38503 + flush_bcache();
38504 +// cf_cache_flush_range(vmaddr, vmaddr+PAGE_SIZE);
38505 +}
38506 +
38507 +/* Push the page at kernel virtual address and clear the icache */
38508 +/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
38509 +#define flush_page_to_ram(page) __flush_page_to_ram((void *) page_address(page))
38510 +extern inline void __flush_page_to_ram(void *address)
38511 +{
38512 + unsigned long set;
38513 + unsigned long start_set;
38514 + unsigned long end_set;
38515 + unsigned long addr = (unsigned long) address;
38516 +
38517 + addr &= ~(PAGE_SIZE - 1); /* round down to page start address */
38518 +
38519 + start_set = addr & _ICACHE_SET_MASK;
38520 + end_set = (addr + PAGE_SIZE-1) & _ICACHE_SET_MASK;
38521 +
38522 + if (start_set > end_set) {
38523 + /* from the begining to the lowest address */
38524 + for (set = 0; set <= end_set; set += (0x10 - 3)) {
38525 + asm volatile("cpushl %%bc,(%0)\n"
38526 + "\taddq%.l #1,%0\n"
38527 + "\tcpushl %%bc,(%0)\n"
38528 + "\taddq%.l #1,%0\n"
38529 + "\tcpushl %%bc,(%0)\n"
38530 + "\taddq%.l #1,%0\n"
38531 + "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set));
38532 + }
38533 + /* next loop will finish the cache ie pass the hole */
38534 + end_set = LAST_ICACHE_ADDR;
38535 + }
38536 + for (set = start_set; set <= end_set; set += (0x10 - 3)) {
38537 + asm volatile("cpushl %%bc,(%0)\n"
38538 + "\taddq%.l #1,%0\n"
38539 + "\tcpushl %%bc,(%0)\n"
38540 + "\taddq%.l #1,%0\n"
38541 + "\tcpushl %%bc,(%0)\n"
38542 + "\taddq%.l #1,%0\n"
38543 + "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set));
38544 + }
38545 +}
38546 +
38547 +/* Use __flush_page_to_ram() for flush_dcache_page all values are same - MW */
38548 +#define flush_dcache_page(page) \
38549 + __flush_page_to_ram((void *) page_address(page))
38550 +#define flush_icache_page(vma,pg) \
38551 + __flush_page_to_ram((void *) page_address(pg))
38552 +#define flush_icache_user_range(adr,len) do { } while (0)
38553 +/* NL */
38554 +#define flush_icache_user_page(vma,page,addr,len) do { } while (0)
38555 +
38556 +/* Push n pages at kernel virtual address and clear the icache */
38557 +/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
38558 +extern inline void flush_icache_range (unsigned long address,
38559 + unsigned long endaddr)
38560 +{
38561 + unsigned long set;
38562 + unsigned long start_set;
38563 + unsigned long end_set;
38564 +
38565 + start_set = address & _ICACHE_SET_MASK;
38566 + end_set = endaddr & _ICACHE_SET_MASK;
38567 +
38568 + if (start_set > end_set) {
38569 + /* from the begining to the lowest address */
38570 + for (set = 0; set <= end_set; set += (0x10 - 3)) {
38571 + asm volatile("cpushl %%ic,(%0)\n"
38572 + "\taddq%.l #1,%0\n"
38573 + "\tcpushl %%ic,(%0)\n"
38574 + "\taddq%.l #1,%0\n"
38575 + "\tcpushl %%ic,(%0)\n"
38576 + "\taddq%.l #1,%0\n"
38577 + "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set));
38578 + }
38579 + /* next loop will finish the cache ie pass the hole */
38580 + end_set = LAST_ICACHE_ADDR;
38581 + }
38582 + for (set = start_set; set <= end_set; set += (0x10 - 3)) {
38583 + asm volatile("cpushl %%ic,(%0)\n"
38584 + "\taddq%.l #1,%0\n"
38585 + "\tcpushl %%ic,(%0)\n"
38586 + "\taddq%.l #1,%0\n"
38587 + "\tcpushl %%ic,(%0)\n"
38588 + "\taddq%.l #1,%0\n"
38589 + "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set));
38590 + }
38591 +}
38592 +
38593 +static inline void copy_to_user_page(struct vm_area_struct *vma,
38594 + struct page *page, unsigned long vaddr,
38595 + void *dst, void *src, int len)
38596 +{
38597 + memcpy(dst, src, len);
38598 + flush_icache_user_page(vma, page, vaddr, len);
38599 +}
38600 +static inline void copy_from_user_page(struct vm_area_struct *vma,
38601 + struct page *page, unsigned long vaddr,
38602 + void *dst, void *src, int len)
38603 +{
38604 + memcpy(dst, src, len);
38605 +}
38606 +
38607 +#define flush_cache_vmap(start, end) flush_cache_all()
38608 +#define flush_cache_vunmap(start, end) flush_cache_all()
38609 +#define flush_dcache_mmap_lock(mapping) do { } while (0)
38610 +#define flush_dcache_mmap_unlock(mapping) do { } while (0)
38611 +
38612 +#endif /* M68K_CF_548x_CACHEFLUSH_H */
38613 --- /dev/null
38614 +++ b/include/asm-m68k/cf_cacheflush.h
38615 @@ -0,0 +1,10 @@
38616 +#ifndef M68K_CF_CACHEFLUSH_H
38617 +#define M68K_CF_CACHEFLUSH_H
38618 +
38619 +#ifdef CONFIG_M5445X
38620 +#include "cf_5445x_cacheflush.h"
38621 +#else
38622 +#include "cf_548x_cacheflush.h"
38623 +#endif
38624 +
38625 +#endif /* M68K_CF_CACHEFLUSH_H */
38626 --- /dev/null
38627 +++ b/include/asm-m68k/cfcache.h
38628 @@ -0,0 +1,114 @@
38629 +/*
38630 + * include/asm-m68k/cfcache.h - Coldfire Cache Controller
38631 + *
38632 + * Kurt Mahan kmahan@freescale.com
38633 + *
38634 + * Copyright Freescale Semiconductor, Inc. 2007
38635 + *
38636 + * This program is free software; you can redistribute it and/or modify it
38637 + * under the terms of the GNU General Public License as published by the
38638 + * Free Software Foundation; either version 2 of the License, or (at your
38639 + * option) any later version.
38640 + */
38641 +#ifndef CF_CFCACHE_H
38642 +#define CF_CFCACHE_H
38643 +
38644 +/*
38645 + * CACR Cache Control Register
38646 + */
38647 +#define CF_CACR_DEC (0x80000000) /* Data Cache Enable */
38648 +#define CF_CACR_DW (0x40000000) /* Data default Write-protect */
38649 +#define CF_CACR_DESB (0x20000000) /* Data Enable Store Buffer */
38650 +#define CF_CACR_DPI (0x10000000) /* Data Disable CPUSHL Invalidate */
38651 +#define CF_CACR_DHLCK (0x08000000) /* 1/2 Data Cache Lock Mode */
38652 +#define CF_CACR_DDCM_00 (0x00000000) /* Cacheable writethrough imprecise */
38653 +#define CF_CACR_DDCM_01 (0x02000000) /* Cacheable copyback */
38654 +#define CF_CACR_DDCM_10 (0x04000000) /* Noncacheable precise */
38655 +#define CF_CACR_DDCM_11 (0x06000000) /* Noncacheable imprecise */
38656 +#define CF_CACR_DCINVA (0x01000000) /* Data Cache Invalidate All */
38657 +#define CF_CACR_DDSP (0x00800000) /* Data default supervisor-protect */
38658 +#define CF_CACR_IVO (0x00100000) /* Invalidate only */
38659 +#define CF_CACR_BEC (0x00080000) /* Branch Cache Enable */
38660 +#define CF_CACR_BCINVA (0x00040000) /* Branch Cache Invalidate All */
38661 +#define CF_CACR_IEC (0x00008000) /* Instruction Cache Enable */
38662 +#define CF_CACR_SPA (0x00004000) /* Search by Physical Address */
38663 +#define CF_CACR_DNFB (0x00002000) /* Default cache-inhibited fill buf */
38664 +#define CF_CACR_IDPI (0x00001000) /* Instr Disable CPUSHL Invalidate */
38665 +#define CF_CACR_IHLCK (0x00000800) /* 1/2 Instruction Cache Lock Mode */
38666 +#define CF_CACR_IDCM (0x00000400) /* Noncacheable Instr default mode */
38667 +#define CF_CACR_ICINVA (0x00000100) /* Instr Cache Invalidate All */
38668 +#define CF_CACR_IDSP (0x00000080) /* Ins default supervisor-protect */
38669 +#define CF_CACR_EUSP (0x00000020) /* Switch stacks in user mode */
38670 +
38671 +#ifdef CONFIG_M5445X
38672 +/*
38673 + * M5445x Cache Configuration
38674 + * - cache line size is 16 bytes
38675 + * - cache is 4-way set associative
38676 + * - each cache has 256 sets (64k / 16bytes / 4way)
38677 + * - I-Cache size is 16KB
38678 + * - D-Cache size is 16KB
38679 + */
38680 +#define ICACHE_SIZE 0x4000 /* instruction - 16k */
38681 +#define DCACHE_SIZE 0x4000 /* data - 16k */
38682 +
38683 +#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */
38684 +#define CACHE_SETS 0x0100 /* 256 sets */
38685 +#define CACHE_WAYS 0x0004 /* 4 way */
38686 +
38687 +#define CACHE_DISABLE_MODE (CF_CACR_DCINVA+ \
38688 + CF_CACR_BCINVA+ \
38689 + CF_CACR_ICINVA)
38690 +
38691 +#ifndef CONFIG_M5445X_DISABLE_CACHE
38692 +#define CACHE_INITIAL_MODE (CF_CACR_DEC+ \
38693 + CF_CACR_BEC+ \
38694 + CF_CACR_IEC+ \
38695 + CF_CACR_DESB+ \
38696 + CF_CACR_EUSP)
38697 +#else
38698 +/* cache disabled for testing */
38699 +#define CACHE_INITIAL_MODE (CF_CACR_EUSP)
38700 +#endif /* CONFIG_M5445X_DISABLE_CACHE */
38701 +
38702 +#elif defined(CONFIG_M547X_8X)
38703 +/*
38704 + * M547x/M548x Cache Configuration
38705 + * - cache line size is 16 bytes
38706 + * - cache is 4-way set associative
38707 + * - each cache has 512 sets (128k / 16bytes / 4way)
38708 + * - I-Cache size is 32KB
38709 + * - D-Cache size is 32KB
38710 + */
38711 +#define ICACHE_SIZE 0x8000 /* instruction - 32k */
38712 +#define DCACHE_SIZE 0x8000 /* data - 32k */
38713 +
38714 +#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */
38715 +#define CACHE_SETS 0x0200 /* 512 sets */
38716 +#define CACHE_WAYS 0x0004 /* 4 way */
38717 +
38718 +/* in for the old cpushl caching code */
38719 +#define _DCACHE_SET_MASK ((DCACHE_SIZE/64-1)<<CACHE_WAYS)
38720 +#define _ICACHE_SET_MASK ((ICACHE_SIZE/64-1)<<CACHE_WAYS)
38721 +#define LAST_DCACHE_ADDR _DCACHE_SET_MASK
38722 +#define LAST_ICACHE_ADDR _ICACHE_SET_MASK
38723 +
38724 +#define CACHE_DISABLE_MODE (CF_CACR_DCINVA+ \
38725 + CF_CACR_BCINVA+ \
38726 + CF_CACR_ICINVA)
38727 +
38728 +#define CACHE_INITIAL_MODE (CF_CACR_DEC+ \
38729 + CF_CACR_BEC+ \
38730 + CF_CACR_IEC+ \
38731 + CF_CACR_DESB+ \
38732 + CF_CACR_EUSP)
38733 +#endif /* CONFIG_M547X_8X */
38734 +
38735 +#ifndef __ASSEMBLY__
38736 +
38737 +extern unsigned long shadow_cacr;
38738 +extern void cacr_set(unsigned long x);
38739 +
38740 +#endif /* !__ASSEMBLY__ */
38741 +
38742 +#endif /* CF_CACHE_H */
38743 --- /dev/null
38744 +++ b/include/asm-m68k/cf_entry.h
38745 @@ -0,0 +1,146 @@
38746 +#ifndef __CF_M68K_ENTRY_H
38747 +#define __CF_M68K_ENTRY_H
38748 +
38749 +#include <asm/setup.h>
38750 +#include <asm/page.h>
38751 +#include <asm/coldfire.h>
38752 +#include <asm/cfmmu.h>
38753 +#include <asm/asm-offsets.h>
38754 +
38755 +/*
38756 + * Stack layout in 'ret_from_exception':
38757 + *
38758 + * This allows access to the syscall arguments in registers d1-d5
38759 + *
38760 + * 0(sp) - d1
38761 + * 4(sp) - d2
38762 + * 8(sp) - d3
38763 + * C(sp) - d4
38764 + * 10(sp) - d5
38765 + * 14(sp) - a0
38766 + * 18(sp) - a1
38767 + * 1C(sp) - a2
38768 + * 20(sp) - d0
38769 + * 24(sp) - orig_d0
38770 + * 28(sp) - stack adjustment
38771 + * 2C(sp) - sr
38772 + * 2E(sp) - pc
38773 + * 32(sp) - format & vector
38774 + * 36(sp) - MMUSR
38775 + * 3A(sp) - MMUAR
38776 + */
38777 +
38778 +/*
38779 + * 97/05/14 Andreas: Register %a2 is now set to the current task throughout
38780 + * the whole kernel.
38781 + */
38782 +
38783 +/* the following macro is used when enabling interrupts */
38784 +/* portable version */
38785 +#define ALLOWINT (~0x700)
38786 +#define MAX_NOINT_IPL 0
38787 +
38788 +#ifdef __ASSEMBLY__
38789 +
38790 +#define curptr a2
38791 +
38792 +LFLUSH_I_AND_D = 0x00000808
38793 +LSIGTRAP = 5
38794 +
38795 +/* process bits for task_struct.ptrace */
38796 +PT_TRACESYS_OFF = 3
38797 +PT_TRACESYS_BIT = 1
38798 +PT_PTRACED_OFF = 3
38799 +PT_PTRACED_BIT = 0
38800 +PT_DTRACE_OFF = 3
38801 +PT_DTRACE_BIT = 2
38802 +
38803 +#define SAVE_ALL_INT save_all_int
38804 +#define SAVE_ALL_SYS save_all_sys
38805 +#define RESTORE_ALL restore_all
38806 +/*
38807 + * This defines the normal kernel pt-regs layout.
38808 + *
38809 + * regs a3-a6 and d6-d7 are preserved by C code
38810 + * the kernel doesn't mess with usp unless it needs to
38811 + */
38812 +
38813 +/*
38814 + * a -1 in the orig_d0 field signifies
38815 + * that the stack frame is NOT for syscall
38816 + */
38817 +.macro save_all_int
38818 + movel MMUSR,%sp@-
38819 + movel MMUAR,%sp@-
38820 + clrl %sp@- | stk_adj
38821 + pea -1:w | orig d0
38822 + movel %d0,%sp@- | d0
38823 + subal #(8*4), %sp
38824 + moveml %d1-%d5/%a0-%a1/%curptr,%sp@
38825 +.endm
38826 +
38827 +.macro save_all_sys
38828 + movel MMUSR,%sp@-
38829 + movel MMUAR,%sp@-
38830 + clrl %sp@- | stk_adj
38831 + movel %d0,%sp@- | orig d0
38832 + movel %d0,%sp@- | d0
38833 + subal #(8*4), %sp
38834 + moveml %d1-%d5/%a0-%a1/%curptr,%sp@
38835 +.endm
38836 +
38837 +.macro restore_all
38838 + moveml %sp@,%a0-%a1/%curptr/%d1-%d5
38839 + addal #(8*4), %sp
38840 + movel %sp@+,%d0 | d0
38841 + addql #4,%sp | orig d0
38842 + addl %sp@+,%sp | stk_adj
38843 + addql #8,%sp | MMUAR & MMUSR
38844 + rte
38845 +.endm
38846 +
38847 +#define SWITCH_STACK_SIZE (6*4+4) /* includes return address */
38848 +
38849 +#define SAVE_SWITCH_STACK save_switch_stack
38850 +#define RESTORE_SWITCH_STACK restore_switch_stack
38851 +#define GET_CURRENT(tmp) get_current tmp
38852 +
38853 +.macro save_switch_stack
38854 + subal #(6*4), %sp
38855 + moveml %a3-%a6/%d6-%d7,%sp@
38856 +.endm
38857 +
38858 +.macro restore_switch_stack
38859 + moveml %sp@,%a3-%a6/%d6-%d7
38860 + addal #(6*4), %sp
38861 +.endm
38862 +
38863 +.macro get_current reg=%d0
38864 + movel %sp,\reg
38865 + andl #-THREAD_SIZE,\reg
38866 + movel \reg,%curptr
38867 + movel %curptr@,%curptr
38868 +.endm
38869 +
38870 +#else /* C source */
38871 +
38872 +#define STR(X) STR1(X)
38873 +#define STR1(X) #X
38874 +
38875 +#define PT_OFF_ORIG_D0 0x24
38876 +#define PT_OFF_FORMATVEC 0x32
38877 +#define PT_OFF_SR 0x2C
38878 +#define SAVE_ALL_INT \
38879 + "clrl %%sp@-;" /* stk_adj */ \
38880 + "pea -1:w;" /* orig d0 = -1 */ \
38881 + "movel %%d0,%%sp@-;" /* d0 */ \
38882 + "subal #(8*4),%sp" \
38883 + "moveml %%d1-%%d5/%%a0-%%a2,%%sp@"
38884 +#define GET_CURRENT(tmp) \
38885 + "movel %%sp,"#tmp"\n\t" \
38886 + "andw #-"STR(THREAD_SIZE)","#tmp"\n\t" \
38887 + "movel "#tmp",%%a2\n\t"
38888 +
38889 +#endif
38890 +
38891 +#endif /* __CF_M68K_ENTRY_H */
38892 --- /dev/null
38893 +++ b/include/asm-m68k/cfmmu.h
38894 @@ -0,0 +1,104 @@
38895 +/*
38896 + * Definitions for Coldfire V4e MMU
38897 + */
38898 +#include <asm/movs.h>
38899 +
38900 +#ifndef __CF_MMU_H__
38901 +#define __CF_MMU_H__
38902 +
38903 +
38904 +#define MMU_BASE 0xE1000000
38905 +
38906 +
38907 +#define MMUCR (MMU_BASE+0x00)
38908 +#define MMUCR_ASMN 1
38909 +#define MMUCR_ASM (1<<MMUCR_ASMN)
38910 +#define MMUCR_ENN 0
38911 +#define MMUCR_EN (1<<MMUCR_ENN)
38912 +
38913 +#define MMUOR REG16(MMU_BASE+0x04+0x02)
38914 +#define MMUOR_AAN 16
38915 +#define MMUOR_AA (0xffff<<MMUOR_AAN)
38916 +#define MMUOR_STLBN 8
38917 +#define MMUOR_STLB (1<<MMUOR_STLBN)
38918 +#define MMUOR_CAN 7
38919 +#define MMUOR_CA (1<<MMUOR_CAN)
38920 +#define MMUOR_CNLN 6
38921 +#define MMUOR_CNL (1<<MMUOR_CNLN)
38922 +#define MMUOR_CASN 5
38923 +#define MMUOR_CAS (1<<MMUOR_CASN)
38924 +#define MMUOR_ITLBN 4
38925 +#define MMUOR_ITLB (1<<MMUOR_ITLBN)
38926 +#define MMUOR_ADRN 3
38927 +#define MMUOR_ADR (1<<MMUOR_ADRN)
38928 +#define MMUOR_RWN 2
38929 +#define MMUOR_RW (1<<MMUOR_RWN)
38930 +#define MMUOR_ACCN 1
38931 +#define MMUOR_ACC (1<<MMUOR_ACCN)
38932 +#define MMUOR_UAAN 0
38933 +#define MMUOR_UAA (1<<MMUOR_UAAN)
38934 +
38935 +#define MMUSR REG32(MMU_BASE+0x08)
38936 +#define MMUSR_SPFN 5
38937 +#define MMUSR_SPF (1<<MMUSR_SPFN)
38938 +#define MMUSR_RFN 4
38939 +#define MMUSR_RF (1<<MMUSR_RFN)
38940 +#define MMUSR_WFN 3
38941 +#define MMUSR_WF (1<<MMUSR_WFN)
38942 +#define MMUSR_HITN 1
38943 +#define MMUSR_HIT (1<<MMUSR_HITN)
38944 +
38945 +#define MMUAR REG32(MMU_BASE+0x10)
38946 +#define MMUAR_VPN 1
38947 +#define MMUAR_VP (0xfffffffe)
38948 +#define MMUAR_SN 0
38949 +#define MMUAR_S (1<<MMUAR_SN)
38950 +
38951 +#define MMUTR REG32(MMU_BASE+0x14)
38952 +#define MMUTR_VAN 10
38953 +#define MMUTR_VA (0xfffffc00)
38954 +#define MMUTR_IDN 2
38955 +#define MMUTR_ID (0xff<<MMUTR_IDN)
38956 +#define MMUTR_SGN 1
38957 +#define MMUTR_SG (1<<MMUTR_SGN)
38958 +#define MMUTR_VN 0
38959 +#define MMUTR_V (1<<MMUTR_VN)
38960 +
38961 +#define MMUDR REG32(MMU_BASE+0x18)
38962 +#define MMUDR_PAN 10
38963 +#define MMUDR_PA (0xfffffc00)
38964 +#define MMUDR_SZN 8
38965 +#define MMUDR_SZ_MASK (0x2<<MMUDR_SZN)
38966 +#define MMUDR_SZ1M (0<<MMUDR_SZN)
38967 +#define MMUDR_SZ4K (1<<MMUDR_SZN)
38968 +#define MMUDR_SZ8K (2<<MMUDR_SZN)
38969 +#define MMUDR_SZ16M (3<<MMUDR_SZN)
38970 +#define MMUDR_CMN 6
38971 +#define MMUDR_INC (2<<MMUDR_CMN)
38972 +#define MMUDR_IC (0<<MMUDR_CMN)
38973 +#define MMUDR_DWT (0<<MMUDR_CMN)
38974 +#define MMUDR_DCB (1<<MMUDR_CMN)
38975 +#define MMUDR_DNCP (2<<MMUDR_CMN)
38976 +#define MMUDR_DNCIP (3<<MMUDR_CMN)
38977 +#define MMUDR_SPN 5
38978 +#define MMUDR_SP (1<<MMUDR_SPN)
38979 +#define MMUDR_RN 4
38980 +#define MMUDR_R (1<<MMUDR_RN)
38981 +#define MMUDR_WN 3
38982 +#define MMUDR_W (1<<MMUDR_WN)
38983 +#define MMUDR_XN 2
38984 +#define MMUDR_X (1<<MMUDR_XN)
38985 +#define MMUDR_LKN 1
38986 +#define MMUDR_LK (1<<MMUDR_LKN)
38987 +
38988 +
38989 +#ifndef __ASSEMBLY__
38990 +#define CF_PMEGS_NUM 256
38991 +#define CF_INVALID_CONTEXT 255
38992 +#define CF_PAGE_PGNUM_MASK (PAGE_MASK)
38993 +
38994 +extern int cf_tlb_miss(struct pt_regs *regs, int write, int dtlb,
38995 + int extension_word);
38996 +#endif /* __ASSEMBLY__*/
38997 +
38998 +#endif /* !__CF_MMU_H__ */
38999 --- /dev/null
39000 +++ b/include/asm-m68k/cf_pgalloc.h
39001 @@ -0,0 +1,103 @@
39002 +#ifndef M68K_CF_PGALLOC_H
39003 +#define M68K_CF_PGALLOC_H
39004 +
39005 +#include <asm/coldfire.h>
39006 +#include <asm/page.h>
39007 +#include <asm/cf_tlbflush.h>
39008 +#include <asm/cf_cacheflush.h>
39009 +
39010 +extern inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
39011 +{
39012 + free_page((unsigned long) pte);
39013 +}
39014 +
39015 +extern const char bad_pmd_string[];
39016 +
39017 +extern inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
39018 + unsigned long address)
39019 +{
39020 + unsigned long page = __get_free_page(GFP_DMA|__GFP_REPEAT);
39021 +
39022 + if (!page)
39023 + return NULL;
39024 +
39025 + memset((void *)page, 0, PAGE_SIZE);
39026 + return (pte_t *) (page);
39027 +}
39028 +
39029 +extern inline pmd_t *pmd_alloc_kernel(pgd_t *pgd, unsigned long address)
39030 +{
39031 + return (pmd_t *) pgd;
39032 +}
39033 +
39034 +#define pmd_alloc_one_fast(mm, address) ({ BUG(); ((pmd_t *)1); })
39035 +#define pmd_alloc_one(mm, address) ({ BUG(); ((pmd_t *)2); })
39036 +
39037 +#define pte_alloc_one_fast(mm, addr) pte_alloc_one(mm, addr)
39038 +
39039 +#define pmd_populate(mm, pmd, page) (pmd_val(*pmd) = \
39040 + (unsigned long)(page_address(page)))
39041 +
39042 +#define pmd_populate_kernel(mm, pmd, pte) (pmd_val(*pmd) = (unsigned long)(pte))
39043 +
39044 +#define pmd_pgtable(pmd) pmd_page(pmd)
39045 +
39046 +static inline void __pte_free_tlb(struct mmu_gather *tlb, struct page *page)
39047 +{
39048 + __free_page(page);
39049 +}
39050 +
39051 +#define __pmd_free_tlb(tlb, pmd) do { } while (0)
39052 +
39053 +static inline struct page *pte_alloc_one(struct mm_struct *mm,
39054 + unsigned long address)
39055 +{
39056 + struct page *page = alloc_pages(GFP_DMA|__GFP_REPEAT, 0);
39057 + pte_t *pte;
39058 +
39059 + if (!page)
39060 + return NULL;
39061 +
39062 + pte = kmap(page);
39063 + if (pte) {
39064 + clear_page(pte);
39065 + __flush_page_to_ram(pte);
39066 + flush_tlb_kernel_page(pte);
39067 + nocache_page(pte);
39068 + }
39069 + kunmap(pte);
39070 +
39071 + return page;
39072 +}
39073 +
39074 +extern inline void pte_free(struct mm_struct *mm, struct page *page)
39075 +{
39076 + __free_page(page);
39077 +}
39078 +
39079 +/*
39080 + * In our implementation, each pgd entry contains 1 pmd that is never allocated
39081 + * or freed. pgd_present is always 1, so this should never be called. -NL
39082 + */
39083 +#define pmd_free(mm, pmd) BUG()
39084 +
39085 +extern inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
39086 +{
39087 + free_page((unsigned long) pgd);
39088 +}
39089 +
39090 +extern inline pgd_t *pgd_alloc(struct mm_struct *mm)
39091 +{
39092 + pgd_t *new_pgd;
39093 +
39094 + new_pgd = (pgd_t *)__get_free_page(GFP_DMA | __GFP_NOWARN);
39095 + if (!new_pgd)
39096 + return NULL;
39097 + memcpy(new_pgd, swapper_pg_dir, PAGE_SIZE);
39098 + memset(new_pgd, 0, PAGE_OFFSET >> PGDIR_SHIFT);
39099 + return new_pgd;
39100 +}
39101 +
39102 +#define pgd_populate(mm, pmd, pte) BUG()
39103 +
39104 +#endif /* M68K_CF_PGALLOC_H */
39105 --- /dev/null
39106 +++ b/include/asm-m68k/cf_pgtable.h
39107 @@ -0,0 +1,357 @@
39108 +#ifndef _CF_PGTABLE_H
39109 +#define _CF_PGTABLE_H
39110 +
39111 +#include <asm/cfmmu.h>
39112 +#include <asm/page.h>
39113 +
39114 +#ifndef __ASSEMBLY__
39115 +#include <asm/virtconvert.h>
39116 +#include <linux/linkage.h>
39117 +
39118 +/* For virtual address to physical address conversion */
39119 +#define VTOP(addr) __pa(addr)
39120 +#define PTOV(addr) __va(addr)
39121 +
39122 +
39123 +#endif /* !__ASSEMBLY__ */
39124 +
39125 +/* Page protection values within PTE. */
39126 +
39127 +/* MMUDR bits, in proper place. */
39128 +#define CF_PAGE_LOCKED (0x00000002)
39129 +#define CF_PAGE_EXEC (0x00000004)
39130 +#define CF_PAGE_WRITABLE (0x00000008)
39131 +#define CF_PAGE_READABLE (0x00000010)
39132 +#define CF_PAGE_SYSTEM (0x00000020)
39133 +#define CF_PAGE_COPYBACK (0x00000040)
39134 +#define CF_PAGE_NOCACHE (0x00000080)
39135 +
39136 +#define CF_CACHEMASK (~0x00000040)
39137 +#define CF_PAGE_MMUDR_MASK (0x000000fe)
39138 +
39139 +#define _PAGE_NOCACHE030 (CF_PAGE_NOCACHE)
39140 +
39141 +/* MMUTR bits, need shifting down. */
39142 +#define CF_PAGE_VALID (0x00000400)
39143 +#define CF_PAGE_SHARED (0x00000800)
39144 +
39145 +#define CF_PAGE_MMUTR_MASK (0x00000c00)
39146 +#define CF_PAGE_MMUTR_SHIFT (10)
39147 +#define CF_ASID_MMU_SHIFT (2)
39148 +
39149 +/* Fake bits, not implemented in CF, will get masked out before
39150 + hitting hardware, and might go away altogether once this port is
39151 + complete. */
39152 +#if PAGE_SHIFT < 13
39153 +#error COLDFIRE Error: Pages must be at least 8k in size
39154 +#endif
39155 +#define CF_PAGE_ACCESSED (0x00001000)
39156 +#define CF_PAGE_FILE (0x00000200)
39157 +#define CF_PAGE_DIRTY (0x00000001)
39158 +
39159 +#define _PAGE_CACHE040 0x020 /* 68040 cache mode, cachable, copyback */
39160 +#define _PAGE_NOCACHE_S 0x040 /* 68040 no-cache mode, serialized */
39161 +#define _PAGE_NOCACHE 0x060 /* 68040 cache mode, non-serialized */
39162 +#define _PAGE_CACHE040W 0x000 /* 68040 cache mode, cachable, write-through */
39163 +#define _DESCTYPE_MASK 0x003
39164 +#define _CACHEMASK040 (~0x060)
39165 +#define _PAGE_GLOBAL040 0x400 /* 68040 global bit, used for kva descs */
39166 +
39167 +
39168 +/* Externally used page protection values. */
39169 +#define _PAGE_PRESENT (CF_PAGE_VALID)
39170 +#define _PAGE_ACCESSED (CF_PAGE_ACCESSED)
39171 +#define _PAGE_DIRTY (CF_PAGE_DIRTY)
39172 +#define _PAGE_READWRITE (CF_PAGE_WRITABLE \
39173 + | CF_PAGE_READABLE \
39174 + | CF_PAGE_SYSTEM \
39175 + | CF_PAGE_SHARED)
39176 +
39177 +/* Compound page protection values. */
39178 +#define PAGE_NONE __pgprot(CF_PAGE_VALID \
39179 + | CF_PAGE_ACCESSED)
39180 +
39181 +#define PAGE_SHARED __pgprot(CF_PAGE_VALID \
39182 + | CF_PAGE_ACCESSED \
39183 + | CF_PAGE_SHARED)
39184 +
39185 +#define PAGE_INIT __pgprot(CF_PAGE_VALID \
39186 + | CF_PAGE_WRITABLE \
39187 + | CF_PAGE_READABLE \
39188 + | CF_PAGE_EXEC \
39189 + | CF_PAGE_SYSTEM \
39190 + | CF_PAGE_SHARED)
39191 +
39192 +#define PAGE_KERNEL __pgprot(CF_PAGE_VALID \
39193 + | CF_PAGE_WRITABLE \
39194 + | CF_PAGE_READABLE \
39195 + | CF_PAGE_EXEC \
39196 + | CF_PAGE_SYSTEM \
39197 + | CF_PAGE_SHARED \
39198 + | CF_PAGE_ACCESSED)
39199 +
39200 +#define PAGE_COPY __pgprot(CF_PAGE_VALID \
39201 + | CF_PAGE_ACCESSED \
39202 + | CF_PAGE_READABLE \
39203 + | CF_PAGE_DIRTY)
39204 +/*
39205 + * Page protections for initialising protection_map. See mm/mmap.c
39206 + * for use. In general, the bit positions are xwr, and P-items are
39207 + * private, the S-items are shared.
39208 + */
39209 +
39210 +#define __P000 PAGE_NONE
39211 +#define __P100 __pgprot(CF_PAGE_VALID \
39212 + | CF_PAGE_ACCESSED \
39213 + | CF_PAGE_EXEC)
39214 +#define __P010 __pgprot(CF_PAGE_VALID \
39215 + | CF_PAGE_WRITABLE \
39216 + | CF_PAGE_ACCESSED)
39217 +#define __P110 __pgprot(CF_PAGE_VALID \
39218 + | CF_PAGE_ACCESSED \
39219 + | CF_PAGE_WRITABLE \
39220 + | CF_PAGE_EXEC)
39221 +#define __P001 __pgprot(CF_PAGE_VALID \
39222 + | CF_PAGE_ACCESSED \
39223 + | CF_PAGE_READABLE)
39224 +#define __P101 __pgprot(CF_PAGE_VALID \
39225 + | CF_PAGE_ACCESSED \
39226 + | CF_PAGE_READABLE \
39227 + | CF_PAGE_EXEC)
39228 +#define __P011 __pgprot(CF_PAGE_VALID \
39229 + | CF_PAGE_READABLE \
39230 + | CF_PAGE_WRITABLE \
39231 + | CF_PAGE_ACCESSED)
39232 +#define __P111 __pgprot(CF_PAGE_VALID \
39233 + | CF_PAGE_ACCESSED \
39234 + | CF_PAGE_WRITABLE \
39235 + | CF_PAGE_READABLE \
39236 + | CF_PAGE_EXEC)
39237 +
39238 +#define __S000 PAGE_NONE
39239 +#define __S100 __pgprot(CF_PAGE_VALID \
39240 + | CF_PAGE_ACCESSED \
39241 + | CF_PAGE_SHARED \
39242 + | CF_PAGE_EXEC)
39243 +#define __S010 PAGE_SHARED
39244 +#define __S110 __pgprot(CF_PAGE_VALID \
39245 + | CF_PAGE_ACCESSED \
39246 + | CF_PAGE_SHARED \
39247 + | CF_PAGE_EXEC)
39248 +#define __S001 __pgprot(CF_PAGE_VALID \
39249 + | CF_PAGE_ACCESSED \
39250 + | CF_PAGE_SHARED \
39251 + | CF_PAGE_READABLE)
39252 +#define __S101 __pgprot(CF_PAGE_VALID \
39253 + | CF_PAGE_ACCESSED \
39254 + | CF_PAGE_SHARED \
39255 + | CF_PAGE_READABLE \
39256 + | CF_PAGE_EXEC)
39257 +#define __S011 __pgprot(CF_PAGE_VALID \
39258 + | CF_PAGE_ACCESSED \
39259 + | CF_PAGE_SHARED \
39260 + | CF_PAGE_READABLE)
39261 +#define __S111 __pgprot(CF_PAGE_VALID \
39262 + | CF_PAGE_ACCESSED \
39263 + | CF_PAGE_SHARED \
39264 + | CF_PAGE_READABLE \
39265 + | CF_PAGE_EXEC)
39266 +
39267 +#define PTE_MASK PAGE_MASK
39268 +#define CF_PAGE_CHG_MASK (PTE_MASK | CF_PAGE_ACCESSED | CF_PAGE_DIRTY)
39269 +
39270 +#ifndef __ASSEMBLY__
39271 +
39272 +/*
39273 + * Conversion functions: convert a page and protection to a page entry,
39274 + * and a page entry and page directory to the page they refer to.
39275 + */
39276 +#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
39277 +
39278 +extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
39279 +{
39280 + pte_val(pte) = (pte_val(pte) & CF_PAGE_CHG_MASK) | pgprot_val(newprot);
39281 + return pte;
39282 +}
39283 +
39284 +#define pmd_set(pmdp, ptep) do {} while (0)
39285 +
39286 +extern inline void pgd_set(pgd_t *pgdp, pmd_t *pmdp)
39287 +{
39288 + pgd_val(*pgdp) = virt_to_phys(pmdp);
39289 +}
39290 +
39291 +#define __pte_page(pte) \
39292 + ((unsigned long) ((pte_val(pte) & CF_PAGE_PGNUM_MASK) + PAGE_OFFSET))
39293 +#define __pmd_page(pmd) ((unsigned long) (pmd_val(pmd)))
39294 +
39295 +extern inline int pte_none(pte_t pte)
39296 +{
39297 + return !pte_val(pte);
39298 +}
39299 +extern inline int pte_present(pte_t pte)
39300 +{
39301 + return pte_val(pte) & CF_PAGE_VALID;
39302 +}
39303 +extern inline void pte_clear(struct mm_struct *mm, unsigned long addr,
39304 + pte_t *ptep)
39305 +{
39306 + pte_val(*ptep) = 0;
39307 +}
39308 +
39309 +#define pte_pagenr(pte) ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT)
39310 +#define pte_page(pte) virt_to_page(__pte_page(pte))
39311 +
39312 +extern inline int pmd_none2(pmd_t *pmd) { return !pmd_val(*pmd); }
39313 +#define pmd_none(pmd) pmd_none2(&(pmd))
39314 +extern inline int pmd_bad2(pmd_t *pmd) { return 0; }
39315 +#define pmd_bad(pmd) pmd_bad2(&(pmd))
39316 +#define pmd_present(pmd) (!pmd_none2(&(pmd)))
39317 +extern inline void pmd_clear(pmd_t *pmdp) { pmd_val(*pmdp) = 0; }
39318 +
39319 +extern inline int pgd_none(pgd_t pgd) { return 0; }
39320 +extern inline int pgd_bad(pgd_t pgd) { return 0; }
39321 +extern inline int pgd_present(pgd_t pgd) { return 1; }
39322 +extern inline void pgd_clear(pgd_t *pgdp) {}
39323 +
39324 +
39325 +#define pte_ERROR(e) \
39326 + printk(KERN_ERR "%s:%d: bad pte %08lx.\n", \
39327 + __FILE__, __LINE__, pte_val(e))
39328 +#define pmd_ERROR(e) \
39329 + printk(KERN_ERR "%s:%d: bad pmd %08lx.\n", \
39330 + __FILE__, __LINE__, pmd_val(e))
39331 +#define pgd_ERROR(e) \
39332 + printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \
39333 + __FILE__, __LINE__, pgd_val(e))
39334 +
39335 +
39336 +/*
39337 + * The following only work if pte_present() is true.
39338 + * Undefined behaviour if not...
39339 + * [we have the full set here even if they don't change from m68k]
39340 + */
39341 +extern inline int pte_read(pte_t pte) \
39342 + { return pte_val(pte) & CF_PAGE_READABLE; }
39343 +extern inline int pte_write(pte_t pte) \
39344 + { return pte_val(pte) & CF_PAGE_WRITABLE; }
39345 +extern inline int pte_exec(pte_t pte) \
39346 + { return pte_val(pte) & CF_PAGE_EXEC; }
39347 +extern inline int pte_dirty(pte_t pte) \
39348 + { return pte_val(pte) & CF_PAGE_DIRTY; }
39349 +extern inline int pte_young(pte_t pte) \
39350 + { return pte_val(pte) & CF_PAGE_ACCESSED; }
39351 +extern inline int pte_file(pte_t pte) \
39352 + { return pte_val(pte) & CF_PAGE_FILE; }
39353 +
39354 +extern inline pte_t pte_wrprotect(pte_t pte) \
39355 + { pte_val(pte) &= ~CF_PAGE_WRITABLE; return pte; }
39356 +extern inline pte_t pte_rdprotect(pte_t pte) \
39357 + { pte_val(pte) &= ~CF_PAGE_READABLE; return pte; }
39358 +extern inline pte_t pte_exprotect(pte_t pte) \
39359 + { pte_val(pte) &= ~CF_PAGE_EXEC; return pte; }
39360 +extern inline pte_t pte_mkclean(pte_t pte) \
39361 + { pte_val(pte) &= ~CF_PAGE_DIRTY; return pte; }
39362 +extern inline pte_t pte_mkold(pte_t pte) \
39363 + { pte_val(pte) &= ~CF_PAGE_ACCESSED; return pte; }
39364 +extern inline pte_t pte_mkwrite(pte_t pte) \
39365 + { pte_val(pte) |= CF_PAGE_WRITABLE; return pte; }
39366 +extern inline pte_t pte_mkread(pte_t pte) \
39367 + { pte_val(pte) |= CF_PAGE_READABLE; return pte; }
39368 +extern inline pte_t pte_mkexec(pte_t pte) \
39369 + { pte_val(pte) |= CF_PAGE_EXEC; return pte; }
39370 +extern inline pte_t pte_mkdirty(pte_t pte) \
39371 + { pte_val(pte) |= CF_PAGE_DIRTY; return pte; }
39372 +extern inline pte_t pte_mkyoung(pte_t pte) \
39373 + { pte_val(pte) |= CF_PAGE_ACCESSED; return pte; }
39374 +extern inline pte_t pte_mknocache(pte_t pte) \
39375 + { pte_val(pte) |= 0x80 | (pte_val(pte) & ~0x40); return pte; }
39376 +extern inline pte_t pte_mkcache(pte_t pte) \
39377 + { pte_val(pte) &= ~CF_PAGE_NOCACHE; return pte; }
39378 +
39379 +#define swapper_pg_dir kernel_pg_dir
39380 +extern pgd_t kernel_pg_dir[PTRS_PER_PGD];
39381 +
39382 +/* Find an entry in a pagetable directory. */
39383 +#define pgd_index(address) ((address) >> PGDIR_SHIFT)
39384 +
39385 +#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
39386 +
39387 +/* Find an entry in a kernel pagetable directory. */
39388 +#define pgd_offset_k(address) pgd_offset(&init_mm, address)
39389 +
39390 +/* Find an entry in the second-level pagetable. */
39391 +extern inline pmd_t *pmd_offset(pgd_t *pgd, unsigned long address)
39392 +{
39393 + return (pmd_t *) pgd;
39394 +}
39395 +
39396 +/* Find an entry in the third-level pagetable. */
39397 +#define __pte_offset(address) ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
39398 +#define pte_offset_kernel(dir, address) ((pte_t *) __pmd_page(*(dir)) + \
39399 + __pte_offset(address))
39400 +
39401 +/* Disable caching for page at given kernel virtual address. */
39402 +static inline void nocache_page(void *vaddr)
39403 +{
39404 + pgd_t *dir;
39405 + pmd_t *pmdp;
39406 + pte_t *ptep;
39407 + unsigned long addr = (unsigned long)vaddr;
39408 +
39409 + dir = pgd_offset_k(addr);
39410 + pmdp = pmd_offset(dir, addr);
39411 + ptep = pte_offset_kernel(pmdp, addr);
39412 + *ptep = pte_mknocache(*ptep);
39413 +}
39414 +
39415 +/* Enable caching for page at given kernel virtual address. */
39416 +static inline void cache_page(void *vaddr)
39417 +{
39418 + pgd_t *dir;
39419 + pmd_t *pmdp;
39420 + pte_t *ptep;
39421 + unsigned long addr = (unsigned long)vaddr;
39422 +
39423 + dir = pgd_offset_k(addr);
39424 + pmdp = pmd_offset(dir, addr);
39425 + ptep = pte_offset_kernel(pmdp, addr);
39426 + *ptep = pte_mkcache(*ptep);
39427 +}
39428 +
39429 +#define PTE_FILE_MAX_BITS 21
39430 +#define PTE_FILE_SHIFT 11
39431 +
39432 +static inline unsigned long pte_to_pgoff(pte_t pte)
39433 +{
39434 + return pte_val(pte) >> PTE_FILE_SHIFT;
39435 +}
39436 +
39437 +static inline pte_t pgoff_to_pte(unsigned pgoff)
39438 +{
39439 + pte_t pte = __pte((pgoff << PTE_FILE_SHIFT) + CF_PAGE_FILE);
39440 + return pte;
39441 +}
39442 +
39443 +/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */
39444 +#define __swp_entry(type, offset) ((swp_entry_t) { (type) | \
39445 + (offset << PTE_FILE_SHIFT) })
39446 +#define __swp_type(x) ((x).val & 0xFF)
39447 +#define __swp_offset(x) ((x).val >> PTE_FILE_SHIFT)
39448 +#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
39449 +#define __swp_entry_to_pte(x) (__pte((x).val))
39450 +
39451 +#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
39452 +
39453 +#define pte_offset_map(pmdp, address) ((pte_t *)__pmd_page(*pmdp) + \
39454 + __pte_offset(address))
39455 +#define pte_offset_map_nested(pmdp, address) pte_offset_map(pmdp, address)
39456 +#define pte_unmap(pte) kunmap(pte)
39457 +#define pte_unmap_nested(pte) kunmap(pte)
39458 +
39459 +#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
39460 +#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
39461 +
39462 +
39463 +#endif /* !__ASSEMBLY__ */
39464 +#endif /* !_CF_PGTABLE_H */
39465 --- /dev/null
39466 +++ b/include/asm-m68k/cf_tlbflush.h
39467 @@ -0,0 +1,59 @@
39468 +#ifndef M68K_CF_TLBFLUSH_H
39469 +#define M68K_CF_TLBFLUSH_H
39470 +
39471 +#include <asm/coldfire.h>
39472 +
39473 +/* Flush all userspace mappings. */
39474 +static inline void flush_tlb_all(void)
39475 +{
39476 + preempt_disable();
39477 + *MMUOR = MMUOR_CNL;
39478 + preempt_enable();
39479 +}
39480 +
39481 +/* Clear user TLB entries within the context named in mm */
39482 +static inline void flush_tlb_mm(struct mm_struct *mm)
39483 +{
39484 + preempt_disable();
39485 + *MMUOR = MMUOR_CNL;
39486 + preempt_enable();
39487 +}
39488 +
39489 +/* Flush a single TLB page. */
39490 +static inline void flush_tlb_page(struct vm_area_struct *vma,
39491 + unsigned long addr)
39492 +{
39493 + preempt_disable();
39494 + *MMUOR = MMUOR_CNL;
39495 + preempt_enable();
39496 +}
39497 +/* Flush a range of pages from TLB. */
39498 +
39499 +static inline void flush_tlb_range(struct mm_struct *mm,
39500 + unsigned long start, unsigned long end)
39501 +{
39502 + preempt_disable();
39503 + *MMUOR = MMUOR_CNL;
39504 + preempt_enable();
39505 +}
39506 +
39507 +/* Flush kernel page from TLB. */
39508 +static inline void flush_tlb_kernel_page(void *addr)
39509 +{
39510 + preempt_disable();
39511 + *MMUOR = MMUOR_CNL;
39512 + preempt_enable();
39513 +}
39514 +
39515 +static inline void flush_tlb_kernel_range(unsigned long start,
39516 + unsigned long end)
39517 +{
39518 + flush_tlb_all();
39519 +}
39520 +
39521 +extern inline void flush_tlb_pgtables(struct mm_struct *mm,
39522 + unsigned long start, unsigned long end)
39523 +{
39524 +}
39525 +
39526 +#endif /* M68K_CF_TLBFLUSH_H */
39527 --- /dev/null
39528 +++ b/include/asm-m68k/cf_uaccess.h
39529 @@ -0,0 +1,376 @@
39530 +#ifndef __M68K_CF_UACCESS_H
39531 +#define __M68K_CF_UACCESS_H
39532 +
39533 +/*
39534 + * User space memory access functions
39535 + */
39536 +
39537 +/* The "moves" command is not available in the CF instruction set. */
39538 +#include <linux/compiler.h>
39539 +#include <linux/errno.h>
39540 +#include <linux/types.h>
39541 +#include <linux/sched.h>
39542 +#include <asm/segment.h>
39543 +
39544 +#define VERIFY_READ 0
39545 +#define VERIFY_WRITE 1
39546 +
39547 +/* We let the MMU do all checking */
39548 +#define access_ok(type, addr, size) 1
39549 +
39550 +/*
39551 + * The exception table consists of pairs of addresses: the first is the
39552 + * address of an instruction that is allowed to fault, and the second is
39553 + * the address at which the program should continue. No registers are
39554 + * modified, so it is entirely up to the continuation code to figure out
39555 + * what to do.
39556 + *
39557 + * All the routines below use bits of fixup code that are out of line
39558 + * with the main instruction path. This means when everything is well,
39559 + * we don't even have to jump over them. Further, they do not intrude
39560 + * on our cache or tlb entries.
39561 + */
39562 +
39563 +struct exception_table_entry
39564 +{
39565 + unsigned long insn, fixup;
39566 +};
39567 +
39568 +extern int __put_user_bad(void);
39569 +extern int __get_user_bad(void);
39570 +
39571 +#define __put_user_asm(res, x, ptr, bwl, reg, err) \
39572 +asm volatile ("\n" \
39573 + "1: move."#bwl" %2,%1\n" \
39574 + "2:\n" \
39575 + " .section .fixup,\"ax\"\n" \
39576 + " .even\n" \
39577 + "10: moveq.l %3,%0\n" \
39578 + " jra 2b\n" \
39579 + " .previous\n" \
39580 + "\n" \
39581 + " .section __ex_table,\"a\"\n" \
39582 + " .align 4\n" \
39583 + " .long 1b,10b\n" \
39584 + " .long 2b,10b\n" \
39585 + " .previous" \
39586 + : "+d" (res), "=m" (*(ptr)) \
39587 + : #reg (x), "i" (err))
39588 +
39589 +/*
39590 + * These are the main single-value transfer routines. They automatically
39591 + * use the right size if we just have the right pointer type.
39592 + */
39593 +
39594 +#define __put_user(x, ptr) \
39595 +({ \
39596 + typeof(*(ptr)) __pu_val = (x); \
39597 + int __pu_err = 0; \
39598 + __chk_user_ptr(ptr); \
39599 + switch (sizeof (*(ptr))) { \
39600 + case 1: \
39601 + __put_user_asm(__pu_err, __pu_val, ptr, b, d, -EFAULT); \
39602 + break; \
39603 + case 2: \
39604 + __put_user_asm(__pu_err, __pu_val, ptr, w, d, -EFAULT); \
39605 + break; \
39606 + case 4: \
39607 + __put_user_asm(__pu_err, __pu_val, ptr, l, r, -EFAULT); \
39608 + break; \
39609 + case 8: \
39610 + { \
39611 + const void __user *__pu_ptr = (ptr); \
39612 + asm volatile ("\n" \
39613 + "1: move.l %2,(%1)+\n" \
39614 + "2: move.l %R2,(%1)\n" \
39615 + "3:\n" \
39616 + " .section .fixup,\"ax\"\n" \
39617 + " .even\n" \
39618 + "10: movel %3,%0\n" \
39619 + " jra 3b\n" \
39620 + " .previous\n" \
39621 + "\n" \
39622 + " .section __ex_table,\"a\"\n" \
39623 + " .align 4\n" \
39624 + " .long 1b,10b\n" \
39625 + " .long 2b,10b\n" \
39626 + " .long 3b,10b\n" \
39627 + " .previous" \
39628 + : "+d" (__pu_err), "+a" (__pu_ptr) \
39629 + : "r" (__pu_val), "i" (-EFAULT) \
39630 + : "memory"); \
39631 + break; \
39632 + } \
39633 + default: \
39634 + __pu_err = __put_user_bad(); \
39635 + break; \
39636 + } \
39637 + __pu_err; \
39638 +})
39639 +#define put_user(x, ptr) __put_user(x, ptr)
39640 +
39641 +
39642 +#define __get_user_asm(res, x, ptr, type, bwl, reg, err) ({ \
39643 + type __gu_val; \
39644 + asm volatile ("\n" \
39645 + "1: move."#bwl" %2,%1\n" \
39646 + "2:\n" \
39647 + " .section .fixup,\"ax\"\n" \
39648 + " .even\n" \
39649 + "10: move.l %3,%0\n" \
39650 + " subl %1,%1\n" \
39651 + " jra 2b\n" \
39652 + " .previous\n" \
39653 + "\n" \
39654 + " .section __ex_table,\"a\"\n" \
39655 + " .align 4\n" \
39656 + " .long 1b,10b\n" \
39657 + " .previous" \
39658 + : "+d" (res), "=&" #reg (__gu_val) \
39659 + : "m" (*(ptr)), "i" (err)); \
39660 + (x) = (typeof(*(ptr)))(unsigned long)__gu_val; \
39661 +})
39662 +
39663 +#define __get_user(x, ptr) \
39664 +({ \
39665 + int __gu_err = 0; \
39666 + __chk_user_ptr(ptr); \
39667 + switch (sizeof(*(ptr))) { \
39668 + case 1: \
39669 + __get_user_asm(__gu_err, x, ptr, u8, b, d, -EFAULT); \
39670 + break; \
39671 + case 2: \
39672 + __get_user_asm(__gu_err, x, ptr, u16, w, d, -EFAULT); \
39673 + break; \
39674 + case 4: \
39675 + __get_user_asm(__gu_err, x, ptr, u32, l, r, -EFAULT); \
39676 + break; \
39677 +/* case 8: disabled because gcc-4.1 has a broken typeof \
39678 + { \
39679 + const void *__gu_ptr = (ptr); \
39680 + u64 __gu_val; \
39681 + asm volatile ("\n" \
39682 + "1: move.l (%2)+,%1\n" \
39683 + "2: move.l (%2),%R1\n" \
39684 + "3:\n" \
39685 + " .section .fixup,\"ax\"\n" \
39686 + " .even\n" \
39687 + "10: move.l %3,%0\n" \
39688 + " subl %1,%1\n" \
39689 + " subl %R1,%R1\n" \
39690 + " jra 3b\n" \
39691 + " .previous\n" \
39692 + "\n" \
39693 + " .section __ex_table,\"a\"\n" \
39694 + " .align 4\n" \
39695 + " .long 1b,10b\n" \
39696 + " .long 2b,10b\n" \
39697 + " .previous" \
39698 + : "+d" (__gu_err), "=&r" (__gu_val), \
39699 + "+a" (__gu_ptr) \
39700 + : "i" (-EFAULT) \
39701 + : "memory"); \
39702 + (x) = (typeof(*(ptr)))__gu_val; \
39703 + break; \
39704 + } */ \
39705 + default: \
39706 + __gu_err = __get_user_bad(); \
39707 + break; \
39708 + } \
39709 + __gu_err; \
39710 +})
39711 +#define get_user(x, ptr) __get_user(x, ptr)
39712 +
39713 +unsigned long __generic_copy_from_user(void *to, const void __user *from,
39714 + unsigned long n);
39715 +unsigned long __generic_copy_to_user(void __user *to, const void *from,
39716 + unsigned long n);
39717 +
39718 +#define __constant_copy_from_user_asm(res, to, from, tmp, n, s1, s2, s3)\
39719 + asm volatile ("\n" \
39720 + "1: move."#s1" (%2)+,%3\n" \
39721 + " move."#s1" %3,(%1)+\n" \
39722 + "2: move."#s2" (%2)+,%3\n" \
39723 + " move."#s2" %3,(%1)+\n" \
39724 + " .ifnc \""#s3"\",\"\"\n" \
39725 + "3: move."#s3" (%2)+,%3\n" \
39726 + " move."#s3" %3,(%1)+\n" \
39727 + " .endif\n" \
39728 + "4:\n" \
39729 + " .section __ex_table,\"a\"\n" \
39730 + " .align 4\n" \
39731 + " .long 1b,10f\n" \
39732 + " .long 2b,20f\n" \
39733 + " .ifnc \""#s3"\",\"\"\n" \
39734 + " .long 3b,30f\n" \
39735 + " .endif\n" \
39736 + " .previous\n" \
39737 + "\n" \
39738 + " .section .fixup,\"ax\"\n" \
39739 + " .even\n" \
39740 + "10: clr."#s1" (%1)+\n" \
39741 + "20: clr."#s2" (%1)+\n" \
39742 + " .ifnc \""#s3"\",\"\"\n" \
39743 + "30: clr."#s3" (%1)+\n" \
39744 + " .endif\n" \
39745 + " moveq.l #"#n",%0\n" \
39746 + " jra 4b\n" \
39747 + " .previous\n" \
39748 + : "+d" (res), "+&a" (to), "+a" (from), "=&d" (tmp) \
39749 + : : "memory")
39750 +
39751 +static __always_inline unsigned long
39752 +__constant_copy_from_user(void *to, const void __user *from, unsigned long n)
39753 +{
39754 + unsigned long res = 0, tmp;
39755 +
39756 + switch (n) {
39757 + case 1:
39758 + __get_user_asm(res, *(u8 *)to, (u8 __user *)from, u8, b, d, 1);
39759 + break;
39760 + case 2:
39761 + __get_user_asm(res, *(u16 *)to, (u16 __user *)from, u16, w,
39762 + d, 2);
39763 + break;
39764 + case 3:
39765 + __constant_copy_from_user_asm(res, to, from, tmp, 3, w, b,);
39766 + break;
39767 + case 4:
39768 + __get_user_asm(res, *(u32 *)to, (u32 __user *)from, u32, l,
39769 + r, 4);
39770 + break;
39771 + case 5:
39772 + __constant_copy_from_user_asm(res, to, from, tmp, 5, l, b,);
39773 + break;
39774 + case 6:
39775 + __constant_copy_from_user_asm(res, to, from, tmp, 6, l, w,);
39776 + break;
39777 + case 7:
39778 + __constant_copy_from_user_asm(res, to, from, tmp, 7, l, w, b);
39779 + break;
39780 + case 8:
39781 + __constant_copy_from_user_asm(res, to, from, tmp, 8, l, l,);
39782 + break;
39783 + case 9:
39784 + __constant_copy_from_user_asm(res, to, from, tmp, 9, l, l, b);
39785 + break;
39786 + case 10:
39787 + __constant_copy_from_user_asm(res, to, from, tmp, 10, l, l, w);
39788 + break;
39789 + case 12:
39790 + __constant_copy_from_user_asm(res, to, from, tmp, 12, l, l, l);
39791 + break;
39792 + default:
39793 + /* we limit the inlined version to 3 moves */
39794 + return __generic_copy_from_user(to, from, n);
39795 + }
39796 +
39797 + return res;
39798 +}
39799 +
39800 +#define __constant_copy_to_user_asm(res, to, from, tmp, n, s1, s2, s3) \
39801 + asm volatile ("\n" \
39802 + " move."#s1" (%2)+,%3\n" \
39803 + "11: move."#s1" %3,(%1)+\n" \
39804 + "12: move."#s2" (%2)+,%3\n" \
39805 + "21: move."#s2" %3,(%1)+\n" \
39806 + "22:\n" \
39807 + " .ifnc \""#s3"\",\"\"\n" \
39808 + " move."#s3" (%2)+,%3\n" \
39809 + "31: move."#s3" %3,(%1)+\n" \
39810 + "32:\n" \
39811 + " .endif\n" \
39812 + "4:\n" \
39813 + "\n" \
39814 + " .section __ex_table,\"a\"\n" \
39815 + " .align 4\n" \
39816 + " .long 11b,5f\n" \
39817 + " .long 12b,5f\n" \
39818 + " .long 21b,5f\n" \
39819 + " .long 22b,5f\n" \
39820 + " .ifnc \""#s3"\",\"\"\n" \
39821 + " .long 31b,5f\n" \
39822 + " .long 32b,5f\n" \
39823 + " .endif\n" \
39824 + " .previous\n" \
39825 + "\n" \
39826 + " .section .fixup,\"ax\"\n" \
39827 + " .even\n" \
39828 + "5: moveq.l #"#n",%0\n" \
39829 + " jra 4b\n" \
39830 + " .previous\n" \
39831 + : "+d" (res), "+a" (to), "+a" (from), "=&d" (tmp) \
39832 + : : "memory")
39833 +
39834 +static __always_inline unsigned long
39835 +__constant_copy_to_user(void __user *to, const void *from, unsigned long n)
39836 +{
39837 + unsigned long res = 0, tmp;
39838 +
39839 + switch (n) {
39840 + case 1:
39841 + __put_user_asm(res, *(u8 *)from, (u8 __user *)to, b, d, 1);
39842 + break;
39843 + case 2:
39844 + __put_user_asm(res, *(u16 *)from, (u16 __user *)to, w, d, 2);
39845 + break;
39846 + case 3:
39847 + __constant_copy_to_user_asm(res, to, from, tmp, 3, w, b,);
39848 + break;
39849 + case 4:
39850 + __put_user_asm(res, *(u32 *)from, (u32 __user *)to, l, r, 4);
39851 + break;
39852 + case 5:
39853 + __constant_copy_to_user_asm(res, to, from, tmp, 5, l, b,);
39854 + break;
39855 + case 6:
39856 + __constant_copy_to_user_asm(res, to, from, tmp, 6, l, w,);
39857 + break;
39858 + case 7:
39859 + __constant_copy_to_user_asm(res, to, from, tmp, 7, l, w, b);
39860 + break;
39861 + case 8:
39862 + __constant_copy_to_user_asm(res, to, from, tmp, 8, l, l,);
39863 + break;
39864 + case 9:
39865 + __constant_copy_to_user_asm(res, to, from, tmp, 9, l, l, b);
39866 + break;
39867 + case 10:
39868 + __constant_copy_to_user_asm(res, to, from, tmp, 10, l, l, w);
39869 + break;
39870 + case 12:
39871 + __constant_copy_to_user_asm(res, to, from, tmp, 12, l, l, l);
39872 + break;
39873 + default:
39874 + /* limit the inlined version to 3 moves */
39875 + return __generic_copy_to_user(to, from, n);
39876 + }
39877 +
39878 + return res;
39879 +}
39880 +
39881 +#define __copy_from_user(to, from, n) \
39882 +(__builtin_constant_p(n) ? \
39883 + __constant_copy_from_user(to, from, n) : \
39884 + __generic_copy_from_user(to, from, n))
39885 +
39886 +#define __copy_to_user(to, from, n) \
39887 +(__builtin_constant_p(n) ? \
39888 + __constant_copy_to_user(to, from, n) : \
39889 + __generic_copy_to_user(to, from, n))
39890 +
39891 +#define __copy_to_user_inatomic __copy_to_user
39892 +#define __copy_from_user_inatomic __copy_from_user
39893 +
39894 +#define copy_from_user(to, from, n) __copy_from_user(to, from, n)
39895 +#define copy_to_user(to, from, n) __copy_to_user(to, from, n)
39896 +
39897 +long strncpy_from_user(char *dst, const char __user *src, long count);
39898 +long strnlen_user(const char __user *src, long n);
39899 +unsigned long __clear_user(void __user *to, unsigned long n);
39900 +
39901 +#define clear_user __clear_user
39902 +
39903 +#define strlen_user(str) strnlen_user(str, 32767)
39904 +
39905 +#endif /* _M68K_CF_UACCESS_H */
39906 --- a/include/asm-m68k/checksum.h
39907 +++ b/include/asm-m68k/checksum.h
39908 @@ -34,6 +34,7 @@ extern __wsum csum_partial_copy_nocheck(
39909 void *dst, int len,
39910 __wsum sum);
39911
39912 +#ifndef CONFIG_COLDFIRE /* CF has own copy in arch/m68k/lib/checksum.c */
39913 /*
39914 * This is a version of ip_compute_csum() optimized for IP headers,
39915 * which always checksum on 4 octet boundaries.
39916 @@ -59,6 +60,9 @@ static inline __sum16 ip_fast_csum(const
39917 : "memory");
39918 return (__force __sum16)~sum;
39919 }
39920 +#else
39921 +extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl);
39922 +#endif
39923
39924 /*
39925 * Fold a partial checksum
39926 @@ -67,6 +71,11 @@ static inline __sum16 ip_fast_csum(const
39927 static inline __sum16 csum_fold(__wsum sum)
39928 {
39929 unsigned int tmp = (__force u32)sum;
39930 +#ifdef CONFIG_COLDFIRE
39931 + tmp = (tmp & 0xffff) + (tmp >> 16);
39932 + tmp = (tmp & 0xffff) + (tmp >> 16);
39933 + return (__force __sum16) ~tmp;
39934 +#else
39935 __asm__("swap %1\n\t"
39936 "addw %1, %0\n\t"
39937 "clrw %1\n\t"
39938 @@ -74,6 +83,7 @@ static inline __sum16 csum_fold(__wsum s
39939 : "=&d" (sum), "=&d" (tmp)
39940 : "0" (sum), "1" (tmp));
39941 return (__force __sum16)~sum;
39942 +#endif
39943 }
39944
39945
39946 --- /dev/null
39947 +++ b/include/asm-m68k/coldfire_edma.h
39948 @@ -0,0 +1,125 @@
39949 +/*
39950 + * coldfire_edma.h - eDMA driver for Coldfire MCF5445x
39951 + *
39952 + * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
39953 + *
39954 + * Copyright Freescale Semiconductor, Inc. 2007
39955 + *
39956 + * This program is free software; you can redistribute it and/or modify it
39957 + * under the terms of the GNU General Public License as published by the
39958 + * Free Software Foundation; either version 2 of the License, or (at your
39959 + * option) any later version.
39960 + */
39961 +
39962 +#ifndef _LINUX_COLDFIRE_DMA_H
39963 +#define _LINUX_COLDFIRE_DMA_H
39964 +
39965 +#include <linux/interrupt.h>
39966 +#include <asm/mcf5445x_edma.h>
39967 +
39968 +#define EDMA_DRIVER_NAME "ColdFire-eDMA"
39969 +#define DMA_DEV_MINOR 1
39970 +
39971 +#ifdef CONFIG_M5445X
39972 +#define EDMA_INT_CHANNEL_BASE 8
39973 +#define EDMA_INT_CONTROLLER_BASE 64
39974 +#define EDMA_INT_BASE (EDMA_INT_CHANNEL_BASE + \
39975 + EDMA_INT_CONTROLLER_BASE)
39976 +#define EDMA_CHANNELS 16
39977 +#define EDMA_INT_ERR 16 /* edma error interrupt */
39978 +#endif /* CONFIG_M5445X */
39979 +
39980 +typedef irqreturn_t (*edma_irq_handler)(int, void *);
39981 +typedef void (*edma_error_handler)(int, void *);
39982 +
39983 +/* Setup transfer control descriptor (TCD)
39984 + * channel - descriptor number
39985 + * source - source address
39986 + * dest - destination address
39987 + * attr - attributes
39988 + * soff - source offset
39989 + * nbytes - number of bytes to be transfered in minor loop
39990 + * slast - last source address adjustment
39991 + * citer - major loop count
39992 + * biter - begining minor loop count
39993 + * doff - destination offset
39994 + * dlast_sga - last destination address adjustment
39995 + * major_int - generate interrupt after each major loop
39996 + * disable_req - disable DMA request after major loop
39997 + */
39998 +void set_edma_params(int channel, u32 source, u32 dest,
39999 + u32 attr, u32 soff, u32 nbytes, u32 slast,
40000 + u32 citer, u32 biter, u32 doff, u32 dlast_sga,
40001 + int major_int, int disable_req);
40002 +
40003 +/* Starts eDMA transfer on specified channel
40004 + * channel - eDMA TCD number
40005 + */
40006 +static inline void start_edma_transfer(int channel)
40007 +{
40008 + MCF_EDMA_SERQ = channel;
40009 + MCF_EDMA_SSRT = channel;
40010 +}
40011 +
40012 +/* Stops eDMA transfer
40013 + * channel - eDMA TCD number
40014 + */
40015 +static inline void stop_edma_transfer(int channel)
40016 +{
40017 + MCF_EDMA_CINT = channel;
40018 + MCF_EDMA_CERQ = channel;
40019 +}
40020 +
40021 +
40022 +/* Confirm that interrupt has been handled
40023 + * channel - eDMA TCD number
40024 + */
40025 +static inline void confirm_edma_interrupt_handled(int channel)
40026 +{
40027 + MCF_EDMA_CINT = channel;
40028 +}
40029 +
40030 +/* Initialize eDMA controller */
40031 +void init_edma(void);
40032 +
40033 +/* Request eDMA channel:
40034 + * channel - eDMA TCD number
40035 + * handler - channel IRQ callback
40036 + * error_handler - error interrupt handler callback for channel
40037 + * dev - device
40038 + * lock - spinlock to be locked (can be NULL)
40039 + * device_id - device driver name for proc file system output
40040 + */
40041 +int request_edma_channel(int channel,
40042 + edma_irq_handler handler,
40043 + edma_error_handler error_handler,
40044 + void *dev,
40045 + spinlock_t *lock,
40046 + const char *device_id);
40047 +
40048 +/**
40049 + * set_edma_callback - Update the channel callback/arg
40050 + * @channel: channel number
40051 + * @handler: dma handler
40052 + * @error_handler: dma error handler
40053 + * @arg: argument to pass back
40054 + *
40055 + * Returns 0 if success or a negative value if failure
40056 + */
40057 +int set_edma_callback(int channel,
40058 + edma_irq_handler handler,
40059 + edma_error_handler error_handler,
40060 + void *arg);
40061 +
40062 +/* Free eDMA channel
40063 + * channel - eDMA TCD number
40064 + * dev - device
40065 + */
40066 +int free_edma_channel(int channel, void *dev);
40067 +
40068 +/*
40069 + * DMA Modes
40070 + */
40071 +#define DMA_MODE_READ 0
40072 +#define DMA_MODE_WRITE 1
40073 +#endif
40074 --- /dev/null
40075 +++ b/include/asm-m68k/coldfire.h
40076 @@ -0,0 +1,51 @@
40077 +#ifndef _COLDFIRE_H_
40078 +#define _COLDFIRE_H_
40079 +
40080 +#if defined(CONFIG_M5445X)
40081 +#define MCF_MBAR 0x0
40082 +/*
40083 + * Even though RAMBAR1 should be in the 0x8xxxxxxx range there
40084 + * is a problem that needs to be resolved. Currently head.S
40085 + * disables SRAM/RAMBAR1.
40086 + */
40087 +#define MCF_RAMBAR1 0x40000000
40088 +#define MCF_SRAM 0x40000000
40089 +#elif defined(CONFIG_M547X_8X)
40090 +#define MCF_MBAR 0xF0000000
40091 +#define MCF_MMUBAR 0xF1000000
40092 +#define MCF_RAMBAR0 0xF3000000
40093 +#define MCF_RAMBAR1 0xF3001000
40094 +#endif
40095 +
40096 +#define MCF_CLK CONFIG_MCFCLK
40097 +#define MCF_BUSCLK (CONFIG_MCFCLK/2)
40098 +
40099 +#ifdef __ASSEMBLY__
40100 +#define REG32
40101 +#define REG16
40102 +#define REG08
40103 +#else /* __ASSEMBLY__ */
40104 +#define REG32(x) ((volatile unsigned long *)(x))
40105 +#define REG16(x) ((volatile unsigned short *)(x))
40106 +#define REG08(x) ((volatile unsigned char *)(x))
40107 +
40108 +#define MCF_REG32(x) *(volatile unsigned long *)(MCF_MBAR+(x))
40109 +#define MCF_REG16(x) *(volatile unsigned short *)(MCF_MBAR+(x))
40110 +#define MCF_REG08(x) *(volatile unsigned char *)(MCF_MBAR+(x))
40111 +
40112 +void cacr_set(unsigned long);
40113 +unsigned long cacr_get(void);
40114 +
40115 +#define coldfire_enable_irq0(irq) MCF_INTC0_CIMR = (irq);
40116 +
40117 +#define coldfire_enable_irq1(irq) MCF_INTC1_CIMR = (irq);
40118 +
40119 +#define coldfire_disable_irq0(irq) MCF_INTC0_SIMR = (irq);
40120 +
40121 +#define coldfire_disable_irq1(irq) MCF_INTC1_SIMR = (irq);
40122 +
40123 +#define getiprh() MCF_INTC0_IPRH
40124 +
40125 +#endif /* __ASSEMBLY__ */
40126 +
40127 +#endif /* _COLDFIRE_H_ */
40128 --- a/include/asm-m68k/delay.h
40129 +++ b/include/asm-m68k/delay.h
40130 @@ -11,8 +11,25 @@
40131
40132 static inline void __delay(unsigned long loops)
40133 {
40134 +#if defined(CONFIG_COLDFIRE)
40135 + /* The coldfire runs this loop at significantly different speeds
40136 + * depending upon long word alignment or not. We'll pad it to
40137 + * long word alignment which is the faster version.
40138 + * The 0x4a8e is of course a 'tstl %fp' instruction. This is better
40139 + * than using a NOP (0x4e71) instruction because it executes in one
40140 + * cycle not three and doesn't allow for an arbitary delay waiting
40141 + * for bus cycles to finish. Also fp/a6 isn't likely to cause a
40142 + * stall waiting for the register to become valid if such is added
40143 + * to the coldfire at some stage.
40144 + */
40145 + __asm__ __volatile__ (".balignw 4, 0x4a8e\n\t"
40146 + "1: subql #1, %0\n\t"
40147 + "jcc 1b"
40148 + : "=d" (loops) : "0" (loops));
40149 +#else
40150 __asm__ __volatile__ ("1: subql #1,%0; jcc 1b"
40151 : "=d" (loops) : "0" (loops));
40152 +#endif
40153 }
40154
40155 extern void __bad_udelay(void);
40156 @@ -26,12 +43,17 @@ extern void __bad_udelay(void);
40157 */
40158 static inline void __const_udelay(unsigned long xloops)
40159 {
40160 +#if defined(CONFIG_COLDFIRE)
40161 +
40162 + __delay(((((unsigned long long) xloops * loops_per_jiffy))>>32)*HZ);
40163 +#else
40164 unsigned long tmp;
40165
40166 __asm__ ("mulul %2,%0:%1"
40167 : "=d" (xloops), "=d" (tmp)
40168 : "d" (xloops), "1" (loops_per_jiffy));
40169 __delay(xloops * HZ);
40170 +#endif
40171 }
40172
40173 static inline void __udelay(unsigned long usecs)
40174 @@ -46,12 +68,16 @@ static inline void __udelay(unsigned lon
40175 static inline unsigned long muldiv(unsigned long a, unsigned long b,
40176 unsigned long c)
40177 {
40178 +#if defined(CONFIG_COLDFIRE)
40179 + return (long)(((unsigned long long)a * b)/c);
40180 +#else
40181 unsigned long tmp;
40182
40183 __asm__ ("mulul %2,%0:%1; divul %3,%0:%1"
40184 : "=d" (tmp), "=d" (a)
40185 : "d" (b), "d" (c), "1" (a));
40186 return a;
40187 +#endif
40188 }
40189
40190 #endif /* defined(_M68K_DELAY_H) */
40191 --- a/include/asm-m68k/div64.h
40192 +++ b/include/asm-m68k/div64.h
40193 @@ -5,6 +5,7 @@
40194
40195 /* n = n / base; return rem; */
40196
40197 +#ifndef CONFIG_COLDFIRE
40198 #define do_div(n, base) ({ \
40199 union { \
40200 unsigned long n32[2]; \
40201 @@ -24,6 +25,9 @@
40202 (n) = __n.n64; \
40203 __rem; \
40204 })
40205 +#else
40206 +# include <asm-generic/div64.h>
40207 +#endif
40208
40209 extern uint64_t div64_64(uint64_t dividend, uint64_t divisor);
40210 #endif /* _M68K_DIV64_H */
40211 --- a/include/asm-m68k/dma.h
40212 +++ b/include/asm-m68k/dma.h
40213 @@ -1,16 +1,120 @@
40214 #ifndef _M68K_DMA_H
40215 #define _M68K_DMA_H 1
40216
40217 -
40218 /* it's useless on the m68k, but unfortunately needed by the new
40219 bootmem allocator (but this should do it for this) */
40220 #define MAX_DMA_ADDRESS PAGE_OFFSET
40221
40222 +#ifndef CONFIG_COLDFIRE
40223 #define MAX_DMA_CHANNELS 8
40224
40225 extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
40226 extern void free_dma(unsigned int dmanr); /* release it again */
40227
40228 +#else /* not (defined(CONFIG_MCF5474) || defined(CONFIG_MCF5484) || defined(CONFIG_MCF5475) || defined(CONFIG_MCF5485)) */
40229 +
40230 +/************************************************
40231 + * Multichannel DMA definitions *
40232 + ************************************************/
40233 +#ifdef CONFIG_MCD_DMA
40234 +#include <asm/MCD_dma.h>
40235 +#include <asm/m5485dma.h>
40236 +
40237 +struct scatterlist;
40238 +
40239 +#define MAX_DMA_CHANNELS NCHANNELS
40240 +/*
40241 + * identifiers for each initiator/requestor
40242 + */
40243 +#define DMA_ALWAYS (0)
40244 +#define DMA_DSPI_RX (1)
40245 +#define DMA_DSPI_TX (2)
40246 +#define DMA_DREQ0 (3)
40247 +#define DMA_PSC0_RX (4)
40248 +#define DMA_PSC0_TX (5)
40249 +#define DMA_USBEP0 (6)
40250 +#define DMA_USBEP1 (7)
40251 +#define DMA_USBEP2 (8)
40252 +#define DMA_USBEP3 (9)
40253 +#define DMA_PCI_TX (10)
40254 +#define DMA_PCI_RX (11)
40255 +#define DMA_PSC1_RX (12)
40256 +#define DMA_PSC1_TX (13)
40257 +#define DMA_I2C_RX (14)
40258 +#define DMA_I2C_TX (15)
40259 +#define DMA_FEC0_RX (16)
40260 +#define DMA_FEC0_TX (17)
40261 +#define DMA_FEC1_RX (18)
40262 +#define DMA_FEC1_TX (19)
40263 +#define DMA_DREQ1 (20)
40264 +#define DMA_CTM0 (21)
40265 +#define DMA_CTM1 (22)
40266 +#define DMA_CTM2 (23)
40267 +#define DMA_CTM3 (24)
40268 +#define DMA_CTM4 (25)
40269 +#define DMA_CTM5 (26)
40270 +#define DMA_CTM6 (27)
40271 +#define DMA_CTM7 (28)
40272 +#define DMA_USBEP4 (29)
40273 +#define DMA_USBEP5 (30)
40274 +#define DMA_USBEP6 (31)
40275 +#define DMA_PSC2_RX (32)
40276 +#define DMA_PSC2_TX (33)
40277 +#define DMA_PSC3_RX (34)
40278 +#define DMA_PSC3_TX (35)
40279 +#define DMA_FEC_RX(x) ((x == 0) ? DMA_FEC0_RX : DMA_FEC1_RX)
40280 +#define DMA_FEC_TX(x) ((x == 0) ? DMA_FEC0_TX : DMA_FEC1_TX)
40281 +
40282 +int dma_set_initiator(int);
40283 +unsigned int dma_get_initiator(int);
40284 +void dma_remove_initiator(int);
40285 +int dma_set_channel(int);
40286 +int dma_get_channel(int);
40287 +void dma_remove_channel(int);
40288 +int dma_set_channel_fec(int requestor);
40289 +int dma_connect(int channel, int address);
40290 +int dma_disconnect(int channel);
40291 +void dma_remove_channel_by_number(int channel);
40292 +int dma_init(void);
40293 +
40294 +#endif /* CONFIG_MCD_DMA */
40295 +
40296 +extern spinlock_t dma_spin_lock;
40297 +
40298 +static __inline__ unsigned long claim_dma_lock(void)
40299 +{
40300 + unsigned long flags;
40301 + spin_lock_irqsave(&dma_spin_lock, flags);
40302 + return flags;
40303 +}
40304 +
40305 +static __inline__ void release_dma_lock(unsigned long flags)
40306 +{
40307 + spin_unlock_irqrestore(&dma_spin_lock, flags);
40308 +}
40309 +
40310 +
40311 +/*
40312 + * Linux standard DMA stuff
40313 + */
40314 +#if 0
40315 +int request_dma(unsigned int channel, const char * device_id);
40316 +void free_dma(unsigned int channel);
40317 +void enable_dma(unsigned int channel);
40318 +void disable_dma(unsigned int channel);
40319 +int dma_channel_active(unsigned int channel);
40320 +void set_dma_sg(unsigned int channel, struct scatterlist *sg, int nr_sg);
40321 +void set_dma_page(unsigned int channel, char pagenr);
40322 +void set_dma_addr(unsigned int channel, unsigned long physaddr);
40323 +void set_dma_count(unsigned int channel, unsigned long count);
40324 +void set_dma_mode(unsigned int channel, unsigned int mode);
40325 +void set_dma_speed(unsigned int channel, int cycle_ns);
40326 +int get_dma_residue(unsigned int channel);
40327 +#endif
40328 +#define clear_dma_ff(channel)
40329 +
40330 +#endif /* not (defined(CONFIG_MCF5474) || defined(CONFIG_MCF5484) || defined(CONFIG_MCF5475) || defined(CONFIG_MCF5485)) */
40331 +
40332 #ifdef CONFIG_PCI
40333 extern int isa_dma_bridge_buggy;
40334 #else
40335 --- a/include/asm-m68k/elf.h
40336 +++ b/include/asm-m68k/elf.h
40337 @@ -34,6 +34,26 @@
40338 #define R_68K_GLOB_DAT 20
40339 #define R_68K_JMP_SLOT 21
40340 #define R_68K_RELATIVE 22
40341 +/* TLS static relocations */
40342 +#define R_68K_TLS_GD32 25
40343 +#define R_68K_TLS_GD16 26
40344 +#define R_68K_TLS_GD8 27
40345 +#define R_68K_TLS_LDM32 28
40346 +#define R_68K_TLS_LDM16 29
40347 +#define R_68K_TLS_LDM8 30
40348 +#define R_68K_TLS_LDO32 31
40349 +#define R_68K_TLS_LDO16 32
40350 +#define R_68K_TLS_LDO8 33
40351 +#define R_68K_TLS_IE32 34
40352 +#define R_68K_TLS_IE16 35
40353 +#define R_68K_TLS_IE8 36
40354 +#define R_68K_TLS_LE32 37
40355 +#define R_68K_TLS_LE16 38
40356 +#define R_68K_TLS_LE8 39
40357 +/* TLS dynamic relocations */
40358 +#define R_68K_TLS_DTPMOD32 40
40359 +#define R_68K_TLS_DTPREL32 41
40360 +#define R_68K_TLS_TPREL32 42
40361
40362 typedef unsigned long elf_greg_t;
40363
40364 @@ -60,7 +80,7 @@ typedef struct user_m68kfp_struct elf_fp
40365 #define ELF_PLAT_INIT(_r, load_addr) _r->a1 = 0
40366
40367 #define USE_ELF_CORE_DUMP
40368 -#ifndef CONFIG_SUN3
40369 +#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
40370 #define ELF_EXEC_PAGESIZE 4096
40371 #else
40372 #define ELF_EXEC_PAGESIZE 8192
40373 @@ -116,4 +136,35 @@ typedef struct user_m68kfp_struct elf_fp
40374
40375 #define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
40376
40377 +/*
40378 + * VDSO
40379 + */
40380 +#ifdef CONFIG_VSYSCALL
40381 +extern unsigned int vdso_enabled;
40382 +
40383 +#define VDSO_BASE ((unsigned long)current->mm->context.vdso)
40384 +#define VDSO_SYM(x) (VDSO_BASE + (unsigned long)(x))
40385 +
40386 +#define VSYSCALL_AUX_ENT \
40387 + if (vdso_enabled) \
40388 + NEW_AUX_ENT(AT_SYSINFO_EHDR, VDSO_BASE);
40389 +
40390 +/* additional pages */
40391 +#define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1
40392 +
40393 +struct linux_binprm;
40394 +extern int arch_setup_additional_pages(struct linux_binprm *bprm,
40395 + int executable_stack);
40396 +
40397 +#else
40398 +/* no VSYSCALL_AUX_ENT */
40399 +#define VSYSCALL_AUX_ENT
40400 +#endif
40401 +
40402 +#define ARCH_DLINFO \
40403 +do { \
40404 + /* vsyscall entry */ \
40405 + VSYSCALL_AUX_ENT; \
40406 +} while (0);
40407 +
40408 #endif
40409 --- a/include/asm-m68k/fpu.h
40410 +++ b/include/asm-m68k/fpu.h
40411 @@ -12,6 +12,8 @@
40412 #define FPSTATESIZE (96/sizeof(unsigned char))
40413 #elif defined(CONFIG_M68KFPU_EMU)
40414 #define FPSTATESIZE (28/sizeof(unsigned char))
40415 +#elif defined(CONFIG_CFV4E)
40416 +#define FPSTATESIZE (16/sizeof(unsigned char))
40417 #elif defined(CONFIG_M68060)
40418 #define FPSTATESIZE (12/sizeof(unsigned char))
40419 #else
40420 --- a/include/asm-m68k/io.h
40421 +++ b/include/asm-m68k/io.h
40422 @@ -204,6 +204,12 @@ static inline u16 __iomem *isa_mtw(unsig
40423 #define isa_outw(val,port) (ISA_SEX ? out_be16(isa_itw(port),(val)) : out_le16(isa_itw(port),(val)))
40424 #define isa_outl(val,port) (ISA_SEX ? out_be32(isa_itl(port),(val)) : out_le32(isa_itl(port),(val)))
40425
40426 +#ifndef CONFIG_COLDFIRE
40427 +#define isa_readb(p) in_8(isa_mtb(p))
40428 +#define isa_readw(p) (ISA_SEX ? in_be16(isa_mtw(p)) : in_le16(isa_mtw(p)))
40429 +#define isa_writeb(val,p) out_8(isa_mtb(p),(val))
40430 +#define isa_writew(val,p) (ISA_SEX ? out_be16(isa_mtw(p),(val)) : out_le16(isa_mtw(p),(val)))
40431 +#else
40432 #define isa_readb(p) in_8(isa_mtb((unsigned long)(p)))
40433 #define isa_readw(p) \
40434 (ISA_SEX ? in_be16(isa_mtw((unsigned long)(p))) \
40435 @@ -212,7 +218,7 @@ static inline u16 __iomem *isa_mtw(unsig
40436 #define isa_writew(val,p) \
40437 (ISA_SEX ? out_be16(isa_mtw((unsigned long)(p)),(val)) \
40438 : out_le16(isa_mtw((unsigned long)(p)),(val)))
40439 -
40440 +#endif
40441 static inline void isa_delay(void)
40442 {
40443 switch(ISA_TYPE)
40444 @@ -285,6 +291,29 @@ static inline void isa_delay(void)
40445 #endif /* CONFIG_ISA */
40446
40447 #if defined(CONFIG_PCI)
40448 +#ifdef CONFIG_COLDFIRE
40449 +#define inb_p inb
40450 +#define inw_p inw
40451 +#define inl_p inl
40452 +#define outb_p outb
40453 +#define outw_p outw
40454 +#define outl_p outl
40455 +
40456 +unsigned char pci_inb(long addr);
40457 +unsigned short pci_inw(long addr);
40458 +unsigned long pci_inl(long addr);
40459 +void pci_outb(unsigned char val, long addr);
40460 +void pci_outw(unsigned short val, long addr);
40461 +void pci_outl(unsigned long val, long addr);
40462 +
40463 +void pci_insb(volatile unsigned char* addr, unsigned char* buf, int len);
40464 +void pci_insw(volatile unsigned short* addr, unsigned short* buf, int len);
40465 +void pci_insl(volatile unsigned long* addr, unsigned long* buf, int len);
40466 +
40467 +void pci_outsb(volatile unsigned char* addr, const unsigned char* buf, int len);
40468 +void pci_outsw(volatile unsigned short* addr, const unsigned short* buf, int len);
40469 +void pci_outsl(volatile unsigned long* addr, const unsigned long* buf, int len);
40470 +#endif
40471
40472 #define readl(addr) in_le32(addr)
40473 #define writel(val,addr) out_le32((addr),(val))
40474 @@ -300,12 +329,48 @@ static inline void isa_delay(void)
40475 #define readl_relaxed(addr) readl(addr)
40476
40477 #ifndef CONFIG_ISA
40478 +#ifndef CONFIG_COLDFIRE
40479 #define inb(port) in_8(port)
40480 #define outb(val,port) out_8((port),(val))
40481 #define inw(port) in_le16(port)
40482 #define outw(val,port) out_le16((port),(val))
40483 #define inl(port) in_le32(port)
40484 #define outl(val,port) out_le32((port),(val))
40485 +#define insb(port, buf, nr) \
40486 + raw_insb((u8 *)(port), (u8 *)(buf), (nr))
40487 +#define outsb(port, buf, nr) \
40488 + raw_outsb((u8 *)(port), (u8 *)(buf), (nr))
40489 +#define insw(port, buf, nr) \
40490 + raw_insw_swapw((u16 *)(port), (u16 *)(buf), (nr))
40491 +#define outsw(port, buf, nr) \
40492 + raw_outsw_swapw((u16 *)(port), (u16 *)(buf), (nr))
40493 +#define insl(port, buf, nr) \
40494 + raw_insw_swapw((u16 *)(port), (u16 *)(buf), (nr)<<1)
40495 +#define outsl(port, buf, nr) \
40496 + raw_outsw_swapw((u16 *)(port), (u16 *)(buf), (nr)<<1)
40497 +#else
40498 +#define inb(port) pci_inb(port)
40499 +#define outb(val,port) pci_outb((val),(port))
40500 +#define inw(port) pci_inw(port)
40501 +#define outw(val,port) pci_outw((val),(port))
40502 +#define insb(a,b,c) pci_insb((volatile unsigned char*)a,(unsigned char*)b,c)
40503 +#define insw(a,b,c) pci_insw((volatile unsigned short*)a,(const unsigned short*)b,c)
40504 +#define insl(a,b,c) pci_insl((volatile unsigned long*)a,(const unsigned long*)b,c)
40505 +#define outsb(a,b,c) pci_outsb((volatile unsigned char*)a,(const unsigned char*)b,c)
40506 +#define outsw(a,b,c) pci_outsw((volatile unsigned short*)a,(const unsigned short*)b,c)
40507 +#define outsl(a,b,c) pci_outsl((volatile unsigned long*)a,(const unsigned long*)b,c)
40508 +#define inl(port) pci_inl(port)
40509 +#define outl(val,port) pci_outl((val),(port))
40510 +#endif
40511 +
40512 +#ifndef CONFIG_COLDFIRE
40513 +#define __raw_readb readb
40514 +#define __raw_readw readw
40515 +#define __raw_readl readl
40516 +#define __raw_writeb writeb
40517 +#define __raw_writew writew
40518 +#define __raw_writel writel
40519 +#endif
40520
40521 #else
40522 /*
40523 @@ -397,10 +462,12 @@ static inline void memcpy_toio(volatile
40524 __builtin_memcpy((void __force *) dst, src, count);
40525 }
40526
40527 -#ifndef CONFIG_SUN3
40528 -#define IO_SPACE_LIMIT 0xffff
40529 -#else
40530 +#if defined(CONFIG_SUN3)
40531 #define IO_SPACE_LIMIT 0x0fffffff
40532 +#elif defined(CONFIG_COLDFIRE)
40533 +#define IO_SPACE_LIMIT 0xffffffff
40534 +#else
40535 +#define IO_SPACE_LIMIT 0xffff
40536 #endif
40537
40538 #endif /* __KERNEL__ */
40539 @@ -418,4 +485,31 @@ static inline void memcpy_toio(volatile
40540 */
40541 #define xlate_dev_kmem_ptr(p) p
40542
40543 +#ifdef CONFIG_COLDFIRE
40544 +#define __raw_readb(addr) \
40545 + ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
40546 +#define __raw_readw(addr) \
40547 + ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
40548 +#define __raw_readl(addr) \
40549 + ({ unsigned long __v = (*(volatile unsigned long *) (addr)); __v; })
40550 +#define __raw_writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
40551 +#define __raw_writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
40552 +#define __raw_writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
40553 +
40554 +#define memset_io(a, b, c) memset((void *)(a), (b), (c))
40555 +#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))
40556 +#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))
40557 +#if !defined(readb)
40558 +#define readb(addr) \
40559 + ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
40560 +#define readw(addr) \
40561 + ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
40562 +#define readl(addr) \
40563 + ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
40564 +#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b))
40565 +#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b))
40566 +#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b))
40567 +#endif /* readb */
40568 +#endif /* CONFIG_COLDFIRE */
40569 +
40570 #endif /* _IO_H */
40571 --- a/include/asm-m68k/irq.h
40572 +++ b/include/asm-m68k/irq.h
40573 @@ -11,7 +11,10 @@
40574 * Currently the Atari has 72 and the Amiga 24, but if both are
40575 * supported in the kernel it is better to make room for 72.
40576 */
40577 -#if defined(CONFIG_VME) || defined(CONFIG_SUN3) || defined(CONFIG_SUN3X)
40578 +#if defined(CONFIG_COLDFIRE)
40579 +#define SYS_IRQS 256
40580 +#define NR_IRQS SYS_IRQS
40581 +#elif defined(CONFIG_VME) || defined(CONFIG_SUN3) || defined(CONFIG_SUN3X)
40582 #define NR_IRQS 200
40583 #elif defined(CONFIG_ATARI) || defined(CONFIG_MAC)
40584 #define NR_IRQS 72
40585 --- /dev/null
40586 +++ b/include/asm-m68k/m5485dma.h
40587 @@ -0,0 +1,97 @@
40588 +/*
40589 + * m5485dma.h -- ColdFire 547x/548x DMA controller support.
40590 + */
40591 +#ifndef __MCF548X_DMA_H__
40592 +#define __MCF548X_DMA_H__
40593 +
40594 +
40595 +/* Register read/write macros */
40596 +#define MCF_DMA_DIPR (*(volatile u32*)(void*)(MCF_MBAR+0x008014))
40597 +#define MCF_DMA_DIMR (*(volatile u32*)(void*)(MCF_MBAR+0x008018))
40598 +#define MCF_DMA_IMCR (*(volatile u32*)(void*)(MCF_MBAR+0x00805C))
40599 +
40600 +/* Bit definitions and macros for MCF_DMA_DIPR */
40601 +#define MCF_DMA_DIPR_TASK0 (0x00000001)
40602 +#define MCF_DMA_DIPR_TASK1 (0x00000002)
40603 +#define MCF_DMA_DIPR_TASK2 (0x00000004)
40604 +#define MCF_DMA_DIPR_TASK3 (0x00000008)
40605 +#define MCF_DMA_DIPR_TASK4 (0x00000010)
40606 +#define MCF_DMA_DIPR_TASK5 (0x00000020)
40607 +#define MCF_DMA_DIPR_TASK6 (0x00000040)
40608 +#define MCF_DMA_DIPR_TASK7 (0x00000080)
40609 +#define MCF_DMA_DIPR_TASK8 (0x00000100)
40610 +#define MCF_DMA_DIPR_TASK9 (0x00000200)
40611 +#define MCF_DMA_DIPR_TASK10 (0x00000400)
40612 +#define MCF_DMA_DIPR_TASK11 (0x00000800)
40613 +#define MCF_DMA_DIPR_TASK12 (0x00001000)
40614 +#define MCF_DMA_DIPR_TASK13 (0x00002000)
40615 +#define MCF_DMA_DIPR_TASK14 (0x00004000)
40616 +#define MCF_DMA_DIPR_TASK15 (0x00008000)
40617 +
40618 +/* Bit definitions and macros for MCF_DMA_DIMR */
40619 +#define MCF_DMA_DIMR_TASK0 (0x00000001)
40620 +#define MCF_DMA_DIMR_TASK1 (0x00000002)
40621 +#define MCF_DMA_DIMR_TASK2 (0x00000004)
40622 +#define MCF_DMA_DIMR_TASK3 (0x00000008)
40623 +#define MCF_DMA_DIMR_TASK4 (0x00000010)
40624 +#define MCF_DMA_DIMR_TASK5 (0x00000020)
40625 +#define MCF_DMA_DIMR_TASK6 (0x00000040)
40626 +#define MCF_DMA_DIMR_TASK7 (0x00000080)
40627 +#define MCF_DMA_DIMR_TASK8 (0x00000100)
40628 +#define MCF_DMA_DIMR_TASK9 (0x00000200)
40629 +#define MCF_DMA_DIMR_TASK10 (0x00000400)
40630 +#define MCF_DMA_DIMR_TASK11 (0x00000800)
40631 +#define MCF_DMA_DIMR_TASK12 (0x00001000)
40632 +#define MCF_DMA_DIMR_TASK13 (0x00002000)
40633 +#define MCF_DMA_DIMR_TASK14 (0x00004000)
40634 +#define MCF_DMA_DIMR_TASK15 (0x00008000)
40635 +
40636 +/* Bit definitions and macros for MCF_DMA_IMCR */
40637 +#define MCF_DMA_IMCR_SRC16(x) (((x)&0x00000003)<<0)
40638 +#define MCF_DMA_IMCR_SRC17(x) (((x)&0x00000003)<<2)
40639 +#define MCF_DMA_IMCR_SRC18(x) (((x)&0x00000003)<<4)
40640 +#define MCF_DMA_IMCR_SRC19(x) (((x)&0x00000003)<<6)
40641 +#define MCF_DMA_IMCR_SRC20(x) (((x)&0x00000003)<<8)
40642 +#define MCF_DMA_IMCR_SRC21(x) (((x)&0x00000003)<<10)
40643 +#define MCF_DMA_IMCR_SRC22(x) (((x)&0x00000003)<<12)
40644 +#define MCF_DMA_IMCR_SRC23(x) (((x)&0x00000003)<<14)
40645 +#define MCF_DMA_IMCR_SRC24(x) (((x)&0x00000003)<<16)
40646 +#define MCF_DMA_IMCR_SRC25(x) (((x)&0x00000003)<<18)
40647 +#define MCF_DMA_IMCR_SRC26(x) (((x)&0x00000003)<<20)
40648 +#define MCF_DMA_IMCR_SRC27(x) (((x)&0x00000003)<<22)
40649 +#define MCF_DMA_IMCR_SRC28(x) (((x)&0x00000003)<<24)
40650 +#define MCF_DMA_IMCR_SRC29(x) (((x)&0x00000003)<<26)
40651 +#define MCF_DMA_IMCR_SRC30(x) (((x)&0x00000003)<<28)
40652 +#define MCF_DMA_IMCR_SRC31(x) (((x)&0x00000003)<<30)
40653 +#define MCF_DMA_IMCR_SRC16_FEC0RX (0x00000000)
40654 +#define MCF_DMA_IMCR_SRC17_FEC0TX (0x00000000)
40655 +#define MCF_DMA_IMCR_SRC18_FEC0RX (0x00000020)
40656 +#define MCF_DMA_IMCR_SRC19_FEC0TX (0x00000080)
40657 +#define MCF_DMA_IMCR_SRC20_FEC1RX (0x00000100)
40658 +#define MCF_DMA_IMCR_SRC21_DREQ1 (0x00000000)
40659 +#define MCF_DMA_IMCR_SRC21_FEC1TX (0x00000400)
40660 +#define MCF_DMA_IMCR_SRC22_FEC0RX (0x00001000)
40661 +#define MCF_DMA_IMCR_SRC23_FEC0TX (0x00004000)
40662 +#define MCF_DMA_IMCR_SRC24_CTM0 (0x00010000)
40663 +#define MCF_DMA_IMCR_SRC24_FEC1RX (0x00020000)
40664 +#define MCF_DMA_IMCR_SRC25_CTM1 (0x00040000)
40665 +#define MCF_DMA_IMCR_SRC25_FEC1TX (0x00080000)
40666 +#define MCF_DMA_IMCR_SRC26_USBEP4 (0x00000000)
40667 +#define MCF_DMA_IMCR_SRC26_CTM2 (0x00200000)
40668 +#define MCF_DMA_IMCR_SRC27_USBEP5 (0x00000000)
40669 +#define MCF_DMA_IMCR_SRC27_CTM3 (0x00800000)
40670 +#define MCF_DMA_IMCR_SRC28_USBEP6 (0x00000000)
40671 +#define MCF_DMA_IMCR_SRC28_CTM4 (0x01000000)
40672 +#define MCF_DMA_IMCR_SRC28_DREQ1 (0x02000000)
40673 +#define MCF_DMA_IMCR_SRC28_PSC2RX (0x03000000)
40674 +#define MCF_DMA_IMCR_SRC29_DREQ1 (0x04000000)
40675 +#define MCF_DMA_IMCR_SRC29_CTM5 (0x08000000)
40676 +#define MCF_DMA_IMCR_SRC29_PSC2TX (0x0C000000)
40677 +#define MCF_DMA_IMCR_SRC30_FEC1RX (0x00000000)
40678 +#define MCF_DMA_IMCR_SRC30_CTM6 (0x10000000)
40679 +#define MCF_DMA_IMCR_SRC30_PSC3RX (0x30000000)
40680 +#define MCF_DMA_IMCR_SRC31_FEC1TX (0x00000000)
40681 +#define MCF_DMA_IMCR_SRC31_CTM7 (0x80000000)
40682 +#define MCF_DMA_IMCR_SRC31_PSC3TX (0xC0000000)
40683 +
40684 +#endif /* __MCF548X_DMA_H__ */
40685 --- /dev/null
40686 +++ b/include/asm-m68k/m5485dspi.h
40687 @@ -0,0 +1,144 @@
40688 +/*
40689 + * File: mcf548x_dspi.h
40690 + * Purpose: Register and bit definitions for the MCF548X
40691 + *
40692 + * Notes:
40693 + *
40694 + */
40695 +
40696 +#ifndef _M5485DSPI_H_
40697 +#define _M5485DSPI_H_
40698 +
40699 +/*
40700 + *
40701 + * DMA Serial Peripheral Interface (DSPI)
40702 + *
40703 + */
40704 +
40705 +/* Register read/write macros */
40706 +#define MCF_DSPI_DMCR MCF_REG32(0x008A00)
40707 +#define MCF_DSPI_DTCR MCF_REG32(0x008A08)
40708 +#define MCF_DSPI_DCTAR0 MCF_REG32(0x008A0C)
40709 +#define MCF_DSPI_DCTAR1 MCF_REG32(0x008A10)
40710 +#define MCF_DSPI_DCTAR2 MCF_REG32(0x008A14)
40711 +#define MCF_DSPI_DCTAR3 MCF_REG32(0x008A18)
40712 +#define MCF_DSPI_DCTAR4 MCF_REG32(0x008A1C)
40713 +#define MCF_DSPI_DCTAR5 MCF_REG32(0x008A20)
40714 +#define MCF_DSPI_DCTAR6 MCF_REG32(0x008A24)
40715 +#define MCF_DSPI_DCTAR7 MCF_REG32(0x008A28)
40716 +#define MCF_DSPI_DCTARn(x) MCF_REG32(0x008A0C+(x*4))
40717 +#define MCF_DSPI_DSR MCF_REG32(0x008A2C)
40718 +#define MCF_DSPI_DRSER MCF_REG32(0x008A30)
40719 +#define MCF_DSPI_DTFR MCF_REG32(0x008A34)
40720 +#define MCF_DSPI_DRFR MCF_REG32(0x008A38)
40721 +#define MCF_DSPI_DTFDR0 MCF_REG32(0x008A3C)
40722 +#define MCF_DSPI_DTFDR1 MCF_REG32(0x008A40)
40723 +#define MCF_DSPI_DTFDR2 MCF_REG32(0x008A44)
40724 +#define MCF_DSPI_DTFDR3 MCF_REG32(0x008A48)
40725 +#define MCF_DSPI_DTFDRn(x) MCF_REG32(0x008A3C+(x*4))
40726 +#define MCF_DSPI_DRFDR0 MCF_REG32(0x008A7C)
40727 +#define MCF_DSPI_DRFDR1 MCF_REG32(0x008A80)
40728 +#define MCF_DSPI_DRFDR2 MCF_REG32(0x008A84)
40729 +#define MCF_DSPI_DRFDR3 MCF_REG32(0x008A88)
40730 +#define MCF_DSPI_DRFDRn(x) MCF_REG32(0x008A7C+(x*4))
40731 +
40732 +/* Bit definitions and macros for MCF_DSPI_DMCR */
40733 +#define MCF_DSPI_DMCR_HALT (0x00000001)
40734 +#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8)
40735 +#define MCF_DSPI_DMCR_CRXF (0x00000400)
40736 +#define MCF_DSPI_DMCR_CTXF (0x00000800)
40737 +#define MCF_DSPI_DMCR_DRXF (0x00001000)
40738 +#define MCF_DSPI_DMCR_DTXF (0x00002000)
40739 +#define MCF_DSPI_DMCR_CSIS0 (0x00010000)
40740 +#define MCF_DSPI_DMCR_CSIS2 (0x00040000)
40741 +#define MCF_DSPI_DMCR_CSIS3 (0x00080000)
40742 +#define MCF_DSPI_DMCR_CSIS5 (0x00200000)
40743 +#define MCF_DSPI_DMCR_ROOE (0x01000000)
40744 +#define MCF_DSPI_DMCR_PCSSE (0x02000000)
40745 +#define MCF_DSPI_DMCR_MTFE (0x04000000)
40746 +#define MCF_DSPI_DMCR_FRZ (0x08000000)
40747 +#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28)
40748 +#define MCF_DSPI_DMCR_CSCK (0x40000000)
40749 +#define MCF_DSPI_DMCR_MSTR (0x80000000)
40750 +
40751 +/* Bit definitions and macros for MCF_DSPI_DTCR */
40752 +#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16)
40753 +
40754 +/* Bit definitions and macros for MCF_DSPI_DCTARn */
40755 +#define MCF_DSPI_DCTAR_BR(x) (((x)&0x0000000F)<<0)
40756 +#define MCF_DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4)
40757 +#define MCF_DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8)
40758 +#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12)
40759 +#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16)
40760 +#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18)
40761 +#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20)
40762 +#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22)
40763 +#define MCF_DSPI_DCTAR_LSBFE (0x01000000)
40764 +#define MCF_DSPI_DCTAR_CPHA (0x02000000)
40765 +#define MCF_DSPI_DCTAR_CPOL (0x04000000)
40766 +/* #define MCF_DSPI_DCTAR_TRSZ(x) (((x)&0x0000000F)<<27) */
40767 +#define MCF_DSPI_DCTAR_FMSZ(x) (((x)&0x0000000F)<<27)
40768 +#define MCF_DSPI_DCTAR_PCSSCK_1CLK (0x00000000)
40769 +#define MCF_DSPI_DCTAR_PCSSCK_3CLK (0x00400000)
40770 +#define MCF_DSPI_DCTAR_PCSSCK_5CLK (0x00800000)
40771 +#define MCF_DSPI_DCTAR_PCSSCK_7CLK (0x00A00000)
40772 +#define MCF_DSPI_DCTAR_PASC_1CLK (0x00000000)
40773 +#define MCF_DSPI_DCTAR_PASC_3CLK (0x00100000)
40774 +#define MCF_DSPI_DCTAR_PASC_5CLK (0x00200000)
40775 +#define MCF_DSPI_DCTAR_PASC_7CLK (0x00300000)
40776 +#define MCF_DSPI_DCTAR_PDT_1CLK (0x00000000)
40777 +#define MCF_DSPI_DCTAR_PDT_3CLK (0x00040000)
40778 +#define MCF_DSPI_DCTAR_PDT_5CLK (0x00080000)
40779 +#define MCF_DSPI_DCTAR_PDT_7CLK (0x000A0000)
40780 +#define MCF_DSPI_DCTAR_PBR_1CLK (0x00000000)
40781 +#define MCF_DSPI_DCTAR_PBR_3CLK (0x00010000)
40782 +#define MCF_DSPI_DCTAR_PBR_5CLK (0x00020000)
40783 +#define MCF_DSPI_DCTAR_PBR_7CLK (0x00030000)
40784 +
40785 +/* Bit definitions and macros for MCF_DSPI_DSR */
40786 +#define MCF_DSPI_DSR_RXPTR(x) (((x)&0x0000000F)<<0)
40787 +#define MCF_DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4)
40788 +#define MCF_DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8)
40789 +#define MCF_DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12)
40790 +#define MCF_DSPI_DSR_RFDF (0x00020000)
40791 +#define MCF_DSPI_DSR_RFOF (0x00080000)
40792 +#define MCF_DSPI_DSR_TFFF (0x02000000)
40793 +#define MCF_DSPI_DSR_TFUF (0x08000000)
40794 +#define MCF_DSPI_DSR_EOQF (0x10000000)
40795 +#define MCF_DSPI_DSR_TXRXS (0x40000000)
40796 +#define MCF_DSPI_DSR_TCF (0x80000000)
40797 +
40798 +/* Bit definitions and macros for MCF_DSPI_DRSER */
40799 +#define MCF_DSPI_DRSER_RFDFS (0x00010000)
40800 +#define MCF_DSPI_DRSER_RFDFE (0x00020000)
40801 +#define MCF_DSPI_DRSER_RFOFE (0x00080000)
40802 +#define MCF_DSPI_DRSER_TFFFS (0x01000000)
40803 +#define MCF_DSPI_DRSER_TFFFE (0x02000000)
40804 +#define MCF_DSPI_DRSER_TFUFE (0x08000000)
40805 +#define MCF_DSPI_DRSER_EOQFE (0x10000000)
40806 +#define MCF_DSPI_DRSER_TCFE (0x80000000)
40807 +
40808 +/* Bit definitions and macros for MCF_DSPI_DTFR */
40809 +#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)<<0)
40810 +#define MCF_DSPI_DTFR_CS0 (0x00010000)
40811 +#define MCF_DSPI_DTFR_CS2 (0x00040000)
40812 +#define MCF_DSPI_DTFR_CS3 (0x00080000)
40813 +#define MCF_DSPI_DTFR_CS5 (0x00200000)
40814 +#define MCF_DSPI_DTFR_CTCNT (0x04000000)
40815 +#define MCF_DSPI_DTFR_EOQ (0x08000000)
40816 +#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28)
40817 +#define MCF_DSPI_DTFR_CONT (0x80000000)
40818 +
40819 +/* Bit definitions and macros for MCF_DSPI_DRFR */
40820 +#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)<<0)
40821 +
40822 +/* Bit definitions and macros for MCF_DSPI_DTFDRn */
40823 +#define MCF_DSPI_DTFDRn_TXDATA(x) (((x)&0x0000FFFF)<<0)
40824 +#define MCF_DSPI_DTFDRn_TXCMD(x) (((x)&0x0000FFFF)<<16)
40825 +
40826 +/* Bit definitions and macros for MCF_DSPI_DRFDRn */
40827 +#define MCF_DSPI_DRFDRn_RXDATA(x) (((x)&0x0000FFFF)<<0)
40828 +
40829 +/********************************************************************/
40830 +
40831 +#endif /* _M5485DSPI_H_ */
40832 --- /dev/null
40833 +++ b/include/asm-m68k/m5485gpio.h
40834 @@ -0,0 +1,694 @@
40835 +/*
40836 + * File: mcf548x_gpio.h
40837 + * Purpose: Register and bit definitions for the MCF548X
40838 + *
40839 + * Notes:
40840 + *
40841 + */
40842 +
40843 +#ifndef _M5485GPIO_H_
40844 +#define _M5485GPIO_H_
40845 +
40846 +/*********************************************************************
40847 +*
40848 +* General Purpose I/O (GPIO)
40849 +*
40850 +*********************************************************************/
40851 +
40852 +/* Register read/write macros */
40853 +#define MCF_GPIO_PODR_FBCTL MCF_REG08(0x000A00)
40854 +#define MCF_GPIO_PODR_FBCS MCF_REG08(0x000A01)
40855 +#define MCF_GPIO_PODR_DMA MCF_REG08(0x000A02)
40856 +#define MCF_GPIO_PODR_FEC0H MCF_REG08(0x000A04)
40857 +#define MCF_GPIO_PODR_FEC0L MCF_REG08(0x000A05)
40858 +#define MCF_GPIO_PODR_FEC1H MCF_REG08(0x000A06)
40859 +#define MCF_GPIO_PODR_FEC1L MCF_REG08(0x000A07)
40860 +#define MCF_GPIO_PODR_FECI2C MCF_REG08(0x000A08)
40861 +#define MCF_GPIO_PODR_PCIBG MCF_REG08(0x000A09)
40862 +#define MCF_GPIO_PODR_PCIBR MCF_REG08(0x000A0A)
40863 +#define MCF_GPIO_PODR_PSC3PSC2 MCF_REG08(0x000A0C)
40864 +#define MCF_GPIO_PODR_PSC1PSC0 MCF_REG08(0x000A0D)
40865 +#define MCF_GPIO_PODR_DSPI MCF_REG08(0x000A0E)
40866 +#define MCF_GPIO_PDDR_FBCTL MCF_REG08(0x000A10)
40867 +#define MCF_GPIO_PDDR_FBCS MCF_REG08(0x000A11)
40868 +#define MCF_GPIO_PDDR_DMA MCF_REG08(0x000A12)
40869 +#define MCF_GPIO_PDDR_FEC0H MCF_REG08(0x000A14)
40870 +#define MCF_GPIO_PDDR_FEC0L MCF_REG08(0x000A15)
40871 +#define MCF_GPIO_PDDR_FEC1H MCF_REG08(0x000A16)
40872 +#define MCF_GPIO_PDDR_FEC1L MCF_REG08(0x000A17)
40873 +#define MCF_GPIO_PDDR_FECI2C MCF_REG08(0x000A18)
40874 +#define MCF_GPIO_PDDR_PCIBG MCF_REG08(0x000A19)
40875 +#define MCF_GPIO_PDDR_PCIBR MCF_REG08(0x000A1A)
40876 +#define MCF_GPIO_PDDR_PSC3PSC2 MCF_REG08(0x000A1C)
40877 +#define MCF_GPIO_PDDR_PSC1PSC0 MCF_REG08(0x000A1D)
40878 +#define MCF_GPIO_PDDR_DSPI MCF_REG08(0x000A1E)
40879 +#define MCF_GPIO_PPDSDR_FBCTL MCF_REG08(0x000A20)
40880 +#define MCF_GPIO_PPDSDR_FBCS MCF_REG08(0x000A21)
40881 +#define MCF_GPIO_PPDSDR_DMA MCF_REG08(0x000A22)
40882 +#define MCF_GPIO_PPDSDR_FEC0H MCF_REG08(0x000A24)
40883 +#define MCF_GPIO_PPDSDR_FEC0L MCF_REG08(0x000A25)
40884 +#define MCF_GPIO_PPDSDR_FEC1H MCF_REG08(0x000A26)
40885 +#define MCF_GPIO_PPDSDR_FEC1L MCF_REG08(0x000A27)
40886 +#define MCF_GPIO_PPDSDR_FECI2C MCF_REG08(0x000A28)
40887 +#define MCF_GPIO_PPDSDR_PCIBG MCF_REG08(0x000A29)
40888 +#define MCF_GPIO_PPDSDR_PCIBR MCF_REG08(0x000A2A)
40889 +#define MCF_GPIO_PPDSDR_PSC3PSC2 MCF_REG08(0x000A2C)
40890 +#define MCF_GPIO_PPDSDR_PSC1PSC0 MCF_REG08(0x000A2D)
40891 +#define MCF_GPIO_PPDSDR_DSPI MCF_REG08(0x000A2E)
40892 +#define MCF_GPIO_PCLRR_FBCTL MCF_REG08(0x000A30)
40893 +#define MCF_GPIO_PCLRR_FBCS MCF_REG08(0x000A31)
40894 +#define MCF_GPIO_PCLRR_DMA MCF_REG08(0x000A32)
40895 +#define MCF_GPIO_PCLRR_FEC0H MCF_REG08(0x000A34)
40896 +#define MCF_GPIO_PCLRR_FEC0L MCF_REG08(0x000A35)
40897 +#define MCF_GPIO_PCLRR_FEC1H MCF_REG08(0x000A36)
40898 +#define MCF_GPIO_PCLRR_FEC1L MCF_REG08(0x000A37)
40899 +#define MCF_GPIO_PCLRR_FECI2C MCF_REG08(0x000A38)
40900 +#define MCF_GPIO_PCLRR_PCIBG MCF_REG08(0x000A39)
40901 +#define MCF_GPIO_PCLRR_PCIBR MCF_REG08(0x000A3A)
40902 +#define MCF_GPIO_PCLRR_PSC3PSC2 MCF_REG08(0x000A3C)
40903 +#define MCF_GPIO_PCLRR_PSC1PSC0 MCF_REG08(0x000A3D)
40904 +#define MCF_GPIO_PCLRR_DSPI MCF_REG08(0x000A3E)
40905 +#define MCF_GPIO_PAR_FBCTL MCF_REG16(0x000A40)
40906 +#define MCF_GPIO_PAR_FBCS MCF_REG08(0x000A42)
40907 +#define MCF_GPIO_PAR_DMA MCF_REG08(0x000A43)
40908 +#define MCF_GPIO_PAR_FECI2CIRQ MCF_REG16(0x000A44)
40909 +#define MCF_GPIO_PAR_PCIBG MCF_REG16(0x000A48)
40910 +#define MCF_GPIO_PAR_PCIBR MCF_REG16(0x000A4A)
40911 +#define MCF_GPIO_PAR_PSC3 MCF_REG08(0x000A4C)
40912 +#define MCF_GPIO_PAR_PSC2 MCF_REG08(0x000A4D)
40913 +#define MCF_GPIO_PAR_PSC1 MCF_REG08(0x000A4E)
40914 +#define MCF_GPIO_PAR_PSC0 MCF_REG08(0x000A4F)
40915 +#define MCF_GPIO_PAR_DSPI MCF_REG16(0x000A50)
40916 +#define MCF_GPIO_PAR_TIMER MCF_REG08(0x000A52)
40917 +
40918 +/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */
40919 +#define MCF_GPIO_PODR_FBCTL_PODRFBCTL0 (0x01)
40920 +#define MCF_GPIO_PODR_FBCTL_PODRFBCTL1 (0x02)
40921 +#define MCF_GPIO_PODR_FBCTL_PODRFBCTL2 (0x04)
40922 +#define MCF_GPIO_PODR_FBCTL_PODRFBCTL3 (0x08)
40923 +#define MCF_GPIO_PODR_FBCTL_PODRFBCTL4 (0x10)
40924 +#define MCF_GPIO_PODR_FBCTL_PODRFBCTL5 (0x20)
40925 +#define MCF_GPIO_PODR_FBCTL_PODRFBCTL6 (0x40)
40926 +#define MCF_GPIO_PODR_FBCTL_PODRFBCTL7 (0x80)
40927 +
40928 +/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */
40929 +#define MCF_GPIO_PODR_FBCS_PODRFBCS1 (0x02)
40930 +#define MCF_GPIO_PODR_FBCS_PODRFBCS2 (0x04)
40931 +#define MCF_GPIO_PODR_FBCS_PODRFBCS3 (0x08)
40932 +#define MCF_GPIO_PODR_FBCS_PODRFBCS4 (0x10)
40933 +#define MCF_GPIO_PODR_FBCS_PODRFBCS5 (0x20)
40934 +
40935 +/* Bit definitions and macros for MCF_GPIO_PODR_DMA */
40936 +#define MCF_GPIO_PODR_DMA_PODRDMA0 (0x01)
40937 +#define MCF_GPIO_PODR_DMA_PODRDMA1 (0x02)
40938 +#define MCF_GPIO_PODR_DMA_PODRDMA2 (0x04)
40939 +#define MCF_GPIO_PODR_DMA_PODRDMA3 (0x08)
40940 +
40941 +/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */
40942 +#define MCF_GPIO_PODR_FEC0H_PODRFEC0H0 (0x01)
40943 +#define MCF_GPIO_PODR_FEC0H_PODRFEC0H1 (0x02)
40944 +#define MCF_GPIO_PODR_FEC0H_PODRFEC0H2 (0x04)
40945 +#define MCF_GPIO_PODR_FEC0H_PODRFEC0H3 (0x08)
40946 +#define MCF_GPIO_PODR_FEC0H_PODRFEC0H4 (0x10)
40947 +#define MCF_GPIO_PODR_FEC0H_PODRFEC0H5 (0x20)
40948 +#define MCF_GPIO_PODR_FEC0H_PODRFEC0H6 (0x40)
40949 +#define MCF_GPIO_PODR_FEC0H_PODRFEC0H7 (0x80)
40950 +
40951 +/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */
40952 +#define MCF_GPIO_PODR_FEC0L_PODRFEC0L0 (0x01)
40953 +#define MCF_GPIO_PODR_FEC0L_PODRFEC0L1 (0x02)
40954 +#define MCF_GPIO_PODR_FEC0L_PODRFEC0L2 (0x04)
40955 +#define MCF_GPIO_PODR_FEC0L_PODRFEC0L3 (0x08)
40956 +#define MCF_GPIO_PODR_FEC0L_PODRFEC0L4 (0x10)
40957 +#define MCF_GPIO_PODR_FEC0L_PODRFEC0L5 (0x20)
40958 +#define MCF_GPIO_PODR_FEC0L_PODRFEC0L6 (0x40)
40959 +#define MCF_GPIO_PODR_FEC0L_PODRFEC0L7 (0x80)
40960 +
40961 +/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */
40962 +#define MCF_GPIO_PODR_FEC1H_PODRFEC1H0 (0x01)
40963 +#define MCF_GPIO_PODR_FEC1H_PODRFEC1H1 (0x02)
40964 +#define MCF_GPIO_PODR_FEC1H_PODRFEC1H2 (0x04)
40965 +#define MCF_GPIO_PODR_FEC1H_PODRFEC1H3 (0x08)
40966 +#define MCF_GPIO_PODR_FEC1H_PODRFEC1H4 (0x10)
40967 +#define MCF_GPIO_PODR_FEC1H_PODRFEC1H5 (0x20)
40968 +#define MCF_GPIO_PODR_FEC1H_PODRFEC1H6 (0x40)
40969 +#define MCF_GPIO_PODR_FEC1H_PODRFEC1H7 (0x80)
40970 +
40971 +/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */
40972 +#define MCF_GPIO_PODR_FEC1L_PODRFEC1L0 (0x01)
40973 +#define MCF_GPIO_PODR_FEC1L_PODRFEC1L1 (0x02)
40974 +#define MCF_GPIO_PODR_FEC1L_PODRFEC1L2 (0x04)
40975 +#define MCF_GPIO_PODR_FEC1L_PODRFEC1L3 (0x08)
40976 +#define MCF_GPIO_PODR_FEC1L_PODRFEC1L4 (0x10)
40977 +#define MCF_GPIO_PODR_FEC1L_PODRFEC1L5 (0x20)
40978 +#define MCF_GPIO_PODR_FEC1L_PODRFEC1L6 (0x40)
40979 +#define MCF_GPIO_PODR_FEC1L_PODRFEC1L7 (0x80)
40980 +
40981 +/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
40982 +#define MCF_GPIO_PODR_FECI2C_PODRFECI2C0 (0x01)
40983 +#define MCF_GPIO_PODR_FECI2C_PODRFECI2C1 (0x02)
40984 +#define MCF_GPIO_PODR_FECI2C_PODRFECI2C2 (0x04)
40985 +#define MCF_GPIO_PODR_FECI2C_PODRFECI2C3 (0x08)
40986 +
40987 +/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */
40988 +#define MCF_GPIO_PODR_PCIBG_PODRPCIBG0 (0x01)
40989 +#define MCF_GPIO_PODR_PCIBG_PODRPCIBG1 (0x02)
40990 +#define MCF_GPIO_PODR_PCIBG_PODRPCIBG2 (0x04)
40991 +#define MCF_GPIO_PODR_PCIBG_PODRPCIBG3 (0x08)
40992 +#define MCF_GPIO_PODR_PCIBG_PODRPCIBG4 (0x10)
40993 +
40994 +/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */
40995 +#define MCF_GPIO_PODR_PCIBR_PODRPCIBR0 (0x01)
40996 +#define MCF_GPIO_PODR_PCIBR_PODRPCIBR1 (0x02)
40997 +#define MCF_GPIO_PODR_PCIBR_PODRPCIBR2 (0x04)
40998 +#define MCF_GPIO_PODR_PCIBR_PODRPCIBR3 (0x08)
40999 +#define MCF_GPIO_PODR_PCIBR_PODRPCIBR4 (0x10)
41000 +
41001 +/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC2 */
41002 +#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC20 (0x01)
41003 +#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC21 (0x02)
41004 +#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC22 (0x04)
41005 +#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC23 (0x08)
41006 +#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC24 (0x10)
41007 +#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC25 (0x20)
41008 +#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC26 (0x40)
41009 +#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC27 (0x80)
41010 +
41011 +/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC0 */
41012 +#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC00 (0x01)
41013 +#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC01 (0x02)
41014 +#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC02 (0x04)
41015 +#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC03 (0x08)
41016 +#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC04 (0x10)
41017 +#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC05 (0x20)
41018 +#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC06 (0x40)
41019 +#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC07 (0x80)
41020 +
41021 +/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */
41022 +#define MCF_GPIO_PODR_DSPI_PODRDSPI0 (0x01)
41023 +#define MCF_GPIO_PODR_DSPI_PODRDSPI1 (0x02)
41024 +#define MCF_GPIO_PODR_DSPI_PODRDSPI2 (0x04)
41025 +#define MCF_GPIO_PODR_DSPI_PODRDSPI3 (0x08)
41026 +#define MCF_GPIO_PODR_DSPI_PODRDSPI4 (0x10)
41027 +#define MCF_GPIO_PODR_DSPI_PODRDSPI5 (0x20)
41028 +#define MCF_GPIO_PODR_DSPI_PODRDSPI6 (0x40)
41029 +
41030 +/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */
41031 +#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL0 (0x01)
41032 +#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL1 (0x02)
41033 +#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL2 (0x04)
41034 +#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL3 (0x08)
41035 +#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL4 (0x10)
41036 +#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL5 (0x20)
41037 +#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL6 (0x40)
41038 +#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL7 (0x80)
41039 +
41040 +/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */
41041 +#define MCF_GPIO_PDDR_FBCS_PDDRFBCS1 (0x02)
41042 +#define MCF_GPIO_PDDR_FBCS_PDDRFBCS2 (0x04)
41043 +#define MCF_GPIO_PDDR_FBCS_PDDRFBCS3 (0x08)
41044 +#define MCF_GPIO_PDDR_FBCS_PDDRFBCS4 (0x10)
41045 +#define MCF_GPIO_PDDR_FBCS_PDDRFBCS5 (0x20)
41046 +
41047 +/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */
41048 +#define MCF_GPIO_PDDR_DMA_PDDRDMA0 (0x01)
41049 +#define MCF_GPIO_PDDR_DMA_PDDRDMA1 (0x02)
41050 +#define MCF_GPIO_PDDR_DMA_PDDRDMA2 (0x04)
41051 +#define MCF_GPIO_PDDR_DMA_PDDRDMA3 (0x08)
41052 +
41053 +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */
41054 +#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H0 (0x01)
41055 +#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H1 (0x02)
41056 +#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H2 (0x04)
41057 +#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H3 (0x08)
41058 +#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H4 (0x10)
41059 +#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H5 (0x20)
41060 +#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H6 (0x40)
41061 +#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H7 (0x80)
41062 +
41063 +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */
41064 +#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L0 (0x01)
41065 +#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L1 (0x02)
41066 +#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L2 (0x04)
41067 +#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L3 (0x08)
41068 +#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L4 (0x10)
41069 +#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L5 (0x20)
41070 +#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L6 (0x40)
41071 +#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L7 (0x80)
41072 +
41073 +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */
41074 +#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H0 (0x01)
41075 +#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H1 (0x02)
41076 +#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H2 (0x04)
41077 +#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H3 (0x08)
41078 +#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H4 (0x10)
41079 +#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H5 (0x20)
41080 +#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H6 (0x40)
41081 +#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H7 (0x80)
41082 +
41083 +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */
41084 +#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L0 (0x01)
41085 +#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L1 (0x02)
41086 +#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L2 (0x04)
41087 +#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L3 (0x08)
41088 +#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L4 (0x10)
41089 +#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L5 (0x20)
41090 +#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L6 (0x40)
41091 +#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L7 (0x80)
41092 +
41093 +/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
41094 +#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C0 (0x01)
41095 +#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C1 (0x02)
41096 +#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C2 (0x04)
41097 +#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C3 (0x08)
41098 +
41099 +/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */
41100 +#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG0 (0x01)
41101 +#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG1 (0x02)
41102 +#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG2 (0x04)
41103 +#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG3 (0x08)
41104 +#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG4 (0x10)
41105 +
41106 +/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */
41107 +#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR0 (0x01)
41108 +#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR1 (0x02)
41109 +#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR2 (0x04)
41110 +#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR3 (0x08)
41111 +#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR4 (0x10)
41112 +
41113 +/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC2 */
41114 +#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC20 (0x01)
41115 +#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC21 (0x02)
41116 +#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC22 (0x04)
41117 +#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC23 (0x08)
41118 +#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC24 (0x10)
41119 +#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC25 (0x20)
41120 +#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC26 (0x40)
41121 +#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC27 (0x80)
41122 +
41123 +/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC0 */
41124 +#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC00 (0x01)
41125 +#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC01 (0x02)
41126 +#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC02 (0x04)
41127 +#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC03 (0x08)
41128 +#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC04 (0x10)
41129 +#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC05 (0x20)
41130 +#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC06 (0x40)
41131 +#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC07 (0x80)
41132 +
41133 +/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */
41134 +#define MCF_GPIO_PDDR_DSPI_PDDRDSPI0 (0x01)
41135 +#define MCF_GPIO_PDDR_DSPI_PDDRDSPI1 (0x02)
41136 +#define MCF_GPIO_PDDR_DSPI_PDDRDSPI2 (0x04)
41137 +#define MCF_GPIO_PDDR_DSPI_PDDRDSPI3 (0x08)
41138 +#define MCF_GPIO_PDDR_DSPI_PDDRDSPI4 (0x10)
41139 +#define MCF_GPIO_PDDR_DSPI_PDDRDSPI5 (0x20)
41140 +#define MCF_GPIO_PDDR_DSPI_PDDRDSPI6 (0x40)
41141 +
41142 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */
41143 +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL0 (0x01)
41144 +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL1 (0x02)
41145 +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL2 (0x04)
41146 +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL3 (0x08)
41147 +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL4 (0x10)
41148 +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL5 (0x20)
41149 +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL6 (0x40)
41150 +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL7 (0x80)
41151 +
41152 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */
41153 +#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS1 (0x02)
41154 +#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS2 (0x04)
41155 +#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS3 (0x08)
41156 +#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS4 (0x10)
41157 +#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS5 (0x20)
41158 +
41159 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */
41160 +#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA0 (0x01)
41161 +#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA1 (0x02)
41162 +#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA2 (0x04)
41163 +#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA3 (0x08)
41164 +
41165 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */
41166 +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H0 (0x01)
41167 +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H1 (0x02)
41168 +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H2 (0x04)
41169 +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H3 (0x08)
41170 +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H4 (0x10)
41171 +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H5 (0x20)
41172 +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H6 (0x40)
41173 +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H7 (0x80)
41174 +
41175 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */
41176 +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L0 (0x01)
41177 +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L1 (0x02)
41178 +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L2 (0x04)
41179 +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L3 (0x08)
41180 +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L4 (0x10)
41181 +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L5 (0x20)
41182 +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L6 (0x40)
41183 +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L7 (0x80)
41184 +
41185 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */
41186 +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H0 (0x01)
41187 +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H1 (0x02)
41188 +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H2 (0x04)
41189 +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H3 (0x08)
41190 +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H4 (0x10)
41191 +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H5 (0x20)
41192 +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H6 (0x40)
41193 +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H7 (0x80)
41194 +
41195 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */
41196 +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L0 (0x01)
41197 +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L1 (0x02)
41198 +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L2 (0x04)
41199 +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L3 (0x08)
41200 +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L4 (0x10)
41201 +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L5 (0x20)
41202 +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L6 (0x40)
41203 +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L7 (0x80)
41204 +
41205 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
41206 +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C0 (0x01)
41207 +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C1 (0x02)
41208 +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C2 (0x04)
41209 +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C3 (0x08)
41210 +
41211 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */
41212 +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG0 (0x01)
41213 +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG1 (0x02)
41214 +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG2 (0x04)
41215 +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG3 (0x08)
41216 +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG4 (0x10)
41217 +
41218 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */
41219 +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR0 (0x01)
41220 +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR1 (0x02)
41221 +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR2 (0x04)
41222 +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR3 (0x08)
41223 +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR4 (0x10)
41224 +
41225 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC2 */
41226 +#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC20 (0x01)
41227 +#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC21 (0x02)
41228 +#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC22 (0x04)
41229 +#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC23 (0x08)
41230 +#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDRPSC3PSC24 (0x10)
41231 +#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDRPSC3PSC25 (0x20)
41232 +#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC26 (0x40)
41233 +#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC27 (0x80)
41234 +
41235 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC0 */
41236 +#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC00 (0x01)
41237 +#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDRPSC1PSC01 (0x02)
41238 +#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC02 (0x04)
41239 +#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDRPSC1PSC03 (0x08)
41240 +#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC04 (0x10)
41241 +#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC05 (0x20)
41242 +#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC06 (0x40)
41243 +#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC07 (0x80)
41244 +
41245 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */
41246 +#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI0 (0x01)
41247 +#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI1 (0x02)
41248 +#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI2 (0x04)
41249 +#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI3 (0x08)
41250 +#define MCF_GPIO_PPDSDR_DSPI_PDDRDSPI4 (0x10)
41251 +#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI5 (0x20)
41252 +#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI6 (0x40)
41253 +
41254 +/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */
41255 +#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL0 (0x01)
41256 +#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL1 (0x02)
41257 +#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL2 (0x04)
41258 +#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL3 (0x08)
41259 +#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL4 (0x10)
41260 +#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL5 (0x20)
41261 +#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL6 (0x40)
41262 +#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL7 (0x80)
41263 +
41264 +/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */
41265 +#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS1 (0x02)
41266 +#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS2 (0x04)
41267 +#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS3 (0x08)
41268 +#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS4 (0x10)
41269 +#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS5 (0x20)
41270 +
41271 +/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */
41272 +#define MCF_GPIO_PCLRR_DMA_PCLRRDMA0 (0x01)
41273 +#define MCF_GPIO_PCLRR_DMA_PCLRRDMA1 (0x02)
41274 +#define MCF_GPIO_PCLRR_DMA_PCLRRDMA2 (0x04)
41275 +#define MCF_GPIO_PCLRR_DMA_PCLRRDMA3 (0x08)
41276 +
41277 +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */
41278 +#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H0 (0x01)
41279 +#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H1 (0x02)
41280 +#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H2 (0x04)
41281 +#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H3 (0x08)
41282 +#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H4 (0x10)
41283 +#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H5 (0x20)
41284 +#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H6 (0x40)
41285 +#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H7 (0x80)
41286 +
41287 +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */
41288 +#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L0 (0x01)
41289 +#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L1 (0x02)
41290 +#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L2 (0x04)
41291 +#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L3 (0x08)
41292 +#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L4 (0x10)
41293 +#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L5 (0x20)
41294 +#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L6 (0x40)
41295 +#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L7 (0x80)
41296 +
41297 +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */
41298 +#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H0 (0x01)
41299 +#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H1 (0x02)
41300 +#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H2 (0x04)
41301 +#define MCF_GPIO_PCLRR_FEC1H_PODRFEC1H3 (0x08)
41302 +#define MCF_GPIO_PCLRR_FEC1H_PODRFEC1H4 (0x10)
41303 +#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H5 (0x20)
41304 +#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H6 (0x40)
41305 +#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H7 (0x80)
41306 +
41307 +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */
41308 +#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L0 (0x01)
41309 +#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L1 (0x02)
41310 +#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L2 (0x04)
41311 +#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L3 (0x08)
41312 +#define MCF_GPIO_PCLRR_FEC1L_PODRFEC1L4 (0x10)
41313 +#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L5 (0x20)
41314 +#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L6 (0x40)
41315 +#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L7 (0x80)
41316 +
41317 +/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
41318 +#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C0 (0x01)
41319 +#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C1 (0x02)
41320 +#define MCF_GPIO_PCLRR_FECI2C_PODRFECI2C2 (0x04)
41321 +#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C3 (0x08)
41322 +
41323 +/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */
41324 +#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG0 (0x01)
41325 +#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG1 (0x02)
41326 +#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG2 (0x04)
41327 +#define MCF_GPIO_PCLRR_PCIBG_PCLRRPCIBG3 (0x08)
41328 +#define MCF_GPIO_PCLRR_PCIBG_PCLRRPCIBG4 (0x10)
41329 +
41330 +/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */
41331 +#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR0 (0x01)
41332 +#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR1 (0x02)
41333 +#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR2 (0x04)
41334 +#define MCF_GPIO_PCLRR_PCIBR_PODRPCIBR3 (0x08)
41335 +#define MCF_GPIO_PCLRR_PCIBR_PODRPCIBR4 (0x10)
41336 +
41337 +/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC2 */
41338 +#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC20 (0x01)
41339 +#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC21 (0x02)
41340 +#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC22 (0x04)
41341 +#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC23 (0x08)
41342 +#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC24 (0x10)
41343 +#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC25 (0x20)
41344 +#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC26 (0x40)
41345 +#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC27 (0x80)
41346 +
41347 +/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC0 */
41348 +#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC00 (0x01)
41349 +#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC01 (0x02)
41350 +#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC02 (0x04)
41351 +#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC03 (0x08)
41352 +#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC04 (0x10)
41353 +#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC05 (0x20)
41354 +#define MCF_GPIO_PCLRR_PSC1PSC0_PODRPSC1PSC06 (0x40)
41355 +#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC07 (0x80)
41356 +
41357 +/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */
41358 +#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI0 (0x01)
41359 +#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI1 (0x02)
41360 +#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI2 (0x04)
41361 +#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI3 (0x08)
41362 +#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI4 (0x10)
41363 +#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI5 (0x20)
41364 +#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI6 (0x40)
41365 +
41366 +/* Bit definitions and macros for MCF_GPIO_PAR_FBCTL */
41367 +#define MCF_GPIO_PAR_FBCTL_PAR_TS(x) (((x)&0x0003)<<0)
41368 +#define MCF_GPIO_PAR_FBCTL_PAR_TA (0x0004)
41369 +#define MCF_GPIO_PAR_FBCTL_PAR_RWB (0x0010)
41370 +#define MCF_GPIO_PAR_FBCTL_PAR_OE (0x0040)
41371 +#define MCF_GPIO_PAR_FBCTL_PAR_BWE0 (0x0100)
41372 +#define MCF_GPIO_PAR_FBCTL_PAR_BWE1 (0x0400)
41373 +#define MCF_GPIO_PAR_FBCTL_PAR_BWE2 (0x1000)
41374 +#define MCF_GPIO_PAR_FBCTL_PAR_BWE3 (0x4000)
41375 +#define MCF_GPIO_PAR_FBCTL_PAR_TS_GPIO (0)
41376 +#define MCF_GPIO_PAR_FBCTL_PAR_TS_TBST (2)
41377 +#define MCF_GPIO_PAR_FBCTL_PAR_TS_TS (3)
41378 +
41379 +/* Bit definitions and macros for MCF_GPIO_PAR_FBCS */
41380 +#define MCF_GPIO_PAR_FBCS_PAR_CS1 (0x02)
41381 +#define MCF_GPIO_PAR_FBCS_PAR_CS2 (0x04)
41382 +#define MCF_GPIO_PAR_FBCS_PAR_CS3 (0x08)
41383 +#define MCF_GPIO_PAR_FBCS_PAR_CS4 (0x10)
41384 +#define MCF_GPIO_PAR_FBCS_PAR_CS5 (0x20)
41385 +
41386 +/* Bit definitions and macros for MCF_GPIO_PAR_DMA */
41387 +#define MCF_GPIO_PAR_DMA_PAR_DREQ0(x) (((x)&0x03)<<0)
41388 +#define MCF_GPIO_PAR_DMA_PAR_DREQ1(x) (((x)&0x03)<<2)
41389 +#define MCF_GPIO_PAR_DMA_PAR_DACK0(x) (((x)&0x03)<<4)
41390 +#define MCF_GPIO_PAR_DMA_PAR_DACK1(x) (((x)&0x03)<<6)
41391 +#define MCF_GPIO_PAR_DMA_PAR_DACKx_GPIO (0)
41392 +#define MCF_GPIO_PAR_DMA_PAR_DACKx_TOUT (2)
41393 +#define MCF_GPIO_PAR_DMA_PAR_DACKx_DACK (3)
41394 +#define MCF_GPIO_PAR_DMA_PAR_DREQx_GPIO (0)
41395 +#define MCF_GPIO_PAR_DMA_PAR_DREQx_TIN (2)
41396 +#define MCF_GPIO_PAR_DMA_PAR_DREQx_DREQ (3)
41397 +
41398 +/* Bit definitions and macros for MCF_GPIO_PAR_FECI2CIRQ */
41399 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ5 (0x0001)
41400 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ6 (0x0002)
41401 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SCL (0x0004)
41402 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SDA (0x0008)
41403 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x0003)<<6)
41404 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x0003)<<8)
41405 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII (0x0400)
41406 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E17 (0x0800)
41407 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC (0x1000)
41408 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000)
41409 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII (0x4000)
41410 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E07 (0x8000)
41411 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_CANRX (0x0000)
41412 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x0200)
41413 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO (0x0300)
41414 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_CANTX (0x0000)
41415 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x0080)
41416 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC (0x00C0)
41417 +
41418 +/* Bit definitions and macros for MCF_GPIO_PAR_PCIBG */
41419 +#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x0003)<<0)
41420 +#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x0003)<<2)
41421 +#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x0003)<<4)
41422 +#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x0003)<<6)
41423 +#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x0003)<<8)
41424 +
41425 +/* Bit definitions and macros for MCF_GPIO_PAR_PCIBR */
41426 +#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG0(x) (((x)&0x0003)<<0)
41427 +#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG1(x) (((x)&0x0003)<<2)
41428 +#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG2(x) (((x)&0x0003)<<4)
41429 +#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG3(x) (((x)&0x0003)<<6)
41430 +#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x0003)<<8)
41431 +
41432 +/* Bit definitions and macros for MCF_GPIO_PAR_PSC3 */
41433 +#define MCF_GPIO_PAR_PSC3_PAR_TXD3 (0x04)
41434 +#define MCF_GPIO_PAR_PSC3_PAR_RXD3 (0x08)
41435 +#define MCF_GPIO_PAR_PSC3_PAR_RTS3(x) (((x)&0x03)<<4)
41436 +#define MCF_GPIO_PAR_PSC3_PAR_CTS3(x) (((x)&0x03)<<6)
41437 +#define MCF_GPIO_PAR_PSC3_PAR_CTS3_GPIO (0x00)
41438 +#define MCF_GPIO_PAR_PSC3_PAR_CTS3_BCLK (0x80)
41439 +#define MCF_GPIO_PAR_PSC3_PAR_CTS3_CTS (0xC0)
41440 +#define MCF_GPIO_PAR_PSC3_PAR_RTS3_GPIO (0x00)
41441 +#define MCF_GPIO_PAR_PSC3_PAR_RTS3_FSYNC (0x20)
41442 +#define MCF_GPIO_PAR_PSC3_PAR_RTS3_RTS (0x30)
41443 +#define MCF_GPIO_PAR_PSC3_PAR_CTS2_CANRX (0x40)
41444 +
41445 +/* Bit definitions and macros for MCF_GPIO_PAR_PSC2 */
41446 +#define MCF_GPIO_PAR_PSC2_PAR_TXD2 (0x04)
41447 +#define MCF_GPIO_PAR_PSC2_PAR_RXD2 (0x08)
41448 +#define MCF_GPIO_PAR_PSC2_PAR_RTS2(x) (((x)&0x03)<<4)
41449 +#define MCF_GPIO_PAR_PSC2_PAR_CTS2(x) (((x)&0x03)<<6)
41450 +#define MCF_GPIO_PAR_PSC2_PAR_CTS2_GPIO (0x00)
41451 +#define MCF_GPIO_PAR_PSC2_PAR_CTS2_BCLK (0x80)
41452 +#define MCF_GPIO_PAR_PSC2_PAR_CTS2_CTS (0xC0)
41453 +#define MCF_GPIO_PAR_PSC2_PAR_RTS2_GPIO (0x00)
41454 +#define MCF_GPIO_PAR_PSC2_PAR_RTS2_CANTX (0x10)
41455 +#define MCF_GPIO_PAR_PSC2_PAR_RTS2_FSYNC (0x20)
41456 +#define MCF_GPIO_PAR_PSC2_PAR_RTS2_RTS (0x30)
41457 +#define MCF_GPIO_PAR_PSC2_PAR_RTS2_CANRX (0x40)
41458 +
41459 +/* Bit definitions and macros for MCF_GPIO_PAR_PSC1 */
41460 +#define MCF_GPIO_PAR_PSC1_PAR_TXD1 (0x04)
41461 +#define MCF_GPIO_PAR_PSC1_PAR_RXD1 (0x08)
41462 +#define MCF_GPIO_PAR_PSC1_PAR_RTS1(x) (((x)&0x03)<<4)
41463 +#define MCF_GPIO_PAR_PSC1_PAR_CTS1(x) (((x)&0x03)<<6)
41464 +#define MCF_GPIO_PAR_PSC1_PAR_CTS1_GPIO (0x00)
41465 +#define MCF_GPIO_PAR_PSC1_PAR_CTS1_BCLK (0x80)
41466 +#define MCF_GPIO_PAR_PSC1_PAR_CTS1_CTS (0xC0)
41467 +#define MCF_GPIO_PAR_PSC1_PAR_RTS1_GPIO (0x00)
41468 +#define MCF_GPIO_PAR_PSC1_PAR_RTS1_FSYNC (0x20)
41469 +#define MCF_GPIO_PAR_PSC1_PAR_RTS1_RTS (0x30)
41470 +
41471 +/* Bit definitions and macros for MCF_GPIO_PAR_PSC0 */
41472 +#define MCF_GPIO_PAR_PSC0_PAR_TXD0 (0x04)
41473 +#define MCF_GPIO_PAR_PSC0_PAR_RXD0 (0x08)
41474 +#define MCF_GPIO_PAR_PSC0_PAR_RTS0(x) (((x)&0x03)<<4)
41475 +#define MCF_GPIO_PAR_PSC0_PAR_CTS0(x) (((x)&0x03)<<6)
41476 +#define MCF_GPIO_PAR_PSC0_PAR_CTS0_GPIO (0x00)
41477 +#define MCF_GPIO_PAR_PSC0_PAR_CTS0_BCLK (0x80)
41478 +#define MCF_GPIO_PAR_PSC0_PAR_CTS0_CTS (0xC0)
41479 +#define MCF_GPIO_PAR_PSC0_PAR_RTS0_GPIO (0x00)
41480 +#define MCF_GPIO_PAR_PSC0_PAR_RTS0_FSYNC (0x20)
41481 +#define MCF_GPIO_PAR_PSC0_PAR_RTS0_RTS (0x30)
41482 +
41483 +/* Bit definitions and macros for MCF_GPIO_PAR_DSPI */
41484 +#define MCF_GPIO_PAR_DSPI_PAR_SOUT(x) (((x)&0x0003)<<0)
41485 +#define MCF_GPIO_PAR_DSPI_PAR_SIN(x) (((x)&0x0003)<<2)
41486 +#define MCF_GPIO_PAR_DSPI_PAR_SCK(x) (((x)&0x0003)<<4)
41487 +#define MCF_GPIO_PAR_DSPI_PAR_CS0(x) (((x)&0x0003)<<6)
41488 +#define MCF_GPIO_PAR_DSPI_PAR_CS2(x) (((x)&0x0003)<<8)
41489 +#define MCF_GPIO_PAR_DSPI_PAR_CS3(x) (((x)&0x0003)<<10)
41490 +#define MCF_GPIO_PAR_DSPI_PAR_CS5 (0x1000)
41491 +#define MCF_GPIO_PAR_DSPI_PAR_CS3_GPIO (0x0000)
41492 +#define MCF_GPIO_PAR_DSPI_PAR_CS3_CANTX (0x0400)
41493 +#define MCF_GPIO_PAR_DSPI_PAR_CS3_TOUT (0x0800)
41494 +#define MCF_GPIO_PAR_DSPI_PAR_CS3_DSPICS (0x0C00)
41495 +#define MCF_GPIO_PAR_DSPI_PAR_CS2_GPIO (0x0000)
41496 +#define MCF_GPIO_PAR_DSPI_PAR_CS2_CANTX (0x0100)
41497 +#define MCF_GPIO_PAR_DSPI_PAR_CS2_TOUT (0x0200)
41498 +#define MCF_GPIO_PAR_DSPI_PAR_CS2_DSPICS (0x0300)
41499 +#define MCF_GPIO_PAR_DSPI_PAR_CS0_GPIO (0x0000)
41500 +#define MCF_GPIO_PAR_DSPI_PAR_CS0_FSYNC (0x0040)
41501 +#define MCF_GPIO_PAR_DSPI_PAR_CS0_RTS (0x0080)
41502 +#define MCF_GPIO_PAR_DSPI_PAR_CS0_DSPICS (0x00C0)
41503 +#define MCF_GPIO_PAR_DSPI_PAR_SCK_GPIO (0x0000)
41504 +#define MCF_GPIO_PAR_DSPI_PAR_SCK_BCLK (0x0010)
41505 +#define MCF_GPIO_PAR_DSPI_PAR_SCK_CTS (0x0020)
41506 +#define MCF_GPIO_PAR_DSPI_PAR_SCK_SCK (0x0030)
41507 +#define MCF_GPIO_PAR_DSPI_PAR_SIN_GPIO (0x0000)
41508 +#define MCF_GPIO_PAR_DSPI_PAR_SIN_RXD (0x0008)
41509 +#define MCF_GPIO_PAR_DSPI_PAR_SIN_SIN (0x000C)
41510 +#define MCF_GPIO_PAR_DSPI_PAR_SOUT_GPIO (0x0000)
41511 +#define MCF_GPIO_PAR_DSPI_PAR_SOUT_TXD (0x0002)
41512 +#define MCF_GPIO_PAR_DSPI_PAR_SOUT_SOUT (0x0003)
41513 +
41514 +/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */
41515 +#define MCF_GPIO_PAR_TIMER_PAR_TOUT2 (0x01)
41516 +#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<1)
41517 +#define MCF_GPIO_PAR_TIMER_PAR_TOUT3 (0x08)
41518 +#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<4)
41519 +#define MCF_GPIO_PAR_TIMER_PAR_TIN3_CANRX (0x00)
41520 +#define MCF_GPIO_PAR_TIMER_PAR_TIN3_IRQ (0x20)
41521 +#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN (0x30)
41522 +#define MCF_GPIO_PAR_TIMER_PAR_TIN2_CANRX (0x00)
41523 +#define MCF_GPIO_PAR_TIMER_PAR_TIN2_IRQ (0x04)
41524 +#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN (0x06)
41525 +
41526 +/********************************************************************/
41527 +
41528 +#endif /* _M5485GPIO_H_ */
41529 --- /dev/null
41530 +++ b/include/asm-m68k/m5485gpt.h
41531 @@ -0,0 +1,88 @@
41532 +/*
41533 + * File: mcf548x_gpt.h
41534 + * Purpose: Register and bit definitions for the MCF548X
41535 + *
41536 + * Notes:
41537 + *
41538 + */
41539 +
41540 +#ifndef __MCF548X_GPT_H__
41541 +#define __MCF548X_GPT_H__
41542 +
41543 +/*********************************************************************
41544 +*
41545 +* General Purpose Timers (GPT)
41546 +*
41547 +*********************************************************************/
41548 +
41549 +/* Register read/write macros */
41550 +#define MCF_GPT_GMS0 MCF_REG32(0x000800)
41551 +#define MCF_GPT_GCIR0 MCF_REG32(0x000804)
41552 +#define MCF_GPT_GPWM0 MCF_REG32(0x000808)
41553 +#define MCF_GPT_GSR0 MCF_REG32(0x00080C)
41554 +#define MCF_GPT_GMS1 MCF_REG32(0x000810)
41555 +#define MCF_GPT_GCIR1 MCF_REG32(0x000814)
41556 +#define MCF_GPT_GPWM1 MCF_REG32(0x000818)
41557 +#define MCF_GPT_GSR1 MCF_REG32(0x00081C)
41558 +#define MCF_GPT_GMS2 MCF_REG32(0x000820)
41559 +#define MCF_GPT_GCIR2 MCF_REG32(0x000824)
41560 +#define MCF_GPT_GPWM2 MCF_REG32(0x000828)
41561 +#define MCF_GPT_GSR2 MCF_REG32(0x00082C)
41562 +#define MCF_GPT_GMS3 MCF_REG32(0x000830)
41563 +#define MCF_GPT_GCIR3 MCF_REG32(0x000834)
41564 +#define MCF_GPT_GPWM3 MCF_REG32(0x000838)
41565 +#define MCF_GPT_GSR3 MCF_REG32(0x00083C)
41566 +#define MCF_GPT_GMS(x) MCF_REG32(0x000800+((x)*0x010))
41567 +#define MCF_GPT_GCIR(x) MCF_REG32(0x000804+((x)*0x010))
41568 +#define MCF_GPT_GPWM(x) MCF_REG32(0x000808+((x)*0x010))
41569 +#define MCF_GPT_GSR(x) MCF_REG32(0x00080C+((x)*0x010))
41570 +
41571 +/* Bit definitions and macros for MCF_GPT_GMS */
41572 +#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0)
41573 +#define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4)
41574 +#define MCF_GPT_GMS_IEN (0x00000100)
41575 +#define MCF_GPT_GMS_OD (0x00000200)
41576 +#define MCF_GPT_GMS_SC (0x00000400)
41577 +#define MCF_GPT_GMS_CE (0x00001000)
41578 +#define MCF_GPT_GMS_WDEN (0x00008000)
41579 +#define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16)
41580 +#define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20)
41581 +#define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24)
41582 +#define MCF_GPT_GMS_OCT_FRCLOW (0x00000000)
41583 +#define MCF_GPT_GMS_OCT_PULSEHI (0x00100000)
41584 +#define MCF_GPT_GMS_OCT_PULSELO (0x00200000)
41585 +#define MCF_GPT_GMS_OCT_TOGGLE (0x00300000)
41586 +#define MCF_GPT_GMS_ICT_ANY (0x00000000)
41587 +#define MCF_GPT_GMS_ICT_RISE (0x00010000)
41588 +#define MCF_GPT_GMS_ICT_FALL (0x00020000)
41589 +#define MCF_GPT_GMS_ICT_PULSE (0x00030000)
41590 +#define MCF_GPT_GMS_GPIO_INPUT (0x00000000)
41591 +#define MCF_GPT_GMS_GPIO_OUTLO (0x00000020)
41592 +#define MCF_GPT_GMS_GPIO_OUTHI (0x00000030)
41593 +#define MCF_GPT_GMS_TMS_DISABLE (0x00000000)
41594 +#define MCF_GPT_GMS_TMS_INCAPT (0x00000001)
41595 +#define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002)
41596 +#define MCF_GPT_GMS_TMS_PWM (0x00000003)
41597 +#define MCF_GPT_GMS_TMS_GPIO (0x00000004)
41598 +
41599 +/* Bit definitions and macros for MCF_GPT_GCIR */
41600 +#define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0)
41601 +#define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16)
41602 +
41603 +/* Bit definitions and macros for MCF_GPT_GPWM */
41604 +#define MCF_GPT_GPWM_LOAD (0x00000001)
41605 +#define MCF_GPT_GPWM_PWMOP (0x00000100)
41606 +#define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16)
41607 +
41608 +/* Bit definitions and macros for MCF_GPT_GSR */
41609 +#define MCF_GPT_GSR_CAPT (0x00000001)
41610 +#define MCF_GPT_GSR_COMP (0x00000002)
41611 +#define MCF_GPT_GSR_PWMP (0x00000004)
41612 +#define MCF_GPT_GSR_TEXP (0x00000008)
41613 +#define MCF_GPT_GSR_PIN (0x00000100)
41614 +#define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12)
41615 +#define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16)
41616 +
41617 +/********************************************************************/
41618 +
41619 +#endif /* __MCF548X_GPT_H__ */
41620 --- /dev/null
41621 +++ b/include/asm-m68k/m5485i2c.h
41622 @@ -0,0 +1,45 @@
41623 +/*
41624 + * m5485i2c.h -- ColdFire 547x/548x i2c controller support.
41625 + */
41626 +#ifndef M548X_I2C_H
41627 +#define M548X_I2C_H
41628 +
41629 +/* Register read/write macros */
41630 +#define MCF_I2AR MCF_REG08(0x008F00) /* I2C Address */
41631 +#define MCF_I2FDR MCF_REG08(0x008F04) /* I2C Frequency Divider */
41632 +#define MCF_I2CR MCF_REG08(0x008F08) /* I2C Control */
41633 +#define MCF_I2SR MCF_REG08(0x008F0C) /* I2C Status */
41634 +#define MCF_I2DR MCF_REG08(0x008F10) /* I2C Data I/O */
41635 +#define MCF_I2ICR MCF_REG08(0x008F20) /* I2C Interrupt Control */
41636 +
41637 +/* Bit definitions and macros for MCF_I2C_I2AR */
41638 +#define MCF_I2AR_ADR(x) (((x)&0x7F)<<1)
41639 +
41640 +/* Bit definitions and macros for MCF_I2C_I2FDR */
41641 +#define MCF_I2FDR_IC(x) (((x)&0x3F)<<0)
41642 +
41643 +/* Bit definitions and macros for MCF_I2C_I2CR */
41644 +#define MCF_I2CR_RSTA (0x04)
41645 +#define MCF_I2CR_TXAK (0x08)
41646 +#define MCF_I2CR_MTX (0x10)
41647 +#define MCF_I2CR_MSTA (0x20)
41648 +#define MCF_I2CR_IIEN (0x40)
41649 +#define MCF_I2CR_IEN (0x80)
41650 +
41651 +/* Bit definitions and macros for MCF_I2C_I2SR */
41652 +#define MCF_I2SR_RXAK (0x01)
41653 +#define MCF_I2SR_IIF (0x02)
41654 +#define MCF_I2SR_SRW (0x04)
41655 +#define MCF_I2SR_IAL (0x10)
41656 +#define MCF_I2SR_IBB (0x20)
41657 +#define MCF_I2SR_IAAS (0x40)
41658 +#define MCF_I2SR_ICF (0x80)
41659 +
41660 +/* Bit definitions and macros for MCF_I2C_I2ICR */
41661 +#define MCF_I2ICR_IE (0x01)
41662 +#define MCF_I2ICR_RE (0x02)
41663 +#define MCF_I2ICR_TE (0x04)
41664 +#define MCF_I2ICR_BNBE (0x08)
41665 +
41666 +/********************************************************************/
41667 +#endif
41668 --- /dev/null
41669 +++ b/include/asm-m68k/m5485pci.h
41670 @@ -0,0 +1,330 @@
41671 +/*
41672 + * m5485pci.h -- ColdFire 547x/548x PCI controller support.
41673 + */
41674 +#ifndef __MCF548X_PCI_H__
41675 +#define __MCF548X_PCI_H__
41676 +
41677 +
41678 +/* PCI Type 0 Configuration Registers */
41679 +#define MCF_PCIIDR MCF_REG32(0x000B00) /* PCI Device ID/Vendor ID */
41680 +#define MCF_PCISCR MCF_REG32(0x000B04) /* PCI Status/Command */
41681 +#define MCF_PCICCRIR MCF_REG32(0x000B08) /* PCI Class Code / Revision ID */
41682 +#define MCF_PCICR1 MCF_REG32(0x000B0C) /* PCI Configuration 1 Register */
41683 +#define MCF_PCIBAR0 MCF_REG32(0x000B10) /* PCI Base Address Register 0 */
41684 +#define MCF_PCIBAR1 MCF_REG32(0x000B14) /* PCI Base Address Register 1 */
41685 +#define MCF_PCICCPR MCF_REG32(0x000B28) /* PCI Cardbus CIS Pointer */
41686 +#define MCF_PCISID MCF_REG32(0x000B2C) /* Subsystem ID/Subsystem Vendor ID*/
41687 +#define MCF_PCIERBAR MCF_REG32(0x000B30) /* PCI Expansion ROM */
41688 +#define MCF_PCICPR MCF_REG32(0x000B30) /* PCI Capabilities Pointer */
41689 +#define MCF_PCICR2 MCF_REG32(0x000B3C) /* PCI Configuration Register 2 */
41690 +
41691 +/* General Control/Status Registers */
41692 +#define MCF_PCIGSCR MCF_REG32(0x000B60) /* Global Status/Control Register */
41693 +#define MCF_PCITBATR0 MCF_REG32(0x000B64) /* Target Base Address Translation 0*/
41694 +#define MCF_PCITBATR1 MCF_REG32(0x000B68) /* Target Base Address Translation 1*/
41695 +#define MCF_PCITCR MCF_REG32(0x000B6C) /* Target Control Register */
41696 +#define MCF_PCIIW0BTAR MCF_REG32(0x000B70) /* Initiator Window 0 Base Address */
41697 +#define MCF_PCIIW1BTAR MCF_REG32(0x000B74) /* Initiator Window 1 Base Address */
41698 +#define MCF_PCIIW2BTAR MCF_REG32(0x000B78) /* Initiator Window 2 Base Address */
41699 +#define MCF_PCIIWCR MCF_REG32(0x000B80) /* Initiator Window Configuration */
41700 +#define MCF_PCIICR MCF_REG32(0x000B84) /* Initiator Control Register */
41701 +#define MCF_PCIISR MCF_REG32(0x000B88) /* Initiator Status Register */
41702 +#define MCF_PCICAR MCF_REG32(0x000BF8) /* Configuration Address Register */
41703 +
41704 +/* CommBus FIFO Transmit Interface Registers */
41705 +#define MCF_PCITPSR MCF_REG32(0x008400) /* Tx Packet Size Register */
41706 +#define MCF_PCITSAR MCF_REG32(0x008404) /* Tx Start Address Register */
41707 +#define MCF_PCITTCR MCF_REG32(0x008408) /* Tx Transaction Control Register */
41708 +#define MCF_PCITER MCF_REG32(0x00840C) /* Tx Enables Register */
41709 +#define MCF_PCITNAR MCF_REG32(0x008410) /* Tx Next Address Register */
41710 +#define MCF_PCITLWR MCF_REG32(0x008414) /* Tx Last Word Register */
41711 +#define MCF_PCITDCR MCF_REG32(0x008418) /* Tx Done Counts Register */
41712 +#define MCF_PCITSR MCF_REG32(0x00841C) /* Tx Status Register */
41713 +#define MCF_PCITFDR MCF_REG32(0x008440) /* Tx FIFO Data Register */
41714 +#define MCF_PCITFSR MCF_REG32(0x008444) /* Tx FIFO Status Register */
41715 +#define MCF_PCITFCR MCF_REG32(0x008448) /* Tx FIFO Control Register */
41716 +#define MCF_PCITFAR MCF_REG32(0x00844C) /* Tx FIFO Alarm Register */
41717 +#define MCF_PCITFRPR MCF_REG32(0x008450) /* Tx FIFO Read Pointer Register */
41718 +#define MCF_PCITFWPR MCF_REG32(0x008454) /* Tx FIFO Write Pointer Register */
41719 +
41720 +/* CommBus FIFO Receive Interface Registers */
41721 +#define MCF_PCIRPSR MCF_REG32(0x008480) /* Tx Packet Size Register */
41722 +#define MCF_PCIRSAR MCF_REG32(0x008484) /* Tx Start Address Register */
41723 +#define MCF_PCIRTCR MCF_REG32(0x008488) /* Tx Transaction Control Register */
41724 +#define MCF_PCIRER MCF_REG32(0x00848C) /* Tx Enables Register */
41725 +#define MCF_PCIRNAR MCF_REG32(0x008490) /* Tx Next Address Register */
41726 +#define MCF_PCIRDCR MCF_REG32(0x008498) /* Tx Done Counts Register */
41727 +#define MCF_PCIRSR MCF_REG32(0x00849C) /* Tx Status Register */
41728 +#define MCF_PCIRFDR MCF_REG32(0x0084C0) /* Tx FIFO Data Register */
41729 +#define MCF_PCIRFSR MCF_REG32(0x0084C4) /* Tx FIFO Status Register */
41730 +#define MCF_PCIRFCR MCF_REG32(0x0084C8) /* Tx FIFO Control Register */
41731 +#define MCF_PCIRFAR MCF_REG32(0x0084CC) /* Tx FIFO Alarm Register */
41732 +#define MCF_PCIRFRPR MCF_REG32(0x0084D0) /* Tx FIFO Read Pointer Register */
41733 +#define MCF_PCIRFWPR MCF_REG32(0x0084D4) /* Tx FIFO Write Pointer Register */
41734 +
41735 +/* PCI Arbiter Registers */
41736 +#define MCF_PCIARB_PACR MCF_REG32(0x000C00)
41737 +#define MCF_PCIARB_PASR MCF_REG32(0x000C04)
41738 +
41739 +
41740 +/* Bit definitions and macros for MCF_PCIIDR */
41741 +#define MCF_PCIIDR_VENDORID(x) (((x)&0x0000FFFF)<<0)
41742 +#define MCF_PCIIDR_DEVICEID(x) (((x)&0x0000FFFF)<<16)
41743 +
41744 +/* Bit definitions and macros for MCF_PCISCR */
41745 +#define MCF_PCISCR_M (0x00000002)
41746 +#define MCF_PCISCR_B (0x00000004)
41747 +#define MCF_PCISCR_SP (0x00000008)
41748 +#define MCF_PCISCR_MW (0x00000010)
41749 +#define MCF_PCISCR_PER (0x00000040)
41750 +#define MCF_PCISCR_S (0x00000100)
41751 +#define MCF_PCISCR_F (0x00000200)
41752 +#define MCF_PCISCR_C (0x00100000)
41753 +#define MCF_PCISCR_66M (0x00200000)
41754 +#define MCF_PCISCR_R (0x00400000)
41755 +#define MCF_PCISCR_FC (0x00800000)
41756 +#define MCF_PCISCR_DP (0x01000000)
41757 +#define MCF_PCISCR_DT(x) (((x)&0x00000003)<<25)
41758 +#define MCF_PCISCR_TS (0x08000000)
41759 +#define MCF_PCISCR_TR (0x10000000)
41760 +#define MCF_PCISCR_MA (0x20000000)
41761 +#define MCF_PCISCR_SE (0x40000000)
41762 +#define MCF_PCISCR_PE (0x80000000)
41763 +
41764 +/* Bit definitions and macros for MCF_PCICCRIR */
41765 +#define MCF_PCICCRIR_REVID(x) (((x)&0x000000FF)<<0)
41766 +#define MCF_PCICCRIR_CLASSCODE(x) (((x)&0x00FFFFFF)<<8)
41767 +
41768 +/* Bit definitions and macros for MCF_PCICR1 */
41769 +#define MCF_PCICR1_CACHELINESIZE(x) (((x)&0x0000000F)<<0)
41770 +#define MCF_PCICR1_LATTIMER(x) (((x)&0x000000FF)<<8)
41771 +#define MCF_PCICR1_HEADERTYPE(x) (((x)&0x000000FF)<<16)
41772 +#define MCF_PCICR1_BIST(x) (((x)&0x000000FF)<<24)
41773 +
41774 +/* Bit definitions and macros for MCF_PCIBAR# */
41775 +#define MCF_PCIBAR0_ADDR(x) (((x)&0x00003FFF)<<18)
41776 +#define MCF_PCIBAR1_ADDR(x) (((x)&0x00000003)<<30)
41777 +
41778 +/* Bit definitions and macros for MCF_PCICR2 */
41779 +#define MCF_PCICR2_INTLINE(x) (((x)&0x000000FF)<<0)
41780 +#define MCF_PCICR2_INTPIN(x) (((x)&0x000000FF)<<8)
41781 +#define MCF_PCICR2_MINGNT(x) (((x)&0x000000FF)<<16)
41782 +#define MCF_PCICR2_MAXLAT(x) (((x)&0x000000FF)<<24)
41783 +
41784 +/* Bit definitions and macros for MCF_PCIGSCR */
41785 +#define MCF_PCIGSCR_PR (0x00000001)
41786 +#define MCF_PCIGSCR_SEE (0x00001000)
41787 +#define MCF_PCIGSCR_PEE (0x00002000)
41788 +#define MCF_PCIGSCR_SE (0x10000000)
41789 +#define MCF_PCIGSCR_PE (0x20000000)
41790 +
41791 +/* Bit definitions and macros for MCF_PCITBATR0 */
41792 +#define MCF_PCITBATR0_EN (0x00000001)
41793 +#define MCF_PCITBATR0_BAT0(x) (((x)&0x00003FFF)<<18)
41794 +
41795 +/* Bit definitions and macros for MCF_PCITBATR1 */
41796 +#define MCF_PCITBATR1_EN (0x00000001)
41797 +#define MCF_PCITBATR1_BAT1(x) (((x)&0x00000003)<<30)
41798 +
41799 +/* Bit definitions and macros for MCF_PCITCR */
41800 +#define MCF_PCITCR_P (0x00010000)
41801 +#define MCF_PCITCR_LD (0x01000000)
41802 +
41803 +/* Bit definitions and macros for MCF_PCIIW0BTAR */
41804 +#define MCF_PCIIW0BTAR_WTA0(x) (((x)&0x000000FF)<<8)
41805 +#define MCF_PCIIW0BTAR_WAM0(x) (((x)&0x000000FF)<<16)
41806 +#define MCF_PCIIW0BTAR_WBA0(x) (((x)&0x000000FF)<<24)
41807 +
41808 +/* Bit definitions and macros for MCF_PCIIW1BTAR */
41809 +#define MCF_PCIIW1BTAR_WTA1(x) (((x)&0x000000FF)<<8)
41810 +#define MCF_PCIIW1BTAR_WAM1(x) (((x)&0x000000FF)<<16)
41811 +#define MCF_PCIIW1BTAR_WBA1(x) (((x)&0x000000FF)<<24)
41812 +
41813 +/* Bit definitions and macros for MCF_PCIIW2BTAR */
41814 +#define MCF_PCIIW2BTAR_WTA2(x) (((x)&0x000000FF)<<8)
41815 +#define MCF_PCIIW2BTAR_WAM2(x) (((x)&0x000000FF)<<16)
41816 +#define MCF_PCIIW2BTAR_WBA2(x) (((x)&0x000000FF)<<24)
41817 +
41818 +/* Bit definitions and macros for MCF_PCIIWCR */
41819 +#define MCF_PCIIWCR_WINCTRL2(x) (((x)&0x0000000F)<<8)
41820 +#define MCF_PCIIWCR_WINCTRL1(x) (((x)&0x0000000F)<<16)
41821 +#define MCF_PCIIWCR_WINCTRL0(x) (((x)&0x0000000F)<<24)
41822 +#define MCF_PCIIWCR_WINCTRL0_MEMREAD (0x01000000)
41823 +#define MCF_PCIIWCR_WINCTRL0_MEMRDLINE (0x03000000)
41824 +#define MCF_PCIIWCR_WINCTRL0_MEMRDMUL (0x05000000)
41825 +#define MCF_PCIIWCR_WINCTRL0_IO (0x09000000)
41826 +#define MCF_PCIIWCR_WINCTRL0_E (0x01000000)
41827 +#define MCF_PCIIWCR_WINCTRL1_MEMREAD (0x00010000)
41828 +#define MCF_PCIIWCR_WINCTRL1_MEMRDLINE (0x00030000)
41829 +#define MCF_PCIIWCR_WINCTRL1_MEMRDMUL (0x00050000)
41830 +#define MCF_PCIIWCR_WINCTRL1_IO (0x00090000)
41831 +#define MCF_PCIIWCR_WINCTRL1_E (0x00010000)
41832 +#define MCF_PCIIWCR_WINCTRL2_MEMREAD (0x00000100)
41833 +#define MCF_PCIIWCR_WINCTRL2_MEMRDLINE (0x00000300)
41834 +#define MCF_PCIIWCR_WINCTRL2_MEMRDMUL (0x00000500)
41835 +#define MCF_PCIIWCR_WINCTRL2_IO (0x00000900)
41836 +#define MCF_PCIIWCR_WINCTRL2_E (0x00000100)
41837 +
41838 +
41839 +/* Bit definitions and macros for MCF_PCIICR */
41840 +#define MCF_PCIICR_MAXRETRY(x) (((x)&0x000000FF)<<0)
41841 +#define MCF_PCIICR_TAE (0x01000000)
41842 +#define MCF_PCIICR_IAE (0x02000000)
41843 +#define MCF_PCIICR_REE (0x04000000)
41844 +
41845 +/* Bit definitions and macros for MCF_PCIISR */
41846 +#define MCF_PCIISR_TA (0x01000000)
41847 +#define MCF_PCIISR_IA (0x02000000)
41848 +#define MCF_PCIISR_RE (0x04000000)
41849 +
41850 +/* Bit definitions and macros for MCF_PCICAR */
41851 +#define MCF_PCICAR_DWORD(x) (((x)&0x0000003F)<<2)
41852 +#define MCF_PCICAR_FUNCNUM(x) (((x)&0x00000007)<<8)
41853 +#define MCF_PCICAR_DEVNUM(x) (((x)&0x0000001F)<<11)
41854 +#define MCF_PCICAR_BUSNUM(x) (((x)&0x000000FF)<<16)
41855 +#define MCF_PCICAR_E (0x80000000)
41856 +
41857 +/* Bit definitions and macros for MCF_PCITPSR */
41858 +#define MCF_PCITPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16)
41859 +
41860 +/* Bit definitions and macros for MCF_PCITTCR */
41861 +#define MCF_PCITTCR_DI (0x00000001)
41862 +#define MCF_PCITTCR_W (0x00000010)
41863 +#define MCF_PCITTCR_MAXBEATS(x) (((x)&0x00000007)<<8)
41864 +#define MCF_PCITTCR_MAXRETRY(x) (((x)&0x000000FF)<<16)
41865 +#define MCF_PCITTCR_PCICMD(x) (((x)&0x0000000F)<<24)
41866 +
41867 +/* Bit definitions and macros for MCF_PCITER */
41868 +#define MCF_PCITER_NE (0x00010000)
41869 +#define MCF_PCITER_IAE (0x00020000)
41870 +#define MCF_PCITER_TAE (0x00040000)
41871 +#define MCF_PCITER_RE (0x00080000)
41872 +#define MCF_PCITER_SE (0x00100000)
41873 +#define MCF_PCITER_FEE (0x00200000)
41874 +#define MCF_PCITER_ME (0x01000000)
41875 +#define MCF_PCITER_BE (0x08000000)
41876 +#define MCF_PCITER_CM (0x10000000)
41877 +#define MCF_PCITER_RF (0x40000000)
41878 +#define MCF_PCITER_RC (0x80000000)
41879 +
41880 +/* Bit definitions and macros for MCF_PCITDCR */
41881 +#define MCF_PCITDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0)
41882 +#define MCF_PCITDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16)
41883 +
41884 +/* Bit definitions and macros for MCF_PCITSR */
41885 +#define MCF_PCITSR_IA (0x00010000)
41886 +#define MCF_PCITSR_TA (0x00020000)
41887 +#define MCF_PCITSR_RE (0x00040000)
41888 +#define MCF_PCITSR_SE (0x00080000)
41889 +#define MCF_PCITSR_FE (0x00100000)
41890 +#define MCF_PCITSR_BE1 (0x00200000)
41891 +#define MCF_PCITSR_BE2 (0x00400000)
41892 +#define MCF_PCITSR_BE3 (0x00800000)
41893 +#define MCF_PCITSR_NT (0x01000000)
41894 +
41895 +/* Bit definitions and macros for MCF_PCITFSR */
41896 +#define MCF_PCITFSR_EMT (0x00010000)
41897 +#define MCF_PCITFSR_ALARM (0x00020000)
41898 +#define MCF_PCITFSR_FU (0x00040000)
41899 +#define MCF_PCITFSR_FR (0x00080000)
41900 +#define MCF_PCITFSR_OF (0x00100000)
41901 +#define MCF_PCITFSR_UF (0x00200000)
41902 +#define MCF_PCITFSR_RXW (0x00400000)
41903 +
41904 +/* Bit definitions and macros for MCF_PCITFCR */
41905 +#define MCF_PCITFCR_OF_MSK (0x00080000)
41906 +#define MCF_PCITFCR_UF_MSK (0x00100000)
41907 +#define MCF_PCITFCR_RXW_MSK (0x00200000)
41908 +#define MCF_PCITFCR_FAE_MSK (0x00400000)
41909 +#define MCF_PCITFCR_IP_MSK (0x00800000)
41910 +#define MCF_PCITFCR_GR(x) (((x)&0x00000007)<<24)
41911 +
41912 +/* Bit definitions and macros for MCF_PCITFAR */
41913 +#define MCF_PCITFAR_ALARM(x) (((x)&0x0000007F)<<0)
41914 +
41915 +/* Bit definitions and macros for MCF_PCITFRPR */
41916 +#define MCF_PCITFRPR_READ(x) (((x)&0x00000FFF)<<0)
41917 +
41918 +/* Bit definitions and macros for MCF_PCITFWPR */
41919 +#define MCF_PCITFWPR_WRITE(x) (((x)&0x00000FFF)<<0)
41920 +
41921 +/* Bit definitions and macros for MCF_PCIRPSR */
41922 +#define MCF_PCIRPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16)
41923 +
41924 +/* Bit definitions and macros for MCF_PCIRTCR */
41925 +#define MCF_PCIRTCR_DI (0x00000001)
41926 +#define MCF_PCIRTCR_W (0x00000010)
41927 +#define MCF_PCIRTCR_MAXBEATS(x) (((x)&0x00000007)<<8)
41928 +#define MCF_PCIRTCR_FB (0x00001000)
41929 +#define MCF_PCIRTCR_MAXRETRY(x) (((x)&0x000000FF)<<16)
41930 +#define MCF_PCIRTCR_PCICMD(x) (((x)&0x0000000F)<<24)
41931 +
41932 +/* Bit definitions and macros for MCF_PCIRER */
41933 +#define MCF_PCIRER_NE (0x00010000)
41934 +#define MCF_PCIRER_IAE (0x00020000)
41935 +#define MCF_PCIRER_TAE (0x00040000)
41936 +#define MCF_PCIRER_RE (0x00080000)
41937 +#define MCF_PCIRER_SE (0x00100000)
41938 +#define MCF_PCIRER_FEE (0x00200000)
41939 +#define MCF_PCIRER_ME (0x01000000)
41940 +#define MCF_PCIRER_BE (0x08000000)
41941 +#define MCF_PCIRER_CM (0x10000000)
41942 +#define MCF_PCIRER_FE (0x20000000)
41943 +#define MCF_PCIRER_RF (0x40000000)
41944 +#define MCF_PCIRER_RC (0x80000000)
41945 +
41946 +/* Bit definitions and macros for MCF_PCIRDCR */
41947 +#define MCF_PCIRDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0)
41948 +#define MCF_PCIRDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16)
41949 +
41950 +/* Bit definitions and macros for MCF_PCIRSR */
41951 +#define MCF_PCIRSR_IA (0x00010000)
41952 +#define MCF_PCIRSR_TA (0x00020000)
41953 +#define MCF_PCIRSR_RE (0x00040000)
41954 +#define MCF_PCIRSR_SE (0x00080000)
41955 +#define MCF_PCIRSR_FE (0x00100000)
41956 +#define MCF_PCIRSR_BE1 (0x00200000)
41957 +#define MCF_PCIRSR_BE2 (0x00400000)
41958 +#define MCF_PCIRSR_BE3 (0x00800000)
41959 +#define MCF_PCIRSR_NT (0x01000000)
41960 +
41961 +/* Bit definitions and macros for MCF_PCIRFSR */
41962 +#define MCF_PCIRFSR_EMT (0x00010000)
41963 +#define MCF_PCIRFSR_ALARM (0x00020000)
41964 +#define MCF_PCIRFSR_FU (0x00040000)
41965 +#define MCF_PCIRFSR_FR (0x00080000)
41966 +#define MCF_PCIRFSR_OF (0x00100000)
41967 +#define MCF_PCIRFSR_UF (0x00200000)
41968 +#define MCF_PCIRFSR_RXW (0x00400000)
41969 +
41970 +/* Bit definitions and macros for MCF_PCIRFCR */
41971 +#define MCF_PCIRFCR_OF_MSK (0x00080000)
41972 +#define MCF_PCIRFCR_UF_MSK (0x00100000)
41973 +#define MCF_PCIRFCR_RXW_MSK (0x00200000)
41974 +#define MCF_PCIRFCR_FAE_MSK (0x00400000)
41975 +#define MCF_PCIRFCR_IP_MSK (0x00800000)
41976 +#define MCF_PCIRFCR_GR(x) (((x)&0x00000007)<<24)
41977 +
41978 +/* Bit definitions and macros for MCF_PCIRFAR */
41979 +#define MCF_PCIRFAR_ALARM(x) (((x)&0x0000007F)<<0)
41980 +
41981 +/* Bit definitions and macros for MCF_PCIRFRPR */
41982 +#define MCF_PCIRFRPR_READ(x) (((x)&0x00000FFF)<<0)
41983 +
41984 +/* Bit definitions and macros for MCF_PCIRFWPR */
41985 +#define MCF_PCIRFWPR_WRITE(x) (((x)&0x00000FFF)<<0)
41986 +
41987 +
41988 +/* Bit definitions and macros for MCF_PCIARB_PACR */
41989 +#define MCF_PCIARB_PACR_INTMPRI (0x00000001)
41990 +#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x0000001F)<<1)
41991 +#define MCF_PCIARB_PACR_INTMINTEN (0x00010000)
41992 +#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x0000001F)<<17)
41993 +#define MCF_PCIARB_PACR_PKMD (0x40000000)
41994 +#define MCF_PCIARB_PACR_DS (0x80000000)
41995 +
41996 +/* Bit definitions and macros for MCF_PCIARB_PASR */
41997 +#define MCF_PCIARB_PASR_ITLMBK (0x00010000)
41998 +#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x0000001F)<<17)
41999 +
42000 +#endif /* __MCF548X_PCI_H__ */
42001 --- /dev/null
42002 +++ b/include/asm-m68k/m5485psc.h
42003 @@ -0,0 +1,474 @@
42004 +/*
42005 + * File: mcf548x_psc.h
42006 + * Purpose: Register and bit definitions for the MCF548X
42007 + *
42008 + * Notes:
42009 + *
42010 + */
42011 +
42012 +#ifndef __MCF548X_PSC_H__
42013 +#define __MCF548X_PSC_H__
42014 +
42015 +/*********************************************************************
42016 +*
42017 +* Programmable Serial Controller (PSC)
42018 +*
42019 +*********************************************************************/
42020 +
42021 +/* Register read/write macros */
42022 +#define MCF_PSC_MR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008600))
42023 +#define MCF_PSC_SR0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008604))
42024 +#define MCF_PSC_CSR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008604))
42025 +#define MCF_PSC_CR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008608))
42026 +#define MCF_PSC_RB0 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C))
42027 +#define MCF_PSC_TB0 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C))
42028 +#define MCF_PSC_TB_8BIT0 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C))
42029 +#define MCF_PSC_TB_16BIT0 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C))
42030 +#define MCF_PSC_TB_AC970 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C))
42031 +#define MCF_PSC_IPCR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008610))
42032 +#define MCF_PSC_ACR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008610))
42033 +#define MCF_PSC_ISR0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008614))
42034 +#define MCF_PSC_IMR0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008614))
42035 +#define MCF_PSC_CTUR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008618))
42036 +#define MCF_PSC_CTLR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00861C))
42037 +#define MCF_PSC_IP0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008634))
42038 +#define MCF_PSC_OPSET0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008638))
42039 +#define MCF_PSC_OPRESET0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00863C))
42040 +#define MCF_PSC_SICR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008640))
42041 +#define MCF_PSC_IRCR10 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008644))
42042 +#define MCF_PSC_IRCR20 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008648))
42043 +#define MCF_PSC_IRSDR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00864C))
42044 +#define MCF_PSC_IRMDR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008650))
42045 +#define MCF_PSC_IRFDR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008654))
42046 +#define MCF_PSC_RFCNT0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008658))
42047 +#define MCF_PSC_TFCNT0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00865C))
42048 +#define MCF_PSC_RFSR0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008664))
42049 +#define MCF_PSC_TFSR0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008684))
42050 +#define MCF_PSC_RFCR0 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008668))
42051 +#define MCF_PSC_TFCR0 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008688))
42052 +#define MCF_PSC_RFAR0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00866E))
42053 +#define MCF_PSC_TFAR0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00868E))
42054 +#define MCF_PSC_RFRP0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008672))
42055 +#define MCF_PSC_TFRP0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008692))
42056 +#define MCF_PSC_RFWP0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008676))
42057 +#define MCF_PSC_TFWP0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008696))
42058 +#define MCF_PSC_RLRFP0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00867A))
42059 +#define MCF_PSC_TLRFP0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00869A))
42060 +#define MCF_PSC_RLWFP0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00867E))
42061 +#define MCF_PSC_TLWFP0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00869E))
42062 +#define MCF_PSC_MR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008700))
42063 +#define MCF_PSC_SR1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008704))
42064 +#define MCF_PSC_CSR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008704))
42065 +#define MCF_PSC_CR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008708))
42066 +#define MCF_PSC_RB1 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00870C))
42067 +#define MCF_PSC_TB1 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00870C))
42068 +#define MCF_PSC_TB_8BIT1 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00870C))
42069 +#define MCF_PSC_TB_16BIT1 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00870C))
42070 +#define MCF_PSC_TB_AC971 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00870C))
42071 +#define MCF_PSC_IPCR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008710))
42072 +#define MCF_PSC_ACR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008710))
42073 +#define MCF_PSC_ISR1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008714))
42074 +#define MCF_PSC_IMR1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008714))
42075 +#define MCF_PSC_CTUR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008718))
42076 +#define MCF_PSC_CTLR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00871C))
42077 +#define MCF_PSC_IP1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008734))
42078 +#define MCF_PSC_OPSET1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008738))
42079 +#define MCF_PSC_OPRESET1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00873C))
42080 +#define MCF_PSC_SICR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008740))
42081 +#define MCF_PSC_IRCR11 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008744))
42082 +#define MCF_PSC_IRCR21 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008748))
42083 +#define MCF_PSC_IRSDR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00874C))
42084 +#define MCF_PSC_IRMDR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008750))
42085 +#define MCF_PSC_IRFDR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008754))
42086 +#define MCF_PSC_RFCNT1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008758))
42087 +#define MCF_PSC_TFCNT1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00875C))
42088 +#define MCF_PSC_RFSR1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008764))
42089 +#define MCF_PSC_TFSR1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008784))
42090 +#define MCF_PSC_RFCR1 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008768))
42091 +#define MCF_PSC_TFCR1 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008788))
42092 +#define MCF_PSC_RFAR1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00876E))
42093 +#define MCF_PSC_TFAR1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00878E))
42094 +#define MCF_PSC_RFRP1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008772))
42095 +#define MCF_PSC_TFRP1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008792))
42096 +#define MCF_PSC_RFWP1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008776))
42097 +#define MCF_PSC_TFWP1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008796))
42098 +#define MCF_PSC_RLRFP1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00877A))
42099 +#define MCF_PSC_TLRFP1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00879A))
42100 +#define MCF_PSC_RLWFP1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00877E))
42101 +#define MCF_PSC_TLWFP1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00879E))
42102 +#define MCF_PSC_MR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008800))
42103 +#define MCF_PSC_SR2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008804))
42104 +#define MCF_PSC_CSR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008804))
42105 +#define MCF_PSC_CR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008808))
42106 +#define MCF_PSC_RB2 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00880C))
42107 +#define MCF_PSC_TB2 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00880C))
42108 +#define MCF_PSC_TB_8BIT2 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00880C))
42109 +#define MCF_PSC_TB_16BIT2 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00880C))
42110 +#define MCF_PSC_TB_AC972 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00880C))
42111 +#define MCF_PSC_IPCR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008810))
42112 +#define MCF_PSC_ACR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008810))
42113 +#define MCF_PSC_ISR2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008814))
42114 +#define MCF_PSC_IMR2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008814))
42115 +#define MCF_PSC_CTUR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008818))
42116 +#define MCF_PSC_CTLR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00881C))
42117 +#define MCF_PSC_IP2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008834))
42118 +#define MCF_PSC_OPSET2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008838))
42119 +#define MCF_PSC_OPRESET2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00883C))
42120 +#define MCF_PSC_SICR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008840))
42121 +#define MCF_PSC_IRCR12 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008844))
42122 +#define MCF_PSC_IRCR22 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008848))
42123 +#define MCF_PSC_IRSDR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00884C))
42124 +#define MCF_PSC_IRMDR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008850))
42125 +#define MCF_PSC_IRFDR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008854))
42126 +#define MCF_PSC_RFCNT2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008858))
42127 +#define MCF_PSC_TFCNT2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00885C))
42128 +#define MCF_PSC_RFSR2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008864))
42129 +#define MCF_PSC_TFSR2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008884))
42130 +#define MCF_PSC_RFCR2 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008868))
42131 +#define MCF_PSC_TFCR2 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008888))
42132 +#define MCF_PSC_RFAR2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00886E))
42133 +#define MCF_PSC_TFAR2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00888E))
42134 +#define MCF_PSC_RFRP2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008872))
42135 +#define MCF_PSC_TFRP2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008892))
42136 +#define MCF_PSC_RFWP2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008876))
42137 +#define MCF_PSC_TFWP2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008896))
42138 +#define MCF_PSC_RLRFP2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00887A))
42139 +#define MCF_PSC_TLRFP2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00889A))
42140 +#define MCF_PSC_RLWFP2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00887E))
42141 +#define MCF_PSC_TLWFP2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00889E))
42142 +#define MCF_PSC_MR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008900))
42143 +#define MCF_PSC_SR3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008904))
42144 +#define MCF_PSC_CSR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008904))
42145 +#define MCF_PSC_CR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008908))
42146 +#define MCF_PSC_RB3 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00890C))
42147 +#define MCF_PSC_TB3 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00890C))
42148 +#define MCF_PSC_TB_8BIT3 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00890C))
42149 +#define MCF_PSC_TB_16BIT3 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00890C))
42150 +#define MCF_PSC_TB_AC973 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00890C))
42151 +#define MCF_PSC_IPCR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008910))
42152 +#define MCF_PSC_ACR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008910))
42153 +#define MCF_PSC_ISR3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008914))
42154 +#define MCF_PSC_IMR3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008914))
42155 +#define MCF_PSC_CTUR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008918))
42156 +#define MCF_PSC_CTLR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00891C))
42157 +#define MCF_PSC_IP3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008934))
42158 +#define MCF_PSC_OPSET3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008938))
42159 +#define MCF_PSC_OPRESET3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00893C))
42160 +#define MCF_PSC_SICR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008940))
42161 +#define MCF_PSC_IRCR13 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008944))
42162 +#define MCF_PSC_IRCR23 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008948))
42163 +#define MCF_PSC_IRSDR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00894C))
42164 +#define MCF_PSC_IRMDR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008950))
42165 +#define MCF_PSC_IRFDR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008954))
42166 +#define MCF_PSC_RFCNT3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008958))
42167 +#define MCF_PSC_TFCNT3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00895C))
42168 +#define MCF_PSC_RFSR3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008964))
42169 +#define MCF_PSC_TFSR3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008984))
42170 +#define MCF_PSC_RFCR3 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008968))
42171 +#define MCF_PSC_TFCR3 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008988))
42172 +#define MCF_PSC_RFAR3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00896E))
42173 +#define MCF_PSC_TFAR3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00898E))
42174 +#define MCF_PSC_RFRP3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008972))
42175 +#define MCF_PSC_TFRP3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008992))
42176 +#define MCF_PSC_RFWP3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008976))
42177 +#define MCF_PSC_TFWP3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008996))
42178 +#define MCF_PSC_RLRFP3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00897A))
42179 +#define MCF_PSC_TLRFP3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00899A))
42180 +#define MCF_PSC_RLWFP3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00897E))
42181 +#define MCF_PSC_TLWFP3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00899E))
42182 +#define MCF_PSC_MR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008600+((x)*0x100)))
42183 +#define MCF_PSC_SR(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008604+((x)*0x100)))
42184 +#define MCF_PSC_CSR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008604+((x)*0x100)))
42185 +#define MCF_PSC_CR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008608+((x)*0x100)))
42186 +#define MCF_PSC_RB(x) (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C+((x)*0x100)))
42187 +#define MCF_PSC_TB(x) (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C+((x)*0x100)))
42188 +#define MCF_PSC_TB_8BIT(x) (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C+((x)*0x100)))
42189 +#define MCF_PSC_TB_16BIT(x) (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C+((x)*0x100)))
42190 +#define MCF_PSC_TB_AC97(x) (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C+((x)*0x100)))
42191 +#define MCF_PSC_IPCR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008610+((x)*0x100)))
42192 +#define MCF_PSC_ACR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008610+((x)*0x100)))
42193 +#define MCF_PSC_ISR(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008614+((x)*0x100)))
42194 +#define MCF_PSC_IMR(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008614+((x)*0x100)))
42195 +#define MCF_PSC_CTUR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008618+((x)*0x100)))
42196 +#define MCF_PSC_CTLR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00861C+((x)*0x100)))
42197 +#define MCF_PSC_IP(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008634+((x)*0x100)))
42198 +#define MCF_PSC_OPSET(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008638+((x)*0x100)))
42199 +#define MCF_PSC_OPRESET(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00863C+((x)*0x100)))
42200 +#define MCF_PSC_SICR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008640+((x)*0x100)))
42201 +#define MCF_PSC_IRCR1(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008644+((x)*0x100)))
42202 +#define MCF_PSC_IRCR2(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008648+((x)*0x100)))
42203 +#define MCF_PSC_IRSDR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00864C+((x)*0x100)))
42204 +#define MCF_PSC_IRMDR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008650+((x)*0x100)))
42205 +#define MCF_PSC_IRFDR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008654+((x)*0x100)))
42206 +#define MCF_PSC_RFCNT(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008658+((x)*0x100)))
42207 +#define MCF_PSC_TFCNT(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00865C+((x)*0x100)))
42208 +#define MCF_PSC_RFSR(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008664+((x)*0x100)))
42209 +#define MCF_PSC_TFSR(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008684+((x)*0x100)))
42210 +#define MCF_PSC_RFCR(x) (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008668+((x)*0x100)))
42211 +#define MCF_PSC_TFCR(x) (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008688+((x)*0x100)))
42212 +#define MCF_PSC_RFAR(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + (0x00866E)+((x)*0x100)))
42213 +#define MCF_PSC_TFAR(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + (0x00868E)+((x)*0x100)))
42214 +#define MCF_PSC_RFRP(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008672+((x)*0x100)))
42215 +#define MCF_PSC_TFRP(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008692+((x)*0x100)))
42216 +#define MCF_PSC_RFWP(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008676+((x)*0x100)))
42217 +#define MCF_PSC_TFWP(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008696+((x)*0x100)))
42218 +#define MCF_PSC_RLRFP(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00867A+((x)*0x100)))
42219 +#define MCF_PSC_TLRFP(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00869A+((x)*0x100)))
42220 +#define MCF_PSC_RLWFP(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00867E+((x)*0x100)))
42221 +#define MCF_PSC_TLWFP(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00869E+((x)*0x100)))
42222 +
42223 +/* Bit definitions and macros for MCF_PSC_MR */
42224 +#define MCF_PSC_MR_BC(x) (((x)&0x03)<<0)
42225 +#define MCF_PSC_MR_PT (0x04)
42226 +#define MCF_PSC_MR_PM(x) (((x)&0x03)<<3)
42227 +#define MCF_PSC_MR_ERR (0x20)
42228 +#define MCF_PSC_MR_RXIRQ (0x40)
42229 +#define MCF_PSC_MR_RXRTS (0x80)
42230 +#define MCF_PSC_MR_SB(x) (((x)&0x0F)<<0)
42231 +#define MCF_PSC_MR_TXCTS (0x10)
42232 +#define MCF_PSC_MR_TXRTS (0x20)
42233 +#define MCF_PSC_MR_CM(x) (((x)&0x03)<<6)
42234 +#define MCF_PSC_MR_PM_MULTI_ADDR (0x1C)
42235 +#define MCF_PSC_MR_PM_MULTI_DATA (0x18)
42236 +#define MCF_PSC_MR_PM_NONE (0x10)
42237 +#define MCF_PSC_MR_PM_FORCE_HI (0x0C)
42238 +#define MCF_PSC_MR_PM_FORCE_LO (0x08)
42239 +#define MCF_PSC_MR_PM_ODD (0x04)
42240 +#define MCF_PSC_MR_PM_EVEN (0x00)
42241 +#define MCF_PSC_MR_BC_5 (0x00)
42242 +#define MCF_PSC_MR_BC_6 (0x01)
42243 +#define MCF_PSC_MR_BC_7 (0x02)
42244 +#define MCF_PSC_MR_BC_8 (0x03)
42245 +#define MCF_PSC_MR_CM_NORMAL (0x00)
42246 +#define MCF_PSC_MR_CM_ECHO (0x40)
42247 +#define MCF_PSC_MR_CM_LOCAL_LOOP (0x80)
42248 +#define MCF_PSC_MR_CM_REMOTE_LOOP (0xC0)
42249 +#define MCF_PSC_MR_SB_STOP_BITS_1 (0x07)
42250 +#define MCF_PSC_MR_SB_STOP_BITS_15 (0x08)
42251 +#define MCF_PSC_MR_SB_STOP_BITS_2 (0x0F)
42252 +
42253 +/* Bit definitions and macros for MCF_PSC_SR */
42254 +#define MCF_PSC_SR_ERR (0x0040)
42255 +#define MCF_PSC_SR_CDE_DEOF (0x0080)
42256 +#define MCF_PSC_SR_RXRDY (0x0100)
42257 +#define MCF_PSC_SR_FU (0x0200)
42258 +#define MCF_PSC_SR_TXRDY (0x0400)
42259 +#define MCF_PSC_SR_TXEMP_URERR (0x0800)
42260 +#define MCF_PSC_SR_OE (0x1000)
42261 +#define MCF_PSC_SR_PE_CRCERR (0x2000)
42262 +#define MCF_PSC_SR_FE_PHYERR (0x4000)
42263 +#define MCF_PSC_SR_RB_NEOF (0x8000)
42264 +
42265 +/* Bit definitions and macros for MCF_PSC_CSR */
42266 +#define MCF_PSC_CSR_TCSEL(x) (((x)&0x0F)<<0)
42267 +#define MCF_PSC_CSR_RCSEL(x) (((x)&0x0F)<<4)
42268 +#define MCF_PSC_CSR_RCSEL_SYS_CLK (0xD0)
42269 +#define MCF_PSC_CSR_RCSEL_CTM16 (0xE0)
42270 +#define MCF_PSC_CSR_RCSEL_CTM (0xF0)
42271 +#define MCF_PSC_CSR_TCSEL_SYS_CLK (0x0D)
42272 +#define MCF_PSC_CSR_TCSEL_CTM16 (0x0E)
42273 +#define MCF_PSC_CSR_TCSEL_CTM (0x0F)
42274 +
42275 +/* Bit definitions and macros for MCF_PSC_CR */
42276 +#define MCF_PSC_CR_RXC(x) (((x)&0x03)<<0)
42277 +#define MCF_PSC_CR_TXC(x) (((x)&0x03)<<2)
42278 +#define MCF_PSC_CR_MISC(x) (((x)&0x07)<<4)
42279 +#define MCF_PSC_CR_NONE (0x00)
42280 +#define MCF_PSC_CR_STOP_BREAK (0x70)
42281 +#define MCF_PSC_CR_START_BREAK (0x60)
42282 +#define MCF_PSC_CR_BKCHGINT (0x50)
42283 +#define MCF_PSC_CR_RESET_ERROR (0x40)
42284 +#define MCF_PSC_CR_RESET_TX (0x30)
42285 +#define MCF_PSC_CR_RESET_RX (0x20)
42286 +#define MCF_PSC_CR_RESET_MR (0x10)
42287 +#define MCF_PSC_CR_TX_DISABLED (0x08)
42288 +#define MCF_PSC_CR_TX_ENABLED (0x04)
42289 +#define MCF_PSC_CR_RX_DISABLED (0x02)
42290 +#define MCF_PSC_CR_RX_ENABLED (0x01)
42291 +
42292 +/* Bit definitions and macros for MCF_PSC_TB_8BIT */
42293 +#define MCF_PSC_TB_8BIT_TB3(x) (((x)&0x000000FF)<<0)
42294 +#define MCF_PSC_TB_8BIT_TB2(x) (((x)&0x000000FF)<<8)
42295 +#define MCF_PSC_TB_8BIT_TB1(x) (((x)&0x000000FF)<<16)
42296 +#define MCF_PSC_TB_8BIT_TB0(x) (((x)&0x000000FF)<<24)
42297 +
42298 +/* Bit definitions and macros for MCF_PSC_TB_16BIT */
42299 +#define MCF_PSC_TB_16BIT_TB1(x) (((x)&0x0000FFFF)<<0)
42300 +#define MCF_PSC_TB_16BIT_TB0(x) (((x)&0x0000FFFF)<<16)
42301 +
42302 +/* Bit definitions and macros for MCF_PSC_TB_AC97 */
42303 +#define MCF_PSC_TB_AC97_SOF (0x00000800)
42304 +#define MCF_PSC_TB_AC97_TB(x) (((x)&0x000FFFFF)<<12)
42305 +
42306 +/* Bit definitions and macros for MCF_PSC_IPCR */
42307 +#define MCF_PSC_IPCR_RESERVED (0x0C)
42308 +#define MCF_PSC_IPCR_CTS (0x0D)
42309 +#define MCF_PSC_IPCR_D_CTS (0x1C)
42310 +#define MCF_PSC_IPCR_SYNC (0x8C)
42311 +
42312 +/* Bit definitions and macros for MCF_PSC_ACR */
42313 +#define MCF_PSC_ACR_IEC0 (0x01)
42314 +#define MCF_PSC_ACR_CTMS(x) (((x)&0x07)<<4)
42315 +#define MCF_PSC_ACR_BRG (0x80)
42316 +
42317 +/* Bit definitions and macros for MCF_PSC_ISR */
42318 +#define MCF_PSC_ISR_ERR (0x0040)
42319 +#define MCF_PSC_ISR_DEOF (0x0080)
42320 +#define MCF_PSC_ISR_TXRDY (0x0100)
42321 +#define MCF_PSC_ISR_RXRDY_FU (0x0200)
42322 +#define MCF_PSC_ISR_DB (0x0400)
42323 +#define MCF_PSC_ISR_IPC (0x8000)
42324 +
42325 +/* Bit definitions and macros for MCF_PSC_IMR */
42326 +#define MCF_PSC_IMR_ERR (0x0040)
42327 +#define MCF_PSC_IMR_DEOF (0x0080)
42328 +#define MCF_PSC_IMR_TXRDY (0x0100)
42329 +#define MCF_PSC_IMR_RXRDY_FU (0x0200)
42330 +#define MCF_PSC_IMR_DB (0x0400)
42331 +#define MCF_PSC_IMR_IPC (0x8000)
42332 +
42333 +/* Bit definitions and macros for MCF_PSC_IP */
42334 +#define MCF_PSC_IP_CTS (0x01)
42335 +#define MCF_PSC_IP_TGL (0x40)
42336 +#define MCF_PSC_IP_LWPR_B (0x80)
42337 +
42338 +/* Bit definitions and macros for MCF_PSC_OPSET */
42339 +#define MCF_PSC_OPSET_RTS (0x01)
42340 +
42341 +/* Bit definitions and macros for MCF_PSC_OPRESET */
42342 +#define MCF_PSC_OPRESET_RTS (0x01)
42343 +
42344 +/* Bit definitions and macros for MCF_PSC_SICR */
42345 +#define MCF_PSC_SICR_SIM(x) (((x)&0x07)<<0)
42346 +#define MCF_PSC_SICR_SHDIR (0x10)
42347 +#define MCF_PSC_SICR_DTS (0x20)
42348 +#define MCF_PSC_SICR_AWR (0x40)
42349 +#define MCF_PSC_SICR_ACRB (0x80)
42350 +#define MCF_PSC_SICR_SIM_UART (0x00)
42351 +#define MCF_PSC_SICR_SIM_MODEM8 (0x01)
42352 +#define MCF_PSC_SICR_SIM_MODEM16 (0x02)
42353 +#define MCF_PSC_SICR_SIM_AC97 (0x03)
42354 +#define MCF_PSC_SICR_SIM_SIR (0x04)
42355 +#define MCF_PSC_SICR_SIM_MIR (0x05)
42356 +#define MCF_PSC_SICR_SIM_FIR (0x06)
42357 +
42358 +/* Bit definitions and macros for MCF_PSC_IRCR1 */
42359 +#define MCF_PSC_IRCR1_SPUL (0x01)
42360 +#define MCF_PSC_IRCR1_SIPEN (0x02)
42361 +#define MCF_PSC_IRCR1_FD (0x04)
42362 +
42363 +/* Bit definitions and macros for MCF_PSC_IRCR2 */
42364 +#define MCF_PSC_IRCR2_NXTEOF (0x01)
42365 +#define MCF_PSC_IRCR2_ABORT (0x02)
42366 +#define MCF_PSC_IRCR2_SIPREQ (0x04)
42367 +
42368 +/* Bit definitions and macros for MCF_PSC_IRMDR */
42369 +#define MCF_PSC_IRMDR_M_FDIV(x) (((x)&0x7F)<<0)
42370 +#define MCF_PSC_IRMDR_FREQ (0x80)
42371 +
42372 +/* Bit definitions and macros for MCF_PSC_IRFDR */
42373 +#define MCF_PSC_IRFDR_F_FDIV(x) (((x)&0x0F)<<0)
42374 +
42375 +/* Bit definitions and macros for MCF_PSC_RFCNT */
42376 +#define MCF_PSC_RFCNT_CNT(x) (((x)&0x01FF)<<0)
42377 +
42378 +/* Bit definitions and macros for MCF_PSC_TFCNT */
42379 +#define MCF_PSC_TFCNT_CNT(x) (((x)&0x01FF)<<0)
42380 +
42381 +/* Bit definitions and macros for MCF_PSC_RFSR */
42382 +#define MCF_PSC_RFSR_EMT (0x0001)
42383 +#define MCF_PSC_RFSR_ALARM (0x0002)
42384 +#define MCF_PSC_RFSR_FU (0x0004)
42385 +#define MCF_PSC_RFSR_FRMRY (0x0008)
42386 +#define MCF_PSC_RFSR_OF (0x0010)
42387 +#define MCF_PSC_RFSR_UF (0x0020)
42388 +#define MCF_PSC_RFSR_RXW (0x0040)
42389 +#define MCF_PSC_RFSR_FAE (0x0080)
42390 +#define MCF_PSC_RFSR_FRM(x) (((x)&0x000F)<<8)
42391 +#define MCF_PSC_RFSR_TAG (0x1000)
42392 +#define MCF_PSC_RFSR_TXW (0x4000)
42393 +#define MCF_PSC_RFSR_IP (0x8000)
42394 +#define MCF_PSC_RFSR_FRM_BYTE0 (0x0800)
42395 +#define MCF_PSC_RFSR_FRM_BYTE1 (0x0400)
42396 +#define MCF_PSC_RFSR_FRM_BYTE2 (0x0200)
42397 +#define MCF_PSC_RFSR_FRM_BYTE3 (0x0100)
42398 +
42399 +/* Bit definitions and macros for MCF_PSC_TFSR */
42400 +#define MCF_PSC_TFSR_EMT (0x0001)
42401 +#define MCF_PSC_TFSR_ALARM (0x0002)
42402 +#define MCF_PSC_TFSR_FU (0x0004)
42403 +#define MCF_PSC_TFSR_FRMRY (0x0008)
42404 +#define MCF_PSC_TFSR_OF (0x0010)
42405 +#define MCF_PSC_TFSR_UF (0x0020)
42406 +#define MCF_PSC_TFSR_RXW (0x0040)
42407 +#define MCF_PSC_TFSR_FAE (0x0080)
42408 +#define MCF_PSC_TFSR_FRM(x) (((x)&0x000F)<<8)
42409 +#define MCF_PSC_TFSR_TAG (0x1000)
42410 +#define MCF_PSC_TFSR_TXW (0x4000)
42411 +#define MCF_PSC_TFSR_IP (0x8000)
42412 +#define MCF_PSC_TFSR_FRM_BYTE0 (0x0800)
42413 +#define MCF_PSC_TFSR_FRM_BYTE1 (0x0400)
42414 +#define MCF_PSC_TFSR_FRM_BYTE2 (0x0200)
42415 +#define MCF_PSC_TFSR_FRM_BYTE3 (0x0100)
42416 +
42417 +/* Bit definitions and macros for MCF_PSC_RFCR */
42418 +#define MCF_PSC_RFCR_CNTR(x) (((x)&0x0000FFFF)<<0)
42419 +#define MCF_PSC_RFCR_TXW_MSK (0x00040000)
42420 +#define MCF_PSC_RFCR_OF_MSK (0x00080000)
42421 +#define MCF_PSC_RFCR_UF_MSK (0x00100000)
42422 +#define MCF_PSC_RFCR_RXW_MSK (0x00200000)
42423 +#define MCF_PSC_RFCR_FAE_MSK (0x00400000)
42424 +#define MCF_PSC_RFCR_IP_MSK (0x00800000)
42425 +#define MCF_PSC_RFCR_GR(x) (((x)&0x00000007)<<24)
42426 +#define MCF_PSC_RFCR_FRMEN (0x08000000)
42427 +#define MCF_PSC_RFCR_TIMER (0x10000000)
42428 +#define MCF_PSC_RFCR_WRITETAG (0x20000000)
42429 +#define MCF_PSC_RFCR_SHADOW (0x80000000)
42430 +
42431 +/* Bit definitions and macros for MCF_PSC_TFCR */
42432 +#define MCF_PSC_TFCR_CNTR(x) (((x)&0x0000FFFF)<<0)
42433 +#define MCF_PSC_TFCR_TXW_MSK (0x00040000)
42434 +#define MCF_PSC_TFCR_OF_MSK (0x00080000)
42435 +#define MCF_PSC_TFCR_UF_MSK (0x00100000)
42436 +#define MCF_PSC_TFCR_RXW_MSK (0x00200000)
42437 +#define MCF_PSC_TFCR_FAE_MSK (0x00400000)
42438 +#define MCF_PSC_TFCR_IP_MSK (0x00800000)
42439 +#define MCF_PSC_TFCR_GR(x) (((x)&0x00000007)<<24)
42440 +#define MCF_PSC_TFCR_FRMEN (0x08000000)
42441 +#define MCF_PSC_TFCR_TIMER (0x10000000)
42442 +#define MCF_PSC_TFCR_WRITETAG (0x20000000)
42443 +#define MCF_PSC_TFCR_SHADOW (0x80000000)
42444 +
42445 +/* Bit definitions and macros for MCF_PSC_RFAR */
42446 +#define MCF_PSC_RFAR_ALARM(x) (((x)&0x01FF)<<0)
42447 +
42448 +/* Bit definitions and macros for MCF_PSC_TFAR */
42449 +#define MCF_PSC_TFAR_ALARM(x) (((x)&0x01FF)<<0)
42450 +
42451 +/* Bit definitions and macros for MCF_PSC_RFRP */
42452 +#define MCF_PSC_RFRP_READ(x) (((x)&0x01FF)<<0)
42453 +
42454 +/* Bit definitions and macros for MCF_PSC_TFRP */
42455 +#define MCF_PSC_TFRP_READ(x) (((x)&0x01FF)<<0)
42456 +
42457 +/* Bit definitions and macros for MCF_PSC_RFWP */
42458 +#define MCF_PSC_RFWP_WRITE(x) (((x)&0x01FF)<<0)
42459 +
42460 +/* Bit definitions and macros for MCF_PSC_TFWP */
42461 +#define MCF_PSC_TFWP_WRITE(x) (((x)&0x01FF)<<0)
42462 +
42463 +/* Bit definitions and macros for MCF_PSC_RLRFP */
42464 +#define MCF_PSC_RLRFP_LFP(x) (((x)&0x01FF)<<0)
42465 +
42466 +/* Bit definitions and macros for MCF_PSC_TLRFP */
42467 +#define MCF_PSC_TLRFP_LFP(x) (((x)&0x01FF)<<0)
42468 +
42469 +/* Bit definitions and macros for MCF_PSC_RLWFP */
42470 +#define MCF_PSC_RLWFP_LFP(x) (((x)&0x01FF)<<0)
42471 +
42472 +/* Bit definitions and macros for MCF_PSC_TLWFP */
42473 +#define MCF_PSC_TLWFP_LFP(x) (((x)&0x01FF)<<0)
42474 +
42475 +/********************************************************************/
42476 +
42477 +#endif /* __MCF548X_PSC_H__ */
42478 --- /dev/null
42479 +++ b/include/asm-m68k/m5485sim.h
42480 @@ -0,0 +1,221 @@
42481 +/*
42482 + * m5485sim.h -- ColdFire 547x/548x System Integration Unit support.
42483 + */
42484 +
42485 +#ifndef m5485sim_h
42486 +#define m5485sim_h
42487 +
42488 +
42489 +/*
42490 + * System Integration Unit Registers
42491 + */
42492 +#define MCF_SDRAMDS MCF_REG32(0x000004) /* SDRAM Drive Strength */
42493 +#define MCF_SBCR MCF_REG32(0x000010) /* System Breakpoint Control */
42494 +#define MCF_CSnCFG(x) MCF_REG32(0x000020+(x*4))/* SDRAM Chip Select X */
42495 +#define MCF_SECSACR MCF_REG32(0x000038) /* Sequential Access Control */
42496 +#define MCF_RSR MCF_REG32(0x000044) /* Reset Status */
42497 +#define MCF_JTAGID MCF_REG32(0x000050) /* JTAG Device Identification */
42498 +
42499 +/*
42500 + * FlexBus Chip Selects Registers
42501 + */
42502 +#define MCF_CSARn(x) MCF_REG32(0x000500+(x*0xC))
42503 +#define MCF_CSMRn(x) MCF_REG32(0x000504+(x*0xC))
42504 +#define MCF_CSCRn(x) MCF_REG32(0x000508+(x*0xC))
42505 +
42506 +/*
42507 + * Interrupt Controller Registers
42508 + */
42509 +#define MCF_IPRH MCF_REG32(0x000700)
42510 +#define MCF_IPRL MCF_REG32(0x000704)
42511 +#define MCF_IMRH MCF_REG32(0x000708)
42512 +#define MCF_IMRL MCF_REG32(0x00070C)
42513 +#define MCF_INTFRCH MCF_REG32(0x000710)
42514 +#define MCF_INTFRCL MCF_REG32(0x000714)
42515 +#define MCF_IRLR MCF_REG08(0x000718)
42516 +#define MCF_IACKLPR MCF_REG08(0x000719)
42517 +#define MCF_SWIACK MCF_REG08(0x0007E0)
42518 +#define MCF_LnIACK(x) MCF_REG08(0x0007E4+((x)*0x004))
42519 +#define MCF_ICR(x) MCF_REG08(0x000740+((x)*0x001))
42520 +
42521 +/*
42522 + * Slice Timers Registers
42523 + */
42524 +#define MCF_SLTCNT(x) MCF_REG32(0x000900+((x)*0x010))
42525 +#define MCF_SCR(x) MCF_REG32(0x000904+((x)*0x010))
42526 +#define MCF_SCNT(x) MCF_REG32(0x000908+((x)*0x010))
42527 +#define MCF_SSR(x) MCF_REG32(0x00090C+((x)*0x010))
42528 +
42529 +/*
42530 + * Interrupt sources
42531 + */
42532 +#define ISC_EPORT_Fn(x) (x) /* EPORT Interrupts */
42533 +#define ISC_USB_EPn(x) (15+(x)) /* USB Endopint */
42534 +#define ISC_USB_ISR (22) /* USB General source */
42535 +#define ISC_USB_AISR (22) /* USB core source */
42536 +#define ISC_DSPI_OVRFW (25) /* DSPI overflow */
42537 +#define ISC_DSPI_RFOF (26)
42538 +#define ISC_DSPI_RFDF (27)
42539 +#define ISC_DSPI_TFUF (28)
42540 +#define ISC_DSPI_TCF (29)
42541 +#define ISC_DSPI_TFFF (30)
42542 +#define ISC_DSPI_EOQF (31)
42543 +#define ISC_PSCn(x) (35-(x))
42544 +#define ISC_COMM_TIM (36)
42545 +#define ISC_SEC (37)
42546 +#define ISC_FEC1 (38)
42547 +#define ISC_FEC0 (39)
42548 +#define ISC_I2C (40)
42549 +#define ISC_PCI_ARB (41)
42550 +#define ISC_PCI_CB (42)
42551 +#define ISC_PCI_XLB (43)
42552 +#define ISC_DMA (48)
42553 +#define ISC_CANn_ERR(x) (49+(6*(x)))
42554 +#define ISC_CANn_BUSOFF(x) (50+(6*(x)))
42555 +#define ISC_CANn_MBOR(x) (51+(6*(x)))
42556 +#define ISC_CAN0_WAKEIN (52)
42557 +#define ISC_SLTn(x) (54-(x))
42558 +#define ISC_GPTn(x) (62-(x))
42559 +
42560 +/*
42561 + * Interrupt level and priorities
42562 + */
42563 +#define ILP_TOP (MCF_ICR_IL(5) | MCF_ICR_IP(3))
42564 +#define ILP_SLT0 (MCF_ICR_IL(5) | MCF_ICR_IP(2))
42565 +#define ILP_SLT1 (MCF_ICR_IL(5) | MCF_ICR_IP(1))
42566 +#define ILP_DMA (MCF_ICR_IL(5) | MCF_ICR_IP(0))
42567 +#define ILP_SEC (MCF_ICR_IL(4) | MCF_ICR_IP(7))
42568 +#define ILP_FEC0 (MCF_ICR_IL(4) | MCF_ICR_IP(6))
42569 +#define ILP_FEC1 (MCF_ICR_IL(4) | MCF_ICR_IP(5))
42570 +#define ILP_PCI_XLB (MCF_ICR_IL(4) | MCF_ICR_IP(4))
42571 +#define ILP_PCI_ARB (MCF_ICR_IL(4) | MCF_ICR_IP(3))
42572 +#define ILP_PCI_CB (MCF_ICR_IL(4) | MCF_ICR_IP(2))
42573 +#define ILP_I2C (MCF_ICR_IL(4) | MCF_ICR_IP(1))
42574 +
42575 +#define ILP_USB_EPn(x) (MCF_ICR_IL(3) | MCF_ICR_IP(7-(x)))
42576 +#define ILP_USB_EP0 (MCF_ICR_IL(3) | MCF_ICR_IP(7))
42577 +#define ILP_USB_EP1 (MCF_ICR_IL(3) | MCF_ICR_IP(6))
42578 +#define ILP_USB_EP2 (MCF_ICR_IL(3) | MCF_ICR_IP(5))
42579 +#define ILP_USB_EP3 (MCF_ICR_IL(3) | MCF_ICR_IP(4))
42580 +#define ILP_USB_EP4 (MCF_ICR_IL(3) | MCF_ICR_IP(3))
42581 +#define ILP_USB_EP5 (MCF_ICR_IL(3) | MCF_ICR_IP(2))
42582 +#define ILP_USB_EP6 (MCF_ICR_IL(3) | MCF_ICR_IP(1))
42583 +#define ILP_USB_ISR (MCF_ICR_IL(3) | MCF_ICR_IP(0))
42584 +
42585 +#define ILP_USB_AISR (MCF_ICR_IL(2) | MCF_ICR_IP(7))
42586 +#define ILP_DSPI_OVRFW (MCF_ICR_IL(2) | MCF_ICR_IP(6))
42587 +#define ILP_DSPI_RFOF (MCF_ICR_IL(2) | MCF_ICR_IP(5))
42588 +#define ILP_DSPI_RFDF (MCF_ICR_IL(2) | MCF_ICR_IP(4))
42589 +#define ILP_DSPI_TFUF (MCF_ICR_IL(2) | MCF_ICR_IP(3))
42590 +#define ILP_DSPI_TCF (MCF_ICR_IL(2) | MCF_ICR_IP(2))
42591 +#define ILP_DSPI_TFFF (MCF_ICR_IL(2) | MCF_ICR_IP(1))
42592 +#define ILP_DSPI_EOQF (MCF_ICR_IL(2) | MCF_ICR_IP(0))
42593 +
42594 +#define ILP_COMM_TIM (MCF_ICR_IL(1) | MCF_ICR_IP(7))
42595 +#define ILP_PSCn(x) (MCF_ICR_IL(1) | MCF_ICR_IP(3-((x)&3)))
42596 +#define ILP_PSC0 (MCF_ICR_IL(1) | MCF_ICR_IP(3))
42597 +#define ILP_PSC1 (MCF_ICR_IL(1) | MCF_ICR_IP(2))
42598 +#define ILP_PSC2 (MCF_ICR_IL(1) | MCF_ICR_IP(1))
42599 +#define ILP_PSC3 (MCF_ICR_IL(1) | MCF_ICR_IP(0))
42600 +
42601 +
42602 +
42603 +
42604 +
42605 +/********************************************************************/
42606 +
42607 +/*
42608 + * System Integration Unit Bitfields
42609 + */
42610 +
42611 +/* SBCR */
42612 +#define MCF_SBCR_PIN2DSPI (0x08000000)
42613 +#define MCF_SBCR_DMA2CPU (0x10000000)
42614 +#define MCF_SBCR_CPU2DMA (0x20000000)
42615 +#define MCF_SBCR_PIN2DMA (0x40000000)
42616 +#define MCF_SBCR_PIN2CPU (0x80000000)
42617 +
42618 +/* SECSACR */
42619 +#define MCF_SECSACR_SEQEN (0x00000001)
42620 +
42621 +/* RSR */
42622 +#define MCF_RSR_RST (0x00000001)
42623 +#define MCF_RSR_RSTWD (0x00000002)
42624 +#define MCF_RSR_RSTJTG (0x00000008)
42625 +
42626 +/* JTAGID */
42627 +#define MCF_JTAGID_REV (0xF0000000)
42628 +#define MCF_JTAGID_PROCESSOR (0x0FFFFFFF)
42629 +#define MCF_JTAGID_MCF5485 (0x0800C01D)
42630 +#define MCF_JTAGID_MCF5484 (0x0800D01D)
42631 +#define MCF_JTAGID_MCF5483 (0x0800E01D)
42632 +#define MCF_JTAGID_MCF5482 (0x0800F01D)
42633 +#define MCF_JTAGID_MCF5481 (0x0801001D)
42634 +#define MCF_JTAGID_MCF5480 (0x0801101D)
42635 +#define MCF_JTAGID_MCF5475 (0x0801201D)
42636 +#define MCF_JTAGID_MCF5474 (0x0801301D)
42637 +#define MCF_JTAGID_MCF5473 (0x0801401D)
42638 +#define MCF_JTAGID_MCF5472 (0x0801501D)
42639 +#define MCF_JTAGID_MCF5471 (0x0801601D)
42640 +#define MCF_JTAGID_MCF5470 (0x0801701D)
42641 +
42642 +
42643 +/*
42644 + * Interrupt Controller Bitfields
42645 + */
42646 +#define MCF_IRLR_IRQ(x) (((x)&0x7F)<<1)
42647 +#define MCF_IACKLPR_PRI(x) (((x)&0x0F)<<0)
42648 +#define MCF_IACKLPR_LEVEL(x) (((x)&0x07)<<4)
42649 +#define MCF_ICR_IP(x) (((x)&0x07)<<0)
42650 +#define MCF_ICR_IL(x) (((x)&0x07)<<3)
42651 +
42652 +/*
42653 + * Slice Timers Bitfields
42654 + */
42655 +#define MCF_SCR_TEN (0x01000000)
42656 +#define MCF_SCR_IEN (0x02000000)
42657 +#define MCF_SCR_RUN (0x04000000)
42658 +#define MCF_SSR_ST (0x01000000)
42659 +#define MCF_SSR_BE (0x02000000)
42660 +
42661 +
42662 +/*
42663 + * Some needed coldfire registers
42664 + */
42665 +#define MCF_PAR_PCIBG MCF_REG16(0x000A48)
42666 +#define MCF_PAR_PCIBR MCF_REG16(0x000A4A)
42667 +#define MCF_PAR_PSCn(x) MCF_REG08(0x000A4F-((x)&0x3))
42668 +#define MCF_PAR_FECI2CIRQ MCF_REG16(0x000A44)
42669 +#define MCF_PAR_DSPI MCF_REG16(0x000A50)
42670 +#define MCF_PAR_TIMER MCF_REG08(0X000A52)
42671 +#define MCF_EPPAR MCF_REG16(0x000F00)
42672 +#define MCF_EPIER MCF_REG08(0x000F05)
42673 +#define MCF_EPFR MCF_REG08(0x000F0C)
42674 +
42675 +/*
42676 + * Some GPIO bitfields
42677 + */
42678 +#define MCF_PAR_SDA (0x0008)
42679 +#define MCF_PAR_SCL (0x0004)
42680 +#define MCF_PAR_PSC_TXD (0x04)
42681 +#define MCF_PAR_PSC_RXD (0x08)
42682 +#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4)
42683 +#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6)
42684 +#define MCF_PAR_PSC_CTS_GPIO (0x00)
42685 +#define MCF_PAR_PSC_CTS_BCLK (0x80)
42686 +#define MCF_PAR_PSC_CTS_CTS (0xC0)
42687 +#define MCF_PAR_PSC_RTS_GPIO (0x00)
42688 +#define MCF_PAR_PSC_RTS_FSYNC (0x20)
42689 +#define MCF_PAR_PSC_RTS_RTS (0x30)
42690 +#define MCF_PAR_PSC_CANRX (0x40)
42691 +
42692 +
42693 +/*
42694 + * Some used coldfire values
42695 + */
42696 +#define MCF_EPIER_EPIE(x) (0x01 << (x))
42697 +#define MCF_EPPAR_EPPAx_FALLING (2)
42698 +#define MCF_EPPAR_EPPA(n,x) (((x)&0x0003) << (2*n))
42699 +
42700 +
42701 +#endif /* m5485sim_h */
42702 --- /dev/null
42703 +++ b/include/asm-m68k/m5485sram.h
42704 @@ -0,0 +1,12 @@
42705 +#ifndef SYS_SRAM_H
42706 +#define SYS_SRAM_H
42707 +
42708 +
42709 +#define SYS_SRAM_DMA_START MCF_MBAR + 0x10000
42710 +#define SYS_SRAM_DMA_SIZE 8192
42711 +#define SYS_SRAM_FEC_START SYS_SRAM_DMA_START + SYS_SRAM_DMA_SIZE
42712 +#define SYS_SRAM_FEC_SIZE 2048
42713 +#define SYS_SRAM_SEC_START SYS_SRAM_FEC_START + SYS_SRAM_FEC_SIZE
42714 +#define SYS_SRAM_SEC_SIZE 1280
42715 +
42716 +#endif /* SYS_SRAM_H */
42717 --- a/include/asm-m68k/machdep.h
42718 +++ b/include/asm-m68k/machdep.h
42719 @@ -32,4 +32,11 @@ extern void (*mach_heartbeat) (int);
42720 extern void (*mach_l2_flush) (int);
42721 extern void (*mach_beep) (unsigned int, unsigned int);
42722
42723 +#ifdef CONFIG_COLDFIRE
42724 +extern void __init config_coldfire(void);
42725 +extern void __init mmu_context_init(void);
42726 +extern irq_handler_t mach_default_handler;
42727 +extern void (*mach_tick)(void);
42728 +#endif
42729 +
42730 #endif /* _M68K_MACHDEP_H */
42731 --- /dev/null
42732 +++ b/include/asm-m68k/MCD_dma.h
42733 @@ -0,0 +1,408 @@
42734 +/*********************************************************************
42735 + *
42736 + * Copyright (C) 2004 Motorola, Inc.
42737 + * MOTOROLA, INC. All Rights Reserved.
42738 + * You are hereby granted a copyright license to use
42739 + * the SOFTWARE so long as this entire notice is
42740 + * retained without alteration in any modified and/or redistributed
42741 + * versions, and that such modified versions are clearly identified
42742 + * as such. No licenses are granted by implication, estoppel or
42743 + * otherwise under any patents or trademarks of Motorola, Inc. This
42744 + * software is provided on an "AS IS" basis and without warranty.
42745 + *
42746 + * To the maximum extent permitted by applicable law, MOTOROLA
42747 + * DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING
42748 + * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
42749 + * PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE
42750 + * SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY
42751 + * ACCOMPANYING WRITTEN MATERIALS.
42752 + *
42753 + * To the maximum extent permitted by applicable law, IN NO EVENT
42754 + * SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING
42755 + * WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS
42756 + * INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
42757 + * LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
42758 + *
42759 + * Motorola assumes no responsibility for the maintenance and support
42760 + * of this software
42761 + ********************************************************************/
42762 +
42763 +/*
42764 + * File: MCD_dma.h
42765 + * Purpose: Main header file for multi-channel DMA API.
42766 + *
42767 + * Notes:
42768 + *
42769 + * Modifications:
42770 + */
42771 +#ifndef _MCD_API_H
42772 +#define _MCD_API_H
42773 +
42774 +#include <asm/types.h>
42775 +
42776 +/*
42777 + * Turn Execution Unit tasks ON (#define) or OFF (#undef)
42778 + */
42779 +#undef MCD_INCLUDE_EU
42780 +
42781 +/*
42782 + * Number of DMA channels
42783 + */
42784 +#define NCHANNELS 16
42785 +
42786 +/*
42787 + * Total number of variants
42788 + */
42789 +#ifdef MCD_INCLUDE_EU
42790 +#define NUMOFVARIANTS 6
42791 +#else
42792 +#define NUMOFVARIANTS 4
42793 +#endif
42794 +
42795 +/*
42796 + * Define sizes of the various tables
42797 + */
42798 +#define TASK_TABLE_SIZE (NCHANNELS*32)
42799 +#define VAR_TAB_SIZE (128)
42800 +#define CONTEXT_SAVE_SIZE (128)
42801 +#define FUNCDESC_TAB_SIZE (256)
42802 +
42803 +#ifdef MCD_INCLUDE_EU
42804 +#define FUNCDESC_TAB_NUM 16
42805 +#else
42806 +#define FUNCDESC_TAB_NUM 1
42807 +#endif
42808 +
42809 +
42810 +#ifndef DEFINESONLY
42811 +
42812 +/*
42813 + * Portability typedefs
42814 + */
42815 + /*
42816 +#ifndef s32
42817 +typedef int s32;
42818 +#endif
42819 +#ifndef u32
42820 +typedef unsigned int u32;
42821 +#endif
42822 +#ifndef s16
42823 +typedef short s16;
42824 +#endif
42825 +#ifndef u16
42826 +typedef unsigned short u16;
42827 +#endif
42828 +#ifndef s8
42829 +typedef char s8;
42830 +#endif
42831 +#ifndef u8
42832 +typedef unsigned char u8;
42833 +#endif
42834 +*/
42835 +/*
42836 + * These structures represent the internal registers of the
42837 + * multi-channel DMA
42838 + */
42839 +struct dmaRegs_s {
42840 + u32 taskbar; /* task table base address register */
42841 + u32 currPtr;
42842 + u32 endPtr;
42843 + u32 varTablePtr;
42844 + u16 dma_rsvd0;
42845 + u16 ptdControl; /* ptd control */
42846 + u32 intPending; /* interrupt pending register */
42847 + u32 intMask; /* interrupt mask register */
42848 + u16 taskControl[16]; /* task control registers */
42849 + u8 priority[32]; /* priority registers */
42850 + u32 initiatorMux; /* initiator mux control */
42851 + u32 taskSize0; /* task size control register 0. */
42852 + u32 taskSize1; /* task size control register 1. */
42853 + u32 dma_rsvd1; /* reserved */
42854 + u32 dma_rsvd2; /* reserved */
42855 + u32 debugComp1; /* debug comparator 1 */
42856 + u32 debugComp2; /* debug comparator 2 */
42857 + u32 debugControl; /* debug control */
42858 + u32 debugStatus; /* debug status */
42859 + u32 ptdDebug; /* priority task decode debug */
42860 + u32 dma_rsvd3[31]; /* reserved */
42861 +};
42862 +typedef volatile struct dmaRegs_s dmaRegs;
42863 +
42864 +#endif
42865 +
42866 +/*
42867 + * PTD contrl reg bits
42868 + */
42869 +#define PTD_CTL_TSK_PRI 0x8000
42870 +#define PTD_CTL_COMM_PREFETCH 0x0001
42871 +
42872 +/*
42873 + * Task Control reg bits and field masks
42874 + */
42875 +#define TASK_CTL_EN 0x8000
42876 +#define TASK_CTL_VALID 0x4000
42877 +#define TASK_CTL_ALWAYS 0x2000
42878 +#define TASK_CTL_INIT_MASK 0x1f00
42879 +#define TASK_CTL_ASTRT 0x0080
42880 +#define TASK_CTL_HIPRITSKEN 0x0040
42881 +#define TASK_CTL_HLDINITNUM 0x0020
42882 +#define TASK_CTL_ASTSKNUM_MASK 0x000f
42883 +
42884 +/*
42885 + * Priority reg bits and field masks
42886 + */
42887 +#define PRIORITY_HLD 0x80
42888 +#define PRIORITY_PRI_MASK 0x07
42889 +
42890 +/*
42891 + * Debug Control reg bits and field masks
42892 + */
42893 +#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000
42894 +#define DBG_CTL_AUTO_ARM 0x00008000
42895 +#define DBG_CTL_BREAK 0x00004000
42896 +#define DBG_CTL_COMP1_TYP_MASK 0x00003800
42897 +#define DBG_CTL_COMP2_TYP_MASK 0x00000070
42898 +#define DBG_CTL_EXT_BREAK 0x00000004
42899 +#define DBG_CTL_INT_BREAK 0x00000002
42900 +
42901 +/*
42902 + * PTD Debug reg selector addresses
42903 + * This reg must be written with a value to show the contents of
42904 + * one of the desired internal register.
42905 + */
42906 +#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */
42907 +#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and
42908 + have initiators asserted */
42909 +
42910 +
42911 +/*
42912 + * General return values
42913 + */
42914 +#define MCD_OK 0
42915 +#define MCD_ERROR -1
42916 +#define MCD_TABLE_UNALIGNED -2
42917 +#define MCD_CHANNEL_INVALID -3
42918 +
42919 +/*
42920 + * MCD_initDma input flags
42921 + */
42922 +#define MCD_RELOC_TASKS 0x00000001
42923 +#define MCD_NO_RELOC_TASKS 0x00000000
42924 +#define MCD_COMM_PREFETCH_EN 0x00000002 /* Commbus Prefetching - MCF547x/548x ONLY */
42925 +
42926 +/*
42927 + * MCD_dmaStatus Status Values for each channel
42928 + */
42929 +#define MCD_NO_DMA 1 /* No DMA has been requested since reset */
42930 +#define MCD_IDLE 2 /* DMA active, but the initiator is currently inactive */
42931 +#define MCD_RUNNING 3 /* DMA active, and the initiator is currently active */
42932 +#define MCD_PAUSED 4 /* DMA active but it is currently paused */
42933 +#define MCD_HALTED 5 /* the most recent DMA has been killed with MCD_killTask() */
42934 +#define MCD_DONE 6 /* the most recent DMA has completed. */
42935 +
42936 +
42937 +/*
42938 + * MCD_startDma parameter defines
42939 + */
42940 +
42941 +/*
42942 + * Constants for the funcDesc parameter
42943 + */
42944 +/* Byte swapping: */
42945 +#define MCD_NO_BYTE_SWAP 0x00045670 /* to disable byte swapping. */
42946 +#define MCD_BYTE_REVERSE 0x00076540 /* to reverse the bytes of each u32 of the DMAed data. */
42947 +#define MCD_U16_REVERSE 0x00067450 /* to reverse the 16-bit halves of
42948 + each 32-bit data value being DMAed.*/
42949 +#define MCD_U16_BYTE_REVERSE 0x00054760 /* to reverse the byte halves of each
42950 + 16-bit half of each 32-bit data value DMAed */
42951 +#define MCD_NO_BIT_REV 0x00000000 /* do not reverse the bits of each byte DMAed. */
42952 +#define MCD_BIT_REV 0x00088880 /* reverse the bits of each byte DMAed */
42953 +/* CRCing: */
42954 +#define MCD_CRC16 0xc0100000 /* to perform CRC-16 on DMAed data. */
42955 +#define MCD_CRCCCITT 0xc0200000 /* to perform CRC-CCITT on DMAed data. */
42956 +#define MCD_CRC32 0xc0300000 /* to perform CRC-32 on DMAed data. */
42957 +#define MCD_CSUMINET 0xc0400000 /* to perform internet checksums on DMAed data.*/
42958 +#define MCD_NO_CSUM 0xa0000000 /* to perform no checksumming. */
42959 +
42960 +#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | MCD_NO_CSUM)
42961 +#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
42962 +
42963 +/*
42964 + * Constants for the flags parameter
42965 + */
42966 +#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */
42967 +#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */
42968 +#define MCD_TT_FLAGS_SP 0x00000004 /* Speculative prefetch(XLB) MCF547x/548x ONLY */
42969 +#define MCD_TT_FLAGS_MASK 0x000000ff
42970 +#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
42971 +
42972 +#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */
42973 +#define MCD_CHAIN_DMA /* TBD */
42974 +#define MCD_EU_DMA /* TBD */
42975 +#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */
42976 +#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */
42977 +
42978 +
42979 +/* these flags are valid for MCD_startDma and the chained buffer descriptors */
42980 +#define MCD_BUF_READY 0x80000000 /* indicates that this buffer is now under the DMA's control */
42981 +#define MCD_WRAP 0x20000000 /* to tell the FEC Dmas to wrap to the first BD */
42982 +#define MCD_INTERRUPT 0x10000000 /* to generate an interrupt after completion of the DMA. */
42983 +#define MCD_END_FRAME 0x08000000 /* tell the DMA to end the frame when transferring
42984 + last byte of data in buffer */
42985 +#define MCD_CRC_RESTART 0x40000000 /* to empty out the accumulated checksum
42986 + prior to performing the DMA. */
42987 +
42988 +/* Defines for the FEC buffer descriptor control/status word*/
42989 +#define MCD_FEC_BUF_READY 0x8000
42990 +#define MCD_FEC_WRAP 0x2000
42991 +#define MCD_FEC_INTERRUPT 0x1000
42992 +#define MCD_FEC_END_FRAME 0x0800
42993 +
42994 +
42995 +/*
42996 + * Defines for general intuitiveness
42997 + */
42998 +
42999 +#define MCD_TRUE 1
43000 +#define MCD_FALSE 0
43001 +
43002 +/*
43003 + * Three different cases for destination and source.
43004 + */
43005 +#define MINUS1 -1
43006 +#define ZERO 0
43007 +#define PLUS1 1
43008 +
43009 +#ifndef DEFINESONLY
43010 +
43011 +/* Task Table Entry struct*/
43012 +typedef struct {
43013 + u32 TDTstart; /* task descriptor table start */
43014 + u32 TDTend; /* task descriptor table end */
43015 + u32 varTab; /* variable table start */
43016 + u32 FDTandFlags; /* function descriptor table start and flags */
43017 + volatile u32 descAddrAndStatus;
43018 + volatile u32 modifiedVarTab;
43019 + u32 contextSaveSpace; /* context save space start */
43020 + u32 literalBases;
43021 +} TaskTableEntry;
43022 +
43023 +
43024 +/* Chained buffer descriptor */
43025 +typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
43026 +struct MCD_bufDesc_struct {
43027 + u32 flags; /* flags describing the DMA */
43028 + u32 csumResult; /* checksum from checksumming performed since last checksum reset */
43029 + s8 *srcAddr; /* the address to move data from */
43030 + s8 *destAddr; /* the address to move data to */
43031 + s8 *lastDestAddr; /* the last address written to */
43032 + u32 dmaSize; /* the number of bytes to transfer independent of the transfer size */
43033 + MCD_bufDesc *next; /* next buffer descriptor in chain */
43034 + u32 info; /* private information about this descriptor; DMA does not affect it */
43035 +};
43036 +
43037 +/* Progress Query struct */
43038 +typedef volatile struct MCD_XferProg_struct {
43039 + s8 *lastSrcAddr; /* the most-recent or last, post-increment source address */
43040 + s8 *lastDestAddr; /* the most-recent or last, post-increment destination address */
43041 + u32 dmaSize; /* the amount of data transferred for the current buffer */
43042 + MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */
43043 +} MCD_XferProg;
43044 +
43045 +
43046 +/* FEC buffer descriptor */
43047 +typedef volatile struct MCD_bufDescFec_struct {
43048 + u16 statCtrl;
43049 + u16 length;
43050 + u32 dataPointer;
43051 +} MCD_bufDescFec;
43052 +
43053 +
43054 +/*************************************************************************/
43055 +/*
43056 + * API function Prototypes - see MCD_dmaApi.c for further notes
43057 + */
43058 +
43059 +/*
43060 + * MCD_startDma starts a particular kind of DMA .
43061 + */
43062 +int MCD_startDma (
43063 + int channel, /* the channel on which to run the DMA */
43064 + s8 *srcAddr, /* the address to move data from, or buffer-descriptor address */
43065 + s16 srcIncr, /* the amount to increment the source address per transfer */
43066 + s8 *destAddr, /* the address to move data to */
43067 + s16 destIncr, /* the amount to increment the destination address per transfer */
43068 + u32 dmaSize, /* the number of bytes to transfer independent of the transfer size */
43069 + u32 xferSize, /* the number bytes in of each data movement (1, 2, or 4) */
43070 + u32 initiator, /* what device initiates the DMA */
43071 + int priority, /* priority of the DMA */
43072 + u32 flags, /* flags describing the DMA */
43073 + u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */
43074 +);
43075 +
43076 +/*
43077 + * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
43078 + * registers, relocating and creating the appropriate task structures, and
43079 + * setting up some global settings
43080 + */
43081 +int MCD_initDma (dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags);
43082 +
43083 +/*
43084 + * MCD_dmaStatus() returns the status of the DMA on the requested channel.
43085 + */
43086 +int MCD_dmaStatus (int channel);
43087 +
43088 +/*
43089 + * MCD_XferProgrQuery() returns progress of DMA on requested channel
43090 + */
43091 +int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep);
43092 +
43093 +/*
43094 + * MCD_killDma() halts the DMA on the requested channel, without any
43095 + * intention of resuming the DMA.
43096 + */
43097 +int MCD_killDma (int channel);
43098 +
43099 +/*
43100 + * MCD_continDma() continues a DMA which as stopped due to encountering an
43101 + * unready buffer descriptor.
43102 + */
43103 +int MCD_continDma (int channel);
43104 +
43105 +/*
43106 + * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
43107 + * running on that channel).
43108 + */
43109 +int MCD_pauseDma (int channel);
43110 +
43111 +/*
43112 + * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
43113 + * running on that channel).
43114 + */
43115 +int MCD_resumeDma (int channel);
43116 +
43117 +/*
43118 + * MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA
43119 + */
43120 +int MCD_csumQuery (int channel, u32 *csum);
43121 +
43122 +/*
43123 + * MCD_getCodeSize provides the packed size required by the microcoded task
43124 + * and structures.
43125 + */
43126 +int MCD_getCodeSize(void);
43127 +
43128 +/*
43129 + * MCD_getVersion provides a pointer to a version string and returns a
43130 + * version number.
43131 + */
43132 +int MCD_getVersion(char **longVersion);
43133 +
43134 +/* macro for setting a location in the variable table */
43135 +#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value
43136 + /* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
43137 + so I'm avoiding surrounding it with "do {} while(0)" */
43138 +
43139 +#endif /* DEFINESONLY */
43140 +
43141 +#endif /* _MCD_API_H */
43142 --- /dev/null
43143 +++ b/include/asm-m68k/mcf5445x_ccm.h
43144 @@ -0,0 +1,163 @@
43145 +/*
43146 + * Matt Waddel Matt.Waddel@freescale.com
43147 + *
43148 + * Copyright Freescale Semiconductor, Inc. 2007
43149 + *
43150 + * This program is free software; you can redistribute it and/or modify it
43151 + * under the terms of the GNU General Public License as published by the
43152 + * Free Software Foundation; either version 2 of the License, or (at your
43153 + * option) any later version.
43154 + */
43155 +
43156 +#ifndef __MCF5445X_CCM_H__
43157 +#define __MCF5445X_CCM_H__
43158 +
43159 +/*********************************************************************
43160 +*
43161 +* Chip Configuration Module (CCM)
43162 +*
43163 +*********************************************************************/
43164 +
43165 +/* Register read/write macros */
43166 +#define MCF_CCM_CCR MCF_REG16(0xFC0A0004) /* Chip Configuration Register (Read-only) (256 or 360 TEPBGA) */
43167 +#define MCF_CCM_RCON MCF_REG16(0xFC0A0008) /* Reset Configuration (Read-only) (256 or 360 TEPBGA) */
43168 +#define MCF_CCM_CIR MCF_REG16(0xFC0A000A) /* Chip Identification Register (Read-only) */
43169 +#define MCF_CCM_MISCCR MCF_REG16(0xFC0A0010) /* Miscellaneous Control Register */
43170 +#define MCF_CCM_CDR MCF_REG16(0xFC0A0012) /* Clock Divider Register */
43171 +#define MCF_CCM_UOCSR MCF_REG16(0xFC0A0014) /* USB On-the-Go Controller Status Register */
43172 +#define MCF_CCM_SBFSR MCF_REG16(0xFC0A0018) /* Serial Boot Facility Status Register (Read Only) */
43173 +#define MCF_CCM_SBFCR MCF_REG16(0xFC0A0020) /* Serial Boot Facility Control Register */
43174 +
43175 +/* Bit definitions and macros for CCR_360 */
43176 +#define MCF_CCM_CCR_360_PLLMULT2(x) (((x) & 0x0003)) /* 2-Bit PLL clock mode */
43177 +#define MCF_CCM_CCR_360_PCISLEW (0x0004) /* PCI pad slew rate mode */
43178 +#define MCF_CCM_CCR_360_PCIMODE (0x0008) /* PCI host/agent mode */
43179 +#define MCF_CCM_CCR_360_PLLMODE (0x0010) /* PLL Mode */
43180 +#define MCF_CCM_CCR_360_FBCONFIG(x) (((x) & 0x0007) << 5) /* Flexbus/PCI port size configuration */
43181 +#define MCF_CCM_CCR_360_PLLMULT3(x) (((x) & 0x0007)) /* 3-Bit PLL Clock Mode */
43182 +#define MCF_CCM_CCR_360_OSCMODE (0x0008) /* Oscillator Clock Mode */
43183 +#define MCF_CCM_CCR_360_FBCONFIG_MASK (0x00E0)
43184 +#define MCF_CCM_CCR_360_PLLMULT2_MASK (0x0003)
43185 +#define MCF_CCM_CCR_360_PLLMULT3_MASK (0x0007)
43186 +#define MCF_CCM_CCR_360_FBCONFIG_NM_NP_32 (0x0000)
43187 +#define MCF_CCM_CCR_360_FBCONFIG_NM_NP_8 (0x0020)
43188 +#define MCF_CCM_CCR_360_FBCONFIG_NM_NP_16 (0x0040)
43189 +#define MCF_CCM_CCR_360_FBCONFIG_M_P_16 (0x0060)
43190 +#define MCF_CCM_CCR_360_FBCONFIG_M_NP_32 (0x0080)
43191 +#define MCF_CCM_CCR_360_FBCONFIG_M_NP_8 (0x00A0)
43192 +#define MCF_CCM_CCR_360_FBCONFIG_M_NP_16 (0x00C0)
43193 +#define MCF_CCM_CCR_360_FBCONFIG_M_P_8 (0x00E0)
43194 +#define MCF_CCM_CCR_360_PLLMULT2_12X (0x0000)
43195 +#define MCF_CCM_CCR_360_PLLMULT2_6X (0x0001)
43196 +#define MCF_CCM_CCR_360_PLLMULT2_16X (0x0002)
43197 +#define MCF_CCM_CCR_360_PLLMULT2_8X (0x0003)
43198 +#define MCF_CCM_CCR_360_PLLMULT3_20X (0x0000)
43199 +#define MCF_CCM_CCR_360_PLLMULT3_10X (0x0001)
43200 +#define MCF_CCM_CCR_360_PLLMULT3_24X (0x0002)
43201 +#define MCF_CCM_CCR_360_PLLMULT3_18X (0x0003)
43202 +#define MCF_CCM_CCR_360_PLLMULT3_12X (0x0004)
43203 +#define MCF_CCM_CCR_360_PLLMULT3_6X (0x0005)
43204 +#define MCF_CCM_CCR_360_PLLMULT3_16X (0x0006)
43205 +#define MCF_CCM_CCR_360_PLLMULT3_8X (0x0007)
43206 +
43207 +/* Bit definitions and macros for CCR_256 */
43208 +#define MCF_CCM_CCR_256_PLLMULT3(x) (((x) & 0x0007)) /* 3-Bit PLL clock mode */
43209 +#define MCF_CCM_CCR_256_OSCMODE (0x0008) /* Oscillator clock mode */
43210 +#define MCF_CCM_CCR_256_PLLMODE (0x0010) /* PLL Mode */
43211 +#define MCF_CCM_CCR_256_FBCONFIG(x) (((x) & 0x0007) << 5) /* Flexbus/PCI port size configuration */
43212 +#define MCF_CCM_CCR_256_FBCONFIG_MASK (0x00E0)
43213 +#define MCF_CCM_CCR_256_FBCONFIG_NM_32 (0x0000)
43214 +#define MCF_CCM_CCR_256_FBCONFIG_NM_8 (0x0020)
43215 +#define MCF_CCM_CCR_256_FBCONFIG_NM_16 (0x0040)
43216 +#define MCF_CCM_CCR_256_FBCONFIG_M_32 (0x0080)
43217 +#define MCF_CCM_CCR_256_FBCONFIG_M_8 (0x00A0)
43218 +#define MCF_CCM_CCR_256_FBCONFIG_M_16 (0x00C0)
43219 +#define MCF_CCM_CCR_256_PLLMULT3_MASK (0x0007)
43220 +#define MCF_CCM_CCR_256_PLLMULT3_20X (0x0000)
43221 +#define MCF_CCM_CCR_256_PLLMULT3_10X (0x0001)
43222 +#define MCF_CCM_CCR_256_PLLMULT3_24X (0x0002)
43223 +#define MCF_CCM_CCR_256_PLLMULT3_18X (0x0003)
43224 +#define MCF_CCM_CCR_256_PLLMULT3_12X (0x0004)
43225 +#define MCF_CCM_CCR_256_PLLMULT3_6X (0x0005)
43226 +#define MCF_CCM_CCR_256_PLLMULT3_16X (0x0006)
43227 +#define MCF_CCM_CCR_256_PLLMULT3_8X (0x0007)
43228 +
43229 +/* Bit definitions and macros for RCON_360 */
43230 +#define MCF_CCM_RCON_360_PLLMULT(x) (((x)&0x0003)) /* PLL clock mode */
43231 +#define MCF_CCM_RCON_360_PCISLEW (0x0004) /* PCI pad slew rate mode */
43232 +#define MCF_CCM_RCON_360_PCIMODE (0x0008) /* PCI host/agent mode */
43233 +#define MCF_CCM_RCON_360_PLLMODE (0x0010) /* PLL Mode */
43234 +#define MCF_CCM_RCON_360_FBCONFIG(x) (((x) & 0x0007) << 5) /* Flexbus/PCI port size configuration */
43235 +
43236 +/* Bit definitions and macros for RCON_256 */
43237 +#define MCF_CCM_RCON_256_PLLMULT(x) (((x) & 0x0007)) /* PLL clock mode */
43238 +#define MCF_CCM_RCON_256_OSCMODE (0x0008) /* Oscillator clock mode */
43239 +#define MCF_CCM_RCON_256_PLLMODE (0x0010) /* PLL Mode */
43240 +#define MCF_CCM_RCON_256_FBCONFIG(x) (((x) & 0x0007) << 5) /* Flexbus/PCI port size configuration */
43241 +
43242 +/* Bit definitions and macros for CIR */
43243 +#define MCF_CCM_CIR_PRN(x) (((x) & 0x003F)) /* Part revision number */
43244 +#define MCF_CCM_CIR_PIN(x) (((x) & 0x03FF) << 6) /* Part identification number */
43245 +#define MCF_CCM_CIR_PIN_MASK (0xFFC0)
43246 +#define MCF_CCM_CIR_PRN_MASK (0x003F)
43247 +#define MCF_CCM_CIR_PIN_MCF54450 (0x4F << 6)
43248 +#define MCF_CCM_CIR_PIN_MCF54451 (0x4D << 6)
43249 +#define MCF_CCM_CIR_PIN_MCF54452 (0x4B << 6)
43250 +#define MCF_CCM_CIR_PIN_MCF54453 (0x49 << 6)
43251 +#define MCF_CCM_CIR_PIN_MCF54454 (0x4A << 6)
43252 +#define MCF_CCM_CIR_PIN_MCF54455 (0x48 << 6)
43253 +
43254 +/* Bit definitions and macros for MISCCR */
43255 +#define MCF_CCM_MISCCR_USBSRC (0x0001) /* USB clock source */
43256 +#define MCF_CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense polarity */
43257 +#define MCF_CCM_MISCCR_USBPUE (0x0004) /* USB transceiver pull-up enable */
43258 +#define MCF_CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */
43259 +#define MCF_CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */
43260 +#define MCF_CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */
43261 +#define MCF_CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */
43262 +#define MCF_CCM_MISCCR_BMT(x) (((x) & 0x0007) << 8) /* Bus monitor timing field */
43263 +#define MCF_CCM_MISCCR_BME (0x0800) /* Bus monitor external enable bit */
43264 +#define MCF_CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */
43265 +#define MCF_CCM_MISCCR_BMT_65536 (0 << 8)
43266 +#define MCF_CCM_MISCCR_BMT_32768 (1 << 8)
43267 +#define MCF_CCM_MISCCR_BMT_16384 (2 << 8)
43268 +#define MCF_CCM_MISCCR_BMT_8192 (3 << 8)
43269 +#define MCF_CCM_MISCCR_BMT_4096 (4 << 8)
43270 +#define MCF_CCM_MISCCR_BMT_2048 (5 << 8)
43271 +#define MCF_CCM_MISCCR_BMT_1024 (6 << 8)
43272 +#define MCF_CCM_MISCCR_BMT_512 (7 << 8)
43273 +#define MCF_CCM_MISCCR_SSIPUE_UP (1 << 7)
43274 +#define MCF_CCM_MISCCR_SSIPUE_DOWN (0 << 7)
43275 +#define MCF_CCM_MISCCR_SSIPUS_UP (1 << 6)
43276 +#define MCF_CCM_MISCCR_SSIPUS_DOWN (0 << 6)
43277 +#define MCF_CCM_MISCCR_TIMDMA_TIM (1 << 5)
43278 +#define MCF_CCM_MISCCR_TIMDMA_SSI (0 << 5)
43279 +#define MCF_CCM_MISCCR_SSISRC_CLKIN (0 << 4)
43280 +#define MCF_CCM_MISCCR_SSISRC_PLL (1 << 4)
43281 +#define MCF_CCM_MISCCR_USBOC_ACTHI (0 << 1)
43282 +#define MCF_CCM_MISCCR_USBOC_ACTLO (1 << 1)
43283 +#define MCF_CCM_MISCCR_USBSRC_CLKIN (0)
43284 +#define MCF_CCM_MISCCR_USBSRC_PLL (1)
43285 +
43286 +/* Bit definitions and macros for CDR */
43287 +#define MCF_CCM_CDR_SSIDIV(x) (((x) & 0x00FF)) /* SSI oversampling clock divider */
43288 +#define MCF_CCM_CDR_LPDIV(x) (((x) & 0x000F) << 8) /* Low power clock divider */
43289 +
43290 +/* Bit definitions and macros for UOCSR */
43291 +#define MCF_CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down enable */
43292 +#define MCF_CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt enable */
43293 +#define MCF_CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */
43294 +#define MCF_CCM_UOCSR_PWRFLT (0x0008) /* VBUS power fault */
43295 +#define MCF_CCM_UOCSR_SEND (0x0010) /* Session end */
43296 +#define MCF_CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */
43297 +#define MCF_CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */
43298 +#define MCF_CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */
43299 +#define MCF_CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (read-only) */
43300 +#define MCF_CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor enabled (read-only) */
43301 +#define MCF_CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (read-only) */
43302 +#define MCF_CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (read-only) */
43303 +#define MCF_CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (read-only) */
43304 +
43305 +/********************************************************************/
43306 +
43307 +#endif /* __MCF5445X_CCM_H__ */
43308 --- /dev/null
43309 +++ b/include/asm-m68k/mcf5445x_dspi.h
43310 @@ -0,0 +1,402 @@
43311 +/*
43312 + * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
43313 + *
43314 + * Copyright Freescale Semiconductor, Inc. 2007
43315 + *
43316 + * This program is free software; you can redistribute it and/or modify it
43317 + * under the terms of the GNU General Public License as published by the
43318 + * Free Software Foundation; either version 2 of the License, or (at your
43319 + * option) any later version.
43320 + */
43321 +
43322 +#ifndef __MCF5445X_DSPI_H__
43323 +#define __MCF5445X_DSPI_H__
43324 +
43325 +/*********************************************************************
43326 +*
43327 +* DMA Serial Peripheral Interface (DSPI)
43328 +*
43329 +*********************************************************************/
43330 +
43331 +/* Register read/write macros */
43332 +#define MCF_DSPI_DMCR MCF_REG32(0xFC05C000) /* DSPI Module Configuration Register */
43333 +#define MCF_DSPI_DTCR MCF_REG32(0xFC05C008) /* DSPI Transfer Count Register */
43334 +#define MCF_DSPI_DCTAR0 MCF_REG32(0xFC05C00C) /* DSPI Clock and Transfer Attributes Register */
43335 +#define MCF_DSPI_DCTAR1 MCF_REG32(0xFC05C010) /* DSPI Clock and Transfer Attributes Register */
43336 +#define MCF_DSPI_DCTAR2 MCF_REG32(0xFC05C014) /* DSPI Clock and Transfer Attributes Register */
43337 +#define MCF_DSPI_DCTAR3 MCF_REG32(0xFC05C018) /* DSPI Clock and Transfer Attributes Register */
43338 +#define MCF_DSPI_DCTAR4 MCF_REG32(0xFC05C01C) /* DSPI Clock and Transfer Attributes Register */
43339 +#define MCF_DSPI_DCTAR5 MCF_REG32(0xFC05C020) /* DSPI Clock and Transfer Attributes Register */
43340 +#define MCF_DSPI_DCTAR6 MCF_REG32(0xFC05C024) /* DSPI Clock and Transfer Attributes Register */
43341 +#define MCF_DSPI_DCTAR7 MCF_REG32(0xFC05C028) /* DSPI Clock and Transfer Attributes Register */
43342 +#define MCF_DSPI_DSR MCF_REG32(0xFC05C02C) /* DSPI Status Register */
43343 +#define MCF_DSPI_DRSER MCF_REG32(0xFC05C030) /* DSPI DMA/Interrupt Request Select and Enable Register */
43344 +#define MCF_DSPI_DTFR MCF_REG32(0xFC05C034) /* DSPI Transmit FIFO Register */
43345 +#define MCF_DSPI_DRFR MCF_REG32(0xFC05C038) /* DSPI Receive FIFO Register */
43346 +#define MCF_DSPI_DTFDR0 MCF_REG32(0xFC05C03C) /* DSPI Transmit FIFO Debugging Registers */
43347 +#define MCF_DSPI_DTFDR1 MCF_REG32(0xFC05C040) /* DSPI Transmit FIFO Debugging Registers */
43348 +#define MCF_DSPI_DTFDR2 MCF_REG32(0xFC05C044) /* DSPI Transmit FIFO Debugging Registers */
43349 +#define MCF_DSPI_DTFDR3 MCF_REG32(0xFC05C048) /* DSPI Transmit FIFO Debugging Registers */
43350 +#define MCF_DSPI_DRFDR0 MCF_REG32(0xFC05C07C) /* DSPI Receive FIFO Debugging Registers */
43351 +#define MCF_DSPI_DRFDR1 MCF_REG32(0xFC05C080) /* DSPI Receive FIFO Debugging Registers */
43352 +#define MCF_DSPI_DRFDR2 MCF_REG32(0xFC05C084) /* DSPI Receive FIFO Debugging Registers */
43353 +#define MCF_DSPI_DRFDR3 MCF_REG32(0xFC05C088) /* DSPI Receive FIFO Debugging Registers */
43354 +
43355 +/* Parameterized register read/write macros for multiple registers */
43356 +#define MCF_DSPI_DCTAR(x) MCF_REG32(0xFC05C00C+((x)*0x004)) /* DSPI Clock and Transfer Attributes Register */
43357 +#define MCF_DSPI_DTFDR(x) MCF_REG32(0xFC05C03C+((x)*0x004)) /* DSPI Transmit FIFO Debugging Registers */
43358 +#define MCF_DSPI_DRFDR(x) MCF_REG32(0xFC05C07C+((x)*0x004)) /* DSPI Receive FIFO Debugging Registers */
43359 +
43360 +/* Bit definitions and macros for DMCR */
43361 +#define MCF_DSPI_DMCR_HALT (0x00000001) /* Halt -- stops and starts DSPI transfers */
43362 +#define MCF_DSPI_DMCR_SMPLPT(x) (((x)&0x00000003)<<8) /* Sample point selection */
43363 +#define MCF_DSPI_DMCR_CLRRXF (0x00000400) /* Clear receive FIFO */
43364 +#define MCF_DSPI_DMCR_CLRTXF (0x00000800) /* Clear transmit FIFO */
43365 +#define MCF_DSPI_DMCR_DISRXF (0x00001000) /* Disable receive FIFO */
43366 +#define MCF_DSPI_DMCR_DISTXF (0x00002000) /* Disable transmit FIFO */
43367 +#define MCF_DSPI_DMCR_MDIS (0x00004000) /* Module Disable */
43368 +#define MCF_DSPI_DMCR_PCSIS0 (0x00010000) /* Peripheral chip-select 0 inactive state */
43369 +#define MCF_DSPI_DMCR_PCSIS1 (0x00020000) /* Peripheral chip-select 1 inactive state */
43370 +#define MCF_DSPI_DMCR_PCSIS2 (0x00040000) /* Peripheral chip-select 2 inactive state */
43371 +#define MCF_DSPI_DMCR_PCSIS3 (0x00080000) /* Peripheral chip-select 3 inactive state */
43372 +#define MCF_DSPI_DMCR_PCSIS4 (0x00100000) /* Peripheral chip-select 4 inactive state */
43373 +#define MCF_DSPI_DMCR_PCSIS5 (0x00200000) /* Peripheral chip-select 5 inactive state */
43374 +#define MCF_DSPI_DMCR_PCSIS6 (0x00400000) /* Peripheral chip-select 6 inactive state */
43375 +#define MCF_DSPI_DMCR_PCSIS7 (0x00800000) /* Peripheral chip-select 7 inactive state */
43376 +#define MCF_DSPI_DMCR_ROOE (0x01000000) /* Receive FIFO overflow overwrite enable */
43377 +#define MCF_DSPI_DMCR_PCSSE (0x02000000) /* Peripheral chip select strobe enable */
43378 +#define MCF_DSPI_DMCR_MTFE (0x04000000) /* Modified timing format enable */
43379 +#define MCF_DSPI_DMCR_FRZ (0x08000000) /* Freeze */
43380 +#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28) /* DSPI configuration */
43381 +#define MCF_DSPI_DMCR_CONT_SCKE (0x40000000) /* Continuous SCK enable */
43382 +#define MCF_DSPI_DMCR_MSTR (0x80000000) /* Master/Slave mode select */
43383 +#define MCF_DSPI_DMCR_DCONF_SPI (0x00000000)
43384 +#define MCF_DSPI_DMCR_PCSIS7_LOW (0x00000000)
43385 +#define MCF_DSPI_DMCR_PCSIS7_HIGH (0x00800000)
43386 +#define MCF_DSPI_DMCR_PCSIS6_LOW (0x00000000)
43387 +#define MCF_DSPI_DMCR_PCSIS6_HIGH (0x00400000)
43388 +#define MCF_DSPI_DMCR_PCSIS5_LOW (0x00000000)
43389 +#define MCF_DSPI_DMCR_PCSIS5_HIGH (0x00200000)
43390 +#define MCF_DSPI_DMCR_PCSIS4_LOW (0x00000000)
43391 +#define MCF_DSPI_DMCR_PCSIS4_HIGH (0x00100000)
43392 +#define MCF_DSPI_DMCR_PCSIS3_LOW (0x00000000)
43393 +#define MCF_DSPI_DMCR_PCSIS3_HIGH (0x00080000)
43394 +#define MCF_DSPI_DMCR_PCSIS2_LOW (0x00000000)
43395 +#define MCF_DSPI_DMCR_PCSIS2_HIGH (0x00040000)
43396 +#define MCF_DSPI_DMCR_PCSIS1_LOW (0x00000000)
43397 +#define MCF_DSPI_DMCR_PCSIS1_HIGH (0x00020000)
43398 +#define MCF_DSPI_DMCR_PCSIS0_LOW (0x00000000)
43399 +#define MCF_DSPI_DMCR_PCSIS0_HIGH (0x00010000)
43400 +
43401 +/* Bit definitions and macros for DTCR */
43402 +#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16) /* SPI transfer count */
43403 +
43404 +/* Bit definitions and macros for DCTAR group */
43405 +#define MCF_DSPI_DCTAR_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
43406 +#define MCF_DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
43407 +#define MCF_DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
43408 +#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
43409 +#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
43410 +#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
43411 +#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
43412 +#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
43413 +#define MCF_DSPI_DCTAR_LSBFE (0x01000000) /* LSB first enable */
43414 +#define MCF_DSPI_DCTAR_CPHA (0x02000000) /* Clock phase */
43415 +#define MCF_DSPI_DCTAR_CPOL (0x04000000) /* Clock polarity */
43416 +#define MCF_DSPI_DCTAR_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
43417 +#define MCF_DSPI_DCTAR_DBR (0x80000000) /* Double baud rate */
43418 +#define MCF_DSPI_DCTAR_CPOL_LOW (0x00000000)
43419 +#define MCF_DSPI_DCTAR_CPOL_HIGH (0x04000000)
43420 +#define MCF_DSPI_DCTAR_CPHA_LATCH_RISING (0x00000000)
43421 +#define MCF_DSPI_DCTAR_CPHA_LATCH_FALLING (0x02000000)
43422 +#define MCF_DSPI_DCTAR_PCSSCK_1CLK (0x00000000)
43423 +#define MCF_DSPI_DCTAR_PCSSCK_3CLK (0x00400000)
43424 +#define MCF_DSPI_DCTAR_PCSSCK_5CLK (0x00800000)
43425 +#define MCF_DSPI_DCTAR_PCSSCK_7CLK (0x00C00000)
43426 +#define MCF_DSPI_DCTAR_PASC_1CLK (0x00000000)
43427 +#define MCF_DSPI_DCTAR_PASC_3CLK (0x00100000)
43428 +#define MCF_DSPI_DCTAR_PASC_5CLK (0x00200000)
43429 +#define MCF_DSPI_DCTAR_PASC_7CLK (0x00300000)
43430 +#define MCF_DSPI_DCTAR_PDT_1CLK (0x00000000)
43431 +#define MCF_DSPI_DCTAR_PDT_3CLK (0x00040000)
43432 +#define MCF_DSPI_DCTAR_PDT_5CLK (0x00080000)
43433 +#define MCF_DSPI_DCTAR_PDT_7CLK (0x000C0000)
43434 +#define MCF_DSPI_DCTAR_PBR_2CLK (0x00000000)
43435 +#define MCF_DSPI_DCTAR_PBR_3CLK (0x00010000)
43436 +#define MCF_DSPI_DCTAR_PBR_5CLK (0x00020000)
43437 +#define MCF_DSPI_DCTAR_PBR_7CLK (0x00030000)
43438 +
43439 +/* Bit definitions and macros for DCTAR0 */
43440 +#define MCF_DSPI_DCTAR0_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
43441 +#define MCF_DSPI_DCTAR0_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
43442 +#define MCF_DSPI_DCTAR0_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
43443 +#define MCF_DSPI_DCTAR0_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
43444 +#define MCF_DSPI_DCTAR0_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
43445 +#define MCF_DSPI_DCTAR0_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
43446 +#define MCF_DSPI_DCTAR0_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
43447 +#define MCF_DSPI_DCTAR0_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
43448 +#define MCF_DSPI_DCTAR0_LSBFE (0x01000000) /* LSB first enable */
43449 +#define MCF_DSPI_DCTAR0_CPHA (0x02000000) /* Clock phase */
43450 +#define MCF_DSPI_DCTAR0_CPOL (0x04000000) /* Clock polarity */
43451 +#define MCF_DSPI_DCTAR0_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
43452 +#define MCF_DSPI_DCTAR0_DBR (0x80000000) /* Double baud rate */
43453 +#define MCF_DSPI_DCTAR0_CPOL_LOW (0x00000000)
43454 +#define MCF_DSPI_DCTAR0_CPOL_HIGH (0x04000000)
43455 +#define MCF_DSPI_DCTAR0_CPHA_LATCH_RISING (0x00000000)
43456 +#define MCF_DSPI_DCTAR0_CPHA_LATCH_FALLING (0x02000000)
43457 +#define MCF_DSPI_DCTAR0_PCSSCK_1CLK (0x00000000)
43458 +#define MCF_DSPI_DCTAR0_PCSSCK_3CLK (0x00400000)
43459 +#define MCF_DSPI_DCTAR0_PCSSCK_5CLK (0x00800000)
43460 +#define MCF_DSPI_DCTAR0_PCSSCK_7CLK (0x00C00000)
43461 +#define MCF_DSPI_DCTAR0_PASC_1CLK (0x00000000)
43462 +#define MCF_DSPI_DCTAR0_PASC_3CLK (0x00100000)
43463 +#define MCF_DSPI_DCTAR0_PASC_5CLK (0x00200000)
43464 +#define MCF_DSPI_DCTAR0_PASC_7CLK (0x00300000)
43465 +#define MCF_DSPI_DCTAR0_PDT_1CLK (0x00000000)
43466 +#define MCF_DSPI_DCTAR0_PDT_3CLK (0x00040000)
43467 +#define MCF_DSPI_DCTAR0_PDT_5CLK (0x00080000)
43468 +#define MCF_DSPI_DCTAR0_PDT_7CLK (0x000C0000)
43469 +#define MCF_DSPI_DCTAR0_PBR_2CLK (0x00000000)
43470 +#define MCF_DSPI_DCTAR0_PBR_3CLK (0x00010000)
43471 +#define MCF_DSPI_DCTAR0_PBR_5CLK (0x00020000)
43472 +#define MCF_DSPI_DCTAR0_PBR_7CLK (0x00030000)
43473 +
43474 +/* Bit definitions and macros for DCTAR1 */
43475 +#define MCF_DSPI_DCTAR1_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
43476 +#define MCF_DSPI_DCTAR1_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
43477 +#define MCF_DSPI_DCTAR1_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
43478 +#define MCF_DSPI_DCTAR1_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
43479 +#define MCF_DSPI_DCTAR1_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
43480 +#define MCF_DSPI_DCTAR1_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
43481 +#define MCF_DSPI_DCTAR1_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
43482 +#define MCF_DSPI_DCTAR1_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
43483 +#define MCF_DSPI_DCTAR1_LSBFE (0x01000000) /* LSB first enable */
43484 +#define MCF_DSPI_DCTAR1_CPHA (0x02000000) /* Clock phase */
43485 +#define MCF_DSPI_DCTAR1_CPOL (0x04000000) /* Clock polarity */
43486 +#define MCF_DSPI_DCTAR1_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
43487 +#define MCF_DSPI_DCTAR1_DBR (0x80000000) /* Double baud rate */
43488 +
43489 +/* Bit definitions and macros for DCTAR2 */
43490 +#define MCF_DSPI_DCTAR2_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
43491 +#define MCF_DSPI_DCTAR2_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
43492 +#define MCF_DSPI_DCTAR2_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
43493 +#define MCF_DSPI_DCTAR2_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
43494 +#define MCF_DSPI_DCTAR2_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
43495 +#define MCF_DSPI_DCTAR2_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
43496 +#define MCF_DSPI_DCTAR2_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
43497 +#define MCF_DSPI_DCTAR2_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
43498 +#define MCF_DSPI_DCTAR2_LSBFE (0x01000000) /* LSB first enable */
43499 +#define MCF_DSPI_DCTAR2_CPHA (0x02000000) /* Clock phase */
43500 +#define MCF_DSPI_DCTAR2_CPOL (0x04000000) /* Clock polarity */
43501 +#define MCF_DSPI_DCTAR2_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
43502 +#define MCF_DSPI_DCTAR2_DBR (0x80000000) /* Double baud rate */
43503 +
43504 +/* Bit definitions and macros for DCTAR3 */
43505 +#define MCF_DSPI_DCTAR3_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
43506 +#define MCF_DSPI_DCTAR3_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
43507 +#define MCF_DSPI_DCTAR3_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
43508 +#define MCF_DSPI_DCTAR3_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
43509 +#define MCF_DSPI_DCTAR3_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
43510 +#define MCF_DSPI_DCTAR3_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
43511 +#define MCF_DSPI_DCTAR3_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
43512 +#define MCF_DSPI_DCTAR3_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
43513 +#define MCF_DSPI_DCTAR3_LSBFE (0x01000000) /* LSB first enable */
43514 +#define MCF_DSPI_DCTAR3_CPHA (0x02000000) /* Clock phase */
43515 +#define MCF_DSPI_DCTAR3_CPOL (0x04000000) /* Clock polarity */
43516 +#define MCF_DSPI_DCTAR3_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
43517 +#define MCF_DSPI_DCTAR3_DBR (0x80000000) /* Double baud rate */
43518 +
43519 +/* Bit definitions and macros for DCTAR4 */
43520 +#define MCF_DSPI_DCTAR4_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
43521 +#define MCF_DSPI_DCTAR4_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
43522 +#define MCF_DSPI_DCTAR4_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
43523 +#define MCF_DSPI_DCTAR4_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
43524 +#define MCF_DSPI_DCTAR4_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
43525 +#define MCF_DSPI_DCTAR4_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
43526 +#define MCF_DSPI_DCTAR4_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
43527 +#define MCF_DSPI_DCTAR4_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
43528 +#define MCF_DSPI_DCTAR4_LSBFE (0x01000000) /* LSB first enable */
43529 +#define MCF_DSPI_DCTAR4_CPHA (0x02000000) /* Clock phase */
43530 +#define MCF_DSPI_DCTAR4_CPOL (0x04000000) /* Clock polarity */
43531 +#define MCF_DSPI_DCTAR4_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
43532 +#define MCF_DSPI_DCTAR4_DBR (0x80000000) /* Double baud rate */
43533 +
43534 +/* Bit definitions and macros for DCTAR5 */
43535 +#define MCF_DSPI_DCTAR5_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
43536 +#define MCF_DSPI_DCTAR5_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
43537 +#define MCF_DSPI_DCTAR5_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
43538 +#define MCF_DSPI_DCTAR5_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
43539 +#define MCF_DSPI_DCTAR5_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
43540 +#define MCF_DSPI_DCTAR5_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
43541 +#define MCF_DSPI_DCTAR5_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
43542 +#define MCF_DSPI_DCTAR5_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
43543 +#define MCF_DSPI_DCTAR5_LSBFE (0x01000000) /* LSB first enable */
43544 +#define MCF_DSPI_DCTAR5_CPHA (0x02000000) /* Clock phase */
43545 +#define MCF_DSPI_DCTAR5_CPOL (0x04000000) /* Clock polarity */
43546 +#define MCF_DSPI_DCTAR5_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
43547 +#define MCF_DSPI_DCTAR5_DBR (0x80000000) /* Double baud rate */
43548 +
43549 +/* Bit definitions and macros for DCTAR6 */
43550 +#define MCF_DSPI_DCTAR6_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
43551 +#define MCF_DSPI_DCTAR6_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
43552 +#define MCF_DSPI_DCTAR6_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
43553 +#define MCF_DSPI_DCTAR6_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
43554 +#define MCF_DSPI_DCTAR6_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
43555 +#define MCF_DSPI_DCTAR6_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
43556 +#define MCF_DSPI_DCTAR6_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
43557 +#define MCF_DSPI_DCTAR6_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
43558 +#define MCF_DSPI_DCTAR6_LSBFE (0x01000000) /* LSB first enable */
43559 +#define MCF_DSPI_DCTAR6_CPHA (0x02000000) /* Clock phase */
43560 +#define MCF_DSPI_DCTAR6_CPOL (0x04000000) /* Clock polarity */
43561 +#define MCF_DSPI_DCTAR6_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
43562 +#define MCF_DSPI_DCTAR6_DBR (0x80000000) /* Double baud rate */
43563 +
43564 +/* Bit definitions and macros for DCTAR7 */
43565 +#define MCF_DSPI_DCTAR7_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
43566 +#define MCF_DSPI_DCTAR7_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
43567 +#define MCF_DSPI_DCTAR7_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
43568 +#define MCF_DSPI_DCTAR7_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
43569 +#define MCF_DSPI_DCTAR7_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
43570 +#define MCF_DSPI_DCTAR7_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
43571 +#define MCF_DSPI_DCTAR7_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
43572 +#define MCF_DSPI_DCTAR7_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
43573 +#define MCF_DSPI_DCTAR7_LSBFE (0x01000000) /* LSB first enable */
43574 +#define MCF_DSPI_DCTAR7_CPHA (0x02000000) /* Clock phase */
43575 +#define MCF_DSPI_DCTAR7_CPOL (0x04000000) /* Clock polarity */
43576 +#define MCF_DSPI_DCTAR7_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
43577 +#define MCF_DSPI_DCTAR7_DBR (0x80000000) /* Double baud rate */
43578 +
43579 +/* Bit definitions and macros for DSR */
43580 +#define MCF_DSPI_DSR_RXPTR(x) (((x)&0x0000000F)) /* Receive next pointer */
43581 +#define MCF_DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4) /* Receive FIFO counter */
43582 +#define MCF_DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8) /* Transmit next pointer */
43583 +#define MCF_DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12) /* Transmit FIFO counter */
43584 +#define MCF_DSPI_DSR_RFDF (0x00020000) /* Receive FIFO drain flag */
43585 +#define MCF_DSPI_DSR_RFOF (0x00080000) /* Receive FIFO overflow flag */
43586 +#define MCF_DSPI_DSR_TFFF (0x02000000) /* Transmit FIFO fill flag */
43587 +#define MCF_DSPI_DSR_TFUF (0x08000000) /* Transmit FIFO underflow flag */
43588 +#define MCF_DSPI_DSR_EOQF (0x10000000) /* End of queue flag */
43589 +#define MCF_DSPI_DSR_TXRXS (0x40000000) /* Tx and Rx status (enabled | disabled) */
43590 +#define MCF_DSPI_DSR_TCF (0x80000000) /* Transfer complete flag */
43591 +
43592 +/* Bit definitions and macros for DRSER */
43593 +#define MCF_DSPI_DRSER_RFDFS (0x00010000) /* Receive FIFO drain DMA or interrupt select */
43594 +#define MCF_DSPI_DRSER_RFDFE (0x00020000) /* Receive FIFO drain request enable */
43595 +#define MCF_DSPI_DRSER_RFOFE (0x00080000) /* Receive FIFO overflow request enable */
43596 +#define MCF_DSPI_DRSER_TFFFS (0x01000000) /* Transmit FIFO fill DMA or interrupt select */
43597 +#define MCF_DSPI_DRSER_TFFFE (0x02000000) /* Transmit FIFO fill request enable */
43598 +#define MCF_DSPI_DRSER_TFUFE (0x08000000) /* Transmit FIFO underflow request enable */
43599 +#define MCF_DSPI_DRSER_EOQFE (0x10000000) /* DSPI finished request enable */
43600 +#define MCF_DSPI_DRSER_TCFE (0x80000000) /* Transmission complete request enable */
43601 +
43602 +/* Bit definitions and macros for DTFR */
43603 +#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)) /* Transmit data */
43604 +#define MCF_DSPI_DTFR_PCS0 (0x00010000) /* Peripheral chip select 0 */
43605 +#define MCF_DSPI_DTFR_PCS1 (0x00020000) /* Peripheral chip select 1 */
43606 +#define MCF_DSPI_DTFR_PCS2 (0x00040000) /* Peripheral chip select 2 */
43607 +#define MCF_DSPI_DTFR_PCS3 (0x00080000) /* Peripheral chip select 3 */
43608 +#define MCF_DSPI_DTFR_PCS4 (0x00100000) /* Peripheral chip select 4 */
43609 +#define MCF_DSPI_DTFR_PCS5 (0x00200000) /* Peripheral chip select 5 */
43610 +#define MCF_DSPI_DTFR_PCS6 (0x00400000) /* Peripheral chip select 6 */
43611 +#define MCF_DSPI_DTFR_PCS7 (0x00800000) /* Peripheral chip select 7 */
43612 +#define MCF_DSPI_DTFR_CTCNT (0x04000000) /* Clear SPI transfer counter */
43613 +#define MCF_DSPI_DTFR_EOQ (0x08000000) /* End of queue */
43614 +#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28) /* Clock and transfer attributes select */
43615 +#define MCF_DSPI_DTFR_CONT (0x80000000) /* Continuous peripheral chip-select enable */
43616 +
43617 +/* Bit definitions and macros for DRFR */
43618 +#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)) /* Receive data */
43619 +
43620 +/* Bit definitions and macros for DTFDR group */
43621 +#define MCF_DSPI_DTFDR_TXDATA(x) (((x)&0x0000FFFF)) /* Transmit data */
43622 +#define MCF_DSPI_DTFDR_PCS0 (0x00010000) /* Peripheral chip select 0 */
43623 +#define MCF_DSPI_DTFDR_PCS1 (0x00020000) /* Peripheral chip select 1 */
43624 +#define MCF_DSPI_DTFDR_PCS2 (0x00040000) /* Peripheral chip select 2 */
43625 +#define MCF_DSPI_DTFDR_PCS3 (0x00080000) /* Peripheral chip select 3 */
43626 +#define MCF_DSPI_DTFDR_PCS4 (0x00100000) /* Peripheral chip select 4 */
43627 +#define MCF_DSPI_DTFDR_PCS5 (0x00200000) /* Peripheral chip select 5 */
43628 +#define MCF_DSPI_DTFDR_PCS6 (0x00400000) /* Peripheral chip select 6 */
43629 +#define MCF_DSPI_DTFDR_PCS7 (0x00800000) /* Peripheral chip select 7 */
43630 +#define MCF_DSPI_DTFDR_CTCNT (0x04000000) /* Clear SPI transfer counter */
43631 +#define MCF_DSPI_DTFDR_EOQ (0x08000000) /* End of queue */
43632 +#define MCF_DSPI_DTFDR_CTAS(x) (((x)&0x00000007)<<28) /* Clock and transfer attributes select */
43633 +#define MCF_DSPI_DTFDR_CONT (0x80000000) /* Continuous peripheral chip-select enable */
43634 +
43635 +/* Bit definitions and macros for DTFDR0 */
43636 +#define MCF_DSPI_DTFDR0_TXDATA(x) (((x)&0x0000FFFF)) /* Transmit data */
43637 +#define MCF_DSPI_DTFDR0_PCS0 (0x00010000) /* Peripheral chip select 0 */
43638 +#define MCF_DSPI_DTFDR0_PCS1 (0x00020000) /* Peripheral chip select 1 */
43639 +#define MCF_DSPI_DTFDR0_PCS2 (0x00040000) /* Peripheral chip select 2 */
43640 +#define MCF_DSPI_DTFDR0_PCS3 (0x00080000) /* Peripheral chip select 3 */
43641 +#define MCF_DSPI_DTFDR0_PCS4 (0x00100000) /* Peripheral chip select 4 */
43642 +#define MCF_DSPI_DTFDR0_PCS5 (0x00200000) /* Peripheral chip select 5 */
43643 +#define MCF_DSPI_DTFDR0_PCS6 (0x00400000) /* Peripheral chip select 6 */
43644 +#define MCF_DSPI_DTFDR0_PCS7 (0x00800000) /* Peripheral chip select 7 */
43645 +#define MCF_DSPI_DTFDR0_CTCNT (0x04000000) /* Clear SPI transfer counter */
43646 +#define MCF_DSPI_DTFDR0_EOQ (0x08000000) /* End of queue */
43647 +#define MCF_DSPI_DTFDR0_CTAS(x) (((x)&0x00000007)<<28) /* Clock and transfer attributes select */
43648 +#define MCF_DSPI_DTFDR0_CONT (0x80000000) /* Continuous peripheral chip-select enable */
43649 +
43650 +/* Bit definitions and macros for DTFDR1 */
43651 +#define MCF_DSPI_DTFDR1_TXDATA(x) (((x)&0x0000FFFF)) /* Transmit data */
43652 +#define MCF_DSPI_DTFDR1_PCS0 (0x00010000) /* Peripheral chip select 0 */
43653 +#define MCF_DSPI_DTFDR1_PCS1 (0x00020000) /* Peripheral chip select 1 */
43654 +#define MCF_DSPI_DTFDR1_PCS2 (0x00040000) /* Peripheral chip select 2 */
43655 +#define MCF_DSPI_DTFDR1_PCS3 (0x00080000) /* Peripheral chip select 3 */
43656 +#define MCF_DSPI_DTFDR1_PCS4 (0x00100000) /* Peripheral chip select 4 */
43657 +#define MCF_DSPI_DTFDR1_PCS5 (0x00200000) /* Peripheral chip select 5 */
43658 +#define MCF_DSPI_DTFDR1_PCS6 (0x00400000) /* Peripheral chip select 6 */
43659 +#define MCF_DSPI_DTFDR1_PCS7 (0x00800000) /* Peripheral chip select 7 */
43660 +#define MCF_DSPI_DTFDR1_CTCNT (0x04000000) /* Clear SPI transfer counter */
43661 +#define MCF_DSPI_DTFDR1_EOQ (0x08000000) /* End of queue */
43662 +#define MCF_DSPI_DTFDR1_CTAS(x) (((x)&0x00000007)<<28) /* Clock and transfer attributes select */
43663 +#define MCF_DSPI_DTFDR1_CONT (0x80000000) /* Continuous peripheral chip-select enable */
43664 +
43665 +/* Bit definitions and macros for DTFDR2 */
43666 +#define MCF_DSPI_DTFDR2_TXDATA(x) (((x)&0x0000FFFF)) /* Transmit data */
43667 +#define MCF_DSPI_DTFDR2_PCS0 (0x00010000) /* Peripheral chip select 0 */
43668 +#define MCF_DSPI_DTFDR2_PCS1 (0x00020000) /* Peripheral chip select 1 */
43669 +#define MCF_DSPI_DTFDR2_PCS2 (0x00040000) /* Peripheral chip select 2 */
43670 +#define MCF_DSPI_DTFDR2_PCS3 (0x00080000) /* Peripheral chip select 3 */
43671 +#define MCF_DSPI_DTFDR2_PCS4 (0x00100000) /* Peripheral chip select 4 */
43672 +#define MCF_DSPI_DTFDR2_PCS5 (0x00200000) /* Peripheral chip select 5 */
43673 +#define MCF_DSPI_DTFDR2_PCS6 (0x00400000) /* Peripheral chip select 6 */
43674 +#define MCF_DSPI_DTFDR2_PCS7 (0x00800000) /* Peripheral chip select 7 */
43675 +#define MCF_DSPI_DTFDR2_CTCNT (0x04000000) /* Clear SPI transfer counter */
43676 +#define MCF_DSPI_DTFDR2_EOQ (0x08000000) /* End of queue */
43677 +#define MCF_DSPI_DTFDR2_CTAS(x) (((x)&0x00000007)<<28) /* Clock and transfer attributes select */
43678 +#define MCF_DSPI_DTFDR2_CONT (0x80000000) /* Continuous peripheral chip-select enable */
43679 +
43680 +/* Bit definitions and macros for DTFDR3 */
43681 +#define MCF_DSPI_DTFDR3_TXDATA(x) (((x)&0x0000FFFF)) /* Transmit data */
43682 +#define MCF_DSPI_DTFDR3_PCS0 (0x00010000) /* Peripheral chip select 0 */
43683 +#define MCF_DSPI_DTFDR3_PCS1 (0x00020000) /* Peripheral chip select 1 */
43684 +#define MCF_DSPI_DTFDR3_PCS2 (0x00040000) /* Peripheral chip select 2 */
43685 +#define MCF_DSPI_DTFDR3_PCS3 (0x00080000) /* Peripheral chip select 3 */
43686 +#define MCF_DSPI_DTFDR3_PCS4 (0x00100000) /* Peripheral chip select 4 */
43687 +#define MCF_DSPI_DTFDR3_PCS5 (0x00200000) /* Peripheral chip select 5 */
43688 +#define MCF_DSPI_DTFDR3_PCS6 (0x00400000) /* Peripheral chip select 6 */
43689 +#define MCF_DSPI_DTFDR3_PCS7 (0x00800000) /* Peripheral chip select 7 */
43690 +#define MCF_DSPI_DTFDR3_CTCNT (0x04000000) /* Clear SPI transfer counter */
43691 +#define MCF_DSPI_DTFDR3_EOQ (0x08000000) /* End of queue */
43692 +#define MCF_DSPI_DTFDR3_CTAS(x) (((x)&0x00000007)<<28) /* Clock and transfer attributes select */
43693 +#define MCF_DSPI_DTFDR3_CONT (0x80000000) /* Continuous peripheral chip-select enable */
43694 +
43695 +/* Bit definitions and macros for DRFDR group */
43696 +#define MCF_DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF)) /* Receive data */
43697 +
43698 +/* Bit definitions and macros for DRFDR0 */
43699 +#define MCF_DSPI_DRFDR0_RXDATA(x) (((x)&0x0000FFFF)) /* Receive data */
43700 +
43701 +/* Bit definitions and macros for DRFDR1 */
43702 +#define MCF_DSPI_DRFDR1_RXDATA(x) (((x)&0x0000FFFF)) /* Receive data */
43703 +
43704 +/* Bit definitions and macros for DRFDR2 */
43705 +#define MCF_DSPI_DRFDR2_RXDATA(x) (((x)&0x0000FFFF)) /* Receive data */
43706 +
43707 +/* Bit definitions and macros for DRFDR3 */
43708 +#define MCF_DSPI_DRFDR3_RXDATA(x) (((x)&0x0000FFFF)) /* Receive data */
43709 +
43710 +/********************************************************************/
43711 +
43712 +#endif /* __MCF5445X_DSPI_H__ */
43713 --- /dev/null
43714 +++ b/include/asm-m68k/mcf5445x_dtim.h
43715 @@ -0,0 +1,87 @@
43716 +/*
43717 + * Matt Waddel Matt.Waddel@freescale.com
43718 + *
43719 + * Copyright Freescale Semiconductor, Inc. 2007
43720 + *
43721 + * This program is free software; you can redistribute it and/or modify it
43722 + * under the terms of the GNU General Public License as published by the
43723 + * Free Software Foundation; either version 2 of the License, or (at your
43724 + * option) any later version.
43725 + */
43726 +
43727 +#ifndef __MCF5445X_DTIM_H__
43728 +#define __MCF5445X_DTIM_H__
43729 +
43730 +/*********************************************************************
43731 +*
43732 +* DMA Timers (DTIM)
43733 +*
43734 +*********************************************************************/
43735 +/* Register read/write macros */
43736 +#define MCF_DTIM0_DTMR 0xFC070000 /* DMA Timer Mode Register */
43737 +#define MCF_DTIM0_DTXMR 0xFC070002 /* DMA Timer Extended Mode Register */
43738 +#define MCF_DTIM0_DTER 0xFC070003 /* DMA Timer Event Register */
43739 +#define MCF_DTIM0_DTRR 0xFC070004 /* DMA Timer Reference Register */
43740 +#define MCF_DTIM0_DTCR 0xFC070008 /* DMA Timer Capture Register */
43741 +#define MCF_DTIM0_DTCN 0xFC07000C /* DMA Timer Counter Register */
43742 +#define MCF_DTIM1_DTMR 0xFC074000 /* DMA Timer Mode Register */
43743 +#define MCF_DTIM1_DTXMR 0xFC074002 /* DMA Timer Extended Mode Register */
43744 +#define MCF_DTIM1_DTER 0xFC074003 /* DMA Timer Event Register */
43745 +#define MCF_DTIM1_DTRR 0xFC074004 /* DMA Timer Reference Register */
43746 +#define MCF_DTIM1_DTCR 0xFC074008 /* DMA Timer Capture Register */
43747 +#define MCF_DTIM1_DTCN 0xFC07400C /* DMA Timer Counter Register */
43748 +#define MCF_DTIM2_DTMR 0xFC078000 /* DMA Timer Mode Register */
43749 +#define MCF_DTIM2_DTXMR 0xFC078002 /* DMA Timer Extended Mode Register */
43750 +#define MCF_DTIM2_DTER 0xFC078003 /* DMA Timer Event Register */
43751 +#define MCF_DTIM2_DTRR 0xFC078004 /* DMA Timer Reference Register */
43752 +#define MCF_DTIM2_DTCR 0xFC078008 /* DMA Timer Capture Register */
43753 +#define MCF_DTIM2_DTCN 0xFC07800C /* DMA Timer Counter Register */
43754 +#define MCF_DTIM3_DTMR 0xFC07C000 /* DMA Timer Mode Register */
43755 +#define MCF_DTIM3_DTXMR 0xFC07C002 /* DMA Timer Extended Mode Register */
43756 +#define MCF_DTIM3_DTER 0xFC07C003 /* DMA Timer Event Register */
43757 +#define MCF_DTIM3_DTRR 0xFC07C004 /* DMA Timer Reference Register */
43758 +#define MCF_DTIM3_DTCR 0xFC07C008 /* DMA Timer Capture Register */
43759 +#define MCF_DTIM3_DTCN 0xFC07C00C /* DMA Timer Counter Register */
43760 +
43761 +/* Parameterized register read/write macros for multiple modules */
43762 +#define MCF_DTIM_DTMR(x) 0xFC070000+((x)*0x4000) /* DMA Timer Mode Register */
43763 +#define MCF_DTIM_DTXMR(x) 0xFC070002+((x)*0x4000) /* DMA Timer Extended Mode Register */
43764 +#define MCF_DTIM_DTER(x) 0xFC070003+((x)*0x4000) /* DMA Timer Event Register */
43765 +#define MCF_DTIM_DTRR(x) 0xFC070004+((x)*0x4000) /* DMA Timer Reference Register */
43766 +#define MCF_DTIM_DTCR(x) 0xFC070008+((x)*0x4000) /* DMA Timer Capture Register */
43767 +#define MCF_DTIM_DTCN(x) 0xFC07000C+((x)*0x4000) /* DMA Timer Counter Register */
43768 +
43769 +/* Bit definitions and macros for DTMR */
43770 +#define MCF_DTIM_DTMR_RST (0x0001) /* Reset */
43771 +#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) /* Input clock source */
43772 +#define MCF_DTIM_DTMR_FRR (0x0008) /* Free run/restart */
43773 +#define MCF_DTIM_DTMR_ORRI (0x0010) /* Output reference request/interrupt enable */
43774 +#define MCF_DTIM_DTMR_OM (0x0020) /* Output Mode */
43775 +#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6) /* Capture Edge */
43776 +#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) /* Prescaler value */
43777 +#define MCF_DTIM_DTMR_RST_EN (0x0001)
43778 +#define MCF_DTIM_DTMR_RST_RST (0x0000)
43779 +#define MCF_DTIM_DTMR_CE_ANY (0x00C0)
43780 +#define MCF_DTIM_DTMR_CE_FALL (0x0080)
43781 +#define MCF_DTIM_DTMR_CE_RISE (0x0040)
43782 +#define MCF_DTIM_DTMR_CE_NONE (0x0000)
43783 +#define MCF_DTIM_DTMR_CLK_DTIN (0x0006)
43784 +#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004)
43785 +#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002)
43786 +#define MCF_DTIM_DTMR_CLK_STOP (0x0000)
43787 +
43788 +/* Bit definitions and macros for DTXMR */
43789 +#define MCF_DTIM_DTXMR_MODE16 (0x01) /* Increment Mode */
43790 +#define MCF_DTIM_DTXMR_DMAEN (0x80) /* DMA request */
43791 +
43792 +/* Bit definitions and macros for DTER */
43793 +#define MCF_DTIM_DTER_CAP (0x01) /* Capture event */
43794 +#define MCF_DTIM_DTER_REF (0x02) /* Output reference event */
43795 +
43796 +/* Interrupts used for system timers */
43797 +#define MCFSIM_ICR_TIMER1 (0xFC048040+32)
43798 +#define MCFSIM_ICR_TIMER2 (0xFC048040+33)
43799 +
43800 +/********************************************************************/
43801 +
43802 +#endif /* __MCF5445X_DTIM_H__ */
43803 --- /dev/null
43804 +++ b/include/asm-m68k/mcf5445x_edma.h
43805 @@ -0,0 +1,1472 @@
43806 +/*
43807 + * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
43808 + *
43809 + * Copyright Freescale Semiconductor, Inc. 2007
43810 + *
43811 + * This program is free software; you can redistribute it and/or modify it
43812 + * under the terms of the GNU General Public License as published by the
43813 + * Free Software Foundation; either version 2 of the License, or (at your
43814 + * option) any later version.
43815 + */
43816 +#ifndef __MCF5445X_EDMA_H__
43817 +#define __MCF5445X_EDMA_H__
43818 +
43819 +/*
43820 + * Enhanced DMA (EDMA)
43821 + */
43822 +
43823 +/* Channels */
43824 +#define MCF_EDMA_CHAN_DREQ0 0 /* External DMA request 0 */
43825 +#define MCF_EDMA_CHAN_DREQ1 1 /* External DMA request 1 */
43826 +#define MCF_EDMA_CHAN_UART0_RX 2 /* UART0 Receive */
43827 +#define MCF_EDMA_CHAN_UART0_TX 3 /* UART0 Transmit */
43828 +#define MCF_EDMA_CHAN_UART1_RX 4 /* UART1 Receive */
43829 +#define MCF_EDMA_CHAN_UART1_TX 5 /* UART1 Transmit */
43830 +#define MCF_EDMA_CHAN_UART2_RX 6 /* UART2 Receive */
43831 +#define MCF_EDMA_CHAN_UART2_TX 7 /* UART2 Transmit */
43832 +#define MCF_EDMA_CHAN_TIMER0 8 /* Timer 0 / SSI0 Rx */
43833 +#define MCF_EDMA_CHAN_TIMER1 9 /* Timer 1 / SSI1 Rx */
43834 +#define MCF_EDMA_CHAN_TIMER2 10 /* Timer 2 / SSI0 Tx */
43835 +#define MCF_EDMA_CHAN_TIMER3 11 /* Timer 3 / SSI1 Tx */
43836 +#define MCF_EDMA_CHAN_DSPI_RX 12 /* DSPI Receive */
43837 +#define MCF_EDMA_CHAN_DSPI_TX 13 /* DSPI Transmit */
43838 +#define MCF_EDMA_CHAN_ATA_RX 14 /* ATA Receive */
43839 +#define MCF_EDMA_CHAN_ATA_TX 15 /* ATA Transmit */
43840 +
43841 +/* Register read/write macros */
43842 +#define MCF_EDMA_CR MCF_REG32(0xFC044000)
43843 +#define MCF_EDMA_ES MCF_REG32(0xFC044004)
43844 +#define MCF_EDMA_ERQ MCF_REG16(0xFC04400E)
43845 +#define MCF_EDMA_EEI MCF_REG16(0xFC044016)
43846 +#define MCF_EDMA_SERQ MCF_REG08(0xFC044018)
43847 +#define MCF_EDMA_CERQ MCF_REG08(0xFC044019)
43848 +#define MCF_EDMA_SEEI MCF_REG08(0xFC04401A)
43849 +#define MCF_EDMA_CEEI MCF_REG08(0xFC04401B)
43850 +#define MCF_EDMA_CINT MCF_REG08(0xFC04401C)
43851 +#define MCF_EDMA_CERR MCF_REG08(0xFC04401D)
43852 +#define MCF_EDMA_SSRT MCF_REG08(0xFC04401E)
43853 +#define MCF_EDMA_CDNE MCF_REG08(0xFC04401F)
43854 +#define MCF_EDMA_INTR MCF_REG16(0xFC044026)
43855 +#define MCF_EDMA_ERR MCF_REG16(0xFC04402E)
43856 +#define MCF_EDMA_DCHPRI0 MCF_REG08(0xFC044100)
43857 +#define MCF_EDMA_DCHPRI1 MCF_REG08(0xFC044101)
43858 +#define MCF_EDMA_DCHPRI2 MCF_REG08(0xFC044102)
43859 +#define MCF_EDMA_DCHPRI3 MCF_REG08(0xFC044103)
43860 +#define MCF_EDMA_DCHPRI4 MCF_REG08(0xFC044104)
43861 +#define MCF_EDMA_DCHPRI5 MCF_REG08(0xFC044105)
43862 +#define MCF_EDMA_DCHPRI6 MCF_REG08(0xFC044106)
43863 +#define MCF_EDMA_DCHPRI7 MCF_REG08(0xFC044107)
43864 +#define MCF_EDMA_DCHPRI8 MCF_REG08(0xFC044108)
43865 +#define MCF_EDMA_DCHPRI9 MCF_REG08(0xFC044109)
43866 +#define MCF_EDMA_DCHPRI10 MCF_REG08(0xFC04410A)
43867 +#define MCF_EDMA_DCHPRI11 MCF_REG08(0xFC04410B)
43868 +#define MCF_EDMA_DCHPRI12 MCF_REG08(0xFC04410C)
43869 +#define MCF_EDMA_DCHPRI13 MCF_REG08(0xFC04410D)
43870 +#define MCF_EDMA_DCHPRI14 MCF_REG08(0xFC04410E)
43871 +#define MCF_EDMA_DCHPRI15 MCF_REG08(0xFC04410F)
43872 +#define MCF_EDMA_TCD0_SADDR MCF_REG32(0xFC045000)
43873 +#define MCF_EDMA_TCD0_ATTR MCF_REG16(0xFC045004)
43874 +#define MCF_EDMA_TCD0_SOFF MCF_REG16(0xFC045006)
43875 +#define MCF_EDMA_TCD0_NBYTES MCF_REG32(0xFC045008)
43876 +#define MCF_EDMA_TCD0_SLAST MCF_REG32(0xFC04500C)
43877 +#define MCF_EDMA_TCD0_DADDR MCF_REG32(0xFC045010)
43878 +#define MCF_EDMA_TCD0_CITER_ELINK MCF_REG16(0xFC045014)
43879 +#define MCF_EDMA_TCD0_CITER MCF_REG16(0xFC045014)
43880 +#define MCF_EDMA_TCD0_DOFF MCF_REG16(0xFC045016)
43881 +#define MCF_EDMA_TCD0_DLAST_SGA MCF_REG32(0xFC045018)
43882 +#define MCF_EDMA_TCD0_BITER_ELINK MCF_REG16(0xFC04501C)
43883 +#define MCF_EDMA_TCD0_BITER MCF_REG16(0xFC04501C)
43884 +#define MCF_EDMA_TCD0_CSR MCF_REG16(0xFC04501E)
43885 +#define MCF_EDMA_TCD1_SADDR MCF_REG32(0xFC045020)
43886 +#define MCF_EDMA_TCD1_ATTR MCF_REG16(0xFC045024)
43887 +#define MCF_EDMA_TCD1_SOFF MCF_REG16(0xFC045026)
43888 +#define MCF_EDMA_TCD1_NBYTES MCF_REG32(0xFC045028)
43889 +#define MCF_EDMA_TCD1_SLAST MCF_REG32(0xFC04502C)
43890 +#define MCF_EDMA_TCD1_DADDR MCF_REG32(0xFC045030)
43891 +#define MCF_EDMA_TCD1_CITER_ELINK MCF_REG16(0xFC045034)
43892 +#define MCF_EDMA_TCD1_CITER MCF_REG16(0xFC045034)
43893 +#define MCF_EDMA_TCD1_DOFF MCF_REG16(0xFC045036)
43894 +#define MCF_EDMA_TCD1_DLAST_SGA MCF_REG32(0xFC045038)
43895 +#define MCF_EDMA_TCD1_BITER MCF_REG16(0xFC04503C)
43896 +#define MCF_EDMA_TCD1_BITER_ELINK MCF_REG16(0xFC04503C)
43897 +#define MCF_EDMA_TCD1_CSR MCF_REG16(0xFC04503E)
43898 +#define MCF_EDMA_TCD2_SADDR MCF_REG32(0xFC045040)
43899 +#define MCF_EDMA_TCD2_ATTR MCF_REG16(0xFC045044)
43900 +#define MCF_EDMA_TCD2_SOFF MCF_REG16(0xFC045046)
43901 +#define MCF_EDMA_TCD2_NBYTES MCF_REG32(0xFC045048)
43902 +#define MCF_EDMA_TCD2_SLAST MCF_REG32(0xFC04504C)
43903 +#define MCF_EDMA_TCD2_DADDR MCF_REG32(0xFC045050)
43904 +#define MCF_EDMA_TCD2_CITER MCF_REG16(0xFC045054)
43905 +#define MCF_EDMA_TCD2_CITER_ELINK MCF_REG16(0xFC045054)
43906 +#define MCF_EDMA_TCD2_DOFF MCF_REG16(0xFC045056)
43907 +#define MCF_EDMA_TCD2_DLAST_SGA MCF_REG32(0xFC045058)
43908 +#define MCF_EDMA_TCD2_BITER_ELINK MCF_REG16(0xFC04505C)
43909 +#define MCF_EDMA_TCD2_BITER MCF_REG16(0xFC04505C)
43910 +#define MCF_EDMA_TCD2_CSR MCF_REG16(0xFC04505E)
43911 +#define MCF_EDMA_TCD3_SADDR MCF_REG32(0xFC045060)
43912 +#define MCF_EDMA_TCD3_ATTR MCF_REG16(0xFC045064)
43913 +#define MCF_EDMA_TCD3_SOFF MCF_REG16(0xFC045066)
43914 +#define MCF_EDMA_TCD3_NBYTES MCF_REG32(0xFC045068)
43915 +#define MCF_EDMA_TCD3_SLAST MCF_REG32(0xFC04506C)
43916 +#define MCF_EDMA_TCD3_DADDR MCF_REG32(0xFC045070)
43917 +#define MCF_EDMA_TCD3_CITER MCF_REG16(0xFC045074)
43918 +#define MCF_EDMA_TCD3_CITER_ELINK MCF_REG16(0xFC045074)
43919 +#define MCF_EDMA_TCD3_DOFF MCF_REG16(0xFC045076)
43920 +#define MCF_EDMA_TCD3_DLAST_SGA MCF_REG32(0xFC045078)
43921 +#define MCF_EDMA_TCD3_BITER_ELINK MCF_REG16(0xFC04507C)
43922 +#define MCF_EDMA_TCD3_BITER MCF_REG16(0xFC04507C)
43923 +#define MCF_EDMA_TCD3_CSR MCF_REG16(0xFC04507E)
43924 +#define MCF_EDMA_TCD4_SADDR MCF_REG32(0xFC045080)
43925 +#define MCF_EDMA_TCD4_ATTR MCF_REG16(0xFC045084)
43926 +#define MCF_EDMA_TCD4_SOFF MCF_REG16(0xFC045086)
43927 +#define MCF_EDMA_TCD4_NBYTES MCF_REG32(0xFC045088)
43928 +#define MCF_EDMA_TCD4_SLAST MCF_REG32(0xFC04508C)
43929 +#define MCF_EDMA_TCD4_DADDR MCF_REG32(0xFC045090)
43930 +#define MCF_EDMA_TCD4_CITER MCF_REG16(0xFC045094)
43931 +#define MCF_EDMA_TCD4_CITER_ELINK MCF_REG16(0xFC045094)
43932 +#define MCF_EDMA_TCD4_DOFF MCF_REG16(0xFC045096)
43933 +#define MCF_EDMA_TCD4_DLAST_SGA MCF_REG32(0xFC045098)
43934 +#define MCF_EDMA_TCD4_BITER MCF_REG16(0xFC04509C)
43935 +#define MCF_EDMA_TCD4_BITER_ELINK MCF_REG16(0xFC04509C)
43936 +#define MCF_EDMA_TCD4_CSR MCF_REG16(0xFC04509E)
43937 +#define MCF_EDMA_TCD5_SADDR MCF_REG32(0xFC0450A0)
43938 +#define MCF_EDMA_TCD5_ATTR MCF_REG16(0xFC0450A4)
43939 +#define MCF_EDMA_TCD5_SOFF MCF_REG16(0xFC0450A6)
43940 +#define MCF_EDMA_TCD5_NBYTES MCF_REG32(0xFC0450A8)
43941 +#define MCF_EDMA_TCD5_SLAST MCF_REG32(0xFC0450AC)
43942 +#define MCF_EDMA_TCD5_DADDR MCF_REG32(0xFC0450B0)
43943 +#define MCF_EDMA_TCD5_CITER MCF_REG16(0xFC0450B4)
43944 +#define MCF_EDMA_TCD5_CITER_ELINK MCF_REG16(0xFC0450B4)
43945 +#define MCF_EDMA_TCD5_DOFF MCF_REG16(0xFC0450B6)
43946 +#define MCF_EDMA_TCD5_DLAST_SGA MCF_REG32(0xFC0450B8)
43947 +#define MCF_EDMA_TCD5_BITER_ELINK MCF_REG16(0xFC0450BC)
43948 +#define MCF_EDMA_TCD5_BITER MCF_REG16(0xFC0450BC)
43949 +#define MCF_EDMA_TCD5_CSR MCF_REG16(0xFC0450BE)
43950 +#define MCF_EDMA_TCD6_SADDR MCF_REG32(0xFC0450C0)
43951 +#define MCF_EDMA_TCD6_ATTR MCF_REG16(0xFC0450C4)
43952 +#define MCF_EDMA_TCD6_SOFF MCF_REG16(0xFC0450C6)
43953 +#define MCF_EDMA_TCD6_NBYTES MCF_REG32(0xFC0450C8)
43954 +#define MCF_EDMA_TCD6_SLAST MCF_REG32(0xFC0450CC)
43955 +#define MCF_EDMA_TCD6_DADDR MCF_REG32(0xFC0450D0)
43956 +#define MCF_EDMA_TCD6_CITER MCF_REG16(0xFC0450D4)
43957 +#define MCF_EDMA_TCD6_CITER_ELINK MCF_REG16(0xFC0450D4)
43958 +#define MCF_EDMA_TCD6_DOFF MCF_REG16(0xFC0450D6)
43959 +#define MCF_EDMA_TCD6_DLAST_SGA MCF_REG32(0xFC0450D8)
43960 +#define MCF_EDMA_TCD6_BITER_ELINK MCF_REG16(0xFC0450DC)
43961 +#define MCF_EDMA_TCD6_BITER MCF_REG16(0xFC0450DC)
43962 +#define MCF_EDMA_TCD6_CSR MCF_REG16(0xFC0450DE)
43963 +#define MCF_EDMA_TCD7_SADDR MCF_REG32(0xFC0450E0)
43964 +#define MCF_EDMA_TCD7_ATTR MCF_REG16(0xFC0450E4)
43965 +#define MCF_EDMA_TCD7_SOFF MCF_REG16(0xFC0450E6)
43966 +#define MCF_EDMA_TCD7_NBYTES MCF_REG32(0xFC0450E8)
43967 +#define MCF_EDMA_TCD7_SLAST MCF_REG32(0xFC0450EC)
43968 +#define MCF_EDMA_TCD7_DADDR MCF_REG32(0xFC0450F0)
43969 +#define MCF_EDMA_TCD7_CITER MCF_REG16(0xFC0450F4)
43970 +#define MCF_EDMA_TCD7_CITER_ELINK MCF_REG16(0xFC0450F4)
43971 +#define MCF_EDMA_TCD7_DOFF MCF_REG16(0xFC0450F6)
43972 +#define MCF_EDMA_TCD7_DLAST_SGA MCF_REG32(0xFC0450F8)
43973 +#define MCF_EDMA_TCD7_BITER_ELINK MCF_REG16(0xFC0450FC)
43974 +#define MCF_EDMA_TCD7_BITER MCF_REG16(0xFC0450FC)
43975 +#define MCF_EDMA_TCD7_CSR MCF_REG16(0xFC0450FE)
43976 +#define MCF_EDMA_TCD8_SADDR MCF_REG32(0xFC045100)
43977 +#define MCF_EDMA_TCD8_ATTR MCF_REG16(0xFC045104)
43978 +#define MCF_EDMA_TCD8_SOFF MCF_REG16(0xFC045106)
43979 +#define MCF_EDMA_TCD8_NBYTES MCF_REG32(0xFC045108)
43980 +#define MCF_EDMA_TCD8_SLAST MCF_REG32(0xFC04510C)
43981 +#define MCF_EDMA_TCD8_DADDR MCF_REG32(0xFC045110)
43982 +#define MCF_EDMA_TCD8_CITER MCF_REG16(0xFC045114)
43983 +#define MCF_EDMA_TCD8_CITER_ELINK MCF_REG16(0xFC045114)
43984 +#define MCF_EDMA_TCD8_DOFF MCF_REG16(0xFC045116)
43985 +#define MCF_EDMA_TCD8_DLAST_SGA MCF_REG32(0xFC045118)
43986 +#define MCF_EDMA_TCD8_BITER_ELINK MCF_REG16(0xFC04511C)
43987 +#define MCF_EDMA_TCD8_BITER MCF_REG16(0xFC04511C)
43988 +#define MCF_EDMA_TCD8_CSR MCF_REG16(0xFC04511E)
43989 +#define MCF_EDMA_TCD9_SADDR MCF_REG32(0xFC045120)
43990 +#define MCF_EDMA_TCD9_ATTR MCF_REG16(0xFC045124)
43991 +#define MCF_EDMA_TCD9_SOFF MCF_REG16(0xFC045126)
43992 +#define MCF_EDMA_TCD9_NBYTES MCF_REG32(0xFC045128)
43993 +#define MCF_EDMA_TCD9_SLAST MCF_REG32(0xFC04512C)
43994 +#define MCF_EDMA_TCD9_DADDR MCF_REG32(0xFC045130)
43995 +#define MCF_EDMA_TCD9_CITER_ELINK MCF_REG16(0xFC045134)
43996 +#define MCF_EDMA_TCD9_CITER MCF_REG16(0xFC045134)
43997 +#define MCF_EDMA_TCD9_DOFF MCF_REG16(0xFC045136)
43998 +#define MCF_EDMA_TCD9_DLAST_SGA MCF_REG32(0xFC045138)
43999 +#define MCF_EDMA_TCD9_BITER_ELINK MCF_REG16(0xFC04513C)
44000 +#define MCF_EDMA_TCD9_BITER MCF_REG16(0xFC04513C)
44001 +#define MCF_EDMA_TCD9_CSR MCF_REG16(0xFC04513E)
44002 +#define MCF_EDMA_TCD10_SADDR MCF_REG32(0xFC045140)
44003 +#define MCF_EDMA_TCD10_ATTR MCF_REG16(0xFC045144)
44004 +#define MCF_EDMA_TCD10_SOFF MCF_REG16(0xFC045146)
44005 +#define MCF_EDMA_TCD10_NBYTES MCF_REG32(0xFC045148)
44006 +#define MCF_EDMA_TCD10_SLAST MCF_REG32(0xFC04514C)
44007 +#define MCF_EDMA_TCD10_DADDR MCF_REG32(0xFC045150)
44008 +#define MCF_EDMA_TCD10_CITER_ELINK MCF_REG16(0xFC045154)
44009 +#define MCF_EDMA_TCD10_CITER MCF_REG16(0xFC045154)
44010 +#define MCF_EDMA_TCD10_DOFF MCF_REG16(0xFC045156)
44011 +#define MCF_EDMA_TCD10_DLAST_SGA MCF_REG32(0xFC045158)
44012 +#define MCF_EDMA_TCD10_BITER MCF_REG16(0xFC04515C)
44013 +#define MCF_EDMA_TCD10_BITER_ELINK MCF_REG16(0xFC04515C)
44014 +#define MCF_EDMA_TCD10_CSR MCF_REG16(0xFC04515E)
44015 +#define MCF_EDMA_TCD11_SADDR MCF_REG32(0xFC045160)
44016 +#define MCF_EDMA_TCD11_ATTR MCF_REG16(0xFC045164)
44017 +#define MCF_EDMA_TCD11_SOFF MCF_REG16(0xFC045166)
44018 +#define MCF_EDMA_TCD11_NBYTES MCF_REG32(0xFC045168)
44019 +#define MCF_EDMA_TCD11_SLAST MCF_REG32(0xFC04516C)
44020 +#define MCF_EDMA_TCD11_DADDR MCF_REG32(0xFC045170)
44021 +#define MCF_EDMA_TCD11_CITER MCF_REG16(0xFC045174)
44022 +#define MCF_EDMA_TCD11_CITER_ELINK MCF_REG16(0xFC045174)
44023 +#define MCF_EDMA_TCD11_DOFF MCF_REG16(0xFC045176)
44024 +#define MCF_EDMA_TCD11_DLAST_SGA MCF_REG32(0xFC045178)
44025 +#define MCF_EDMA_TCD11_BITER MCF_REG16(0xFC04517C)
44026 +#define MCF_EDMA_TCD11_BITER_ELINK MCF_REG16(0xFC04517C)
44027 +#define MCF_EDMA_TCD11_CSR MCF_REG16(0xFC04517E)
44028 +#define MCF_EDMA_TCD12_SADDR MCF_REG32(0xFC045180)
44029 +#define MCF_EDMA_TCD12_ATTR MCF_REG16(0xFC045184)
44030 +#define MCF_EDMA_TCD12_SOFF MCF_REG16(0xFC045186)
44031 +#define MCF_EDMA_TCD12_NBYTES MCF_REG32(0xFC045188)
44032 +#define MCF_EDMA_TCD12_SLAST MCF_REG32(0xFC04518C)
44033 +#define MCF_EDMA_TCD12_DADDR MCF_REG32(0xFC045190)
44034 +#define MCF_EDMA_TCD12_CITER MCF_REG16(0xFC045194)
44035 +#define MCF_EDMA_TCD12_CITER_ELINK MCF_REG16(0xFC045194)
44036 +#define MCF_EDMA_TCD12_DOFF MCF_REG16(0xFC045196)
44037 +#define MCF_EDMA_TCD12_DLAST_SGA MCF_REG32(0xFC045198)
44038 +#define MCF_EDMA_TCD12_BITER MCF_REG16(0xFC04519C)
44039 +#define MCF_EDMA_TCD12_BITER_ELINK MCF_REG16(0xFC04519C)
44040 +#define MCF_EDMA_TCD12_CSR MCF_REG16(0xFC04519E)
44041 +#define MCF_EDMA_TCD13_SADDR MCF_REG32(0xFC0451A0)
44042 +#define MCF_EDMA_TCD13_ATTR MCF_REG16(0xFC0451A4)
44043 +#define MCF_EDMA_TCD13_SOFF MCF_REG16(0xFC0451A6)
44044 +#define MCF_EDMA_TCD13_NBYTES MCF_REG32(0xFC0451A8)
44045 +#define MCF_EDMA_TCD13_SLAST MCF_REG32(0xFC0451AC)
44046 +#define MCF_EDMA_TCD13_DADDR MCF_REG32(0xFC0451B0)
44047 +#define MCF_EDMA_TCD13_CITER_ELINK MCF_REG16(0xFC0451B4)
44048 +#define MCF_EDMA_TCD13_CITER MCF_REG16(0xFC0451B4)
44049 +#define MCF_EDMA_TCD13_DOFF MCF_REG16(0xFC0451B6)
44050 +#define MCF_EDMA_TCD13_DLAST_SGA MCF_REG32(0xFC0451B8)
44051 +#define MCF_EDMA_TCD13_BITER_ELINK MCF_REG16(0xFC0451BC)
44052 +#define MCF_EDMA_TCD13_BITER MCF_REG16(0xFC0451BC)
44053 +#define MCF_EDMA_TCD13_CSR MCF_REG16(0xFC0451BE)
44054 +#define MCF_EDMA_TCD14_SADDR MCF_REG32(0xFC0451C0)
44055 +#define MCF_EDMA_TCD14_ATTR MCF_REG16(0xFC0451C4)
44056 +#define MCF_EDMA_TCD14_SOFF MCF_REG16(0xFC0451C6)
44057 +#define MCF_EDMA_TCD14_NBYTES MCF_REG32(0xFC0451C8)
44058 +#define MCF_EDMA_TCD14_SLAST MCF_REG32(0xFC0451CC)
44059 +#define MCF_EDMA_TCD14_DADDR MCF_REG32(0xFC0451D0)
44060 +#define MCF_EDMA_TCD14_CITER MCF_REG16(0xFC0451D4)
44061 +#define MCF_EDMA_TCD14_CITER_ELINK MCF_REG16(0xFC0451D4)
44062 +#define MCF_EDMA_TCD14_DOFF MCF_REG16(0xFC0451D6)
44063 +#define MCF_EDMA_TCD14_DLAST_SGA MCF_REG32(0xFC0451D8)
44064 +#define MCF_EDMA_TCD14_BITER_ELINK MCF_REG16(0xFC0451DC)
44065 +#define MCF_EDMA_TCD14_BITER MCF_REG16(0xFC0451DC)
44066 +#define MCF_EDMA_TCD14_CSR MCF_REG16(0xFC0451DE)
44067 +#define MCF_EDMA_TCD15_SADDR MCF_REG32(0xFC0451E0)
44068 +#define MCF_EDMA_TCD15_ATTR MCF_REG16(0xFC0451E4)
44069 +#define MCF_EDMA_TCD15_SOFF MCF_REG16(0xFC0451E6)
44070 +#define MCF_EDMA_TCD15_NBYTES MCF_REG32(0xFC0451E8)
44071 +#define MCF_EDMA_TCD15_SLAST MCF_REG32(0xFC0451EC)
44072 +#define MCF_EDMA_TCD15_DADDR MCF_REG32(0xFC0451F0)
44073 +#define MCF_EDMA_TCD15_CITER_ELINK MCF_REG16(0xFC0451F4)
44074 +#define MCF_EDMA_TCD15_CITER MCF_REG16(0xFC0451F4)
44075 +#define MCF_EDMA_TCD15_DOFF MCF_REG16(0xFC0451F6)
44076 +#define MCF_EDMA_TCD15_DLAST_SGA MCF_REG32(0xFC0451F8)
44077 +#define MCF_EDMA_TCD15_BITER MCF_REG16(0xFC0451FC)
44078 +#define MCF_EDMA_TCD15_BITER_ELINK MCF_REG16(0xFC0451FC)
44079 +#define MCF_EDMA_TCD15_CSR MCF_REG16(0xFC0451FE)
44080 +
44081 +/* Parameterized register read/write macros for multiple registers */
44082 +#define MCF_EDMA_DCHPRI(x) MCF_REG08(0xFC044100+((x)*0x001))
44083 +#define MCF_EDMA_TCD_SADDR(x) MCF_REG32(0xFC045000+((x)*0x020))
44084 +#define MCF_EDMA_TCD_ATTR(x) MCF_REG16(0xFC045004+((x)*0x020))
44085 +#define MCF_EDMA_TCD_SOFF(x) MCF_REG16(0xFC045006+((x)*0x020))
44086 +#define MCF_EDMA_TCD_NBYTES(x) MCF_REG32(0xFC045008+((x)*0x020))
44087 +#define MCF_EDMA_TCD_SLAST(x) MCF_REG32(0xFC04500C+((x)*0x020))
44088 +#define MCF_EDMA_TCD_DADDR(x) MCF_REG32(0xFC045010+((x)*0x020))
44089 +#define MCF_EDMA_TCD_CITER_ELINK(x) MCF_REG16(0xFC045014+((x)*0x020))
44090 +#define MCF_EDMA_TCD_CITER(x) MCF_REG16(0xFC045014+((x)*0x020))
44091 +#define MCF_EDMA_TCD_DOFF(x) MCF_REG16(0xFC045016+((x)*0x020))
44092 +#define MCF_EDMA_TCD_DLAST_SGA(x) MCF_REG32(0xFC045018+((x)*0x020))
44093 +#define MCF_EDMA_TCD_BITER_ELINK(x) MCF_REG16(0xFC04501C+((x)*0x020))
44094 +#define MCF_EDMA_TCD_BITER(x) MCF_REG16(0xFC04501C+((x)*0x020))
44095 +#define MCF_EDMA_TCD_CSR(x) MCF_REG16(0xFC04501e +((x)*0x020))
44096 +
44097 +/* Bit definitions and macros for CR */
44098 +#define MCF_EDMA_CR_EDBG (0x00000002)
44099 +#define MCF_EDMA_CR_ERCA (0x00000004)
44100 +
44101 +/* Bit definitions and macros for ES */
44102 +#define MCF_EDMA_ES_DBE (0x00000001)
44103 +#define MCF_EDMA_ES_SBE (0x00000002)
44104 +#define MCF_EDMA_ES_SGE (0x00000004)
44105 +#define MCF_EDMA_ES_NCE (0x00000008)
44106 +#define MCF_EDMA_ES_DOE (0x00000010)
44107 +#define MCF_EDMA_ES_DAE (0x00000020)
44108 +#define MCF_EDMA_ES_SOE (0x00000040)
44109 +#define MCF_EDMA_ES_SAE (0x00000080)
44110 +#define MCF_EDMA_ES_ERRCHN(x) (((x)&0x0000000F)<<8)
44111 +#define MCF_EDMA_ES_CPE (0x00004000)
44112 +#define MCF_EDMA_ES_VLD (0x80000000)
44113 +
44114 +/* Bit definitions and macros for ERQ */
44115 +#define MCF_EDMA_ERQ_ERQ0 (0x0001)
44116 +#define MCF_EDMA_ERQ_ERQ1 (0x0002)
44117 +#define MCF_EDMA_ERQ_ERQ2 (0x0004)
44118 +#define MCF_EDMA_ERQ_ERQ3 (0x0008)
44119 +#define MCF_EDMA_ERQ_ERQ4 (0x0010)
44120 +#define MCF_EDMA_ERQ_ERQ5 (0x0020)
44121 +#define MCF_EDMA_ERQ_ERQ6 (0x0040)
44122 +#define MCF_EDMA_ERQ_ERQ7 (0x0080)
44123 +#define MCF_EDMA_ERQ_ERQ8 (0x0100)
44124 +#define MCF_EDMA_ERQ_ERQ9 (0x0200)
44125 +#define MCF_EDMA_ERQ_ERQ10 (0x0400)
44126 +#define MCF_EDMA_ERQ_ERQ11 (0x0800)
44127 +#define MCF_EDMA_ERQ_ERQ12 (0x1000)
44128 +#define MCF_EDMA_ERQ_ERQ13 (0x2000)
44129 +#define MCF_EDMA_ERQ_ERQ14 (0x4000)
44130 +#define MCF_EDMA_ERQ_ERQ15 (0x8000)
44131 +
44132 +/* Bit definitions and macros for EEI */
44133 +#define MCF_EDMA_EEI_EEI0 (0x0001)
44134 +#define MCF_EDMA_EEI_EEI1 (0x0002)
44135 +#define MCF_EDMA_EEI_EEI2 (0x0004)
44136 +#define MCF_EDMA_EEI_EEI3 (0x0008)
44137 +#define MCF_EDMA_EEI_EEI4 (0x0010)
44138 +#define MCF_EDMA_EEI_EEI5 (0x0020)
44139 +#define MCF_EDMA_EEI_EEI6 (0x0040)
44140 +#define MCF_EDMA_EEI_EEI7 (0x0080)
44141 +#define MCF_EDMA_EEI_EEI8 (0x0100)
44142 +#define MCF_EDMA_EEI_EEI9 (0x0200)
44143 +#define MCF_EDMA_EEI_EEI10 (0x0400)
44144 +#define MCF_EDMA_EEI_EEI11 (0x0800)
44145 +#define MCF_EDMA_EEI_EEI12 (0x1000)
44146 +#define MCF_EDMA_EEI_EEI13 (0x2000)
44147 +#define MCF_EDMA_EEI_EEI14 (0x4000)
44148 +#define MCF_EDMA_EEI_EEI15 (0x8000)
44149 +
44150 +/* Bit definitions and macros for SERQ */
44151 +#define MCF_EDMA_SERQ_SERQ(x) (((x)&0x0F))
44152 +#define MCF_EDMA_SERQ_SAER (0x40)
44153 +
44154 +/* Bit definitions and macros for CERQ */
44155 +#define MCF_EDMA_CERQ_CERQ(x) (((x)&0x0F))
44156 +#define MCF_EDMA_CERQ_CAER (0x40)
44157 +
44158 +/* Bit definitions and macros for SEEI */
44159 +#define MCF_EDMA_SEEI_SEEI(x) (((x)&0x0F))
44160 +#define MCF_EDMA_SEEI_SAEE (0x40)
44161 +
44162 +/* Bit definitions and macros for CEEI */
44163 +#define MCF_EDMA_CEEI_CEEI(x) (((x)&0x0F))
44164 +#define MCF_EDMA_CEEI_CAEE (0x40)
44165 +
44166 +/* Bit definitions and macros for CINT */
44167 +#define MCF_EDMA_CINT_CINT(x) (((x)&0x0F))
44168 +#define MCF_EDMA_CINT_CAIR (0x40)
44169 +
44170 +/* Bit definitions and macros for CERR */
44171 +#define MCF_EDMA_CERR_CERR(x) (((x)&0x0F))
44172 +#define MCF_EDMA_CERR_CAER (0x40)
44173 +
44174 +/* Bit definitions and macros for SSRT */
44175 +#define MCF_EDMA_SSRT_SSRT(x) (((x)&0x0F))
44176 +#define MCF_EDMA_SSRT_SAST (0x40)
44177 +
44178 +/* Bit definitions and macros for CDNE */
44179 +#define MCF_EDMA_CDNE_CDNE(x) (((x)&0x0F))
44180 +#define MCF_EDMA_CDNE_CADN (0x40)
44181 +
44182 +/* Bit definitions and macros for INTR */
44183 +#define MCF_EDMA_INTR_INT0 (0x0001)
44184 +#define MCF_EDMA_INTR_INT1 (0x0002)
44185 +#define MCF_EDMA_INTR_INT2 (0x0004)
44186 +#define MCF_EDMA_INTR_INT3 (0x0008)
44187 +#define MCF_EDMA_INTR_INT4 (0x0010)
44188 +#define MCF_EDMA_INTR_INT5 (0x0020)
44189 +#define MCF_EDMA_INTR_INT6 (0x0040)
44190 +#define MCF_EDMA_INTR_INT7 (0x0080)
44191 +#define MCF_EDMA_INTR_INT8 (0x0100)
44192 +#define MCF_EDMA_INTR_INT9 (0x0200)
44193 +#define MCF_EDMA_INTR_INT10 (0x0400)
44194 +#define MCF_EDMA_INTR_INT11 (0x0800)
44195 +#define MCF_EDMA_INTR_INT12 (0x1000)
44196 +#define MCF_EDMA_INTR_INT13 (0x2000)
44197 +#define MCF_EDMA_INTR_INT14 (0x4000)
44198 +#define MCF_EDMA_INTR_INT15 (0x8000)
44199 +
44200 +/* Bit definitions and macros for ERR */
44201 +#define MCF_EDMA_ERR_ERR0 (0x0001)
44202 +#define MCF_EDMA_ERR_ERR1 (0x0002)
44203 +#define MCF_EDMA_ERR_ERR2 (0x0004)
44204 +#define MCF_EDMA_ERR_ERR3 (0x0008)
44205 +#define MCF_EDMA_ERR_ERR4 (0x0010)
44206 +#define MCF_EDMA_ERR_ERR5 (0x0020)
44207 +#define MCF_EDMA_ERR_ERR6 (0x0040)
44208 +#define MCF_EDMA_ERR_ERR7 (0x0080)
44209 +#define MCF_EDMA_ERR_ERR8 (0x0100)
44210 +#define MCF_EDMA_ERR_ERR9 (0x0200)
44211 +#define MCF_EDMA_ERR_ERR10 (0x0400)
44212 +#define MCF_EDMA_ERR_ERR11 (0x0800)
44213 +#define MCF_EDMA_ERR_ERR12 (0x1000)
44214 +#define MCF_EDMA_ERR_ERR13 (0x2000)
44215 +#define MCF_EDMA_ERR_ERR14 (0x4000)
44216 +#define MCF_EDMA_ERR_ERR15 (0x8000)
44217 +
44218 +/* Bit definitions and macros for DCHPRI group */
44219 +#define MCF_EDMA_DCHPRI_CHPRI(x) (((x)&0x0F))
44220 +#define MCF_EDMA_DCHPRI_ECP (0x80)
44221 +
44222 +/* Bit definitions and macros for DCHPRI0 */
44223 +#define MCF_EDMA_DCHPRI0_CHPRI(x) (((x)&0x0F))
44224 +#define MCF_EDMA_DCHPRI0_ECP (0x80)
44225 +
44226 +/* Bit definitions and macros for DCHPRI1 */
44227 +#define MCF_EDMA_DCHPRI1_CHPRI(x) (((x)&0x0F))
44228 +#define MCF_EDMA_DCHPRI1_ECP (0x80)
44229 +
44230 +/* Bit definitions and macros for DCHPRI2 */
44231 +#define MCF_EDMA_DCHPRI2_CHPRI(x) (((x)&0x0F))
44232 +#define MCF_EDMA_DCHPRI2_ECP (0x80)
44233 +
44234 +/* Bit definitions and macros for DCHPRI3 */
44235 +#define MCF_EDMA_DCHPRI3_CHPRI(x) (((x)&0x0F))
44236 +#define MCF_EDMA_DCHPRI3_ECP (0x80)
44237 +
44238 +/* Bit definitions and macros for DCHPRI4 */
44239 +#define MCF_EDMA_DCHPRI4_CHPRI(x) (((x)&0x0F))
44240 +#define MCF_EDMA_DCHPRI4_ECP (0x80)
44241 +
44242 +/* Bit definitions and macros for DCHPRI5 */
44243 +#define MCF_EDMA_DCHPRI5_CHPRI(x) (((x)&0x0F))
44244 +#define MCF_EDMA_DCHPRI5_ECP (0x80)
44245 +
44246 +/* Bit definitions and macros for DCHPRI6 */
44247 +#define MCF_EDMA_DCHPRI6_CHPRI(x) (((x)&0x0F))
44248 +#define MCF_EDMA_DCHPRI6_ECP (0x80)
44249 +
44250 +/* Bit definitions and macros for DCHPRI7 */
44251 +#define MCF_EDMA_DCHPRI7_CHPRI(x) (((x)&0x0F))
44252 +#define MCF_EDMA_DCHPRI7_ECP (0x80)
44253 +
44254 +/* Bit definitions and macros for DCHPRI8 */
44255 +#define MCF_EDMA_DCHPRI8_CHPRI(x) (((x)&0x0F))
44256 +#define MCF_EDMA_DCHPRI8_ECP (0x80)
44257 +
44258 +/* Bit definitions and macros for DCHPRI9 */
44259 +#define MCF_EDMA_DCHPRI9_CHPRI(x) (((x)&0x0F))
44260 +#define MCF_EDMA_DCHPRI9_ECP (0x80)
44261 +
44262 +/* Bit definitions and macros for DCHPRI10 */
44263 +#define MCF_EDMA_DCHPRI10_CHPRI(x) (((x)&0x0F))
44264 +#define MCF_EDMA_DCHPRI10_ECP (0x80)
44265 +
44266 +/* Bit definitions and macros for DCHPRI11 */
44267 +#define MCF_EDMA_DCHPRI11_CHPRI(x) (((x)&0x0F))
44268 +#define MCF_EDMA_DCHPRI11_ECP (0x80)
44269 +
44270 +/* Bit definitions and macros for DCHPRI12 */
44271 +#define MCF_EDMA_DCHPRI12_CHPRI(x) (((x)&0x0F))
44272 +#define MCF_EDMA_DCHPRI12_ECP (0x80)
44273 +
44274 +/* Bit definitions and macros for DCHPRI13 */
44275 +#define MCF_EDMA_DCHPRI13_CHPRI(x) (((x)&0x0F))
44276 +#define MCF_EDMA_DCHPRI13_ECP (0x80)
44277 +
44278 +/* Bit definitions and macros for DCHPRI14 */
44279 +#define MCF_EDMA_DCHPRI14_CHPRI(x) (((x)&0x0F))
44280 +#define MCF_EDMA_DCHPRI14_ECP (0x80)
44281 +
44282 +/* Bit definitions and macros for DCHPRI15 */
44283 +#define MCF_EDMA_DCHPRI15_CHPRI(x) (((x)&0x0F))
44284 +#define MCF_EDMA_DCHPRI15_ECP (0x80)
44285 +
44286 +/* Bit definitions and macros for TCD_SADDR group */
44287 +#define MCF_EDMA_TCD_SADDR_SADDR(x) (x)
44288 +
44289 +/* Bit definitions and macros for TCD0_SADDR */
44290 +#define MCF_EDMA_TCD0_SADDR_SADDR(x) (x)
44291 +
44292 +/* Bit definitions and macros for TCD_ATTR group */
44293 +#define MCF_EDMA_TCD_ATTR_DSIZE(x) (((x)&0x0007))
44294 +#define MCF_EDMA_TCD_ATTR_DMOD(x) (((x)&0x001F)<<3)
44295 +#define MCF_EDMA_TCD_ATTR_SSIZE(x) (((x)&0x0007)<<8)
44296 +#define MCF_EDMA_TCD_ATTR_SMOD(x) (((x)&0x001F)<<11)
44297 +#define MCF_EDMA_TCD_ATTR_SSIZE_8BIT (0x0000)
44298 +#define MCF_EDMA_TCD_ATTR_SSIZE_16BIT (0x0100)
44299 +#define MCF_EDMA_TCD_ATTR_SSIZE_32BIT (0x0200)
44300 +#define MCF_EDMA_TCD_ATTR_SSIZE_16BYTE (0x0400)
44301 +#define MCF_EDMA_TCD_ATTR_DSIZE_8BIT (0x0000)
44302 +#define MCF_EDMA_TCD_ATTR_DSIZE_16BIT (0x0001)
44303 +#define MCF_EDMA_TCD_ATTR_DSIZE_32BIT (0x0002)
44304 +#define MCF_EDMA_TCD_ATTR_DSIZE_16BYTE (0x0004)
44305 +
44306 +/* Bit definitions and macros for TCD0_ATTR */
44307 +#define MCF_EDMA_TCD0_ATTR_DSIZE(x) (((x)&0x0007))
44308 +#define MCF_EDMA_TCD0_ATTR_DMOD(x) (((x)&0x001F)<<3)
44309 +#define MCF_EDMA_TCD0_ATTR_SSIZE(x) (((x)&0x0007)<<8)
44310 +#define MCF_EDMA_TCD0_ATTR_SMOD(x) (((x)&0x001F)<<11)
44311 +#define MCF_EDMA_TCD0_ATTR_SSIZE_8BIT (0x0000)
44312 +#define MCF_EDMA_TCD0_ATTR_SSIZE_16BIT (0x0100)
44313 +#define MCF_EDMA_TCD0_ATTR_SSIZE_32BIT (0x0200)
44314 +#define MCF_EDMA_TCD0_ATTR_SSIZE_16BYTE (0x0400)
44315 +#define MCF_EDMA_TCD0_ATTR_DSIZE_8BIT (0x0000)
44316 +#define MCF_EDMA_TCD0_ATTR_DSIZE_16BIT (0x0001)
44317 +#define MCF_EDMA_TCD0_ATTR_DSIZE_32BIT (0x0002)
44318 +#define MCF_EDMA_TCD0_ATTR_DSIZE_16BYTE (0x0004)
44319 +
44320 +/* Bit definitions and macros for TCD_SOFF group */
44321 +#define MCF_EDMA_TCD_SOFF_SOFF(x) (x)
44322 +
44323 +/* Bit definitions and macros for TCD0_SOFF */
44324 +#define MCF_EDMA_TCD0_SOFF_SOFF(x) (x)
44325 +
44326 +/* Bit definitions and macros for TCD_NBYTES group */
44327 +#define MCF_EDMA_TCD_NBYTES_NBYTES(x) (x)
44328 +
44329 +/* Bit definitions and macros for TCD0_NBYTES */
44330 +#define MCF_EDMA_TCD0_NBYTES_NBYTES(x) (x)
44331 +
44332 +/* Bit definitions and macros for TCD_SLAST group */
44333 +#define MCF_EDMA_TCD_SLAST_SLAST(x) (x)
44334 +
44335 +/* Bit definitions and macros for TCD0_SLAST */
44336 +#define MCF_EDMA_TCD0_SLAST_SLAST(x) (x)
44337 +
44338 +/* Bit definitions and macros for TCD_DADDR group */
44339 +#define MCF_EDMA_TCD_DADDR_DADDR(x) (x)
44340 +
44341 +/* Bit definitions and macros for TCD0_DADDR */
44342 +#define MCF_EDMA_TCD0_DADDR_DADDR(x) (x)
44343 +
44344 +/* Bit definitions and macros for TCD_CITER_ELINK group */
44345 +#define MCF_EDMA_TCD_CITER_ELINK_CITER(x) (((x)&0x01FF))
44346 +#define MCF_EDMA_TCD_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
44347 +#define MCF_EDMA_TCD_CITER_ELINK_E_LINK (0x8000)
44348 +
44349 +/* Bit definitions and macros for TCD0_CITER_ELINK */
44350 +#define MCF_EDMA_TCD0_CITER_ELINK_CITER(x) (((x)&0x01FF))
44351 +#define MCF_EDMA_TCD0_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
44352 +#define MCF_EDMA_TCD0_CITER_ELINK_E_LINK (0x8000)
44353 +
44354 +/* Bit definitions and macros for TCD_CITER group */
44355 +#define MCF_EDMA_TCD_CITER_CITER(x) (((x)&0x7FFF))
44356 +#define MCF_EDMA_TCD_CITER_E_LINK (0x8000)
44357 +
44358 +/* Bit definitions and macros for TCD0_CITER */
44359 +#define MCF_EDMA_TCD0_CITER_CITER(x) (((x)&0x7FFF))
44360 +#define MCF_EDMA_TCD0_CITER_E_LINK (0x8000)
44361 +
44362 +/* Bit definitions and macros for TCD_DOFF group */
44363 +#define MCF_EDMA_TCD_DOFF_DOFF(x) (x)
44364 +
44365 +/* Bit definitions and macros for TCD0_DOFF */
44366 +#define MCF_EDMA_TCD0_DOFF_DOFF(x) (x)
44367 +
44368 +/* Bit definitions and macros for TCD_DLAST_SGA group */
44369 +#define MCF_EDMA_TCD_DLAST_SGA_DLAST_SGA(x) (x)
44370 +
44371 +/* Bit definitions and macros for TCD0_DLAST_SGA */
44372 +#define MCF_EDMA_TCD0_DLAST_SGA_DLAST_SGA(x) (x)
44373 +
44374 +/* Bit definitions and macros for TCD_BITER_ELINK group */
44375 +#define MCF_EDMA_TCD_BITER_ELINK_BITER(x) (((x)&0x01FF))
44376 +#define MCF_EDMA_TCD_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
44377 +#define MCF_EDMA_TCD_BITER_ELINK_E_LINK (0x8000)
44378 +
44379 +/* Bit definitions and macros for TCD0_BITER_ELINK */
44380 +#define MCF_EDMA_TCD0_BITER_ELINK_BITER(x) (((x)&0x01FF))
44381 +#define MCF_EDMA_TCD0_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
44382 +#define MCF_EDMA_TCD0_BITER_ELINK_E_LINK (0x8000)
44383 +
44384 +/* Bit definitions and macros for TCD_BITER group */
44385 +#define MCF_EDMA_TCD_BITER_BITER(x) (((x)&0x7FFF))
44386 +#define MCF_EDMA_TCD_BITER_E_LINK (0x8000)
44387 +
44388 +/* Bit definitions and macros for TCD0_BITER */
44389 +#define MCF_EDMA_TCD0_BITER_BITER(x) (((x)&0x7FFF))
44390 +#define MCF_EDMA_TCD0_BITER_E_LINK (0x8000)
44391 +
44392 +/* Bit definitions and macros for TCD_CSR group */
44393 +#define MCF_EDMA_TCD_CSR_START (0x0001)
44394 +#define MCF_EDMA_TCD_CSR_INT_MAJOR (0x0002)
44395 +#define MCF_EDMA_TCD_CSR_INT_HALF (0x0004)
44396 +#define MCF_EDMA_TCD_CSR_D_REQ (0x0008)
44397 +#define MCF_EDMA_TCD_CSR_E_SG (0x0010)
44398 +#define MCF_EDMA_TCD_CSR_E_LINK (0x0020)
44399 +#define MCF_EDMA_TCD_CSR_ACTIVE (0x0040)
44400 +#define MCF_EDMA_TCD_CSR_DONE (0x0080)
44401 +#define MCF_EDMA_TCD_CSR_LINKCH(x) (((x)&0x003F)<<8)
44402 +#define MCF_EDMA_TCD_CSR_BWC(x) (((x)&0x0003)<<14)
44403 +#define MCF_EDMA_TCD_CSR_BWC_NO_STALL (0x0000)
44404 +#define MCF_EDMA_TCD_CSR_BWC_4CYC_STALL (0x8000)
44405 +#define MCF_EDMA_TCD_CSR_BWC_8CYC_STALL (0xC000)
44406 +
44407 +/* Bit definitions and macros for TCD0_CSR */
44408 +#define MCF_EDMA_TCD0_CSR_START (0x0001)
44409 +#define MCF_EDMA_TCD0_CSR_INT_MAJOR (0x0002)
44410 +#define MCF_EDMA_TCD0_CSR_INT_HALF (0x0004)
44411 +#define MCF_EDMA_TCD0_CSR_D_REQ (0x0008)
44412 +#define MCF_EDMA_TCD0_CSR_E_SG (0x0010)
44413 +#define MCF_EDMA_TCD0_CSR_E_LINK (0x0020)
44414 +#define MCF_EDMA_TCD0_CSR_ACTIVE (0x0040)
44415 +#define MCF_EDMA_TCD0_CSR_DONE (0x0080)
44416 +#define MCF_EDMA_TCD0_CSR_LINKCH(x) (((x)&0x003F)<<8)
44417 +#define MCF_EDMA_TCD0_CSR_BWC(x) (((x)&0x0003)<<14)
44418 +#define MCF_EDMA_TCD0_CSR_BWC_NO_STALL (0x0000)
44419 +#define MCF_EDMA_TCD0_CSR_BWC_4CYC_STALL (0x8000)
44420 +#define MCF_EDMA_TCD0_CSR_BWC_8CYC_STALL (0xC000)
44421 +
44422 +/* Bit definitions and macros for TCD1_SADDR */
44423 +#define MCF_EDMA_TCD1_SADDR_SADDR(x) (x)
44424 +
44425 +/* Bit definitions and macros for TCD1_ATTR */
44426 +#define MCF_EDMA_TCD1_ATTR_DSIZE(x) (((x)&0x0007))
44427 +#define MCF_EDMA_TCD1_ATTR_DMOD(x) (((x)&0x001F)<<3)
44428 +#define MCF_EDMA_TCD1_ATTR_SSIZE(x) (((x)&0x0007)<<8)
44429 +#define MCF_EDMA_TCD1_ATTR_SMOD(x) (((x)&0x001F)<<11)
44430 +
44431 +/* Bit definitions and macros for TCD1_SOFF */
44432 +#define MCF_EDMA_TCD1_SOFF_SOFF(x) (x)
44433 +
44434 +/* Bit definitions and macros for TCD1_NBYTES */
44435 +#define MCF_EDMA_TCD1_NBYTES_NBYTES(x) (x)
44436 +
44437 +/* Bit definitions and macros for TCD1_SLAST */
44438 +#define MCF_EDMA_TCD1_SLAST_SLAST(x) (x)
44439 +
44440 +/* Bit definitions and macros for TCD1_DADDR */
44441 +#define MCF_EDMA_TCD1_DADDR_DADDR(x) (x)
44442 +
44443 +/* Bit definitions and macros for TCD1_CITER_ELINK */
44444 +#define MCF_EDMA_TCD1_CITER_ELINK_CITER(x) (((x)&0x01FF))
44445 +#define MCF_EDMA_TCD1_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
44446 +#define MCF_EDMA_TCD1_CITER_ELINK_E_LINK (0x8000)
44447 +
44448 +/* Bit definitions and macros for TCD1_CITER */
44449 +#define MCF_EDMA_TCD1_CITER_CITER(x) (((x)&0x7FFF))
44450 +#define MCF_EDMA_TCD1_CITER_E_LINK (0x8000)
44451 +
44452 +/* Bit definitions and macros for TCD1_DOFF */
44453 +#define MCF_EDMA_TCD1_DOFF_DOFF(x) (x)
44454 +
44455 +/* Bit definitions and macros for TCD1_DLAST_SGA */
44456 +#define MCF_EDMA_TCD1_DLAST_SGA_DLAST_SGA(x) (x)
44457 +
44458 +/* Bit definitions and macros for TCD1_BITER */
44459 +#define MCF_EDMA_TCD1_BITER_BITER(x) (((x)&0x7FFF))
44460 +#define MCF_EDMA_TCD1_BITER_E_LINK (0x8000)
44461 +
44462 +/* Bit definitions and macros for TCD1_BITER_ELINK */
44463 +#define MCF_EDMA_TCD1_BITER_ELINK_BITER(x) (((x)&0x01FF))
44464 +#define MCF_EDMA_TCD1_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
44465 +#define MCF_EDMA_TCD1_BITER_ELINK_E_LINK (0x8000)
44466 +
44467 +/* Bit definitions and macros for TCD1_CSR */
44468 +#define MCF_EDMA_TCD1_CSR_START (0x0001)
44469 +#define MCF_EDMA_TCD1_CSR_INT_MAJOR (0x0002)
44470 +#define MCF_EDMA_TCD1_CSR_INT_HALF (0x0004)
44471 +#define MCF_EDMA_TCD1_CSR_D_REQ (0x0008)
44472 +#define MCF_EDMA_TCD1_CSR_E_SG (0x0010)
44473 +#define MCF_EDMA_TCD1_CSR_E_LINK (0x0020)
44474 +#define MCF_EDMA_TCD1_CSR_ACTIVE (0x0040)
44475 +#define MCF_EDMA_TCD1_CSR_DONE (0x0080)
44476 +#define MCF_EDMA_TCD1_CSR_LINKCH(x) (((x)&0x003F)<<8)
44477 +#define MCF_EDMA_TCD1_CSR_BWC(x) (((x)&0x0003)<<14)
44478 +
44479 +/* Bit definitions and macros for TCD2_SADDR */
44480 +#define MCF_EDMA_TCD2_SADDR_SADDR(x) (x)
44481 +
44482 +/* Bit definitions and macros for TCD2_ATTR */
44483 +#define MCF_EDMA_TCD2_ATTR_DSIZE(x) (((x)&0x0007))
44484 +#define MCF_EDMA_TCD2_ATTR_DMOD(x) (((x)&0x001F)<<3)
44485 +#define MCF_EDMA_TCD2_ATTR_SSIZE(x) (((x)&0x0007)<<8)
44486 +#define MCF_EDMA_TCD2_ATTR_SMOD(x) (((x)&0x001F)<<11)
44487 +
44488 +/* Bit definitions and macros for TCD2_SOFF */
44489 +#define MCF_EDMA_TCD2_SOFF_SOFF(x) (x)
44490 +
44491 +/* Bit definitions and macros for TCD2_NBYTES */
44492 +#define MCF_EDMA_TCD2_NBYTES_NBYTES(x) (x)
44493 +
44494 +/* Bit definitions and macros for TCD2_SLAST */
44495 +#define MCF_EDMA_TCD2_SLAST_SLAST(x) (x)
44496 +
44497 +/* Bit definitions and macros for TCD2_DADDR */
44498 +#define MCF_EDMA_TCD2_DADDR_DADDR(x) (x)
44499 +
44500 +/* Bit definitions and macros for TCD2_CITER */
44501 +#define MCF_EDMA_TCD2_CITER_CITER(x) (((x)&0x7FFF))
44502 +#define MCF_EDMA_TCD2_CITER_E_LINK (0x8000)
44503 +
44504 +/* Bit definitions and macros for TCD2_CITER_ELINK */
44505 +#define MCF_EDMA_TCD2_CITER_ELINK_CITER(x) (((x)&0x01FF))
44506 +#define MCF_EDMA_TCD2_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
44507 +#define MCF_EDMA_TCD2_CITER_ELINK_E_LINK (0x8000)
44508 +
44509 +/* Bit definitions and macros for TCD2_DOFF */
44510 +#define MCF_EDMA_TCD2_DOFF_DOFF(x) (x)
44511 +
44512 +/* Bit definitions and macros for TCD2_DLAST_SGA */
44513 +#define MCF_EDMA_TCD2_DLAST_SGA_DLAST_SGA(x) (x)
44514 +
44515 +/* Bit definitions and macros for TCD2_BITER_ELINK */
44516 +#define MCF_EDMA_TCD2_BITER_ELINK_BITER(x) (((x)&0x01FF))
44517 +#define MCF_EDMA_TCD2_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
44518 +#define MCF_EDMA_TCD2_BITER_ELINK_E_LINK (0x8000)
44519 +
44520 +/* Bit definitions and macros for TCD2_BITER */
44521 +#define MCF_EDMA_TCD2_BITER_BITER(x) (((x)&0x7FFF))
44522 +#define MCF_EDMA_TCD2_BITER_E_LINK (0x8000)
44523 +
44524 +/* Bit definitions and macros for TCD2_CSR */
44525 +#define MCF_EDMA_TCD2_CSR_START (0x0001)
44526 +#define MCF_EDMA_TCD2_CSR_INT_MAJOR (0x0002)
44527 +#define MCF_EDMA_TCD2_CSR_INT_HALF (0x0004)
44528 +#define MCF_EDMA_TCD2_CSR_D_REQ (0x0008)
44529 +#define MCF_EDMA_TCD2_CSR_E_SG (0x0010)
44530 +#define MCF_EDMA_TCD2_CSR_E_LINK (0x0020)
44531 +#define MCF_EDMA_TCD2_CSR_ACTIVE (0x0040)
44532 +#define MCF_EDMA_TCD2_CSR_DONE (0x0080)
44533 +#define MCF_EDMA_TCD2_CSR_LINKCH(x) (((x)&0x003F)<<8)
44534 +#define MCF_EDMA_TCD2_CSR_BWC(x) (((x)&0x0003)<<14)
44535 +
44536 +/* Bit definitions and macros for TCD3_SADDR */
44537 +#define MCF_EDMA_TCD3_SADDR_SADDR(x) (x)
44538 +
44539 +/* Bit definitions and macros for TCD3_ATTR */
44540 +#define MCF_EDMA_TCD3_ATTR_DSIZE(x) (((x)&0x0007))
44541 +#define MCF_EDMA_TCD3_ATTR_DMOD(x) (((x)&0x001F)<<3)
44542 +#define MCF_EDMA_TCD3_ATTR_SSIZE(x) (((x)&0x0007)<<8)
44543 +#define MCF_EDMA_TCD3_ATTR_SMOD(x) (((x)&0x001F)<<11)
44544 +
44545 +/* Bit definitions and macros for TCD3_SOFF */
44546 +#define MCF_EDMA_TCD3_SOFF_SOFF(x) (x)
44547 +
44548 +/* Bit definitions and macros for TCD3_NBYTES */
44549 +#define MCF_EDMA_TCD3_NBYTES_NBYTES(x) (x)
44550 +
44551 +/* Bit definitions and macros for TCD3_SLAST */
44552 +#define MCF_EDMA_TCD3_SLAST_SLAST(x) (x)
44553 +
44554 +/* Bit definitions and macros for TCD3_DADDR */
44555 +#define MCF_EDMA_TCD3_DADDR_DADDR(x) (x)
44556 +
44557 +/* Bit definitions and macros for TCD3_CITER */
44558 +#define MCF_EDMA_TCD3_CITER_CITER(x) (((x)&0x7FFF))
44559 +#define MCF_EDMA_TCD3_CITER_E_LINK (0x8000)
44560 +
44561 +/* Bit definitions and macros for TCD3_CITER_ELINK */
44562 +#define MCF_EDMA_TCD3_CITER_ELINK_CITER(x) (((x)&0x01FF))
44563 +#define MCF_EDMA_TCD3_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
44564 +#define MCF_EDMA_TCD3_CITER_ELINK_E_LINK (0x8000)
44565 +
44566 +/* Bit definitions and macros for TCD3_DOFF */
44567 +#define MCF_EDMA_TCD3_DOFF_DOFF(x) (x)
44568 +
44569 +/* Bit definitions and macros for TCD3_DLAST_SGA */
44570 +#define MCF_EDMA_TCD3_DLAST_SGA_DLAST_SGA(x) (x)
44571 +
44572 +/* Bit definitions and macros for TCD3_BITER_ELINK */
44573 +#define MCF_EDMA_TCD3_BITER_ELINK_BITER(x) (((x)&0x01FF))
44574 +#define MCF_EDMA_TCD3_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
44575 +#define MCF_EDMA_TCD3_BITER_ELINK_E_LINK (0x8000)
44576 +
44577 +/* Bit definitions and macros for TCD3_BITER */
44578 +#define MCF_EDMA_TCD3_BITER_BITER(x) (((x)&0x7FFF))
44579 +#define MCF_EDMA_TCD3_BITER_E_LINK (0x8000)
44580 +
44581 +/* Bit definitions and macros for TCD3_CSR */
44582 +#define MCF_EDMA_TCD3_CSR_START (0x0001)
44583 +#define MCF_EDMA_TCD3_CSR_INT_MAJOR (0x0002)
44584 +#define MCF_EDMA_TCD3_CSR_INT_HALF (0x0004)
44585 +#define MCF_EDMA_TCD3_CSR_D_REQ (0x0008)
44586 +#define MCF_EDMA_TCD3_CSR_E_SG (0x0010)
44587 +#define MCF_EDMA_TCD3_CSR_E_LINK (0x0020)
44588 +#define MCF_EDMA_TCD3_CSR_ACTIVE (0x0040)
44589 +#define MCF_EDMA_TCD3_CSR_DONE (0x0080)
44590 +#define MCF_EDMA_TCD3_CSR_LINKCH(x) (((x)&0x003F)<<8)
44591 +#define MCF_EDMA_TCD3_CSR_BWC(x) (((x)&0x0003)<<14)
44592 +
44593 +/* Bit definitions and macros for TCD4_SADDR */
44594 +#define MCF_EDMA_TCD4_SADDR_SADDR(x) (x)
44595 +
44596 +/* Bit definitions and macros for TCD4_ATTR */
44597 +#define MCF_EDMA_TCD4_ATTR_DSIZE(x) (((x)&0x0007))
44598 +#define MCF_EDMA_TCD4_ATTR_DMOD(x) (((x)&0x001F)<<3)
44599 +#define MCF_EDMA_TCD4_ATTR_SSIZE(x) (((x)&0x0007)<<8)
44600 +#define MCF_EDMA_TCD4_ATTR_SMOD(x) (((x)&0x001F)<<11)
44601 +
44602 +/* Bit definitions and macros for TCD4_SOFF */
44603 +#define MCF_EDMA_TCD4_SOFF_SOFF(x) (x)
44604 +
44605 +/* Bit definitions and macros for TCD4_NBYTES */
44606 +#define MCF_EDMA_TCD4_NBYTES_NBYTES(x) (x)
44607 +
44608 +/* Bit definitions and macros for TCD4_SLAST */
44609 +#define MCF_EDMA_TCD4_SLAST_SLAST(x) (x)
44610 +
44611 +/* Bit definitions and macros for TCD4_DADDR */
44612 +#define MCF_EDMA_TCD4_DADDR_DADDR(x) (x)
44613 +
44614 +/* Bit definitions and macros for TCD4_CITER */
44615 +#define MCF_EDMA_TCD4_CITER_CITER(x) (((x)&0x7FFF))
44616 +#define MCF_EDMA_TCD4_CITER_E_LINK (0x8000)
44617 +
44618 +/* Bit definitions and macros for TCD4_CITER_ELINK */
44619 +#define MCF_EDMA_TCD4_CITER_ELINK_CITER(x) (((x)&0x01FF))
44620 +#define MCF_EDMA_TCD4_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
44621 +#define MCF_EDMA_TCD4_CITER_ELINK_E_LINK (0x8000)
44622 +
44623 +/* Bit definitions and macros for TCD4_DOFF */
44624 +#define MCF_EDMA_TCD4_DOFF_DOFF(x) (x)
44625 +
44626 +/* Bit definitions and macros for TCD4_DLAST_SGA */
44627 +#define MCF_EDMA_TCD4_DLAST_SGA_DLAST_SGA(x) (x)
44628 +
44629 +/* Bit definitions and macros for TCD4_BITER */
44630 +#define MCF_EDMA_TCD4_BITER_BITER(x) (((x)&0x7FFF))
44631 +#define MCF_EDMA_TCD4_BITER_E_LINK (0x8000)
44632 +
44633 +/* Bit definitions and macros for TCD4_BITER_ELINK */
44634 +#define MCF_EDMA_TCD4_BITER_ELINK_BITER(x) (((x)&0x01FF))
44635 +#define MCF_EDMA_TCD4_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
44636 +#define MCF_EDMA_TCD4_BITER_ELINK_E_LINK (0x8000)
44637 +
44638 +/* Bit definitions and macros for TCD4_CSR */
44639 +#define MCF_EDMA_TCD4_CSR_START (0x0001)
44640 +#define MCF_EDMA_TCD4_CSR_INT_MAJOR (0x0002)
44641 +#define MCF_EDMA_TCD4_CSR_INT_HALF (0x0004)
44642 +#define MCF_EDMA_TCD4_CSR_D_REQ (0x0008)
44643 +#define MCF_EDMA_TCD4_CSR_E_SG (0x0010)
44644 +#define MCF_EDMA_TCD4_CSR_E_LINK (0x0020)
44645 +#define MCF_EDMA_TCD4_CSR_ACTIVE (0x0040)
44646 +#define MCF_EDMA_TCD4_CSR_DONE (0x0080)
44647 +#define MCF_EDMA_TCD4_CSR_LINKCH(x) (((x)&0x003F)<<8)
44648 +#define MCF_EDMA_TCD4_CSR_BWC(x) (((x)&0x0003)<<14)
44649 +
44650 +/* Bit definitions and macros for TCD5_SADDR */
44651 +#define MCF_EDMA_TCD5_SADDR_SADDR(x) (x)
44652 +
44653 +/* Bit definitions and macros for TCD5_ATTR */
44654 +#define MCF_EDMA_TCD5_ATTR_DSIZE(x) (((x)&0x0007))
44655 +#define MCF_EDMA_TCD5_ATTR_DMOD(x) (((x)&0x001F)<<3)
44656 +#define MCF_EDMA_TCD5_ATTR_SSIZE(x) (((x)&0x0007)<<8)
44657 +#define MCF_EDMA_TCD5_ATTR_SMOD(x) (((x)&0x001F)<<11)
44658 +
44659 +/* Bit definitions and macros for TCD5_SOFF */
44660 +#define MCF_EDMA_TCD5_SOFF_SOFF(x) (x)
44661 +
44662 +/* Bit definitions and macros for TCD5_NBYTES */
44663 +#define MCF_EDMA_TCD5_NBYTES_NBYTES(x) (x)
44664 +
44665 +/* Bit definitions and macros for TCD5_SLAST */
44666 +#define MCF_EDMA_TCD5_SLAST_SLAST(x) (x)
44667 +
44668 +/* Bit definitions and macros for TCD5_DADDR */
44669 +#define MCF_EDMA_TCD5_DADDR_DADDR(x) (x)
44670 +
44671 +/* Bit definitions and macros for TCD5_CITER */
44672 +#define MCF_EDMA_TCD5_CITER_CITER(x) (((x)&0x7FFF))
44673 +#define MCF_EDMA_TCD5_CITER_E_LINK (0x8000)
44674 +
44675 +/* Bit definitions and macros for TCD5_CITER_ELINK */
44676 +#define MCF_EDMA_TCD5_CITER_ELINK_CITER(x) (((x)&0x01FF))
44677 +#define MCF_EDMA_TCD5_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
44678 +#define MCF_EDMA_TCD5_CITER_ELINK_E_LINK (0x8000)
44679 +
44680 +/* Bit definitions and macros for TCD5_DOFF */
44681 +#define MCF_EDMA_TCD5_DOFF_DOFF(x) (x)
44682 +
44683 +/* Bit definitions and macros for TCD5_DLAST_SGA */
44684 +#define MCF_EDMA_TCD5_DLAST_SGA_DLAST_SGA(x) (x)
44685 +
44686 +/* Bit definitions and macros for TCD5_BITER_ELINK */
44687 +#define MCF_EDMA_TCD5_BITER_ELINK_BITER(x) (((x)&0x01FF))
44688 +#define MCF_EDMA_TCD5_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
44689 +#define MCF_EDMA_TCD5_BITER_ELINK_E_LINK (0x8000)
44690 +
44691 +/* Bit definitions and macros for TCD5_BITER */
44692 +#define MCF_EDMA_TCD5_BITER_BITER(x) (((x)&0x7FFF))
44693 +#define MCF_EDMA_TCD5_BITER_E_LINK (0x8000)
44694 +
44695 +/* Bit definitions and macros for TCD5_CSR */
44696 +#define MCF_EDMA_TCD5_CSR_START (0x0001)
44697 +#define MCF_EDMA_TCD5_CSR_INT_MAJOR (0x0002)
44698 +#define MCF_EDMA_TCD5_CSR_INT_HALF (0x0004)
44699 +#define MCF_EDMA_TCD5_CSR_D_REQ (0x0008)
44700 +#define MCF_EDMA_TCD5_CSR_E_SG (0x0010)
44701 +#define MCF_EDMA_TCD5_CSR_E_LINK (0x0020)
44702 +#define MCF_EDMA_TCD5_CSR_ACTIVE (0x0040)
44703 +#define MCF_EDMA_TCD5_CSR_DONE (0x0080)
44704 +#define MCF_EDMA_TCD5_CSR_LINKCH(x) (((x)&0x003F)<<8)
44705 +#define MCF_EDMA_TCD5_CSR_BWC(x) (((x)&0x0003)<<14)
44706 +
44707 +/* Bit definitions and macros for TCD6_SADDR */
44708 +#define MCF_EDMA_TCD6_SADDR_SADDR(x) (x)
44709 +
44710 +/* Bit definitions and macros for TCD6_ATTR */
44711 +#define MCF_EDMA_TCD6_ATTR_DSIZE(x) (((x)&0x0007))
44712 +#define MCF_EDMA_TCD6_ATTR_DMOD(x) (((x)&0x001F)<<3)
44713 +#define MCF_EDMA_TCD6_ATTR_SSIZE(x) (((x)&0x0007)<<8)
44714 +#define MCF_EDMA_TCD6_ATTR_SMOD(x) (((x)&0x001F)<<11)
44715 +
44716 +/* Bit definitions and macros for TCD6_SOFF */
44717 +#define MCF_EDMA_TCD6_SOFF_SOFF(x) (x)
44718 +
44719 +/* Bit definitions and macros for TCD6_NBYTES */
44720 +#define MCF_EDMA_TCD6_NBYTES_NBYTES(x) (x)
44721 +
44722 +/* Bit definitions and macros for TCD6_SLAST */
44723 +#define MCF_EDMA_TCD6_SLAST_SLAST(x) (x)
44724 +
44725 +/* Bit definitions and macros for TCD6_DADDR */
44726 +#define MCF_EDMA_TCD6_DADDR_DADDR(x) (x)
44727 +
44728 +/* Bit definitions and macros for TCD6_CITER */
44729 +#define MCF_EDMA_TCD6_CITER_CITER(x) (((x)&0x7FFF))
44730 +#define MCF_EDMA_TCD6_CITER_E_LINK (0x8000)
44731 +
44732 +/* Bit definitions and macros for TCD6_CITER_ELINK */
44733 +#define MCF_EDMA_TCD6_CITER_ELINK_CITER(x) (((x)&0x01FF))
44734 +#define MCF_EDMA_TCD6_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
44735 +#define MCF_EDMA_TCD6_CITER_ELINK_E_LINK (0x8000)
44736 +
44737 +/* Bit definitions and macros for TCD6_DOFF */
44738 +#define MCF_EDMA_TCD6_DOFF_DOFF(x) (x)
44739 +
44740 +/* Bit definitions and macros for TCD6_DLAST_SGA */
44741 +#define MCF_EDMA_TCD6_DLAST_SGA_DLAST_SGA(x) (x)
44742 +
44743 +/* Bit definitions and macros for TCD6_BITER_ELINK */
44744 +#define MCF_EDMA_TCD6_BITER_ELINK_BITER(x) (((x)&0x01FF))
44745 +#define MCF_EDMA_TCD6_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
44746 +#define MCF_EDMA_TCD6_BITER_ELINK_E_LINK (0x8000)
44747 +
44748 +/* Bit definitions and macros for TCD6_BITER */
44749 +#define MCF_EDMA_TCD6_BITER_BITER(x) (((x)&0x7FFF))
44750 +#define MCF_EDMA_TCD6_BITER_E_LINK (0x8000)
44751 +
44752 +/* Bit definitions and macros for TCD6_CSR */
44753 +#define MCF_EDMA_TCD6_CSR_START (0x0001)
44754 +#define MCF_EDMA_TCD6_CSR_INT_MAJOR (0x0002)
44755 +#define MCF_EDMA_TCD6_CSR_INT_HALF (0x0004)
44756 +#define MCF_EDMA_TCD6_CSR_D_REQ (0x0008)
44757 +#define MCF_EDMA_TCD6_CSR_E_SG (0x0010)
44758 +#define MCF_EDMA_TCD6_CSR_E_LINK (0x0020)
44759 +#define MCF_EDMA_TCD6_CSR_ACTIVE (0x0040)
44760 +#define MCF_EDMA_TCD6_CSR_DONE (0x0080)
44761 +#define MCF_EDMA_TCD6_CSR_LINKCH(x) (((x)&0x003F)<<8)
44762 +#define MCF_EDMA_TCD6_CSR_BWC(x) (((x)&0x0003)<<14)
44763 +
44764 +/* Bit definitions and macros for TCD7_SADDR */
44765 +#define MCF_EDMA_TCD7_SADDR_SADDR(x) (x)
44766 +
44767 +/* Bit definitions and macros for TCD7_ATTR */
44768 +#define MCF_EDMA_TCD7_ATTR_DSIZE(x) (((x)&0x0007))
44769 +#define MCF_EDMA_TCD7_ATTR_DMOD(x) (((x)&0x001F)<<3)
44770 +#define MCF_EDMA_TCD7_ATTR_SSIZE(x) (((x)&0x0007)<<8)
44771 +#define MCF_EDMA_TCD7_ATTR_SMOD(x) (((x)&0x001F)<<11)
44772 +
44773 +/* Bit definitions and macros for TCD7_SOFF */
44774 +#define MCF_EDMA_TCD7_SOFF_SOFF(x) (x)
44775 +
44776 +/* Bit definitions and macros for TCD7_NBYTES */
44777 +#define MCF_EDMA_TCD7_NBYTES_NBYTES(x) (x)
44778 +
44779 +/* Bit definitions and macros for TCD7_SLAST */
44780 +#define MCF_EDMA_TCD7_SLAST_SLAST(x) (x)
44781 +
44782 +/* Bit definitions and macros for TCD7_DADDR */
44783 +#define MCF_EDMA_TCD7_DADDR_DADDR(x) (x)
44784 +
44785 +/* Bit definitions and macros for TCD7_CITER */
44786 +#define MCF_EDMA_TCD7_CITER_CITER(x) (((x)&0x7FFF))
44787 +#define MCF_EDMA_TCD7_CITER_E_LINK (0x8000)
44788 +
44789 +/* Bit definitions and macros for TCD7_CITER_ELINK */
44790 +#define MCF_EDMA_TCD7_CITER_ELINK_CITER(x) (((x)&0x01FF))
44791 +#define MCF_EDMA_TCD7_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
44792 +#define MCF_EDMA_TCD7_CITER_ELINK_E_LINK (0x8000)
44793 +
44794 +/* Bit definitions and macros for TCD7_DOFF */
44795 +#define MCF_EDMA_TCD7_DOFF_DOFF(x) (x)
44796 +
44797 +/* Bit definitions and macros for TCD7_DLAST_SGA */
44798 +#define MCF_EDMA_TCD7_DLAST_SGA_DLAST_SGA(x) (x)
44799 +
44800 +/* Bit definitions and macros for TCD7_BITER_ELINK */
44801 +#define MCF_EDMA_TCD7_BITER_ELINK_BITER(x) (((x)&0x01FF))
44802 +#define MCF_EDMA_TCD7_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
44803 +#define MCF_EDMA_TCD7_BITER_ELINK_E_LINK (0x8000)
44804 +
44805 +/* Bit definitions and macros for TCD7_BITER */
44806 +#define MCF_EDMA_TCD7_BITER_BITER(x) (((x)&0x7FFF))
44807 +#define MCF_EDMA_TCD7_BITER_E_LINK (0x8000)
44808 +
44809 +/* Bit definitions and macros for TCD7_CSR */
44810 +#define MCF_EDMA_TCD7_CSR_START (0x0001)
44811 +#define MCF_EDMA_TCD7_CSR_INT_MAJOR (0x0002)
44812 +#define MCF_EDMA_TCD7_CSR_INT_HALF (0x0004)
44813 +#define MCF_EDMA_TCD7_CSR_D_REQ (0x0008)
44814 +#define MCF_EDMA_TCD7_CSR_E_SG (0x0010)
44815 +#define MCF_EDMA_TCD7_CSR_E_LINK (0x0020)
44816 +#define MCF_EDMA_TCD7_CSR_ACTIVE (0x0040)
44817 +#define MCF_EDMA_TCD7_CSR_DONE (0x0080)
44818 +#define MCF_EDMA_TCD7_CSR_LINKCH(x) (((x)&0x003F)<<8)
44819 +#define MCF_EDMA_TCD7_CSR_BWC(x) (((x)&0x0003)<<14)
44820 +
44821 +/* Bit definitions and macros for TCD8_SADDR */
44822 +#define MCF_EDMA_TCD8_SADDR_SADDR(x) (x)
44823 +
44824 +/* Bit definitions and macros for TCD8_ATTR */
44825 +#define MCF_EDMA_TCD8_ATTR_DSIZE(x) (((x)&0x0007))
44826 +#define MCF_EDMA_TCD8_ATTR_DMOD(x) (((x)&0x001F)<<3)
44827 +#define MCF_EDMA_TCD8_ATTR_SSIZE(x) (((x)&0x0007)<<8)
44828 +#define MCF_EDMA_TCD8_ATTR_SMOD(x) (((x)&0x001F)<<11)
44829 +
44830 +/* Bit definitions and macros for TCD8_SOFF */
44831 +#define MCF_EDMA_TCD8_SOFF_SOFF(x) (x)
44832 +
44833 +/* Bit definitions and macros for TCD8_NBYTES */
44834 +#define MCF_EDMA_TCD8_NBYTES_NBYTES(x) (x)
44835 +
44836 +/* Bit definitions and macros for TCD8_SLAST */
44837 +#define MCF_EDMA_TCD8_SLAST_SLAST(x) (x)
44838 +
44839 +/* Bit definitions and macros for TCD8_DADDR */
44840 +#define MCF_EDMA_TCD8_DADDR_DADDR(x) (x)
44841 +
44842 +/* Bit definitions and macros for TCD8_CITER */
44843 +#define MCF_EDMA_TCD8_CITER_CITER(x) (((x)&0x7FFF))
44844 +#define MCF_EDMA_TCD8_CITER_E_LINK (0x8000)
44845 +
44846 +/* Bit definitions and macros for TCD8_CITER_ELINK */
44847 +#define MCF_EDMA_TCD8_CITER_ELINK_CITER(x) (((x)&0x01FF))
44848 +#define MCF_EDMA_TCD8_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
44849 +#define MCF_EDMA_TCD8_CITER_ELINK_E_LINK (0x8000)
44850 +
44851 +/* Bit definitions and macros for TCD8_DOFF */
44852 +#define MCF_EDMA_TCD8_DOFF_DOFF(x) (x)
44853 +
44854 +/* Bit definitions and macros for TCD8_DLAST_SGA */
44855 +#define MCF_EDMA_TCD8_DLAST_SGA_DLAST_SGA(x) (x)
44856 +
44857 +/* Bit definitions and macros for TCD8_BITER_ELINK */
44858 +#define MCF_EDMA_TCD8_BITER_ELINK_BITER(x) (((x)&0x01FF))
44859 +#define MCF_EDMA_TCD8_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
44860 +#define MCF_EDMA_TCD8_BITER_ELINK_E_LINK (0x8000)
44861 +
44862 +/* Bit definitions and macros for TCD8_BITER */
44863 +#define MCF_EDMA_TCD8_BITER_BITER(x) (((x)&0x7FFF))
44864 +#define MCF_EDMA_TCD8_BITER_E_LINK (0x8000)
44865 +
44866 +/* Bit definitions and macros for TCD8_CSR */
44867 +#define MCF_EDMA_TCD8_CSR_START (0x0001)
44868 +#define MCF_EDMA_TCD8_CSR_INT_MAJOR (0x0002)
44869 +#define MCF_EDMA_TCD8_CSR_INT_HALF (0x0004)
44870 +#define MCF_EDMA_TCD8_CSR_D_REQ (0x0008)
44871 +#define MCF_EDMA_TCD8_CSR_E_SG (0x0010)
44872 +#define MCF_EDMA_TCD8_CSR_E_LINK (0x0020)
44873 +#define MCF_EDMA_TCD8_CSR_ACTIVE (0x0040)
44874 +#define MCF_EDMA_TCD8_CSR_DONE (0x0080)
44875 +#define MCF_EDMA_TCD8_CSR_LINKCH(x) (((x)&0x003F)<<8)
44876 +#define MCF_EDMA_TCD8_CSR_BWC(x) (((x)&0x0003)<<14)
44877 +
44878 +/* Bit definitions and macros for TCD9_SADDR */
44879 +#define MCF_EDMA_TCD9_SADDR_SADDR(x) (x)
44880 +
44881 +/* Bit definitions and macros for TCD9_ATTR */
44882 +#define MCF_EDMA_TCD9_ATTR_DSIZE(x) (((x)&0x0007))
44883 +#define MCF_EDMA_TCD9_ATTR_DMOD(x) (((x)&0x001F)<<3)
44884 +#define MCF_EDMA_TCD9_ATTR_SSIZE(x) (((x)&0x0007)<<8)
44885 +#define MCF_EDMA_TCD9_ATTR_SMOD(x) (((x)&0x001F)<<11)
44886 +
44887 +/* Bit definitions and macros for TCD9_SOFF */
44888 +#define MCF_EDMA_TCD9_SOFF_SOFF(x) (x)
44889 +
44890 +/* Bit definitions and macros for TCD9_NBYTES */
44891 +#define MCF_EDMA_TCD9_NBYTES_NBYTES(x) (x)
44892 +
44893 +/* Bit definitions and macros for TCD9_SLAST */
44894 +#define MCF_EDMA_TCD9_SLAST_SLAST(x) (x)
44895 +
44896 +/* Bit definitions and macros for TCD9_DADDR */
44897 +#define MCF_EDMA_TCD9_DADDR_DADDR(x) (x)
44898 +
44899 +/* Bit definitions and macros for TCD9_CITER_ELINK */
44900 +#define MCF_EDMA_TCD9_CITER_ELINK_CITER(x) (((x)&0x01FF))
44901 +#define MCF_EDMA_TCD9_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
44902 +#define MCF_EDMA_TCD9_CITER_ELINK_E_LINK (0x8000)
44903 +
44904 +/* Bit definitions and macros for TCD9_CITER */
44905 +#define MCF_EDMA_TCD9_CITER_CITER(x) (((x)&0x7FFF))
44906 +#define MCF_EDMA_TCD9_CITER_E_LINK (0x8000)
44907 +
44908 +/* Bit definitions and macros for TCD9_DOFF */
44909 +#define MCF_EDMA_TCD9_DOFF_DOFF(x) (x)
44910 +
44911 +/* Bit definitions and macros for TCD9_DLAST_SGA */
44912 +#define MCF_EDMA_TCD9_DLAST_SGA_DLAST_SGA(x) (x)
44913 +
44914 +/* Bit definitions and macros for TCD9_BITER_ELINK */
44915 +#define MCF_EDMA_TCD9_BITER_ELINK_BITER(x) (((x)&0x01FF))
44916 +#define MCF_EDMA_TCD9_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
44917 +#define MCF_EDMA_TCD9_BITER_ELINK_E_LINK (0x8000)
44918 +
44919 +/* Bit definitions and macros for TCD9_BITER */
44920 +#define MCF_EDMA_TCD9_BITER_BITER(x) (((x)&0x7FFF))
44921 +#define MCF_EDMA_TCD9_BITER_E_LINK (0x8000)
44922 +
44923 +/* Bit definitions and macros for TCD9_CSR */
44924 +#define MCF_EDMA_TCD9_CSR_START (0x0001)
44925 +#define MCF_EDMA_TCD9_CSR_INT_MAJOR (0x0002)
44926 +#define MCF_EDMA_TCD9_CSR_INT_HALF (0x0004)
44927 +#define MCF_EDMA_TCD9_CSR_D_REQ (0x0008)
44928 +#define MCF_EDMA_TCD9_CSR_E_SG (0x0010)
44929 +#define MCF_EDMA_TCD9_CSR_E_LINK (0x0020)
44930 +#define MCF_EDMA_TCD9_CSR_ACTIVE (0x0040)
44931 +#define MCF_EDMA_TCD9_CSR_DONE (0x0080)
44932 +#define MCF_EDMA_TCD9_CSR_LINKCH(x) (((x)&0x003F)<<8)
44933 +#define MCF_EDMA_TCD9_CSR_BWC(x) (((x)&0x0003)<<14)
44934 +
44935 +/* Bit definitions and macros for TCD10_SADDR */
44936 +#define MCF_EDMA_TCD10_SADDR_SADDR(x) (x)
44937 +
44938 +/* Bit definitions and macros for TCD10_ATTR */
44939 +#define MCF_EDMA_TCD10_ATTR_DSIZE(x) (((x)&0x0007))
44940 +#define MCF_EDMA_TCD10_ATTR_DMOD(x) (((x)&0x001F)<<3)
44941 +#define MCF_EDMA_TCD10_ATTR_SSIZE(x) (((x)&0x0007)<<8)
44942 +#define MCF_EDMA_TCD10_ATTR_SMOD(x) (((x)&0x001F)<<11)
44943 +
44944 +/* Bit definitions and macros for TCD10_SOFF */
44945 +#define MCF_EDMA_TCD10_SOFF_SOFF(x) (x)
44946 +
44947 +/* Bit definitions and macros for TCD10_NBYTES */
44948 +#define MCF_EDMA_TCD10_NBYTES_NBYTES(x) (x)
44949 +
44950 +/* Bit definitions and macros for TCD10_SLAST */
44951 +#define MCF_EDMA_TCD10_SLAST_SLAST(x) (x)
44952 +
44953 +/* Bit definitions and macros for TCD10_DADDR */
44954 +#define MCF_EDMA_TCD10_DADDR_DADDR(x) (x)
44955 +
44956 +/* Bit definitions and macros for TCD10_CITER_ELINK */
44957 +#define MCF_EDMA_TCD10_CITER_ELINK_CITER(x) (((x)&0x01FF))
44958 +#define MCF_EDMA_TCD10_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
44959 +#define MCF_EDMA_TCD10_CITER_ELINK_E_LINK (0x8000)
44960 +
44961 +/* Bit definitions and macros for TCD10_CITER */
44962 +#define MCF_EDMA_TCD10_CITER_CITER(x) (((x)&0x7FFF))
44963 +#define MCF_EDMA_TCD10_CITER_E_LINK (0x8000)
44964 +
44965 +/* Bit definitions and macros for TCD10_DOFF */
44966 +#define MCF_EDMA_TCD10_DOFF_DOFF(x) (x)
44967 +
44968 +/* Bit definitions and macros for TCD10_DLAST_SGA */
44969 +#define MCF_EDMA_TCD10_DLAST_SGA_DLAST_SGA(x) (x)
44970 +
44971 +/* Bit definitions and macros for TCD10_BITER */
44972 +#define MCF_EDMA_TCD10_BITER_BITER(x) (((x)&0x7FFF))
44973 +#define MCF_EDMA_TCD10_BITER_E_LINK (0x8000)
44974 +
44975 +/* Bit definitions and macros for TCD10_BITER_ELINK */
44976 +#define MCF_EDMA_TCD10_BITER_ELINK_BITER(x) (((x)&0x01FF))
44977 +#define MCF_EDMA_TCD10_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
44978 +#define MCF_EDMA_TCD10_BITER_ELINK_E_LINK (0x8000)
44979 +
44980 +/* Bit definitions and macros for TCD10_CSR */
44981 +#define MCF_EDMA_TCD10_CSR_START (0x0001)
44982 +#define MCF_EDMA_TCD10_CSR_INT_MAJOR (0x0002)
44983 +#define MCF_EDMA_TCD10_CSR_INT_HALF (0x0004)
44984 +#define MCF_EDMA_TCD10_CSR_D_REQ (0x0008)
44985 +#define MCF_EDMA_TCD10_CSR_E_SG (0x0010)
44986 +#define MCF_EDMA_TCD10_CSR_E_LINK (0x0020)
44987 +#define MCF_EDMA_TCD10_CSR_ACTIVE (0x0040)
44988 +#define MCF_EDMA_TCD10_CSR_DONE (0x0080)
44989 +#define MCF_EDMA_TCD10_CSR_LINKCH(x) (((x)&0x003F)<<8)
44990 +#define MCF_EDMA_TCD10_CSR_BWC(x) (((x)&0x0003)<<14)
44991 +
44992 +/* Bit definitions and macros for TCD11_SADDR */
44993 +#define MCF_EDMA_TCD11_SADDR_SADDR(x) (x)
44994 +
44995 +/* Bit definitions and macros for TCD11_ATTR */
44996 +#define MCF_EDMA_TCD11_ATTR_DSIZE(x) (((x)&0x0007))
44997 +#define MCF_EDMA_TCD11_ATTR_DMOD(x) (((x)&0x001F)<<3)
44998 +#define MCF_EDMA_TCD11_ATTR_SSIZE(x) (((x)&0x0007)<<8)
44999 +#define MCF_EDMA_TCD11_ATTR_SMOD(x) (((x)&0x001F)<<11)
45000 +
45001 +/* Bit definitions and macros for TCD11_SOFF */
45002 +#define MCF_EDMA_TCD11_SOFF_SOFF(x) (x)
45003 +
45004 +/* Bit definitions and macros for TCD11_NBYTES */
45005 +#define MCF_EDMA_TCD11_NBYTES_NBYTES(x) (x)
45006 +
45007 +/* Bit definitions and macros for TCD11_SLAST */
45008 +#define MCF_EDMA_TCD11_SLAST_SLAST(x) (x)
45009 +
45010 +/* Bit definitions and macros for TCD11_DADDR */
45011 +#define MCF_EDMA_TCD11_DADDR_DADDR(x) (x)
45012 +
45013 +/* Bit definitions and macros for TCD11_CITER */
45014 +#define MCF_EDMA_TCD11_CITER_CITER(x) (((x)&0x7FFF))
45015 +#define MCF_EDMA_TCD11_CITER_E_LINK (0x8000)
45016 +
45017 +/* Bit definitions and macros for TCD11_CITER_ELINK */
45018 +#define MCF_EDMA_TCD11_CITER_ELINK_CITER(x) (((x)&0x01FF))
45019 +#define MCF_EDMA_TCD11_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
45020 +#define MCF_EDMA_TCD11_CITER_ELINK_E_LINK (0x8000)
45021 +
45022 +/* Bit definitions and macros for TCD11_DOFF */
45023 +#define MCF_EDMA_TCD11_DOFF_DOFF(x) (x)
45024 +
45025 +/* Bit definitions and macros for TCD11_DLAST_SGA */
45026 +#define MCF_EDMA_TCD11_DLAST_SGA_DLAST_SGA(x) (x)
45027 +
45028 +/* Bit definitions and macros for TCD11_BITER */
45029 +#define MCF_EDMA_TCD11_BITER_BITER(x) (((x)&0x7FFF))
45030 +#define MCF_EDMA_TCD11_BITER_E_LINK (0x8000)
45031 +
45032 +/* Bit definitions and macros for TCD11_BITER_ELINK */
45033 +#define MCF_EDMA_TCD11_BITER_ELINK_BITER(x) (((x)&0x01FF))
45034 +#define MCF_EDMA_TCD11_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
45035 +#define MCF_EDMA_TCD11_BITER_ELINK_E_LINK (0x8000)
45036 +
45037 +/* Bit definitions and macros for TCD11_CSR */
45038 +#define MCF_EDMA_TCD11_CSR_START (0x0001)
45039 +#define MCF_EDMA_TCD11_CSR_INT_MAJOR (0x0002)
45040 +#define MCF_EDMA_TCD11_CSR_INT_HALF (0x0004)
45041 +#define MCF_EDMA_TCD11_CSR_D_REQ (0x0008)
45042 +#define MCF_EDMA_TCD11_CSR_E_SG (0x0010)
45043 +#define MCF_EDMA_TCD11_CSR_E_LINK (0x0020)
45044 +#define MCF_EDMA_TCD11_CSR_ACTIVE (0x0040)
45045 +#define MCF_EDMA_TCD11_CSR_DONE (0x0080)
45046 +#define MCF_EDMA_TCD11_CSR_LINKCH(x) (((x)&0x003F)<<8)
45047 +#define MCF_EDMA_TCD11_CSR_BWC(x) (((x)&0x0003)<<14)
45048 +
45049 +/* Bit definitions and macros for TCD12_SADDR */
45050 +#define MCF_EDMA_TCD12_SADDR_SADDR(x) (x)
45051 +
45052 +/* Bit definitions and macros for TCD12_ATTR */
45053 +#define MCF_EDMA_TCD12_ATTR_DSIZE(x) (((x)&0x0007))
45054 +#define MCF_EDMA_TCD12_ATTR_DMOD(x) (((x)&0x001F)<<3)
45055 +#define MCF_EDMA_TCD12_ATTR_SSIZE(x) (((x)&0x0007)<<8)
45056 +#define MCF_EDMA_TCD12_ATTR_SMOD(x) (((x)&0x001F)<<11)
45057 +
45058 +/* Bit definitions and macros for TCD12_SOFF */
45059 +#define MCF_EDMA_TCD12_SOFF_SOFF(x) (x)
45060 +
45061 +/* Bit definitions and macros for TCD12_NBYTES */
45062 +#define MCF_EDMA_TCD12_NBYTES_NBYTES(x) (x)
45063 +
45064 +/* Bit definitions and macros for TCD12_SLAST */
45065 +#define MCF_EDMA_TCD12_SLAST_SLAST(x) (x)
45066 +
45067 +/* Bit definitions and macros for TCD12_DADDR */
45068 +#define MCF_EDMA_TCD12_DADDR_DADDR(x) (x)
45069 +
45070 +/* Bit definitions and macros for TCD12_CITER */
45071 +#define MCF_EDMA_TCD12_CITER_CITER(x) (((x)&0x7FFF))
45072 +#define MCF_EDMA_TCD12_CITER_E_LINK (0x8000)
45073 +
45074 +/* Bit definitions and macros for TCD12_CITER_ELINK */
45075 +#define MCF_EDMA_TCD12_CITER_ELINK_CITER(x) (((x)&0x01FF))
45076 +#define MCF_EDMA_TCD12_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
45077 +#define MCF_EDMA_TCD12_CITER_ELINK_E_LINK (0x8000)
45078 +
45079 +/* Bit definitions and macros for TCD12_DOFF */
45080 +#define MCF_EDMA_TCD12_DOFF_DOFF(x) (x)
45081 +
45082 +/* Bit definitions and macros for TCD12_DLAST_SGA */
45083 +#define MCF_EDMA_TCD12_DLAST_SGA_DLAST_SGA(x) (x)
45084 +
45085 +/* Bit definitions and macros for TCD12_BITER */
45086 +#define MCF_EDMA_TCD12_BITER_BITER(x) (((x)&0x7FFF))
45087 +#define MCF_EDMA_TCD12_BITER_E_LINK (0x8000)
45088 +
45089 +/* Bit definitions and macros for TCD12_BITER_ELINK */
45090 +#define MCF_EDMA_TCD12_BITER_ELINK_BITER(x) (((x)&0x01FF))
45091 +#define MCF_EDMA_TCD12_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
45092 +#define MCF_EDMA_TCD12_BITER_ELINK_E_LINK (0x8000)
45093 +
45094 +/* Bit definitions and macros for TCD12_CSR */
45095 +#define MCF_EDMA_TCD12_CSR_START (0x0001)
45096 +#define MCF_EDMA_TCD12_CSR_INT_MAJOR (0x0002)
45097 +#define MCF_EDMA_TCD12_CSR_INT_HALF (0x0004)
45098 +#define MCF_EDMA_TCD12_CSR_D_REQ (0x0008)
45099 +#define MCF_EDMA_TCD12_CSR_E_SG (0x0010)
45100 +#define MCF_EDMA_TCD12_CSR_E_LINK (0x0020)
45101 +#define MCF_EDMA_TCD12_CSR_ACTIVE (0x0040)
45102 +#define MCF_EDMA_TCD12_CSR_DONE (0x0080)
45103 +#define MCF_EDMA_TCD12_CSR_LINKCH(x) (((x)&0x003F)<<8)
45104 +#define MCF_EDMA_TCD12_CSR_BWC(x) (((x)&0x0003)<<14)
45105 +
45106 +/* Bit definitions and macros for TCD13_SADDR */
45107 +#define MCF_EDMA_TCD13_SADDR_SADDR(x) (x)
45108 +
45109 +/* Bit definitions and macros for TCD13_ATTR */
45110 +#define MCF_EDMA_TCD13_ATTR_DSIZE(x) (((x)&0x0007))
45111 +#define MCF_EDMA_TCD13_ATTR_DMOD(x) (((x)&0x001F)<<3)
45112 +#define MCF_EDMA_TCD13_ATTR_SSIZE(x) (((x)&0x0007)<<8)
45113 +#define MCF_EDMA_TCD13_ATTR_SMOD(x) (((x)&0x001F)<<11)
45114 +
45115 +/* Bit definitions and macros for TCD13_SOFF */
45116 +#define MCF_EDMA_TCD13_SOFF_SOFF(x) (x)
45117 +
45118 +/* Bit definitions and macros for TCD13_NBYTES */
45119 +#define MCF_EDMA_TCD13_NBYTES_NBYTES(x) (x)
45120 +
45121 +/* Bit definitions and macros for TCD13_SLAST */
45122 +#define MCF_EDMA_TCD13_SLAST_SLAST(x) (x)
45123 +
45124 +/* Bit definitions and macros for TCD13_DADDR */
45125 +#define MCF_EDMA_TCD13_DADDR_DADDR(x) (x)
45126 +
45127 +/* Bit definitions and macros for TCD13_CITER_ELINK */
45128 +#define MCF_EDMA_TCD13_CITER_ELINK_CITER(x) (((x)&0x01FF))
45129 +#define MCF_EDMA_TCD13_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
45130 +#define MCF_EDMA_TCD13_CITER_ELINK_E_LINK (0x8000)
45131 +
45132 +/* Bit definitions and macros for TCD13_CITER */
45133 +#define MCF_EDMA_TCD13_CITER_CITER(x) (((x)&0x7FFF))
45134 +#define MCF_EDMA_TCD13_CITER_E_LINK (0x8000)
45135 +
45136 +/* Bit definitions and macros for TCD13_DOFF */
45137 +#define MCF_EDMA_TCD13_DOFF_DOFF(x) (x)
45138 +
45139 +/* Bit definitions and macros for TCD13_DLAST_SGA */
45140 +#define MCF_EDMA_TCD13_DLAST_SGA_DLAST_SGA(x) (x)
45141 +
45142 +/* Bit definitions and macros for TCD13_BITER_ELINK */
45143 +#define MCF_EDMA_TCD13_BITER_ELINK_BITER(x) (((x)&0x01FF))
45144 +#define MCF_EDMA_TCD13_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
45145 +#define MCF_EDMA_TCD13_BITER_ELINK_E_LINK (0x8000)
45146 +
45147 +/* Bit definitions and macros for TCD13_BITER */
45148 +#define MCF_EDMA_TCD13_BITER_BITER(x) (((x)&0x7FFF))
45149 +#define MCF_EDMA_TCD13_BITER_E_LINK (0x8000)
45150 +
45151 +/* Bit definitions and macros for TCD13_CSR */
45152 +#define MCF_EDMA_TCD13_CSR_START (0x0001)
45153 +#define MCF_EDMA_TCD13_CSR_INT_MAJOR (0x0002)
45154 +#define MCF_EDMA_TCD13_CSR_INT_HALF (0x0004)
45155 +#define MCF_EDMA_TCD13_CSR_D_REQ (0x0008)
45156 +#define MCF_EDMA_TCD13_CSR_E_SG (0x0010)
45157 +#define MCF_EDMA_TCD13_CSR_E_LINK (0x0020)
45158 +#define MCF_EDMA_TCD13_CSR_ACTIVE (0x0040)
45159 +#define MCF_EDMA_TCD13_CSR_DONE (0x0080)
45160 +#define MCF_EDMA_TCD13_CSR_LINKCH(x) (((x)&0x003F)<<8)
45161 +#define MCF_EDMA_TCD13_CSR_BWC(x) (((x)&0x0003)<<14)
45162 +
45163 +/* Bit definitions and macros for TCD14_SADDR */
45164 +#define MCF_EDMA_TCD14_SADDR_SADDR(x) (x)
45165 +
45166 +/* Bit definitions and macros for TCD14_ATTR */
45167 +#define MCF_EDMA_TCD14_ATTR_DSIZE(x) (((x)&0x0007))
45168 +#define MCF_EDMA_TCD14_ATTR_DMOD(x) (((x)&0x001F)<<3)
45169 +#define MCF_EDMA_TCD14_ATTR_SSIZE(x) (((x)&0x0007)<<8)
45170 +#define MCF_EDMA_TCD14_ATTR_SMOD(x) (((x)&0x001F)<<11)
45171 +
45172 +/* Bit definitions and macros for TCD14_SOFF */
45173 +#define MCF_EDMA_TCD14_SOFF_SOFF(x) (x)
45174 +
45175 +/* Bit definitions and macros for TCD14_NBYTES */
45176 +#define MCF_EDMA_TCD14_NBYTES_NBYTES(x) (x)
45177 +
45178 +/* Bit definitions and macros for TCD14_SLAST */
45179 +#define MCF_EDMA_TCD14_SLAST_SLAST(x) (x)
45180 +
45181 +/* Bit definitions and macros for TCD14_DADDR */
45182 +#define MCF_EDMA_TCD14_DADDR_DADDR(x) (x)
45183 +
45184 +/* Bit definitions and macros for TCD14_CITER */
45185 +#define MCF_EDMA_TCD14_CITER_CITER(x) (((x)&0x7FFF))
45186 +#define MCF_EDMA_TCD14_CITER_E_LINK (0x8000)
45187 +
45188 +/* Bit definitions and macros for TCD14_CITER_ELINK */
45189 +#define MCF_EDMA_TCD14_CITER_ELINK_CITER(x) (((x)&0x01FF))
45190 +#define MCF_EDMA_TCD14_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
45191 +#define MCF_EDMA_TCD14_CITER_ELINK_E_LINK (0x8000)
45192 +
45193 +/* Bit definitions and macros for TCD14_DOFF */
45194 +#define MCF_EDMA_TCD14_DOFF_DOFF(x) (x)
45195 +
45196 +/* Bit definitions and macros for TCD14_DLAST_SGA */
45197 +#define MCF_EDMA_TCD14_DLAST_SGA_DLAST_SGA(x) (x)
45198 +
45199 +/* Bit definitions and macros for TCD14_BITER_ELINK */
45200 +#define MCF_EDMA_TCD14_BITER_ELINK_BITER(x) (((x)&0x01FF))
45201 +#define MCF_EDMA_TCD14_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
45202 +#define MCF_EDMA_TCD14_BITER_ELINK_E_LINK (0x8000)
45203 +
45204 +/* Bit definitions and macros for TCD14_BITER */
45205 +#define MCF_EDMA_TCD14_BITER_BITER(x) (((x)&0x7FFF))
45206 +#define MCF_EDMA_TCD14_BITER_E_LINK (0x8000)
45207 +
45208 +/* Bit definitions and macros for TCD14_CSR */
45209 +#define MCF_EDMA_TCD14_CSR_START (0x0001)
45210 +#define MCF_EDMA_TCD14_CSR_INT_MAJOR (0x0002)
45211 +#define MCF_EDMA_TCD14_CSR_INT_HALF (0x0004)
45212 +#define MCF_EDMA_TCD14_CSR_D_REQ (0x0008)
45213 +#define MCF_EDMA_TCD14_CSR_E_SG (0x0010)
45214 +#define MCF_EDMA_TCD14_CSR_E_LINK (0x0020)
45215 +#define MCF_EDMA_TCD14_CSR_ACTIVE (0x0040)
45216 +#define MCF_EDMA_TCD14_CSR_DONE (0x0080)
45217 +#define MCF_EDMA_TCD14_CSR_LINKCH(x) (((x)&0x003F)<<8)
45218 +#define MCF_EDMA_TCD14_CSR_BWC(x) (((x)&0x0003)<<14)
45219 +
45220 +/* Bit definitions and macros for TCD15_SADDR */
45221 +#define MCF_EDMA_TCD15_SADDR_SADDR(x) (x)
45222 +
45223 +/* Bit definitions and macros for TCD15_ATTR */
45224 +#define MCF_EDMA_TCD15_ATTR_DSIZE(x) (((x)&0x0007))
45225 +#define MCF_EDMA_TCD15_ATTR_DMOD(x) (((x)&0x001F)<<3)
45226 +#define MCF_EDMA_TCD15_ATTR_SSIZE(x) (((x)&0x0007)<<8)
45227 +#define MCF_EDMA_TCD15_ATTR_SMOD(x) (((x)&0x001F)<<11)
45228 +
45229 +/* Bit definitions and macros for TCD15_SOFF */
45230 +#define MCF_EDMA_TCD15_SOFF_SOFF(x) (x)
45231 +
45232 +/* Bit definitions and macros for TCD15_NBYTES */
45233 +#define MCF_EDMA_TCD15_NBYTES_NBYTES(x) (x)
45234 +
45235 +/* Bit definitions and macros for TCD15_SLAST */
45236 +#define MCF_EDMA_TCD15_SLAST_SLAST(x) (x)
45237 +
45238 +/* Bit definitions and macros for TCD15_DADDR */
45239 +#define MCF_EDMA_TCD15_DADDR_DADDR(x) (x)
45240 +
45241 +/* Bit definitions and macros for TCD15_CITER_ELINK */
45242 +#define MCF_EDMA_TCD15_CITER_ELINK_CITER(x) (((x)&0x01FF))
45243 +#define MCF_EDMA_TCD15_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
45244 +#define MCF_EDMA_TCD15_CITER_ELINK_E_LINK (0x8000)
45245 +
45246 +/* Bit definitions and macros for TCD15_CITER */
45247 +#define MCF_EDMA_TCD15_CITER_CITER(x) (((x)&0x7FFF))
45248 +#define MCF_EDMA_TCD15_CITER_E_LINK (0x8000)
45249 +
45250 +/* Bit definitions and macros for TCD15_DOFF */
45251 +#define MCF_EDMA_TCD15_DOFF_DOFF(x) (x)
45252 +
45253 +/* Bit definitions and macros for TCD15_DLAST_SGA */
45254 +#define MCF_EDMA_TCD15_DLAST_SGA_DLAST_SGA(x) (x)
45255 +
45256 +/* Bit definitions and macros for TCD15_BITER */
45257 +#define MCF_EDMA_TCD15_BITER_BITER(x) (((x)&0x7FFF))
45258 +#define MCF_EDMA_TCD15_BITER_E_LINK (0x8000)
45259 +
45260 +/* Bit definitions and macros for TCD15_BITER_ELINK */
45261 +#define MCF_EDMA_TCD15_BITER_ELINK_BITER(x) (((x)&0x01FF))
45262 +#define MCF_EDMA_TCD15_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
45263 +#define MCF_EDMA_TCD15_BITER_ELINK_E_LINK (0x8000)
45264 +
45265 +/* Bit definitions and macros for TCD15_CSR */
45266 +#define MCF_EDMA_TCD15_CSR_START (0x0001)
45267 +#define MCF_EDMA_TCD15_CSR_INT_MAJOR (0x0002)
45268 +#define MCF_EDMA_TCD15_CSR_INT_HALF (0x0004)
45269 +#define MCF_EDMA_TCD15_CSR_D_REQ (0x0008)
45270 +#define MCF_EDMA_TCD15_CSR_E_SG (0x0010)
45271 +#define MCF_EDMA_TCD15_CSR_E_LINK (0x0020)
45272 +#define MCF_EDMA_TCD15_CSR_ACTIVE (0x0040)
45273 +#define MCF_EDMA_TCD15_CSR_DONE (0x0080)
45274 +#define MCF_EDMA_TCD15_CSR_LINKCH(x) (((x)&0x003F)<<8)
45275 +#define MCF_EDMA_TCD15_CSR_BWC(x) (((x)&0x0003)<<14)
45276 +
45277 +#endif /* __MCF5445X_EDMA_H__ */
45278 --- /dev/null
45279 +++ b/include/asm-m68k/mcf5445x_eport.h
45280 @@ -0,0 +1,117 @@
45281 +/*
45282 + * Kurt Mahan kmahan@freescale.com
45283 + *
45284 + * Copyright Freescale Semiconductor, Inc. 2007
45285 + *
45286 + * This program is free software; you can redistribute it and/or modify it
45287 + * under the terms of the GNU General Public License as published by the
45288 + * Free Software Foundation; either version 2 of the License, or (at your
45289 + * option) any later version.
45290 + */
45291 +
45292 +#ifndef __MCF5445X_EPORT_H__
45293 +#define __MCF5445X_EPORT_H__
45294 +
45295 +/*********************************************************************
45296 +*
45297 +* Edge Port Module (EPORT)
45298 +*
45299 +*********************************************************************/
45300 +
45301 +/* Register read/write macros */
45302 +#define MCF_EPORT_EPPAR MCF_REG16(0xFC094000)
45303 +#define MCF_EPORT_EPDDR MCF_REG08(0xFC094002)
45304 +#define MCF_EPORT_EPIER MCF_REG08(0xFC094003)
45305 +#define MCF_EPORT_EPDR MCF_REG08(0xFC094004)
45306 +#define MCF_EPORT_EPPDR MCF_REG08(0xFC094005)
45307 +#define MCF_EPORT_EPFR MCF_REG08(0xFC094006)
45308 +
45309 +/* Bit definitions and macros for EPPAR */
45310 +#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
45311 +#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
45312 +#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
45313 +#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
45314 +#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
45315 +#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
45316 +#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
45317 +#define MCF_EPORT_EPPAR_LEVEL (0)
45318 +#define MCF_EPORT_EPPAR_RISING (1)
45319 +#define MCF_EPORT_EPPAR_FALLING (2)
45320 +#define MCF_EPORT_EPPAR_BOTH (3)
45321 +#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000)
45322 +#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
45323 +#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
45324 +#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
45325 +#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000)
45326 +#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
45327 +#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
45328 +#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
45329 +#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000)
45330 +#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400)
45331 +#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800)
45332 +#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00)
45333 +#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000)
45334 +#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100)
45335 +#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200)
45336 +#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300)
45337 +#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000)
45338 +#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040)
45339 +#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080)
45340 +#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0)
45341 +#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000)
45342 +#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010)
45343 +#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020)
45344 +#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030)
45345 +#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000)
45346 +#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004)
45347 +#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008)
45348 +#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C)
45349 +
45350 +/* Bit definitions and macros for EPDDR */
45351 +#define MCF_EPORT_EPDDR_EPDD1 (0x02)
45352 +#define MCF_EPORT_EPDDR_EPDD2 (0x04)
45353 +#define MCF_EPORT_EPDDR_EPDD3 (0x08)
45354 +#define MCF_EPORT_EPDDR_EPDD4 (0x10)
45355 +#define MCF_EPORT_EPDDR_EPDD5 (0x20)
45356 +#define MCF_EPORT_EPDDR_EPDD6 (0x40)
45357 +#define MCF_EPORT_EPDDR_EPDD7 (0x80)
45358 +
45359 +/* Bit definitions and macros for EPIER */
45360 +#define MCF_EPORT_EPIER_EPIE1 (0x02)
45361 +#define MCF_EPORT_EPIER_EPIE2 (0x04)
45362 +#define MCF_EPORT_EPIER_EPIE3 (0x08)
45363 +#define MCF_EPORT_EPIER_EPIE4 (0x10)
45364 +#define MCF_EPORT_EPIER_EPIE5 (0x20)
45365 +#define MCF_EPORT_EPIER_EPIE6 (0x40)
45366 +#define MCF_EPORT_EPIER_EPIE7 (0x80)
45367 +
45368 +/* Bit definitions and macros for EPDR */
45369 +#define MCF_EPORT_EPDR_EPD1 (0x02)
45370 +#define MCF_EPORT_EPDR_EPD2 (0x04)
45371 +#define MCF_EPORT_EPDR_EPD3 (0x08)
45372 +#define MCF_EPORT_EPDR_EPD4 (0x10)
45373 +#define MCF_EPORT_EPDR_EPD5 (0x20)
45374 +#define MCF_EPORT_EPDR_EPD6 (0x40)
45375 +#define MCF_EPORT_EPDR_EPD7 (0x80)
45376 +
45377 +/* Bit definitions and macros for EPPDR */
45378 +#define MCF_EPORT_EPPDR_EPPD1 (0x02)
45379 +#define MCF_EPORT_EPPDR_EPPD2 (0x04)
45380 +#define MCF_EPORT_EPPDR_EPPD3 (0x08)
45381 +#define MCF_EPORT_EPPDR_EPPD4 (0x10)
45382 +#define MCF_EPORT_EPPDR_EPPD5 (0x20)
45383 +#define MCF_EPORT_EPPDR_EPPD6 (0x40)
45384 +#define MCF_EPORT_EPPDR_EPPD7 (0x80)
45385 +
45386 +/* Bit definitions and macros for EPFR */
45387 +#define MCF_EPORT_EPFR_EPF1 (0x02)
45388 +#define MCF_EPORT_EPFR_EPF2 (0x04)
45389 +#define MCF_EPORT_EPFR_EPF3 (0x08)
45390 +#define MCF_EPORT_EPFR_EPF4 (0x10)
45391 +#define MCF_EPORT_EPFR_EPF5 (0x20)
45392 +#define MCF_EPORT_EPFR_EPF6 (0x40)
45393 +#define MCF_EPORT_EPFR_EPF7 (0x80)
45394 +
45395 +/********************************************************************/
45396 +
45397 +#endif /* __MCF5445X_EPORT_H__ */
45398 --- /dev/null
45399 +++ b/include/asm-m68k/mcf5445x_fbcs.h
45400 @@ -0,0 +1,182 @@
45401 +/*
45402 + * Matt Waddel Matt.Waddel@freescale.com
45403 + *
45404 + * Copyright Freescale Semiconductor, Inc. 2007
45405 + *
45406 + * This program is free software; you can redistribute it and/or modify it
45407 + * under the terms of the GNU General Public License as published by the
45408 + * Free Software Foundation; either version 2 of the License, or (at your
45409 + * option) any later version.
45410 + */
45411 +
45412 +#ifndef __MCF5445X_FBCS_H__
45413 +#define __MCF5445X_FBCS_H__
45414 +
45415 +/*********************************************************************
45416 +*
45417 +* FlexBus Chip Selects (FBCS)
45418 +*
45419 +*********************************************************************/
45420 +
45421 +/* Register read/write macros */
45422 +#define MCF_FBCS_CSAR0 MCF_REG32(0xFC008000) /* Chip-select Addr Register */
45423 +#define MCF_FBCS_CSMR0 MCF_REG32(0xFC008004) /* Chip-select Mask Register */
45424 +#define MCF_FBCS_CSCR0 MCF_REG32(0xFC008008) /* Chip-select Cntl Register */
45425 +#define MCF_FBCS_CSAR1 MCF_REG32(0xFC00800C) /* Chip-select Addr Register */
45426 +#define MCF_FBCS_CSMR1 MCF_REG32(0xFC008010) /* Chip-select Mask Register */
45427 +#define MCF_FBCS_CSCR1 MCF_REG32(0xFC008014) /* Chip-select Cntl Register */
45428 +#define MCF_FBCS_CSAR2 MCF_REG32(0xFC008018) /* Chip-select Addr Register */
45429 +#define MCF_FBCS_CSMR2 MCF_REG32(0xFC00801C) /* Chip-select Mask Register */
45430 +#define MCF_FBCS_CSCR2 MCF_REG32(0xFC008020) /* Chip-select Cntl Register */
45431 +#define MCF_FBCS_CSAR3 MCF_REG32(0xFC008024) /* Chip-select Addr Register */
45432 +#define MCF_FBCS_CSMR3 MCF_REG32(0xFC008028) /* Chip-select Mask Register */
45433 +#define MCF_FBCS_CSCR3 MCF_REG32(0xFC00802C) /* Chip-select Cntl Register */
45434 +
45435 +/* Parameterized register read/write macros for multiple registers */
45436 +#define MCF_FBCS_CSAR(x) MCF_REG32(0xFC008000+((x)*0x00C)) /* Chip-select Addr Register */
45437 +#define MCF_FBCS_CSMR(x) MCF_REG32(0xFC008004+((x)*0x00C)) /* Chip-select Mask Register */
45438 +#define MCF_FBCS_CSCR(x) MCF_REG32(0xFC008008+((x)*0x00C)) /* Chip-select Cntl Register */
45439 +
45440 +/* Bit definitions and macros for CSAR group */
45441 +#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
45442 +
45443 +/* Bit definitions and macros for CSAR0 */
45444 +#define MCF_FBCS_CSAR0_BA(x) ((x)&0xFFFF0000)
45445 +
45446 +/* Bit definitions and macros for CSMR group */
45447 +#define MCF_FBCS_CSMR_V (0x00000001) /* Valid bit */
45448 +#define MCF_FBCS_CSMR_WP (0x00000100) /* Write protect */
45449 +#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) /* Base addr mask */
45450 +#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)
45451 +#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)
45452 +#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)
45453 +#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
45454 +#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)
45455 +#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000)
45456 +#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000)
45457 +#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000)
45458 +#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000)
45459 +#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000)
45460 +#define MCF_FBCS_CSMR_BAM_8M (0x007F0000)
45461 +#define MCF_FBCS_CSMR_BAM_4M (0x003F0000)
45462 +#define MCF_FBCS_CSMR_BAM_2M (0x001F0000)
45463 +#define MCF_FBCS_CSMR_BAM_1M (0x000F0000)
45464 +#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000)
45465 +#define MCF_FBCS_CSMR_BAM_512K (0x00070000)
45466 +#define MCF_FBCS_CSMR_BAM_256K (0x00030000)
45467 +#define MCF_FBCS_CSMR_BAM_128K (0x00010000)
45468 +#define MCF_FBCS_CSMR_BAM_64K (0x00000000)
45469 +
45470 +/* Bit definitions and macros for CSMR0 */
45471 +#define MCF_FBCS_CSMR0_V (0x00000001) /* Valid bit */
45472 +#define MCF_FBCS_CSMR0_WP (0x00000100) /* Write protect */
45473 +#define MCF_FBCS_CSMR0_BAM(x) (((x)&0x0000FFFF)<<16) /* Base addr mask */
45474 +#define MCF_FBCS_CSMR0_BAM_4G (0xFFFF0000)
45475 +#define MCF_FBCS_CSMR0_BAM_2G (0x7FFF0000)
45476 +#define MCF_FBCS_CSMR0_BAM_1G (0x3FFF0000)
45477 +#define MCF_FBCS_CSMR0_BAM_1024M (0x3FFF0000)
45478 +#define MCF_FBCS_CSMR0_BAM_512M (0x1FFF0000)
45479 +#define MCF_FBCS_CSMR0_BAM_256M (0x0FFF0000)
45480 +#define MCF_FBCS_CSMR0_BAM_128M (0x07FF0000)
45481 +#define MCF_FBCS_CSMR0_BAM_64M (0x03FF0000)
45482 +#define MCF_FBCS_CSMR0_BAM_32M (0x01FF0000)
45483 +#define MCF_FBCS_CSMR0_BAM_16M (0x00FF0000)
45484 +#define MCF_FBCS_CSMR0_BAM_8M (0x007F0000)
45485 +#define MCF_FBCS_CSMR0_BAM_4M (0x003F0000)
45486 +#define MCF_FBCS_CSMR0_BAM_2M (0x001F0000)
45487 +#define MCF_FBCS_CSMR0_BAM_1M (0x000F0000)
45488 +#define MCF_FBCS_CSMR0_BAM_1024K (0x000F0000)
45489 +#define MCF_FBCS_CSMR0_BAM_512K (0x00070000)
45490 +#define MCF_FBCS_CSMR0_BAM_256K (0x00030000)
45491 +#define MCF_FBCS_CSMR0_BAM_128K (0x00010000)
45492 +#define MCF_FBCS_CSMR0_BAM_64K (0x00000000)
45493 +
45494 +/* Bit definitions and macros for CSCR group */
45495 +#define MCF_FBCS_CSCR_BSTW (0x00000008) /* Burst-write enable */
45496 +#define MCF_FBCS_CSCR_BSTR (0x00000010) /* Burst-read enable */
45497 +#define MCF_FBCS_CSCR_BEM (0x00000020) /* Byte-enable mode */
45498 +#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) /* Port size */
45499 +#define MCF_FBCS_CSCR_AA (0x00000100) /* Auto-acknowledge */
45500 +#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
45501 +#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */
45502 +#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */
45503 +#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
45504 +#define MCF_FBCS_CSCR_SWSEN (0x00800000) /* Secondary wait state enable */
45505 +#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */
45506 +#define MCF_FBCS_CSCR_PS_8 (0x00000040)
45507 +#define MCF_FBCS_CSCR_PS_16 (0x00000080)
45508 +#define MCF_FBCS_CSCR_PS_32 (0x00000000)
45509 +
45510 +/* Bit definitions and macros for CSCR0 */
45511 +#define MCF_FBCS_CSCR0_BSTW (0x00000008) /* Burst-write enable */
45512 +#define MCF_FBCS_CSCR0_BSTR (0x00000010) /* Burst-read enable */
45513 +#define MCF_FBCS_CSCR0_BEM (0x00000020) /* Byte-enable mode */
45514 +#define MCF_FBCS_CSCR0_PS(x) (((x)&0x00000003)<<6) /* Port size */
45515 +#define MCF_FBCS_CSCR0_AA (0x00000100) /* Auto-acknowledge */
45516 +#define MCF_FBCS_CSCR0_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
45517 +#define MCF_FBCS_CSCR0_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */
45518 +#define MCF_FBCS_CSCR0_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */
45519 +#define MCF_FBCS_CSCR0_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
45520 +#define MCF_FBCS_CSCR0_SWSEN (0x00800000) /* Secondary wait state enable */
45521 +#define MCF_FBCS_CSCR0_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */
45522 +#define MCF_FBCS_CSCR0_PS_8 (0x00000040)
45523 +#define MCF_FBCS_CSCR0_PS_16 (0x00000080)
45524 +#define MCF_FBCS_CSCR0_PS_32 (0x00000000)
45525 +
45526 +/* Bit definitions and macros for CSMR1 */
45527 +#define MCF_FBCS_CSMR1_V (0x00000001) /* Valid bit */
45528 +#define MCF_FBCS_CSMR1_WP (0x00000100) /* Write protect */
45529 +#define MCF_FBCS_CSMR1_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
45530 +
45531 +/* Bit definitions and macros for CSCR1 */
45532 +#define MCF_FBCS_CSCR1_BSTW (0x00000008) /* Burst-write enable */
45533 +#define MCF_FBCS_CSCR1_BSTR (0x00000010) /* Burst-read enable */
45534 +#define MCF_FBCS_CSCR1_BEM (0x00000020) /* Byte-enable mode */
45535 +#define MCF_FBCS_CSCR1_PS(x) (((x)&0x00000003)<<6) /* Port size */
45536 +#define MCF_FBCS_CSCR1_AA (0x00000100) /* Auto-acknowledge */
45537 +#define MCF_FBCS_CSCR1_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
45538 +#define MCF_FBCS_CSCR1_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */
45539 +#define MCF_FBCS_CSCR1_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */
45540 +#define MCF_FBCS_CSCR1_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
45541 +#define MCF_FBCS_CSCR1_SWSEN (0x00800000) /* Secondary wait state enable */
45542 +#define MCF_FBCS_CSCR1_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */
45543 +
45544 +/* Bit definitions and macros for CSMR2 */
45545 +#define MCF_FBCS_CSMR2_V (0x00000001) /* Valid bit */
45546 +#define MCF_FBCS_CSMR2_WP (0x00000100) /* Write protect */
45547 +#define MCF_FBCS_CSMR2_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
45548 +
45549 +/* Bit definitions and macros for CSCR2 */
45550 +#define MCF_FBCS_CSCR2_BSTW (0x00000008) /* Burst-write enable */
45551 +#define MCF_FBCS_CSCR2_BSTR (0x00000010) /* Burst-read enable */
45552 +#define MCF_FBCS_CSCR2_BEM (0x00000020) /* Byte-enable mode */
45553 +#define MCF_FBCS_CSCR2_PS(x) (((x)&0x00000003)<<6) /* Port size */
45554 +#define MCF_FBCS_CSCR2_AA (0x00000100) /* Auto-acknowledge */
45555 +#define MCF_FBCS_CSCR2_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
45556 +#define MCF_FBCS_CSCR2_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */
45557 +#define MCF_FBCS_CSCR2_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */
45558 +#define MCF_FBCS_CSCR2_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
45559 +#define MCF_FBCS_CSCR2_SWSEN (0x00800000) /* Secondary wait state enable */
45560 +#define MCF_FBCS_CSCR2_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */
45561 +
45562 +/* Bit definitions and macros for CSMR3 */
45563 +#define MCF_FBCS_CSMR3_V (0x00000001) /* Valid bit */
45564 +#define MCF_FBCS_CSMR3_WP (0x00000100) /* Write protect */
45565 +#define MCF_FBCS_CSMR3_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
45566 +
45567 +/* Bit definitions and macros for CSCR3 */
45568 +#define MCF_FBCS_CSCR3_BSTW (0x00000008) /* Burst-write enable */
45569 +#define MCF_FBCS_CSCR3_BSTR (0x00000010) /* Burst-read enable */
45570 +#define MCF_FBCS_CSCR3_BEM (0x00000020) /* Byte-enable mode */
45571 +#define MCF_FBCS_CSCR3_PS(x) (((x)&0x00000003)<<6) /* Port size */
45572 +#define MCF_FBCS_CSCR3_AA (0x00000100) /* Auto-acknowledge */
45573 +#define MCF_FBCS_CSCR3_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
45574 +#define MCF_FBCS_CSCR3_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */
45575 +#define MCF_FBCS_CSCR3_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */
45576 +#define MCF_FBCS_CSCR3_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
45577 +#define MCF_FBCS_CSCR3_SWSEN (0x00800000) /* Secondary wait state enable */
45578 +#define MCF_FBCS_CSCR3_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */
45579 +
45580 +/********************************************************************/
45581 +
45582 +#endif /* __MCF5445X_FBCS_H__ */
45583 --- /dev/null
45584 +++ b/include/asm-m68k/mcf5445x_gpio.h
45585 @@ -0,0 +1,1257 @@
45586 +/*
45587 + * Matt Waddel Matt.Waddel@freescale.com
45588 + *
45589 + * Copyright Freescale Semiconductor, Inc. 2007
45590 + *
45591 + * This program is free software; you can redistribute it and/or modify it
45592 + * under the terms of the GNU General Public License as published by the
45593 + * Free Software Foundation; either version 2 of the License, or (at your
45594 + * option) any later version.
45595 + */
45596 +
45597 +#ifndef __MCF5445X_GPIO_H__
45598 +#define __MCF5445X_GPIO_H__
45599 +
45600 +/*********************************************************************
45601 +*
45602 +* General Purpose I/O Module (GPIO)
45603 +*
45604 +*********************************************************************/
45605 +
45606 +/* Register read/write macros */
45607 +#define MCF_GPIO_PODR_FEC0H MCF_REG08(0xFC0A4000) /* FEC0 High Port Output Data Register */
45608 +#define MCF_GPIO_PODR_FEC0L MCF_REG08(0xFC0A4001) /* FEC0 Low Port Output Data Register */
45609 +#define MCF_GPIO_PODR_SSI MCF_REG08(0xFC0A4002) /* SSI Port Output Data Register */
45610 +#define MCF_GPIO_PODR_FBCTL MCF_REG08(0xFC0A4003) /* Flexbus Control Port Output Data Register */
45611 +#define MCF_GPIO_PODR_BE MCF_REG08(0xFC0A4004) /* Flexbus Byte Enable Port Output Data Register */
45612 +#define MCF_GPIO_PODR_CS MCF_REG08(0xFC0A4005) /* Flexbus Chip-Select Port Output Data Register */
45613 +#define MCF_GPIO_PODR_DMA MCF_REG08(0xFC0A4006) /* DMA Port Output Data Register */
45614 +#define MCF_GPIO_PODR_FECI2C MCF_REG08(0xFC0A4007) /* FEC1 / I2C Port Output Data Register */
45615 +#define MCF_GPIO_PODR_UART MCF_REG08(0xFC0A4009) /* UART Port Output Data Register */
45616 +#define MCF_GPIO_PODR_DSPI MCF_REG08(0xFC0A400A) /* DSPI Port Output Data Register */
45617 +#define MCF_GPIO_PODR_TIMER MCF_REG08(0xFC0A400B) /* Timer Port Output Data Register */
45618 +#define MCF_GPIO_PODR_PCI MCF_REG08(0xFC0A400C) /* PCI Port Output Data Register */
45619 +#define MCF_GPIO_PODR_USB MCF_REG08(0xFC0A400D) /* USB Port Output Data Register */
45620 +#define MCF_GPIO_PODR_ATAH MCF_REG08(0xFC0A400E) /* ATA High Port Output Data Register */
45621 +#define MCF_GPIO_PODR_ATAL MCF_REG08(0xFC0A400F) /* ATA Low Port Output Data Register */
45622 +#define MCF_GPIO_PODR_FEC1H MCF_REG08(0xFC0A4010) /* FEC1 High Port Output Data Register */
45623 +#define MCF_GPIO_PODR_FEC1L MCF_REG08(0xFC0A4011) /* FEC1 Low Port Output Data Register */
45624 +#define MCF_GPIO_PODR_FBADH MCF_REG08(0xFC0A4014) /* Flexbus AD High Port Output Data Register */
45625 +#define MCF_GPIO_PODR_FBADMH MCF_REG08(0xFC0A4015) /* Flexbus AD Med-High Port Output Data Register */
45626 +#define MCF_GPIO_PODR_FBADML MCF_REG08(0xFC0A4016) /* Flexbus AD Med-Low Port Output Data Register */
45627 +#define MCF_GPIO_PODR_FBADL MCF_REG08(0xFC0A4017) /* Flexbus AD Low Port Output Data Register */
45628 +#define MCF_GPIO_PDDR_FEC0H MCF_REG08(0xFC0A4018) /* FEC0 High Port Data Direction Register */
45629 +#define MCF_GPIO_PDDR_FEC0L MCF_REG08(0xFC0A4019) /* FEC0 Low Port Data Direction Register */
45630 +#define MCF_GPIO_PDDR_SSI MCF_REG08(0xFC0A401A) /* SSI Port Data Direction Register */
45631 +#define MCF_GPIO_PDDR_FBCTL MCF_REG08(0xFC0A401B) /* Flexbus Control Port Data Direction Register */
45632 +#define MCF_GPIO_PDDR_BE MCF_REG08(0xFC0A401C) /* Flexbus Byte Enable Port Data Direction Register */
45633 +#define MCF_GPIO_PDDR_CS MCF_REG08(0xFC0A401D) /* Flexbus Chip-Select Port Data Direction Register */
45634 +#define MCF_GPIO_PDDR_DMA MCF_REG08(0xFC0A401E) /* DMA Port Data Direction Register */
45635 +#define MCF_GPIO_PDDR_FECI2C MCF_REG08(0xFC0A401F) /* FEC1 / I2C Port Data Direction Register */
45636 +#define MCF_GPIO_PDDR_UART MCF_REG08(0xFC0A4021) /* UART Port Data Direction Register */
45637 +#define MCF_GPIO_PDDR_DSPI MCF_REG08(0xFC0A4022) /* DSPI Port Data Direction Register */
45638 +#define MCF_GPIO_PDDR_TIMER MCF_REG08(0xFC0A4023) /* Timer Port Data Direction Register */
45639 +#define MCF_GPIO_PDDR_PCI MCF_REG08(0xFC0A4024) /* PCI Port Data Direction Register */
45640 +#define MCF_GPIO_PDDR_USB MCF_REG08(0xFC0A4025) /* USB Port Data Direction Register */
45641 +#define MCF_GPIO_PDDR_ATAH MCF_REG08(0xFC0A4026) /* ATA High Port Data Direction Register */
45642 +#define MCF_GPIO_PDDR_ATAL MCF_REG08(0xFC0A4027) /* ATA Low Port Data Direction Register */
45643 +#define MCF_GPIO_PDDR_FEC1H MCF_REG08(0xFC0A4028) /* FEC1 High Port Data Direction Register */
45644 +#define MCF_GPIO_PDDR_FEC1L MCF_REG08(0xFC0A4029) /* FEC1 Low Port Data Direction Register */
45645 +#define MCF_GPIO_PDDR_FBADH MCF_REG08(0xFC0A402C) /* Flexbus AD High Port Data Direction Register */
45646 +#define MCF_GPIO_PDDR_FBADMH MCF_REG08(0xFC0A402D) /* Flexbus AD Med-High Port Data Direction Register */
45647 +#define MCF_GPIO_PDDR_FBADML MCF_REG08(0xFC0A402E) /* Flexbus AD Med-Low Port Data Direction Register */
45648 +#define MCF_GPIO_PDDR_FBADL MCF_REG08(0xFC0A402F) /* Flexbus AD Low Port Data Direction Register */
45649 +#define MCF_GPIO_PPDSDR_FEC0H MCF_REG08(0xFC0A4030) /* FEC0 High Port Pin Data/Set Data Register */
45650 +#define MCF_GPIO_PPDSDR_FEC0L MCF_REG08(0xFC0A4031) /* FEC0 Low Port Clear Output Data Register */
45651 +#define MCF_GPIO_PPDSDR_SSI MCF_REG08(0xFC0A4032) /* SSI Port Pin Data/Set Data Register */
45652 +#define MCF_GPIO_PPDSDR_FBCTL MCF_REG08(0xFC0A4033) /* Flexbus Control Port Pin Data/Set Data Register */
45653 +#define MCF_GPIO_PPDSDR_BE MCF_REG08(0xFC0A4034) /* Flexbus Byte Enable Port Pin Data/Set Data Register */
45654 +#define MCF_GPIO_PPDSDR_CS MCF_REG08(0xFC0A4035) /* Flexbus Chip-Select Port Pin Data/Set Data Register */
45655 +#define MCF_GPIO_PPDSDR_DMA MCF_REG08(0xFC0A4036) /* DMA Port Pin Data/Set Data Register */
45656 +#define MCF_GPIO_PPDSDR_FECI2C MCF_REG08(0xFC0A4037) /* FEC1 / I2C Port Pin Data/Set Data Register */
45657 +#define MCF_GPIO_PPDSDR_UART MCF_REG08(0xFC0A4039) /* UART Port Pin Data/Set Data Register */
45658 +#define MCF_GPIO_PPDSDR_DSPI MCF_REG08(0xFC0A403A) /* DSPI Port Pin Data/Set Data Register */
45659 +#define MCF_GPIO_PPDSDR_TIMER MCF_REG08(0xFC0A403B) /* FTimer Port Pin Data/Set Data Register */
45660 +#define MCF_GPIO_PPDSDR_PCI MCF_REG08(0xFC0A403C) /* PCI Port Pin Data/Set Data Register */
45661 +#define MCF_GPIO_PPDSDR_USB MCF_REG08(0xFC0A403D) /* USB Port Pin Data/Set Data Register */
45662 +#define MCF_GPIO_PPDSDR_ATAH MCF_REG08(0xFC0A403E) /* ATA High Port Pin Data/Set Data Register */
45663 +#define MCF_GPIO_PPDSDR_ATAL MCF_REG08(0xFC0A403F) /* ATA Low Port Pin Data/Set Data Register */
45664 +#define MCF_GPIO_PPDSDR_FEC1H MCF_REG08(0xFC0A4040) /* FEC1 High Port Pin Data/Set Data Register */
45665 +#define MCF_GPIO_PPDSDR_FEC1L MCF_REG08(0xFC0A4041) /* FEC1 Low Port Pin Data/Set Data Register */
45666 +#define MCF_GPIO_PPDSDR_FBADH MCF_REG08(0xFC0A4044) /* Flexbus AD High Port Pin Data/Set Data Register */
45667 +#define MCF_GPIO_PPDSDR_FBADMH MCF_REG08(0xFC0A4045) /* Flexbus AD Med-High Port Pin Data/Set Data Register */
45668 +#define MCF_GPIO_PPDSDR_FBADML MCF_REG08(0xFC0A4046) /* Flexbus AD Med-Low Port Pin Data/Set Data Register */
45669 +#define MCF_GPIO_PPDSDR_FBADL MCF_REG08(0xFC0A4047) /* Flexbus AD Low Port Pin Data/Set Data Register */
45670 +#define MCF_GPIO_PCLRR_FEC0H MCF_REG08(0xFC0A4048) /* FEC0 High Port Clear Output Data Register */
45671 +#define MCF_GPIO_PCLRR_FEC0L MCF_REG08(0xFC0A4049) /* FEC0 Low Port Pin Data/Set Data Register */
45672 +#define MCF_GPIO_PCLRR_SSI MCF_REG08(0xFC0A404A) /* SSI Port Clear Output Data Register */
45673 +#define MCF_GPIO_PCLRR_FBCTL MCF_REG08(0xFC0A404B) /* Flexbus Control Port Clear Output Data Register */
45674 +#define MCF_GPIO_PCLRR_BE MCF_REG08(0xFC0A404C) /* Flexbus Byte Enable Port Clear Output Data Register */
45675 +#define MCF_GPIO_PCLRR_CS MCF_REG08(0xFC0A404D) /* Flexbus Chip-Select Port Clear Output Data Register */
45676 +#define MCF_GPIO_PCLRR_DMA MCF_REG08(0xFC0A404E) /* DMA Port Clear Output Data Register */
45677 +#define MCF_GPIO_PCLRR_FECI2C MCF_REG08(0xFC0A404F) /* FEC1 / I2C Port Clear Output Data Register */
45678 +#define MCF_GPIO_PCLRR_UART MCF_REG08(0xFC0A4051) /* UART Port Clear Output Data Register */
45679 +#define MCF_GPIO_PCLRR_DSPI MCF_REG08(0xFC0A4052) /* DSPI Port Clear Output Data Register */
45680 +#define MCF_GPIO_PCLRR_TIMER MCF_REG08(0xFC0A4053) /* Timer Port Clear Output Data Register */
45681 +#define MCF_GPIO_PCLRR_PCI MCF_REG08(0xFC0A4054) /* PCI Port Clear Output Data Register */
45682 +#define MCF_GPIO_PCLRR_USB MCF_REG08(0xFC0A4055) /* USB Port Clear Output Data Register */
45683 +#define MCF_GPIO_PCLRR_ATAH MCF_REG08(0xFC0A4056) /* ATA High Port Clear Output Data Register */
45684 +#define MCF_GPIO_PCLRR_ATAL MCF_REG08(0xFC0A4057) /* ATA Low Port Clear Output Data Register */
45685 +#define MCF_GPIO_PCLRR_FEC1H MCF_REG08(0xFC0A4058) /* FEC1 High Port Clear Output Data Register */
45686 +#define MCF_GPIO_PCLRR_FEC1L MCF_REG08(0xFC0A4059) /* FEC1 Low Port Clear Output Data Register */
45687 +#define MCF_GPIO_PCLRR_FBADH MCF_REG08(0xFC0A405C) /* Flexbus AD High Port Clear Output Data Register */
45688 +#define MCF_GPIO_PCLRR_FBADMH MCF_REG08(0xFC0A405D) /* Flexbus AD Med-High Port Clear Output Data Register */
45689 +#define MCF_GPIO_PCLRR_FBADML MCF_REG08(0xFC0A405E) /* Flexbus AD Med-Low Port Clear Output Data Register */
45690 +#define MCF_GPIO_PCLRR_FBADL MCF_REG08(0xFC0A405F) /* Flexbus AD Low Port Clear Output Data Register */
45691 +#define MCF_GPIO_PAR_FEC MCF_REG08(0xFC0A4060) /* FEC Pin Assignment Register */
45692 +#define MCF_GPIO_PAR_DMA MCF_REG08(0xFC0A4061) /* DMA Pin Assignment Register */
45693 +#define MCF_GPIO_PAR_FBCTL MCF_REG08(0xFC0A4062) /* Flexbus Control Pin Assignment Register */
45694 +#define MCF_GPIO_PAR_DSPI MCF_REG08(0xFC0A4063) /* DSPI Pin Assignment Register */
45695 +#define MCF_GPIO_PAR_BE MCF_REG08(0xFC0A4064) /* Flexbus Byte-Enable Pin Assignment Register */
45696 +#define MCF_GPIO_PAR_CS MCF_REG08(0xFC0A4065) /* Flexbus Chip-Select Pin Assignment Register */
45697 +#define MCF_GPIO_PAR_TIMER MCF_REG08(0xFC0A4066) /* Time Pin Assignment Register */
45698 +#define MCF_GPIO_PAR_USB MCF_REG08(0xFC0A4067) /* USB Pin Assignment Register */
45699 +#define MCF_GPIO_PAR_UART MCF_REG08(0xFC0A4069) /* UART Pin Assignment Register */
45700 +#define MCF_GPIO_PAR_FECI2C MCF_REG16(0xFC0A406A) /* FEC / I2C Pin Assignment Register */
45701 +#define MCF_GPIO_PAR_SSI MCF_REG16(0xFC0A406C) /* SSI Pin Assignment Register */
45702 +#define MCF_GPIO_PAR_ATA MCF_REG16(0xFC0A406E) /* ATA Pin Assignment Register */
45703 +#define MCF_GPIO_PAR_IRQ MCF_REG08(0xFC0A4070) /* IRQ Pin Assignment Register */
45704 +#define MCF_GPIO_PAR_PCI MCF_REG16(0xFC0A4072) /* PCI Pin Assignment Register */
45705 +#define MCF_GPIO_MSCR_SDRAM MCF_REG08(0xFC0A4074) /* SDRAM Mode Select Control Register */
45706 +#define MCF_GPIO_MSCR_PCI MCF_REG08(0xFC0A4075) /* PCI Mode Select Control Register */
45707 +#define MCF_GPIO_DSCR_I2C MCF_REG08(0xFC0A4078) /* I2C Drive Strength Control Register */
45708 +#define MCF_GPIO_DSCR_FLEXBUS MCF_REG08(0xFC0A4079) /* FLEXBUS Drive Strength Control Register */
45709 +#define MCF_GPIO_DSCR_FEC MCF_REG08(0xFC0A407A) /* FEC Drive Strength Control Register */
45710 +#define MCF_GPIO_DSCR_UART MCF_REG08(0xFC0A407B) /* UART Drive Strength Control Register */
45711 +#define MCF_GPIO_DSCR_DSPI MCF_REG08(0xFC0A407C) /* DSPI Drive Strength Control Register */
45712 +#define MCF_GPIO_DSCR_TIMER MCF_REG08(0xFC0A407D) /* TIMER Drive Strength Control Register */
45713 +#define MCF_GPIO_DSCR_SSI MCF_REG08(0xFC0A407E) /* SSI Drive Strength Control Register */
45714 +#define MCF_GPIO_DSCR_DMA MCF_REG08(0xFC0A407F) /* DMA Drive Strength Control Register */
45715 +#define MCF_GPIO_DSCR_DEBUG MCF_REG08(0xFC0A4080) /* DEBUG Drive Strength Control Register */
45716 +#define MCF_GPIO_DSCR_RESET MCF_REG08(0xFC0A4081) /* RESET Drive Strength Control Register */
45717 +#define MCF_GPIO_DSCR_IRQ MCF_REG08(0xFC0A4082) /* IRQ Drive Strength Control Register */
45718 +#define MCF_GPIO_DSCR_USB MCF_REG08(0xFC0A4083) /* USB Drive Strength Control Register */
45719 +#define MCF_GPIO_DSCR_ATA MCF_REG08(0xFC0A4084) /* ATA Drive Strength Control Register */
45720 +
45721 +/* Bit definitions and macros for PODR_FEC0H */
45722 +#define MCF_GPIO_PODR_FEC0H_PODR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */
45723 +#define MCF_GPIO_PODR_FEC0H_PODR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */
45724 +#define MCF_GPIO_PODR_FEC0H_PODR2 (0x04) /* FEC0_RXDV/FEC0_RMII_CRS_DV */
45725 +#define MCF_GPIO_PODR_FEC0H_PODR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */
45726 +#define MCF_GPIO_PODR_FEC0H_PODR4 (0x10) /* FEC0_COL / ULPI_DATA7 */
45727 +#define MCF_GPIO_PODR_FEC0H_PODR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */
45728 +#define MCF_GPIO_PODR_FEC0H_PODR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */
45729 +#define MCF_GPIO_PODR_FEC0H_PODR7 (0x80) /* FEC0_TXCLK / FEC0_RMII_REF_CLK */
45730 +
45731 +/* Bit definitions and macros for PODR_FEC0L */
45732 +#define MCF_GPIO_PODR_FEC0L_PODR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */
45733 +#define MCF_GPIO_PODR_FEC0L_PODR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */
45734 +#define MCF_GPIO_PODR_FEC0L_PODR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */
45735 +#define MCF_GPIO_PODR_FEC0L_PODR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */
45736 +#define MCF_GPIO_PODR_FEC0L_PODR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */
45737 +#define MCF_GPIO_PODR_FEC0L_PODR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */
45738 +#define MCF_GPIO_PODR_FEC0L_PODR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */
45739 +#define MCF_GPIO_PODR_FEC0L_PODR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */
45740 +
45741 +/* Bit definitions and macros for PODR_SSI */
45742 +#define MCF_GPIO_PODR_SSI_PODR0 (0x01) /* SSI_TXD / U1TXD */
45743 +#define MCF_GPIO_PODR_SSI_PODR1 (0x02) /* SSI_RXD / U1RXD */
45744 +#define MCF_GPIO_PODR_SSI_PODR2 (0x04) /* SSI_FS / U1RTS */
45745 +#define MCF_GPIO_PODR_SSI_PODR3 (0x08) /* SSI_BCLK / U1CTS */
45746 +#define MCF_GPIO_PODR_SSI_PODR4 (0x10) /* SSI_MCLK */
45747 +
45748 +/* Bit definitions and macros for PODR_FBCTL */
45749 +#define MCF_GPIO_PODR_FBCTL_PODR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */
45750 +#define MCF_GPIO_PODR_FBCTL_PODR1 (0x02) /* FB_RW */
45751 +#define MCF_GPIO_PODR_FBCTL_PODR2 (0x04) /* FB_TA */
45752 +#define MCF_GPIO_PODR_FBCTL_PODR3 (0x08) /* FB_OE */
45753 +
45754 +/* Bit definitions and macros for PODR_BE */
45755 +#define MCF_GPIO_PODR_BE_PODR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */
45756 +#define MCF_GPIO_PODR_BE_PODR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */
45757 +#define MCF_GPIO_PODR_BE_PODR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */
45758 +#define MCF_GPIO_PODR_BE_PODR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */
45759 +
45760 +/* Bit definitions and macros for PODR_CS */
45761 +#define MCF_GPIO_PODR_CS_PODR1 (0x02) /* FB_CS1 */
45762 +#define MCF_GPIO_PODR_CS_PODR2 (0x04) /* FB_CS2 */
45763 +#define MCF_GPIO_PODR_CS_PODR3 (0x08) /* FB_CS3 */
45764 +
45765 +/* Bit definitions and macros for PODR_DMA */
45766 +#define MCF_GPIO_PODR_DMA_PODR0 (0x01) /* DREQ0 */
45767 +#define MCF_GPIO_PODR_DMA_PODR1 (0x02) /* DACK0 / DSPI_PCS3 */
45768 +#define MCF_GPIO_PODR_DMA_PODR2 (0x04) /* DREQ1 / USB_CLKIN */
45769 +#define MCF_GPIO_PODR_DMA_PODR3 (0x08) /* DACK1 / ULPI_DIR */
45770 +
45771 +/* Bit definitions and macros for PODR_FECI2C */
45772 +#define MCF_GPIO_PODR_FECI2C_PODR0 (0x01) /* I2C_SDA / U2RXD */
45773 +#define MCF_GPIO_PODR_FECI2C_PODR1 (0x02) /* I2C_SCL / U2TXD */
45774 +#define MCF_GPIO_PODR_FECI2C_PODR2 (0x04) /* FEC0_MDIO */
45775 +#define MCF_GPIO_PODR_FECI2C_PODR3 (0x08) /* FEC0_MDC */
45776 +#define MCF_GPIO_PODR_FECI2C_PODR4 (0x10) /* FEC1_MDIO / ATA_DIOW */
45777 +#define MCF_GPIO_PODR_FECI2C_PODR5 (0x20) /* FEC1_MDC / ATA_DIOR */
45778 +
45779 +/* Bit definitions and macros for PODR_UART */
45780 +#define MCF_GPIO_PODR_UART_PODR0 (0x01) /* U1TXD */
45781 +#define MCF_GPIO_PODR_UART_PODR1 (0x02) /* U1RXD */
45782 +#define MCF_GPIO_PODR_UART_PODR2 (0x04) /* U1RTS */
45783 +#define MCF_GPIO_PODR_UART_PODR3 (0x08) /* U0CTS */
45784 +#define MCF_GPIO_PODR_UART_PODR4 (0x10) /* U1TXD */
45785 +#define MCF_GPIO_PODR_UART_PODR5 (0x20) /* U1RXD */
45786 +#define MCF_GPIO_PODR_UART_PODR6 (0x40) /* U1RTS */
45787 +#define MCF_GPIO_PODR_UART_PODR7 (0x80) /* U1CTS */
45788 +
45789 +/* Bit definitions and macros for PODR_DSPI */
45790 +#define MCF_GPIO_PODR_DSPI_PODR0 (0x01) /* DSPI_SOUT / SBF_DO */
45791 +#define MCF_GPIO_PODR_DSPI_PODR1 (0x02) /* DSPI_SIN / SBF_DI */
45792 +#define MCF_GPIO_PODR_DSPI_PODR2 (0x04) /* DSPI_SCK / SBF_CK */
45793 +#define MCF_GPIO_PODR_DSPI_PODR3 (0x08) /* DSPI_PCS0/SS */
45794 +#define MCF_GPIO_PODR_DSPI_PODR4 (0x10) /* DSPI_PCS1 / SBF_CS */
45795 +#define MCF_GPIO_PODR_DSPI_PODR5 (0x20) /* DSPI_PCS2 */
45796 +#define MCF_GPIO_PODR_DSPI_PODR6 (0x40) /* DSPI_PCS5/SS */
45797 +
45798 +/* Bit definitions and macros for PODR_TIMER */
45799 +#define MCF_GPIO_PODR_TIMER_PODR0 (0x01) /* T0IN / T0OUT / U2RTS */
45800 +#define MCF_GPIO_PODR_TIMER_PODR1 (0x02) /* T1IN / T1OUT / U2CTS */
45801 +#define MCF_GPIO_PODR_TIMER_PODR2 (0x04) /* T2IN / T2OUT / U2TXD */
45802 +#define MCF_GPIO_PODR_TIMER_PODR3 (0x08) /* T3IN / T3OUT / U2RXD */
45803 +
45804 +/* Bit definitions and macros for PODR_PCI */
45805 +#define MCF_GPIO_PODR_PCI_PODR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */
45806 +#define MCF_GPIO_PODR_PCI_PODR1 (0x02) /* PCI_REQ1 */
45807 +#define MCF_GPIO_PODR_PCI_PODR2 (0x04) /* PCI_REQ2 */
45808 +#define MCF_GPIO_PODR_PCI_PODR3 (0x08) /* PCI_REQ3 / ATA_INTR */
45809 +#define MCF_GPIO_PODR_PCI_PODR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */
45810 +#define MCF_GPIO_PODR_PCI_PODR5 (0x20) /* PCI_GNT1 / */
45811 +#define MCF_GPIO_PODR_PCI_PODR6 (0x40) /* PCI_GNT2 / */
45812 +#define MCF_GPIO_PODR_PCI_PODR7 (0x80) /* PCI_GNT3 / ATA_DMACK */
45813 +
45814 +/* Bit definitions and macros for PODR_USB */
45815 +#define MCF_GPIO_PODR_USB_PODR0 (0x01) /* USB_VBUS_OC / ULPI_STP */
45816 +#define MCF_GPIO_PODR_USB_PODR1 (0x02) /* USB_VBUS_EN / USB_PULLUP / ULPI_NXT */
45817 +
45818 +/* Bit definitions and macros for PODR_ATAH */
45819 +#define MCF_GPIO_PODR_ATAH_PODR0 (0x01) /* ATA_DA0 */
45820 +#define MCF_GPIO_PODR_ATAH_PODR1 (0x02) /* ATA_DA1 */
45821 +#define MCF_GPIO_PODR_ATAH_PODR2 (0x04) /* ATA_DA2 */
45822 +#define MCF_GPIO_PODR_ATAH_PODR3 (0x08) /* ATA_CS0 */
45823 +#define MCF_GPIO_PODR_ATAH_PODR4 (0x10) /* ATA_CS1 */
45824 +#define MCF_GPIO_PODR_ATAH_PODR5 (0x20) /* ATA_BUFFER_EN */
45825 +
45826 +/* Bit definitions and macros for PODR_ATAL */
45827 +#define MCF_GPIO_PODR_ATAL_PODR0 (0x01) /* ATA_IORDY */
45828 +#define MCF_GPIO_PODR_ATAL_PODR1 (0x02) /* ATA_DMARQ */
45829 +#define MCF_GPIO_PODR_ATAL_PODR2 (0x04) /* ATA_RESET */
45830 +
45831 +/* Bit definitions and macros for PODR_FEC1H */
45832 +#define MCF_GPIO_PODR_FEC1H_PODR0 (0x01) /* FEC1_CRS / ATA_DATA6 */
45833 +#define MCF_GPIO_PODR_FEC1H_PODR1 (0x02) /* FEC1_RXD0 / FEC1_RMII_RXD0 / ATA_DATA13 */
45834 +#define MCF_GPIO_PODR_FEC1H_PODR2 (0x04) /* FEC1_RXDV / FEC1_RMII_CRS_DV / ATA_DATA15 */
45835 +#define MCF_GPIO_PODR_FEC1H_PODR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */
45836 +#define MCF_GPIO_PODR_FEC1H_PODR4 (0x10) /* FEC1_COL / ATA_DATA7 */
45837 +#define MCF_GPIO_PODR_FEC1H_PODR5 (0x20) /* FEC1_TXD0 / FEC1_RMII_TXD0 / ATA_DATA9 */
45838 +#define MCF_GPIO_PODR_FEC1H_PODR6 (0x40) /* FEC1_TXEN / FEC1_RMII_TXEN / ATA_DATA8 */
45839 +#define MCF_GPIO_PODR_FEC1H_PODR7 (0x80) /* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */
45840 +
45841 +/* Bit definitions and macros for PODR_FEC1L */
45842 +#define MCF_GPIO_PODR_FEC1L_PODR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER / ATA_DATA12 */
45843 +#define MCF_GPIO_PODR_FEC1L_PODR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1 / ATA_DATA14 */
45844 +#define MCF_GPIO_PODR_FEC1L_PODR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */
45845 +#define MCF_GPIO_PODR_FEC1L_PODR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */
45846 +#define MCF_GPIO_PODR_FEC1L_PODR4 (0x10) /* FEC1_TXER / ATA_DATA0 */
45847 +#define MCF_GPIO_PODR_FEC1L_PODR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1 / ATA_DATA10 */
45848 +#define MCF_GPIO_PODR_FEC1L_PODR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */
45849 +#define MCF_GPIO_PODR_FEC1L_PODR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */
45850 +
45851 +/* Bit definitions and macros for PODR_FBADH */
45852 +#define MCF_GPIO_PODR_FBADH_PODR0 (0x01) /* FB_AD24 */
45853 +#define MCF_GPIO_PODR_FBADH_PODR1 (0x02) /* FB_AD25 */
45854 +#define MCF_GPIO_PODR_FBADH_PODR2 (0x04) /* FB_AD26 */
45855 +#define MCF_GPIO_PODR_FBADH_PODR3 (0x08) /* FB_AD27 */
45856 +#define MCF_GPIO_PODR_FBADH_PODR4 (0x10) /* FB_AD28 */
45857 +#define MCF_GPIO_PODR_FBADH_PODR5 (0x20) /* FB_AD29 */
45858 +#define MCF_GPIO_PODR_FBADH_PODR6 (0x40) /* FB_AD30 */
45859 +#define MCF_GPIO_PODR_FBADH_PODR7 (0x80) /* FB_AD31 */
45860 +
45861 +/* Bit definitions and macros for PODR_FBADMH */
45862 +#define MCF_GPIO_PODR_FBADMH_PODR0 (0x01) /* FB_AD16 */
45863 +#define MCF_GPIO_PODR_FBADMH_PODR1 (0x02) /* FB_AD17 */
45864 +#define MCF_GPIO_PODR_FBADMH_PODR2 (0x04) /* FB_AD18 */
45865 +#define MCF_GPIO_PODR_FBADMH_PODR3 (0x08) /* FB_AD19 */
45866 +#define MCF_GPIO_PODR_FBADMH_PODR4 (0x10) /* FB_AD20 */
45867 +#define MCF_GPIO_PODR_FBADMH_PODR5 (0x20) /* FB_AD21 */
45868 +#define MCF_GPIO_PODR_FBADMH_PODR6 (0x40) /* FB_AD22 */
45869 +#define MCF_GPIO_PODR_FBADMH_PODR7 (0x80) /* FB_AD23 */
45870 +
45871 +/* Bit definitions and macros for PODR_FBADML */
45872 +#define MCF_GPIO_PODR_FBADML_PODR0 (0x01) /* FB_AD8 */
45873 +#define MCF_GPIO_PODR_FBADML_PODR1 (0x02) /* FB_AD9 */
45874 +#define MCF_GPIO_PODR_FBADML_PODR2 (0x04) /* FB_AD10 */
45875 +#define MCF_GPIO_PODR_FBADML_PODR3 (0x08) /* FB_AD11 */
45876 +#define MCF_GPIO_PODR_FBADML_PODR4 (0x10) /* FB_AD12 */
45877 +#define MCF_GPIO_PODR_FBADML_PODR5 (0x20) /* FB_AD13 */
45878 +#define MCF_GPIO_PODR_FBADML_PODR6 (0x40) /* FB_AD14 */
45879 +#define MCF_GPIO_PODR_FBADML_PODR7 (0x80) /* FB_AD15 */
45880 +
45881 +/* Bit definitions and macros for PODR_FBADL */
45882 +#define MCF_GPIO_PODR_FBADL_PODR0 (0x01) /* FB_AD0 */
45883 +#define MCF_GPIO_PODR_FBADL_PODR1 (0x02) /* FB_AD1 */
45884 +#define MCF_GPIO_PODR_FBADL_PODR2 (0x04) /* FB_AD2 */
45885 +#define MCF_GPIO_PODR_FBADL_PODR3 (0x08) /* FB_AD3 */
45886 +#define MCF_GPIO_PODR_FBADL_PODR4 (0x10) /* FB_AD4 */
45887 +#define MCF_GPIO_PODR_FBADL_PODR5 (0x20) /* FB_AD5 */
45888 +#define MCF_GPIO_PODR_FBADL_PODR6 (0x40) /* FB_AD6 */
45889 +#define MCF_GPIO_PODR_FBADL_PODR7 (0x80) /* FB_AD7 */
45890 +
45891 +/* Bit definitions and macros for PDDR_FEC0H */
45892 +#define MCF_GPIO_PDDR_FEC0H_PDDR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */
45893 +#define MCF_GPIO_PDDR_FEC0H_PDDR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */
45894 +#define MCF_GPIO_PDDR_FEC0H_PDDR2 (0x04) /* FEC0_RXDV/FEC0_RMII_CRS_DV */
45895 +#define MCF_GPIO_PDDR_FEC0H_PDDR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */
45896 +#define MCF_GPIO_PDDR_FEC0H_PDDR4 (0x10) /* FEC0_COL / ULPI_DATA7 */
45897 +#define MCF_GPIO_PDDR_FEC0H_PDDR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */
45898 +#define MCF_GPIO_PDDR_FEC0H_PDDR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */
45899 +#define MCF_GPIO_PDDR_FEC0H_PDDR7 (0x80) /* FEC0_TXCLK / FEC0_RMII_REF_CLK */
45900 +
45901 +/* Bit definitions and macros for PDDR_FEC0L */
45902 +#define MCF_GPIO_PDDR_FEC0L_PDDR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */
45903 +#define MCF_GPIO_PDDR_FEC0L_PDDR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */
45904 +#define MCF_GPIO_PDDR_FEC0L_PDDR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */
45905 +#define MCF_GPIO_PDDR_FEC0L_PDDR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */
45906 +#define MCF_GPIO_PDDR_FEC0L_PDDR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */
45907 +#define MCF_GPIO_PDDR_FEC0L_PDDR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */
45908 +#define MCF_GPIO_PDDR_FEC0L_PDDR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */
45909 +#define MCF_GPIO_PDDR_FEC0L_PDDR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */
45910 +
45911 +/* Bit definitions and macros for PDDR_SSI */
45912 +#define MCF_GPIO_PDDR_SSI_PDDR0 (0x01) /* SSI_TXD / U1TXD */
45913 +#define MCF_GPIO_PDDR_SSI_PDDR1 (0x02) /* SSI_RXD / U1RXD */
45914 +#define MCF_GPIO_PDDR_SSI_PDDR2 (0x04) /* SSI_FS / U1RTS */
45915 +#define MCF_GPIO_PDDR_SSI_PDDR3 (0x08) /* SSI_BCLK / U1CTS */
45916 +#define MCF_GPIO_PDDR_SSI_PDDR4 (0x10) /* SSI_MCLK */
45917 +
45918 +/* Bit definitions and macros for PDDR_FBCTL */
45919 +#define MCF_GPIO_PDDR_FBCTL_PDDR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */
45920 +#define MCF_GPIO_PDDR_FBCTL_PDDR1 (0x02) /* FB_RW */
45921 +#define MCF_GPIO_PDDR_FBCTL_PDDR2 (0x04) /* FB_TA */
45922 +#define MCF_GPIO_PDDR_FBCTL_PDDR3 (0x08) /* FB_OE */
45923 +
45924 +/* Bit definitions and macros for PDDR_BE */
45925 +#define MCF_GPIO_PDDR_BE_PDDR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */
45926 +#define MCF_GPIO_PDDR_BE_PDDR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */
45927 +#define MCF_GPIO_PDDR_BE_PDDR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */
45928 +#define MCF_GPIO_PDDR_BE_PDDR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */
45929 +
45930 +/* Bit definitions and macros for PDDR_CS */
45931 +#define MCF_GPIO_PDDR_CS_PDDR1 (0x02) /* FB_CS1 */
45932 +#define MCF_GPIO_PDDR_CS_PDDR2 (0x04) /* FB_CS2 */
45933 +#define MCF_GPIO_PDDR_CS_PDDR3 (0x08) /* FB_CS3 */
45934 +
45935 +/* Bit definitions and macros for PDDR_DMA */
45936 +#define MCF_GPIO_PDDR_DMA_PDDR0 (0x01) /* DREQ0 */
45937 +#define MCF_GPIO_PDDR_DMA_PDDR1 (0x02) /* DACK0 / DSPI_PCS3 */
45938 +#define MCF_GPIO_PDDR_DMA_PDDR2 (0x04) /* DREQ1 / USB_CLKIN */
45939 +#define MCF_GPIO_PDDR_DMA_PDDR3 (0x08) /* DACK1 / ULPI_DIR */
45940 +
45941 +/* Bit definitions and macros for PDDR_FECI2C */
45942 +#define MCF_GPIO_PDDR_FECI2C_PDDR0 (0x01) /* I2C_SDA / U2RXD */
45943 +#define MCF_GPIO_PDDR_FECI2C_PDDR1 (0x02) /* I2C_SCL / U2TXD */
45944 +#define MCF_GPIO_PDDR_FECI2C_PDDR2 (0x04) /* FEC0_MDIO */
45945 +#define MCF_GPIO_PDDR_FECI2C_PDDR3 (0x08) /* FEC0_MDC */
45946 +#define MCF_GPIO_PDDR_FECI2C_PDDR4 (0x10) /* FEC1_MDIO / ATA_DIOW */
45947 +#define MCF_GPIO_PDDR_FECI2C_PDDR5 (0x20) /* FEC1_MDC / ATA_DIOR */
45948 +
45949 +/* Bit definitions and macros for PDDR_UART */
45950 +#define MCF_GPIO_PDDR_UART_PDDR0 (0x01) /* U1TXD */
45951 +#define MCF_GPIO_PDDR_UART_PDDR1 (0x02) /* U1RXD */
45952 +#define MCF_GPIO_PDDR_UART_PDDR2 (0x04) /* U1RTS */
45953 +#define MCF_GPIO_PDDR_UART_PDDR3 (0x08) /* U0CTS */
45954 +#define MCF_GPIO_PDDR_UART_PDDR4 (0x10) /* U1TXD */
45955 +#define MCF_GPIO_PDDR_UART_PDDR5 (0x20) /* U1RXD */
45956 +#define MCF_GPIO_PDDR_UART_PDDR6 (0x40) /* U1RTS */
45957 +#define MCF_GPIO_PDDR_UART_PDDR7 (0x80) /* U1CTS */
45958 +
45959 +/* Bit definitions and macros for PDDR_DSPI */
45960 +#define MCF_GPIO_PDDR_DSPI_PDDR0 (0x01) /* DSPI_SOUT / SBF_DO */
45961 +#define MCF_GPIO_PDDR_DSPI_PDDR1 (0x02) /* DSPI_SIN / SBF_DI */
45962 +#define MCF_GPIO_PDDR_DSPI_PDDR2 (0x04) /* DSPI_SCK / SBF_CK */
45963 +#define MCF_GPIO_PDDR_DSPI_PDDR3 (0x08) /* DSPI_PCS0/SS */
45964 +#define MCF_GPIO_PDDR_DSPI_PDDR4 (0x10) /* DSPI_PCS1 / SBF_CS */
45965 +#define MCF_GPIO_PDDR_DSPI_PDDR5 (0x20) /* DSPI_PCS2 */
45966 +#define MCF_GPIO_PDDR_DSPI_PDDR6 (0x40) /* DSPI_PCS5/SS */
45967 +
45968 +/* Bit definitions and macros for PDDR_TIMER */
45969 +#define MCF_GPIO_PDDR_TIMER_PDDR0 (0x01) /* T0IN / T0OUT / U2RTS */
45970 +#define MCF_GPIO_PDDR_TIMER_PDDR1 (0x02) /* T1IN / T1OUT / U2CTS */
45971 +#define MCF_GPIO_PDDR_TIMER_PDDR2 (0x04) /* T2IN / T2OUT / U2TXD */
45972 +#define MCF_GPIO_PDDR_TIMER_PDDR3 (0x08) /* T3IN / T3OUT / U2RXD */
45973 +
45974 +/* Bit definitions and macros for PDDR_PCI */
45975 +#define MCF_GPIO_PDDR_PCI_PDDR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */
45976 +#define MCF_GPIO_PDDR_PCI_PDDR1 (0x02) /* PCI_REQ1 */
45977 +#define MCF_GPIO_PDDR_PCI_PDDR2 (0x04) /* PCI_REQ2 */
45978 +#define MCF_GPIO_PDDR_PCI_PDDR3 (0x08) /* PCI_REQ3 / ATA_INTR */
45979 +#define MCF_GPIO_PDDR_PCI_PDDR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */
45980 +#define MCF_GPIO_PDDR_PCI_PDDR5 (0x20) /* PCI_GNT1 / */
45981 +#define MCF_GPIO_PDDR_PCI_PDDR6 (0x40) /* PCI_GNT2 / */
45982 +#define MCF_GPIO_PDDR_PCI_PDDR7 (0x80) /* PCI_GNT3 / ATA_DMACK */
45983 +
45984 +/* Bit definitions and macros for PDDR_USB */
45985 +#define MCF_GPIO_PDDR_USB_PDDR0 (0x01) /* USB_VBUS_OC / ULPI_STP */
45986 +#define MCF_GPIO_PDDR_USB_PDDR1 (0x02) /* USB_VBUS_EN / USB_PULLUP / ULPI_NXT */
45987 +
45988 +/* Bit definitions and macros for PDDR_ATAH */
45989 +#define MCF_GPIO_PDDR_ATAH_PDDR0 (0x01) /* ATA_DA0 */
45990 +#define MCF_GPIO_PDDR_ATAH_PDDR1 (0x02) /* ATA_DA1 */
45991 +#define MCF_GPIO_PDDR_ATAH_PDDR2 (0x04) /* ATA_DA2 */
45992 +#define MCF_GPIO_PDDR_ATAH_PDDR3 (0x08) /* ATA_CS0 */
45993 +#define MCF_GPIO_PDDR_ATAH_PDDR4 (0x10) /* ATA_CS1 */
45994 +#define MCF_GPIO_PDDR_ATAH_PDDR5 (0x20) /* ATA_BUFFER_EN */
45995 +
45996 +/* Bit definitions and macros for PDDR_ATAL */
45997 +#define MCF_GPIO_PDDR_ATAL_PDDR0 (0x01) /* ATA_IORDY */
45998 +#define MCF_GPIO_PDDR_ATAL_PDDR1 (0x02) /* ATA_DMARQ */
45999 +#define MCF_GPIO_PDDR_ATAL_PDDR2 (0x04) /* ATA_RESET */
46000 +
46001 +/* Bit definitions and macros for PDDR_FEC1H */
46002 +#define MCF_GPIO_PDDR_FEC1H_PDDR0 (0x01) /* FEC1_CRS / ATA_DATA6 */
46003 +#define MCF_GPIO_PDDR_FEC1H_PDDR1 (0x02) /* FEC1_RXD0 / FEC1_RMII_RXD0 / ATA_DATA13 */
46004 +#define MCF_GPIO_PDDR_FEC1H_PDDR2 (0x04) /* FEC1_RXDV / FEC1_RMII_CRS_DV / ATA_DATA15 */
46005 +#define MCF_GPIO_PDDR_FEC1H_PDDR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */
46006 +#define MCF_GPIO_PDDR_FEC1H_PDDR4 (0x10) /* FEC1_COL / ATA_DATA7 */
46007 +#define MCF_GPIO_PDDR_FEC1H_PDDR5 (0x20) /* FEC1_TXD0 / FEC1_RMII_TXD0 / ATA_DATA9 */
46008 +#define MCF_GPIO_PDDR_FEC1H_PDDR6 (0x40) /* FEC1_TXEN / FEC1_RMII_TXEN / ATA_DATA8 */
46009 +#define MCF_GPIO_PDDR_FEC1H_PDDR7 (0x80) /* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */
46010 +
46011 +/* Bit definitions and macros for PDDR_FEC1L */
46012 +#define MCF_GPIO_PDDR_FEC1L_PDDR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER / ATA_DATA12 */
46013 +#define MCF_GPIO_PDDR_FEC1L_PDDR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1 / ATA_DATA14 */
46014 +#define MCF_GPIO_PDDR_FEC1L_PDDR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */
46015 +#define MCF_GPIO_PDDR_FEC1L_PDDR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */
46016 +#define MCF_GPIO_PDDR_FEC1L_PDDR4 (0x10) /* FEC1_TXER / ATA_DATA0 */
46017 +#define MCF_GPIO_PDDR_FEC1L_PDDR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1 / ATA_DATA10 */
46018 +#define MCF_GPIO_PDDR_FEC1L_PDDR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */
46019 +#define MCF_GPIO_PDDR_FEC1L_PDDR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */
46020 +
46021 +/* Bit definitions and macros for PDDR_FBADH */
46022 +#define MCF_GPIO_PDDR_FBADH_PDDR0 (0x01) /* FB_AD24 */
46023 +#define MCF_GPIO_PDDR_FBADH_PDDR1 (0x02) /* FB_AD25 */
46024 +#define MCF_GPIO_PDDR_FBADH_PDDR2 (0x04) /* FB_AD26 */
46025 +#define MCF_GPIO_PDDR_FBADH_PDDR3 (0x08) /* FB_AD27 */
46026 +#define MCF_GPIO_PDDR_FBADH_PDDR4 (0x10) /* FB_AD28 */
46027 +#define MCF_GPIO_PDDR_FBADH_PDDR5 (0x20) /* FB_AD29 */
46028 +#define MCF_GPIO_PDDR_FBADH_PDDR6 (0x40) /* FB_AD30 */
46029 +#define MCF_GPIO_PDDR_FBADH_PDDR7 (0x80) /* FB_AD31 */
46030 +
46031 +/* Bit definitions and macros for PDDR_FBADMH */
46032 +#define MCF_GPIO_PDDR_FBADMH_PDDR0 (0x01) /* FB_AD16 */
46033 +#define MCF_GPIO_PDDR_FBADMH_PDDR1 (0x02) /* FB_AD17 */
46034 +#define MCF_GPIO_PDDR_FBADMH_PDDR2 (0x04) /* FB_AD18 */
46035 +#define MCF_GPIO_PDDR_FBADMH_PDDR3 (0x08) /* FB_AD19 */
46036 +#define MCF_GPIO_PDDR_FBADMH_PDDR4 (0x10) /* FB_AD20 */
46037 +#define MCF_GPIO_PDDR_FBADMH_PDDR5 (0x20) /* FB_AD21 */
46038 +#define MCF_GPIO_PDDR_FBADMH_PDDR6 (0x40) /* FB_AD22 */
46039 +#define MCF_GPIO_PDDR_FBADMH_PDDR7 (0x80) /* FB_AD23 */
46040 +
46041 +/* Bit definitions and macros for PDDR_FBADML */
46042 +#define MCF_GPIO_PDDR_FBADML_PDDR0 (0x01) /* FB_AD8 */
46043 +#define MCF_GPIO_PDDR_FBADML_PDDR1 (0x02) /* FB_AD9 */
46044 +#define MCF_GPIO_PDDR_FBADML_PDDR2 (0x04) /* FB_AD10 */
46045 +#define MCF_GPIO_PDDR_FBADML_PDDR3 (0x08) /* FB_AD11 */
46046 +#define MCF_GPIO_PDDR_FBADML_PDDR4 (0x10) /* FB_AD12 */
46047 +#define MCF_GPIO_PDDR_FBADML_PDDR5 (0x20) /* FB_AD13 */
46048 +#define MCF_GPIO_PDDR_FBADML_PDDR6 (0x40) /* FB_AD14 */
46049 +#define MCF_GPIO_PDDR_FBADML_PDDR7 (0x80) /* FB_AD15 */
46050 +
46051 +/* Bit definitions and macros for PDDR_FBADL */
46052 +#define MCF_GPIO_PDDR_FBADL_PDDR0 (0x01) /* FB_AD0 */
46053 +#define MCF_GPIO_PDDR_FBADL_PDDR1 (0x02) /* FB_AD1 */
46054 +#define MCF_GPIO_PDDR_FBADL_PDDR2 (0x04) /* FB_AD2 */
46055 +#define MCF_GPIO_PDDR_FBADL_PDDR3 (0x08) /* FB_AD3 */
46056 +#define MCF_GPIO_PDDR_FBADL_PDDR4 (0x10) /* FB_AD4 */
46057 +#define MCF_GPIO_PDDR_FBADL_PDDR5 (0x20) /* FB_AD5 */
46058 +#define MCF_GPIO_PDDR_FBADL_PDDR6 (0x40) /* FB_AD6 */
46059 +#define MCF_GPIO_PDDR_FBADL_PDDR7 (0x80) /* FB_AD7 */
46060 +
46061 +/* Bit definitions and macros for PPDSDR_FEC0H */
46062 +#define MCF_GPIO_PPDSDR_FEC0H_PPDR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */
46063 +#define MCF_GPIO_PPDSDR_FEC0H_PPDR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */
46064 +#define MCF_GPIO_PPDSDR_FEC0H_PPDR2 (0x04) /* FEC0_RXDV / FEC0_RMII_CRS_DV */
46065 +#define MCF_GPIO_PPDSDR_FEC0H_PPDR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */
46066 +#define MCF_GPIO_PPDSDR_FEC0H_PPDR4 (0x10) /* FEC0_COL / ULPI_DATA7 */
46067 +#define MCF_GPIO_PPDSDR_FEC0H_PPDR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */
46068 +#define MCF_GPIO_PPDSDR_FEC0H_PPDR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */
46069 +#define MCF_GPIO_PPDSDR_FEC0H_PPDR7 (0x80) /* FEC0_TXCLK / FEC0_RMII_REF_CLK */
46070 +
46071 +/* Bit definitions and macros for PPDSDR_FEC0L */
46072 +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */
46073 +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */
46074 +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */
46075 +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */
46076 +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */
46077 +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */
46078 +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */
46079 +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */
46080 +
46081 +/* Bit definitions and macros for PPDSDR_SSI */
46082 +#define MCF_GPIO_PPDSDR_SSI_PPDR0 (0x01) /* SSI_TXD / U1TXD */
46083 +#define MCF_GPIO_PPDSDR_SSI_PPDR1 (0x02) /* SSI_RXD / U1RXD */
46084 +#define MCF_GPIO_PPDSDR_SSI_PPDR2 (0x04) /* SSI_FS / U1RTS */
46085 +#define MCF_GPIO_PPDSDR_SSI_PPDR3 (0x08) /* SSI_BCLK / U1CTS */
46086 +#define MCF_GPIO_PPDSDR_SSI_PPDR4 (0x10) /* SSI_MCLK */
46087 +
46088 +/* Bit definitions and macros for PPDSDR_FBCTL */
46089 +#define MCF_GPIO_PPDSDR_FBCTL_PPDR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */
46090 +#define MCF_GPIO_PPDSDR_FBCTL_PPDR1 (0x02) /* FB_RW */
46091 +#define MCF_GPIO_PPDSDR_FBCTL_PPDR2 (0x04) /* FB_TA */
46092 +#define MCF_GPIO_PPDSDR_FBCTL_PPDR3 (0x08) /* FB_OE */
46093 +
46094 +/* Bit definitions and macros for PPDSDR_BE */
46095 +#define MCF_GPIO_PPDSDR_BE_PPDR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */
46096 +#define MCF_GPIO_PPDSDR_BE_PPDR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */
46097 +#define MCF_GPIO_PPDSDR_BE_PPDR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */
46098 +#define MCF_GPIO_PPDSDR_BE_PPDR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */
46099 +
46100 +/* Bit definitions and macros for PPDSDR_CS */
46101 +#define MCF_GPIO_PPDSDR_CS_PPDR1 (0x02) /* FB_CS1 */
46102 +#define MCF_GPIO_PPDSDR_CS_PPDR2 (0x04) /* FB_CS2 */
46103 +#define MCF_GPIO_PPDSDR_CS_PPDR3 (0x08) /* FB_CS3 */
46104 +
46105 +/* Bit definitions and macros for PPDSDR_DMA */
46106 +#define MCF_GPIO_PPDSDR_DMA_PPDR0 (0x01) /* DREQ0 */
46107 +#define MCF_GPIO_PPDSDR_DMA_PPDR1 (0x02) /* DACK0 / DSPI_PCS3 */
46108 +#define MCF_GPIO_PPDSDR_DMA_PPDR2 (0x04) /* DREQ1 / USB_CLKIN */
46109 +#define MCF_GPIO_PPDSDR_DMA_PPDR3 (0x08) /* DACK1 / ULPI_DIR */
46110 +
46111 +/* Bit definitions and macros for PPDSDR_FECI2C */
46112 +#define MCF_GPIO_PPDSDR_FECI2C_PPDR0 (0x01) /* I2C_SDA / U2RXD */
46113 +#define MCF_GPIO_PPDSDR_FECI2C_PPDR1 (0x02) /* I2C_SCL / U2TXD */
46114 +#define MCF_GPIO_PPDSDR_FECI2C_PPDR2 (0x04) /* FEC0_MDIO */
46115 +#define MCF_GPIO_PPDSDR_FECI2C_PPDR3 (0x08) /* FEC0_MDC */
46116 +#define MCF_GPIO_PPDSDR_FECI2C_PPDR4 (0x10) /* FEC1_MDIO / ATA_DIOW */
46117 +#define MCF_GPIO_PPDSDR_FECI2C_PPDR5 (0x20) /* FEC1_MDC / ATA_DIOR */
46118 +
46119 +/* Bit definitions and macros for PPDSDR_UART */
46120 +#define MCF_GPIO_PPDSDR_UART_PPDR0 (0x01) /* U1TXD */
46121 +#define MCF_GPIO_PPDSDR_UART_PPDR1 (0x02) /* U1RXD */
46122 +#define MCF_GPIO_PPDSDR_UART_PPDR2 (0x04) /* U1RTS */
46123 +#define MCF_GPIO_PPDSDR_UART_PPDR3 (0x08) /* U0CTS */
46124 +#define MCF_GPIO_PPDSDR_UART_PPDR4 (0x10) /* U1TXD */
46125 +#define MCF_GPIO_PPDSDR_UART_PPDR5 (0x20) /* U1RXD */
46126 +#define MCF_GPIO_PPDSDR_UART_PPDR6 (0x40) /* U1RTS */
46127 +#define MCF_GPIO_PPDSDR_UART_PPDR7 (0x80) /* U1CTS */
46128 +
46129 +/* Bit definitions and macros for PPDSDR_DSPI */
46130 +#define MCF_GPIO_PPDSDR_DSPI_PPDR0 (0x01) /* DSPI_SOUT / SBF_DO */
46131 +#define MCF_GPIO_PPDSDR_DSPI_PPDR1 (0x02) /* DSPI_SIN / SBF_DI */
46132 +#define MCF_GPIO_PPDSDR_DSPI_PPDR2 (0x04) /* DSPI_SCK / SBF_CK */
46133 +#define MCF_GPIO_PPDSDR_DSPI_PPDR3 (0x08) /* DSPI_PCS0/SS */
46134 +#define MCF_GPIO_PPDSDR_DSPI_PPDR4 (0x10) /* DSPI_PCS1 / SBF_CS */
46135 +#define MCF_GPIO_PPDSDR_DSPI_PPDR5 (0x20) /* DSPI_PCS2 */
46136 +#define MCF_GPIO_PPDSDR_DSPI_PPDR6 (0x40) /* DSPI_PCS5/SS */
46137 +
46138 +/* Bit definitions and macros for PPDSDR_TIMER */
46139 +#define MCF_GPIO_PPDSDR_TIMER_PPDR0 (0x01) /* T0IN / T0OUT / U2RTS */
46140 +#define MCF_GPIO_PPDSDR_TIMER_PPDR1 (0x02) /* T1IN / T1OUT / U2CTS */
46141 +#define MCF_GPIO_PPDSDR_TIMER_PPDR2 (0x04) /* T2IN / T2OUT / U2TXD */
46142 +#define MCF_GPIO_PPDSDR_TIMER_PPDR3 (0x08) /* T3IN / T3OUT / U2RXD */
46143 +
46144 +/* Bit definitions and macros for PPDSDR_PCI */
46145 +#define MCF_GPIO_PPDSDR_PCI_PPDR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */
46146 +#define MCF_GPIO_PPDSDR_PCI_PPDR1 (0x02) /* PCI_REQ1 */
46147 +#define MCF_GPIO_PPDSDR_PCI_PPDR2 (0x04) /* PCI_REQ2 */
46148 +#define MCF_GPIO_PPDSDR_PCI_PPDR3 (0x08) /* PCI_REQ3 / ATA_INTR */
46149 +#define MCF_GPIO_PPDSDR_PCI_PPDR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */
46150 +#define MCF_GPIO_PPDSDR_PCI_PPDR5 (0x20) /* PCI_GNT1 / */
46151 +#define MCF_GPIO_PPDSDR_PCI_PPDR6 (0x40) /* PCI_GNT2 / */
46152 +#define MCF_GPIO_PPDSDR_PCI_PPDR7 (0x80) /* PCI_GNT3 / ATA_DMACK */
46153 +
46154 +/* Bit definitions and macros for PPDSDR_USB */
46155 +#define MCF_GPIO_PPDSDR_USB_PPDR0 (0x01) /* USB_VBUS_OC / ULPI_STP */
46156 +#define MCF_GPIO_PPDSDR_USB_PPDR1 (0x02) /* USB_VBUS_EN / USB_PULLUP / ULPI_NXT */
46157 +
46158 +/* Bit definitions and macros for PPDSDR_ATAH */
46159 +#define MCF_GPIO_PPDSDR_ATAH_PPDR0 (0x01) /* ATA_DA0 */
46160 +#define MCF_GPIO_PPDSDR_ATAH_PPDR1 (0x02) /* ATA_DA1 */
46161 +#define MCF_GPIO_PPDSDR_ATAH_PPDR2 (0x04) /* ATA_DA2 */
46162 +#define MCF_GPIO_PPDSDR_ATAH_PPDR3 (0x08) /* ATA_CS0 */
46163 +#define MCF_GPIO_PPDSDR_ATAH_PPDR4 (0x10) /* ATA_CS1 */
46164 +#define MCF_GPIO_PPDSDR_ATAH_PPDR5 (0x20) /* ATA_BUFFER_EN */
46165 +
46166 +/* Bit definitions and macros for PPDSDR_ATAL */
46167 +#define MCF_GPIO_PPDSDR_ATAL_PPDR0 (0x01) /* ATA_IORDY */
46168 +#define MCF_GPIO_PPDSDR_ATAL_PPDR1 (0x02) /* ATA_DMARQ */
46169 +#define MCF_GPIO_PPDSDR_ATAL_PPDR2 (0x04) /* ATA_RESET */
46170 +
46171 +/* Bit definitions and macros for PPDSDR_FEC1H */
46172 +#define MCF_GPIO_PPDSDR_FEC1H_PPDR0 (0x01) /* FEC1_CRS / ATA_DATA6 */
46173 +#define MCF_GPIO_PPDSDR_FEC1H_PPDR1 (0x02) /* FEC1_RXD0 / FEC1_RMII_RXD0 / ATA_DATA13 */
46174 +#define MCF_GPIO_PPDSDR_FEC1H_PPDR2 (0x04) /* FEC1_RXDV / FEC1_RMII_CRS_DV / ATA_DATA15 */
46175 +#define MCF_GPIO_PPDSDR_FEC1H_PPDR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */
46176 +#define MCF_GPIO_PPDSDR_FEC1H_PPDR4 (0x10) /* FEC1_COL / ATA_DATA7 */
46177 +#define MCF_GPIO_PPDSDR_FEC1H_PPDR5 (0x20) /* FEC1_TXD0 / FEC1_RMII_TXD0 / ATA_DATA9 */
46178 +#define MCF_GPIO_PPDSDR_FEC1H_PPDR6 (0x40) /* FEC1_TXEN / FEC1_RMII_TXEN / ATA_DATA8 */
46179 +#define MCF_GPIO_PPDSDR_FEC1H_PPDR7 (0x80) /* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */
46180 +
46181 +/* Bit definitions and macros for PPDSDR_FEC1L */
46182 +#define MCF_GPIO_PPDSDR_FEC1L_PPDR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER / ATA_DATA12 */
46183 +#define MCF_GPIO_PPDSDR_FEC1L_PPDR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1 / ATA_DATA14 */
46184 +#define MCF_GPIO_PPDSDR_FEC1L_PPDR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */
46185 +#define MCF_GPIO_PPDSDR_FEC1L_PPDR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */
46186 +#define MCF_GPIO_PPDSDR_FEC1L_PPDR4 (0x10) /* FEC1_TXER / ATA_DATA0 */
46187 +#define MCF_GPIO_PPDSDR_FEC1L_PPDR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1 / ATA_DATA10 */
46188 +#define MCF_GPIO_PPDSDR_FEC1L_PPDR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */
46189 +#define MCF_GPIO_PPDSDR_FEC1L_PPDR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */
46190 +
46191 +/* Bit definitions and macros for PPDSDR_FBADH */
46192 +#define MCF_GPIO_PPDSDR_FBADH_PPDR0 (0x01) /* FB_AD24 */
46193 +#define MCF_GPIO_PPDSDR_FBADH_PPDR1 (0x02) /* FB_AD25 */
46194 +#define MCF_GPIO_PPDSDR_FBADH_PPDR2 (0x04) /* FB_AD26 */
46195 +#define MCF_GPIO_PPDSDR_FBADH_PPDR3 (0x08) /* FB_AD27 */
46196 +#define MCF_GPIO_PPDSDR_FBADH_PPDR4 (0x10) /* FB_AD28 */
46197 +#define MCF_GPIO_PPDSDR_FBADH_PPDR5 (0x20) /* FB_AD29 */
46198 +#define MCF_GPIO_PPDSDR_FBADH_PPDR6 (0x40) /* FB_AD30 */
46199 +#define MCF_GPIO_PPDSDR_FBADH_PPDR7 (0x80) /* FB_AD31 */
46200 +
46201 +/* Bit definitions and macros for PPDSDR_FBADMH */
46202 +#define MCF_GPIO_PPDSDR_FBADMH_PPDR0 (0x01) /* FB_AD16 */
46203 +#define MCF_GPIO_PPDSDR_FBADMH_PPDR1 (0x02) /* FB_AD17 */
46204 +#define MCF_GPIO_PPDSDR_FBADMH_PPDR2 (0x04) /* FB_AD18 */
46205 +#define MCF_GPIO_PPDSDR_FBADMH_PPDR3 (0x08) /* FB_AD19 */
46206 +#define MCF_GPIO_PPDSDR_FBADMH_PPDR4 (0x10) /* FB_AD20 */
46207 +#define MCF_GPIO_PPDSDR_FBADMH_PPDR5 (0x20) /* FB_AD21 */
46208 +#define MCF_GPIO_PPDSDR_FBADMH_PPDR6 (0x40) /* FB_AD22 */
46209 +#define MCF_GPIO_PPDSDR_FBADMH_PPDR7 (0x80) /* FB_AD23 */
46210 +
46211 +/* Bit definitions and macros for PPDSDR_FBADML */
46212 +#define MCF_GPIO_PPDSDR_FBADML_PPDR0 (0x01) /* FB_AD8 */
46213 +#define MCF_GPIO_PPDSDR_FBADML_PPDR1 (0x02) /* FB_AD9 */
46214 +#define MCF_GPIO_PPDSDR_FBADML_PPDR2 (0x04) /* FB_AD10 */
46215 +#define MCF_GPIO_PPDSDR_FBADML_PPDR3 (0x08) /* FB_AD11 */
46216 +#define MCF_GPIO_PPDSDR_FBADML_PPDR4 (0x10) /* FB_AD12 */
46217 +#define MCF_GPIO_PPDSDR_FBADML_PPDR5 (0x20) /* FB_AD13 */
46218 +#define MCF_GPIO_PPDSDR_FBADML_PPDR6 (0x40) /* FB_AD14 */
46219 +#define MCF_GPIO_PPDSDR_FBADML_PPDR7 (0x80) /* FB_AD15 */
46220 +
46221 +/* Bit definitions and macros for PPDSDR_FBADL */
46222 +#define MCF_GPIO_PPDSDR_FBADL_PPDR0 (0x01) /* FB_AD0 */
46223 +#define MCF_GPIO_PPDSDR_FBADL_PPDR1 (0x02) /* FB_AD1 */
46224 +#define MCF_GPIO_PPDSDR_FBADL_PPDR2 (0x04) /* FB_AD2 */
46225 +#define MCF_GPIO_PPDSDR_FBADL_PPDR3 (0x08) /* FB_AD3 */
46226 +#define MCF_GPIO_PPDSDR_FBADL_PPDR4 (0x10) /* FB_AD4 */
46227 +#define MCF_GPIO_PPDSDR_FBADL_PPDR5 (0x20) /* FB_AD5 */
46228 +#define MCF_GPIO_PPDSDR_FBADL_PPDR6 (0x40) /* FB_AD6 */
46229 +#define MCF_GPIO_PPDSDR_FBADL_PPDR7 (0x80) /* FB_AD7 */
46230 +
46231 +/* Bit definitions and macros for PCLRR_FEC0H */
46232 +#define MCF_GPIO_PCLRR_FEC0H_PCLRR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */
46233 +#define MCF_GPIO_PCLRR_FEC0H_PCLRR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */
46234 +#define MCF_GPIO_PCLRR_FEC0H_PCLRR2 (0x04) /* FEC0_RXDV/FEC0_RMII_CRS_DV */
46235 +#define MCF_GPIO_PCLRR_FEC0H_PCLRR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */
46236 +#define MCF_GPIO_PCLRR_FEC0H_PCLRR4 (0x10) /* FEC0_COL / ULPI_DATA7 */
46237 +#define MCF_GPIO_PCLRR_FEC0H_PCLRR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */
46238 +#define MCF_GPIO_PCLRR_FEC0H_PCLRR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */
46239 +#define MCF_GPIO_PCLRR_FEC0H_PCLRR7 (0x80) /* FEC0_TXCLK / FEC0_RMII_REF_CLK */
46240 +
46241 +/* Bit definitions and macros for PCLRR_FEC0L */
46242 +#define MCF_GPIO_PCLRR_FEC0L_PPDR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */
46243 +#define MCF_GPIO_PCLRR_FEC0L_PPDR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */
46244 +#define MCF_GPIO_PCLRR_FEC0L_PPDR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */
46245 +#define MCF_GPIO_PCLRR_FEC0L_PPDR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */
46246 +#define MCF_GPIO_PCLRR_FEC0L_PPDR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */
46247 +#define MCF_GPIO_PCLRR_FEC0L_PPDR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */
46248 +#define MCF_GPIO_PCLRR_FEC0L_PPDR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */
46249 +#define MCF_GPIO_PCLRR_FEC0L_PPDR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */
46250 +
46251 +/* Bit definitions and macros for PCLRR_SSI */
46252 +#define MCF_GPIO_PCLRR_SSI_PCLRR0 (0x01) /* SSI_TXD / U1TXD */
46253 +#define MCF_GPIO_PCLRR_SSI_PCLRR1 (0x02) /* SSI_RXD / U1RXD */
46254 +#define MCF_GPIO_PCLRR_SSI_PCLRR2 (0x04) /* SSI_FS / U1RTS */
46255 +#define MCF_GPIO_PCLRR_SSI_PCLRR3 (0x08) /* SSI_BCLK / U1CTS */
46256 +#define MCF_GPIO_PCLRR_SSI_PCLRR4 (0x10) /* SSI_MCLK */
46257 +
46258 +/* Bit definitions and macros for PCLRR_FBCTL */
46259 +#define MCF_GPIO_PCLRR_FBCTL_PCLRR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */
46260 +#define MCF_GPIO_PCLRR_FBCTL_PCLRR1 (0x02) /* FB_RW */
46261 +#define MCF_GPIO_PCLRR_FBCTL_PCLRR2 (0x04) /* FB_TA */
46262 +#define MCF_GPIO_PCLRR_FBCTL_PCLRR3 (0x08) /* FB_OE */
46263 +
46264 +/* Bit definitions and macros for PCLRR_BE */
46265 +#define MCF_GPIO_PCLRR_BE_PCLRR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */
46266 +#define MCF_GPIO_PCLRR_BE_PCLRR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */
46267 +#define MCF_GPIO_PCLRR_BE_PCLRR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */
46268 +#define MCF_GPIO_PCLRR_BE_PCLRR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */
46269 +
46270 +/* Bit definitions and macros for PCLRR_CS */
46271 +#define MCF_GPIO_PCLRR_CS_PCLRR1 (0x02) /* FB_CS1 */
46272 +#define MCF_GPIO_PCLRR_CS_PCLRR2 (0x04) /* FB_CS2 */
46273 +#define MCF_GPIO_PCLRR_CS_PCLRR3 (0x08) /* FB_CS3 */
46274 +
46275 +/* Bit definitions and macros for PCLRR_DMA */
46276 +#define MCF_GPIO_PCLRR_DMA_PCLRR0 (0x01) /* DREQ0 */
46277 +#define MCF_GPIO_PCLRR_DMA_PCLRR1 (0x02) /* DACK0 / DSPI_PCS3 */
46278 +#define MCF_GPIO_PCLRR_DMA_PCLRR2 (0x04) /* DREQ1 / USB_CLKIN */
46279 +#define MCF_GPIO_PCLRR_DMA_PCLRR3 (0x08) /* DACK1 / ULPI_DIR */
46280 +
46281 +/* Bit definitions and macros for PCLRR_FECI2C */
46282 +#define MCF_GPIO_PCLRR_FECI2C_PCLRR0 (0x01) /* I2C_SDA / U2RXD */
46283 +#define MCF_GPIO_PCLRR_FECI2C_PCLRR1 (0x02) /* I2C_SCL / U2TXD */
46284 +#define MCF_GPIO_PCLRR_FECI2C_PCLRR2 (0x04) /* FEC0_MDIO */
46285 +#define MCF_GPIO_PCLRR_FECI2C_PCLRR3 (0x08) /* FEC0_MDC */
46286 +#define MCF_GPIO_PCLRR_FECI2C_PCLRR4 (0x10) /* FEC1_MDIO / ATA_DIOW */
46287 +#define MCF_GPIO_PCLRR_FECI2C_PCLRR5 (0x20) /* FEC1_MDC / ATA_DIOR */
46288 +
46289 +/* Bit definitions and macros for PCLRR_UART */
46290 +#define MCF_GPIO_PCLRR_UART_PCLRR0 (0x01) /* U1TXD */
46291 +#define MCF_GPIO_PCLRR_UART_PCLRR1 (0x02) /* U1RXD */
46292 +#define MCF_GPIO_PCLRR_UART_PCLRR2 (0x04) /* U1RTS */
46293 +#define MCF_GPIO_PCLRR_UART_PCLRR3 (0x08) /* U0CTS */
46294 +#define MCF_GPIO_PCLRR_UART_PCLRR4 (0x10) /* U1TXD */
46295 +#define MCF_GPIO_PCLRR_UART_PCLRR5 (0x20) /* U1RXD */
46296 +#define MCF_GPIO_PCLRR_UART_PCLRR6 (0x40) /* U1RTS */
46297 +#define MCF_GPIO_PCLRR_UART_PCLRR7 (0x80) /* U1CTS */
46298 +
46299 +/* Bit definitions and macros for PCLRR_DSPI */
46300 +#define MCF_GPIO_PCLRR_DSPI_PCLRR0 (0x01) /* DSPI_SOUT / SBF_DO */
46301 +#define MCF_GPIO_PCLRR_DSPI_PCLRR1 (0x02) /* DSPI_SIN / SBF_DI */
46302 +#define MCF_GPIO_PCLRR_DSPI_PCLRR2 (0x04) /* DSPI_SCK / SBF_CK */
46303 +#define MCF_GPIO_PCLRR_DSPI_PCLRR3 (0x08) /* DSPI_PCS0/SS */
46304 +#define MCF_GPIO_PCLRR_DSPI_PCLRR4 (0x10) /* DSPI_PCS1 / SBF_CS */
46305 +#define MCF_GPIO_PCLRR_DSPI_PCLRR5 (0x20) /* DSPI_PCS2 */
46306 +#define MCF_GPIO_PCLRR_DSPI_PCLRR6 (0x40) /* DSPI_PCS5/SS */
46307 +
46308 +/* Bit definitions and macros for PCLRR_TIMER */
46309 +#define MCF_GPIO_PCLRR_TIMER_PCLRR0 (0x01) /* T0IN / T0OUT / U2RTS */
46310 +#define MCF_GPIO_PCLRR_TIMER_PCLRR1 (0x02) /* T1IN / T1OUT / U2CTS */
46311 +#define MCF_GPIO_PCLRR_TIMER_PCLRR2 (0x04) /* T2IN / T2OUT / U2TXD */
46312 +#define MCF_GPIO_PCLRR_TIMER_PCLRR3 (0x08) /* T3IN / T3OUT / U2RXD */
46313 +
46314 +/* Bit definitions and macros for PCLRR_PCI */
46315 +#define MCF_GPIO_PCLRR_PCI_PCLRR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */
46316 +#define MCF_GPIO_PCLRR_PCI_PCLRR1 (0x02) /* PCI_REQ1 */
46317 +#define MCF_GPIO_PCLRR_PCI_PCLRR2 (0x04) /* PCI_REQ2 */
46318 +#define MCF_GPIO_PCLRR_PCI_PCLRR3 (0x08) /* PCI_REQ3 / ATA_INTR */
46319 +#define MCF_GPIO_PCLRR_PCI_PCLRR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */
46320 +#define MCF_GPIO_PCLRR_PCI_PCLRR5 (0x20) /* PCI_GNT1 / */
46321 +#define MCF_GPIO_PCLRR_PCI_PCLRR6 (0x40) /* PCI_GNT2 / */
46322 +#define MCF_GPIO_PCLRR_PCI_PCLRR7 (0x80) /* PCI_GNT3 / ATA_DMACK */
46323 +
46324 +/* Bit definitions and macros for PCLRR_USB */
46325 +#define MCF_GPIO_PCLRR_USB_PCLRR0 (0x01) /* USB_VBUS_OC / ULPI_STP */
46326 +#define MCF_GPIO_PCLRR_USB_PCLRR1 (0x02) /* USB_VBUS_EN / USB_PULLUP / ULPI_NXT */
46327 +
46328 +/* Bit definitions and macros for PCLRR_ATAH */
46329 +#define MCF_GPIO_PCLRR_ATAH_PCLRR0 (0x01) /* ATA_DA0 */
46330 +#define MCF_GPIO_PCLRR_ATAH_PCLRR1 (0x02) /* ATA_DA1 */
46331 +#define MCF_GPIO_PCLRR_ATAH_PCLRR2 (0x04) /* ATA_DA2 */
46332 +#define MCF_GPIO_PCLRR_ATAH_PCLRR3 (0x08) /* ATA_CS0 */
46333 +#define MCF_GPIO_PCLRR_ATAH_PCLRR4 (0x10) /* ATA_CS1 */
46334 +#define MCF_GPIO_PCLRR_ATAH_PCLRR5 (0x20) /* ATA_BUFFER_EN */
46335 +
46336 +/* Bit definitions and macros for PCLRR_ATAL */
46337 +#define MCF_GPIO_PCLRR_ATAL_PCLRR0 (0x01) /* ATA_IORDY */
46338 +#define MCF_GPIO_PCLRR_ATAL_PCLRR1 (0x02) /* ATA_DMARQ */
46339 +#define MCF_GPIO_PCLRR_ATAL_PCLRR2 (0x04) /* ATA_RESET */
46340 +
46341 +/* Bit definitions and macros for PCLRR_FEC1H */
46342 +#define MCF_GPIO_PCLRR_FEC1H_PCLRR0 (0x01) /* FEC1_CRS / ATA_DATA6 */
46343 +#define MCF_GPIO_PCLRR_FEC1H_PCLRR1 (0x02) /* FEC1_RXD0 / FEC1_RMII_RXD0 / ATA_DATA13 */
46344 +#define MCF_GPIO_PCLRR_FEC1H_PCLRR2 (0x04) /* FEC1_RXDV / FEC1_RMII_CRS_DV / ATA_DATA15 */
46345 +#define MCF_GPIO_PCLRR_FEC1H_PCLRR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */
46346 +#define MCF_GPIO_PCLRR_FEC1H_PCLRR4 (0x10) /* FEC1_COL / ATA_DATA7 */
46347 +#define MCF_GPIO_PCLRR_FEC1H_PCLRR5 (0x20) /* FEC1_TXD0 / FEC1_RMII_TXD0 / ATA_DATA9 */
46348 +#define MCF_GPIO_PCLRR_FEC1H_PCLRR6 (0x40) /* FEC1_TXEN / FEC1_RMII_TXEN / ATA_DATA8 */
46349 +#define MCF_GPIO_PCLRR_FEC1H_PCLRR7 (0x80) /* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */
46350 +
46351 +/* Bit definitions and macros for PCLRR_FEC1L */
46352 +#define MCF_GPIO_PCLRR_FEC1L_PCLRR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER / ATA_DATA12 */
46353 +#define MCF_GPIO_PCLRR_FEC1L_PCLRR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1 / ATA_DATA14 */
46354 +#define MCF_GPIO_PCLRR_FEC1L_PCLRR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */
46355 +#define MCF_GPIO_PCLRR_FEC1L_PCLRR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */
46356 +#define MCF_GPIO_PCLRR_FEC1L_PCLRR4 (0x10) /* FEC1_TXER / ATA_DATA0 */
46357 +#define MCF_GPIO_PCLRR_FEC1L_PCLRR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1 / ATA_DATA10 */
46358 +#define MCF_GPIO_PCLRR_FEC1L_PCLRR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */
46359 +#define MCF_GPIO_PCLRR_FEC1L_PCLRR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */
46360 +
46361 +/* Bit definitions and macros for PCLRR_FBADH */
46362 +#define MCF_GPIO_PCLRR_FBADH_PCLRR0 (0x01) /* FB_AD24 */
46363 +#define MCF_GPIO_PCLRR_FBADH_PCLRR1 (0x02) /* FB_AD25 */
46364 +#define MCF_GPIO_PCLRR_FBADH_PCLRR2 (0x04) /* FB_AD26 */
46365 +#define MCF_GPIO_PCLRR_FBADH_PCLRR3 (0x08) /* FB_AD27 */
46366 +#define MCF_GPIO_PCLRR_FBADH_PCLRR4 (0x10) /* FB_AD28 */
46367 +#define MCF_GPIO_PCLRR_FBADH_PCLRR5 (0x20) /* FB_AD29 */
46368 +#define MCF_GPIO_PCLRR_FBADH_PCLRR6 (0x40) /* FB_AD30 */
46369 +#define MCF_GPIO_PCLRR_FBADH_PCLRR7 (0x80) /* FB_AD31 */
46370 +
46371 +/* Bit definitions and macros for PCLRR_FBADMH */
46372 +#define MCF_GPIO_PCLRR_FBADMH_PCLRR0 (0x01) /* FB_AD16 */
46373 +#define MCF_GPIO_PCLRR_FBADMH_PCLRR1 (0x02) /* FB_AD17 */
46374 +#define MCF_GPIO_PCLRR_FBADMH_PCLRR2 (0x04) /* FB_AD18 */
46375 +#define MCF_GPIO_PCLRR_FBADMH_PCLRR3 (0x08) /* FB_AD19 */
46376 +#define MCF_GPIO_PCLRR_FBADMH_PCLRR4 (0x10) /* FB_AD20 */
46377 +#define MCF_GPIO_PCLRR_FBADMH_PCLRR5 (0x20) /* FB_AD21 */
46378 +#define MCF_GPIO_PCLRR_FBADMH_PCLRR6 (0x40) /* FB_AD22 */
46379 +#define MCF_GPIO_PCLRR_FBADMH_PCLRR7 (0x80) /* FB_AD23 */
46380 +
46381 +/* Bit definitions and macros for PCLRR_FBADML */
46382 +#define MCF_GPIO_PCLRR_FBADML_PCLRR0 (0x01) /* FB_AD8 */
46383 +#define MCF_GPIO_PCLRR_FBADML_PCLRR1 (0x02) /* FB_AD9 */
46384 +#define MCF_GPIO_PCLRR_FBADML_PCLRR2 (0x04) /* FB_AD10 */
46385 +#define MCF_GPIO_PCLRR_FBADML_PCLRR3 (0x08) /* FB_AD11 */
46386 +#define MCF_GPIO_PCLRR_FBADML_PCLRR4 (0x10) /* FB_AD12 */
46387 +#define MCF_GPIO_PCLRR_FBADML_PCLRR5 (0x20) /* FB_AD13 */
46388 +#define MCF_GPIO_PCLRR_FBADML_PCLRR6 (0x40) /* FB_AD14 */
46389 +#define MCF_GPIO_PCLRR_FBADML_PCLRR7 (0x80) /* FB_AD15 */
46390 +
46391 +/* Bit definitions and macros for PCLRR_FBADL */
46392 +#define MCF_GPIO_PCLRR_FBADL_PCLRR0 (0x01) /* FB_AD0 */
46393 +#define MCF_GPIO_PCLRR_FBADL_PCLRR1 (0x02) /* FB_AD1 */
46394 +#define MCF_GPIO_PCLRR_FBADL_PCLRR2 (0x04) /* FB_AD2 */
46395 +#define MCF_GPIO_PCLRR_FBADL_PCLRR3 (0x08) /* FB_AD3 */
46396 +#define MCF_GPIO_PCLRR_FBADL_PCLRR4 (0x10) /* FB_AD4 */
46397 +#define MCF_GPIO_PCLRR_FBADL_PCLRR5 (0x20) /* FB_AD5 */
46398 +#define MCF_GPIO_PCLRR_FBADL_PCLRR6 (0x40) /* FB_AD6 */
46399 +#define MCF_GPIO_PCLRR_FBADL_PCLRR7 (0x80) /* FB_AD7 */
46400 +
46401 +/* Bit definitions and macros for PAR_FEC */
46402 +#define MCF_GPIO_PAR_FEC_FEC0(x) (((x)&0x07))
46403 +#define MCF_GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4)
46404 +#define MCF_GPIO_PAR_FEC_FEC1_MASK (0x8F)
46405 +#define MCF_GPIO_PAR_FEC_FEC1_MII (0x70)
46406 +#define MCF_GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30)
46407 +#define MCF_GPIO_PAR_FEC_FEC1_RMII_ATA (0x20)
46408 +#define MCF_GPIO_PAR_FEC_FEC1_ATA (0x10)
46409 +#define MCF_GPIO_PAR_FEC_FEC1_GPIO (0x00)
46410 +#define MCF_GPIO_PAR_FEC_FEC0_MASK (0xF8)
46411 +#define MCF_GPIO_PAR_FEC_FEC0_MII (0x07)
46412 +#define MCF_GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03)
46413 +#define MCF_GPIO_PAR_FEC_FEC0_RMII_ULPI (0x02)
46414 +#define MCF_GPIO_PAR_FEC_FEC0_ULPI (0x01)
46415 +#define MCF_GPIO_PAR_FEC_FEC0_GPIO (0x00)
46416 +
46417 +/* Bit definitions and macros for PAR_DMA */
46418 +#define MCF_GPIO_PAR_DMA_DREQ0 (0x01)
46419 +#define MCF_GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2)
46420 +#define MCF_GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4)
46421 +#define MCF_GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6)
46422 +#define MCF_GPIO_PAR_DMA_DACK1_MASK (0x3F)
46423 +#define MCF_GPIO_PAR_DMA_DACK1_DACK1 (0xC0)
46424 +#define MCF_GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40)
46425 +#define MCF_GPIO_PAR_DMA_DACK1_GPIO (0x00)
46426 +#define MCF_GPIO_PAR_DMA_DREQ1_MASK (0xCF)
46427 +#define MCF_GPIO_PAR_DMA_DREQ1_DREQ1 (0x30)
46428 +#define MCF_GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10)
46429 +#define MCF_GPIO_PAR_DMA_DREQ1_GPIO (0x00)
46430 +#define MCF_GPIO_PAR_DMA_DACK0_MASK (0xF3)
46431 +#define MCF_GPIO_PAR_DMA_DACK0_DACK1 (0x0C)
46432 +#define MCF_GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04)
46433 +#define MCF_GPIO_PAR_DMA_DACK0_GPIO (0x00)
46434 +#define MCF_GPIO_PAR_DMA_DREQ0_DREQ0 (0x01)
46435 +#define MCF_GPIO_PAR_DMA_DREQ0_GPIO (0x00)
46436 +
46437 +/* Bit definitions and macros for PAR_FBCTL */
46438 +#define MCF_GPIO_PAR_FBCTL_TS(x) (((x)&0x03)<<3)
46439 +#define MCF_GPIO_PAR_FBCTL_RW (0x20)
46440 +#define MCF_GPIO_PAR_FBCTL_TA (0x40)
46441 +#define MCF_GPIO_PAR_FBCTL_OE (0x80)
46442 +#define MCF_GPIO_PAR_FBCTL_OE_OE (0x80)
46443 +#define MCF_GPIO_PAR_FBCTL_OE_GPIO (0x00)
46444 +#define MCF_GPIO_PAR_FBCTL_TA_TA (0x40)
46445 +#define MCF_GPIO_PAR_FBCTL_TA_GPIO (0x00)
46446 +#define MCF_GPIO_PAR_FBCTL_RW_RW (0x20)
46447 +#define MCF_GPIO_PAR_FBCTL_RW_GPIO (0x00)
46448 +#define MCF_GPIO_PAR_FBCTL_TS_MASK (0xE7)
46449 +#define MCF_GPIO_PAR_FBCTL_TS_TS (0x18)
46450 +#define MCF_GPIO_PAR_FBCTL_TS_ALE (0x10)
46451 +#define MCF_GPIO_PAR_FBCTL_TS_TBST (0x08)
46452 +#define MCF_GPIO_PAR_FBCTL_TS_GPIO (0x80)
46453 +
46454 +/* Bit definitions and macros for PAR_DSPI */
46455 +#define MCF_GPIO_PAR_DSPI_SCK (0x01)
46456 +#define MCF_GPIO_PAR_DSPI_SOUT (0x02)
46457 +#define MCF_GPIO_PAR_DSPI_SIN (0x04)
46458 +#define MCF_GPIO_PAR_DSPI_PCS0 (0x08)
46459 +#define MCF_GPIO_PAR_DSPI_PCS1 (0x10)
46460 +#define MCF_GPIO_PAR_DSPI_PCS2 (0x20)
46461 +#define MCF_GPIO_PAR_DSPI_PCS5 (0x40)
46462 +#define MCF_GPIO_PAR_DSPI_PCS5_PCS5 (0x40)
46463 +#define MCF_GPIO_PAR_DSPI_PCS5_GPIO (0x00)
46464 +#define MCF_GPIO_PAR_DSPI_PCS2_PCS2 (0x20)
46465 +#define MCF_GPIO_PAR_DSPI_PCS2_GPIO (0x00)
46466 +#define MCF_GPIO_PAR_DSPI_PCS1_PCS1 (0x10)
46467 +#define MCF_GPIO_PAR_DSPI_PCS1_GPIO (0x00)
46468 +#define MCF_GPIO_PAR_DSPI_PCS0_PCS0 (0x08)
46469 +#define MCF_GPIO_PAR_DSPI_PCS0_GPIO (0x00)
46470 +#define MCF_GPIO_PAR_DSPI_SIN_SIN (0x04)
46471 +#define MCF_GPIO_PAR_DSPI_SIN_GPIO (0x00)
46472 +#define MCF_GPIO_PAR_DSPI_SOUT_SOUT (0x02)
46473 +#define MCF_GPIO_PAR_DSPI_SOUT_GPIO (0x00)
46474 +#define MCF_GPIO_PAR_DSPI_SCK_SCK (0x01)
46475 +#define MCF_GPIO_PAR_DSPI_SCK_GPIO (0x00)
46476 +
46477 +/* Bit definitions and macros for PAR_BE */
46478 +#define MCF_GPIO_PAR_BE_BE0 (0x01)
46479 +#define MCF_GPIO_PAR_BE_BE1 (0x04)
46480 +#define MCF_GPIO_PAR_BE_BE2(x) (((x)&0x03)<<4)
46481 +#define MCF_GPIO_PAR_BE_BE3(x) (((x)&0x03)<<6)
46482 +#define MCF_GPIO_PAR_BE_BE3_MASK (0x3F)
46483 +#define MCF_GPIO_PAR_BE_BE3_BE3 (0xC0)
46484 +#define MCF_GPIO_PAR_BE_BE3_TSIZ1 (0x80)
46485 +#define MCF_GPIO_PAR_BE_BE3_GPIO (0x00)
46486 +#define MCF_GPIO_PAR_BE_BE2_MASK (0xCF)
46487 +#define MCF_GPIO_PAR_BE_BE2_BE2 (0x30)
46488 +#define MCF_GPIO_PAR_BE_BE2_TSIZ0 (0x20)
46489 +#define MCF_GPIO_PAR_BE_BE2_GPIO (0x00)
46490 +#define MCF_GPIO_PAR_BE_BE1_BE1 (0x04)
46491 +#define MCF_GPIO_PAR_BE_BE1_GPIO (0x00)
46492 +#define MCF_GPIO_PAR_BE_BE0_BE0 (0x01)
46493 +#define MCF_GPIO_PAR_BE_BE0_GPIO (0x00)
46494 +
46495 +/* Bit definitions and macros for PAR_CS */
46496 +#define MCF_GPIO_PAR_CS_CS1 (0x02)
46497 +#define MCF_GPIO_PAR_CS_CS2 (0x04)
46498 +#define MCF_GPIO_PAR_CS_CS3 (0x08)
46499 +#define MCF_GPIO_PAR_CS_CS3_CS3 (0x08)
46500 +#define MCF_GPIO_PAR_CS_CS3_GPIO (0x00)
46501 +#define MCF_GPIO_PAR_CS_CS2_CS2 (0x04)
46502 +#define MCF_GPIO_PAR_CS_CS2_GPIO (0x00)
46503 +#define MCF_GPIO_PAR_CS_CS1_CS1 (0x02)
46504 +#define MCF_GPIO_PAR_CS_CS1_GPIO (0x00)
46505 +
46506 +/* Bit definitions and macros for PAR_TIMER */
46507 +#define MCF_GPIO_PAR_TIMER_T0IN(x) (((x)&0x03))
46508 +#define MCF_GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2)
46509 +#define MCF_GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4)
46510 +#define MCF_GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6)
46511 +#define MCF_GPIO_PAR_TIMER_T3IN_MASK (0x3F)
46512 +#define MCF_GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
46513 +#define MCF_GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
46514 +#define MCF_GPIO_PAR_TIMER_T3IN_U2RXD (0x40)
46515 +#define MCF_GPIO_PAR_TIMER_T3IN_GPIO (0x00)
46516 +#define MCF_GPIO_PAR_TIMER_T2IN_MASK (0xCF)
46517 +#define MCF_GPIO_PAR_TIMER_T2IN_T2IN (0x30)
46518 +#define MCF_GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
46519 +#define MCF_GPIO_PAR_TIMER_T2IN_U2TXD (0x10)
46520 +#define MCF_GPIO_PAR_TIMER_T2IN_GPIO (0x00)
46521 +#define MCF_GPIO_PAR_TIMER_T1IN_MASK (0xF3)
46522 +#define MCF_GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
46523 +#define MCF_GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
46524 +#define MCF_GPIO_PAR_TIMER_T1IN_U2CTS (0x04)
46525 +#define MCF_GPIO_PAR_TIMER_T1IN_GPIO (0x00)
46526 +#define MCF_GPIO_PAR_TIMER_T0IN_MASK (0xFC)
46527 +#define MCF_GPIO_PAR_TIMER_T0IN_T0IN (0x03)
46528 +#define MCF_GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
46529 +#define MCF_GPIO_PAR_TIMER_T0IN_U2RTS (0x01)
46530 +#define MCF_GPIO_PAR_TIMER_T0IN_GPIO (0x00)
46531 +
46532 +/* Bit definitions and macros for PAR_USB */
46533 +#define MCF_GPIO_PAR_USB_VBUSOC(x) (((x)&0x03))
46534 +#define MCF_GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2)
46535 +#define MCF_GPIO_PAR_USB_VBUSEN_MASK (0xF3)
46536 +#define MCF_GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C)
46537 +#define MCF_GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08)
46538 +#define MCF_GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04)
46539 +#define MCF_GPIO_PAR_USB_VBUSEN_GPIO (0x00)
46540 +#define MCF_GPIO_PAR_USB_VBUSOC_MASK (0xFC)
46541 +#define MCF_GPIO_PAR_USB_VBUSOC_VBUSOC (0x03)
46542 +#define MCF_GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01)
46543 +#define MCF_GPIO_PAR_USB_VBUSOC_GPIO (0x00)
46544 +
46545 +/* Bit definitions and macros for PAR_UART */
46546 +#define MCF_GPIO_PAR_UART_U0TXD (0x01)
46547 +#define MCF_GPIO_PAR_UART_U0RXD (0x02)
46548 +#define MCF_GPIO_PAR_UART_U0RTS (0x04)
46549 +#define MCF_GPIO_PAR_UART_U0CTS (0x08)
46550 +#define MCF_GPIO_PAR_UART_U1TXD (0x10)
46551 +#define MCF_GPIO_PAR_UART_U1RXD (0x20)
46552 +#define MCF_GPIO_PAR_UART_U1RTS (0x40)
46553 +#define MCF_GPIO_PAR_UART_U1CTS (0x80)
46554 +#define MCF_GPIO_PAR_UART_U1CTS_U1CTS (0x80)
46555 +#define MCF_GPIO_PAR_UART_U1CTS_GPIO (0x00)
46556 +#define MCF_GPIO_PAR_UART_U1RTS_U1RTS (0x40)
46557 +#define MCF_GPIO_PAR_UART_U1RTS_GPIO (0x00)
46558 +#define MCF_GPIO_PAR_UART_U1RXD_U1RXD (0x20)
46559 +#define MCF_GPIO_PAR_UART_U1RXD_GPIO (0x00)
46560 +#define MCF_GPIO_PAR_UART_U1TXD_U1TXD (0x10)
46561 +#define MCF_GPIO_PAR_UART_U1TXD_GPIO (0x00)
46562 +#define MCF_GPIO_PAR_UART_U0CTS_U0CTS (0x08)
46563 +#define MCF_GPIO_PAR_UART_U0CTS_GPIO (0x00)
46564 +#define MCF_GPIO_PAR_UART_U0RTS_U0RTS (0x04)
46565 +#define MCF_GPIO_PAR_UART_U0RTS_GPIO (0x00)
46566 +#define MCF_GPIO_PAR_UART_U0RXD_U0RXD (0x02)
46567 +#define MCF_GPIO_PAR_UART_U0RXD_GPIO (0x00)
46568 +#define MCF_GPIO_PAR_UART_U0TXD_U0TXD (0x01)
46569 +#define MCF_GPIO_PAR_UART_U0TXD_GPIO (0x00)
46570 +
46571 +/* Bit definitions and macros for PAR_FECI2C */
46572 +#define MCF_GPIO_PAR_FECI2C_SDA(x) (((x)&0x0003))
46573 +#define MCF_GPIO_PAR_FECI2C_SCL(x) (((x)&0x0003)<<2)
46574 +#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x0003))
46575 +#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x0003)<<2)
46576 +#define MCF_GPIO_PAR_FECI2C_MDIO0 (0x0010)
46577 +#define MCF_GPIO_PAR_FECI2C_MDC0 (0x0040)
46578 +#define MCF_GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8)
46579 +#define MCF_GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10)
46580 +#define MCF_GPIO_PAR_FECI2C_MDC1_MASK (0xF3FF)
46581 +#define MCF_GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00)
46582 +#define MCF_GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800)
46583 +#define MCF_GPIO_PAR_FECI2C_MDC1_GPIO (0x0000)
46584 +#define MCF_GPIO_PAR_FECI2C_MDIO1_MASK (0xFCFF)
46585 +#define MCF_GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300)
46586 +#define MCF_GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200)
46587 +#define MCF_GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000)
46588 +#define MCF_GPIO_PAR_FECI2C_MDC0_MDC0 (0x0040)
46589 +#define MCF_GPIO_PAR_FECI2C_MDC0_GPIO (0x0000)
46590 +#define MCF_GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010)
46591 +#define MCF_GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000)
46592 +#define MCF_GPIO_PAR_FECI2C_SCL_MASK (0xFFF3)
46593 +#define MCF_GPIO_PAR_FECI2C_SCL_SCL (0x000C)
46594 +#define MCF_GPIO_PAR_FECI2C_SCL_U2TXD (0x0004)
46595 +#define MCF_GPIO_PAR_FECI2C_SCL_GPIO (0x0000)
46596 +#define MCF_GPIO_PAR_FECI2C_SDA_MASK (0xFFFC)
46597 +#define MCF_GPIO_PAR_FECI2C_SDA_SDA (0x0003)
46598 +#define MCF_GPIO_PAR_FECI2C_SDA_U2RXD (0x0001)
46599 +#define MCF_GPIO_PAR_FECI2C_SDA_GPIO (0x0000)
46600 +
46601 +/* Bit definitions and macros for PAR_SSI */
46602 +#define MCF_GPIO_PAR_SSI_MCLK (0x0001)
46603 +#define MCF_GPIO_PAR_SSI_STXD(x) (((x)&0x0003)<<2)
46604 +#define MCF_GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4)
46605 +#define MCF_GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6)
46606 +#define MCF_GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8)
46607 +#define MCF_GPIO_PAR_SSI_BCLK_MASK (0xFCFF)
46608 +#define MCF_GPIO_PAR_SSI_BCLK_BCLK (0x0300)
46609 +#define MCF_GPIO_PAR_SSI_BCLK_U1CTS (0x0200)
46610 +#define MCF_GPIO_PAR_SSI_BCLK_GPIO (0x0000)
46611 +#define MCF_GPIO_PAR_SSI_FS_MASK (0xFF3F)
46612 +#define MCF_GPIO_PAR_SSI_FS_FS (0x00C0)
46613 +#define MCF_GPIO_PAR_SSI_FS_U1RTS (0x0080)
46614 +#define MCF_GPIO_PAR_SSI_FS_GPIO (0x0000)
46615 +#define MCF_GPIO_PAR_SSI_SRXD_MASK (0xFFCF)
46616 +#define MCF_GPIO_PAR_SSI_SRXD_SRXD (0x0030)
46617 +#define MCF_GPIO_PAR_SSI_SRXD_U1RXD (0x0020)
46618 +#define MCF_GPIO_PAR_SSI_SRXD_GPIO (0x0000)
46619 +#define MCF_GPIO_PAR_SSI_STXD_MASK (0xFFF3)
46620 +#define MCF_GPIO_PAR_SSI_STXD_STXD (0x000C)
46621 +#define MCF_GPIO_PAR_SSI_STXD_U1TXD (0x0008)
46622 +#define MCF_GPIO_PAR_SSI_STXD_GPIO (0x0000)
46623 +#define MCF_GPIO_PAR_SSI_MCLK_MCLK (0x0001)
46624 +#define MCF_GPIO_PAR_SSI_MCLK_GPIO (0x0000)
46625 +
46626 +/* Bit definitions and macros for PAR_ATA */
46627 +#define MCF_GPIO_PAR_ATA_IORDY (0x0001)
46628 +#define MCF_GPIO_PAR_ATA_DMARQ (0x0002)
46629 +#define MCF_GPIO_PAR_ATA_RESET (0x0004)
46630 +#define MCF_GPIO_PAR_ATA_DA0 (0x0020)
46631 +#define MCF_GPIO_PAR_ATA_DA1 (0x0040)
46632 +#define MCF_GPIO_PAR_ATA_DA2 (0x0080)
46633 +#define MCF_GPIO_PAR_ATA_CS0 (0x0100)
46634 +#define MCF_GPIO_PAR_ATA_CS1 (0x0200)
46635 +#define MCF_GPIO_PAR_ATA_BUFEN (0x0400)
46636 +#define MCF_GPIO_PAR_ATA_BUFEN_BUFEN (0x0400)
46637 +#define MCF_GPIO_PAR_ATA_BUFEN_GPIO (0x0000)
46638 +#define MCF_GPIO_PAR_ATA_CS1_CS1 (0x0200)
46639 +#define MCF_GPIO_PAR_ATA_CS1_GPIO (0x0000)
46640 +#define MCF_GPIO_PAR_ATA_CS0_CS0 (0x0100)
46641 +#define MCF_GPIO_PAR_ATA_CS0_GPIO (0x0000)
46642 +#define MCF_GPIO_PAR_ATA_DA2_DA2 (0x0080)
46643 +#define MCF_GPIO_PAR_ATA_DA2_GPIO (0x0000)
46644 +#define MCF_GPIO_PAR_ATA_DA1_DA1 (0x0040)
46645 +#define MCF_GPIO_PAR_ATA_DA1_GPIO (0x0000)
46646 +#define MCF_GPIO_PAR_ATA_DA0_DA0 (0x0020)
46647 +#define MCF_GPIO_PAR_ATA_DA0_GPIO (0x0000)
46648 +#define MCF_GPIO_PAR_ATA_RESET_RESET (0x0004)
46649 +#define MCF_GPIO_PAR_ATA_RESET_GPIO (0x0000)
46650 +#define MCF_GPIO_PAR_ATA_DMARQ_DMARQ (0x0002)
46651 +#define MCF_GPIO_PAR_ATA_DMARQ_GPIO (0x0000)
46652 +#define MCF_GPIO_PAR_ATA_IORDY_IORDY (0x0001)
46653 +#define MCF_GPIO_PAR_ATA_IORDY_GPIO (0x0000)
46654 +
46655 +/* Bit definitions and macros for PAR_IRQ */
46656 +#define MCF_GPIO_PAR_IRQ_IRQ1 (0x02)
46657 +#define MCF_GPIO_PAR_IRQ_IRQ4 (0x10)
46658 +#define MCF_GPIO_PAR_IRQ_IRQ4_IRQ4 (0x10)
46659 +#define MCF_GPIO_PAR_IRQ_IRQ4_GPIO (0x00)
46660 +#define MCF_GPIO_PAR_IRQ_IRQ1_IRQ1 (0x02)
46661 +#define MCF_GPIO_PAR_IRQ_IRQ1_GPIO (0x00)
46662 +
46663 +/* Bit definitions and macros for PAR_PCI */
46664 +#define MCF_GPIO_PAR_PCI_REQ0 (0x0001)
46665 +#define MCF_GPIO_PAR_PCI_REQ1 (0x0004)
46666 +#define MCF_GPIO_PAR_PCI_REQ2 (0x0010)
46667 +#define MCF_GPIO_PAR_PCI_REQ3(x) (((x)&0x0003)<<6)
46668 +#define MCF_GPIO_PAR_PCI_GNT0 (0x0100)
46669 +#define MCF_GPIO_PAR_PCI_GNT1 (0x0400)
46670 +#define MCF_GPIO_PAR_PCI_GNT2 (0x1000)
46671 +#define MCF_GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14)
46672 +#define MCF_GPIO_PAR_PCI_GNT3_MASK (0x3FFF)
46673 +#define MCF_GPIO_PAR_PCI_GNT3_GNT3 (0xC000)
46674 +#define MCF_GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000)
46675 +#define MCF_GPIO_PAR_PCI_GNT3_GPIO (0x0000)
46676 +#define MCF_GPIO_PAR_PCI_GNT2_GNT2 (0x1000)
46677 +#define MCF_GPIO_PAR_PCI_GNT2_GPIO (0x0000)
46678 +#define MCF_GPIO_PAR_PCI_GNT1_GNT1 (0x0400)
46679 +#define MCF_GPIO_PAR_PCI_GNT1_GPIO (0x0000)
46680 +#define MCF_GPIO_PAR_PCI_GNT0_GNT0 (0x0100)
46681 +#define MCF_GPIO_PAR_PCI_GNT0_GPIO (0x0000)
46682 +#define MCF_GPIO_PAR_PCI_REQ3_MASK (0xFF3F)
46683 +#define MCF_GPIO_PAR_PCI_REQ3_REQ3 (0x00C0)
46684 +#define MCF_GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080)
46685 +#define MCF_GPIO_PAR_PCI_REQ3_GPIO (0x0000)
46686 +#define MCF_GPIO_PAR_PCI_REQ2_REQ2 (0x0010)
46687 +#define MCF_GPIO_PAR_PCI_REQ2_GPIO (0x0000)
46688 +#define MCF_GPIO_PAR_PCI_REQ1_REQ1 (0x0040)
46689 +#define MCF_GPIO_PAR_PCI_REQ1_GPIO (0x0000)
46690 +#define MCF_GPIO_PAR_PCI_REQ0_REQ0 (0x0001)
46691 +#define MCF_GPIO_PAR_PCI_REQ0_GPIO (0x0000)
46692 +
46693 +/* Bit definitions and macros for MSCR_SDRAM */
46694 +#define MCF_GPIO_MSCR_SDRAM_SDCTL(x) (((x)&0x03))
46695 +#define MCF_GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2)
46696 +#define MCF_GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4)
46697 +#define MCF_GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6)
46698 +#define MCF_GPIO_MSCR_SDRAM_SDDATA_MASK (0x3F)
46699 +#define MCF_GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0)
46700 +#define MCF_GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80)
46701 +#define MCF_GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40)
46702 +#define MCF_GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00)
46703 +#define MCF_GPIO_MSCR_SDRAM_SDDQS_MASK (0xCF)
46704 +#define MCF_GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30)
46705 +#define MCF_GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20)
46706 +#define MCF_GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10)
46707 +#define MCF_GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00)
46708 +#define MCF_GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3)
46709 +#define MCF_GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C)
46710 +#define MCF_GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08)
46711 +#define MCF_GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04)
46712 +#define MCF_GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00)
46713 +#define MCF_GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC)
46714 +#define MCF_GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03)
46715 +#define MCF_GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02)
46716 +#define MCF_GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01)
46717 +#define MCF_GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR (0x00)
46718 +
46719 +/* Bit definitions and macros for MSCR_PCI */
46720 +#define MCF_GPIO_MSCR_PCI_PCI (0x01)
46721 +#define MCF_GPIO_MSCR_PCI_PCI_HI_66MHZ (0x01)
46722 +#define MCF_GPIO_MSCR_PCI_PCI_LO_33MHZ (0x00)
46723 +
46724 +/* Bit definitions and macros for DSCR_I2C */
46725 +#define MCF_GPIO_DSCR_I2C_I2C(x) (((x)&0x03))
46726 +#define MCF_GPIO_DSCR_I2C_I2C_LOAD_50PF (0x03)
46727 +#define MCF_GPIO_DSCR_I2C_I2C_LOAD_30PF (0x02)
46728 +#define MCF_GPIO_DSCR_I2C_I2C_LOAD_20PF (0x01)
46729 +#define MCF_GPIO_DSCR_I2C_I2C_LOAD_10PF (0x00)
46730 +
46731 +/* Bit definitions and macros for DSCR_FLEXBUS */
46732 +#define MCF_GPIO_DSCR_FLEXBUS_FBADL(x) (((x)&0x03))
46733 +#define MCF_GPIO_DSCR_FLEXBUS_FBADH(x) (((x)&0x03)<<2)
46734 +#define MCF_GPIO_DSCR_FLEXBUS_FBCTL(x) (((x)&0x03)<<4)
46735 +#define MCF_GPIO_DSCR_FLEXBUS_FBCLK(x) (((x)&0x03)<<6)
46736 +#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF (0xC0)
46737 +#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30P (0x80)
46738 +#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF (0x40)
46739 +#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF (0x00)
46740 +#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF (0x30)
46741 +#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF (0x20)
46742 +#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF (0x10)
46743 +#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF (0x00)
46744 +#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF (0x0C)
46745 +#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF (0x08)
46746 +#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF (0x04)
46747 +#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF (0x00)
46748 +#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF (0x03)
46749 +#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF (0x02)
46750 +#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF (0x01)
46751 +#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF (0x00)
46752 +
46753 +/* Bit definitions and macros for DSCR_FEC */
46754 +#define MCF_GPIO_DSCR_FEC_FEC0(x) (((x)&0x03))
46755 +#define MCF_GPIO_DSCR_FEC_FEC1(x) (((x)&0x03)<<2)
46756 +#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_50PF (0x0C)
46757 +#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_30PF (0x08)
46758 +#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_20PF (0x04)
46759 +#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_10PF (0x00)
46760 +#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_50PF (0x03)
46761 +#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_30PF (0x02)
46762 +#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_20PF (0x01)
46763 +#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_10PF (0x00)
46764 +
46765 +/* Bit definitions and macros for DSCR_UART */
46766 +#define MCF_GPIO_DSCR_UART_UART0(x) (((x)&0x03))
46767 +#define MCF_GPIO_DSCR_UART_UART1(x) (((x)&0x03)<<2)
46768 +#define MCF_GPIO_DSCR_UART_UART1_LOAD_50PF (0x0C)
46769 +#define MCF_GPIO_DSCR_UART_UART1_LOAD_30PF (0x08)
46770 +#define MCF_GPIO_DSCR_UART_UART1_LOAD_20PF (0x04)
46771 +#define MCF_GPIO_DSCR_UART_UART1_LOAD_10PF (0x00)
46772 +#define MCF_GPIO_DSCR_UART_UART0_LOAD_50PF (0x03)
46773 +#define MCF_GPIO_DSCR_UART_UART0_LOAD_30PF (0x02)
46774 +#define MCF_GPIO_DSCR_UART_UART0_LOAD_20PF (0x01)
46775 +#define MCF_GPIO_DSCR_UART_UART0_LOAD_10PF (0x00)
46776 +
46777 +/* Bit definitions and macros for DSCR_DSPI */
46778 +#define MCF_GPIO_DSCR_DSPI_DSPI(x) (((x)&0x03))
46779 +#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_50PF (0x03)
46780 +#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_30PF (0x02)
46781 +#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_20PF (0x01)
46782 +#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_10PF (0x00)
46783 +
46784 +/* Bit definitions and macros for DSCR_TIMER */
46785 +#define MCF_GPIO_DSCR_TIMER_TIMER(x) (((x)&0x03))
46786 +#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_50PF (0x03)
46787 +#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_30PF (0x02)
46788 +#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_20PF (0x01)
46789 +#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_10PF (0x00)
46790 +
46791 +/* Bit definitions and macros for DSCR_SSI */
46792 +#define MCF_GPIO_DSCR_SSI_SSI(x) (((x)&0x03))
46793 +#define MCF_GPIO_DSCR_SSI_SSI_LOAD_50PF (0x03)
46794 +#define MCF_GPIO_DSCR_SSI_SSI_LOAD_30PF (0x02)
46795 +#define MCF_GPIO_DSCR_SSI_SSI_LOAD_20PF (0x01)
46796 +#define MCF_GPIO_DSCR_SSI_SSI_LOAD_10PF (0x00)
46797 +
46798 +/* Bit definitions and macros for DSCR_DMA */
46799 +#define MCF_GPIO_DSCR_DMA_DMA(x) (((x)&0x03))
46800 +#define MCF_GPIO_DSCR_DMA_DMA_LOAD_50PF (0x03)
46801 +#define MCF_GPIO_DSCR_DMA_DMA_LOAD_30PF (0x02)
46802 +#define MCF_GPIO_DSCR_DMA_DMA_LOAD_20PF (0x01)
46803 +#define MCF_GPIO_DSCR_DMA_DMA_LOAD_10PF (0x00)
46804 +
46805 +/* Bit definitions and macros for DSCR_DEBUG */
46806 +#define MCF_GPIO_DSCR_DEBUG_DEBUG(x) (((x)&0x03))
46807 +#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF (0x03)
46808 +#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF (0x02)
46809 +#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF (0x01)
46810 +#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF (0x00)
46811 +
46812 +/* Bit definitions and macros for DSCR_RESET */
46813 +#define MCF_GPIO_DSCR_RESET_RESET(x) (((x)&0x03))
46814 +#define MCF_GPIO_DSCR_RESET_RESET_LOAD_50PF (0x03)
46815 +#define MCF_GPIO_DSCR_RESET_RESET_LOAD_30PF (0x02)
46816 +#define MCF_GPIO_DSCR_RESET_RESET_LOAD_20PF (0x01)
46817 +#define MCF_GPIO_DSCR_RESET_RESET_LOAD_10PF (0x00)
46818 +
46819 +/* Bit definitions and macros for DSCR_IRQ */
46820 +#define MCF_GPIO_DSCR_IRQ_IRQ(x) (((x)&0x03))
46821 +#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_50PF (0x03)
46822 +#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_30PF (0x02)
46823 +#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_20PF (0x01)
46824 +#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_10PF (0x00)
46825 +
46826 +/* Bit definitions and macros for DSCR_USB */
46827 +#define MCF_GPIO_DSCR_USB_USB(x) (((x)&0x03))
46828 +#define MCF_GPIO_DSCR_USB_USB_LOAD_50PF (0x03)
46829 +#define MCF_GPIO_DSCR_USB_USB_LOAD_30PF (0x02)
46830 +#define MCF_GPIO_DSCR_USB_USB_LOAD_20PF (0x01)
46831 +#define MCF_GPIO_DSCR_USB_USB_LOAD_10PF (0x00)
46832 +
46833 +/* Bit definitions and macros for DSCR_ATA */
46834 +#define MCF_GPIO_DSCR_ATA_ATA(x) (((x)&0x03))
46835 +#define MCF_GPIO_DSCR_ATA_ATA_LOAD_50PF (0x03)
46836 +#define MCF_GPIO_DSCR_ATA_ATA_LOAD_30PF (0x02)
46837 +#define MCF_GPIO_DSCR_ATA_ATA_LOAD_20PF (0x01)
46838 +#define MCF_GPIO_DSCR_ATA_ATA_LOAD_10PF (0x00)
46839 +
46840 +/********************************************************************/
46841 +
46842 +#endif /* __MCF5445X_GPIO_H__ */
46843 --- /dev/null
46844 +++ b/include/asm-m68k/mcf5445x_i2c.h
46845 @@ -0,0 +1,39 @@
46846 +/*
46847 + * Matt Waddel Matt.Waddel@freescale.com
46848 + *
46849 + * Copyright Freescale Semiconductor, Inc. 2007
46850 + *
46851 + * This program is free software; you can redistribute it and/or modify it
46852 + * under the terms of the GNU General Public License as published by the
46853 + * Free Software Foundation; either version 2 of the License, or (at your
46854 + * option) any later version.
46855 + */
46856 +
46857 +#ifndef __MCF5445X_I2C_H__
46858 +#define __MCF5445X_I2C_H__
46859 +
46860 +/*********************************************************************
46861 +*
46862 +* I2C Module (I2C)
46863 +*
46864 +*********************************************************************/
46865 +
46866 +/* Register read/write macros */
46867 +#define MCF_I2C_I2ADR (volatile u8 *)(0xFC058000)
46868 +#define MCF_I2C_I2FDR (volatile u8 *)(0xFC058004)
46869 +#define MCF_I2C_I2CR (volatile u8 *)(0xFC058008)
46870 +#define MCF_I2C_I2SR (volatile u8 *)(0xFC05800C)
46871 +#define MCF_I2C_I2DR (volatile u8 *)(0xFC058010)
46872 +
46873 +/* Bit definitions and macros for I2AR */
46874 +#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1)
46875 +
46876 +/* Bit definitions and macros for I2FDR */
46877 +#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F))
46878 +
46879 +/* Bit definitions and macros for I2DR */
46880 +#define MCF_I2C_I2DR_DATA(x) (x)
46881 +
46882 +/********************************************************************/
46883 +
46884 +#endif /* __MCF5445X_I2C_H__ */
46885 --- /dev/null
46886 +++ b/include/asm-m68k/mcf5445x_intc.h
46887 @@ -0,0 +1,724 @@
46888 +/*
46889 + * Matt Waddel Matt.Waddel@freescale.com
46890 + *
46891 + * Copyright Freescale Semiconductor, Inc. 2007
46892 + *
46893 + * This program is free software; you can redistribute it and/or modify it
46894 + * under the terms of the GNU General Public License as published by the
46895 + * Free Software Foundation; either version 2 of the License, or (at your
46896 + * option) any later version.
46897 + */
46898 +
46899 +#ifndef __MCF5445X_INTC_H__
46900 +#define __MCF5445X_INTC_H__
46901 +
46902 +/*********************************************************************
46903 +*
46904 +* Interrupt Controller (INTC)
46905 +*
46906 +*********************************************************************/
46907 +
46908 +/* Register read/write macros */
46909 +#define MCF_INTC0_IPRH MCF_REG32(0xFC048000)
46910 +#define MCF_INTC0_IPRL MCF_REG32(0xFC048004)
46911 +#define MCF_INTC0_IMRH MCF_REG32(0xFC048008)
46912 +#define MCF_INTC0_IMRL MCF_REG32(0xFC04800C)
46913 +#define MCF_INTC0_INTFRCH MCF_REG32(0xFC048010)
46914 +#define MCF_INTC0_INTFRCL MCF_REG32(0xFC048014)
46915 +#define MCF_INTC0_ICONFIG MCF_REG16(0xFC04801A)
46916 +#define MCF_INTC0_SIMR MCF_REG08(0xFC04801C)
46917 +#define MCF_INTC0_CIMR MCF_REG08(0xFC04801D)
46918 +#define MCF_INTC0_CLMASK MCF_REG08(0xFC04801E)
46919 +#define MCF_INTC0_SLMASK MCF_REG08(0xFC04801F)
46920 +#define MCF_INTC0_ICR1 MCF_REG08(0xFC048041)
46921 +#define MCF_INTC0_ICR2 MCF_REG08(0xFC048042)
46922 +#define MCF_INTC0_ICR3 MCF_REG08(0xFC048043)
46923 +#define MCF_INTC0_ICR4 MCF_REG08(0xFC048044)
46924 +#define MCF_INTC0_ICR5 MCF_REG08(0xFC048045)
46925 +#define MCF_INTC0_ICR6 MCF_REG08(0xFC048046)
46926 +#define MCF_INTC0_ICR7 MCF_REG08(0xFC048047)
46927 +#define MCF_INTC0_ICR8 MCF_REG08(0xFC048048)
46928 +#define MCF_INTC0_ICR9 MCF_REG08(0xFC048049)
46929 +#define MCF_INTC0_ICR10 MCF_REG08(0xFC04804A)
46930 +#define MCF_INTC0_ICR11 MCF_REG08(0xFC04804B)
46931 +#define MCF_INTC0_ICR12 MCF_REG08(0xFC04804C)
46932 +#define MCF_INTC0_ICR13 MCF_REG08(0xFC04804D)
46933 +#define MCF_INTC0_ICR14 MCF_REG08(0xFC04804E)
46934 +#define MCF_INTC0_ICR15 MCF_REG08(0xFC04804F)
46935 +#define MCF_INTC0_ICR16 MCF_REG08(0xFC048050)
46936 +#define MCF_INTC0_ICR17 MCF_REG08(0xFC048051)
46937 +#define MCF_INTC0_ICR18 MCF_REG08(0xFC048052)
46938 +#define MCF_INTC0_ICR19 MCF_REG08(0xFC048053)
46939 +#define MCF_INTC0_ICR20 MCF_REG08(0xFC048054)
46940 +#define MCF_INTC0_ICR21 MCF_REG08(0xFC048055)
46941 +#define MCF_INTC0_ICR22 MCF_REG08(0xFC048056)
46942 +#define MCF_INTC0_ICR23 MCF_REG08(0xFC048057)
46943 +#define MCF_INTC0_ICR24 MCF_REG08(0xFC048058)
46944 +#define MCF_INTC0_ICR25 MCF_REG08(0xFC048059)
46945 +#define MCF_INTC0_ICR26 MCF_REG08(0xFC04805A)
46946 +#define MCF_INTC0_ICR27 MCF_REG08(0xFC04805B)
46947 +#define MCF_INTC0_ICR28 MCF_REG08(0xFC04805C)
46948 +#define MCF_INTC0_ICR29 MCF_REG08(0xFC04805D)
46949 +#define MCF_INTC0_ICR30 MCF_REG08(0xFC04805E)
46950 +#define MCF_INTC0_ICR31 MCF_REG08(0xFC04805F)
46951 +#define MCF_INTC0_ICR32 MCF_REG08(0xFC048060)
46952 +#define MCF_INTC0_ICR33 MCF_REG08(0xFC048061)
46953 +#define MCF_INTC0_ICR34 MCF_REG08(0xFC048062)
46954 +#define MCF_INTC0_ICR35 MCF_REG08(0xFC048063)
46955 +#define MCF_INTC0_ICR36 MCF_REG08(0xFC048064)
46956 +#define MCF_INTC0_ICR37 MCF_REG08(0xFC048065)
46957 +#define MCF_INTC0_ICR38 MCF_REG08(0xFC048066)
46958 +#define MCF_INTC0_ICR39 MCF_REG08(0xFC048067)
46959 +#define MCF_INTC0_ICR40 MCF_REG08(0xFC048068)
46960 +#define MCF_INTC0_ICR41 MCF_REG08(0xFC048069)
46961 +#define MCF_INTC0_ICR42 MCF_REG08(0xFC04806A)
46962 +#define MCF_INTC0_ICR43 MCF_REG08(0xFC04806B)
46963 +#define MCF_INTC0_ICR44 MCF_REG08(0xFC04806C)
46964 +#define MCF_INTC0_ICR45 MCF_REG08(0xFC04806D)
46965 +#define MCF_INTC0_ICR46 MCF_REG08(0xFC04806E)
46966 +#define MCF_INTC0_ICR47 MCF_REG08(0xFC04806F)
46967 +#define MCF_INTC0_ICR48 MCF_REG08(0xFC048070)
46968 +#define MCF_INTC0_ICR49 MCF_REG08(0xFC048071)
46969 +#define MCF_INTC0_ICR50 MCF_REG08(0xFC048072)
46970 +#define MCF_INTC0_ICR51 MCF_REG08(0xFC048073)
46971 +#define MCF_INTC0_ICR52 MCF_REG08(0xFC048074)
46972 +#define MCF_INTC0_ICR53 MCF_REG08(0xFC048075)
46973 +#define MCF_INTC0_ICR54 MCF_REG08(0xFC048076)
46974 +#define MCF_INTC0_ICR55 MCF_REG08(0xFC048077)
46975 +#define MCF_INTC0_ICR56 MCF_REG08(0xFC048078)
46976 +#define MCF_INTC0_ICR57 MCF_REG08(0xFC048079)
46977 +#define MCF_INTC0_ICR58 MCF_REG08(0xFC04807A)
46978 +#define MCF_INTC0_ICR59 MCF_REG08(0xFC04807B)
46979 +#define MCF_INTC0_ICR60 MCF_REG08(0xFC04807C)
46980 +#define MCF_INTC0_ICR61 MCF_REG08(0xFC04807D)
46981 +#define MCF_INTC0_ICR62 MCF_REG08(0xFC04807E)
46982 +#define MCF_INTC0_ICR63 MCF_REG08(0xFC04807F)
46983 +#define MCF_INTC0_SWIACK MCF_REG08(0xFC0480E0)
46984 +#define MCF_INTC0_L1IACK MCF_REG08(0xFC0480E4)
46985 +#define MCF_INTC0_L2IACK MCF_REG08(0xFC0480E8)
46986 +#define MCF_INTC0_L3IACK MCF_REG08(0xFC0480EC)
46987 +#define MCF_INTC0_L4IACK MCF_REG08(0xFC0480F0)
46988 +#define MCF_INTC0_L5IACK MCF_REG08(0xFC0480F4)
46989 +#define MCF_INTC0_L6IACK MCF_REG08(0xFC0480F8)
46990 +#define MCF_INTC0_L7IACK MCF_REG08(0xFC0480FC)
46991 +#define MCF_INTC1_IPRH MCF_REG32(0xFC04C000)
46992 +#define MCF_INTC1_IPRL MCF_REG32(0xFC04C004)
46993 +#define MCF_INTC1_IMRH MCF_REG32(0xFC04C008)
46994 +#define MCF_INTC1_IMRL MCF_REG32(0xFC04C00C)
46995 +#define MCF_INTC1_INTFRCH MCF_REG32(0xFC04C010)
46996 +#define MCF_INTC1_INTFRCL MCF_REG32(0xFC04C014)
46997 +#define MCF_INTC1_ICONFIG MCF_REG16(0xFC04C01A)
46998 +#define MCF_INTC1_SIMR MCF_REG08(0xFC04C01C)
46999 +#define MCF_INTC1_CIMR MCF_REG08(0xFC04C01D)
47000 +#define MCF_INTC1_CLMASK MCF_REG08(0xFC04C01E)
47001 +#define MCF_INTC1_SLMASK MCF_REG08(0xFC04C01F)
47002 +#define MCF_INTC1_ICR1 MCF_REG08(0xFC04C041)
47003 +#define MCF_INTC1_ICR2 MCF_REG08(0xFC04C042)
47004 +#define MCF_INTC1_ICR3 MCF_REG08(0xFC04C043)
47005 +#define MCF_INTC1_ICR4 MCF_REG08(0xFC04C044)
47006 +#define MCF_INTC1_ICR5 MCF_REG08(0xFC04C045)
47007 +#define MCF_INTC1_ICR6 MCF_REG08(0xFC04C046)
47008 +#define MCF_INTC1_ICR7 MCF_REG08(0xFC04C047)
47009 +#define MCF_INTC1_ICR8 MCF_REG08(0xFC04C048)
47010 +#define MCF_INTC1_ICR9 MCF_REG08(0xFC04C049)
47011 +#define MCF_INTC1_ICR10 MCF_REG08(0xFC04C04A)
47012 +#define MCF_INTC1_ICR11 MCF_REG08(0xFC04C04B)
47013 +#define MCF_INTC1_ICR12 MCF_REG08(0xFC04C04C)
47014 +#define MCF_INTC1_ICR13 MCF_REG08(0xFC04C04D)
47015 +#define MCF_INTC1_ICR14 MCF_REG08(0xFC04C04E)
47016 +#define MCF_INTC1_ICR15 MCF_REG08(0xFC04C04F)
47017 +#define MCF_INTC1_ICR16 MCF_REG08(0xFC04C050)
47018 +#define MCF_INTC1_ICR17 MCF_REG08(0xFC04C051)
47019 +#define MCF_INTC1_ICR18 MCF_REG08(0xFC04C052)
47020 +#define MCF_INTC1_ICR19 MCF_REG08(0xFC04C053)
47021 +#define MCF_INTC1_ICR20 MCF_REG08(0xFC04C054)
47022 +#define MCF_INTC1_ICR21 MCF_REG08(0xFC04C055)
47023 +#define MCF_INTC1_ICR22 MCF_REG08(0xFC04C056)
47024 +#define MCF_INTC1_ICR23 MCF_REG08(0xFC04C057)
47025 +#define MCF_INTC1_ICR24 MCF_REG08(0xFC04C058)
47026 +#define MCF_INTC1_ICR25 MCF_REG08(0xFC04C059)
47027 +#define MCF_INTC1_ICR26 MCF_REG08(0xFC04C05A)
47028 +#define MCF_INTC1_ICR27 MCF_REG08(0xFC04C05B)
47029 +#define MCF_INTC1_ICR28 MCF_REG08(0xFC04C05C)
47030 +#define MCF_INTC1_ICR29 MCF_REG08(0xFC04C05D)
47031 +#define MCF_INTC1_ICR30 MCF_REG08(0xFC04C05E)
47032 +#define MCF_INTC1_ICR31 MCF_REG08(0xFC04C05F)
47033 +#define MCF_INTC1_ICR32 MCF_REG08(0xFC04C060)
47034 +#define MCF_INTC1_ICR33 MCF_REG08(0xFC04C061)
47035 +#define MCF_INTC1_ICR34 MCF_REG08(0xFC04C062)
47036 +#define MCF_INTC1_ICR35 MCF_REG08(0xFC04C063)
47037 +#define MCF_INTC1_ICR36 MCF_REG08(0xFC04C064)
47038 +#define MCF_INTC1_ICR37 MCF_REG08(0xFC04C065)
47039 +#define MCF_INTC1_ICR38 MCF_REG08(0xFC04C066)
47040 +#define MCF_INTC1_ICR39 MCF_REG08(0xFC04C067)
47041 +#define MCF_INTC1_ICR40 MCF_REG08(0xFC04C068)
47042 +#define MCF_INTC1_ICR41 MCF_REG08(0xFC04C069)
47043 +#define MCF_INTC1_ICR42 MCF_REG08(0xFC04C06A)
47044 +#define MCF_INTC1_ICR43 MCF_REG08(0xFC04C06B)
47045 +#define MCF_INTC1_ICR44 MCF_REG08(0xFC04C06C)
47046 +#define MCF_INTC1_ICR45 MCF_REG08(0xFC04C06D)
47047 +#define MCF_INTC1_ICR46 MCF_REG08(0xFC04C06E)
47048 +#define MCF_INTC1_ICR47 MCF_REG08(0xFC04C06F)
47049 +#define MCF_INTC1_ICR48 MCF_REG08(0xFC04C070)
47050 +#define MCF_INTC1_ICR49 MCF_REG08(0xFC04C071)
47051 +#define MCF_INTC1_ICR50 MCF_REG08(0xFC04C072)
47052 +#define MCF_INTC1_ICR51 MCF_REG08(0xFC04C073)
47053 +#define MCF_INTC1_ICR52 MCF_REG08(0xFC04C074)
47054 +#define MCF_INTC1_ICR53 MCF_REG08(0xFC04C075)
47055 +#define MCF_INTC1_ICR54 MCF_REG08(0xFC04C076)
47056 +#define MCF_INTC1_ICR55 MCF_REG08(0xFC04C077)
47057 +#define MCF_INTC1_ICR56 MCF_REG08(0xFC04C078)
47058 +#define MCF_INTC1_ICR57 MCF_REG08(0xFC04C079)
47059 +#define MCF_INTC1_ICR58 MCF_REG08(0xFC04C07A)
47060 +#define MCF_INTC1_ICR59 MCF_REG08(0xFC04C07B)
47061 +#define MCF_INTC1_ICR60 MCF_REG08(0xFC04C07C)
47062 +#define MCF_INTC1_ICR61 MCF_REG08(0xFC04C07D)
47063 +#define MCF_INTC1_ICR62 MCF_REG08(0xFC04C07E)
47064 +#define MCF_INTC1_ICR63 MCF_REG08(0xFC04C07F)
47065 +#define MCF_INTC1_SWIACK MCF_REG08(0xFC04C0E0)
47066 +#define MCF_INTC1_L1IACK MCF_REG08(0xFC04C0E4)
47067 +#define MCF_INTC1_L2IACK MCF_REG08(0xFC04C0E8)
47068 +#define MCF_INTC1_L3IACK MCF_REG08(0xFC04C0EC)
47069 +#define MCF_INTC1_L4IACK MCF_REG08(0xFC04C0F0)
47070 +#define MCF_INTC1_L5IACK MCF_REG08(0xFC04C0F4)
47071 +#define MCF_INTC1_L6IACK MCF_REG08(0xFC04C0F8
47072 +#define MCF_INTC1_L7IACK MCF_REG08(0xFC04C0FC)
47073 +
47074 +/* Parameterized register read/write macros for multiple registers */
47075 +#define MCF_INTC0_ICR(x) MCF_REG08(0xFC048041+((x-1)*0x001))
47076 +#define MCF_INTC0_LIACK(x) MCF_REG08(0xFC0480E4+((x-1)*0x004))
47077 +#define MCF_INTC1_ICR(x) MCF_REG08(0xFC04C041+((x-1)*0x001))
47078 +#define MCF_INTC1_LIACK(x) MCF_REG08(0xFC04C0E4+((x-1)*0x004))
47079 +
47080 +/* Parameterized register read/write macros for multiple modules */
47081 +#define MCF_INTC_IPRH(x) MCF_REG32(0xFC048000+((x)*0x4000))
47082 +#define MCF_INTC_IPRL(x) MCF_REG32(0xFC048004+((x)*0x4000))
47083 +#define MCF_INTC_IMRH(x) MCF_REG32(0xFC048008+((x)*0x4000))
47084 +#define MCF_INTC_IMRL(x) MCF_REG32(0xFC04800C+((x)*0x4000))
47085 +#define MCF_INTC_INTFRCH(x) MCF_REG32(0xFC048010+((x)*0x4000))
47086 +#define MCF_INTC_INTFRCL(x) MCF_REG32(0xFC048014+((x)*0x4000))
47087 +#define MCF_INTC_ICONFIG(x) MCF_REG16(0xFC04801A+((x)*0x4000))
47088 +#define MCF_INTC_SIMR(x) MCF_REG08(0xFC04801C+((x)*0x4000))
47089 +#define MCF_INTC_CIMR(x) MCF_REG08(0xFC04801D+((x)*0x4000))
47090 +#define MCF_INTC_CLMASK(x) MCF_REG08(0xFC04801E+((x)*0x4000))
47091 +#define MCF_INTC_SLMASK(x) MCF_REG08(0xFC04801F+((x)*0x4000))
47092 +#define MCF_INTC_ICR1(x) MCF_REG08(0xFC048041+((x)*0x4000))
47093 +#define MCF_INTC_ICR2(x) MCF_REG08(0xFC048042+((x)*0x4000))
47094 +#define MCF_INTC_ICR3(x) MCF_REG08(0xFC048043+((x)*0x4000))
47095 +#define MCF_INTC_ICR4(x) MCF_REG08(0xFC048044+((x)*0x4000))
47096 +#define MCF_INTC_ICR5(x) MCF_REG08(0xFC048045+((x)*0x4000))
47097 +#define MCF_INTC_ICR6(x) MCF_REG08(0xFC048046+((x)*0x4000))
47098 +#define MCF_INTC_ICR7(x) MCF_REG08(0xFC048047+((x)*0x4000))
47099 +#define MCF_INTC_ICR8(x) MCF_REG08(0xFC048048+((x)*0x4000))
47100 +#define MCF_INTC_ICR9(x) MCF_REG08(0xFC048049+((x)*0x4000))
47101 +#define MCF_INTC_ICR10(x) MCF_REG08(0xFC04804A+((x)*0x4000))
47102 +#define MCF_INTC_ICR11(x) MCF_REG08(0xFC04804B+((x)*0x4000))
47103 +#define MCF_INTC_ICR12(x) MCF_REG08(0xFC04804C+((x)*0x4000))
47104 +#define MCF_INTC_ICR13(x) MCF_REG08(0xFC04804D+((x)*0x4000))
47105 +#define MCF_INTC_ICR14(x) MCF_REG08(0xFC04804E+((x)*0x4000))
47106 +#define MCF_INTC_ICR15(x) MCF_REG08(0xFC04804F+((x)*0x4000))
47107 +#define MCF_INTC_ICR16(x) MCF_REG08(0xFC048050+((x)*0x4000))
47108 +#define MCF_INTC_ICR17(x) MCF_REG08(0xFC048051+((x)*0x4000))
47109 +#define MCF_INTC_ICR18(x) MCF_REG08(0xFC048052+((x)*0x4000))
47110 +#define MCF_INTC_ICR19(x) MCF_REG08(0xFC048053+((x)*0x4000))
47111 +#define MCF_INTC_ICR20(x) MCF_REG08(0xFC048054+((x)*0x4000))
47112 +#define MCF_INTC_ICR21(x) MCF_REG08(0xFC048055+((x)*0x4000))
47113 +#define MCF_INTC_ICR22(x) MCF_REG08(0xFC048056+((x)*0x4000))
47114 +#define MCF_INTC_ICR23(x) MCF_REG08(0xFC048057+((x)*0x4000))
47115 +#define MCF_INTC_ICR24(x) MCF_REG08(0xFC048058+((x)*0x4000))
47116 +#define MCF_INTC_ICR25(x) MCF_REG08(0xFC048059+((x)*0x4000))
47117 +#define MCF_INTC_ICR26(x) MCF_REG08(0xFC04805A+((x)*0x4000))
47118 +#define MCF_INTC_ICR27(x) MCF_REG08(0xFC04805B+((x)*0x4000))
47119 +#define MCF_INTC_ICR28(x) MCF_REG08(0xFC04805C+((x)*0x4000))
47120 +#define MCF_INTC_ICR29(x) MCF_REG08(0xFC04805D+((x)*0x4000))
47121 +#define MCF_INTC_ICR30(x) MCF_REG08(0xFC04805E+((x)*0x4000))
47122 +#define MCF_INTC_ICR31(x) MCF_REG08(0xFC04805F+((x)*0x4000))
47123 +#define MCF_INTC_ICR32(x) MCF_REG08(0xFC048060+((x)*0x4000))
47124 +#define MCF_INTC_ICR33(x) MCF_REG08(0xFC048061+((x)*0x4000))
47125 +#define MCF_INTC_ICR34(x) MCF_REG08(0xFC048062+((x)*0x4000))
47126 +#define MCF_INTC_ICR35(x) MCF_REG08(0xFC048063+((x)*0x4000))
47127 +#define MCF_INTC_ICR36(x) MCF_REG08(0xFC048064+((x)*0x4000))
47128 +#define MCF_INTC_ICR37(x) MCF_REG08(0xFC048065+((x)*0x4000))
47129 +#define MCF_INTC_ICR38(x) MCF_REG08(0xFC048066+((x)*0x4000))
47130 +#define MCF_INTC_ICR39(x) MCF_REG08(0xFC048067+((x)*0x4000))
47131 +#define MCF_INTC_ICR40(x) MCF_REG08(0xFC048068+((x)*0x4000))
47132 +#define MCF_INTC_ICR41(x) MCF_REG08(0xFC048069+((x)*0x4000))
47133 +#define MCF_INTC_ICR42(x) MCF_REG08(0xFC04806A+((x)*0x4000))
47134 +#define MCF_INTC_ICR43(x) MCF_REG08(0xFC04806B+((x)*0x4000))
47135 +#define MCF_INTC_ICR44(x) MCF_REG08(0xFC04806C+((x)*0x4000))
47136 +#define MCF_INTC_ICR45(x) MCF_REG08(0xFC04806D+((x)*0x4000))
47137 +#define MCF_INTC_ICR46(x) MCF_REG08(0xFC04806E+((x)*0x4000))
47138 +#define MCF_INTC_ICR47(x) MCF_REG08(0xFC04806F+((x)*0x4000))
47139 +#define MCF_INTC_ICR48(x) MCF_REG08(0xFC048070+((x)*0x4000))
47140 +#define MCF_INTC_ICR49(x) MCF_REG08(0xFC048071+((x)*0x4000))
47141 +#define MCF_INTC_ICR50(x) MCF_REG08(0xFC048072+((x)*0x4000))
47142 +#define MCF_INTC_ICR51(x) MCF_REG08(0xFC048073+((x)*0x4000))
47143 +#define MCF_INTC_ICR52(x) MCF_REG08(0xFC048074+((x)*0x4000))
47144 +#define MCF_INTC_ICR53(x) MCF_REG08(0xFC048075+((x)*0x4000))
47145 +#define MCF_INTC_ICR54(x) MCF_REG08(0xFC048076+((x)*0x4000))
47146 +#define MCF_INTC_ICR55(x) MCF_REG08(0xFC048077+((x)*0x4000))
47147 +#define MCF_INTC_ICR56(x) MCF_REG08(0xFC048078+((x)*0x4000))
47148 +#define MCF_INTC_ICR57(x) MCF_REG08(0xFC048079+((x)*0x4000))
47149 +#define MCF_INTC_ICR58(x) MCF_REG08(0xFC04807A+((x)*0x4000))
47150 +#define MCF_INTC_ICR59(x) MCF_REG08(0xFC04807B+((x)*0x4000))
47151 +#define MCF_INTC_ICR60(x) MCF_REG08(0xFC04807C+((x)*0x4000))
47152 +#define MCF_INTC_ICR61(x) MCF_REG08(0xFC04807D+((x)*0x4000))
47153 +#define MCF_INTC_ICR62(x) MCF_REG08(0xFC04807E+((x)*0x4000))
47154 +#define MCF_INTC_ICR63(x) MCF_REG08(0xFC04807F+((x)*0x4000))
47155 +#define MCF_INTC_SWIACK(x) MCF_REG08(0xFC0480E0+((x)*0x4000))
47156 +#define MCF_INTC_L1IACK(x) MCF_REG08(0xFC0480E4+((x)*0x4000))
47157 +#define MCF_INTC_L2IACK(x) MCF_REG08(0xFC0480E8+((x)*0x4000))
47158 +#define MCF_INTC_L3IACK(x) MCF_REG08(0xFC0480EC+((x)*0x4000))
47159 +#define MCF_INTC_L4IACK(x) MCF_REG08(0xFC0480F0+((x)*0x4000))
47160 +#define MCF_INTC_L5IACK(x) MCF_REG08(0xFC0480F4+((x)*0x4000))
47161 +#define MCF_INTC_L6IACK(x) MCF_REG08(0xFC0480F8+((x)*0x4000))
47162 +#define MCF_INTC_L7IACK(x) MCF_REG08(0xFC0480FC+((x)*0x4000))
47163 +
47164 +/* Bit definitions and macros for IPRH */
47165 +#define MCF_INTC_IPRH_INT32 (0x00000001)
47166 +#define MCF_INTC_IPRH_INT33 (0x00000002)
47167 +#define MCF_INTC_IPRH_INT34 (0x00000004)
47168 +#define MCF_INTC_IPRH_INT35 (0x00000008)
47169 +#define MCF_INTC_IPRH_INT36 (0x00000010)
47170 +#define MCF_INTC_IPRH_INT37 (0x00000020)
47171 +#define MCF_INTC_IPRH_INT38 (0x00000040)
47172 +#define MCF_INTC_IPRH_INT39 (0x00000080)
47173 +#define MCF_INTC_IPRH_INT40 (0x00000100)
47174 +#define MCF_INTC_IPRH_INT41 (0x00000200)
47175 +#define MCF_INTC_IPRH_INT42 (0x00000400)
47176 +#define MCF_INTC_IPRH_INT43 (0x00000800)
47177 +#define MCF_INTC_IPRH_INT44 (0x00001000)
47178 +#define MCF_INTC_IPRH_INT45 (0x00002000)
47179 +#define MCF_INTC_IPRH_INT46 (0x00004000)
47180 +#define MCF_INTC_IPRH_INT47 (0x00008000)
47181 +#define MCF_INTC_IPRH_INT48 (0x00010000)
47182 +#define MCF_INTC_IPRH_INT49 (0x00020000)
47183 +#define MCF_INTC_IPRH_INT50 (0x00040000)
47184 +#define MCF_INTC_IPRH_INT51 (0x00080000)
47185 +#define MCF_INTC_IPRH_INT52 (0x00100000)
47186 +#define MCF_INTC_IPRH_INT53 (0x00200000)
47187 +#define MCF_INTC_IPRH_INT54 (0x00400000)
47188 +#define MCF_INTC_IPRH_INT55 (0x00800000)
47189 +#define MCF_INTC_IPRH_INT56 (0x01000000)
47190 +#define MCF_INTC_IPRH_INT57 (0x02000000)
47191 +#define MCF_INTC_IPRH_INT58 (0x04000000)
47192 +#define MCF_INTC_IPRH_INT59 (0x08000000)
47193 +#define MCF_INTC_IPRH_INT60 (0x10000000)
47194 +#define MCF_INTC_IPRH_INT61 (0x20000000)
47195 +#define MCF_INTC_IPRH_INT62 (0x40000000)
47196 +#define MCF_INTC_IPRH_INT63 (0x80000000)
47197 +
47198 +/* Bit definitions and macros for IPRL */
47199 +#define MCF_INTC_IPRL_INT0 (0x00000001)
47200 +#define MCF_INTC_IPRL_INT1 (0x00000002)
47201 +#define MCF_INTC_IPRL_INT2 (0x00000004)
47202 +#define MCF_INTC_IPRL_INT3 (0x00000008)
47203 +#define MCF_INTC_IPRL_INT4 (0x00000010)
47204 +#define MCF_INTC_IPRL_INT5 (0x00000020)
47205 +#define MCF_INTC_IPRL_INT6 (0x00000040)
47206 +#define MCF_INTC_IPRL_INT7 (0x00000080)
47207 +#define MCF_INTC_IPRL_INT8 (0x00000100)
47208 +#define MCF_INTC_IPRL_INT9 (0x00000200)
47209 +#define MCF_INTC_IPRL_INT10 (0x00000400)
47210 +#define MCF_INTC_IPRL_INT11 (0x00000800)
47211 +#define MCF_INTC_IPRL_INT12 (0x00001000)
47212 +#define MCF_INTC_IPRL_INT13 (0x00002000)
47213 +#define MCF_INTC_IPRL_INT14 (0x00004000)
47214 +#define MCF_INTC_IPRL_INT15 (0x00008000)
47215 +#define MCF_INTC_IPRL_INT16 (0x00010000)
47216 +#define MCF_INTC_IPRL_INT17 (0x00020000)
47217 +#define MCF_INTC_IPRL_INT18 (0x00040000)
47218 +#define MCF_INTC_IPRL_INT19 (0x00080000)
47219 +#define MCF_INTC_IPRL_INT20 (0x00100000)
47220 +#define MCF_INTC_IPRL_INT21 (0x00200000)
47221 +#define MCF_INTC_IPRL_INT22 (0x00400000)
47222 +#define MCF_INTC_IPRL_INT23 (0x00800000)
47223 +#define MCF_INTC_IPRL_INT24 (0x01000000)
47224 +#define MCF_INTC_IPRL_INT25 (0x02000000)
47225 +#define MCF_INTC_IPRL_INT26 (0x04000000)
47226 +#define MCF_INTC_IPRL_INT27 (0x08000000)
47227 +#define MCF_INTC_IPRL_INT28 (0x10000000)
47228 +#define MCF_INTC_IPRL_INT29 (0x20000000)
47229 +#define MCF_INTC_IPRL_INT30 (0x40000000)
47230 +#define MCF_INTC_IPRL_INT31 (0x80000000)
47231 +
47232 +/* Bit definitions and macros for IMRH */
47233 +#define MCF_INTC_IMRH_INT_MASK32 (0x00000001)
47234 +#define MCF_INTC_IMRH_INT_MASK33 (0x00000002)
47235 +#define MCF_INTC_IMRH_INT_MASK34 (0x00000004)
47236 +#define MCF_INTC_IMRH_INT_MASK35 (0x00000008)
47237 +#define MCF_INTC_IMRH_INT_MASK36 (0x00000010)
47238 +#define MCF_INTC_IMRH_INT_MASK37 (0x00000020)
47239 +#define MCF_INTC_IMRH_INT_MASK38 (0x00000040)
47240 +#define MCF_INTC_IMRH_INT_MASK39 (0x00000080)
47241 +#define MCF_INTC_IMRH_INT_MASK40 (0x00000100)
47242 +#define MCF_INTC_IMRH_INT_MASK41 (0x00000200)
47243 +#define MCF_INTC_IMRH_INT_MASK42 (0x00000400)
47244 +#define MCF_INTC_IMRH_INT_MASK43 (0x00000800)
47245 +#define MCF_INTC_IMRH_INT_MASK44 (0x00001000)
47246 +#define MCF_INTC_IMRH_INT_MASK45 (0x00002000)
47247 +#define MCF_INTC_IMRH_INT_MASK46 (0x00004000)
47248 +#define MCF_INTC_IMRH_INT_MASK47 (0x00008000)
47249 +#define MCF_INTC_IMRH_INT_MASK48 (0x00010000)
47250 +#define MCF_INTC_IMRH_INT_MASK49 (0x00020000)
47251 +#define MCF_INTC_IMRH_INT_MASK50 (0x00040000)
47252 +#define MCF_INTC_IMRH_INT_MASK51 (0x00080000)
47253 +#define MCF_INTC_IMRH_INT_MASK52 (0x00100000)
47254 +#define MCF_INTC_IMRH_INT_MASK53 (0x00200000)
47255 +#define MCF_INTC_IMRH_INT_MASK54 (0x00400000)
47256 +#define MCF_INTC_IMRH_INT_MASK55 (0x00800000)
47257 +#define MCF_INTC_IMRH_INT_MASK56 (0x01000000)
47258 +#define MCF_INTC_IMRH_INT_MASK57 (0x02000000)
47259 +#define MCF_INTC_IMRH_INT_MASK58 (0x04000000)
47260 +#define MCF_INTC_IMRH_INT_MASK59 (0x08000000)
47261 +#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
47262 +#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
47263 +#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
47264 +#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
47265 +
47266 +/* Bit definitions and macros for IMRL */
47267 +#define MCF_INTC_IMRL_INT_MASK0 (0x00000001)
47268 +#define MCF_INTC_IMRL_INT_MASK1 (0x00000002)
47269 +#define MCF_INTC_IMRL_INT_MASK2 (0x00000004)
47270 +#define MCF_INTC_IMRL_INT_MASK3 (0x00000008)
47271 +#define MCF_INTC_IMRL_INT_MASK4 (0x00000010)
47272 +#define MCF_INTC_IMRL_INT_MASK5 (0x00000020)
47273 +#define MCF_INTC_IMRL_INT_MASK6 (0x00000040)
47274 +#define MCF_INTC_IMRL_INT_MASK7 (0x00000080)
47275 +#define MCF_INTC_IMRL_INT_MASK8 (0x00000100)
47276 +#define MCF_INTC_IMRL_INT_MASK9 (0x00000200)
47277 +#define MCF_INTC_IMRL_INT_MASK10 (0x00000400)
47278 +#define MCF_INTC_IMRL_INT_MASK11 (0x00000800)
47279 +#define MCF_INTC_IMRL_INT_MASK12 (0x00001000)
47280 +#define MCF_INTC_IMRL_INT_MASK13 (0x00002000)
47281 +#define MCF_INTC_IMRL_INT_MASK14 (0x00004000)
47282 +#define MCF_INTC_IMRL_INT_MASK15 (0x00008000)
47283 +#define MCF_INTC_IMRL_INT_MASK16 (0x00010000)
47284 +#define MCF_INTC_IMRL_INT_MASK17 (0x00020000)
47285 +#define MCF_INTC_IMRL_INT_MASK18 (0x00040000)
47286 +#define MCF_INTC_IMRL_INT_MASK19 (0x00080000)
47287 +#define MCF_INTC_IMRL_INT_MASK20 (0x00100000)
47288 +#define MCF_INTC_IMRL_INT_MASK21 (0x00200000)
47289 +#define MCF_INTC_IMRL_INT_MASK22 (0x00400000)
47290 +#define MCF_INTC_IMRL_INT_MASK23 (0x00800000)
47291 +#define MCF_INTC_IMRL_INT_MASK24 (0x01000000)
47292 +#define MCF_INTC_IMRL_INT_MASK25 (0x02000000)
47293 +#define MCF_INTC_IMRL_INT_MASK26 (0x04000000)
47294 +#define MCF_INTC_IMRL_INT_MASK27 (0x08000000)
47295 +#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
47296 +#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
47297 +#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
47298 +#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
47299 +
47300 +/* Bit definitions and macros for INTFRCH */
47301 +#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001)
47302 +#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002)
47303 +#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004)
47304 +#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008)
47305 +#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010)
47306 +#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020)
47307 +#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040)
47308 +#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080)
47309 +#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100)
47310 +#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200)
47311 +#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400)
47312 +#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800)
47313 +#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000)
47314 +#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000)
47315 +#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000)
47316 +#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000)
47317 +#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000)
47318 +#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000)
47319 +#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000)
47320 +#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000)
47321 +#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000)
47322 +#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000)
47323 +#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000)
47324 +#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000)
47325 +#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000)
47326 +#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000)
47327 +#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000)
47328 +#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000)
47329 +#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
47330 +#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
47331 +#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
47332 +#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
47333 +
47334 +/* Bit definitions and macros for INTFRCL */
47335 +#define MCF_INTC_INTFRCL_INTFRC0 (0x00000001)
47336 +#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002)
47337 +#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004)
47338 +#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008)
47339 +#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010)
47340 +#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020)
47341 +#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040)
47342 +#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080)
47343 +#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100)
47344 +#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200)
47345 +#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400)
47346 +#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800)
47347 +#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000)
47348 +#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000)
47349 +#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000)
47350 +#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000)
47351 +#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000)
47352 +#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000)
47353 +#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000)
47354 +#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000)
47355 +#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000)
47356 +#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000)
47357 +#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000)
47358 +#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000)
47359 +#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000)
47360 +#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000)
47361 +#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000)
47362 +#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000)
47363 +#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
47364 +#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
47365 +#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
47366 +#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
47367 +
47368 +/* Bit definitions and macros for ICONFIG */
47369 +#define MCF_INTC_ICONFIG_EMASK (0x0020)
47370 +#define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200)
47371 +#define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400)
47372 +#define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800)
47373 +#define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000)
47374 +#define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000)
47375 +#define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000)
47376 +#define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000)
47377 +
47378 +/* Bit definitions and macros for SIMR */
47379 +#define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F))
47380 +
47381 +/* Bit definitions and macros for CIMR */
47382 +#define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F))
47383 +
47384 +/* Bit definitions and macros for CLMASK */
47385 +#define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F))
47386 +
47387 +/* Bit definitions and macros for SLMASK */
47388 +#define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F))
47389 +
47390 +/* Bit definitions and macros for ICR group */
47391 +#define MCF_INTC_ICR_IL(x) (((x)&0x07))
47392 +
47393 +/* Bit definitions and macros for ICR1 */
47394 +#define MCF_INTC_ICR1_IL(x) (((x)&0x07))
47395 +
47396 +/* Bit definitions and macros for ICR2 */
47397 +#define MCF_INTC_ICR2_IL(x) (((x)&0x07))
47398 +
47399 +/* Bit definitions and macros for ICR3 */
47400 +#define MCF_INTC_ICR3_IL(x) (((x)&0x07))
47401 +
47402 +/* Bit definitions and macros for ICR4 */
47403 +#define MCF_INTC_ICR4_IL(x) (((x)&0x07))
47404 +
47405 +/* Bit definitions and macros for ICR5 */
47406 +#define MCF_INTC_ICR5_IL(x) (((x)&0x07))
47407 +
47408 +/* Bit definitions and macros for ICR6 */
47409 +#define MCF_INTC_ICR6_IL(x) (((x)&0x07))
47410 +
47411 +/* Bit definitions and macros for ICR7 */
47412 +#define MCF_INTC_ICR7_IL(x) (((x)&0x07))
47413 +
47414 +/* Bit definitions and macros for ICR8 */
47415 +#define MCF_INTC_ICR8_IL(x) (((x)&0x07))
47416 +
47417 +/* Bit definitions and macros for ICR9 */
47418 +#define MCF_INTC_ICR9_IL(x) (((x)&0x07))
47419 +
47420 +/* Bit definitions and macros for ICR10 */
47421 +#define MCF_INTC_ICR10_IL(x) (((x)&0x07))
47422 +
47423 +/* Bit definitions and macros for ICR11 */
47424 +#define MCF_INTC_ICR11_IL(x) (((x)&0x07))
47425 +
47426 +/* Bit definitions and macros for ICR12 */
47427 +#define MCF_INTC_ICR12_IL(x) (((x)&0x07))
47428 +
47429 +/* Bit definitions and macros for ICR13 */
47430 +#define MCF_INTC_ICR13_IL(x) (((x)&0x07))
47431 +
47432 +/* Bit definitions and macros for ICR14 */
47433 +#define MCF_INTC_ICR14_IL(x) (((x)&0x07))
47434 +
47435 +/* Bit definitions and macros for ICR15 */
47436 +#define MCF_INTC_ICR15_IL(x) (((x)&0x07))
47437 +
47438 +/* Bit definitions and macros for ICR16 */
47439 +#define MCF_INTC_ICR16_IL(x) (((x)&0x07))
47440 +
47441 +/* Bit definitions and macros for ICR17 */
47442 +#define MCF_INTC_ICR17_IL(x) (((x)&0x07))
47443 +
47444 +/* Bit definitions and macros for ICR18 */
47445 +#define MCF_INTC_ICR18_IL(x) (((x)&0x07))
47446 +
47447 +/* Bit definitions and macros for ICR19 */
47448 +#define MCF_INTC_ICR19_IL(x) (((x)&0x07))
47449 +
47450 +/* Bit definitions and macros for ICR20 */
47451 +#define MCF_INTC_ICR20_IL(x) (((x)&0x07))
47452 +
47453 +/* Bit definitions and macros for ICR21 */
47454 +#define MCF_INTC_ICR21_IL(x) (((x)&0x07))
47455 +
47456 +/* Bit definitions and macros for ICR22 */
47457 +#define MCF_INTC_ICR22_IL(x) (((x)&0x07))
47458 +
47459 +/* Bit definitions and macros for ICR23 */
47460 +#define MCF_INTC_ICR23_IL(x) (((x)&0x07))
47461 +
47462 +/* Bit definitions and macros for ICR24 */
47463 +#define MCF_INTC_ICR24_IL(x) (((x)&0x07))
47464 +
47465 +/* Bit definitions and macros for ICR25 */
47466 +#define MCF_INTC_ICR25_IL(x) (((x)&0x07))
47467 +
47468 +/* Bit definitions and macros for ICR26 */
47469 +#define MCF_INTC_ICR26_IL(x) (((x)&0x07))
47470 +
47471 +/* Bit definitions and macros for ICR27 */
47472 +#define MCF_INTC_ICR27_IL(x) (((x)&0x07))
47473 +
47474 +/* Bit definitions and macros for ICR28 */
47475 +#define MCF_INTC_ICR28_IL(x) (((x)&0x07))
47476 +
47477 +/* Bit definitions and macros for ICR29 */
47478 +#define MCF_INTC_ICR29_IL(x) (((x)&0x07))
47479 +
47480 +/* Bit definitions and macros for ICR30 */
47481 +#define MCF_INTC_ICR30_IL(x) (((x)&0x07))
47482 +
47483 +/* Bit definitions and macros for ICR31 */
47484 +#define MCF_INTC_ICR31_IL(x) (((x)&0x07))
47485 +
47486 +/* Bit definitions and macros for ICR32 */
47487 +#define MCF_INTC_ICR32_IL(x) (((x)&0x07))
47488 +
47489 +/* Bit definitions and macros for ICR33 */
47490 +#define MCF_INTC_ICR33_IL(x) (((x)&0x07))
47491 +
47492 +/* Bit definitions and macros for ICR34 */
47493 +#define MCF_INTC_ICR34_IL(x) (((x)&0x07))
47494 +
47495 +/* Bit definitions and macros for ICR35 */
47496 +#define MCF_INTC_ICR35_IL(x) (((x)&0x07))
47497 +
47498 +/* Bit definitions and macros for ICR36 */
47499 +#define MCF_INTC_ICR36_IL(x) (((x)&0x07))
47500 +
47501 +/* Bit definitions and macros for ICR37 */
47502 +#define MCF_INTC_ICR37_IL(x) (((x)&0x07))
47503 +
47504 +/* Bit definitions and macros for ICR38 */
47505 +#define MCF_INTC_ICR38_IL(x) (((x)&0x07))
47506 +
47507 +/* Bit definitions and macros for ICR39 */
47508 +#define MCF_INTC_ICR39_IL(x) (((x)&0x07))
47509 +
47510 +/* Bit definitions and macros for ICR40 */
47511 +#define MCF_INTC_ICR40_IL(x) (((x)&0x07))
47512 +
47513 +/* Bit definitions and macros for ICR41 */
47514 +#define MCF_INTC_ICR41_IL(x) (((x)&0x07))
47515 +
47516 +/* Bit definitions and macros for ICR42 */
47517 +#define MCF_INTC_ICR42_IL(x) (((x)&0x07))
47518 +
47519 +/* Bit definitions and macros for ICR43 */
47520 +#define MCF_INTC_ICR43_IL(x) (((x)&0x07))
47521 +
47522 +/* Bit definitions and macros for ICR44 */
47523 +#define MCF_INTC_ICR44_IL(x) (((x)&0x07))
47524 +
47525 +/* Bit definitions and macros for ICR45 */
47526 +#define MCF_INTC_ICR45_IL(x) (((x)&0x07))
47527 +
47528 +/* Bit definitions and macros for ICR46 */
47529 +#define MCF_INTC_ICR46_IL(x) (((x)&0x07))
47530 +
47531 +/* Bit definitions and macros for ICR47 */
47532 +#define MCF_INTC_ICR47_IL(x) (((x)&0x07))
47533 +
47534 +/* Bit definitions and macros for ICR48 */
47535 +#define MCF_INTC_ICR48_IL(x) (((x)&0x07))
47536 +
47537 +/* Bit definitions and macros for ICR49 */
47538 +#define MCF_INTC_ICR49_IL(x) (((x)&0x07))
47539 +
47540 +/* Bit definitions and macros for ICR50 */
47541 +#define MCF_INTC_ICR50_IL(x) (((x)&0x07))
47542 +
47543 +/* Bit definitions and macros for ICR51 */
47544 +#define MCF_INTC_ICR51_IL(x) (((x)&0x07))
47545 +
47546 +/* Bit definitions and macros for ICR52 */
47547 +#define MCF_INTC_ICR52_IL(x) (((x)&0x07))
47548 +
47549 +/* Bit definitions and macros for ICR53 */
47550 +#define MCF_INTC_ICR53_IL(x) (((x)&0x07))
47551 +
47552 +/* Bit definitions and macros for ICR54 */
47553 +#define MCF_INTC_ICR54_IL(x) (((x)&0x07))
47554 +
47555 +/* Bit definitions and macros for ICR55 */
47556 +#define MCF_INTC_ICR55_IL(x) (((x)&0x07))
47557 +
47558 +/* Bit definitions and macros for ICR56 */
47559 +#define MCF_INTC_ICR56_IL(x) (((x)&0x07))
47560 +
47561 +/* Bit definitions and macros for ICR57 */
47562 +#define MCF_INTC_ICR57_IL(x) (((x)&0x07))
47563 +
47564 +/* Bit definitions and macros for ICR58 */
47565 +#define MCF_INTC_ICR58_IL(x) (((x)&0x07))
47566 +
47567 +/* Bit definitions and macros for ICR59 */
47568 +#define MCF_INTC_ICR59_IL(x) (((x)&0x07))
47569 +
47570 +/* Bit definitions and macros for ICR60 */
47571 +#define MCF_INTC_ICR60_IL(x) (((x)&0x07))
47572 +
47573 +/* Bit definitions and macros for ICR61 */
47574 +#define MCF_INTC_ICR61_IL(x) (((x)&0x07))
47575 +
47576 +/* Bit definitions and macros for ICR62 */
47577 +#define MCF_INTC_ICR62_IL(x) (((x)&0x07))
47578 +
47579 +/* Bit definitions and macros for ICR63 */
47580 +#define MCF_INTC_ICR63_IL(x) (((x)&0x07))
47581 +
47582 +/* Bit definitions and macros for SWIACK */
47583 +#define MCF_INTC_SWIACK_VECTOR(x) (x)
47584 +
47585 +/* Bit definitions and macros for LIACK group */
47586 +#define MCF_INTC_LIACK_VECTOR(x) (x)
47587 +
47588 +/* Bit definitions and macros for L1IACK */
47589 +#define MCF_INTC_L1IACK_VECTOR(x) (x)
47590 +
47591 +/* Bit definitions and macros for L2IACK */
47592 +#define MCF_INTC_L2IACK_VECTOR(x) (x)
47593 +
47594 +/* Bit definitions and macros for L3IACK */
47595 +#define MCF_INTC_L3IACK_VECTOR(x) (x)
47596 +
47597 +/* Bit definitions and macros for L4IACK */
47598 +#define MCF_INTC_L4IACK_VECTOR(x) (x)
47599 +
47600 +/* Bit definitions and macros for L5IACK */
47601 +#define MCF_INTC_L5IACK_VECTOR(x) (x)
47602 +
47603 +/* Bit definitions and macros for L6IACK */
47604 +#define MCF_INTC_L6IACK_VECTOR(x) (x)
47605 +
47606 +/* Bit definitions and macros for L7IACK */
47607 +#define MCF_INTC_L7IACK_VECTOR(x) (x)
47608 +
47609 +/********************************************************************/
47610 +
47611 +#endif /* __MCF5445X_INTC_H__ */
47612 --- /dev/null
47613 +++ b/include/asm-m68k/mcf5445x_pciarb.h
47614 @@ -0,0 +1,40 @@
47615 +/*
47616 + * Kurt Mahan kmahan@freescale.com
47617 + *
47618 + * Copyright Freescale Semiconductor, Inc. 2007
47619 + *
47620 + * This program is free software; you can redistribute it and/or modify it
47621 + * under the terms of the GNU General Public License as published by the
47622 + * Free Software Foundation; either version 2 of the License, or (at your
47623 + * option) any later version.
47624 + */
47625 +
47626 +#ifndef __MCF5445X_PCIARB_H__
47627 +#define __MCF5445X_PCIARB_H__
47628 +
47629 +/*********************************************************************
47630 +*
47631 +* PCI Arbiter Module (PCIARB)
47632 +*
47633 +*********************************************************************/
47634 +
47635 +/* Register read/write macros */
47636 +#define MCF_PCIARB_PACR MCF_REG32(0xFC0AC000)
47637 +#define MCF_PCIARB_PASR MCF_REG32(0xFC0AC004)
47638 +
47639 +/* Bit definitions and macros for PACR */
47640 +#define MCF_PCIARB_PACR_INTMPRI (0x00000001)
47641 +#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x0000001F)<<1)
47642 +#define MCF_PCIARB_PACR_RA (0x00008000)
47643 +#define MCF_PCIARB_PACR_INTMINTEN (0x00010000)
47644 +#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x0000001F)<<17)
47645 +#define MCF_PCIARB_PACR_PKMD (0x40000000)
47646 +#define MCF_PCIARB_PACR_DS (0x80000000)
47647 +
47648 +/* Bit definitions and macros for PASR */
47649 +#define MCF_PCIARB_PASR_ITLMBK (0x00010000)
47650 +#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x0000001F)<<17)
47651 +
47652 +/********************************************************************/
47653 +
47654 +#endif /* __MCF5445X_PCIARB_H__ */
47655 --- /dev/null
47656 +++ b/include/asm-m68k/mcf5445x_pci.h
47657 @@ -0,0 +1,238 @@
47658 +/*
47659 + * Kurt Mahan kmahan@freescale.com
47660 + *
47661 + * Copyright Freescale Semiconductor, Inc. 2007
47662 + *
47663 + * This program is free software; you can redistribute it and/or modify it
47664 + * under the terms of the GNU General Public License as published by the
47665 + * Free Software Foundation; either version 2 of the License, or (at your
47666 + * option) any later version.
47667 + */
47668 +
47669 +#ifndef __MCF5445X_PCI_H__
47670 +#define __MCF5445X_PCI_H__
47671 +
47672 +/*********************************************************************
47673 +*
47674 +* PCI Bus Controller (PCI)
47675 +*
47676 +*********************************************************************/
47677 +
47678 +/* Register read/write macros */
47679 +#define MCF_PCI_PCIIDR MCF_REG32(0xFC0A8000)
47680 +#define MCF_PCI_PCISCR MCF_REG32(0xFC0A8004)
47681 +#define MCF_PCI_PCICCRIR MCF_REG32(0xFC0A8008)
47682 +#define MCF_PCI_PCICR1 MCF_REG32(0xFC0A800C)
47683 +#define MCF_PCI_PCIBAR0 MCF_REG32(0xFC0A8010)
47684 +#define MCF_PCI_PCIBAR1 MCF_REG32(0xFC0A8014)
47685 +#define MCF_PCI_PCIBAR2 MCF_REG32(0xFC0A8018)
47686 +#define MCF_PCI_PCIBAR3 MCF_REG32(0xFC0A801C)
47687 +#define MCF_PCI_PCIBAR4 MCF_REG32(0xFC0A8020)
47688 +#define MCF_PCI_PCIBAR5 MCF_REG32(0xFC0A8024)
47689 +#define MCF_PCI_PCISID MCF_REG32(0xFC0A802C)
47690 +#define MCF_PCI_PCICR2 MCF_REG32(0xFC0A803C)
47691 +#define MCF_PCI_PCIGSCR MCF_REG32(0xFC0A8060)
47692 +#define MCF_PCI_PCITBATR0A MCF_REG32(0xFC0A8064)
47693 +#define MCF_PCI_PCITBATR1A MCF_REG32(0xFC0A8068)
47694 +#define MCF_PCI_PCITCR MCF_REG32(0xFC0A806C)
47695 +#define MCF_PCI_PCIIW0BTAR MCF_REG32(0xFC0A8070)
47696 +#define MCF_PCI_PCIIW1BTAR MCF_REG32(0xFC0A8074)
47697 +#define MCF_PCI_PCIIW2BTAR MCF_REG32(0xFC0A8078)
47698 +#define MCF_PCI_PCIIWCR MCF_REG32(0xFC0A8080)
47699 +#define MCF_PCI_PCIICR MCF_REG32(0xFC0A8084)
47700 +#define MCF_PCI_PCIISR MCF_REG32(0xFC0A8088)
47701 +#define MCF_PCI_PCITCR2 MCF_REG32(0xFC0A808C)
47702 +#define MCF_PCI_PCITBATR0 MCF_REG32(0xFC0A8090)
47703 +#define MCF_PCI_PCITBATR1 MCF_REG32(0xFC0A8094)
47704 +#define MCF_PCI_PCITBATR2 MCF_REG32(0xFC0A8098)
47705 +#define MCF_PCI_PCITBATR3 MCF_REG32(0xFC0A809C)
47706 +#define MCF_PCI_PCITBATR4 MCF_REG32(0xFC0A80A0)
47707 +#define MCF_PCI_PCITBATR5 MCF_REG32(0xFC0A80A4)
47708 +#define MCF_PCI_PCICAR MCF_REG32(0xFC0A80F8)
47709 +
47710 +/* Parameterized register read/write macros for multiple registers */
47711 +#define MCF_PCI_PCIIWBTAR(x) MCF_REG32(0xFC0A8070+((x)*0x004))
47712 +
47713 +/* Bit definitions and macros for PCIIDR */
47714 +#define MCF_PCI_PCIIDR_VENDORID(x) (((x)&0x0000FFFF))
47715 +#define MCF_PCI_PCIIDR_DEVICEID(x) (((x)&0x0000FFFF)<<16)
47716 +
47717 +/* Bit definitions and macros for PCISCR */
47718 +#define MCF_PCI_PCISCR_M (0x00000002)
47719 +#define MCF_PCI_PCISCR_B (0x00000004)
47720 +#define MCF_PCI_PCISCR_SP (0x00000008)
47721 +#define MCF_PCI_PCISCR_MW (0x00000010)
47722 +#define MCF_PCI_PCISCR_PER (0x00000040)
47723 +#define MCF_PCI_PCISCR_S (0x00000100)
47724 +#define MCF_PCI_PCISCR_F (0x00000200)
47725 +#define MCF_PCI_PCISCR_C (0x00100000)
47726 +#define MCF_PCI_PCISCR_66M (0x00200000)
47727 +#define MCF_PCI_PCISCR_R (0x00400000)
47728 +#define MCF_PCI_PCISCR_FC (0x00800000)
47729 +#define MCF_PCI_PCISCR_DP (0x01000000)
47730 +#define MCF_PCI_PCISCR_DT(x) (((x)&0x00000003)<<25)
47731 +#define MCF_PCI_PCISCR_TS (0x08000000)
47732 +#define MCF_PCI_PCISCR_TR (0x10000000)
47733 +#define MCF_PCI_PCISCR_MA (0x20000000)
47734 +#define MCF_PCI_PCISCR_SE (0x40000000)
47735 +#define MCF_PCI_PCISCR_PE (0x80000000)
47736 +
47737 +/* Bit definitions and macros for PCICCRIR */
47738 +#define MCF_PCI_PCICCRIR_REVID(x) (((x)&0x000000FF))
47739 +#define MCF_PCI_PCICCRIR_CLASSCODE(x) (((x)&0x00FFFFFF)<<8)
47740 +
47741 +/* Bit definitions and macros for PCICR1 */
47742 +#define MCF_PCI_PCICR1_CACHELINESIZE(x) (((x)&0x0000000F))
47743 +#define MCF_PCI_PCICR1_LATTIMER(x) (((x)&0x000000FF)<<8)
47744 +#define MCF_PCI_PCICR1_HEADERTYPE(x) (((x)&0x000000FF)<<16)
47745 +#define MCF_PCI_PCICR1_BIST(x) (((x)&0x000000FF)<<24)
47746 +
47747 +/* Bit definitions and macros for PCIBAR0 */
47748 +#define MCF_PCI_PCIBAR0_IO (0x00000001)
47749 +#define MCF_PCI_PCIBAR0_RANGE(x) (((x)&0x00000003)<<1)
47750 +#define MCF_PCI_PCIBAR0_PREF (0x00000008)
47751 +#define MCF_PCI_PCIBAR0_BAR0(x) (((x)&0x00003FFF)<<18)
47752 +
47753 +/* Bit definitions and macros for PCIBAR1 */
47754 +#define MCF_PCI_PCIBAR1_IO (0x00000001)
47755 +#define MCF_PCI_PCIBAR1_PREF (0x00000008)
47756 +#define MCF_PCI_PCIBAR1_BAR1(x) (((x)&0x00000FFF)<<20)
47757 +
47758 +/* Bit definitions and macros for PCIBAR2 */
47759 +#define MCF_PCI_PCIBAR2_IO (0x00000001)
47760 +#define MCF_PCI_PCIBAR2_RANGE(x) (((x)&0x00000003)<<1)
47761 +#define MCF_PCI_PCIBAR2_PREF (0x00000008)
47762 +#define MCF_PCI_PCIBAR2_BAR2(x) (((x)&0x000003FF)<<22)
47763 +
47764 +/* Bit definitions and macros for PCIBAR3 */
47765 +#define MCF_PCI_PCIBAR3_IO (0x00000001)
47766 +#define MCF_PCI_PCIBAR3_PREF (0x00000008)
47767 +#define MCF_PCI_PCIBAR3_BAR3(x) (((x)&0x000000FF)<<24)
47768 +
47769 +/* Bit definitions and macros for PCIBAR4 */
47770 +#define MCF_PCI_PCIBAR4_IO (0x00000001)
47771 +#define MCF_PCI_PCIBAR4_RANGE(x) (((x)&0x00000003)<<1)
47772 +#define MCF_PCI_PCIBAR4_PREF (0x00000008)
47773 +#define MCF_PCI_PCIBAR4_BAR4(x) (((x)&0x0000001F)<<27)
47774 +
47775 +/* Bit definitions and macros for PCIBAR5 */
47776 +#define MCF_PCI_PCIBAR5_IO (0x00000001)
47777 +#define MCF_PCI_PCIBAR5_PREF (0x00000008)
47778 +#define MCF_PCI_PCIBAR5_BAR5(x) (((x)&0x0000000F)<<28)
47779 +
47780 +/* Bit definitions and macros for PCISID */
47781 +#define MCF_PCI_PCISID_VENDORID(x) (((x)&0x0000FFFF))
47782 +#define MCF_PCI_PCISID_ID(x) (((x)&0x0000FFFF)<<16)
47783 +
47784 +/* Bit definitions and macros for PCICR2 */
47785 +#define MCF_PCI_PCICR2_INTLINE(x) (((x)&0x000000FF))
47786 +#define MCF_PCI_PCICR2_INTPIN(x) (((x)&0x000000FF)<<8)
47787 +#define MCF_PCI_PCICR2_MINGNT(x) (((x)&0x000000FF)<<16)
47788 +#define MCF_PCI_PCICR2_MAXLAT(x) (((x)&0x000000FF)<<24)
47789 +
47790 +/* Bit definitions and macros for PCIGSCR */
47791 +#define MCF_PCI_PCIGSCR_PR (0x00000001)
47792 +#define MCF_PCI_PCIGSCR_SEE (0x00001000)
47793 +#define MCF_PCI_PCIGSCR_PEE (0x00002000)
47794 +#define MCF_PCI_PCIGSCR_SE (0x10000000)
47795 +#define MCF_PCI_PCIGSCR_PE (0x20000000)
47796 +
47797 +/* Bit definitions and macros for PCITBATR0A */
47798 +#define MCF_PCI_PCITBATR0A_EN (0x00000001)
47799 +#define MCF_PCI_PCITBATR0A_BAT0(x) (((x)&0x00003FFF)<<18)
47800 +
47801 +/* Bit definitions and macros for PCITBATR1A */
47802 +#define MCF_PCI_PCITBATR1A_EN (0x00000001)
47803 +#define MCF_PCI_PCITBATR1A_BAT1(x) (((x)&0x00000FFF)<<20)
47804 +
47805 +/* Bit definitions and macros for PCITCR */
47806 +#define MCF_PCI_PCITCR_WCT(x) (((x)&0x000000FF))
47807 +#define MCF_PCI_PCITCR_WCD (0x00000100)
47808 +#define MCF_PCI_PCITCR_P (0x00010000)
47809 +#define MCF_PCI_PCITCR_PID (0x00020000)
47810 +#define MCF_PCI_PCITCR_LD (0x01000000)
47811 +
47812 +/* Bit definitions and macros for PCIIWBTAR group */
47813 +#define MCF_PCI_PCIIWBTAR_WBA(x) ((((x)&0xFF000000)))
47814 +#define MCF_PCI_PCIIWBTAR_WAM(x) ((((x)&0xFF000000)
47815 +#define MCF_PCI_PCIIWBTAR_WTA(x) ((((x)&0xFF000000)
47816 +
47817 +/* Bit definitions and macros for PCIIW0BTAR */
47818 +#define MCF_PCI_PCIIW0BTAR_WBA(x) ((((x)&0xFF000000)))
47819 +#define MCF_PCI_PCIIW0BTAR_WAM(x) ((((x)&0xFF000000)
47820 +#define MCF_PCI_PCIIW0BTAR_WTA(x) ((((x)&0xFF000000)
47821 +
47822 +/* Bit definitions and macros for PCIIWCR */
47823 +#define MCF_PCI_PCIIWCR_WINCTRL2(x) (((x)&0x0000000F)<<8)
47824 +#define MCF_PCI_PCIIWCR_WINCTRL1(x) (((x)&0x0000000F)<<16)
47825 +#define MCF_PCI_PCIIWCR_WINCTRL0(x) (((x)&0x0000000F)<<24)
47826 +#define MCF_PCI_PCIIWCR_WINCTRL0_ENABLE (0x01000000)
47827 +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD (0x01000000)
47828 +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE (0x03000000)
47829 +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL (0x05000000)
47830 +#define MCF_PCI_PCIIWCR_WINCTRL0_IO (0x09000000)
47831 +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD (0x00010000)
47832 +#define MCF_PCI_PCIIWCR_WINCTRL1_ENABLE (0x00010000)
47833 +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE (0x00030000)
47834 +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL (0x00050000)
47835 +#define MCF_PCI_PCIIWCR_WINCTRL1_IO (0x00090000)
47836 +#define MCF_PCI_PCIIWCR_WINCTRL2_ENABLE (0x00000100)
47837 +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD (0x00000100)
47838 +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE (0x00000300)
47839 +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL (0x00000500)
47840 +#define MCF_PCI_PCIIWCR_WINCTRL2_IO (0x00000900)
47841 +
47842 +/* Bit definitions and macros for PCIICR */
47843 +#define MCF_PCI_PCIICR_MAXRETRY(x) (((x)&0x000000FF))
47844 +#define MCF_PCI_PCIICR_TAE (0x01000000)
47845 +#define MCF_PCI_PCIICR_IAE (0x02000000)
47846 +#define MCF_PCI_PCIICR_REE (0x04000000)
47847 +
47848 +/* Bit definitions and macros for PCIISR */
47849 +#define MCF_PCI_PCIISR_TA (0x01000000)
47850 +#define MCF_PCI_PCIISR_IA (0x02000000)
47851 +#define MCF_PCI_PCIISR_RE (0x04000000)
47852 +
47853 +/* Bit definitions and macros for PCITCR2 */
47854 +#define MCF_PCI_PCITCR2_CR (0x00000001)
47855 +#define MCF_PCI_PCITCR2_B0E (0x00000100)
47856 +#define MCF_PCI_PCITCR2_B1E (0x00000200)
47857 +#define MCF_PCI_PCITCR2_B2E (0x00000400)
47858 +#define MCF_PCI_PCITCR2_B3E (0x00000800)
47859 +#define MCF_PCI_PCITCR2_B4E (0x00001000)
47860 +#define MCF_PCI_PCITCR2_B5E (0x00002000)
47861 +
47862 +/* Bit definitions and macros for PCITBATR0 */
47863 +#define MCF_PCI_PCITBATR0_EN (0x00000001)
47864 +#define MCF_PCI_PCITBATR0_BAT0(x) (((x)&0x00003FFF)<<18)
47865 +
47866 +/* Bit definitions and macros for PCITBATR1 */
47867 +#define MCF_PCI_PCITBATR1_EN (0x00000001)
47868 +#define MCF_PCI_PCITBATR1_BAT1(x) (((x)&0x00000FFF)<<20)
47869 +
47870 +/* Bit definitions and macros for PCITBATR2 */
47871 +#define MCF_PCI_PCITBATR2_EN (0x00000001)
47872 +#define MCF_PCI_PCITBATR2_BAT2(x) (((x)&0x000003FF)<<22)
47873 +
47874 +/* Bit definitions and macros for PCITBATR3 */
47875 +#define MCF_PCI_PCITBATR3_EN (0x00000001)
47876 +#define MCF_PCI_PCITBATR3_BAT3(x) (((x)&0x000000FF)<<24)
47877 +
47878 +/* Bit definitions and macros for PCITBATR4 */
47879 +#define MCF_PCI_PCITBATR4_EN (0x00000001)
47880 +#define MCF_PCI_PCITBATR4_BAT4(x) (((x)&0x0000001F)<<27)
47881 +
47882 +/* Bit definitions and macros for PCITBATR5 */
47883 +#define MCF_PCI_PCITBATR5_EN (0x00000001)
47884 +#define MCF_PCI_PCITBATR5_BAT5(x) (((x)&0x0000000F)<<28)
47885 +
47886 +/* Bit definitions and macros for PCICAR */
47887 +#define MCF_PCI_PCICAR_DWORD(x) ((x)&0x000000FC)
47888 +#define MCF_PCI_PCICAR_FUNCNUM(x) (((x)&0x00000007)<<8)
47889 +#define MCF_PCI_PCICAR_DEVNUM(x) (((x)&0x0000001F)<<11)
47890 +#define MCF_PCI_PCICAR_BUSNUM(x) (((x)&0x000000FF)<<16)
47891 +#define MCF_PCI_PCICAR_E (0x80000000)
47892 +
47893 +/********************************************************************/
47894 +
47895 +#endif /* __MCF5445X_PCI_H__ */
47896 --- /dev/null
47897 +++ b/include/asm-m68k/mcf5445x_sdramc.h
47898 @@ -0,0 +1,115 @@
47899 +/*
47900 + * Matt Waddel Matt.Waddel@freescale.com
47901 + *
47902 + * Copyright Freescale Semiconductor, Inc. 2007
47903 + *
47904 + * This program is free software; you can redistribute it and/or modify it
47905 + * under the terms of the GNU General Public License as published by the
47906 + * Free Software Foundation; either version 2 of the License, or (at your
47907 + * option) any later version.
47908 + */
47909 +
47910 +#ifndef __MCF5445X_SDRAMC_H__
47911 +#define __MCF5445X_SDRAMC_H__
47912 +
47913 +/*********************************************************************
47914 +*
47915 +* SDRAM Controller (SDRAMC)
47916 +*
47917 +*********************************************************************/
47918 +
47919 +/* Register read/write macros */
47920 +#define MCF_SDRAMC_SDMR (*(vuint32 *)(0xFC0B8000)) /* SDRAM Mode/Extended Mode Register */
47921 +#define MCF_SDRAMC_SDCR (*(vuint32 *)(0xFC0B8004)) /* SDRAM Control Register */
47922 +#define MCF_SDRAMC_SDCFG1 (*(vuint32 *)(0xFC0B8008)) /* SDRAM Configuration Register 1 */
47923 +#define MCF_SDRAMC_SDCFG2 (*(vuint32 *)(0xFC0B800C)) /* SDRAM Configuration Register 2 */
47924 +#define MCF_SDRAMC_SDCS0 (*(vuint32 *)(0xFC0B8110)) /* SDRAM Chip Select Register */
47925 +#define MCF_SDRAMC_SDCS1 (*(vuint32 *)(0xFC0B8114)) /* SDRAM Chip Select Register */
47926 +
47927 +/* Parameterized register read/write macros for multiple registers */
47928 +#define MCF_SDRAMC_SDCS(x) (*(vuint32 *)(0xFC0B8110+((x)*0x004))) /* SDRAM Chip Select Register */
47929 +
47930 +/* Bit definitions and macros for SDMR */
47931 +#define MCF_SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */
47932 +#define MCF_SDRAMC_SDMR_CMD (0x00010000) /* Command */
47933 +#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */
47934 +#define MCF_SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */
47935 +#define MCF_SDRAMC_SDMR_BK_LMR (0x00000000)
47936 +#define MCF_SDRAMC_SDMR_BK_LEMR (0x40000000)
47937 +
47938 +/* Bit definitions and macros for SDCR */
47939 +#define MCF_SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */
47940 +#define MCF_SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */
47941 +#define MCF_SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */
47942 +#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */
47943 +#define MCF_SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */
47944 +#define MCF_SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */
47945 +#define MCF_SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */
47946 +#define MCF_SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */
47947 +#define MCF_SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */
47948 +#define MCF_SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */
47949 +#define MCF_SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */
47950 +#define MCF_SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */
47951 +#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */
47952 +#define MCF_SDRAMC_SDCR_DQS_OE_BOTH (0x00000C00)
47953 +
47954 +/* Bit definitions and macros for SDCFG1 */
47955 +#define MCF_SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */
47956 +#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */
47957 +#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */
47958 +#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */
47959 +#define MCF_SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */
47960 +#define MCF_SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */
47961 +#define MCF_SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */
47962 +
47963 +/* Bit definitions and macros for SDCFG2 */
47964 +#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */
47965 +#define MCF_SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */
47966 +#define MCF_SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */
47967 +#define MCF_SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */
47968 +
47969 +/* Bit definitions and macros for SDCS group */
47970 +#define MCF_SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */
47971 +#define MCF_SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */
47972 +#define MCF_SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
47973 +#define MCF_SDRAMC_SDCS_CSSZ_DISABLE (0x00000000)
47974 +#define MCF_SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
47975 +#define MCF_SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
47976 +#define MCF_SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
47977 +#define MCF_SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
47978 +#define MCF_SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
47979 +#define MCF_SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
47980 +#define MCF_SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
47981 +#define MCF_SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
47982 +#define MCF_SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
47983 +#define MCF_SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
47984 +#define MCF_SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
47985 +#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
47986 +#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
47987 +
47988 +/* Bit definitions and macros for SDCS0 */
47989 +#define MCF_SDRAMC_SDCS0_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */
47990 +#define MCF_SDRAMC_SDCS0_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */
47991 +#define MCF_SDRAMC_SDCS0_BA(x) ((x)&0xFFF00000)
47992 +#define MCF_SDRAMC_SDCS0_CSSZ_DISABLE (0x00000000)
47993 +#define MCF_SDRAMC_SDCS0_CSSZ_1MBYTE (0x00000013)
47994 +#define MCF_SDRAMC_SDCS0_CSSZ_2MBYTE (0x00000014)
47995 +#define MCF_SDRAMC_SDCS0_CSSZ_4MBYTE (0x00000015)
47996 +#define MCF_SDRAMC_SDCS0_CSSZ_8MBYTE (0x00000016)
47997 +#define MCF_SDRAMC_SDCS0_CSSZ_16MBYTE (0x00000017)
47998 +#define MCF_SDRAMC_SDCS0_CSSZ_32MBYTE (0x00000018)
47999 +#define MCF_SDRAMC_SDCS0_CSSZ_64MBYTE (0x00000019)
48000 +#define MCF_SDRAMC_SDCS0_CSSZ_128MBYTE (0x0000001A)
48001 +#define MCF_SDRAMC_SDCS0_CSSZ_256MBYTE (0x0000001B)
48002 +#define MCF_SDRAMC_SDCS0_CSSZ_512MBYTE (0x0000001C)
48003 +#define MCF_SDRAMC_SDCS0_CSSZ_1GBYTE (0x0000001D)
48004 +#define MCF_SDRAMC_SDCS0_CSSZ_2GBYTE (0x0000001E)
48005 +#define MCF_SDRAMC_SDCS0_CSSZ_4GBYTE (0x0000001F)
48006 +
48007 +/* Bit definitions and macros for SDCS1 */
48008 +#define MCF_SDRAMC_SDCS1_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */
48009 +#define MCF_SDRAMC_SDCS1_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */
48010 +
48011 +/********************************************************************/
48012 +
48013 +#endif /* __MCF5445X_SDRAMC_H__ */
48014 --- /dev/null
48015 +++ b/include/asm-m68k/mcf5445x_ssi.h
48016 @@ -0,0 +1,187 @@
48017 +/*
48018 + * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
48019 + *
48020 + * Copyright Freescale Semiconductor, Inc. 2007
48021 + *
48022 + * This program is free software; you can redistribute it and/or modify it
48023 + * under the terms of the GNU General Public License as published by the
48024 + * Free Software Foundation; either version 2 of the License, or (at your
48025 + * option) any later version.
48026 + */
48027 +
48028 +#ifndef __MCF5445X_SSI_H__
48029 +#define __MCF5445X_SSI_H__
48030 +
48031 +/*********************************************************************
48032 +*
48033 +* Synchronous Serial Interface (SSI)
48034 +*
48035 +*********************************************************************/
48036 +
48037 +/* Register read/write macros */
48038 +#define MCF_SSI_TX0 MCF_REG32(0xFC0BC000)
48039 +#define MCF_SSI_TX1 MCF_REG32(0xFC0BC004)
48040 +#define MCF_SSI_RX0 MCF_REG32(0xFC0BC008)
48041 +#define MCF_SSI_RX1 MCF_REG32(0xFC0BC00C)
48042 +#define MCF_SSI_CR MCF_REG32(0xFC0BC010)
48043 +#define MCF_SSI_ISR MCF_REG32(0xFC0BC014)
48044 +#define MCF_SSI_IER MCF_REG32(0xFC0BC018)
48045 +#define MCF_SSI_TCR MCF_REG32(0xFC0BC01C)
48046 +#define MCF_SSI_RCR MCF_REG32(0xFC0BC020)
48047 +#define MCF_SSI_CCR MCF_REG32(0xFC0BC024)
48048 +#define MCF_SSI_FCSR MCF_REG32(0xFC0BC02C)
48049 +#define MCF_SSI_ACR MCF_REG32(0xFC0BC038)
48050 +#define MCF_SSI_ACADD MCF_REG32(0xFC0BC03C)
48051 +#define MCF_SSI_ACDAT MCF_REG32(0xFC0BC040)
48052 +#define MCF_SSI_ATAG MCF_REG32(0xFC0BC044)
48053 +#define MCF_SSI_TMASK MCF_REG32(0xFC0BC048)
48054 +#define MCF_SSI_RMASK MCF_REG32(0xFC0BC04C)
48055 +
48056 +/* Parameterized register read/write macros for multiple registers */
48057 +#define MCF_SSI_TX(x) MCF_REG32(0xFC0BC000+((x)*0x004))
48058 +#define MCF_SSI_RX(x) MCF_REG32(0xFC0BC008+((x)*0x004))
48059 +
48060 +/* Bit definitions and macros for TX group */
48061 +#define MCF_SSI_TX_SSI_TX(x) (x)
48062 +
48063 +/* Bit definitions and macros for TX0 */
48064 +#define MCF_SSI_TX0_SSI_TX(x) (x)
48065 +
48066 +/* Bit definitions and macros for TX1 */
48067 +#define MCF_SSI_TX1_SSI_TX(x) (x)
48068 +
48069 +/* Bit definitions and macros for RX group */
48070 +#define MCF_SSI_RX_SSI_RX(x) (x)
48071 +
48072 +/* Bit definitions and macros for RX0 */
48073 +#define MCF_SSI_RX0_SSI_RX(x) (x)
48074 +
48075 +/* Bit definitions and macros for RX1 */
48076 +#define MCF_SSI_RX1_SSI_RX(x) (x)
48077 +
48078 +/* Bit definitions and macros for CR */
48079 +#define MCF_SSI_CR_SSI_EN (0x00000001)
48080 +#define MCF_SSI_CR_TE (0x00000002)
48081 +#define MCF_SSI_CR_RE (0x00000004)
48082 +#define MCF_SSI_CR_NET (0x00000008)
48083 +#define MCF_SSI_CR_SYN (0x00000010)
48084 +#define MCF_SSI_CR_I2S(x) (((x)&0x00000003)<<5)
48085 +#define MCF_SSI_CR_MCE (0x00000080)
48086 +#define MCF_SSI_CR_TCH (0x00000100)
48087 +#define MCF_SSI_CR_CIS (0x00000200)
48088 +#define MCF_SSI_CR_I2S_NORMAL (0x00000000)
48089 +#define MCF_SSI_CR_I2S_MASTER (0x00000020)
48090 +#define MCF_SSI_CR_I2S_SLAVE (0x00000040)
48091 +
48092 +/* Bit definitions and macros for ISR */
48093 +#define MCF_SSI_ISR_TFE0 (0x00000001)
48094 +#define MCF_SSI_ISR_TFE1 (0x00000002)
48095 +#define MCF_SSI_ISR_RFF0 (0x00000004)
48096 +#define MCF_SSI_ISR_RFF1 (0x00000008)
48097 +#define MCF_SSI_ISR_RLS (0x00000010)
48098 +#define MCF_SSI_ISR_TLS (0x00000020)
48099 +#define MCF_SSI_ISR_RFS (0x00000040)
48100 +#define MCF_SSI_ISR_TFS (0x00000080)
48101 +#define MCF_SSI_ISR_TUE0 (0x00000100)
48102 +#define MCF_SSI_ISR_TUE1 (0x00000200)
48103 +#define MCF_SSI_ISR_ROE0 (0x00000400)
48104 +#define MCF_SSI_ISR_ROE1 (0x00000800)
48105 +#define MCF_SSI_ISR_TDE0 (0x00001000)
48106 +#define MCF_SSI_ISR_TDE1 (0x00002000)
48107 +#define MCF_SSI_ISR_RDR0 (0x00004000)
48108 +#define MCF_SSI_ISR_RDR1 (0x00008000)
48109 +#define MCF_SSI_ISR_RXT (0x00010000)
48110 +#define MCF_SSI_ISR_CMDDU (0x00020000)
48111 +#define MCF_SSI_ISR_CMDAU (0x00040000)
48112 +
48113 +/* Bit definitions and macros for IER */
48114 +#define MCF_SSI_IER_TFE0 (0x00000001)
48115 +#define MCF_SSI_IER_TFE1 (0x00000002)
48116 +#define MCF_SSI_IER_RFF0 (0x00000004)
48117 +#define MCF_SSI_IER_RFF1 (0x00000008)
48118 +#define MCF_SSI_IER_RLS (0x00000010)
48119 +#define MCF_SSI_IER_TLS (0x00000020)
48120 +#define MCF_SSI_IER_RFS (0x00000040)
48121 +#define MCF_SSI_IER_TFS (0x00000080)
48122 +#define MCF_SSI_IER_TUE0 (0x00000100)
48123 +#define MCF_SSI_IER_TUE1 (0x00000200)
48124 +#define MCF_SSI_IER_ROE0 (0x00000400)
48125 +#define MCF_SSI_IER_ROE1 (0x00000800)
48126 +#define MCF_SSI_IER_TDE0 (0x00001000)
48127 +#define MCF_SSI_IER_TDE1 (0x00002000)
48128 +#define MCF_SSI_IER_RDR0 (0x00004000)
48129 +#define MCF_SSI_IER_RDR1 (0x00008000)
48130 +#define MCF_SSI_IER_RXT (0x00010000)
48131 +#define MCF_SSI_IER_CMDU (0x00020000)
48132 +#define MCF_SSI_IER_CMDAU (0x00040000)
48133 +#define MCF_SSI_IER_TIE (0x00080000)
48134 +#define MCF_SSI_IER_TDMAE (0x00100000)
48135 +#define MCF_SSI_IER_RIE (0x00200000)
48136 +#define MCF_SSI_IER_RDMAE (0x00400000)
48137 +
48138 +/* Bit definitions and macros for TCR */
48139 +#define MCF_SSI_TCR_TEFS (0x00000001)
48140 +#define MCF_SSI_TCR_TFSL (0x00000002)
48141 +#define MCF_SSI_TCR_TFSI (0x00000004)
48142 +#define MCF_SSI_TCR_TSCKP (0x00000008)
48143 +#define MCF_SSI_TCR_TSHFD (0x00000010)
48144 +#define MCF_SSI_TCR_TXDIR (0x00000020)
48145 +#define MCF_SSI_TCR_TFDIR (0x00000040)
48146 +#define MCF_SSI_TCR_TFEN0 (0x00000080)
48147 +#define MCF_SSI_TCR_TFEN1 (0x00000100)
48148 +#define MCF_SSI_TCR_TXBIT0 (0x00000200)
48149 +
48150 +/* Bit definitions and macros for RCR */
48151 +#define MCF_SSI_RCR_REFS (0x00000001)
48152 +#define MCF_SSI_RCR_RFSL (0x00000002)
48153 +#define MCF_SSI_RCR_RFSI (0x00000004)
48154 +#define MCF_SSI_RCR_RSCKP (0x00000008)
48155 +#define MCF_SSI_RCR_RSHFD (0x00000010)
48156 +#define MCF_SSI_RCR_RFEN0 (0x00000080)
48157 +#define MCF_SSI_RCR_RFEN1 (0x00000100)
48158 +#define MCF_SSI_RCR_RXBIT0 (0x00000200)
48159 +#define MCF_SSI_RCR_RXEXT (0x00000400)
48160 +
48161 +/* Bit definitions and macros for CCR */
48162 +#define MCF_SSI_CCR_PM(x) (((x)&0x000000FF))
48163 +#define MCF_SSI_CCR_DC(x) (((x)&0x0000001F)<<8)
48164 +#define MCF_SSI_CCR_WL(x) (((x)&0x0000000F)<<13)
48165 +#define MCF_SSI_CCR_PSR (0x00020000)
48166 +#define MCF_SSI_CCR_DIV2 (0x00040000)
48167 +
48168 +/* Bit definitions and macros for FCSR */
48169 +#define MCF_SSI_FCSR_TFWM0(x) (((x)&0x0000000F))
48170 +#define MCF_SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4)
48171 +#define MCF_SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8)
48172 +#define MCF_SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12)
48173 +#define MCF_SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16)
48174 +#define MCF_SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20)
48175 +#define MCF_SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24)
48176 +#define MCF_SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28)
48177 +
48178 +/* Bit definitions and macros for ACR */
48179 +#define MCF_SSI_ACR_AC97EN (0x00000001)
48180 +#define MCF_SSI_ACR_FV (0x00000002)
48181 +#define MCF_SSI_ACR_TIF (0x00000004)
48182 +#define MCF_SSI_ACR_RD (0x00000008)
48183 +#define MCF_SSI_ACR_WR (0x00000010)
48184 +#define MCF_SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5)
48185 +
48186 +/* Bit definitions and macros for ACADD */
48187 +#define MCF_SSI_ACADD_SSI_ACADD(x) (((x)&0x0007FFFF))
48188 +
48189 +/* Bit definitions and macros for ACDAT */
48190 +#define MCF_SSI_ACDAT_SSI_ACDAT(x) (((x)&0x0007FFFF))
48191 +
48192 +/* Bit definitions and macros for ATAG */
48193 +#define MCF_SSI_ATAG_DDI_ATAG(x) (((x)&0x0000FFFF))
48194 +
48195 +/* Bit definitions and macros for TMASK */
48196 +#define MCF_SSI_TMASK_SSI_TMASK(x) (x)
48197 +
48198 +/* Bit definitions and macros for RMASK */
48199 +#define MCF_SSI_RMASK_SSI_RMASK(x) (x)
48200 +
48201 +/********************************************************************/
48202 +
48203 +#endif /* __MCF5445X_SSI_H__ */
48204 --- /dev/null
48205 +++ b/include/asm-m68k/mcf5445x_usb.h
48206 @@ -0,0 +1,50 @@
48207 +/*
48208 + * Duck Schmid duck@freescale.com
48209 + *
48210 + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
48211 + */
48212 +
48213 +/*
48214 + * The code contained herein is licensed under the GNU General Public
48215 + * License. You may obtain a copy of the GNU General Public License
48216 + * Version 2 or later at the following locations:
48217 + *
48218 + * http://www.opensource.org/licenses/gpl-license.html
48219 + * http://www.gnu.org/copyleft/gpl.html
48220 + */
48221 +
48222 +#include <asm/mcfsim.h>
48223 +
48224 +/* ehci_arc_hc_driver.flags value */
48225 +#define FSL_PLATFORM_HC_FLAGS (HCD_USB2 | HCD_MEMORY)
48226 +
48227 +static inline int fsl_platform_verify(struct platform_device *pdev)
48228 +{
48229 + return 0;
48230 +}
48231 +
48232 +static inline void fsl_platform_usb_setup(struct usb_hcd *hcd)
48233 +{
48234 +}
48235 +
48236 +static inline void fsl_platform_set_host_mode(struct usb_hcd *hcd)
48237 +{
48238 + unsigned int temp;
48239 + struct fsl_usb2_platform_data *pdata;
48240 + struct fsl_usb_host_regs *regs;
48241 +
48242 + pdata = hcd->self.controller->platform_data;
48243 + regs = pdata->regs;
48244 +
48245 + if (pdata->xcvr_ops && pdata->xcvr_ops->set_host)
48246 + pdata->xcvr_ops->set_host();
48247 +
48248 + /* set host mode and select "big endian" */
48249 + temp = fsl_readl(&regs->usbmode);
48250 + temp |= USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
48251 + fsl_writel(temp, &regs->usbmode);
48252 +
48253 + pr_debug("%s: set usbmode to 0x%x\n\n", __FUNCTION__,
48254 + fsl_readl(&regs->usbmode));
48255 +
48256 +}
48257 --- /dev/null
48258 +++ b/include/asm-m68k/mcf5445x_xbs.h
48259 @@ -0,0 +1,81 @@
48260 +/*
48261 + * Kurt Mahan kmahan@freescale.com
48262 + *
48263 + * Copyright Freescale Semiconductor, Inc. 2007
48264 + *
48265 + * This program is free software; you can redistribute it and/or modify it
48266 + * under the terms of the GNU General Public License as published by the
48267 + * Free Software Foundation; either version 2 of the License, or (at your
48268 + * option) any later version.
48269 + */
48270 +
48271 +#ifndef __MCF5445X_XBS_H__
48272 +#define __MCF5445X_XBS_H__
48273 +
48274 +/*
48275 + * Crossbar Switch (XBS)
48276 + */
48277 +
48278 +/* Register read/write macros */
48279 +#define MCF_XBS_PRS1 MCF_REG32(0xFC004100) /* Flexbus Priority */
48280 +#define MCF_XBS_CRS1 MCF_REG32(0xFC004110) /* Flexbus Control */
48281 +#define MCF_XBS_PRS2 MCF_REG32(0xFC004200) /* SDRam Priority */
48282 +#define MCF_XBS_CRS2 MCF_REG32(0xFC004210) /* SDRam Control */
48283 +#define MCF_XBS_PRS3 MCF_REG32(0xFC004300) /* ATA Priority */
48284 +#define MCF_XBS_CRS3 MCF_REG32(0xFC004310) /* ATA Control */
48285 +#define MCF_XBS_PRS4 MCF_REG32(0xFC004400) /* SRAM Priority */
48286 +#define MCF_XBS_CRS4 MCF_REG32(0xFC004410) /* SRAM Control */
48287 +#define MCF_XBS_PRS5 MCF_REG32(0xFC004500) /* PCI Priority */
48288 +#define MCF_XBS_CRS5 MCF_REG32(0xFC004510) /* PCI Control */
48289 +#define MCF_XBS_PRS6 MCF_REG32(0xFC004600) /* Slave6 Priority */
48290 +#define MCF_XBS_CRS6 MCF_REG32(0xFC004610) /* Slave6 Control */
48291 +#define MCF_XBS_PRS7 MCF_REG32(0xFC004700) /* Other Priority */
48292 +#define MCF_XBS_CRS7 MCF_REG32(0xFC004710) /* Other Control */
48293 +
48294 +/* Priorities */
48295 +#define MCF_XBS_PRI_1 0 /* Level 1 (highest) */
48296 +#define MCF_XBS_PRI_2 1 /* Level 2 */
48297 +#define MCF_XBS_PRI_3 2 /* Level 3 */
48298 +#define MCF_XBS_PRI_4 3 /* Level 4 */
48299 +#define MCF_XBS_PRI_5 4 /* Level 5 */
48300 +#define MCF_XBS_PRI_6 5 /* Level 6 */
48301 +#define MCF_XBS_PRI_7 6 /* Level 7 (lowest) */
48302 +#define MCF_XBS_PRI_MASK 7 /* Mask (Not a valid level) */
48303 +
48304 +/* Priority Register (PRSn) Defs */
48305 +#define MCF_XBS_PRS_MACRO(m,p) ((p)<<((m)<<2))
48306 +#define MCF_XBS_PRS_M0(p) MCF_XBS_PRS_MACRO(0, p) /* Coldfire Core */
48307 +#define MCF_XBS_PRS_M1(p) MCF_XBS_PRS_MACRO(1, p) /* eDMA */
48308 +#define MCF_XBS_PRS_M2(p) MCF_XBS_PRS_MACRO(2, p) /* FEC0 */
48309 +#define MCF_XBS_PRS_M3(p) MCF_XBS_PRS_MACRO(3, p) /* FEC1 */
48310 +#define MCF_XBS_PRS_M4(p) MCF_XBS_PRS_MACRO(4, p) /* Master 4 */
48311 +#define MCF_XBS_PRS_M5(p) MCF_XBS_PRS_MACRO(5, p) /* PCI */
48312 +#define MCF_XBS_PRS_M6(p) MCF_XBS_PRS_MACRO(6, p) /* USB OTG */
48313 +#define MCF_XBS_PRS_M7(p) MCF_XBS_PRS_MACRO(7, p) /* Serial Boot */
48314 +
48315 +/* Control Register (CRSn) Defs */
48316 +#define MCF_XBS_CRS_RO 0x80000000 /* Read Only */
48317 +#define MCF_XBS_CRS_ARB 0x00000100 /* Arbitration Mode */
48318 +#define MCF_XBS_CRS_PCTL 0x00000030 /* Parking Control */
48319 +#define MCF_XBS_CRS_PARK 0x00000007 /* Park Location */
48320 +
48321 +/* MCF_XBS_CRS_ARB Defs */
48322 +#define MCF_ABS_CRS_ARB_FIXED 0x00000000 /* Fixed priority */
48323 +#define MCF_ABS_CRS_ARB_ROUND 0x00000100 /* Round Robin priority */
48324 +
48325 +/* MCF_XBS_CRS_PCTL Defs */
48326 +#define MCF_ABS_CRS_PCTL_PARK 0x00000000 /* Park on the defined PARK */
48327 +#define MCF_ABS_CRS_PCTL_LAST 0x00000010 /* Park on the last master */
48328 +#define MCF_ABS_CRS_PCTL_NONE 0x00000020 /* Don't park */
48329 +
48330 +/* MCF_XBS_CRS_PARK Defs */
48331 +#define MCF_ABS_CRS_PARK_M0 0x00000000 /* Park on Coldfire Core */
48332 +#define MCF_ABS_CRS_PARK_M1 0x00000001 /* Park on eDMA */
48333 +#define MCF_ABS_CRS_PARK_M2 0x00000002 /* Park on FEC0 */
48334 +#define MCF_ABS_CRS_PARK_M3 0x00000003 /* Park on FEC1 */
48335 +#define MCF_ABS_CRS_PARK_M4 0x00000004 /* Park on Reserved */
48336 +#define MCF_ABS_CRS_PARK_M5 0x00000005 /* Park on PCI */
48337 +#define MCF_ABS_CRS_PARK_M6 0x00000006 /* Park on USB OTG */
48338 +#define MCF_ABS_CRS_PARK_M7 0x00000007 /* Park on Serial Boot */
48339 +
48340 +#endif /* __MCF5445X_XBS_H__ */
48341 --- /dev/null
48342 +++ b/include/asm-m68k/mcfdspi.h
48343 @@ -0,0 +1,48 @@
48344 +/*
48345 + * mcfdspi.h-DSPI controller for the ColdFire processors.
48346 + *
48347 + * Andrey Butok
48348 + * Copyright Freescale Semiconductor, Inc. 2008
48349 + *
48350 + * This file is based on mcfqspi.h
48351 + *
48352 + * This program is free software; you can redistribute it and/or modify it
48353 + * under the terms of the GNU General Public License as published by the
48354 + * Free Software Foundation; either version 2 of the License, or (at your
48355 + * option) any later version.
48356 + *
48357 + * This program is distributed in the hope that it will be useful,
48358 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
48359 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
48360 + * GNU General Public License for more details.
48361 + *
48362 + * You should have received a copy of the GNU General Public License
48363 + * along with this program; if not, write to the Free Software
48364 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
48365 + *
48366 + ***************************************************************************
48367 + * Changes:
48368 + * v0.001 25 March 2008 Andrey Butok
48369 + * Initial Release - developed on uClinux with 2.6.23 kernel.
48370 + *
48371 + */
48372 +
48373 +#ifndef MCFDSPI_H_
48374 +#define MCFDSPI_H_
48375 +
48376 +struct coldfire_dspi_chip {
48377 + u8 mode;
48378 + u8 bits_per_word;
48379 + u16 void_write_data;
48380 + /* Only used in master mode */
48381 + u8 dbr; /* Double baud rate */
48382 + u8 pbr; /* Baud rate prescaler */
48383 + u8 br; /* Baud rate scaler */
48384 + u8 pcssck; /* PCS to SCK delay prescaler */
48385 + u8 pasc; /* After SCK delay prescaler */
48386 + u8 pdt; /* Delay after transfer prescaler */
48387 + u8 cssck; /* PCS to SCK delay scaler */
48388 + u8 asc; /* After SCK delay scaler */
48389 + u8 dt; /* Delay after transfer scaler */
48390 +};
48391 +#endif /*MCFDSPI_H_*/
48392 --- /dev/null
48393 +++ b/include/asm-m68k/mcfqspi.h
48394 @@ -0,0 +1,51 @@
48395 +/****************************************************************************/
48396 +/*
48397 + * mcfqspi.h - Master QSPI controller for the ColdFire processors
48398 + *
48399 + * (C) Copyright 2005, Intec Automation,
48400 + * Mike Lavender (mike@steroidmicros)
48401 + *
48402 +
48403 + This program is free software; you can redistribute it and/or modify
48404 + it under the terms of the GNU General Public License as published by
48405 + the Free Software Foundation; either version 2 of the License, or
48406 + (at your option) any later version.
48407 +
48408 + This program is distributed in the hope that it will be useful,
48409 + but WITHOUT ANY WARRANTY; without even the implied warranty of
48410 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
48411 + GNU General Public License for more details.
48412 +
48413 + You should have received a copy of the GNU General Public License
48414 + along with this program; if not, write to the Free Software
48415 + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
48416 +/* ------------------------------------------------------------------------- */
48417 +
48418 +#ifndef MCFQSPI_H_
48419 +#define MCFQSPI_H_
48420 +
48421 +#define QSPI_CS_INIT 0x01
48422 +#define QSPI_CS_ASSERT 0x02
48423 +#define QSPI_CS_DROP 0x04
48424 +
48425 +struct coldfire_spi_master {
48426 + u16 bus_num;
48427 + u16 num_chipselect;
48428 + u8 irq_source;
48429 + u32 irq_vector;
48430 + u32 irq_mask;
48431 + u8 irq_lp;
48432 + u8 par_val;
48433 + u32 *irq_list;
48434 + void (*cs_control)(u8 cs, u8 command);
48435 +};
48436 +
48437 +
48438 +struct coldfire_spi_chip {
48439 + u8 mode;
48440 + u8 bits_per_word;
48441 + u8 del_cs_to_clk;
48442 + u8 del_after_trans;
48443 + u16 void_write_data;
48444 +};
48445 +#endif /*MCFQSPI_H_*/
48446 --- /dev/null
48447 +++ b/include/asm-m68k/mcfsim.h
48448 @@ -0,0 +1,102 @@
48449 +/*
48450 + * mcfsim.h -- ColdFire System Integration Module support.
48451 + *
48452 + * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
48453 + * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
48454 + */
48455 +
48456 +#ifndef mcfsim_h
48457 +#define mcfsim_h
48458 +
48459 +#if defined(CONFIG_COLDFIRE)
48460 +#include <asm/coldfire.h>
48461 +#endif
48462 +
48463 +#if defined(CONFIG_M5445X)
48464 +#include <asm/mcf5445x_intc.h>
48465 +#include <asm/mcf5445x_gpio.h>
48466 +#include <asm/mcf5445x_i2c.h>
48467 +#include <asm/mcf5445x_ccm.h>
48468 +#include <asm/mcf5445x_pci.h>
48469 +#include <asm/mcf5445x_pciarb.h>
48470 +#include <asm/mcf5445x_eport.h>
48471 +#include <asm/mcf5445x_fbcs.h>
48472 +#include <asm/mcf5445x_xbs.h>
48473 +#include <asm/mcf5445x_dtim.h>
48474 +#elif defined(CONFIG_M547X_8X)
48475 +#include <asm/m5485sim.h>
48476 +#include <asm/m5485gpio.h>
48477 +#endif
48478 +
48479 +/*
48480 + * Define the base address of the SIM within the MBAR address space.
48481 + */
48482 +#define MCFSIM_BASE 0x0 /* Base address of SIM */
48483 +
48484 +/*
48485 + * Bit definitions for the ICR family of registers.
48486 + */
48487 +#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
48488 +#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
48489 +#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
48490 +#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
48491 +#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
48492 +#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
48493 +#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
48494 +#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
48495 +#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
48496 +
48497 +#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
48498 +#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
48499 +#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
48500 +#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
48501 +
48502 +/*
48503 + * Bit definitions for the Interrupt Mask register (IMR).
48504 + */
48505 +#define MCFSIM_IMR_EINT1 0x0002 /* External intr # 1 */
48506 +#define MCFSIM_IMR_EINT2 0x0004 /* External intr # 2 */
48507 +#define MCFSIM_IMR_EINT3 0x0008 /* External intr # 3 */
48508 +#define MCFSIM_IMR_EINT4 0x0010 /* External intr # 4 */
48509 +#define MCFSIM_IMR_EINT5 0x0020 /* External intr # 5 */
48510 +#define MCFSIM_IMR_EINT6 0x0040 /* External intr # 6 */
48511 +#define MCFSIM_IMR_EINT7 0x0080 /* External intr # 7 */
48512 +
48513 +#define MCFSIM_IMR_SWD 0x0100 /* Software Watchdog intr */
48514 +#define MCFSIM_IMR_TIMER1 0x0200 /* TIMER 1 intr */
48515 +#define MCFSIM_IMR_TIMER2 0x0400 /* TIMER 2 intr */
48516 +#define MCFSIM_IMR_MBUS 0x0800 /* MBUS intr */
48517 +#define MCFSIM_IMR_UART1 0x1000 /* UART 1 intr */
48518 +#define MCFSIM_IMR_UART2 0x2000 /* UART 2 intr */
48519 +
48520 +/*
48521 + * Mask for all of the SIM devices. Some parts have more or less
48522 + * SIM devices. This is a catchall for the sandard set.
48523 + */
48524 +#ifndef MCFSIM_IMR_MASKALL
48525 +#define MCFSIM_IMR_MASKALL 0x3ffe /* All intr sources */
48526 +#endif
48527 +
48528 +
48529 +/*
48530 + * PIT interrupt settings, if not found in mXXXXsim.h file.
48531 + */
48532 +#ifndef ICR_INTRCONF
48533 +#define ICR_INTRCONF 0x2b /* PIT1 level 5, priority 3 */
48534 +#endif
48535 +#ifndef MCFPIT_IMR
48536 +#define MCFPIT_IMR MCFINTC_IMRH
48537 +#endif
48538 +#ifndef MCFPIT_IMR_IBIT
48539 +#define MCFPIT_IMR_IBIT (1 << (MCFINT_PIT1 - 32))
48540 +#endif
48541 +
48542 +
48543 +#ifndef __ASSEMBLY__
48544 +/*
48545 + * Definition for the interrupt auto-vectoring support.
48546 + */
48547 +extern void mcf_autovector(unsigned int vec);
48548 +#endif /* __ASSEMBLY__ */
48549 +
48550 +#endif /* mcfsim_h */
48551 --- /dev/null
48552 +++ b/include/asm-m68k/mcfuart.h
48553 @@ -0,0 +1,194 @@
48554 +/*
48555 + * mcfuart.h -- ColdFire internal UART support defines.
48556 + *
48557 + * Matt Waddel Matt.Waddel@freescale.com
48558 + * Copyright Freescale Semiconductor, Inc. 2007
48559 + *
48560 + * Derived from m68knommu version of this same file (Greg Ungerer & Lineo).
48561 + *
48562 + */
48563 +
48564 +#ifndef mcfuart_h
48565 +#define mcfuart_h
48566 +
48567 +/*
48568 + * Define the base address of the UARTS within the MBAR address
48569 + * space.
48570 + */
48571 +#if defined(CONFIG_M5445X)
48572 +#include <asm/mcf5445x_intc.h>
48573 +#define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */
48574 +#define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */
48575 +#define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */
48576 +#define MCFINT_VECBASE 64
48577 +#define MCFINT_UART0 26
48578 +
48579 +#elif defined(CONFIG_M547X_8X)
48580 +
48581 +#define MCFUART_BASE1 0x8600 /* Base address of UART1 */
48582 +#define MCFUART_BASE2 0x8700 /* Base address of UART2 */
48583 +#define MCFUART_BASE3 0x8800 /* Base address of UART3 */
48584 +#define MCFUART_BASE4 0x8900 /* Base address of UART4 */
48585 +#define MCFINT_VECBASE 64
48586 +#define MCFINT_UART0 35
48587 +#endif
48588 +
48589 +
48590 +/*
48591 + * Define the ColdFire UART register set addresses.
48592 + */
48593 +#define MCFUART_UMR 0x00 /* Mode register (r/w) */
48594 +#define MCFUART_USR 0x04 /* Status register (r) */
48595 +#define MCFUART_UCSR 0x04 /* Clock Select (w) */
48596 +#define MCFUART_UCR 0x08 /* Command register (w) */
48597 +#define MCFUART_URB 0x0c /* Receiver Buffer (r) */
48598 +#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */
48599 +#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */
48600 +#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */
48601 +#define MCFUART_UISR 0x14 /* Interrup Status (r) */
48602 +#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */
48603 +#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */
48604 +#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */
48605 +#ifdef CONFIG_M5272
48606 +#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */
48607 +#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */
48608 +#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
48609 +#else
48610 +#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */
48611 +#endif
48612 +#define MCFUART_UIPR 0x34 /* Input Port (r) */
48613 +#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */
48614 +#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */
48615 +
48616 +
48617 +/*
48618 + * Define bit flags in Mode Register 1 (MR1).
48619 + */
48620 +#define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */
48621 +#define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */
48622 +#define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */
48623 +#define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */
48624 +#define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */
48625 +
48626 +#define MCFUART_MR1_PARITYNONE 0x10 /* No parity */
48627 +#define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */
48628 +#define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */
48629 +#define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */
48630 +#define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */
48631 +
48632 +#define MCFUART_MR1_CS5 0x00 /* 5 bits per char */
48633 +#define MCFUART_MR1_CS6 0x01 /* 6 bits per char */
48634 +#define MCFUART_MR1_CS7 0x02 /* 7 bits per char */
48635 +#define MCFUART_MR1_CS8 0x03 /* 8 bits per char */
48636 +
48637 +/*
48638 + * Define bit flags in Mode Register 2 (MR2).
48639 + */
48640 +#define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */
48641 +#define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */
48642 +#define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */
48643 +#define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */
48644 +#define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */
48645 +
48646 +#define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */
48647 +#define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */
48648 +#define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */
48649 +
48650 +/*
48651 + * Define bit flags in Status Register (USR).
48652 + */
48653 +#define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */
48654 +#define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */
48655 +#define MCFUART_USR_RXPARITY 0x20 /* Received parity error */
48656 +#define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */
48657 +#define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */
48658 +#define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */
48659 +#define MCFUART_USR_RXFULL 0x02 /* Receiver full */
48660 +#define MCFUART_USR_RXREADY 0x01 /* Receiver ready */
48661 +
48662 +#if defined(CONFIG_M547X_8X)
48663 +#define MCFUART_USR_TXREADY_BN 0x0a
48664 +#define MCFUART_USR_TXEMPTY_BN 0x0b
48665 +#endif
48666 +
48667 +#define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
48668 + MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)
48669 +
48670 +/*
48671 + * Define bit flags in Clock Select Register (UCSR).
48672 + */
48673 +#define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */
48674 +#define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */
48675 +#define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */
48676 +
48677 +#define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */
48678 +#define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */
48679 +#define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */
48680 +
48681 +/*
48682 + * Define bit flags in Command Register (UCR).
48683 + */
48684 +#define MCFUART_UCR_CMDNULL 0x00 /* No command */
48685 +#define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */
48686 +#define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */
48687 +#define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */
48688 +#define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */
48689 +#define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */
48690 +#define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */
48691 +#define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */
48692 +
48693 +#define MCFUART_UCR_TXNULL 0x00 /* No TX command */
48694 +#define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */
48695 +#define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */
48696 +#define MCFUART_UCR_RXNULL 0x00 /* No RX command */
48697 +#define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */
48698 +#define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */
48699 +
48700 +/*
48701 + * Define bit flags in Input Port Change Register (UIPCR).
48702 + */
48703 +#define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */
48704 +#define MCFUART_UIPCR_CTS 0x01 /* CTS value */
48705 +
48706 +/*
48707 + * Define bit flags in Input Port Register (UIP).
48708 + */
48709 +#define MCFUART_UIPR_CTS 0x01 /* CTS value */
48710 +
48711 +/*
48712 + * Define bit flags in Output Port Registers (UOP).
48713 + * Clear bit by writing to UOP0, set by writing to UOP1.
48714 + */
48715 +#define MCFUART_UOP_RTS 0x01 /* RTS set or clear */
48716 +
48717 +/*
48718 + * Define bit flags in the Auxiliary Control Register (UACR).
48719 + */
48720 +#define MCFUART_UACR_IEC 0x01 /* Input enable control */
48721 +
48722 +/*
48723 + * Define bit flags in Interrupt Status Register (UISR).
48724 + * These same bits are used for the Interrupt Mask Register (UIMR).
48725 + */
48726 +#define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */
48727 +#define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */
48728 +#define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */
48729 +#define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */
48730 +
48731 +#ifdef CONFIG_M5272
48732 +/*
48733 + * Define bit flags in the Transmitter FIFO Register (UTF).
48734 + */
48735 +#define MCFUART_UTF_TXB 0x1f /* Transmitter data level */
48736 +#define MCFUART_UTF_FULL 0x20 /* Transmitter fifo full */
48737 +#define MCFUART_UTF_TXS 0xc0 /* Transmitter status */
48738 +
48739 +/*
48740 + * Define bit flags in the Receiver FIFO Register (URF).
48741 + */
48742 +#define MCFUART_URF_RXB 0x1f /* Receiver data level */
48743 +#define MCFUART_URF_FULL 0x20 /* Receiver fifo full */
48744 +#define MCFUART_URF_RXS 0xc0 /* Receiver status */
48745 +#endif
48746 +
48747 +#endif /* mcfuart_h */
48748 --- a/include/asm-m68k/mmu_context.h
48749 +++ b/include/asm-m68k/mmu_context.h
48750 @@ -7,7 +7,7 @@ static inline void enter_lazy_tlb(struct
48751 {
48752 }
48753
48754 -#ifndef CONFIG_SUN3
48755 +#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
48756
48757 #include <asm/setup.h>
48758 #include <asm/page.h>
48759 @@ -102,7 +102,7 @@ static inline void activate_mm(struct mm
48760 switch_mm_0460(next_mm);
48761 }
48762
48763 -#else /* CONFIG_SUN3 */
48764 +#elif defined(CONFIG_SUN3)
48765 #include <asm/sun3mmu.h>
48766 #include <linux/sched.h>
48767
48768 @@ -150,5 +150,155 @@ static inline void activate_mm(struct mm
48769 activate_context(next_mm);
48770 }
48771
48772 -#endif
48773 +#else /* CONFIG_COLDFIRE */
48774 +
48775 +#include <asm/coldfire.h>
48776 +#include <asm/atomic.h>
48777 +#include <asm/bitops.h>
48778 +#include <asm/mmu.h>
48779 +
48780 +#define NO_CONTEXT 256
48781 +#define LAST_CONTEXT 255
48782 +#define FIRST_CONTEXT 1
48783 +
48784 +extern void set_context(mm_context_t context, pgd_t *pgd);
48785 +extern unsigned long context_map[];
48786 +extern mm_context_t next_mmu_context;
48787 +
48788 +extern atomic_t nr_free_contexts;
48789 +extern struct mm_struct *context_mm[LAST_CONTEXT+1];
48790 +extern void steal_context(void);
48791 +
48792 +static inline void get_mmu_context(struct mm_struct *mm)
48793 +{
48794 + mm_context_t ctx;
48795 +
48796 + if (mm->context != NO_CONTEXT)
48797 + return;
48798 + while (atomic_dec_and_test_lt(&nr_free_contexts)) {
48799 + atomic_inc(&nr_free_contexts);
48800 + steal_context();
48801 + }
48802 + ctx = next_mmu_context;
48803 + while (test_and_set_bit(ctx, context_map)) {
48804 + ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx);
48805 + if (ctx > LAST_CONTEXT)
48806 + ctx = 0;
48807 + }
48808 + next_mmu_context = (ctx + 1) & LAST_CONTEXT;
48809 + mm->context = ctx;
48810 + context_mm[ctx] = mm;
48811 +}
48812 +
48813 +/*
48814 + * Set up the context for a new address space.
48815 + */
48816 +#define init_new_context(tsk, mm) (((mm)->context = NO_CONTEXT), 0)
48817 +
48818 +/*
48819 + * We're finished using the context for an address space.
48820 + */
48821 +static inline void destroy_context(struct mm_struct *mm)
48822 +{
48823 + if (mm->context != NO_CONTEXT) {
48824 + clear_bit(mm->context, context_map);
48825 + mm->context = NO_CONTEXT;
48826 + atomic_inc(&nr_free_contexts);
48827 + }
48828 +}
48829 +
48830 +static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
48831 + struct task_struct *tsk)
48832 +{
48833 + get_mmu_context(tsk->mm);
48834 + set_context(tsk->mm->context, next->pgd);
48835 +}
48836 +
48837 +/*
48838 + * After we have set current->mm to a new value, this activates
48839 + * the context for the new mm so we see the new mappings.
48840 + */
48841 +static inline void activate_mm(struct mm_struct *active_mm,
48842 + struct mm_struct *mm)
48843 +{
48844 + get_mmu_context(mm);
48845 + set_context(mm->context, mm->pgd);
48846 +}
48847 +
48848 +#define deactivate_mm(tsk, mm) do { } while (0)
48849 +
48850 +extern void mmu_context_init(void);
48851 +#if defined(CONFIG_M547X_8X)
48852 +#define prepare_arch_switch(next) load_ksp_mmu(next)
48853 +
48854 +static inline void load_ksp_mmu(struct task_struct *task)
48855 +{
48856 + int flags;
48857 + struct mm_struct *mm;
48858 + int asid;
48859 + pgd_t *pgd;
48860 + pmd_t *pmd;
48861 + pte_t *pte;
48862 + unsigned long mmuar;
48863 +
48864 + local_irq_save(flags);
48865 + mmuar = task->thread.ksp;
48866 +
48867 + /* Search for a valid TLB entry, if one is found, don't remap */
48868 + *MMUAR = mmuar;
48869 + *MMUOR = MMUOR_STLB | MMUOR_ADR;
48870 + if ((*MMUSR) & MMUSR_HIT)
48871 + goto end;
48872 +
48873 + if (mmuar >= PAGE_OFFSET) {
48874 + mm = &init_mm;
48875 + } else {
48876 + printk ("load_ksp_mmu: non-kernel mm found: 0x%08x\n", (unsigned int) task->mm);
48877 + mm = task->mm;
48878 + }
48879 +
48880 + if (!mm)
48881 + goto bug;
48882 +
48883 + pgd = pgd_offset(mm, mmuar);
48884 + if (pgd_none(*pgd))
48885 + goto bug;
48886 +
48887 + pmd = pmd_offset(pgd, mmuar);
48888 + if (pmd_none(*pmd))
48889 + goto bug;
48890 +
48891 + pte = (mmuar >= PAGE_OFFSET) ? pte_offset_kernel(pmd, mmuar)
48892 + : pte_offset_map(pmd, mmuar);
48893 + if (pte_none(*pte) || !pte_present(*pte))
48894 + goto bug;
48895 +
48896 + set_pte(pte, pte_mkyoung(*pte));
48897 + asid = mm->context & 0xff;
48898 + if (!pte_dirty(*pte) && mmuar<=PAGE_OFFSET)
48899 + set_pte(pte, pte_wrprotect(*pte));
48900 +
48901 + *MMUTR = (mmuar & PAGE_MASK) | (asid << CF_ASID_MMU_SHIFT)
48902 + | (((int)(pte->pte) & (int)CF_PAGE_MMUTR_MASK ) >> CF_PAGE_MMUTR_SHIFT)
48903 + | MMUTR_V;
48904 +
48905 + *MMUDR = (pte_val(*pte) & PAGE_MASK)
48906 + | ((pte->pte) & CF_PAGE_MMUDR_MASK)
48907 + | MMUDR_SZ8K | MMUDR_X;
48908 +
48909 + *MMUOR = MMUOR_ACC | MMUOR_UAA;
48910 + asm ("nop");
48911 +
48912 + goto end;
48913 +
48914 +bug:
48915 + printk ("ksp load failed: mm=0x%08x ksp=0x%08x\n", (unsigned int) mm, (unsigned int) mmuar);
48916 +
48917 +end:
48918 + local_irq_restore(flags);
48919 +}
48920 +
48921 +#endif /* CONFIG_M547X_8X */
48922 +
48923 +#endif /* CONFIG_COLDFIRE */
48924 #endif
48925 --- a/include/asm-m68k/page.h
48926 +++ b/include/asm-m68k/page.h
48927 @@ -4,7 +4,7 @@
48928 #include <linux/const.h>
48929
48930 /* PAGE_SHIFT determines the page size */
48931 -#ifndef CONFIG_SUN3
48932 +#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
48933 #define PAGE_SHIFT (12)
48934 #else
48935 #define PAGE_SHIFT (13)
48936 @@ -116,10 +116,31 @@ typedef struct page *pgtable_t;
48937
48938 extern unsigned long m68k_memoffset;
48939
48940 -#ifndef CONFIG_SUN3
48941 +#if !defined(CONFIG_SUN3)
48942
48943 #define WANT_PAGE_VIRTUAL
48944
48945 +#if defined(CONFIG_COLDFIRE)
48946 +static inline unsigned long ___pa(void *vaddr)
48947 +{
48948 +#if CONFIG_SDRAM_BASE != PAGE_OFFSET
48949 + return (((unsigned long)vaddr & 0x0fffffff) + CONFIG_SDRAM_BASE);
48950 +#else
48951 + return (unsigned long)vaddr;
48952 +#endif
48953 +}
48954 +#define __pa(vaddr) ___pa((void *)(vaddr))
48955 +
48956 +static inline void *__va(unsigned long paddr)
48957 +{
48958 +#if CONFIG_SDRAM_BASE != PAGE_OFFSET
48959 + return (void *)((paddr & 0x0fffffff) + PAGE_OFFSET);
48960 +#else
48961 + return (void *)paddr;
48962 +#endif
48963 +}
48964 +
48965 +#else
48966 static inline unsigned long ___pa(void *vaddr)
48967 {
48968 unsigned long paddr;
48969 @@ -141,6 +162,7 @@ static inline void *__va(unsigned long p
48970 : "0" (paddr), "i" (m68k_fixup_memoffset));
48971 return vaddr;
48972 }
48973 +#endif
48974
48975 #else /* !CONFIG_SUN3 */
48976 /* This #define is a horrible hack to suppress lots of warnings. --m */
48977 @@ -172,6 +194,8 @@ static inline void *__va(unsigned long x
48978 * memory node, but we have no highmem, so that works for now.
48979 * TODO: implement (fast) pfn<->pgdat_idx conversion functions, this makes lots
48980 * of the shifts unnecessary.
48981 + *
48982 + * PFNs are used to map physical pages. So PFN[0] maps to the base phys addr.
48983 */
48984 #define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT)
48985 #define pfn_to_virt(pfn) __va((pfn) << PAGE_SHIFT)
48986 @@ -228,4 +252,9 @@ static inline __attribute_const__ int __
48987
48988 #include <asm-generic/page.h>
48989
48990 +#ifdef CONFIG_VSYSCALL
48991 +/* vDSO support */
48992 +#define __HAVE_ARCH_GATE_AREA
48993 +#endif
48994 +
48995 #endif /* _M68K_PAGE_H */
48996 --- a/include/asm-m68k/page_offset.h
48997 +++ b/include/asm-m68k/page_offset.h
48998 @@ -1,8 +1,15 @@
48999 +/*
49000 + * Page and physical memory maps.
49001 + */
49002 +#if defined(CONFIG_SUN3)
49003 +#define PAGE_OFFSET_RAW 0x0E000000
49004 +
49005 +#elif defined(CONFIG_M5445X) || defined(CONFIG_M547X_8X)
49006 +#define PHYS_OFFSET CONFIG_SDRAM_BASE
49007 +#define PAGE_OFFSET_RAW (PHYS_OFFSET)
49008 +/* #define PAGE_OFFSET_RAW 0xC0000000 */
49009
49010 -/* This handles the memory map.. */
49011 -#ifndef CONFIG_SUN3
49012 -#define PAGE_OFFSET_RAW 0x00000000
49013 #else
49014 -#define PAGE_OFFSET_RAW 0x0E000000
49015 +/* default */
49016 +#define PAGE_OFFSET_RAW 0x00000000
49017 #endif
49018 -
49019 --- a/include/asm-m68k/pci.h
49020 +++ b/include/asm-m68k/pci.h
49021 @@ -1,57 +1,10 @@
49022 -#ifndef _ASM_M68K_PCI_H
49023 -#define _ASM_M68K_PCI_H
49024 +#ifndef M68K_PCI_H
49025 +#define M68K_PCI_H
49026
49027 -/*
49028 - * asm-m68k/pci_m68k.h - m68k specific PCI declarations.
49029 - *
49030 - * Written by Wout Klaren.
49031 - */
49032 +#ifdef CONFIG_M5445X
49033 +#include "5445x_pci.h"
49034 +#else
49035 +#include "548x_pci.h"
49036 +#endif
49037
49038 -#include <asm/scatterlist.h>
49039 -
49040 -struct pci_ops;
49041 -
49042 -/*
49043 - * Structure with hardware dependent information and functions of the
49044 - * PCI bus.
49045 - */
49046 -
49047 -struct pci_bus_info
49048 -{
49049 - /*
49050 - * Resources of the PCI bus.
49051 - */
49052 -
49053 - struct resource mem_space;
49054 - struct resource io_space;
49055 -
49056 - /*
49057 - * System dependent functions.
49058 - */
49059 -
49060 - struct pci_ops *m68k_pci_ops;
49061 -
49062 - void (*fixup)(int pci_modify);
49063 - void (*conf_device)(struct pci_dev *dev);
49064 -};
49065 -
49066 -#define pcibios_assign_all_busses() 0
49067 -#define pcibios_scan_all_fns(a, b) 0
49068 -
49069 -static inline void pcibios_set_master(struct pci_dev *dev)
49070 -{
49071 - /* No special bus mastering setup handling */
49072 -}
49073 -
49074 -static inline void pcibios_penalize_isa_irq(int irq, int active)
49075 -{
49076 - /* We don't do dynamic PCI IRQ allocation */
49077 -}
49078 -
49079 -/* The PCI address space does equal the physical memory
49080 - * address space. The networking and block device layers use
49081 - * this boolean for bounce buffer decisions.
49082 - */
49083 -#define PCI_DMA_BUS_IS_PHYS (1)
49084 -
49085 -#endif /* _ASM_M68K_PCI_H */
49086 +#endif /* M68K_PCI_H */
49087 --- a/include/asm-m68k/pgalloc.h
49088 +++ b/include/asm-m68k/pgalloc.h
49089 @@ -8,8 +8,10 @@
49090 #include <asm/virtconvert.h>
49091
49092
49093 -#ifdef CONFIG_SUN3
49094 +#if defined(CONFIG_SUN3)
49095 #include <asm/sun3_pgalloc.h>
49096 +#elif defined(CONFIG_COLDFIRE)
49097 +#include <asm/cf_pgalloc.h>
49098 #else
49099 #include <asm/motorola_pgalloc.h>
49100 #endif
49101 --- a/include/asm-m68k/pgtable.h
49102 +++ b/include/asm-m68k/pgtable.h
49103 @@ -40,6 +40,8 @@
49104 /* PGDIR_SHIFT determines what a third-level page table entry can map */
49105 #ifdef CONFIG_SUN3
49106 #define PGDIR_SHIFT 17
49107 +#elif defined(CONFIG_COLDFIRE)
49108 +#define PGDIR_SHIFT 22
49109 #else
49110 #define PGDIR_SHIFT 25
49111 #endif
49112 @@ -54,6 +56,10 @@
49113 #define PTRS_PER_PTE 16
49114 #define PTRS_PER_PMD 1
49115 #define PTRS_PER_PGD 2048
49116 +#elif defined(CONFIG_COLDFIRE)
49117 +#define PTRS_PER_PTE 512
49118 +#define PTRS_PER_PMD 1
49119 +#define PTRS_PER_PGD 1024
49120 #else
49121 #define PTRS_PER_PTE 1024
49122 #define PTRS_PER_PMD 8
49123 @@ -66,6 +72,11 @@
49124 #ifdef CONFIG_SUN3
49125 #define KMAP_START 0x0DC00000
49126 #define KMAP_END 0x0E000000
49127 +#elif defined(CONFIG_COLDFIRE)
49128 +#define VMALLOC_START 0xc0000000
49129 +#define VMALLOC_END 0xcfffffff
49130 +#define KMAP_START (VMALLOC_END + 1)
49131 +#define KMAP_END 0xe0000000
49132 #else
49133 #define KMAP_START 0xd0000000
49134 #define KMAP_END 0xf0000000
49135 @@ -79,9 +90,11 @@
49136 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
49137 * area for the same reason. ;)
49138 */
49139 +#if !defined(CONFIG_COLDFIRE)
49140 #define VMALLOC_OFFSET (8*1024*1024)
49141 #define VMALLOC_START (((unsigned long) high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
49142 #define VMALLOC_END KMAP_START
49143 +#endif
49144 #else
49145 extern unsigned long vmalloc_end;
49146 #define VMALLOC_START 0x0f800000
49147 @@ -130,6 +143,8 @@ static inline void update_mmu_cache(stru
49148
49149 #ifdef CONFIG_SUN3
49150 #include <asm/sun3_pgtable.h>
49151 +#elif defined(CONFIG_COLDFIRE)
49152 +#include <asm/cf_pgtable.h>
49153 #else
49154 #include <asm/motorola_pgtable.h>
49155 #endif
49156 @@ -140,6 +155,9 @@ static inline void update_mmu_cache(stru
49157 /*
49158 * Macro to mark a page protection value as "uncacheable".
49159 */
49160 +#ifdef CONFIG_COLDFIRE
49161 +# define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | CF_PAGE_NOCACHE))
49162 +#else /* CONFIG_COLDFIRE */
49163 #ifdef SUN3_PAGE_NOCACHE
49164 # define __SUN3_PAGE_NOCACHE SUN3_PAGE_NOCACHE
49165 #else
49166 @@ -154,6 +172,7 @@ static inline void update_mmu_cache(stru
49167 ? (__pgprot((pgprot_val(prot) & _CACHEMASK040) | _PAGE_NOCACHE_S)) \
49168 : (prot)))
49169
49170 +#endif /* CONFIG_COLDFIRE */
49171 #endif /* !__ASSEMBLY__ */
49172
49173 /*
49174 --- a/include/asm-m68k/processor.h
49175 +++ b/include/asm-m68k/processor.h
49176 @@ -22,24 +22,38 @@ static inline unsigned long rdusp(void)
49177 {
49178 unsigned long usp;
49179
49180 +#ifndef CONFIG_COLDFIRE
49181 __asm__ __volatile__("move %/usp,%0" : "=a" (usp));
49182 +#else
49183 + __asm__ __volatile__("movel %/usp,%0" : "=a" (usp));
49184 +#endif
49185 return usp;
49186 }
49187
49188 static inline void wrusp(unsigned long usp)
49189 {
49190 +#ifndef CONFIG_COLDFIRE
49191 __asm__ __volatile__("move %0,%/usp" : : "a" (usp));
49192 +#else
49193 + __asm__ __volatile__("movel %0,%/usp" : : "a" (usp));
49194 +#endif
49195 }
49196
49197 /*
49198 * User space process size: 3.75GB. This is hardcoded into a few places,
49199 * so don't change it unless you know what you are doing.
49200 */
49201 -#ifndef CONFIG_SUN3
49202 +#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
49203 #define TASK_SIZE (0xF0000000UL)
49204 +#elif defined(CONFIG_COLDFIRE)
49205 +#define TASK_SIZE (0xC0000000UL)
49206 +#else /* CONFIG_SUN3 */
49207 +#ifdef __ASSEMBLY__
49208 +#define TASK_SIZE (0x0E000000)
49209 #else
49210 #define TASK_SIZE (0x0E000000UL)
49211 #endif
49212 +#endif
49213
49214 #ifdef __KERNEL__
49215 #define STACK_TOP TASK_SIZE
49216 @@ -49,9 +63,11 @@ static inline void wrusp(unsigned long u
49217 /* This decides where the kernel will search for a free chunk of vm
49218 * space during mmap's.
49219 */
49220 -#ifndef CONFIG_SUN3
49221 -#define TASK_UNMAPPED_BASE 0xC0000000UL
49222 -#else
49223 +#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
49224 +#define TASK_UNMAPPED_BASE 0xC0000000UL
49225 +#elif defined(CONFIG_COLDFIRE)
49226 +#define TASK_UNMAPPED_BASE 0x80000000UL
49227 +#else /* CONFIG_SUN3 */
49228 #define TASK_UNMAPPED_BASE 0x0A000000UL
49229 #endif
49230 #define TASK_UNMAPPED_ALIGN(addr, off) PAGE_ALIGN(addr)
49231 @@ -60,7 +76,11 @@ struct thread_struct {
49232 unsigned long ksp; /* kernel stack pointer */
49233 unsigned long usp; /* user stack pointer */
49234 unsigned short sr; /* saved status register */
49235 +#ifndef CONFIG_COLDFIRE
49236 unsigned short fs; /* saved fs (sfc, dfc) */
49237 +#else
49238 + mm_segment_t fs;
49239 +#endif
49240 unsigned long crp[2]; /* cpu root pointer */
49241 unsigned long esp0; /* points to SR of stack frame */
49242 unsigned long faddr; /* info about last fault */
49243 @@ -81,6 +101,7 @@ struct thread_struct {
49244 /*
49245 * Do necessary setup to start up a newly executed thread.
49246 */
49247 +#ifndef CONFIG_COLDFIRE
49248 static inline void start_thread(struct pt_regs * regs, unsigned long pc,
49249 unsigned long usp)
49250 {
49251 @@ -91,6 +112,23 @@ static inline void start_thread(struct p
49252 regs->sr &= ~0x2000;
49253 wrusp(usp);
49254 }
49255 +#else
49256 +/*
49257 + * Do necessary setup to start up a newly executed thread.
49258 + *
49259 + * pass the data segment into user programs if it exists,
49260 + * it can't hurt anything as far as I can tell
49261 + */
49262 +#define start_thread(_regs, _pc, _usp) \
49263 +do { \
49264 + set_fs(USER_DS); /* reads from user space */ \
49265 + (_regs)->pc = (_pc); \
49266 + if (current->mm) \
49267 + (_regs)->d5 = current->mm->start_data; \
49268 + (_regs)->sr &= ~0x2000; \
49269 + wrusp(_usp); \
49270 +} while (0)
49271 +#endif
49272
49273 /* Forward declaration, a strange C thing */
49274 struct task_struct;
49275 --- a/include/asm-m68k/ptrace.h
49276 +++ b/include/asm-m68k/ptrace.h
49277 @@ -38,10 +38,21 @@ struct pt_regs {
49278 long d0;
49279 long orig_d0;
49280 long stkadj;
49281 +#ifndef CONFIG_COLDFIRE
49282 unsigned short sr;
49283 unsigned long pc;
49284 unsigned format : 4; /* frame format specifier */
49285 unsigned vector : 12; /* vector offset */
49286 +#else
49287 + unsigned long mmuar;
49288 + unsigned long mmusr;
49289 + unsigned format : 4; /* frame format specifier */
49290 + unsigned fs2 : 2;
49291 + unsigned vector: 8;
49292 + unsigned fs1 : 2;
49293 + unsigned short sr;
49294 + unsigned long pc;
49295 +#endif
49296 };
49297
49298 /*
49299 --- a/include/asm-m68k/raw_io.h
49300 +++ b/include/asm-m68k/raw_io.h
49301 @@ -46,6 +46,29 @@ extern void __iounmap(void *addr, unsign
49302 #define out_le16(addr,w) (void)((*(__force volatile __le16 *) (addr)) = cpu_to_le16(w))
49303 #define out_le32(addr,l) (void)((*(__force volatile __le32 *) (addr)) = cpu_to_le32(l))
49304
49305 +#if (defined CONFIG_COLDFIRE) && (defined CONFIG_PCI)
49306 +unsigned char pci_inb(long addr);
49307 +unsigned short pci_inw(long addr);
49308 +unsigned long pci_inl(long addr);
49309 +void pci_outb(unsigned char val, long addr);
49310 +void pci_outw(unsigned short val, long addr);
49311 +void pci_outl(unsigned long val, long addr);
49312 +unsigned short pci_raw_inw(long addr);
49313 +unsigned long pci_raw_inl(long addr);
49314 +void pci_raw_outw(unsigned short val, long addr);
49315 +void pci_raw_outl(unsigned long val, long addr);
49316 +#define raw_inb(port) pci_inb((long)((volatile unsigned char *)(port)))
49317 +#define raw_inw(port) pci_raw_inw((long)((volatile unsigned short *)(port)))
49318 +#define raw_inl(port) pci_raw_inl((long)((volatile unsigned long *)(port)))
49319 +
49320 +#define raw_outb(val,port) pci_outb((val),(long)((volatile unsigned char *)(port)))
49321 +#define raw_outw(val,port) pci_raw_outw((val),(long)((volatile unsigned short *)(port)))
49322 +#define raw_outl(val,port) pci_raw_outl((val),(long)((volatile unsigned long *)(port)))
49323 +
49324 +#define swap_inw(port) pci_inw((long)((volatile unsigned short *)(port)))
49325 +#define swap_outw(val,port) pci_outw((val),(long)((volatile unsigned short *)(port)))
49326 +
49327 +#else
49328 #define raw_inb in_8
49329 #define raw_inw in_be16
49330 #define raw_inl in_be32
49331 @@ -60,6 +83,9 @@ extern void __iounmap(void *addr, unsign
49332 #define __raw_writew(val,addr) out_be16((addr),(val))
49333 #define __raw_writel(val,addr) out_be32((addr),(val))
49334
49335 +#define swap_inw(port) in_le16((port))
49336 +#define swap_outw(val,port) out_le16((port),(val))
49337 +#endif
49338 static inline void raw_insb(volatile u8 __iomem *port, u8 *buf, unsigned int len)
49339 {
49340 unsigned int i;
49341 @@ -77,6 +103,7 @@ static inline void raw_outsb(volatile u8
49342 out_8(port, *buf++);
49343 }
49344
49345 +#ifndef CONFIG_COLDFIRE
49346 static inline void raw_insw(volatile u16 __iomem *port, u16 *buf, unsigned int nr)
49347 {
49348 unsigned int tmp;
49349 @@ -342,6 +369,63 @@ static inline void raw_outsw_swapw(volat
49350 : "d0", "a0", "a1", "d6");
49351 }
49352
49353 +
49354 +#else /*CONFIG_COLDFIRE */
49355 +
49356 +static inline void raw_insw(volatile u16 *port, u16 *buf, unsigned int nr)
49357 +{
49358 + unsigned int i;
49359 +
49360 + for (i = 0; i < nr; i++)
49361 + *buf++ = raw_inw(port);
49362 +}
49363 +
49364 +static inline void raw_outsw(volatile u16 *port, const u16 *buf,
49365 + unsigned int nr)
49366 +{
49367 + unsigned int i;
49368 +
49369 + for (i = 0; i < nr; i++, buf++)
49370 + raw_outw(*buf, port);
49371 +}
49372 +
49373 +static inline void raw_insl(volatile u32 *port, u32 *buf, unsigned int nr)
49374 +{
49375 + unsigned int i;
49376 +
49377 + for (i = 0; i < nr; i++)
49378 + *buf++ = raw_inl(port);
49379 +}
49380 +
49381 +static inline void raw_outsl(volatile u32 *port, const u32 *buf,
49382 + unsigned int nr)
49383 +{
49384 + unsigned int i;
49385 +
49386 + for (i = 0; i < nr; i++, buf++)
49387 + raw_outl(*buf, port);
49388 +}
49389 +
49390 +static inline void raw_insw_swapw(volatile u16 *port, u16 *buf,
49391 + unsigned int nr)
49392 +{
49393 + unsigned int i;
49394 +
49395 + for (i = 0; i < nr; i++)
49396 + *buf++ = in_le16(port);
49397 +
49398 +}
49399 +
49400 +static inline void raw_outsw_swapw(volatile u16 __iomem *port, const u16 *buf,
49401 + unsigned int nr)
49402 +{
49403 + unsigned int i;
49404 +
49405 + for (i = 0; i < nr; i++, buf++)
49406 + out_le16(port, *buf);
49407 +}
49408 +#endif /*CONFIG_COLDFIRE */
49409 +
49410 #endif /* __KERNEL__ */
49411
49412 #endif /* _RAW_IO_H */
49413 --- a/include/asm-m68k/segment.h
49414 +++ b/include/asm-m68k/segment.h
49415 @@ -29,6 +29,7 @@ typedef struct {
49416 * Get/set the SFC/DFC registers for MOVES instructions
49417 */
49418
49419 +#ifndef CONFIG_COLDFIRE
49420 static inline mm_segment_t get_fs(void)
49421 {
49422 mm_segment_t _v;
49423 @@ -50,6 +51,15 @@ static inline void set_fs(mm_segment_t v
49424 : /* no outputs */ : "r" (val.seg) : "memory");
49425 }
49426
49427 +#else /* CONFIG_COLDFIRE */
49428 +
49429 +#include <asm/current.h>
49430 +#define get_fs() (current->thread.fs)
49431 +#define set_fs(val) (current->thread.fs = (val))
49432 +#define get_ds() (KERNEL_DS)
49433 +
49434 +#endif /* CONFIG_COLDFIRE */
49435 +
49436 #define segment_eq(a,b) ((a).seg == (b).seg)
49437
49438 #endif /* __ASSEMBLY__ */
49439 --- a/include/asm-m68k/setup.h
49440 +++ b/include/asm-m68k/setup.h
49441 @@ -40,6 +40,7 @@
49442 #define MACH_HP300 9
49443 #define MACH_Q40 10
49444 #define MACH_SUN3X 11
49445 +#define MACH_CFMMU 12
49446
49447 #define COMMAND_LINE_SIZE 256
49448
49449 @@ -189,6 +190,14 @@ extern unsigned long m68k_machtype;
49450 # define MACH_TYPE (MACH_SUN3X)
49451 #endif
49452
49453 +#if !defined(CONFIG_COLDFIRE)
49454 +# define MACH_IS_COLDFIRE (0)
49455 +#else
49456 +# define CONFIG_COLDFIRE_ONLY
49457 +# define MACH_IS_COLDFIRE (1)
49458 +# define MACH_TYPE (MACH_CFMMU)
49459 +#endif
49460 +
49461 #ifndef MACH_TYPE
49462 # define MACH_TYPE (m68k_machtype)
49463 #endif
49464 @@ -211,23 +220,31 @@ extern unsigned long m68k_machtype;
49465 #define CPUB_68030 1
49466 #define CPUB_68040 2
49467 #define CPUB_68060 3
49468 +#define CPUB_CFV4E 4
49469
49470 #define CPU_68020 (1<<CPUB_68020)
49471 #define CPU_68030 (1<<CPUB_68030)
49472 #define CPU_68040 (1<<CPUB_68040)
49473 #define CPU_68060 (1<<CPUB_68060)
49474 +#define CPU_CFV4E (1<<CPUB_CFV4E)
49475
49476 #define FPUB_68881 0
49477 #define FPUB_68882 1
49478 #define FPUB_68040 2 /* Internal FPU */
49479 #define FPUB_68060 3 /* Internal FPU */
49480 #define FPUB_SUNFPA 4 /* Sun-3 FPA */
49481 +#define FPUB_CFV4E 5
49482
49483 #define FPU_68881 (1<<FPUB_68881)
49484 #define FPU_68882 (1<<FPUB_68882)
49485 #define FPU_68040 (1<<FPUB_68040)
49486 #define FPU_68060 (1<<FPUB_68060)
49487 #define FPU_SUNFPA (1<<FPUB_SUNFPA)
49488 +#ifndef CONFIG_M5445X
49489 +#define FPU_CFV4E (1<<FPUB_CFV4E)
49490 +#else
49491 +#define FPU_CFV4E 0
49492 +#endif
49493
49494 #define MMUB_68851 0
49495 #define MMUB_68030 1 /* Internal MMU */
49496 @@ -235,6 +252,7 @@ extern unsigned long m68k_machtype;
49497 #define MMUB_68060 3 /* Internal MMU */
49498 #define MMUB_APOLLO 4 /* Custom Apollo */
49499 #define MMUB_SUN3 5 /* Custom Sun-3 */
49500 +#define MMUB_CFV4E 6
49501
49502 #define MMU_68851 (1<<MMUB_68851)
49503 #define MMU_68030 (1<<MMUB_68030)
49504 @@ -242,6 +260,7 @@ extern unsigned long m68k_machtype;
49505 #define MMU_68060 (1<<MMUB_68060)
49506 #define MMU_SUN3 (1<<MMUB_SUN3)
49507 #define MMU_APOLLO (1<<MMUB_APOLLO)
49508 +#define MMU_CFV4E (1<<MMUB_CFV4E)
49509
49510 #ifdef __KERNEL__
49511
49512 @@ -341,6 +360,14 @@ extern int m68k_is040or060;
49513 # endif
49514 #endif
49515
49516 +#if !defined(CONFIG_CFV4E)
49517 +# define CPU_IS_COLDFIRE (0)
49518 +#else
49519 +# define CPU_IS_COLDFIRE (1)
49520 +# define CPU_IS_CFV4E (1)
49521 +# define MMU_IS_CFV4E (1)
49522 +#endif
49523 +
49524 #define CPU_TYPE (m68k_cputype)
49525
49526 #ifdef CONFIG_M68KFPU_EMU
49527 --- a/include/asm-m68k/signal.h
49528 +++ b/include/asm-m68k/signal.h
49529 @@ -150,6 +150,7 @@ typedef struct sigaltstack {
49530 #ifdef __KERNEL__
49531 #include <asm/sigcontext.h>
49532
49533 +#ifndef CONFIG_COLDFIRE
49534 #define __HAVE_ARCH_SIG_BITOPS
49535
49536 static inline void sigaddset(sigset_t *set, int _sig)
49537 @@ -200,6 +201,10 @@ static inline int sigfindinword(unsigned
49538
49539 struct pt_regs;
49540 extern void ptrace_signal_deliver(struct pt_regs *regs, void *cookie);
49541 +#else
49542 +
49543 +#define ptrace_signal_deliver(regs, cookie) do { } while (0)
49544 +#endif /* CONFIG_COLDFIRE */
49545
49546 #endif /* __KERNEL__ */
49547
49548 --- a/include/asm-m68k/string.h
49549 +++ b/include/asm-m68k/string.h
49550 @@ -93,6 +93,7 @@ static inline char *strchr(const char *s
49551 return (char *)s - 1;
49552 }
49553
49554 +#ifndef CONFIG_COLDFIRE
49555 #define __HAVE_ARCH_STRCMP
49556 static inline int strcmp(const char *cs, const char *ct)
49557 {
49558 @@ -110,6 +111,7 @@ static inline int strcmp(const char *cs,
49559 : "+a" (cs), "+a" (ct), "=d" (res));
49560 return res;
49561 }
49562 +#endif
49563
49564 #define __HAVE_ARCH_MEMSET
49565 extern void *memset(void *, int, __kernel_size_t);
49566 --- a/include/asm-m68k/system.h
49567 +++ b/include/asm-m68k/system.h
49568 @@ -5,9 +5,24 @@
49569 #include <linux/kernel.h>
49570 #include <asm/segment.h>
49571 #include <asm/entry.h>
49572 +#include <asm/cfcache.h>
49573
49574 #ifdef __KERNEL__
49575
49576 +#ifdef CONFIG_COLDFIRE
49577 +#define FLUSH_BC (0x00040000)
49578 +
49579 +#define finish_arch_switch(prev) do { \
49580 + unsigned long tmpreg; \
49581 + asm volatile ( "move.l %2,%0\n" \
49582 + "orl %1,%0\n" \
49583 + "movec %0,%%cacr" \
49584 + : "=&d" (tmpreg) \
49585 + : "id" (FLUSH_BC), "m" (shadow_cacr)); \
49586 + } while(0)
49587 +
49588 +#endif
49589 +
49590 /*
49591 * switch_to(n) should switch tasks to task ptr, first checking that
49592 * ptr isn't the current task, in which case it does nothing. This
49593 @@ -63,16 +78,25 @@ asmlinkage void resume(void);
49594 #define smp_read_barrier_depends() ((void)0)
49595
49596 /* interrupt control.. */
49597 -#if 0
49598 -#define local_irq_enable() asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory")
49599 -#else
49600 #include <linux/hardirq.h>
49601 +#ifndef CONFIG_COLDFIRE
49602 #define local_irq_enable() ({ \
49603 if (MACH_IS_Q40 || !hardirq_count()) \
49604 asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory"); \
49605 })
49606 -#endif
49607 #define local_irq_disable() asm volatile ("oriw #0x0700,%%sr": : : "memory")
49608 +#else /* CONFIG_COLDFIRE */
49609 +#define local_irq_enable() \
49610 + asm volatile ("move.w %%sr, %%d0\n\t" \
49611 + "andil #0xf8ff,%%d0\n\t" \
49612 + "move.w %%d0, %%sr\n" \
49613 + : : : "cc", "d0", "memory")
49614 +#define local_irq_disable() \
49615 + asm volatile ("move %/sr,%%d0\n\t" \
49616 + "ori.l #0x0700,%%d0\n\t" \
49617 + "move %%d0,%/sr\n" \
49618 + : : : "cc", "%d0", "memory")
49619 +#endif
49620 #define local_save_flags(x) asm volatile ("movew %%sr,%0":"=d" (x) : : "memory")
49621 #define local_irq_restore(x) asm volatile ("movew %0,%%sr": :"d" (x) : "memory")
49622
49623 --- a/include/asm-m68k/thread_info.h
49624 +++ b/include/asm-m68k/thread_info.h
49625 @@ -58,5 +58,6 @@ struct thread_info {
49626 #define TIF_DELAYED_TRACE 14 /* single step a syscall */
49627 #define TIF_SYSCALL_TRACE 15 /* syscall trace active */
49628 #define TIF_MEMDIE 16
49629 +#define TIF_FREEZE 17 /* freezing processes */
49630
49631 #endif /* _ASM_M68K_THREAD_INFO_H */
49632 --- a/include/asm-m68k/tlbflush.h
49633 +++ b/include/asm-m68k/tlbflush.h
49634 @@ -2,7 +2,7 @@
49635 #define _M68K_TLBFLUSH_H
49636
49637
49638 -#ifndef CONFIG_SUN3
49639 +#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
49640
49641 #include <asm/current.h>
49642
49643 @@ -92,7 +92,12 @@ static inline void flush_tlb_kernel_rang
49644 flush_tlb_all();
49645 }
49646
49647 -#else
49648 +static inline void flush_tlb_pgtables(struct mm_struct *mm,
49649 + unsigned long start, unsigned long end)
49650 +{
49651 +}
49652 +
49653 +#elif defined(CONFIG_SUN3)
49654
49655
49656 /* Reserved PMEGs. */
49657 @@ -214,6 +219,13 @@ static inline void flush_tlb_kernel_page
49658 sun3_put_segmap (addr & ~(SUN3_PMEG_SIZE - 1), SUN3_INVALID_PMEG);
49659 }
49660
49661 +static inline void flush_tlb_pgtables(struct mm_struct *mm,
49662 + unsigned long start, unsigned long end)
49663 +{
49664 +}
49665 +
49666 +#else /* CONFIG_COLDFIRE */
49667 +#include <asm/cf_tlbflush.h>
49668 #endif
49669
49670 #endif /* _M68K_TLBFLUSH_H */
49671 --- a/include/asm-m68k/uaccess.h
49672 +++ b/include/asm-m68k/uaccess.h
49673 @@ -1,6 +1,9 @@
49674 #ifndef __M68K_UACCESS_H
49675 #define __M68K_UACCESS_H
49676
49677 +#ifdef CONFIG_COLDFIRE
49678 +#include <asm/cf_uaccess.h>
49679 +#else
49680 /*
49681 * User space memory access functions
49682 */
49683 @@ -367,4 +370,5 @@ unsigned long __clear_user(void __user *
49684
49685 #define strlen_user(str) strnlen_user(str, 32767)
49686
49687 +#endif /* CONFIG_COLDFIRE */
49688 #endif /* _M68K_UACCESS_H */
49689 --- a/include/asm-m68k/virtconvert.h
49690 +++ b/include/asm-m68k/virtconvert.h
49691 @@ -46,9 +46,14 @@ static inline void *phys_to_virt(unsigne
49692 #define virt_to_bus(a) (virt_to_phys(a) + (MACH_IS_HADES ? 0x80000000 : 0))
49693 #define bus_to_virt(a) (phys_to_virt((a) - (MACH_IS_HADES ? 0x80000000 : 0)))
49694 #else
49695 +#ifdef CONFIG_COLDFIRE
49696 +#define virt_to_bus(a) (a - PAGE_OFFSET + PCI_DMA_BASE)
49697 +#define bus_to_virt(a) (a - PCI_DMA_BASE + PAGE_OFFSET)
49698 +#else /* CONFIG_COLDFIRE */
49699 #define virt_to_bus virt_to_phys
49700 #define bus_to_virt phys_to_virt
49701 #endif
49702 +#endif
49703
49704 #endif
49705 #endif
49706 --- /dev/null
49707 +++ b/include/linux/can/dev.h
49708 @@ -0,0 +1,62 @@
49709 +/*
49710 + * linux/can/dev.h
49711 + *
49712 + * Definitions for CAN controller network devices lib (work in progress)
49713 + *
49714 + * * * $Id$
49715 + *
49716 + * Author: Andrey Volkov <avolkov@varma-el.com>
49717 + * Copyright (c) 2006 Varma Electronics Oy
49718 + *
49719 + */
49720 +
49721 +#ifndef CAN_DEVICE_H
49722 +#define CAN_DEVICE_H
49723 +
49724 +#include <linux/version.h>
49725 +#include <linux/can/error.h>
49726 +#include <linux/can/ioctl.h>
49727 +
49728 +struct can_priv {
49729 + struct can_device_stats can_stats;
49730 +
49731 + /* can-bus oscillator frequency, in Hz,
49732 + BE CAREFUL! SOME CONTROLLERS (LIKE SJA1000)
49733 + FOOLISH ABOUT THIS FRQ (for sja1000 as ex. this
49734 + clock must be xtal clock divided by 2). */
49735 + u32 can_sys_clock;
49736 +
49737 + /* by default max_brp is equal 64,
49738 + but for a Freescale TouCAN, as ex., it can be 255*/
49739 + u32 max_brp;
49740 + /* For the mostly all controllers, max_sjw is equal 4, but
49741 + some, hmm, CAN implementations hardwared it to 1 */
49742 + u8 max_sjw;
49743 +
49744 + u32 baudrate; /* in bauds */
49745 + struct can_bittime bit_time;
49746 +
49747 + spinlock_t irq_lock;
49748 + /* Please hold this lock when touching net_stats/can_stats*/
49749 + spinlock_t stats_lock;
49750 +
49751 + can_state_t state;
49752 + can_mode_t mode;
49753 + can_ctrlmode_t ctrlmode;
49754 +
49755 + int (*do_set_bit_time)(struct net_device *dev, struct can_bittime *br);
49756 + int (*do_get_state) (struct net_device *dev, can_state_t *state);
49757 + int (*do_set_mode) (struct net_device *dev, can_mode_t mode);
49758 + int (*do_set_ctrlmode)(struct net_device *dev, can_ctrlmode_t ctrlmode);
49759 + int (*do_get_ctrlmode)(struct net_device *dev, can_ctrlmode_t *ctrlmode);
49760 +};
49761 +
49762 +#define ND2D(_ndev) (_ndev->dev.parent)
49763 +
49764 +struct net_device *alloc_candev(int sizeof_priv);
49765 +void free_candev(struct net_device *dev);
49766 +
49767 +int can_calc_bit_time(struct can_priv *can, u32 baudrate,
49768 + struct can_bittime_std *bit_time);
49769 +
49770 +#endif /* CAN_DEVICE_H */
49771 --- /dev/null
49772 +++ b/include/linux/can/ioctl.h
49773 @@ -0,0 +1,152 @@
49774 +/*
49775 + * linux/can/ioctl.h
49776 + *
49777 + * Definitions for CAN controller setup (work in progress)
49778 + *
49779 + * $Id$
49780 + *
49781 + * Send feedback to <socketcan-users@lists.berlios.de>
49782 + *
49783 + */
49784 +
49785 +#ifndef CAN_IOCTL_H
49786 +#define CAN_IOCTL_H
49787 +
49788 +#include <linux/sockios.h>
49789 +
49790 +
49791 +/* max. 16 private ioctls */
49792 +
49793 +#define SIOCSCANBAUDRATE (SIOCDEVPRIVATE+0)
49794 +#define SIOCGCANBAUDRATE (SIOCDEVPRIVATE+1)
49795 +
49796 +#define SIOCSCANCUSTOMBITTIME (SIOCDEVPRIVATE+2)
49797 +#define SIOCGCANCUSTOMBITTIME (SIOCDEVPRIVATE+3)
49798 +
49799 +#define SIOCSCANMODE (SIOCDEVPRIVATE+4)
49800 +#define SIOCGCANMODE (SIOCDEVPRIVATE+5)
49801 +
49802 +#define SIOCSCANCTRLMODE (SIOCDEVPRIVATE+6)
49803 +#define SIOCGCANCTRLMODE (SIOCDEVPRIVATE+7)
49804 +
49805 +#define SIOCSCANFILTER (SIOCDEVPRIVATE+8)
49806 +#define SIOCGCANFILTER (SIOCDEVPRIVATE+9)
49807 +
49808 +#define SIOCGCANSTATE (SIOCDEVPRIVATE+10)
49809 +#define SIOCGCANSTATS (SIOCDEVPRIVATE+11)
49810 +
49811 +#define SIOCSCANERRORCONFIG (SIOCDEVPRIVATE+12)
49812 +#define SIOCGCANERRORCONFIG (SIOCDEVPRIVATE+13)
49813 +
49814 +/* parameters for ioctls */
49815 +
49816 +/* SIOC[SG]CANBAUDRATE */
49817 +/* baudrate for CAN-controller in bits per second. */
49818 +/* 0 = Scan for baudrate (Autobaud) */
49819 +
49820 +typedef __u32 can_baudrate_t;
49821 +
49822 +
49823 +/* SIOC[SG]CANCUSTOMBITTIME */
49824 +
49825 +typedef enum CAN_BITTIME_TYPE {
49826 + CAN_BITTIME_STD,
49827 + CAN_BITTIME_BTR
49828 +} can_bittime_type_t;
49829 +
49830 +/* TSEG1 of controllers usually is a sum of synch_seg (always 1),
49831 + * prop_seg and phase_seg1, TSEG2 = phase_seg2 */
49832 +
49833 +struct can_bittime_std {
49834 + __u32 brp; /* baud rate prescaler */
49835 + __u8 prop_seg; /* from 1 to 8 */
49836 + __u8 phase_seg1; /* from 1 to 8 */
49837 + __u8 phase_seg2; /* from 1 to 8 */
49838 + __u8 sjw:7; /* from 1 to 4 */
49839 + __u8 sam:1; /* 1 - enable triple sampling */
49840 +};
49841 +
49842 +struct can_bittime_btr {
49843 + __u8 btr0;
49844 + __u8 btr1;
49845 +};
49846 +
49847 +struct can_bittime {
49848 + can_bittime_type_t type;
49849 + union {
49850 + struct can_bittime_std std;
49851 + struct can_bittime_btr btr;
49852 + };
49853 +};
49854 +
49855 +#define CAN_BAUDRATE_UNCONFIGURED ((__u32) 0xFFFFFFFFU)
49856 +#define CAN_BAUDRATE_UNKNOWN 0
49857 +
49858 +/* SIOC[SG]CANMODE */
49859 +
49860 +typedef __u32 can_mode_t;
49861 +
49862 +#define CAN_MODE_STOP 0
49863 +#define CAN_MODE_START 1
49864 +#define CAN_MODE_SLEEP 2
49865 +
49866 +
49867 +/* SIOC[SG]CANCTRLMODE */
49868 +
49869 +typedef __u32 can_ctrlmode_t;
49870 +
49871 +#define CAN_CTRLMODE_LOOPBACK 0x1
49872 +#define CAN_CTRLMODE_LISTENONLY 0x2
49873 +
49874 +
49875 +/* SIOCGCANFILTER */
49876 +
49877 +typedef __u32 can_filter_t;
49878 +
49879 +/* filter modes (may vary due to controller specific capabilities) */
49880 +#define CAN_FILTER_CAPAB 0 /* get filter type capabilities
49881 + (32 Bit value) */
49882 +#define CAN_FILTER_MASK_VALUE 1 /* easy bit filter (see struct can_filter) */
49883 +#define CAN_FILTER_SFF_BITMASK 2 /* bitfield with 2048 bit SFF filter */
49884 + /* filters 3 - 31 currently undefined */
49885 +
49886 +#define CAN_FILTER_MAX 31 /* max. filter type value */
49887 +
49888 +
49889 +/* SIOCGCANSTATE */
49890 +
49891 +typedef __u32 can_state_t;
49892 +
49893 +#define CAN_STATE_ACTIVE 0
49894 +#define CAN_STATE_BUS_WARNING 1
49895 +#define CAN_STATE_BUS_PASSIVE 2
49896 +#define CAN_STATE_BUS_OFF 3
49897 +#define CAN_STATE_SCANNING_BAUDRATE 4
49898 +#define CAN_STATE_STOPPED 5
49899 +#define CAN_STATE_SLEEPING 6
49900 +
49901 +
49902 +/* SIOCGCANSTATS */
49903 +
49904 +struct can_device_stats {
49905 + int error_warning;
49906 + int data_overrun;
49907 + int wakeup;
49908 + int bus_error;
49909 + int error_passive;
49910 + int arbitration_lost;
49911 + int restarts;
49912 + int bus_error_at_init;
49913 +};
49914 +
49915 +/* SIOC[SG]CANERRORCONFIG */
49916 +
49917 +typedef enum CAN_ERRCFG_TYPE {
49918 + CAN_ERRCFG_MASK,
49919 + CAN_ERRCFG_BUSERR,
49920 + CAN_ERRCFG_BUSOFF
49921 +} can_errcfg_type_t;
49922 +
49923 +/* tbd */
49924 +
49925 +#endif /* CAN_IOCTL_H */
49926 --- /dev/null
49927 +++ b/include/linux/can/version.h
49928 @@ -0,0 +1,22 @@
49929 +/*
49930 + * linux/can/version.h
49931 + *
49932 + * Version information for the CAN network layer implementation
49933 +
49934 + * Author: Urs Thuermann <urs.thuermann@volkswagen.de>
49935 + * Copyright (c) 2002-2007 Volkswagen Group Electronic Research
49936 + * All rights reserved.
49937 + *
49938 + * Send feedback to <socketcan-users@lists.berlios.de>
49939 + *
49940 + */
49941 +
49942 +#ifndef CAN_VERSION_H
49943 +#define CAN_VERSION_H
49944 +
49945 +#define RCSID(s) asm(".section .rodata.str1.1,\"aMS\",@progbits,1\n\t" \
49946 + ".string \"" s "\"\n\t.previous\n")
49947 +
49948 +RCSID("$Id$");
49949 +
49950 +#endif /* CAN_VERSION_H */
49951 --- a/include/linux/fb.h
49952 +++ b/include/linux/fb.h
49953 @@ -873,6 +873,17 @@ struct fb_info {
49954 #define fb_writeq sbus_writeq
49955 #define fb_memset sbus_memset_io
49956
49957 +#elif defined(CONFIG_COLDFIRE)
49958 +#define fb_readb readb
49959 +#define fb_readw readw
49960 +#define fb_readl readl
49961 +#define fb_readq readq
49962 +#define fb_writeb writeb
49963 +#define fb_writew writew
49964 +#define fb_writel writel
49965 +#define fb_writeq writeq
49966 +#define fb_memset memset_io
49967 +
49968 #elif defined(__i386__) || defined(__alpha__) || defined(__x86_64__) || defined(__hppa__) || (defined(__sh__) && !defined(__SH5__)) || defined(__powerpc__) || defined(__avr32__)
49969
49970 #define fb_readb __raw_readb
49971 @@ -899,7 +910,7 @@ struct fb_info {
49972
49973 #endif
49974
49975 -#if defined (__BIG_ENDIAN)
49976 +#if defined (__BIG_ENDIAN) && !defined(CONFIG_COLDFIRE)
49977 #define FB_LEFT_POS(bpp) (32 - bpp)
49978 #define FB_SHIFT_HIGH(val, bits) ((val) >> (bits))
49979 #define FB_SHIFT_LOW(val, bits) ((val) << (bits))
49980 --- a/include/linux/fsl_devices.h
49981 +++ b/include/linux/fsl_devices.h
49982 @@ -91,6 +91,19 @@ enum fsl_usb2_operating_modes {
49983 FSL_USB2_DR_OTG,
49984 };
49985
49986 +/* DDD
49987 + * replace _operating_modes with _controller
49988 + *
49989 + * the operating_mode tests in fsl_platform_verify() aren't needed,
49990 + * since the ehci driver isn't going to be probe()d unless it's
49991 + * "fsl-ehci" device anyway, and what we really need to know is
49992 + * which controller (MPH/DR) we're dealing with
49993 + */
49994 +enum fsl_usb2_controller {
49995 + FSL_USB2_MPH,
49996 + FSL_USB2_DR,
49997 +};
49998 +
49999 enum fsl_usb2_phy_modes {
50000 FSL_USB2_PHY_NONE,
50001 FSL_USB2_PHY_ULPI,
50002 @@ -101,9 +114,36 @@ enum fsl_usb2_phy_modes {
50003
50004 struct fsl_usb2_platform_data {
50005 /* board specific information */
50006 - enum fsl_usb2_operating_modes operating_mode;
50007 + /*
50008 + * DDD see note above
50009 + * enum fsl_usb2_operating_modes operating_mode;
50010 + */
50011 + enum fsl_usb2_controller controller;
50012 enum fsl_usb2_phy_modes phy_mode;
50013 unsigned int port_enables;
50014 + /*
50015 + * DDD this could arguably be moved to a separate
50016 + * fsl usb2 device header file
50017 + */
50018 + char *name; /* pretty print */
50019 + int (*platform_init) (struct platform_device *);
50020 + void (*platform_uninit) (struct platform_device *);
50021 + int (*platform_verify) (struct platform_device *);
50022 + u32 xcvr_type; /* PORTSCX_PTS_* */
50023 + u32 view; /* ULPI viewport register */
50024 + u32 r_start; /* start of MEM resource */
50025 + u32 r_len; /* length of MEM resource */
50026 + void __iomem *regs; /* ioremap'd register base */
50027 + unsigned big_endian_mmio : 1;
50028 + unsigned big_endian_desc : 1;
50029 + unsigned es : 1; /* need USBMODE:ES */
50030 + unsigned have_sysif_regs : 1;
50031 + unsigned le_setup_buf : 1;
50032 + unsigned does_otg : 1; /* set IFF it's an OTG port */
50033 +
50034 + unsigned power_budget; /* for hcd->power_budget */
50035 + struct fsl_xcvr_ops *xcvr_ops;
50036 + int max_ep_nr; /* max # of endpoints */
50037 };
50038
50039 /* Flags in fsl_usb2_mph_platform_data */
50040 @@ -126,5 +166,16 @@ struct mpc8xx_pcmcia_ops {
50041 int(*voltage_set)(int slot, int vcc, int vpp);
50042 };
50043
50044 +struct fsl_ata_platform_data {
50045 +#ifdef CONFIG_FSL_PATA_USE_DMA
50046 + int udma_mask; /* UDMA modes h/w can handle */
50047 + int fifo_alarm; /* value for fifo_alarm reg */
50048 + int max_sg; /* longest sglist h/w can handle */
50049 +#endif
50050 + int (*init)(struct platform_device *pdev);
50051 + void (*exit)(void);
50052 + int (*get_clk_rate)(void);
50053 +};
50054 +
50055 #endif /* _FSL_DEVICE_H_ */
50056 #endif /* __KERNEL__ */
50057 --- a/include/linux/pci.h
50058 +++ b/include/linux/pci.h
50059 @@ -458,8 +458,10 @@ int __must_check pcibios_enable_device(s
50060 char *pcibios_setup(char *str);
50061
50062 /* Used only when drivers/pci/setup.c is used */
50063 +#ifndef CONFIG_COLDFIRE
50064 void pcibios_align_resource(void *, struct resource *, resource_size_t,
50065 resource_size_t);
50066 +#endif
50067 void pcibios_update_irq(struct pci_dev *, int irq);
50068
50069 /* Generic PCI functions used internally */
50070 --- /dev/null
50071 +++ b/include/linux/spi/mcfqspi.h
50072 @@ -0,0 +1,80 @@
50073 +/****************************************************************************/
50074 +
50075 +/*
50076 + * mcfqspi.c - Master QSPI controller for the ColdFire processors
50077 + *
50078 + * (C) Copyright 2005, Intec Automation,
50079 + * Mike Lavender (mike@steroidmicros)
50080 + *
50081 +
50082 + This program is free software; you can redistribute it and/or modify
50083 + it under the terms of the GNU General Public License as published by
50084 + the Free Software Foundation; either version 2 of the License, or
50085 + (at your option) any later version.
50086 +
50087 + This program is distributed in the hope that it will be useful,
50088 + but WITHOUT ANY WARRANTY; without even the implied warranty of
50089 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
50090 + GNU General Public License for more details.
50091 +
50092 + You should have received a copy of the GNU General Public License
50093 + along with this program; if not, write to the Free Software
50094 + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
50095 +/* ------------------------------------------------------------------------- */
50096 +
50097 +#ifndef MCFQSPI_H_
50098 +#define MCFQSPI_H_
50099 +
50100 +#define QSPI_CS_INIT 0x01
50101 +#define QSPI_CS_ASSERT 0x02
50102 +#define QSPI_CS_DROP 0x04
50103 +
50104 +#define QSPIIOCS_DOUT_HIZ 1 /* QMR[DOHIE] set hi-z dout between transfers */
50105 +#define QSPIIOCS_BITS 2 /* QMR[BITS] set transfer size */
50106 +#define QSPIIOCG_BITS 3 /* QMR[BITS] get transfer size */
50107 +#define QSPIIOCS_CPOL 4 /* QMR[CPOL] set SCK inactive state */
50108 +#define QSPIIOCS_CPHA 5 /* QMR[CPHA] set SCK phase, 1=rising edge */
50109 +#define QSPIIOCS_BAUD 6 /* QMR[BAUD] set SCK baud rate divider */
50110 +#define QSPIIOCS_QCD 7 /* QDLYR[QCD] set start delay */
50111 +#define QSPIIOCS_DTL 8 /* QDLYR[DTL] set after delay */
50112 +#define QSPIIOCS_CONT 9 /* continuous CS asserted during transfer */
50113 +#define QSPIIOCS_READDATA 10 /* set data send during read */
50114 +#define QSPIIOCS_ODD_MOD 11 /* if length of buffer is a odd number, 16-bit transfers */
50115 + /* are finalized with a 8-bit transfer */
50116 +#define QSPIIOCS_DSP_MOD 12 /* transfers are bounded to 15/30 bytes (a multiple of 3 bytes = 1 DSPword) */
50117 +#define QSPIIOCS_POLL_MOD 13 /* driver uses polling instead of interrupts */
50118 +
50119 +#define QSPIIOCS_SET_CSIV 14 /* sets CSIV flag (cs inactive level) */
50120 +
50121 +#ifdef CONFIG_M520x
50122 +#undef MCF_GPIO_PAR_QSPI
50123 +#define MCF_GPIO_PAR_QSPI (0xA4034)
50124 +#endif
50125 +
50126 +struct coldfire_spi_master {
50127 + u16 bus_num;
50128 + u16 num_chipselect;
50129 + u8 irq_source;
50130 + u32 irq_vector;
50131 + u32 irq_mask;
50132 + u8 irq_lp;
50133 + u8 par_val;
50134 + u16 par_val16;
50135 + void (*cs_control)(u8 cs, u8 command);
50136 +};
50137 +
50138 +
50139 +struct coldfire_spi_chip {
50140 + u8 mode;
50141 + u8 bits_per_word;
50142 + u8 del_cs_to_clk;
50143 + u8 del_after_trans;
50144 + u16 void_write_data;
50145 +};
50146 +
50147 +typedef struct qspi_read_data {
50148 + __u32 length;
50149 + __u8 *buf; /* data to send during read */
50150 + unsigned int loop : 1;
50151 +} qspi_read_data;
50152 +#endif /*MCFQSPI_H_*/
50153 --- /dev/null
50154 +++ b/include/linux/usb/fsl_usb2.h
50155 @@ -0,0 +1,463 @@
50156 +/*
50157 + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
50158 + */
50159 +
50160 +/*
50161 + * The code contained herein is licensed under the GNU General Public
50162 + * License. You may obtain a copy of the GNU General Public License
50163 + * Version 2 or later at the following locations:
50164 + *
50165 + * http://www.opensource.org/licenses/gpl-license.html
50166 + * http://www.gnu.org/copyleft/gpl.html
50167 + */
50168 +
50169 +/*
50170 + * Freescale USB device/endpoint management registers
50171 + */
50172 +#ifndef __FSL_USB2_H
50173 +#define __FSL_USB2_H
50174 +
50175 +
50176 + /* USB DR device mode registers (Little Endian) */
50177 +struct fsl_usb_device_regs {
50178 + /* Capability register */
50179 + u32 id;
50180 + u32 res1[63];
50181 + u16 caplength; /* Capability Register Length */
50182 + u16 hciversion; /* Host Controller Interface Version */
50183 + u32 hcsparams; /* Host Controller Structual Parameters */
50184 + u32 hccparams; /* Host Controller Capability Parameters */
50185 + u32 res2[5];
50186 + u32 dciversion; /* Device Controller Interface Version */
50187 + u32 dccparams; /* Device Controller Capability Parameters */
50188 + u32 res3[6];
50189 + /* Operation register */
50190 + u32 usbcmd; /* USB Command Register */
50191 + u32 usbsts; /* USB Status Register */
50192 + u32 usbintr; /* USB Interrupt Enable Register */
50193 + u32 frindex; /* Frame Index Register */
50194 + u32 res4;
50195 + u32 deviceaddr; /* Device Address */
50196 + u32 endpointlistaddr; /* Endpoint List Address Register */
50197 + u32 res5;
50198 + u32 burstsize; /* Master Interface Data Burst Size Register */
50199 + u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
50200 + u32 res6[2];
50201 + u32 ulpiview;
50202 + u32 res7[3];
50203 + u32 configflag; /* Configure Flag Register */
50204 + u32 portsc1; /* Port 1 Status and Control Register */
50205 + u32 res8[7];
50206 + u32 otgsc; /* On-The-Go Status and Control */
50207 + u32 usbmode; /* USB Mode Register */
50208 + u32 endptsetupstat; /* Endpoint Setup Status Register */
50209 + u32 endpointprime; /* Endpoint Initialization Register */
50210 + u32 endptflush; /* Endpoint Flush Register */
50211 + u32 endptstatus; /* Endpoint Status Register */
50212 + u32 endptcomplete; /* Endpoint Complete Register */
50213 +#if 0
50214 + u32 endptctrl[USB_MAX_ENDPOINTS]; /* Endpoint Control Registers */
50215 +#else
50216 + // DDD see DCCPARAMS:DEN for the real number of device endpoints
50217 + // DDD 16 is the max
50218 + u32 endptctrl[16]; /* Endpoint Control Registers */
50219 +#endif
50220 +};
50221 +
50222 + /* USB DR host mode registers (Little Endian) */
50223 +struct fsl_usb_host_regs {
50224 + /* Capability register */
50225 + u32 id;
50226 + u32 res1[63];
50227 + u16 caplength; /* Capability Register Length */
50228 + u16 hciversion; /* Host Controller Interface Version */
50229 + u32 hcsparams; /* Host Controller Structual Parameters */
50230 + u32 hccparams; /* Host Controller Capability Parameters */
50231 + u32 res2[5];
50232 + u32 dciversion; /* Device Controller Interface Version */
50233 + u32 dccparams; /* Device Controller Capability Parameters */
50234 + u32 res3[6];
50235 + /* Operation register */
50236 + u32 usbcmd; /* USB Command Register */
50237 + u32 usbsts; /* USB Status Register */
50238 + u32 usbintr; /* USB Interrupt Enable Register */
50239 + u32 frindex; /* Frame Index Register */
50240 + u32 res4;
50241 + u32 periodiclistbase; /* Periodic Frame List Base Address Register */
50242 + u32 asynclistaddr; /* Current Asynchronous List Address Register */
50243 + u32 res5;
50244 + u32 burstsize; /* Master Interface Data Burst Size Register */
50245 + u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
50246 + u32 res6[2];
50247 + u32 ulpiview;
50248 + u32 res7[3];
50249 + u32 configflag; /* Configure Flag Register */
50250 + u32 portsc1; /* Port 1 Status and Control Register */
50251 + u32 res8[7];
50252 + u32 otgsc; /* On-The-Go Status and Control */
50253 + u32 usbmode; /* USB Mode Register */
50254 + u32 endptsetupstat; /* Endpoint Setup Status Register */
50255 + u32 endpointprime; /* Endpoint Initialization Register */
50256 + u32 endptflush; /* Endpoint Flush Register */
50257 + u32 endptstatus; /* Endpoint Status Register */
50258 + u32 endptcomplete; /* Endpoint Complete Register */
50259 +#if 0
50260 + u32 endptctrl[USB_MAX_ENDPOINTS]; /* Endpoint Control Registers */
50261 +#else
50262 + /* DDD see DCCPARAMS:DEN for the real number of device endpoints */
50263 + /* DDD 16 is the max */
50264 + u32 endptctrl[16]; /* Endpoint Control Registers */
50265 +#endif
50266 +};
50267 +
50268 + /* non-EHCI USB system interface registers (Big Endian) */
50269 +struct usb_sys_interface {
50270 + u32 snoop1;
50271 + u32 snoop2;
50272 + u32 age_cnt_thresh; /* Age Count Threshold Register */
50273 + u32 pri_ctrl; /* Priority Control Register */
50274 + u32 si_ctrl; /* System Interface Control Register */
50275 + u32 res[59];
50276 + u32 control; /* General Purpose Control Register */
50277 +};
50278 +
50279 +/* ep0 transfer state */
50280 +#define WAIT_FOR_SETUP 0
50281 +#define DATA_STATE_XMIT 1
50282 +#define DATA_STATE_NEED_ZLP 2
50283 +#define WAIT_FOR_OUT_STATUS 3
50284 +#define DATA_STATE_RECV 4
50285 +
50286 +/* Frame Index Register Bit Masks */
50287 +#define USB_FRINDEX_MASKS 0x3fff
50288 +
50289 +
50290 +
50291 +/* USBCMD Register Bit Masks */
50292 +#define USB_CMD_RUN_STOP 0x00000001
50293 +#define USB_CMD_CTRL_RESET 0x00000002
50294 +#define USB_CMD_PERIODIC_SCHEDULE_EN 0x00000010
50295 +#define USB_CMD_ASYNC_SCHEDULE_EN 0x00000020
50296 +#define USB_CMD_INT_AA_DOORBELL 0x00000040
50297 +#define USB_CMD_ASP 0x00000300
50298 +#define USB_CMD_ASYNC_SCH_PARK_EN 0x00000800
50299 +#define USB_CMD_SUTW 0x00002000
50300 +#define USB_CMD_ATDTW 0x00004000
50301 +#define USB_CMD_ITC 0x00FF0000
50302 +
50303 +/* bit 15,3,2 are frame list size */
50304 +#define USB_CMD_FRAME_SIZE_1024 0x00000000
50305 +#define USB_CMD_FRAME_SIZE_512 0x00000004
50306 +#define USB_CMD_FRAME_SIZE_256 0x00000008
50307 +#define USB_CMD_FRAME_SIZE_128 0x0000000C
50308 +#define USB_CMD_FRAME_SIZE_64 0x00008000
50309 +#define USB_CMD_FRAME_SIZE_32 0x00008004
50310 +#define USB_CMD_FRAME_SIZE_16 0x00008008
50311 +#define USB_CMD_FRAME_SIZE_8 0x0000800C
50312 +
50313 +/* bit 9-8 are async schedule park mode count */
50314 +#define USB_CMD_ASP_00 0x00000000
50315 +#define USB_CMD_ASP_01 0x00000100
50316 +#define USB_CMD_ASP_10 0x00000200
50317 +#define USB_CMD_ASP_11 0x00000300
50318 +#define USB_CMD_ASP_BIT_POS 8
50319 +
50320 +/* bit 23-16 are interrupt threshold control */
50321 +#define USB_CMD_ITC_NO_THRESHOLD 0x00000000
50322 +#define USB_CMD_ITC_1_MICRO_FRM 0x00010000
50323 +#define USB_CMD_ITC_2_MICRO_FRM 0x00020000
50324 +#define USB_CMD_ITC_4_MICRO_FRM 0x00040000
50325 +#define USB_CMD_ITC_8_MICRO_FRM 0x00080000
50326 +#define USB_CMD_ITC_16_MICRO_FRM 0x00100000
50327 +#define USB_CMD_ITC_32_MICRO_FRM 0x00200000
50328 +#define USB_CMD_ITC_64_MICRO_FRM 0x00400000
50329 +#define USB_CMD_ITC_BIT_POS 16
50330 +
50331 +
50332 +
50333 +
50334 +/* USB STS Register Bit Masks */
50335 +#define USB_STS_INT 0x00000001
50336 +#define USB_STS_ERR 0x00000002
50337 +#define USB_STS_PORT_CHANGE 0x00000004
50338 +#define USB_STS_FRM_LST_ROLL 0x00000008
50339 +#define USB_STS_SYS_ERR 0x00000010
50340 +#define USB_STS_IAA 0x00000020
50341 +#define USB_STS_RESET 0x00000040
50342 +#define USB_STS_SOF 0x00000080
50343 +#define USB_STS_SUSPEND 0x00000100
50344 +#define USB_STS_HC_HALTED 0x00001000
50345 +#define USB_STS_RCL 0x00002000
50346 +#define USB_STS_PERIODIC_SCHEDULE 0x00004000
50347 +#define USB_STS_ASYNC_SCHEDULE 0x00008000
50348 +
50349 +/* USB INTR Register Bit Masks */
50350 +#define USB_INTR_INT_EN 0x00000001
50351 +#define USB_INTR_ERR_INT_EN 0x00000002
50352 +#define USB_INTR_PTC_DETECT_EN 0x00000004
50353 +#define USB_INTR_FRM_LST_ROLL_EN 0x00000008
50354 +#define USB_INTR_SYS_ERR_EN 0x00000010
50355 +#define USB_INTR_ASYN_ADV_EN 0x00000020
50356 +#define USB_INTR_RESET_EN 0x00000040
50357 +#define USB_INTR_SOF_EN 0x00000080
50358 +#define USB_INTR_DEVICE_SUSPEND 0x00000100
50359 +
50360 +/* Device Address bit masks */
50361 +#define USB_DEVICE_ADDRESS_MASK 0xFE000000
50362 +#define USB_DEVICE_ADDRESS_BIT_POS 25
50363 +
50364 +/* endpoint list address bit masks */
50365 +#define USB_EP_LIST_ADDRESS_MASK 0xfffff800
50366 +
50367 +
50368 +/* x_PORTSCx */
50369 +/* bit 31-30 are port transceiver select */
50370 +#define PORTSCX_PTS_MASK (3 << 30) /* parallel xcvr select mask */
50371 +#define PORTSCX_PHY_TYPE_SEL PORTSCX_PTS_MASK
50372 +#define PORTSCX_PTS_UTMI (0 << 30) /* UTMI/UTMI+ */
50373 +#define PORTSCX_PTS_PHILIPS (1 << 30) /* Philips classic */
50374 +#define PORTSCX_PTS_ULPI (2 << 30) /* ULPI */
50375 +#define PORTSCX_PTS_SERIAL (3 << 30) /* serial */
50376 +#define PORTSCX_PTS_FSLS PORTSCX_PTS_SERIAL
50377 +#define PORTSCX_PTS_ONCHIP PORTSCX_PTS_FSLS
50378 +
50379 +#define PORTSCX_STS (1 << 29) /* serial xcvr select */
50380 +
50381 +/* bit 28 is parallel transceiver width for UTMI interface */
50382 +#define PORTSCX_PTW_8BIT (0 << 28) /* 8 bit parallel xcvr */
50383 +#define PORTSCX_PTW_16BIT (1 << 28) /* 16 bi parallel xcvr */
50384 +
50385 +/* bit 27-26 are port speed */
50386 +#define PORTSCX_PORT_SPEED_FULL (0 << 26)
50387 +#define PORTSCX_PORT_SPEED_LOW (1 << 26)
50388 +#define PORTSCX_PORT_SPEED_HIGH (2 << 26)
50389 +#define PORTSCX_PORT_SPEED_UNDEF (3 << 26)
50390 +#define PORTSCX_PORT_SPEED_MASK (3 << 26)
50391 +
50392 +#define PORTSCX_PHY_LOW_POWER_SPD (1 << 23) /* phy low pwr suspend/clk disable */
50393 +
50394 +/* bit 19-16 are port test control */
50395 +#define PORTSCX_PTC_DISABLE (0 << 16)
50396 +#define PORTSCX_PTC_JSTATE (1 << 16)
50397 +#define PORTSCX_PTC_KSTATE (2 << 16)
50398 +#define PORTSCX_PTC_SEQNAK (3 << 16) /* SE0 (host) / NAK (device) */
50399 +#define PORTSCX_PTC_PACKET (4 << 16)
50400 +#define PORTSCX_PTC_FORCE_EN_HS (5 << 16)
50401 +#define PORTSCX_PTC_FORCE_EN_FS (6 << 16)
50402 +#define PORTSCX_PTC_FORCE_EN_LS (7 << 16)
50403 +
50404 +
50405 +/* bit 15-14 are port indicator control */
50406 +#define PORTSCX_PIC_OFF (0 << 14)
50407 +#define PORTSCX_PIC_AMBER (1 << 14)
50408 +#define PORTSCX_PIC_GREEN (2 << 14)
50409 +#define PORTSCX_PIC_UNDEF (3 << 14)
50410 +
50411 +#define PORTSCX_PORT_POWER (1 << 12) /* port power */
50412 +
50413 +/* bit 11-10 are line status */
50414 +#define PORTSCX_LS_MASK (3 << 10) /* Line State mask */
50415 +#define PORTSCX_LS_SE0 (0 << 10) /* SE0 */
50416 +#define PORTSCX_LS_K_STATE (1 << 10) /* K-state */
50417 +#define PORTSCX_LS_J_STATE (2 << 10) /* J-state */
50418 +
50419 +#define PORTSCX_PORT_RESET (1 << 8) /* Port reset */
50420 +#define PORTSCX_PORT_SUSPEND (1 << 7) /* Suspend */
50421 +#define PORTSCX_PORT_FORCE_RESUME (1 << 6) /* Force port resume */
50422 +#define PORTSCX_OVER_CURRENT_CHG (1 << 5) /* over current change */
50423 +#define PORTSCX_OVER_CURRENT_ACT (1 << 4) /* over currrent active */
50424 +#define PORTSCX_PORT_EN_DIS_CHANGE (1 << 3) /* port {en,dis}able change */
50425 +#define PORTSCX_PORT_ENABLE (1 << 2) /* port enabled */
50426 +#define PORTSCX_CONNECT_STATUS_CHANGE (1 << 1) /* connect status change */
50427 +#define PORTSCX_CURRENT_CONNECT_STATUS (1 << 0) /* current connect status */
50428 +
50429 +#define PORTSCX_W1C_BITS \
50430 + ( PORTSCX_CONNECT_STATUS_CHANGE | \
50431 + PORTSCX_PORT_EN_DIS_CHANGE | \
50432 + PORTSCX_OVER_CURRENT_CHG )
50433 +
50434 +
50435 +
50436 +/* UOG_OTGSC Register Bits */
50437 +/* control bits: */
50438 +#define OTGSC_CTRL_VBUS_DISCHARGE (1 << 0)
50439 +#define OTGSC_CTRL_VBUS_CHARGE (1 << 1)
50440 +#define OTGSC_CTRL_OTG_TERM (1 << 3) /* controls DM pulldown */
50441 +#define OTGSC_CTRL_DATA_PULSING (1 << 4)
50442 +#define OTGSC_CTRL_USB_ID_PU (1 << 5) /* enable ID pullup */
50443 +/* current status: (R/O) */
50444 +#define OTGSC_STS_USB_ID (1 << 8) /* 0=A-device 1=B-device */
50445 +#define OTGSC_STS_A_VBUS_VALID (1 << 9)
50446 +#define OTGSC_STS_A_SESSION_VALID (1 << 10)
50447 +#define OTGSC_STS_B_SESSION_VALID (1 << 11)
50448 +#define OTGSC_STS_B_SESSION_END (1 << 12)
50449 +#define OTGSC_STS_1ms_TIMER (1 << 13)
50450 +#define OTGSC_STS_DATA_PULSE (1 << 14)
50451 +/* interrupt status: (write to clear) */
50452 +#define OTGSC_INTSTS_MASK (0x7f << 16)
50453 +#define OTGSC_INTSTS_USB_ID (1 << 16)
50454 +#define OTGSC_INTSTS_A_VBUS_VALID (1 << 17)
50455 +#define OTGSC_INTSTS_A_SESSION_VALID (1 << 18)
50456 +#define OTGSC_INTSTS_B_SESSION_VALID (1 << 19)
50457 +#define OTGSC_INTSTS_B_SESSION_END (1 << 20)
50458 +#define OTGSC_INTSTS_1MS_TIMER (1 << 21)
50459 +#define OTGSC_INTSTS_DATA_PULSE (1 << 22)
50460 +/* interrupt enables: */
50461 +#define OTGSC_IE_MASK (0x7f << 24)
50462 +#define OTGSC_IE_USB_ID (1 << 24)
50463 +#define OTGSC_IE_A_VBUS_VALID (1 << 25)
50464 +#define OTGSC_IE_A_SESSION_VALID (1 << 26)
50465 +#define OTGSC_IE_B_SESSION_VALID (1 << 27)
50466 +#define OTGSC_IE_B_SESSION_END (1 << 28)
50467 +#define OTGSC_IE_1ms_TIMER (1 << 29)
50468 +#define OTGSC_IE_DATA_PULSE (1 << 30)
50469 +
50470 +#if 1 /* DDD FIXME these here for compatibility between my names and Leo's */
50471 +/* OTG interrupt enable bit masks */
50472 +#define OTGSC_INTERRUPT_ENABLE_BITS_MASK OTGSC_IE_MASK
50473 +
50474 +/* OTG interrupt status bit masks */
50475 +#define OTGSC_INTERRUPT_STATUS_BITS_MASK OTGSC_INTSTS_MASK
50476 +#endif // 1
50477 +
50478 +
50479 +
50480 +/* x_USBMODE */
50481 +#undef USBMODE_SDIS /* defined as bit 3 in drivers/usb/host/ehci.h */
50482 +#define USBMODE_SDIS (1 << 4) /* stream disable mode */
50483 +#define USBMODE_SLOM (1 << 3) /* setup lockout mode */
50484 +#define USBMODE_ES (1 << 2) /* (big) endian select */
50485 +#define USBMODE_CM_MASK (3 << 0) /* controller mode mask */
50486 +#define USBMODE_CM_HOST (3 << 0) /* host */
50487 +#define USBMODE_CM_DEVICE (2 << 0) /* device */
50488 +// DDD #define USBMODE_CM_IDLE (0 << 0) /* idle */
50489 +
50490 +/* DDD for compatibility for now */
50491 +#define USB_MODE_CTRL_MODE_IDLE USBMODE_CM_IDLE
50492 +#define USB_MODE_CTRL_MODE_DEVICE USBMODE_CM_DEVICE
50493 +#define USB_MODE_CTRL_MODE_HOST USBMODE_CM_HOST
50494 +#define USB_MODE_SETUP_LOCK_OFF USBMODE_SLOM
50495 +#define USB_MODE_STREAM_DISABLE USBMODE_SDIS
50496 +
50497 +
50498 +/* ULPIVIEW register bits */
50499 +#define ULPIVW_WU (1 << 31) /* Wakeup */
50500 +#define ULPIVW_RUN (1 << 30) /* read/write run */
50501 +#define ULPIVW_WRITE (1 << 29) /* 0=read 1=write */
50502 +#define ULPIVW_SS (1 << 27) /* SyncState */
50503 +#define ULPIVW_PORT_MASK 0x07 /* Port field */
50504 +#define ULPIVW_PORT_SHIFT 24
50505 +#define ULPIVW_ADDR_MASK 0xFF /* data address field */
50506 +#define ULPIVW_ADDR_SHIFT 16
50507 +#define ULPIVW_RDATA_MASK 0xFF /* read data field */
50508 +#define ULPIVW_RDATA_SHIFT 8
50509 +#define ULPIVW_WDATA_MASK 0xFF /* write data field */
50510 +#define ULPIVW_WDATA_SHIFT 0
50511 +
50512 +
50513 +/* Endpoint Flush Register */
50514 +#define EPFLUSH_TX_OFFSET 0x00010000
50515 +#define EPFLUSH_RX_OFFSET 0x00000000
50516 +
50517 +/* Endpoint Setup Status bit masks */
50518 +#define EP_SETUP_STATUS_MASK 0x0000003F
50519 +#define EP_SETUP_STATUS_EP0 0x00000001
50520 +
50521 +/* ENDPOINTCTRLx Register Bit Masks */
50522 +#define EPCTRL_TX_ENABLE 0x00800000
50523 +#define EPCTRL_TX_DATA_TOGGLE_RST 0x00400000 /* Not EP0 */
50524 +#define EPCTRL_TX_DATA_TOGGLE_INH 0x00200000 /* Not EP0 */
50525 +#define EPCTRL_TX_TYPE 0x000C0000
50526 +#define EPCTRL_TX_DATA_SOURCE 0x00020000 /* Not EP0 */
50527 +#define EPCTRL_TX_EP_STALL 0x00010000
50528 +#define EPCTRL_RX_ENABLE 0x00000080
50529 +#define EPCTRL_RX_DATA_TOGGLE_RST 0x00000040 /* Not EP0 */
50530 +#define EPCTRL_RX_DATA_TOGGLE_INH 0x00000020 /* Not EP0 */
50531 +#define EPCTRL_RX_TYPE 0x0000000C
50532 +#define EPCTRL_RX_DATA_SINK 0x00000002 /* Not EP0 */
50533 +#define EPCTRL_RX_EP_STALL 0x00000001
50534 +
50535 +/* bit 19-18 and 3-2 are endpoint type */
50536 +#define EPCTRL_EP_TYPE_CONTROL 0
50537 +#define EPCTRL_EP_TYPE_ISO 1
50538 +#define EPCTRL_EP_TYPE_BULK 2
50539 +#define EPCTRL_EP_TYPE_INTERRUPT 3
50540 +#define EPCTRL_TX_EP_TYPE_SHIFT 18
50541 +#define EPCTRL_RX_EP_TYPE_SHIFT 2
50542 +
50543 +/* SNOOPn Register Bit Masks */
50544 +#define SNOOP_ADDRESS_MASK 0xFFFFF000
50545 +#define SNOOP_SIZE_ZERO 0x00 /* snooping disable */
50546 +#define SNOOP_SIZE_4KB 0x0B /* 4KB snoop size */
50547 +#define SNOOP_SIZE_8KB 0x0C
50548 +#define SNOOP_SIZE_16KB 0x0D
50549 +#define SNOOP_SIZE_32KB 0x0E
50550 +#define SNOOP_SIZE_64KB 0x0F
50551 +#define SNOOP_SIZE_128KB 0x10
50552 +#define SNOOP_SIZE_256KB 0x11
50553 +#define SNOOP_SIZE_512KB 0x12
50554 +#define SNOOP_SIZE_1MB 0x13
50555 +#define SNOOP_SIZE_2MB 0x14
50556 +#define SNOOP_SIZE_4MB 0x15
50557 +#define SNOOP_SIZE_8MB 0x16
50558 +#define SNOOP_SIZE_16MB 0x17
50559 +#define SNOOP_SIZE_32MB 0x18
50560 +#define SNOOP_SIZE_64MB 0x19
50561 +#define SNOOP_SIZE_128MB 0x1A
50562 +#define SNOOP_SIZE_256MB 0x1B
50563 +#define SNOOP_SIZE_512MB 0x1C
50564 +#define SNOOP_SIZE_1GB 0x1D
50565 +#define SNOOP_SIZE_2GB 0x1E /* 2GB snoop size */
50566 +
50567 +/* pri_ctrl Register Bit Masks */
50568 +#define PRI_CTRL_PRI_LVL1 0x0000000C
50569 +#define PRI_CTRL_PRI_LVL0 0x00000003
50570 +
50571 +/* si_ctrl Register Bit Masks */
50572 +#define SI_CTRL_ERR_DISABLE 0x00000010
50573 +#define SI_CTRL_IDRC_DISABLE 0x00000008
50574 +#define SI_CTRL_RD_SAFE_EN 0x00000004
50575 +#define SI_CTRL_RD_PREFETCH_DISABLE 0x00000002
50576 +#define SI_CTRL_RD_PREFEFETCH_VAL 0x00000001
50577 +
50578 +
50579 +/* control Register Bit Masks */
50580 +#define USB_CTRL_IOENB 0x00000004
50581 +#define USB_CTRL_ULPI_INT0EN 0x00000001
50582 +
50583 +
50584 +/* Endpoint Transfer Descriptor bit Masks */
50585 +#define DTD_NEXT_TERMINATE 0x00000001
50586 +#define DTD_IOC 0x00008000
50587 +#define DTD_STATUS_ACTIVE 0x00000080
50588 +#define DTD_STATUS_HALTED 0x00000040
50589 +#define DTD_STATUS_DATA_BUFF_ERR 0x00000020
50590 +#define DTD_STATUS_TRANSACTION_ERR 0x00000008
50591 +#define DTD_RESERVED_FIELDS 0x80007300
50592 +#define DTD_ADDR_MASK 0xFFFFFFE0
50593 +#define DTD_PACKET_SIZE 0x7FFF0000
50594 +#define DTD_LENGTH_BIT_POS 16
50595 +#define DTD_ERROR_MASK (DTD_STATUS_HALTED | \
50596 + DTD_STATUS_DATA_BUFF_ERR | \
50597 + DTD_STATUS_TRANSACTION_ERR)
50598 +/* Alignment requirements; must be a power of two */
50599 +#define DTD_ALIGNMENT 0x20
50600 +#define QH_ALIGNMENT 2048
50601 +
50602 +/* Controller dma boundary */
50603 +#define UDC_DMA_BOUNDARY 0x1000
50604 +
50605 +#if defined CONFIG_PPC32
50606 +#define fsl_readl(addr) in_le32((addr))
50607 +#define fsl_writel(addr, val32) out_le32((addr), (val32))
50608 +#elif defined CONFIG_COLDFIRE
50609 +#define fsl_readl(addr) in_be32((__force unsigned *)(addr))
50610 +#define fsl_writel(val32, addr) out_be32((__force unsigned *)(addr), (val32))
50611 +
50612 +#define fsl_readw(addr) in_be16((__force unsigned *)(addr))
50613 +#define fsl_writew(val16, addr) out_be16((__force unsigned *)(addr), (val16))
50614 +#else
50615 +#error fsl_{readl, writel} must be defined
50616 +#endif
50617 +
50618 +#endif /* __FSL_USB2_H */
50619 --- /dev/null
50620 +++ b/include/linux/usb/fsl_xcvr.h
50621 @@ -0,0 +1,42 @@
50622 +/*
50623 + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
50624 + */
50625 +
50626 +/*
50627 + * The code contained herein is licensed under the GNU General Public
50628 + * License. You may obtain a copy of the GNU General Public License
50629 + * Version 2 or later at the following locations:
50630 + *
50631 + * http://www.opensource.org/licenses/gpl-license.html
50632 + * http://www.gnu.org/copyleft/gpl.html
50633 + */
50634 +
50635 +enum fsl_usb_ctrlr {
50636 + USB_CTRLR_H1 = 0,
50637 + USB_CTRLR_H2 = 1,
50638 + USB_CTRLR_OTG = 2,
50639 +};
50640 +
50641 +
50642 +/**
50643 + * struct fsl_xcvr_ops - USB transceiver operations
50644 + *
50645 + * @xcvr_type: one of PORTSCX_PTS_{UTMI,SERIAL,ULPI}
50646 + * @init: transceiver- and board-specific initialization function
50647 + * @uninit: transceiver- and board-specific uninitialization function
50648 + * @set_host:
50649 + * @set_device:
50650 + *
50651 + */
50652 +struct fsl_xcvr_ops {
50653 + enum fsl_usb_ctrlr ctrlr; /* H1, H2, OTG */
50654 + u32 xcvr_type;
50655 +
50656 + void (*init)(struct platform_device *pdev);
50657 + void (*uninit)(struct platform_device *pdev);
50658 + void (*set_host)(void); /* DDD combine set_host and _device ? */
50659 + void (*set_device)(void);
50660 + void (*set_vbus_power)(struct fsl_usb2_platform_data *pdata, int on);
50661 +};
50662 +
50663 +
50664 --- /dev/null
50665 +++ b/net/can/dev.c
50666 @@ -0,0 +1,292 @@
50667 +/*
50668 + * $Id$
50669 + *
50670 + * Copyright (C) 2005 Marc Kleine-Budde, Pengutronix
50671 + * Copyright (C) 2006 Andrey Volkov, Varma Electronics
50672 + *
50673 + * This program is free software; you can redistribute it and/or modify
50674 + * it under the terms of the version 2 of the GNU General Public License
50675 + * as published by the Free Software Foundation
50676 + *
50677 + * This program is distributed in the hope that it will be useful,
50678 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
50679 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
50680 + * GNU General Public License for more details.
50681 + *
50682 + * You should have received a copy of the GNU General Public License
50683 + * along with this program; if not, write to the Free Software
50684 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
50685 + */
50686 +
50687 +#include <linux/module.h>
50688 +#include <linux/netdevice.h>
50689 +#include <linux/if_arp.h>
50690 +#include <linux/can.h>
50691 +#include <linux/can/dev.h>
50692 +
50693 +MODULE_DESCRIPTION("CAN netdevice library");
50694 +MODULE_LICENSE("GPL v2");
50695 +MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>, "
50696 + "Andrey Volkov <avolkov@varma-el.com>");
50697 +
50698 +/*
50699 + Abstract:
50700 + Baud rate calculated with next formula:
50701 + baud = frq/(brp*(1 + prop_seg+ phase_seg1 + phase_seg2))
50702 +
50703 + This calc function based on work of Florian Hartwich and Armin Bassemi
50704 + "The Configuration of the CAN Bit Timing"
50705 + (http://www.semiconductors.bosch.de/pdf/CiA99Paper.pdf)
50706 +
50707 + Parameters:
50708 + [in]
50709 + bit_time_nsec - expected bit time in nanosecs
50710 +
50711 + [out]
50712 + bit_time - calculated time segments, for meaning of
50713 + each field read CAN standard.
50714 +*/
50715 +
50716 +#define DEFAULT_MAX_BRP 64U
50717 +#define DEFAULT_MAX_SJW 4U
50718 +
50719 +/* All below values in tq units */
50720 +#define MAX_BIT_TIME 25U
50721 +#define MIN_BIT_TIME 8U
50722 +#define MAX_PROP_SEG 8U
50723 +#define MAX_PHASE_SEG1 8U
50724 +#define MAX_PHASE_SEG2 8U
50725 +
50726 +int can_calc_bit_time(struct can_priv *can, u32 baudrate,
50727 + struct can_bittime_std *bit_time)
50728 +{
50729 + int best_error = -1; /* Ariphmetic error */
50730 + int df, best_df = -1; /* oscillator's tolerance range */
50731 + u32 quanta; /*in tq units*/
50732 + u32 brp, phase_seg1, phase_seg2, sjw, prop_seg;
50733 + u32 brp_min, brp_max, brp_expected;
50734 + u64 tmp;
50735 +
50736 + /* baudrate range [1baud,1Mbaud] */
50737 + if (baudrate == 0 || baudrate > 1000000UL)
50738 + return -EINVAL;
50739 +
50740 + tmp = (u64)can->can_sys_clock*1000;
50741 + do_div(tmp, baudrate);
50742 + brp_expected = (u32)tmp;
50743 +
50744 + brp_min = brp_expected / (1000 * MAX_BIT_TIME);
50745 + if (brp_min == 0)
50746 + brp_min = 1;
50747 + if (brp_min > can->max_brp)
50748 + return -ERANGE;
50749 +
50750 + brp_max = (brp_expected + 500 * MIN_BIT_TIME) / (1000 * MIN_BIT_TIME);
50751 + if (brp_max == 0)
50752 + brp_max = 1;
50753 + if (brp_max > can->max_brp)
50754 + brp_max = can->max_brp;
50755 +
50756 + for (brp = brp_min; brp <= brp_max; brp++) {
50757 + quanta = brp_expected / (brp * 1000);
50758 + if (quanta < MAX_BIT_TIME && quanta * brp * 1000 !=
50759 + brp_expected)
50760 + quanta++;
50761 + if (quanta < MIN_BIT_TIME || quanta > MAX_BIT_TIME)
50762 + continue;
50763 +
50764 + phase_seg2 = min((quanta - 3) / 2, MAX_PHASE_SEG2);
50765 + for (sjw = can->max_sjw; sjw > 0; sjw--) {
50766 + for (; phase_seg2 > sjw; phase_seg2--) {
50767 + u32 err1, err2;
50768 + phase_seg1 = phase_seg2 % 2 ?
50769 + phase_seg2-1 : phase_seg2;
50770 + prop_seg = quanta-1 - phase_seg2 - phase_seg1;
50771 + /*
50772 + * FIXME: support of longer lines
50773 + * (i.e. bigger prop_seg) is more prefered
50774 + * than support of cheap oscillators
50775 + * (i.e. bigger df/phase_seg1/phase_seg2)
50776 + * */
50777 +
50778 + if (prop_seg < phase_seg1)
50779 + continue;
50780 + if (prop_seg > MAX_PROP_SEG)
50781 + goto next_brp;
50782 +
50783 + err1 = phase_seg1 * brp * 500 * 1000 /
50784 + (13 * brp_expected - phase_seg2 *
50785 + brp * 1000);
50786 + err2 = sjw * brp * 50 * 1000 / brp_expected;
50787 +
50788 + df = min(err1, err2);
50789 + if (df >= best_df) {
50790 + unsigned error = abs(brp_expected * 10 /
50791 + (brp * (1 + prop_seg +
50792 + phase_seg1 +
50793 + phase_seg2)) - 10000);
50794 +
50795 + if (error > 10 || error > best_error)
50796 + continue;
50797 +
50798 + if (error == best_error && prop_seg <
50799 + bit_time->prop_seg)
50800 + continue;
50801 +
50802 + best_error = error;
50803 + best_df = df;
50804 + bit_time->brp = brp;
50805 + bit_time->prop_seg = prop_seg;
50806 + bit_time->phase_seg1 = phase_seg1;
50807 + bit_time->phase_seg2 = phase_seg2;
50808 + bit_time->sjw = sjw;
50809 + bit_time->sam =
50810 + (bit_time->phase_seg1 > 3);
50811 + }
50812 + }
50813 + }
50814 +next_brp: ;
50815 + }
50816 +
50817 + if (best_error < 0)
50818 + return -EDOM;
50819 + return 0;
50820 +}
50821 +EXPORT_SYMBOL(can_calc_bit_time);
50822 +
50823 +static int can_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
50824 +{
50825 + struct can_priv *can = netdev_priv(dev);
50826 + struct can_bittime *bt = (struct can_bittime *)&ifr->ifr_ifru;
50827 + ulong *baudrate = (ulong *)&ifr->ifr_ifru;
50828 + int ret = -EOPNOTSUPP;
50829 +
50830 + dev_dbg(ND2D(dev), "(%s) 0x%08x %p\n", __func__, cmd, &ifr->ifr_ifru);
50831 +
50832 + switch (cmd) {
50833 + case SIOCSCANBAUDRATE:
50834 + if (can->do_set_bit_time) {
50835 + struct can_bittime bit_time;
50836 + ret = can_calc_bit_time(can, *baudrate, &bit_time.std);
50837 + if (ret != 0)
50838 + break;
50839 + bit_time.type = CAN_BITTIME_STD;
50840 + ret = can->do_set_bit_time(dev, &bit_time);
50841 + if (!ret) {
50842 + can->baudrate = *baudrate;
50843 + can->bit_time = bit_time;
50844 + }
50845 + }
50846 + break;
50847 + case SIOCGCANBAUDRATE:
50848 + *baudrate = can->baudrate;
50849 + ret = 0;
50850 + break;
50851 + case SIOCSCANCUSTOMBITTIME:
50852 + if (can->do_set_bit_time) {
50853 + ret = can->do_set_bit_time(dev, bt);
50854 + if (!ret) {
50855 + can->bit_time = *bt;
50856 + if (bt->type == CAN_BITTIME_STD && bt->std.brp) {
50857 + can->baudrate = can->can_sys_clock /
50858 + (bt->std.brp * (1 + bt->std.prop_seg +
50859 + bt->std.phase_seg1 +
50860 + bt->std.phase_seg2));
50861 + } else
50862 + can->baudrate = CAN_BAUDRATE_UNKNOWN;
50863 + }
50864 + }
50865 + break;
50866 + case SIOCGCANCUSTOMBITTIME:
50867 + *bt = can->bit_time;
50868 + ret = 0;
50869 + break;
50870 + case SIOCSCANMODE:
50871 + if (can->do_set_mode) {
50872 + can_mode_t mode =
50873 + *((can_mode_t *)(&ifr->ifr_ifru));
50874 + if (mode == CAN_MODE_START &&
50875 + can->baudrate == CAN_BAUDRATE_UNCONFIGURED) {
50876 + dev_info(ND2D(dev), "Impossible to start \
50877 + on UNKNOWN speed\n");
50878 + ret = EINVAL;
50879 + } else
50880 + return can->do_set_mode(dev, mode);
50881 + }
50882 + break;
50883 + case SIOCGCANMODE:
50884 + *((can_mode_t *)(&ifr->ifr_ifru)) = can->mode;
50885 + ret = 0;
50886 + break;
50887 + case SIOCSCANCTRLMODE:
50888 + if (can->do_set_ctrlmode) {
50889 + can_ctrlmode_t ctrlmode =
50890 + *((can_ctrlmode_t *)(&ifr->ifr_ifru));
50891 + return can->do_set_ctrlmode(dev, ctrlmode);
50892 + }
50893 + break;
50894 + case SIOCGCANCTRLMODE:
50895 + *((can_ctrlmode_t *)(&ifr->ifr_ifru)) = can->ctrlmode;
50896 + ret = 0;
50897 + break;
50898 + case SIOCSCANFILTER:
50899 + break;
50900 + case SIOCGCANFILTER:
50901 + break;
50902 + case SIOCGCANSTATE:
50903 + if (can->do_get_state)
50904 + return can->do_get_state(dev,
50905 + (can_state_t *)(&ifr->ifr_ifru));
50906 + break;
50907 + case SIOCGCANSTATS:
50908 + *((struct can_device_stats *)(&ifr->ifr_ifru)) = can->can_stats;
50909 + ret = 0;
50910 + break;
50911 + }
50912 +
50913 + return ret;
50914 +}
50915 +
50916 +static void can_setup(struct net_device *dev)
50917 +{
50918 + dev->type = ARPHRD_CAN;
50919 + dev->mtu = sizeof(struct can_frame);
50920 + dev->do_ioctl = can_ioctl;
50921 + dev->hard_header_len = 0;
50922 + dev->addr_len = 0;
50923 + dev->tx_queue_len = 10;
50924 +
50925 + /* New-style flags. */
50926 + dev->flags = IFF_NOARP;
50927 + dev->features = NETIF_F_NO_CSUM;
50928 +}
50929 +
50930 +/*
50931 + * Function alloc_candev
50932 + * Allocates and sets up an CAN device
50933 + */
50934 +struct net_device *alloc_candev(int sizeof_priv)
50935 +{
50936 + struct net_device *dev;
50937 + struct can_priv *priv;
50938 +
50939 + dev = alloc_netdev(sizeof_priv, "can%d", can_setup);
50940 + if (!dev)
50941 + return NULL;
50942 +
50943 + priv = netdev_priv(dev);
50944 +
50945 + priv->baudrate = CAN_BAUDRATE_UNCONFIGURED;
50946 + priv->max_brp = DEFAULT_MAX_BRP;
50947 + priv->max_sjw = DEFAULT_MAX_SJW;
50948 + spin_lock_init(&priv->irq_lock);
50949 +
50950 + return dev;
50951 +}
50952 +EXPORT_SYMBOL(alloc_candev);
50953 +
50954 +void free_candev(struct net_device *dev)
50955 +{
50956 + free_netdev(dev);
50957 +}
50958 +EXPORT_SYMBOL(free_candev);
50959 --- a/net/can/Makefile
50960 +++ b/net/can/Makefile
50961 @@ -10,3 +10,6 @@ can-raw-objs := raw.o
50962
50963 obj-$(CONFIG_CAN_BCM) += can-bcm.o
50964 can-bcm-objs := bcm.o
50965 +
50966 +obj-$(CONFIG_CAN) += candev.o
50967 +candev-objs := dev.o
50968 --- a/net/irda/irlap.c
50969 +++ b/net/irda/irlap.c
50970 @@ -627,7 +627,7 @@ void irlap_status_indication(struct irla
50971 {
50972 switch (quality_of_link) {
50973 case STATUS_NO_ACTIVITY:
50974 - IRDA_MESSAGE("IrLAP, no activity on link!\n");
50975 + /* IRDA_MESSAGE("IrLAP, no activity on link!\n"); */
50976 break;
50977 case STATUS_NOISY:
50978 IRDA_MESSAGE("IrLAP, noisy link!\n");
50979 --- /dev/null
50980 +++ b/scripts/checkfiles
50981 @@ -0,0 +1,35 @@
50982 +#!/bin/sh
50983 +# (c) 2007, Erez Zadok <ezk@cs.sunysb.edu> (initial version)
50984 +# Licensed under the terms of the GNU GPL License version 2
50985 +#
50986 +# Check source files for compliance with coding standards, using terse
50987 +# output in the style that g/cc produces. This output can be easily parsed
50988 +# within text editors (e.g., emacs/vim) which can produce a split text
50989 +# screen showing in one screen the error message, and in another screen the
50990 +# corresponding source file, with the cursor placed on the offending line.
50991 +# See for example the documentation for Emacs's "next-error" command, often
50992 +# bound to M-x ` (ESC x back-tick).
50993 +
50994 +# Usage: checkfiles file [files...]
50995 +# if "file" is a directory, will check all *.[hc] files recursively
50996 +
50997 +# check usage
50998 +usage() {
50999 + echo "Usage: checkfiles file [files...]"
51000 + echo "(if \"file\" is a directory, check recursively for all C sources/headers)"
51001 + exit 1
51002 +}
51003 +
51004 +# if test -z "$@" ; then
51005 +# usage
51006 +# fi
51007 +if ! test -f scripts/checkpatch.pl ; then
51008 + echo "checkfiles: must run from top level source tree"
51009 + exit 1
51010 +fi
51011 +
51012 +# check coding-style compliance of each source file found
51013 +find "$@" -type f -name '*.[hc]' | \
51014 +while read f ; do
51015 + diff -u /dev/null $f | perl scripts/checkpatch.pl -
51016 +done
51017 --- /dev/null
51018 +++ b/scripts/checkfilesterse
51019 @@ -0,0 +1,34 @@
51020 +#!/bin/sh
51021 +# (c) 2007, Erez Zadok <ezk@cs.sunysb.edu> (initial version)
51022 +# Licensed under the terms of the GNU GPL License version 2
51023 +#
51024 +# Check source files for compliance with coding standards, using terse
51025 +# output in the style that g/cc produces. This output can be easily parsed
51026 +# within text editors (e.g., emacs/vim) which can produce a split text
51027 +# screen showing in one screen the error message, and in another screen the
51028 +# corresponding source file, with the cursor placed on the offending line.
51029 +# See for example the documentation for Emacs's "next-error" command, often
51030 +# bound to M-x ` (ESC x back-tick).
51031 +
51032 +# Usage: checkfiles file [files...]
51033 +# if "file" is a directory, will check all *.[hc] files recursively
51034 +
51035 +# check usage
51036 +usage() {
51037 + echo "Usage: checkfiles file [files...]"
51038 + echo "(if \"file\" is a directory, check recursively for all C sources/headers)"
51039 + exit 1
51040 +}
51041 +if test -z "" ; then
51042 + usage
51043 +fi
51044 +if ! test -f scripts/checkpatch.pl ; then
51045 + echo "checkfiles: must run from top level source tree"
51046 + exit 1
51047 +fi
51048 +
51049 +# check coding-style compliance of each source file found, using terse output
51050 +find "$@" -type f -name '*.[hc]' | \
51051 +while read f ; do
51052 + diff -u /dev/null $f | perl scripts/checkpatch.pl -t -
51053 +done
OpenWrt Source Repository