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gemini: drop Linux 4.1 support
[openwrt/openwrt.git] / target / linux / gemini / files / drivers / net / ethernet / gemini / sl351x_hw.h
1 /*
2 * Register definitions for Gemini LEPUS GMAC Ethernet device driver.
3 *
4 * Copyright (C) 2006, Storlink, Corp.
5 * Copyright (C) 2008-2009, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 * Copyright (C) 2010, Michał Mirosław <mirq-linux@rere.qmqm.pl>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13 #ifndef _GMAC_HW_H
14 #define _GMAC_HW_H
15
16 #include <linux/bitops.h>
17
18 /*
19 * Base Registers
20 */
21 #define TOE_NONTOE_QUE_HDR_BASE 0x2000
22 #define TOE_TOE_QUE_HDR_BASE 0x3000
23 #define TOE_V_BIT_BASE 0x4000
24 #define TOE_A_BIT_BASE 0x6000
25 #define TOE_GMAC_DMA_BASE(x) (0x8000 + 0x4000 * (x))
26 #define TOE_GMAC_BASE(x) (0xA000 + 0x4000 * (x))
27
28 /*
29 * Queue ID
30 */
31 #define TOE_SW_FREE_QID 0x00
32 #define TOE_HW_FREE_QID 0x01
33 #define TOE_GMAC0_SW_TXQ0_QID 0x02
34 #define TOE_GMAC0_SW_TXQ1_QID 0x03
35 #define TOE_GMAC0_SW_TXQ2_QID 0x04
36 #define TOE_GMAC0_SW_TXQ3_QID 0x05
37 #define TOE_GMAC0_SW_TXQ4_QID 0x06
38 #define TOE_GMAC0_SW_TXQ5_QID 0x07
39 #define TOE_GMAC0_HW_TXQ0_QID 0x08
40 #define TOE_GMAC0_HW_TXQ1_QID 0x09
41 #define TOE_GMAC0_HW_TXQ2_QID 0x0A
42 #define TOE_GMAC0_HW_TXQ3_QID 0x0B
43 #define TOE_GMAC1_SW_TXQ0_QID 0x12
44 #define TOE_GMAC1_SW_TXQ1_QID 0x13
45 #define TOE_GMAC1_SW_TXQ2_QID 0x14
46 #define TOE_GMAC1_SW_TXQ3_QID 0x15
47 #define TOE_GMAC1_SW_TXQ4_QID 0x16
48 #define TOE_GMAC1_SW_TXQ5_QID 0x17
49 #define TOE_GMAC1_HW_TXQ0_QID 0x18
50 #define TOE_GMAC1_HW_TXQ1_QID 0x19
51 #define TOE_GMAC1_HW_TXQ2_QID 0x1A
52 #define TOE_GMAC1_HW_TXQ3_QID 0x1B
53 #define TOE_GMAC0_DEFAULT_QID 0x20
54 #define TOE_GMAC1_DEFAULT_QID 0x21
55 #define TOE_CLASSIFICATION_QID(x) (0x22 + x) /* 0x22 ~ 0x2F */
56 #define TOE_TOE_QID(x) (0x40 + x) /* 0x40 ~ 0x7F */
57
58 /*
59 * old info:
60 * TOE DMA Queue Size should be 2^n, n = 6...12
61 * TOE DMA Queues are the following queue types:
62 * SW Free Queue, HW Free Queue,
63 * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
64 * The base address and descriptor number are configured at
65 * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
66 */
67
68 #define GET_WPTR(addr) __raw_readw((addr) + 2)
69 #define GET_RPTR(addr) __raw_readw((addr))
70 #define SET_WPTR(addr, data) __raw_writew((data), (addr) + 2)
71 #define SET_RPTR(addr, data) __raw_writew((data), (addr))
72 #define __RWPTR_NEXT(x, mask) (((unsigned int)(x) + 1) & (mask))
73 #define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask))
74 #define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask))
75 #define __RWPTR_MASK(order) ((1 << (order)) - 1)
76 #define RWPTR_NEXT(x, order) __RWPTR_NEXT((x), __RWPTR_MASK((order)))
77 #define RWPTR_PREV(x, order) __RWPTR_PREV((x), __RWPTR_MASK((order)))
78 #define RWPTR_DISTANCE(r, w, order) __RWPTR_DISTANCE((r), (w), \
79 __RWPTR_MASK((order)))
80
81 /*
82 * Global registers
83 * #define TOE_GLOBAL_BASE (TOE_BASE + 0x0000)
84 * Base 0x60000000
85 */
86 #define GLOBAL_TOE_VERSION_REG 0x0000
87 #define GLOBAL_SW_FREEQ_BASE_SIZE_REG 0x0004
88 #define GLOBAL_HW_FREEQ_BASE_SIZE_REG 0x0008
89 #define GLOBAL_DMA_SKB_SIZE_REG 0x0010
90 #define GLOBAL_SWFQ_RWPTR_REG 0x0014
91 #define GLOBAL_HWFQ_RWPTR_REG 0x0018
92 #define GLOBAL_INTERRUPT_STATUS_0_REG 0x0020
93 #define GLOBAL_INTERRUPT_ENABLE_0_REG 0x0024
94 #define GLOBAL_INTERRUPT_SELECT_0_REG 0x0028
95 #define GLOBAL_INTERRUPT_STATUS_1_REG 0x0030
96 #define GLOBAL_INTERRUPT_ENABLE_1_REG 0x0034
97 #define GLOBAL_INTERRUPT_SELECT_1_REG 0x0038
98 #define GLOBAL_INTERRUPT_STATUS_2_REG 0x0040
99 #define GLOBAL_INTERRUPT_ENABLE_2_REG 0x0044
100 #define GLOBAL_INTERRUPT_SELECT_2_REG 0x0048
101 #define GLOBAL_INTERRUPT_STATUS_3_REG 0x0050
102 #define GLOBAL_INTERRUPT_ENABLE_3_REG 0x0054
103 #define GLOBAL_INTERRUPT_SELECT_3_REG 0x0058
104 #define GLOBAL_INTERRUPT_STATUS_4_REG 0x0060
105 #define GLOBAL_INTERRUPT_ENABLE_4_REG 0x0064
106 #define GLOBAL_INTERRUPT_SELECT_4_REG 0x0068
107 #define GLOBAL_HASH_TABLE_BASE_REG 0x006C
108 #define GLOBAL_QUEUE_THRESHOLD_REG 0x0070
109
110 /*
111 * GMAC 0/1 DMA/TOE register
112 * #define TOE_GMAC0_DMA_BASE (TOE_BASE + 0x8000)
113 * #define TOE_GMAC1_DMA_BASE (TOE_BASE + 0xC000)
114 * Base 0x60008000 or 0x6000C000
115 */
116 #define GMAC_DMA_CTRL_REG 0x0000
117 #define GMAC_TX_WEIGHTING_CTRL_0_REG 0x0004
118 #define GMAC_TX_WEIGHTING_CTRL_1_REG 0x0008
119 #define GMAC_SW_TX_QUEUE0_PTR_REG 0x000C
120 #define GMAC_SW_TX_QUEUE1_PTR_REG 0x0010
121 #define GMAC_SW_TX_QUEUE2_PTR_REG 0x0014
122 #define GMAC_SW_TX_QUEUE3_PTR_REG 0x0018
123 #define GMAC_SW_TX_QUEUE4_PTR_REG 0x001C
124 #define GMAC_SW_TX_QUEUE5_PTR_REG 0x0020
125 #define GMAC_SW_TX_QUEUE_PTR_REG(i) (GMAC_SW_TX_QUEUE0_PTR_REG + 4 * (i))
126 #define GMAC_HW_TX_QUEUE0_PTR_REG 0x0024
127 #define GMAC_HW_TX_QUEUE1_PTR_REG 0x0028
128 #define GMAC_HW_TX_QUEUE2_PTR_REG 0x002C
129 #define GMAC_HW_TX_QUEUE3_PTR_REG 0x0030
130 #define GMAC_HW_TX_QUEUE_PTR_REG(i) (GMAC_HW_TX_QUEUE0_PTR_REG + 4 * (i))
131 #define GMAC_DMA_TX_FIRST_DESC_REG 0x0038
132 #define GMAC_DMA_TX_CURR_DESC_REG 0x003C
133 #define GMAC_DMA_TX_DESC_WORD0_REG 0x0040
134 #define GMAC_DMA_TX_DESC_WORD1_REG 0x0044
135 #define GMAC_DMA_TX_DESC_WORD2_REG 0x0048
136 #define GMAC_DMA_TX_DESC_WORD3_REG 0x004C
137 #define GMAC_SW_TX_QUEUE_BASE_REG 0x0050
138 #define GMAC_HW_TX_QUEUE_BASE_REG 0x0054
139 #define GMAC_DMA_RX_FIRST_DESC_REG 0x0058
140 #define GMAC_DMA_RX_CURR_DESC_REG 0x005C
141 #define GMAC_DMA_RX_DESC_WORD0_REG 0x0060
142 #define GMAC_DMA_RX_DESC_WORD1_REG 0x0064
143 #define GMAC_DMA_RX_DESC_WORD2_REG 0x0068
144 #define GMAC_DMA_RX_DESC_WORD3_REG 0x006C
145 #define GMAC_HASH_ENGINE_REG0 0x0070
146 #define GMAC_HASH_ENGINE_REG1 0x0074
147 /* matching rule 0 Control register 0 */
148 #define GMAC_MR0CR0 0x0078
149 #define GMAC_MR0CR1 0x007C
150 #define GMAC_MR0CR2 0x0080
151 #define GMAC_MR1CR0 0x0084
152 #define GMAC_MR1CR1 0x0088
153 #define GMAC_MR1CR2 0x008C
154 #define GMAC_MR2CR0 0x0090
155 #define GMAC_MR2CR1 0x0094
156 #define GMAC_MR2CR2 0x0098
157 #define GMAC_MR3CR0 0x009C
158 #define GMAC_MR3CR1 0x00A0
159 #define GMAC_MR3CR2 0x00A4
160 /* Support Protocol Regsister 0 */
161 #define GMAC_SPR0 0x00A8
162 #define GMAC_SPR1 0x00AC
163 #define GMAC_SPR2 0x00B0
164 #define GMAC_SPR3 0x00B4
165 #define GMAC_SPR4 0x00B8
166 #define GMAC_SPR5 0x00BC
167 #define GMAC_SPR6 0x00C0
168 #define GMAC_SPR7 0x00C4
169 /* GMAC Hash/Rx/Tx AHB Weighting register */
170 #define GMAC_AHB_WEIGHT_REG 0x00C8
171
172 /*
173 * TOE GMAC 0/1 register
174 * #define TOE_GMAC0_BASE (TOE_BASE + 0xA000)
175 * #define TOE_GMAC1_BASE (TOE_BASE + 0xE000)
176 * Base 0x6000A000 or 0x6000E000
177 */
178 enum GMAC_REGISTER {
179 GMAC_STA_ADD0 = 0x0000,
180 GMAC_STA_ADD1 = 0x0004,
181 GMAC_STA_ADD2 = 0x0008,
182 GMAC_RX_FLTR = 0x000c,
183 GMAC_MCAST_FIL0 = 0x0010,
184 GMAC_MCAST_FIL1 = 0x0014,
185 GMAC_CONFIG0 = 0x0018,
186 GMAC_CONFIG1 = 0x001c,
187 GMAC_CONFIG2 = 0x0020,
188 GMAC_CONFIG3 = 0x0024,
189 GMAC_RESERVED = 0x0028,
190 GMAC_STATUS = 0x002c,
191 GMAC_IN_DISCARDS= 0x0030,
192 GMAC_IN_ERRORS = 0x0034,
193 GMAC_IN_MCAST = 0x0038,
194 GMAC_IN_BCAST = 0x003c,
195 GMAC_IN_MAC1 = 0x0040, /* for STA 1 MAC Address */
196 GMAC_IN_MAC2 = 0x0044 /* for STA 2 MAC Address */
197 };
198
199 #define RX_STATS_NUM 6
200
201 /*
202 * DMA Queues description Ring Base Address/Size Register (offset 0x0004)
203 */
204 typedef union {
205 unsigned int bits32;
206 unsigned int base_size;
207 } DMA_Q_BASE_SIZE_T;
208 #define DMA_Q_BASE_MASK (~0x0f)
209
210 /*
211 * DMA SKB Buffer register (offset 0x0008)
212 */
213 typedef union {
214 unsigned int bits32;
215 struct bit_0008 {
216 unsigned int sw_skb_size : 16; /* SW Free poll SKB Size */
217 unsigned int hw_skb_size : 16; /* HW Free poll SKB Size */
218 } bits;
219 } DMA_SKB_SIZE_T;
220
221 /*
222 * DMA SW Free Queue Read/Write Pointer Register (offset 0x000C)
223 */
224 typedef union {
225 unsigned int bits32;
226 struct bit_000c {
227 unsigned int rptr : 16; /* Read Ptr, RO */
228 unsigned int wptr : 16; /* Write Ptr, RW */
229 } bits;
230 } DMA_RWPTR_T;
231
232 /*
233 * DMA HW Free Queue Read/Write Pointer Register (offset 0x0010)
234 * see DMA_RWPTR_T structure
235 */
236
237 /*
238 * Interrupt Status Register 0 (offset 0x0020)
239 * Interrupt Mask Register 0 (offset 0x0024)
240 * Interrupt Select Register 0 (offset 0x0028)
241 */
242 typedef union {
243 unsigned int bits32;
244 struct bit_0020 {
245 /* GMAC0 SW Tx Queue 0 EOF Interrupt */
246 unsigned int swtq00_eof : 1;
247 unsigned int swtq01_eof : 1;
248 unsigned int swtq02_eof : 1;
249 unsigned int swtq03_eof : 1;
250 unsigned int swtq04_eof : 1;
251 unsigned int swtq05_eof : 1;
252 /* GMAC1 SW Tx Queue 0 EOF Interrupt */
253 unsigned int swtq10_eof : 1;
254 unsigned int swtq11_eof : 1;
255 unsigned int swtq12_eof : 1;
256 unsigned int swtq13_eof : 1;
257 unsigned int swtq14_eof : 1;
258 unsigned int swtq15_eof : 1;
259 /* GMAC0 SW Tx Queue 0 Finish Interrupt */
260 unsigned int swtq00_fin : 1;
261 unsigned int swtq01_fin : 1;
262 unsigned int swtq02_fin : 1;
263 unsigned int swtq03_fin : 1;
264 unsigned int swtq04_fin : 1;
265 unsigned int swtq05_fin : 1;
266 /* GMAC1 SW Tx Queue 0 Finish Interrupt */
267 unsigned int swtq10_fin : 1;
268 unsigned int swtq11_fin : 1;
269 unsigned int swtq12_fin : 1;
270 unsigned int swtq13_fin : 1;
271 unsigned int swtq14_fin : 1;
272 unsigned int swtq15_fin : 1;
273 /* GMAC0 Rx Descriptor Protocol Error */
274 unsigned int rxPerr0 : 1;
275 /* GMAC0 AHB Bus Error while Rx */
276 unsigned int rxDerr0 : 1;
277 /* GMAC1 Rx Descriptor Protocol Error */
278 unsigned int rxPerr1 : 1;
279 /* GMAC1 AHB Bus Error while Rx */
280 unsigned int rxDerr1 : 1;
281 /* GMAC0 Tx Descriptor Protocol Error */
282 unsigned int txPerr0 : 1;
283 /* GMAC0 AHB Bus Error while Tx */
284 unsigned int txDerr0 : 1;
285 /* GMAC1 Tx Descriptor Protocol Error */
286 unsigned int txPerr1 : 1;
287 /* GMAC1 AHB Bus Error while Tx */
288 unsigned int txDerr1 : 1;
289 } bits;
290 } INTR_REG0_T;
291
292 #define GMAC1_TXDERR_INT_BIT BIT(31)
293 #define GMAC1_TXPERR_INT_BIT BIT(30)
294 #define GMAC0_TXDERR_INT_BIT BIT(29)
295 #define GMAC0_TXPERR_INT_BIT BIT(28)
296 #define GMAC1_RXDERR_INT_BIT BIT(27)
297 #define GMAC1_RXPERR_INT_BIT BIT(26)
298 #define GMAC0_RXDERR_INT_BIT BIT(25)
299 #define GMAC0_RXPERR_INT_BIT BIT(24)
300 #define GMAC1_SWTQ15_FIN_INT_BIT BIT(23)
301 #define GMAC1_SWTQ14_FIN_INT_BIT BIT(22)
302 #define GMAC1_SWTQ13_FIN_INT_BIT BIT(21)
303 #define GMAC1_SWTQ12_FIN_INT_BIT BIT(20)
304 #define GMAC1_SWTQ11_FIN_INT_BIT BIT(19)
305 #define GMAC1_SWTQ10_FIN_INT_BIT BIT(18)
306 #define GMAC0_SWTQ05_FIN_INT_BIT BIT(17)
307 #define GMAC0_SWTQ04_FIN_INT_BIT BIT(16)
308 #define GMAC0_SWTQ03_FIN_INT_BIT BIT(15)
309 #define GMAC0_SWTQ02_FIN_INT_BIT BIT(14)
310 #define GMAC0_SWTQ01_FIN_INT_BIT BIT(13)
311 #define GMAC0_SWTQ00_FIN_INT_BIT BIT(12)
312 #define GMAC1_SWTQ15_EOF_INT_BIT BIT(11)
313 #define GMAC1_SWTQ14_EOF_INT_BIT BIT(10)
314 #define GMAC1_SWTQ13_EOF_INT_BIT BIT(9)
315 #define GMAC1_SWTQ12_EOF_INT_BIT BIT(8)
316 #define GMAC1_SWTQ11_EOF_INT_BIT BIT(7)
317 #define GMAC1_SWTQ10_EOF_INT_BIT BIT(6)
318 #define GMAC0_SWTQ05_EOF_INT_BIT BIT(5)
319 #define GMAC0_SWTQ04_EOF_INT_BIT BIT(4)
320 #define GMAC0_SWTQ03_EOF_INT_BIT BIT(3)
321 #define GMAC0_SWTQ02_EOF_INT_BIT BIT(2)
322 #define GMAC0_SWTQ01_EOF_INT_BIT BIT(1)
323 #define GMAC0_SWTQ00_EOF_INT_BIT BIT(0)
324
325 /*
326 * Interrupt Status Register 1 (offset 0x0030)
327 * Interrupt Mask Register 1 (offset 0x0034)
328 * Interrupt Select Register 1 (offset 0x0038)
329 */
330 typedef union {
331 unsigned int bits32;
332 struct bit_0030 {
333 unsigned int default_q0_eof : 1; /* Default Queue 0 EOF Interrupt */
334 unsigned int default_q1_eof : 1; /* Default Queue 1 EOF Interrupt */
335 unsigned int class_rx : 14; /* Classification Queue Rx Interrupt */
336 unsigned int hwtq00_eof : 1; /* GMAC0 HW Tx Queue0 EOF Interrupt */
337 unsigned int hwtq01_eof : 1; /* GMAC0 HW Tx Queue1 EOF Interrupt */
338 unsigned int hwtq02_eof : 1; /* GMAC0 HW Tx Queue2 EOF Interrupt */
339 unsigned int hwtq03_eof : 1; /* GMAC0 HW Tx Queue3 EOF Interrupt */
340 unsigned int hwtq10_eof : 1; /* GMAC1 HW Tx Queue0 EOF Interrupt */
341 unsigned int hwtq11_eof : 1; /* GMAC1 HW Tx Queue1 EOF Interrupt */
342 unsigned int hwtq12_eof : 1; /* GMAC1 HW Tx Queue2 EOF Interrupt */
343 unsigned int hwtq13_eof : 1; /* GMAC1 HW Tx Queue3 EOF Interrupt */
344 unsigned int toe_iq0_intr : 1; /* TOE Interrupt Queue 0 with Interrupts */
345 unsigned int toe_iq1_intr : 1; /* TOE Interrupt Queue 1 with Interrupts */
346 unsigned int toe_iq2_intr : 1; /* TOE Interrupt Queue 2 with Interrupts */
347 unsigned int toe_iq3_intr : 1; /* TOE Interrupt Queue 3 with Interrupts */
348 unsigned int toe_iq0_full : 1; /* TOE Interrupt Queue 0 Full Interrupt */
349 unsigned int toe_iq1_full : 1; /* TOE Interrupt Queue 1 Full Interrupt */
350 unsigned int toe_iq2_full : 1; /* TOE Interrupt Queue 2 Full Interrupt */
351 unsigned int toe_iq3_full : 1; /* TOE Interrupt Queue 3 Full Interrupt */
352 } bits;
353 } INTR_REG1_T;
354
355 #define TOE_IQ3_FULL_INT_BIT BIT(31)
356 #define TOE_IQ2_FULL_INT_BIT BIT(30)
357 #define TOE_IQ1_FULL_INT_BIT BIT(29)
358 #define TOE_IQ0_FULL_INT_BIT BIT(28)
359 #define TOE_IQ3_INT_BIT BIT(27)
360 #define TOE_IQ2_INT_BIT BIT(26)
361 #define TOE_IQ1_INT_BIT BIT(25)
362 #define TOE_IQ0_INT_BIT BIT(24)
363 #define GMAC1_HWTQ13_EOF_INT_BIT BIT(23)
364 #define GMAC1_HWTQ12_EOF_INT_BIT BIT(22)
365 #define GMAC1_HWTQ11_EOF_INT_BIT BIT(21)
366 #define GMAC1_HWTQ10_EOF_INT_BIT BIT(20)
367 #define GMAC0_HWTQ03_EOF_INT_BIT BIT(19)
368 #define GMAC0_HWTQ02_EOF_INT_BIT BIT(18)
369 #define GMAC0_HWTQ01_EOF_INT_BIT BIT(17)
370 #define GMAC0_HWTQ00_EOF_INT_BIT BIT(16)
371 #define CLASS_RX_INT_BIT(x) BIT((x + 2))
372 #define DEFAULT_Q1_INT_BIT BIT(1)
373 #define DEFAULT_Q0_INT_BIT BIT(0)
374
375 #define TOE_IQ_INT_BITS (TOE_IQ0_INT_BIT | TOE_IQ1_INT_BIT | \
376 TOE_IQ2_INT_BIT | TOE_IQ3_INT_BIT)
377 #define TOE_IQ_FULL_BITS (TOE_IQ0_FULL_INT_BIT | TOE_IQ1_FULL_INT_BIT | \
378 TOE_IQ2_FULL_INT_BIT | TOE_IQ3_FULL_INT_BIT)
379 #define TOE_IQ_ALL_BITS (TOE_IQ_INT_BITS | TOE_IQ_FULL_BITS)
380 #define TOE_CLASS_RX_INT_BITS 0xfffc
381
382 /*
383 * Interrupt Status Register 2 (offset 0x0040)
384 * Interrupt Mask Register 2 (offset 0x0044)
385 * Interrupt Select Register 2 (offset 0x0048)
386 */
387 typedef union {
388 unsigned int bits32;
389 struct bit_0040 {
390 unsigned int toe_q0_full : 1; /* bit 0 TOE Queue 0 Full Interrupt */
391 unsigned int toe_q1_full : 1; /* bit 1 TOE Queue 1 Full Interrupt */
392 unsigned int toe_q2_full : 1; /* bit 2 TOE Queue 2 Full Interrupt */
393 unsigned int toe_q3_full : 1; /* bit 3 TOE Queue 3 Full Interrupt */
394 unsigned int toe_q4_full : 1; /* bit 4 TOE Queue 4 Full Interrupt */
395 unsigned int toe_q5_full : 1; /* bit 5 TOE Queue 5 Full Interrupt */
396 unsigned int toe_q6_full : 1; /* bit 6 TOE Queue 6 Full Interrupt */
397 unsigned int toe_q7_full : 1; /* bit 7 TOE Queue 7 Full Interrupt */
398 unsigned int toe_q8_full : 1; /* bit 8 TOE Queue 8 Full Interrupt */
399 unsigned int toe_q9_full : 1; /* bit 9 TOE Queue 9 Full Interrupt */
400 unsigned int toe_q10_full : 1; /* bit 10 TOE Queue 10 Full Interrupt */
401 unsigned int toe_q11_full : 1; /* bit 11 TOE Queue 11 Full Interrupt */
402 unsigned int toe_q12_full : 1; /* bit 12 TOE Queue 12 Full Interrupt */
403 unsigned int toe_q13_full : 1; /* bit 13 TOE Queue 13 Full Interrupt */
404 unsigned int toe_q14_full : 1; /* bit 14 TOE Queue 14 Full Interrupt */
405 unsigned int toe_q15_full : 1; /* bit 15 TOE Queue 15 Full Interrupt */
406 unsigned int toe_q16_full : 1; /* bit 16 TOE Queue 16 Full Interrupt */
407 unsigned int toe_q17_full : 1; /* bit 17 TOE Queue 17 Full Interrupt */
408 unsigned int toe_q18_full : 1; /* bit 18 TOE Queue 18 Full Interrupt */
409 unsigned int toe_q19_full : 1; /* bit 19 TOE Queue 19 Full Interrupt */
410 unsigned int toe_q20_full : 1; /* bit 20 TOE Queue 20 Full Interrupt */
411 unsigned int toe_q21_full : 1; /* bit 21 TOE Queue 21 Full Interrupt */
412 unsigned int toe_q22_full : 1; /* bit 22 TOE Queue 22 Full Interrupt */
413 unsigned int toe_q23_full : 1; /* bit 23 TOE Queue 23 Full Interrupt */
414 unsigned int toe_q24_full : 1; /* bit 24 TOE Queue 24 Full Interrupt */
415 unsigned int toe_q25_full : 1; /* bit 25 TOE Queue 25 Full Interrupt */
416 unsigned int toe_q26_full : 1; /* bit 26 TOE Queue 26 Full Interrupt */
417 unsigned int toe_q27_full : 1; /* bit 27 TOE Queue 27 Full Interrupt */
418 unsigned int toe_q28_full : 1; /* bit 28 TOE Queue 28 Full Interrupt */
419 unsigned int toe_q29_full : 1; /* bit 29 TOE Queue 29 Full Interrupt */
420 unsigned int toe_q30_full : 1; /* bit 30 TOE Queue 30 Full Interrupt */
421 unsigned int toe_q31_full : 1; /* bit 31 TOE Queue 31 Full Interrupt */
422 } bits;
423 } INTR_REG2_T;
424
425 #define TOE_QL_FULL_INT_BIT(x) BIT(x)
426
427 /*
428 * Interrupt Status Register 3 (offset 0x0050)
429 * Interrupt Mask Register 3 (offset 0x0054)
430 * Interrupt Select Register 3 (offset 0x0058)
431 */
432 typedef union {
433 unsigned int bits32;
434 struct bit_0050 {
435 unsigned int toe_q32_full : 1; /* bit 32 TOE Queue 32 Full Interrupt */
436 unsigned int toe_q33_full : 1; /* bit 33 TOE Queue 33 Full Interrupt */
437 unsigned int toe_q34_full : 1; /* bit 34 TOE Queue 34 Full Interrupt */
438 unsigned int toe_q35_full : 1; /* bit 35 TOE Queue 35 Full Interrupt */
439 unsigned int toe_q36_full : 1; /* bit 36 TOE Queue 36 Full Interrupt */
440 unsigned int toe_q37_full : 1; /* bit 37 TOE Queue 37 Full Interrupt */
441 unsigned int toe_q38_full : 1; /* bit 38 TOE Queue 38 Full Interrupt */
442 unsigned int toe_q39_full : 1; /* bit 39 TOE Queue 39 Full Interrupt */
443 unsigned int toe_q40_full : 1; /* bit 40 TOE Queue 40 Full Interrupt */
444 unsigned int toe_q41_full : 1; /* bit 41 TOE Queue 41 Full Interrupt */
445 unsigned int toe_q42_full : 1; /* bit 42 TOE Queue 42 Full Interrupt */
446 unsigned int toe_q43_full : 1; /* bit 43 TOE Queue 43 Full Interrupt */
447 unsigned int toe_q44_full : 1; /* bit 44 TOE Queue 44 Full Interrupt */
448 unsigned int toe_q45_full : 1; /* bit 45 TOE Queue 45 Full Interrupt */
449 unsigned int toe_q46_full : 1; /* bit 46 TOE Queue 46 Full Interrupt */
450 unsigned int toe_q47_full : 1; /* bit 47 TOE Queue 47 Full Interrupt */
451 unsigned int toe_q48_full : 1; /* bit 48 TOE Queue 48 Full Interrupt */
452 unsigned int toe_q49_full : 1; /* bit 49 TOE Queue 49 Full Interrupt */
453 unsigned int toe_q50_full : 1; /* bit 50 TOE Queue 50 Full Interrupt */
454 unsigned int toe_q51_full : 1; /* bit 51 TOE Queue 51 Full Interrupt */
455 unsigned int toe_q52_full : 1; /* bit 52 TOE Queue 52 Full Interrupt */
456 unsigned int toe_q53_full : 1; /* bit 53 TOE Queue 53 Full Interrupt */
457 unsigned int toe_q54_full : 1; /* bit 54 TOE Queue 54 Full Interrupt */
458 unsigned int toe_q55_full : 1; /* bit 55 TOE Queue 55 Full Interrupt */
459 unsigned int toe_q56_full : 1; /* bit 56 TOE Queue 56 Full Interrupt */
460 unsigned int toe_q57_full : 1; /* bit 57 TOE Queue 57 Full Interrupt */
461 unsigned int toe_q58_full : 1; /* bit 58 TOE Queue 58 Full Interrupt */
462 unsigned int toe_q59_full : 1; /* bit 59 TOE Queue 59 Full Interrupt */
463 unsigned int toe_q60_full : 1; /* bit 60 TOE Queue 60 Full Interrupt */
464 unsigned int toe_q61_full : 1; /* bit 61 TOE Queue 61 Full Interrupt */
465 unsigned int toe_q62_full : 1; /* bit 62 TOE Queue 62 Full Interrupt */
466 unsigned int toe_q63_full : 1; /* bit 63 TOE Queue 63 Full Interrupt */
467 } bits;
468 } INTR_REG3_T;
469
470 #define TOE_QH_FULL_INT_BIT(x) BIT(x-32)
471
472 /*
473 * Interrupt Status Register 4 (offset 0x0060)
474 * Interrupt Mask Register 4 (offset 0x0064)
475 * Interrupt Select Register 4 (offset 0x0068)
476 */
477 typedef union {
478 unsigned char byte;
479 struct bit_0060 {
480 unsigned char status_changed : 1; /* Status Changed Intr for RGMII Mode */
481 unsigned char rx_overrun : 1; /* GMAC Rx FIFO overrun interrupt */
482 unsigned char tx_pause_off : 1; /* received pause off frame interrupt */
483 unsigned char rx_pause_off : 1; /* received pause off frame interrupt */
484 unsigned char tx_pause_on : 1; /* transmit pause on frame interrupt */
485 unsigned char rx_pause_on : 1; /* received pause on frame interrupt */
486 unsigned char cnt_full : 1; /* MIB counters half full interrupt */
487 unsigned char reserved : 1; /* */
488 } __packed bits;
489 } __packed GMAC_INTR_T;
490
491 typedef union {
492 unsigned int bits32;
493 struct bit_0060_2 {
494 unsigned int swfq_empty : 1; /* bit 0 Software Free Queue Empty Intr. */
495 unsigned int hwfq_empty : 1; /* bit 1 Hardware Free Queue Empty Intr. */
496 unsigned int class_qf_int : 14; /* bit 15:2 Classification Rx Queue13-0 Full Intr. */
497 GMAC_INTR_T gmac0;
498 GMAC_INTR_T gmac1;
499 } bits;
500 } INTR_REG4_T;
501
502 #define GMAC1_RESERVED_INT_BIT BIT(31)
503 #define GMAC1_MIB_INT_BIT BIT(30)
504 #define GMAC1_RX_PAUSE_ON_INT_BIT BIT(29)
505 #define GMAC1_TX_PAUSE_ON_INT_BIT BIT(28)
506 #define GMAC1_RX_PAUSE_OFF_INT_BIT BIT(27)
507 #define GMAC1_TX_PAUSE_OFF_INT_BIT BIT(26)
508 #define GMAC1_RX_OVERRUN_INT_BIT BIT(25)
509 #define GMAC1_STATUS_CHANGE_INT_BIT BIT(24)
510 #define GMAC0_RESERVED_INT_BIT BIT(23)
511 #define GMAC0_MIB_INT_BIT BIT(22)
512 #define GMAC0_RX_PAUSE_ON_INT_BIT BIT(21)
513 #define GMAC0_TX_PAUSE_ON_INT_BIT BIT(20)
514 #define GMAC0_RX_PAUSE_OFF_INT_BIT BIT(19)
515 #define GMAC0_TX_PAUSE_OFF_INT_BIT BIT(18)
516 #define GMAC0_RX_OVERRUN_INT_BIT BIT(17)
517 #define GMAC0_STATUS_CHANGE_INT_BIT BIT(16)
518 #define CLASS_RX_FULL_INT_BIT(x) BIT((x+2))
519 #define HWFQ_EMPTY_INT_BIT BIT(1)
520 #define SWFQ_EMPTY_INT_BIT BIT(0)
521
522 #define GMAC0_INT_BITS (GMAC0_RESERVED_INT_BIT | GMAC0_MIB_INT_BIT | \
523 GMAC0_RX_PAUSE_ON_INT_BIT | GMAC0_TX_PAUSE_ON_INT_BIT | \
524 GMAC0_RX_PAUSE_OFF_INT_BIT | GMAC0_TX_PAUSE_OFF_INT_BIT | \
525 GMAC0_RX_OVERRUN_INT_BIT | GMAC0_STATUS_CHANGE_INT_BIT)
526 #define GMAC1_INT_BITS (GMAC1_RESERVED_INT_BIT | GMAC1_MIB_INT_BIT | \
527 GMAC1_RX_PAUSE_ON_INT_BIT | GMAC1_TX_PAUSE_ON_INT_BIT | \
528 GMAC1_RX_PAUSE_OFF_INT_BIT | GMAC1_TX_PAUSE_OFF_INT_BIT | \
529 GMAC1_RX_OVERRUN_INT_BIT | GMAC1_STATUS_CHANGE_INT_BIT)
530
531 #define CLASS_RX_FULL_INT_BITS 0xfffc
532
533 /*
534 * GLOBAL_QUEUE_THRESHOLD_REG (offset 0x0070)
535 */
536 typedef union {
537 unsigned int bits32;
538 struct bit_0070_2 {
539 unsigned int swfq_empty : 8; /* 7:0 Software Free Queue Empty Threshold */
540 unsigned int hwfq_empty : 8; /* 15:8 Hardware Free Queue Empty Threshold */
541 unsigned int intrq : 8; /* 23:16 */
542 unsigned int toe_class : 8; /* 31:24 */
543 } bits;
544 } QUEUE_THRESHOLD_T;
545
546
547 /*
548 * GMAC DMA Control Register
549 * GMAC0 offset 0x8000
550 * GMAC1 offset 0xC000
551 */
552 typedef union {
553 unsigned int bits32;
554 struct bit_8000 {
555 unsigned int td_bus : 2; /* bit 1:0 Peripheral Bus Width */
556 unsigned int td_burst_size : 2; /* bit 3:2 TxDMA max burst size for every AHB request */
557 unsigned int td_prot : 4; /* bit 7:4 TxDMA protection control */
558 unsigned int rd_bus : 2; /* bit 9:8 Peripheral Bus Width */
559 unsigned int rd_burst_size : 2; /* bit 11:10 DMA max burst size for every AHB request */
560 unsigned int rd_prot : 4; /* bit 15:12 DMA Protection Control */
561 unsigned int rd_insert_bytes : 2; /* bit 17:16 */
562 unsigned int reserved : 10; /* bit 27:18 */
563 unsigned int drop_small_ack : 1; /* bit 28 1: Drop, 0: Accept */
564 unsigned int loopback : 1; /* bit 29 Loopback TxDMA to RxDMA */
565 unsigned int td_enable : 1; /* bit 30 Tx DMA Enable */
566 unsigned int rd_enable : 1; /* bit 31 Rx DMA Enable */
567 } bits;
568 } GMAC_DMA_CTRL_T;
569
570 /*
571 * GMAC Tx Weighting Control Register 0
572 * GMAC0 offset 0x8004
573 * GMAC1 offset 0xC004
574 */
575 typedef union {
576 unsigned int bits32;
577 struct bit_8004 {
578 unsigned int hw_tq0 : 6; /* bit 5:0 HW TX Queue 3 */
579 unsigned int hw_tq1 : 6; /* bit 11:6 HW TX Queue 2 */
580 unsigned int hw_tq2 : 6; /* bit 17:12 HW TX Queue 1 */
581 unsigned int hw_tq3 : 6; /* bit 23:18 HW TX Queue 0 */
582 unsigned int reserved : 8; /* bit 31:24 */
583 } bits;
584 } GMAC_TX_WCR0_T; /* Weighting Control Register 0 */
585
586 /*
587 * GMAC Tx Weighting Control Register 1
588 * GMAC0 offset 0x8008
589 * GMAC1 offset 0xC008
590 */
591 typedef union {
592 unsigned int bits32;
593 struct bit_8008 {
594 unsigned int sw_tq0 : 5; /* bit 4:0 SW TX Queue 0 */
595 unsigned int sw_tq1 : 5; /* bit 9:5 SW TX Queue 1 */
596 unsigned int sw_tq2 : 5; /* bit 14:10 SW TX Queue 2 */
597 unsigned int sw_tq3 : 5; /* bit 19:15 SW TX Queue 3 */
598 unsigned int sw_tq4 : 5; /* bit 24:20 SW TX Queue 4 */
599 unsigned int sw_tq5 : 5; /* bit 29:25 SW TX Queue 5 */
600 unsigned int reserved : 2; /* bit 31:30 */
601 } bits;
602 } GMAC_TX_WCR1_T; /* Weighting Control Register 1 */
603
604 /*
605 * Queue Read/Write Pointer
606 * GMAC SW TX Queue 0~5 Read/Write Pointer register
607 * GMAC0 offset 0x800C ~ 0x8020
608 * GMAC1 offset 0xC00C ~ 0xC020
609 * GMAC HW TX Queue 0~3 Read/Write Pointer register
610 * GMAC0 offset 0x8024 ~ 0x8030
611 * GMAC1 offset 0xC024 ~ 0xC030
612 *
613 * see DMA_RWPTR_T structure
614 */
615
616 /*
617 * GMAC DMA Tx First Description Address Register
618 * GMAC0 offset 0x8038
619 * GMAC1 offset 0xC038
620 */
621 typedef union {
622 unsigned int bits32;
623 struct bit_8038 {
624 unsigned int reserved : 3;
625 unsigned int td_busy : 1; /* bit 3 1: TxDMA busy; 0: TxDMA idle */
626 unsigned int td_first_des_ptr : 28; /* bit 31:4 first descriptor address */
627 } bits;
628 } GMAC_TXDMA_FIRST_DESC_T;
629
630 /*
631 * GMAC DMA Tx Current Description Address Register
632 * GMAC0 offset 0x803C
633 * GMAC1 offset 0xC03C
634 */
635 typedef union {
636 unsigned int bits32;
637 struct bit_803C {
638 unsigned int reserved : 4;
639 unsigned int td_curr_desc_ptr : 28; /* bit 31:4 current descriptor address */
640 } bits;
641 } GMAC_TXDMA_CURR_DESC_T;
642
643 /*
644 * GMAC DMA Tx Description Word 0 Register
645 * GMAC0 offset 0x8040
646 * GMAC1 offset 0xC040
647 */
648 typedef union {
649 unsigned int bits32;
650 struct bit_8040 {
651 unsigned int buffer_size : 16; /* bit 15:0 Transfer size */
652 unsigned int desc_count : 6; /* bit 21:16 number of descriptors used for the current frame */
653 unsigned int status_tx_ok : 1; /* bit 22 Tx Status, 1: Successful 0: Failed */
654 unsigned int status_rvd : 6; /* bit 28:23 Tx Status, Reserved bits */
655 unsigned int perr : 1; /* bit 29 protocol error during processing this descriptor */
656 unsigned int derr : 1; /* bit 30 data error during processing this descriptor */
657 unsigned int reserved : 1; /* bit 31 */
658 } bits;
659 } GMAC_TXDESC_0_T;
660
661 /*
662 * GMAC DMA Tx Description Word 1 Register
663 * GMAC0 offset 0x8044
664 * GMAC1 offset 0xC044
665 */
666 typedef union {
667 unsigned int bits32;
668 struct txdesc_word1 {
669 unsigned int byte_count : 16; /* bit 15: 0 Tx Frame Byte Count */
670 unsigned int mtu_enable : 1; /* bit 16 TSS segmentation use MTU setting */
671 unsigned int ip_chksum : 1; /* bit 17 IPV4 Header Checksum Enable */
672 unsigned int ipv6_enable : 1; /* bit 18 IPV6 Tx Enable */
673 unsigned int tcp_chksum : 1; /* bit 19 TCP Checksum Enable */
674 unsigned int udp_chksum : 1; /* bit 20 UDP Checksum Enable */
675 unsigned int bypass_tss : 1; /* bit 21 Bypass HW offload engine */
676 unsigned int ip_fixed_len : 1; /* bit 22 Don't update IP length field */
677 unsigned int reserved : 9; /* bit 31:23 Tx Flag, Reserved */
678 } bits;
679 } GMAC_TXDESC_1_T;
680
681 #define TSS_IP_FIXED_LEN_BIT BIT(22)
682 #define TSS_BYPASS_BIT BIT(21)
683 #define TSS_UDP_CHKSUM_BIT BIT(20)
684 #define TSS_TCP_CHKSUM_BIT BIT(19)
685 #define TSS_IPV6_ENABLE_BIT BIT(18)
686 #define TSS_IP_CHKSUM_BIT BIT(17)
687 #define TSS_MTU_ENABLE_BIT BIT(16)
688
689 #define TSS_CHECKUM_ENABLE \
690 (TSS_IP_CHKSUM_BIT|TSS_IPV6_ENABLE_BIT| \
691 TSS_TCP_CHKSUM_BIT|TSS_UDP_CHKSUM_BIT)
692
693 /*
694 * GMAC DMA Tx Description Word 2 Register
695 * GMAC0 offset 0x8048
696 * GMAC1 offset 0xC048
697 */
698 typedef union {
699 unsigned int bits32;
700 unsigned int buf_adr;
701 } GMAC_TXDESC_2_T;
702
703 /*
704 * GMAC DMA Tx Description Word 3 Register
705 * GMAC0 offset 0x804C
706 * GMAC1 offset 0xC04C
707 */
708 typedef union {
709 unsigned int bits32;
710 struct txdesc_word3 {
711 unsigned int mtu_size : 13; /* bit 12: 0 Tx Frame Byte Count */
712 unsigned int reserved : 16; /* bit 28:13 */
713 unsigned int eofie : 1; /* bit 29 End of frame interrupt enable */
714 unsigned int sof_eof : 2; /* bit 31:30 11: only one, 10: first, 01: last, 00: linking */
715 } bits;
716 } GMAC_TXDESC_3_T;
717 #define SOF_EOF_BIT_MASK 0x3fffffff
718 #define SOF_BIT 0x80000000
719 #define EOF_BIT 0x40000000
720 #define EOFIE_BIT BIT(29)
721 #define MTU_SIZE_BIT_MASK 0x1fff
722
723 /*
724 * GMAC Tx Descriptor
725 */
726 typedef struct {
727 GMAC_TXDESC_0_T word0;
728 GMAC_TXDESC_1_T word1;
729 GMAC_TXDESC_2_T word2;
730 GMAC_TXDESC_3_T word3;
731 } GMAC_TXDESC_T;
732
733 /*
734 * GMAC DMA Rx First Description Address Register
735 * GMAC0 offset 0x8058
736 * GMAC1 offset 0xC058
737 */
738 typedef union {
739 unsigned int bits32;
740 struct bit_8058 {
741 unsigned int reserved : 3; /* bit 2:0 */
742 unsigned int rd_busy : 1; /* bit 3 1-RxDMA busy; 0-RxDMA idle */
743 unsigned int rd_first_des_ptr : 28; /* bit 31:4 first descriptor address */
744 } bits;
745 } GMAC_RXDMA_FIRST_DESC_T;
746
747 /*
748 * GMAC DMA Rx Current Description Address Register
749 * GMAC0 offset 0x805C
750 * GMAC1 offset 0xC05C
751 */
752 typedef union {
753 unsigned int bits32;
754 struct bit_805C {
755 unsigned int reserved : 4; /* bit 3:0 */
756 unsigned int rd_curr_des_ptr : 28; /* bit 31:4 current descriptor address */
757 } bits;
758 } GMAC_RXDMA_CURR_DESC_T;
759
760 /*
761 * GMAC DMA Rx Description Word 0 Register
762 * GMAC0 offset 0x8060
763 * GMAC1 offset 0xC060
764 */
765 typedef union {
766 unsigned int bits32;
767 struct bit_8060 {
768 unsigned int buffer_size : 16; /* bit 15:0 number of descriptors used for the current frame */
769 unsigned int desc_count : 6; /* bit 21:16 number of descriptors used for the current frame */
770 unsigned int status : 4; /* bit 24:22 Status of rx frame */
771 unsigned int chksum_status : 3; /* bit 28:26 Check Sum Status */
772 unsigned int perr : 1; /* bit 29 protocol error during processing this descriptor */
773 unsigned int derr : 1; /* bit 30 data error during processing this descriptor */
774 unsigned int drop : 1; /* bit 31 TOE/CIS Queue Full dropped packet to default queue */
775 } bits;
776 } GMAC_RXDESC_0_T;
777
778 #define GMAC_RXDESC_0_T_derr BIT(30)
779 #define GMAC_RXDESC_0_T_perr BIT(29)
780 #define GMAC_RXDESC_0_T_chksum_status(x) BIT((x+26))
781 #define GMAC_RXDESC_0_T_status(x) BIT((x+22))
782 #define GMAC_RXDESC_0_T_desc_count(x) BIT((x+16))
783
784 #define RX_CHKSUM_IP_UDP_TCP_OK 0
785 #define RX_CHKSUM_IP_OK_ONLY 1
786 #define RX_CHKSUM_NONE 2
787 #define RX_CHKSUM_IP_ERR_UNKNOWN 4
788 #define RX_CHKSUM_IP_ERR 5
789 #define RX_CHKSUM_TCP_UDP_ERR 6
790 #define RX_CHKSUM_NUM 8
791
792 #define RX_STATUS_GOOD_FRAME 0
793 #define RX_STATUS_TOO_LONG_GOOD_CRC 1
794 #define RX_STATUS_RUNT_FRAME 2
795 #define RX_STATUS_SFD_NOT_FOUND 3
796 #define RX_STATUS_CRC_ERROR 4
797 #define RX_STATUS_TOO_LONG_BAD_CRC 5
798 #define RX_STATUS_ALIGNMENT_ERROR 6
799 #define RX_STATUS_TOO_LONG_BAD_ALIGN 7
800 #define RX_STATUS_RX_ERR 8
801 #define RX_STATUS_DA_FILTERED 9
802 #define RX_STATUS_BUFFER_FULL 10
803 #define RX_STATUS_NUM 16
804
805 #define RX_ERROR_LENGTH(s) \
806 ((s) == RX_STATUS_TOO_LONG_GOOD_CRC || \
807 (s) == RX_STATUS_TOO_LONG_BAD_CRC || \
808 (s) == RX_STATUS_TOO_LONG_BAD_ALIGN)
809 #define RX_ERROR_OVER(s) \
810 ((s) == RX_STATUS_BUFFER_FULL)
811 #define RX_ERROR_CRC(s) \
812 ((s) == RX_STATUS_CRC_ERROR || \
813 (s) == RX_STATUS_TOO_LONG_BAD_CRC)
814 #define RX_ERROR_FRAME(s) \
815 ((s) == RX_STATUS_ALIGNMENT_ERROR || \
816 (s) == RX_STATUS_TOO_LONG_BAD_ALIGN)
817 #define RX_ERROR_FIFO(s) \
818 (0)
819
820 /*
821 * GMAC DMA Rx Description Word 1 Register
822 * GMAC0 offset 0x8064
823 * GMAC1 offset 0xC064
824 */
825 typedef union {
826 unsigned int bits32;
827 struct rxdesc_word1 {
828 unsigned int byte_count : 16; /* bit 15: 0 Rx Frame Byte Count */
829 unsigned int sw_id : 16; /* bit 31:16 Software ID */
830 } bits;
831 } GMAC_RXDESC_1_T;
832
833 /*
834 * GMAC DMA Rx Description Word 2 Register
835 * GMAC0 offset 0x8068
836 * GMAC1 offset 0xC068
837 */
838 typedef union {
839 unsigned int bits32;
840 unsigned int buf_adr;
841 } GMAC_RXDESC_2_T;
842
843 #define RX_INSERT_NONE 0
844 #define RX_INSERT_1_BYTE 1
845 #define RX_INSERT_2_BYTE 2
846 #define RX_INSERT_3_BYTE 3
847
848 /*
849 * GMAC DMA Rx Description Word 3 Register
850 * GMAC0 offset 0x806C
851 * GMAC1 offset 0xC06C
852 */
853 typedef union {
854 unsigned int bits32;
855 struct rxdesc_word3 {
856 unsigned int l3_offset : 8; /* bit 7: 0 L3 data offset */
857 unsigned int l4_offset : 8; /* bit 15: 8 L4 data offset */
858 unsigned int l7_offset : 8; /* bit 23: 16 L7 data offset */
859 unsigned int dup_ack : 1; /* bit 24 Duplicated ACK detected */
860 unsigned int abnormal : 1; /* bit 25 abnormal case found */
861 unsigned int option : 1; /* bit 26 IPV4 option or IPV6 extension header */
862 unsigned int out_of_seq : 1; /* bit 27 Out of Sequence packet */
863 unsigned int ctrl_flag : 1; /* bit 28 Control Flag is present */
864 unsigned int eofie : 1; /* bit 29 End of frame interrupt enable */
865 unsigned int sof_eof : 2; /* bit 31:30 11: only one, 10: first, 01: last, 00: linking */
866 } bits;
867 } GMAC_RXDESC_3_T;
868
869 /*
870 * GMAC Rx Descriptor
871 */
872 typedef struct {
873 GMAC_RXDESC_0_T word0;
874 GMAC_RXDESC_1_T word1;
875 GMAC_RXDESC_2_T word2;
876 GMAC_RXDESC_3_T word3;
877 } GMAC_RXDESC_T;
878
879 /*
880 * GMAC Hash Engine Enable/Action Register 0 Offset Register
881 * GMAC0 offset 0x8070
882 * GMAC1 offset 0xC070
883 */
884 typedef union {
885 unsigned int bits32;
886 struct bit_8070 {
887 unsigned int mr0hel : 6; /* bit 5:0 match rule 0 hash entry size */
888 unsigned int mr0_action : 5; /* bit 10:6 Matching Rule 0 action offset */
889 unsigned int reserved0 : 4; /* bit 14:11 */
890 unsigned int mr0en : 1; /* bit 15 Enable Matching Rule 0 */
891 unsigned int mr1hel : 6; /* bit 21:16 match rule 1 hash entry size */
892 unsigned int mr1_action : 5; /* bit 26:22 Matching Rule 1 action offset */
893 unsigned int timing : 3; /* bit 29:27 */
894 unsigned int reserved1 : 1; /* bit 30 */
895 unsigned int mr1en : 1; /* bit 31 Enable Matching Rule 1 */
896 } bits;
897 } GMAC_HASH_ENABLE_REG0_T;
898
899 /*
900 * GMAC Hash Engine Enable/Action Register 1 Offset Register
901 * GMAC0 offset 0x8074
902 * GMAC1 offset 0xC074
903 */
904 typedef union {
905 unsigned int bits32;
906 struct bit_8074 {
907 unsigned int mr2hel : 6; /* bit 5:0 match rule 2 hash entry size */
908 unsigned int mr2_action : 5; /* bit 10:6 Matching Rule 2 action offset */
909 unsigned int reserved2 : 4; /* bit 14:11 */
910 unsigned int mr2en : 1; /* bit 15 Enable Matching Rule 2 */
911 unsigned int mr3hel : 6; /* bit 21:16 match rule 3 hash entry size */
912 unsigned int mr3_action : 5; /* bit 26:22 Matching Rule 3 action offset */
913 unsigned int reserved1 : 4; /* bit 30:27 */
914 unsigned int mr3en : 1; /* bit 31 Enable Matching Rule 3 */
915 } bits;
916 } GMAC_HASH_ENABLE_REG1_T;
917
918 /*
919 * GMAC Matching Rule Control Register 0
920 * GMAC0 offset 0x8078
921 * GMAC1 offset 0xC078
922 */
923 typedef union {
924 unsigned int bits32;
925 struct bit_8078 {
926 unsigned int sprx : 8; /* bit 7:0 Support Protocol Register 7:0 */
927 unsigned int reserved2 : 4; /* bit 11:8 */
928 unsigned int tos_traffic : 1; /* bit 12 IPV4 TOS or IPV6 Traffice Class */
929 unsigned int flow_lable : 1; /* bit 13 IPV6 Flow label */
930 unsigned int ip_hdr_len : 1; /* bit 14 IPV4 Header length */
931 unsigned int ip_version : 1; /* bit 15 0: IPV4, 1: IPV6 */
932 unsigned int reserved1 : 3; /* bit 18:16 */
933 unsigned int pppoe : 1; /* bit 19 PPPoE Session ID enable */
934 unsigned int vlan : 1; /* bit 20 VLAN ID enable */
935 unsigned int ether_type : 1; /* bit 21 Ethernet type enable */
936 unsigned int sa : 1; /* bit 22 MAC SA enable */
937 unsigned int da : 1; /* bit 23 MAC DA enable */
938 unsigned int priority : 3; /* bit 26:24 priority if multi-rules matched */
939 unsigned int port : 1; /* bit 27 PORT ID matching enable */
940 unsigned int l7 : 1; /* bit 28 L7 matching enable */
941 unsigned int l4 : 1; /* bit 29 L4 matching enable */
942 unsigned int l3 : 1; /* bit 30 L3 matching enable */
943 unsigned int l2 : 1; /* bit 31 L2 matching enable */
944 } bits;
945 } GMAC_MRxCR0_T;
946
947 #define MR_L2_BIT BIT(31)
948 #define MR_L3_BIT BIT(30)
949 #define MR_L4_BIT BIT(29)
950 #define MR_L7_BIT BIT(28)
951 #define MR_PORT_BIT BIT(27)
952 #define MR_PRIORITY_BIT BIT(26)
953 #define MR_DA_BIT BIT(23)
954 #define MR_SA_BIT BIT(22)
955 #define MR_ETHER_TYPE_BIT BIT(21)
956 #define MR_VLAN_BIT BIT(20)
957 #define MR_PPPOE_BIT BIT(19)
958 #define MR_IP_VER_BIT BIT(15)
959 #define MR_IP_HDR_LEN_BIT BIT(14)
960 #define MR_FLOW_LABLE_BIT BIT(13)
961 #define MR_TOS_TRAFFIC_BIT BIT(12)
962 #define MR_SPR_BIT(x) BIT(x)
963 #define MR_SPR_BITS 0xff
964
965 /*
966 * GMAC Matching Rule Control Register 1
967 * GMAC0 offset 0x807C
968 * GMAC1 offset 0xC07C
969 */
970 typedef union {
971 unsigned int bits32;
972 struct bit_807C {
973 unsigned int l4_byte0_15 : 16; /* bit 15: 0 */
974 unsigned int dip_netmask : 7; /* bit 22:16 Dest IP net mask, number of mask bits */
975 unsigned int dip : 1; /* bit 23 Dest IP */
976 unsigned int sip_netmask : 7; /* bit 30:24 Srce IP net mask, number of mask bits */
977 unsigned int sip : 1; /* bit 31 Srce IP */
978 } bits;
979 } GMAC_MRxCR1_T;
980
981 /*
982 * GMAC Matching Rule Control Register 2
983 * GMAC0 offset 0x8080
984 * GMAC1 offset 0xC080
985 */
986 typedef union {
987 unsigned int bits32;
988 struct bit_8080 {
989 unsigned int l7_byte0_23 : 24; /* bit 23:0 */
990 unsigned int l4_byte16_24 : 8; /* bit 31: 24 */
991 } bits;
992 } GMAC_MRxCR2_T;
993
994 /*
995 * GMAC Support registers
996 * GMAC0 offset 0x80A8
997 * GMAC1 offset 0xC0A8
998 */
999 typedef union {
1000 unsigned int bits32;
1001 struct bit_80A8 {
1002 unsigned int protocol : 8; /* bit 7:0 Supported protocol */
1003 unsigned int swap : 3; /* bit 10:8 Swap */
1004 unsigned int reserved : 21; /* bit 31:11 */
1005 } bits;
1006 } GMAC_SPR_T;
1007
1008 /*
1009 * GMAC_AHB_WEIGHT registers
1010 * GMAC0 offset 0x80C8
1011 * GMAC1 offset 0xC0C8
1012 */
1013 typedef union {
1014 unsigned int bits32;
1015 struct bit_80C8 {
1016 unsigned int hash_weight : 5; /* 4:0 */
1017 unsigned int rx_weight : 5; /* 9:5 */
1018 unsigned int tx_weight : 5; /* 14:10 */
1019 unsigned int pre_req : 5; /* 19:15 Rx Data Pre Request FIFO Threshold */
1020 unsigned int tqDV_threshold : 5; /* 24:20 DMA TqCtrl to Start tqDV FIFO Threshold */
1021 unsigned int reserved : 7; /* 31:25 */
1022 } bits;
1023 } GMAC_AHB_WEIGHT_T;
1024
1025 /*
1026 * the register structure of GMAC
1027 */
1028
1029 /*
1030 * GMAC RX FLTR
1031 * GMAC0 Offset 0xA00C
1032 * GMAC1 Offset 0xE00C
1033 */
1034 typedef union {
1035 unsigned int bits32;
1036 struct bit1_000c {
1037 unsigned int unicast : 1; /* enable receive of unicast frames that are sent to STA address */
1038 unsigned int multicast : 1; /* enable receive of multicast frames that pass multicast filter */
1039 unsigned int broadcast : 1; /* enable receive of broadcast frames */
1040 unsigned int promiscuous : 1; /* enable receive of all frames */
1041 unsigned int error : 1; /* enable receive of all error frames */
1042 unsigned int : 27;
1043 } bits;
1044 } GMAC_RX_FLTR_T;
1045
1046 /*
1047 * GMAC Configuration 0
1048 * GMAC0 Offset 0xA018
1049 * GMAC1 Offset 0xE018
1050 */
1051 typedef union {
1052 unsigned int bits32;
1053 struct bit1_0018 {
1054 unsigned int dis_tx : 1; /* 0: disable transmit */
1055 unsigned int dis_rx : 1; /* 1: disable receive */
1056 unsigned int loop_back : 1; /* 2: transmit data loopback enable */
1057 unsigned int flow_ctrl : 1; /* 3: flow control also trigged by Rx queues */
1058 unsigned int adj_ifg : 4; /* 4-7: adjust IFG from 96+/-56 */
1059 unsigned int max_len : 3; /* 8-10 maximum receive frame length allowed */
1060 unsigned int dis_bkoff : 1; /* 11: disable back-off function */
1061 unsigned int dis_col : 1; /* 12: disable 16 collisions abort function */
1062 unsigned int sim_test : 1; /* 13: speed up timers in simulation */
1063 unsigned int rx_fc_en : 1; /* 14: RX flow control enable */
1064 unsigned int tx_fc_en : 1; /* 15: TX flow control enable */
1065 unsigned int rgmii_en : 1; /* 16: RGMII in-band status enable */
1066 unsigned int ipv4_rx_chksum : 1; /* 17: IPv4 RX Checksum enable */
1067 unsigned int ipv6_rx_chksum : 1; /* 18: IPv6 RX Checksum enable */
1068 unsigned int rx_tag_remove : 1; /* 19: Remove Rx VLAN tag */
1069 unsigned int rgmm_edge : 1; /* 20 */
1070 unsigned int rxc_inv : 1; /* 21 */
1071 unsigned int ipv6_exthdr_order : 1; /* 22 */
1072 unsigned int rx_err_detect : 1; /* 23 */
1073 unsigned int port0_chk_hwq : 1; /* 24 */
1074 unsigned int port1_chk_hwq : 1; /* 25 */
1075 unsigned int port0_chk_toeq : 1; /* 26 */
1076 unsigned int port1_chk_toeq : 1; /* 27 */
1077 unsigned int port0_chk_classq : 1; /* 28 */
1078 unsigned int port1_chk_classq : 1; /* 29 */
1079 unsigned int reserved : 2; /* 31 */
1080 } bits;
1081 } GMAC_CONFIG0_T;
1082
1083 #define CONFIG0_TX_RX_DISABLE (BIT(1)|BIT(0))
1084 #define CONFIG0_RX_CHKSUM (BIT(18)|BIT(17))
1085 #define CONFIG0_FLOW_RX (BIT(14))
1086 #define CONFIG0_FLOW_TX (BIT(15))
1087 #define CONFIG0_FLOW_TX_RX (BIT(14)|BIT(15))
1088 #define CONFIG0_FLOW_CTL (BIT(14)|BIT(15))
1089
1090 #define CONFIG0_MAXLEN_SHIFT 8
1091 #define CONFIG0_MAXLEN_MASK (7 << CONFIG0_MAXLEN_SHIFT)
1092 #define CONFIG0_MAXLEN_1536 0
1093 #define CONFIG0_MAXLEN_1518 1
1094 #define CONFIG0_MAXLEN_1522 2
1095 #define CONFIG0_MAXLEN_1542 3
1096 #define CONFIG0_MAXLEN_9k 4 /* 9212 */
1097 #define CONFIG0_MAXLEN_10k 5 /* 10236 */
1098 #define CONFIG0_MAXLEN_1518__6 6
1099 #define CONFIG0_MAXLEN_1518__7 7
1100
1101 /*
1102 * GMAC Configuration 1
1103 * GMAC0 Offset 0xA01C
1104 * GMAC1 Offset 0xE01C
1105 */
1106 typedef union {
1107 unsigned int bits32;
1108 struct bit1_001c {
1109 unsigned int set_threshold : 8; /* flow control set threshold */
1110 unsigned int rel_threshold : 8; /* flow control release threshold */
1111 unsigned int reserved : 16;
1112 } bits;
1113 } GMAC_CONFIG1_T;
1114
1115 #define GMAC_FLOWCTRL_SET_MAX 32
1116 #define GMAC_FLOWCTRL_SET_MIN 0
1117 #define GMAC_FLOWCTRL_RELEASE_MAX 32
1118 #define GMAC_FLOWCTRL_RELEASE_MIN 0
1119
1120 /*
1121 * GMAC Configuration 2
1122 * GMAC0 Offset 0xA020
1123 * GMAC1 Offset 0xE020
1124 */
1125 typedef union {
1126 unsigned int bits32;
1127 struct bit1_0020 {
1128 unsigned int set_threshold : 16; /* flow control set threshold */
1129 unsigned int rel_threshold : 16; /* flow control release threshold */
1130 } bits;
1131 } GMAC_CONFIG2_T;
1132
1133 /*
1134 * GMAC Configuration 3
1135 * GMAC0 Offset 0xA024
1136 * GMAC1 Offset 0xE024
1137 */
1138 typedef union {
1139 unsigned int bits32;
1140 struct bit1_0024 {
1141 unsigned int set_threshold : 16; /* flow control set threshold */
1142 unsigned int rel_threshold : 16; /* flow control release threshold */
1143 } bits;
1144 } GMAC_CONFIG3_T;
1145
1146
1147 /*
1148 * GMAC STATUS
1149 * GMAC0 Offset 0xA02C
1150 * GMAC1 Offset 0xE02C
1151 */
1152 typedef union {
1153 unsigned int bits32;
1154 struct bit1_002c {
1155 unsigned int link : 1; /* link status */
1156 unsigned int speed : 2; /* link speed(00->2.5M 01->25M 10->125M) */
1157 unsigned int duplex : 1; /* duplex mode */
1158 unsigned int reserved : 1;
1159 unsigned int mii_rmii : 2; /* PHY interface type */
1160 unsigned int : 25;
1161 } bits;
1162 } GMAC_STATUS_T;
1163
1164 #define GMAC_SPEED_10 0
1165 #define GMAC_SPEED_100 1
1166 #define GMAC_SPEED_1000 2
1167
1168 #define GMAC_PHY_MII 0
1169 #define GMAC_PHY_GMII 1
1170 #define GMAC_PHY_RGMII_100_10 2
1171 #define GMAC_PHY_RGMII_1000 3
1172
1173 /*
1174 * Queue Header
1175 * (1) TOE Queue Header
1176 * (2) Non-TOE Queue Header
1177 * (3) Interrupt Queue Header
1178 *
1179 * memory Layout
1180 * TOE Queue Header
1181 * 0x60003000 +---------------------------+ 0x0000
1182 * | TOE Queue 0 Header |
1183 * | 8 * 4 Bytes |
1184 * +---------------------------+ 0x0020
1185 * | TOE Queue 1 Header |
1186 * | 8 * 4 Bytes |
1187 * +---------------------------+ 0x0040
1188 * | ...... |
1189 * | |
1190 * +---------------------------+
1191 *
1192 * Non TOE Queue Header
1193 * 0x60002000 +---------------------------+ 0x0000
1194 * | Default Queue 0 Header |
1195 * | 2 * 4 Bytes |
1196 * +---------------------------+ 0x0008
1197 * | Default Queue 1 Header |
1198 * | 2 * 4 Bytes |
1199 * +---------------------------+ 0x0010
1200 * | Classification Queue 0 |
1201 * | 2 * 4 Bytes |
1202 * +---------------------------+
1203 * | Classification Queue 1 |
1204 * | 2 * 4 Bytes |
1205 * +---------------------------+ (n * 8 + 0x10)
1206 * | ... |
1207 * | 2 * 4 Bytes |
1208 * +---------------------------+ (13 * 8 + 0x10)
1209 * | Classification Queue 13 |
1210 * | 2 * 4 Bytes |
1211 * +---------------------------+ 0x80
1212 * | Interrupt Queue 0 |
1213 * | 2 * 4 Bytes |
1214 * +---------------------------+
1215 * | Interrupt Queue 1 |
1216 * | 2 * 4 Bytes |
1217 * +---------------------------+
1218 * | Interrupt Queue 2 |
1219 * | 2 * 4 Bytes |
1220 * +---------------------------+
1221 * | Interrupt Queue 3 |
1222 * | 2 * 4 Bytes |
1223 * +---------------------------+
1224 *
1225 */
1226 #define TOE_QUEUE_HDR_ADDR(n) (TOE_TOE_QUE_HDR_BASE + n * 32)
1227 #define TOE_Q_HDR_AREA_END (TOE_QUEUE_HDR_ADDR(TOE_TOE_QUEUE_MAX + 1))
1228 #define TOE_DEFAULT_Q_HDR_BASE(x) (TOE_NONTOE_QUE_HDR_BASE + 0x08 * (x))
1229 #define TOE_CLASS_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x10)
1230 #define TOE_INTR_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x80)
1231 #define INTERRUPT_QUEUE_HDR_ADDR(n) (TOE_INTR_Q_HDR_BASE + n * 8)
1232 #define NONTOE_Q_HDR_AREA_END (INTERRUPT_QUEUE_HDR_ADDR(TOE_INTR_QUEUE_MAX + 1))
1233 /*
1234 * TOE Queue Header Word 0
1235 */
1236 typedef union {
1237 unsigned int bits32;
1238 unsigned int base_size;
1239 } TOE_QHDR0_T;
1240
1241 #define TOE_QHDR0_BASE_MASK (~0x0f)
1242
1243 /*
1244 * TOE Queue Header Word 1
1245 */
1246 typedef union {
1247 unsigned int bits32;
1248 struct bit_qhdr1 {
1249 unsigned int rptr : 16; /* bit 15:0 */
1250 unsigned int wptr : 16; /* bit 31:16 */
1251 } bits;
1252 } TOE_QHDR1_T;
1253
1254 /*
1255 * TOE Queue Header Word 2
1256 */
1257 typedef union {
1258 unsigned int bits32;
1259 struct bit_qhdr2 {
1260 unsigned int TotalPktSize : 17; /* bit 16: 0 Total packet size */
1261 unsigned int reserved : 7; /* bit 23:17 */
1262 unsigned int dack : 1; /* bit 24 1: Duplicated ACK */
1263 unsigned int abn : 1; /* bit 25 1: Abnormal case Found */
1264 unsigned int tcp_opt : 1; /* bit 26 1: Have TCP option */
1265 unsigned int ip_opt : 1; /* bit 27 1: have IPV4 option or IPV6 Extension header */
1266 unsigned int sat : 1; /* bit 28 1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold */
1267 unsigned int osq : 1; /* bit 29 1: out of sequence */
1268 unsigned int ctl : 1; /* bit 30 1: have control flag bits (except ack) */
1269 unsigned int usd : 1; /* bit 31 0: if no data assembled yet */
1270 } bits;
1271 } TOE_QHDR2_T;
1272
1273 /*
1274 * TOE Queue Header Word 3
1275 */
1276 typedef union {
1277 unsigned int bits32;
1278 unsigned int seq_num;
1279 } TOE_QHDR3_T;
1280
1281 /*
1282 * TOE Queue Header Word 4
1283 */
1284 typedef union {
1285 unsigned int bits32;
1286 unsigned int ack_num;
1287 } TOE_QHDR4_T;
1288
1289 /*
1290 * TOE Queue Header Word 5
1291 */
1292 typedef union {
1293 unsigned int bits32;
1294 struct bit_qhdr5 {
1295 unsigned int AckCnt : 16; /* bit 15:0 */
1296 unsigned int SeqCnt : 16; /* bit 31:16 */
1297 } bits;
1298 } TOE_QHDR5_T;
1299
1300 /*
1301 * TOE Queue Header Word 6
1302 */
1303 typedef union {
1304 unsigned int bits32;
1305 struct bit_qhdr6 {
1306 unsigned int WinSize : 16; /* bit 15:0 */
1307 unsigned int iq_num : 2; /* bit 17:16 */
1308 unsigned int MaxPktSize : 14; /* bit 31:18 */
1309 } bits;
1310 } TOE_QHDR6_T;
1311
1312 /*
1313 * TOE Queue Header Word 7
1314 */
1315 typedef union {
1316 unsigned int bits32;
1317 struct bit_qhdr7 {
1318 unsigned int AckThreshold : 16; /* bit 15:0 */
1319 unsigned int SeqThreshold : 16; /* bit 31:16 */
1320 } bits;
1321 } TOE_QHDR7_T;
1322
1323 /*
1324 * TOE Queue Header
1325 */
1326 typedef struct {
1327 TOE_QHDR0_T word0;
1328 TOE_QHDR1_T word1;
1329 TOE_QHDR2_T word2;
1330 TOE_QHDR3_T word3;
1331 TOE_QHDR4_T word4;
1332 TOE_QHDR5_T word5;
1333 TOE_QHDR6_T word6;
1334 TOE_QHDR7_T word7;
1335 } TOE_QHDR_T;
1336
1337 /*
1338 * NONTOE Queue Header Word 0
1339 */
1340 typedef union {
1341 unsigned int bits32;
1342 unsigned int base_size;
1343 } NONTOE_QHDR0_T;
1344
1345 #define NONTOE_QHDR0_BASE_MASK (~0x0f)
1346
1347 /*
1348 * NONTOE Queue Header Word 1
1349 */
1350 typedef union {
1351 unsigned int bits32;
1352 struct bit_nonqhdr1 {
1353 unsigned int rptr : 16; /* bit 15:0 */
1354 unsigned int wptr : 16; /* bit 31:16 */
1355 } bits;
1356 } NONTOE_QHDR1_T;
1357
1358 /*
1359 * Non-TOE Queue Header
1360 */
1361 typedef struct {
1362 NONTOE_QHDR0_T word0;
1363 NONTOE_QHDR1_T word1;
1364 } NONTOE_QHDR_T;
1365
1366 /*
1367 * Interrupt Queue Header Word 0
1368 */
1369 typedef union {
1370 unsigned int bits32;
1371 struct bit_intrqhdr0 {
1372 unsigned int win_size : 16; /* bit 15:0 Descriptor Ring Size */
1373 unsigned int wptr : 16; /* bit 31:16 Write Pointer where hw stopped */
1374 } bits;
1375 } INTR_QHDR0_T;
1376
1377 /*
1378 * Interrupt Queue Header Word 1
1379 */
1380 typedef union {
1381 unsigned int bits32;
1382 struct bit_intrqhdr1 {
1383 unsigned int TotalPktSize : 17; /* bit 16: 0 Total packet size */
1384 unsigned int tcp_qid : 8; /* bit 24:17 TCP Queue ID */
1385 unsigned int dack : 1; /* bit 25 1: Duplicated ACK */
1386 unsigned int abn : 1; /* bit 26 1: Abnormal case Found */
1387 unsigned int tcp_opt : 1; /* bit 27 1: Have TCP option */
1388 unsigned int ip_opt : 1; /* bit 28 1: have IPV4 option or IPV6 Extension header */
1389 unsigned int sat : 1; /* bit 29 1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold */
1390 unsigned int osq : 1; /* bit 30 1: out of sequence */
1391 unsigned int ctl : 1; /* bit 31 1: have control flag bits (except ack) */
1392 } bits;
1393 } INTR_QHDR1_T;
1394
1395 /*
1396 * Interrupt Queue Header Word 2
1397 */
1398 typedef union {
1399 unsigned int bits32;
1400 unsigned int seq_num;
1401 } INTR_QHDR2_T;
1402
1403 /*
1404 * Interrupt Queue Header Word 3
1405 */
1406 typedef union {
1407 unsigned int bits32;
1408 unsigned int ack_num;
1409 } INTR_QHDR3_T;
1410
1411 /*
1412 * Interrupt Queue Header Word 4
1413 */
1414 typedef union {
1415 unsigned int bits32;
1416 struct bit_intrqhdr4 {
1417 unsigned int AckCnt : 16; /* bit 15:0 Ack# change since last ack# intr. */
1418 unsigned int SeqCnt : 16; /* bit 31:16 Seq# change since last seq# intr. */
1419 } bits;
1420 } INTR_QHDR4_T;
1421
1422 /*
1423 * Interrupt Queue Header
1424 */
1425 typedef struct {
1426 INTR_QHDR0_T word0;
1427 INTR_QHDR1_T word1;
1428 INTR_QHDR2_T word2;
1429 INTR_QHDR3_T word3;
1430 INTR_QHDR4_T word4;
1431 unsigned int word5;
1432 unsigned int word6;
1433 unsigned int word7;
1434 } INTR_QHDR_T;
1435
1436 #endif /* _GMAC_SL351x_H */
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