revert 15922 - add back 2.6.29 kernel support
[openwrt/openwrt.git] / target / linux / generic-2.6 / patches-2.6.29 / 022-mips_div64_gcc4.4.0.patch
1 From: Ralf Baechle <ralf@linux-mips.org>
2 Date: Thu, 30 Apr 2009 16:14:56 +0000 (+0200)
3 Subject: MIPS: Rewrite <asm/div64.h> to work with gcc 4.4.0.
4 X-Git-Url: http://www.linux-mips.org/git?p=linux.git;a=commitdiff_plain;h=a1b68289997030df64cba8478d5767fe10e42a58
5
6 MIPS: Rewrite <asm/div64.h> to work with gcc 4.4.0.
7
8 The inline assembler used on 32-bit kernels was using the "h" constraint
9 which was considered dangerous and removed for gcc 4.4.0.
10
11 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
12 ---
13
14 diff --git a/arch/mips/include/asm/div64.h b/arch/mips/include/asm/div64.h
15 index d1d6991..dc5ea57 100644
16 --- a/arch/mips/include/asm/div64.h
17 +++ b/arch/mips/include/asm/div64.h
18 @@ -6,105 +6,63 @@
19 * License. See the file "COPYING" in the main directory of this archive
20 * for more details.
21 */
22 -#ifndef _ASM_DIV64_H
23 -#define _ASM_DIV64_H
24 +#ifndef __ASM_DIV64_H
25 +#define __ASM_DIV64_H
26
27 -#include <linux/types.h>
28 +#include <asm-generic/div64.h>
29
30 -#if (_MIPS_SZLONG == 32)
31 +#if BITS_PER_LONG == 64
32
33 -#include <asm/compiler.h>
34 +#include <linux/types.h>
35
36 /*
37 * No traps on overflows for any of these...
38 */
39
40 -#define do_div64_32(res, high, low, base) ({ \
41 - unsigned long __quot32, __mod32; \
42 - unsigned long __cf, __tmp, __tmp2, __i; \
43 - \
44 - __asm__(".set push\n\t" \
45 - ".set noat\n\t" \
46 - ".set noreorder\n\t" \
47 - "move %2, $0\n\t" \
48 - "move %3, $0\n\t" \
49 - "b 1f\n\t" \
50 - " li %4, 0x21\n" \
51 - "0:\n\t" \
52 - "sll $1, %0, 0x1\n\t" \
53 - "srl %3, %0, 0x1f\n\t" \
54 - "or %0, $1, %5\n\t" \
55 - "sll %1, %1, 0x1\n\t" \
56 - "sll %2, %2, 0x1\n" \
57 - "1:\n\t" \
58 - "bnez %3, 2f\n\t" \
59 - " sltu %5, %0, %z6\n\t" \
60 - "bnez %5, 3f\n" \
61 - "2:\n\t" \
62 - " addiu %4, %4, -1\n\t" \
63 - "subu %0, %0, %z6\n\t" \
64 - "addiu %2, %2, 1\n" \
65 - "3:\n\t" \
66 - "bnez %4, 0b\n\t" \
67 - " srl %5, %1, 0x1f\n\t" \
68 - ".set pop" \
69 - : "=&r" (__mod32), "=&r" (__tmp), \
70 - "=&r" (__quot32), "=&r" (__cf), \
71 - "=&r" (__i), "=&r" (__tmp2) \
72 - : "Jr" (base), "0" (high), "1" (low)); \
73 - \
74 - (res) = __quot32; \
75 - __mod32; })
76 -
77 -#define do_div(n, base) ({ \
78 - unsigned long long __quot; \
79 - unsigned long __mod; \
80 - unsigned long long __div; \
81 - unsigned long __upper, __low, __high, __base; \
82 - \
83 - __div = (n); \
84 - __base = (base); \
85 - \
86 - __high = __div >> 32; \
87 - __low = __div; \
88 - __upper = __high; \
89 - \
90 - if (__high) \
91 - __asm__("divu $0, %z2, %z3" \
92 - : "=h" (__upper), "=l" (__high) \
93 - : "Jr" (__high), "Jr" (__base) \
94 - : GCC_REG_ACCUM); \
95 - \
96 - __mod = do_div64_32(__low, __upper, __low, __base); \
97 - \
98 - __quot = __high; \
99 - __quot = __quot << 32 | __low; \
100 - (n) = __quot; \
101 - __mod; })
102 -
103 -#endif /* (_MIPS_SZLONG == 32) */
104 -
105 -#if (_MIPS_SZLONG == 64)
106 -
107 -/*
108 - * Hey, we're already 64-bit, no
109 - * need to play games..
110 - */
111 -#define do_div(n, base) ({ \
112 - unsigned long __quot; \
113 - unsigned int __mod; \
114 - unsigned long __div; \
115 - unsigned int __base; \
116 - \
117 - __div = (n); \
118 - __base = (base); \
119 - \
120 - __mod = __div % __base; \
121 - __quot = __div / __base; \
122 - \
123 - (n) = __quot; \
124 - __mod; })
125 +#define __div64_32(n, base) \
126 +({ \
127 + unsigned long __cf, __tmp, __tmp2, __i; \
128 + unsigned long __quot32, __mod32; \
129 + unsigned long __high, __low; \
130 + unsigned long long __n; \
131 + \
132 + __high = *__n >> 32; \
133 + __low = __n; \
134 + __asm__( \
135 + " .set push \n" \
136 + " .set noat \n" \
137 + " .set noreorder \n" \
138 + " move %2, $0 \n" \
139 + " move %3, $0 \n" \
140 + " b 1f \n" \
141 + " li %4, 0x21 \n" \
142 + "0: \n" \
143 + " sll $1, %0, 0x1 \n" \
144 + " srl %3, %0, 0x1f \n" \
145 + " or %0, $1, %5 \n" \
146 + " sll %1, %1, 0x1 \n" \
147 + " sll %2, %2, 0x1 \n" \
148 + "1: \n" \
149 + " bnez %3, 2f \n" \
150 + " sltu %5, %0, %z6 \n" \
151 + " bnez %5, 3f \n" \
152 + "2: \n" \
153 + " addiu %4, %4, -1 \n" \
154 + " subu %0, %0, %z6 \n" \
155 + " addiu %2, %2, 1 \n" \
156 + "3: \n" \
157 + " bnez %4, 0b\n\t" \
158 + " srl %5, %1, 0x1f\n\t" \
159 + " .set pop" \
160 + : "=&r" (__mod32), "=&r" (__tmp), \
161 + "=&r" (__quot32), "=&r" (__cf), \
162 + "=&r" (__i), "=&r" (__tmp2) \
163 + : "Jr" (base), "0" (__high), "1" (__low)); \
164 + \
165 + (__n) = __quot32; \
166 + __mod32; \
167 +})
168
169 -#endif /* (_MIPS_SZLONG == 64) */
170 +#endif /* BITS_PER_LONG == 64 */
171
172 -#endif /* _ASM_DIV64_H */
173 +#endif /* __ASM_DIV64_H */