target/linux/generic/backport-4.14/100-arm-cns3xxx-fix-writing-to-wrong-PCI-registers-after.patch

   1 From 03556dab1cb02d85b50d7be3ee3a3bac001f5991 Mon Sep 17 00:00:00 2001
   2 From: Koen Vandeputte <koen.vandeputte@ncentric.com>
   3 Date: Tue, 18 Dec 2018 12:14:06 +0100
   4 Subject: [PATCH] arm: cns3xxx: fix writing to wrong PCI registers after
   5  alignment
   6
   7 Originally, cns3xxx used it's own functions for mapping, reading and writing registers.
   8
   9 Commit 802b7c06adc7 ("ARM: cns3xxx: Convert PCI to use generic config accessors")
  10 removed the internal PCI config write function in favor of the generic one:
  11
  12 cns3xxx_pci_write_config() --> pci_generic_config_write()
  13
  14 cns3xxx_pci_write_config() expected aligned addresses, being produced by cns3xxx_pci_map_bus()
  15 while the generic one pci_generic_config_write() actually expects the real address
  16 as both the function and hardware are capable of byte-aligned writes.
  17
  18 This currently leads to pci_generic_config_write() writing
  19 to the wrong registers on some ocasions.
  20
  21 First issue seen due to this:
  22
  23 - driver ath9k gets loaded
  24 - The driver wants to write value 0xA8 to register PCI_LATENCY_TIMER, located at 0x0D
  25 - cns3xxx_pci_map_bus() aligns the address to 0x0C
  26 - pci_generic_config_write() effectively writes 0xA8 into register 0x0C (CACHE_LINE_SIZE)
  27
  28 This seems to cause some slight instability when certain PCI devices are used.
  29
  30 Another issue example caused by this this is the PCI bus numbering,
  31 where the primary bus is higher than the secondary, which is impossible.
  32
  33 Before:
  34
  35 00:00.0 PCI bridge: Cavium, Inc. Device 3400 (rev 01) (prog-if 00 [Normal decode])
  36     Flags: bus master, fast devsel, latency 0, IRQ 255
  37     Bus: primary=02, secondary=01, subordinate=ff, sec-latency=0
  38
  39 After fix:
  40
  41 00:00.0 PCI bridge: Cavium, Inc. Device 3400 (rev 01) (prog-if 00 [Normal decode])
  42     Flags: bus master, fast devsel, latency 0, IRQ 255
  43     Bus: primary=00, secondary=01, subordinate=02, sec-latency=0
  44
  45 And very likely some more ..
  46
  47 Fix all by omitting the alignment being done in the mapping function.
  48
  49 Fixes: 802b7c06adc7 ("ARM: cns3xxx: Convert PCI to use generic config accessors")
  50 Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
  51 CC: Arnd Bergmann <arnd@arndb.de>
  52 CC: Bjorn Helgaas <bhelgaas@google.com>
  53 CC: Krzysztof Halasa <khalasa@piap.pl>
  54 CC: Olof Johansson <olof@lixom.net>
  55 CC: Robin Leblon <robin.leblon@ncentric.com>
  56 CC: Rob Herring <robh@kernel.org>
  57 CC: Russell King <linux@armlinux.org.uk>
  58 CC: Tim Harvey <tharvey@gateworks.com>
  59 CC: stable@vger.kernel.org # v4.0+
  60 ---
  61  arch/arm/mach-cns3xxx/pcie.c | 2 +-
  62  1 file changed, 1 insertion(+), 1 deletion(-)
  63
  64 --- a/arch/arm/mach-cns3xxx/pcie.c
  65 +++ b/arch/arm/mach-cns3xxx/pcie.c
  66 @@ -83,7 +83,7 @@ static void __iomem *cns3xxx_pci_map_bus
  67         } else /* remote PCI bus */
  68                 base = cnspci->cfg1_regs + ((busno & 0xf) << 20);
  69
  70 -       return base + (where & 0xffc) + (devfn << 12);
  71 +       return base + where + (devfn << 12);
  72  }
  73
  74  static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,