target/linux/generic/backport-4.9/075-v4.10-0002-net-phy-broadcom-Add-support-for-BCM54612E.patch

   1 From: Xo Wang <xow@google.com>
   2 Date: Fri, 21 Oct 2016 10:20:13 -0700
   3 Subject: [PATCH] net: phy: broadcom: Add support for BCM54612E
   4
   5 This PHY has internal delays enabled after reset. This clears the
   6 internal delay enables unless the interface specifically requests them.
   7
   8 Signed-off-by: Xo Wang <xow@google.com>
   9 Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
  10 Reviewed-by: Joel Stanley <joel@jms.id.au>
  11 Signed-off-by: David S. Miller <davem@davemloft.net>
  12 ---
  13
  14 --- a/drivers/net/phy/broadcom.c
  15 +++ b/drivers/net/phy/broadcom.c
  16 @@ -337,6 +337,41 @@ static int bcm5481_config_aneg(struct ph
  17         return ret;
  18  }
  19
  20 +static int bcm54612e_config_aneg(struct phy_device *phydev)
  21 +{
  22 +       int ret;
  23 +
  24 +       /* First, auto-negotiate. */
  25 +       ret = genphy_config_aneg(phydev);
  26 +
  27 +       /* Clear TX internal delay unless requested. */
  28 +       if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
  29 +           (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
  30 +               /* Disable TXD to GTXCLK clock delay (default set) */
  31 +               /* Bit 9 is the only field in shadow register 00011 */
  32 +               bcm_phy_write_shadow(phydev, 0x03, 0);
  33 +       }
  34 +
  35 +       /* Clear RX internal delay unless requested. */
  36 +       if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
  37 +           (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
  38 +               u16 reg;
  39 +
  40 +               /* Errata: reads require filling in the write selector field */
  41 +               bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
  42 +                                    MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC);
  43 +               reg = phy_read(phydev, MII_BCM54XX_AUX_CTL);
  44 +               /* Disable RXD to RXC delay (default set) */
  45 +               reg &= ~MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW;
  46 +               /* Clear shadow selector field */
  47 +               reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
  48 +               bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
  49 +                                    MII_BCM54XX_AUXCTL_MISC_WREN | reg);
  50 +       }
  51 +
  52 +       return ret;
  53 +}
  54 +
  55  static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
  56  {
  57         int val;
  58 @@ -485,6 +520,18 @@ static struct phy_driver broadcom_driver
  59         .ack_interrupt  = bcm_phy_ack_intr,
  60         .config_intr    = bcm_phy_config_intr,
  61  }, {
  62 +       .phy_id         = PHY_ID_BCM54612E,
  63 +       .phy_id_mask    = 0xfffffff0,
  64 +       .name           = "Broadcom BCM54612E",
  65 +       .features       = PHY_GBIT_FEATURES |
  66 +                         SUPPORTED_Pause | SUPPORTED_Asym_Pause,
  67 +       .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
  68 +       .config_init    = bcm54xx_config_init,
  69 +       .config_aneg    = bcm54612e_config_aneg,
  70 +       .read_status    = genphy_read_status,
  71 +       .ack_interrupt  = bcm_phy_ack_intr,
  72 +       .config_intr    = bcm_phy_config_intr,
  73 +}, {
  74         .phy_id         = PHY_ID_BCM54616S,
  75         .phy_id_mask    = 0xfffffff0,
  76         .name           = "Broadcom BCM54616S",
  77 @@ -600,6 +647,7 @@ static struct mdio_device_id __maybe_unu
  78         { PHY_ID_BCM5411, 0xfffffff0 },
  79         { PHY_ID_BCM5421, 0xfffffff0 },
  80         { PHY_ID_BCM5461, 0xfffffff0 },
  81 +       { PHY_ID_BCM54612E, 0xfffffff0 },
  82         { PHY_ID_BCM54616S, 0xfffffff0 },
  83         { PHY_ID_BCM5464, 0xfffffff0 },
  84         { PHY_ID_BCM5481, 0xfffffff0 },
  85 --- a/include/linux/brcmphy.h
  86 +++ b/include/linux/brcmphy.h
  87 @@ -18,6 +18,7 @@
  88  #define PHY_ID_BCM5421                 0x002060e0
  89  #define PHY_ID_BCM5464                 0x002060b0
  90  #define PHY_ID_BCM5461                 0x002060c0
  91 +#define PHY_ID_BCM54612E               0x03625e60
  92  #define PHY_ID_BCM54616S               0x03625d10
  93  #define PHY_ID_BCM57780                        0x03625d90
  94