target/linux/generic/backport-4.9/075-v4.10-0004-net-phy-broadcom-Add-BCM54810-PHY-entry.patch

   1 From: Jon Mason <jon.mason@broadcom.com>
   2 Date: Fri, 4 Nov 2016 01:10:58 -0400
   3 Subject: [PATCH] net: phy: broadcom: Add BCM54810 PHY entry
   4
   5 The BCM54810 PHY requires some semi-unique configuration, which results
   6 in some additional configuration in addition to the standard config.
   7 Also, some users of the BCM54810 require the PHY lanes to be swapped.
   8 Since there is no way to detect this, add a device tree query to see if
   9 it is applicable.
  10
  11 Inspired-by: Vikas Soni <vsoni@broadcom.com>
  12 Signed-off-by: Jon Mason <jon.mason@broadcom.com>
  13 Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
  14 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
  15 Signed-off-by: David S. Miller <davem@davemloft.net>
  16 ---
  17
  18 --- a/drivers/net/phy/broadcom.c
  19 +++ b/drivers/net/phy/broadcom.c
  20 @@ -18,7 +18,7 @@
  21  #include <linux/module.h>
  22  #include <linux/phy.h>
  23  #include <linux/brcmphy.h>
  24 -
  25 +#include <linux/of.h>
  26
  27  #define BRCM_PHY_MODEL(phydev) \
  28         ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
  29 @@ -45,6 +45,34 @@ static int bcm54xx_auxctl_write(struct p
  30         return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
  31  }
  32
  33 +static int bcm54810_config(struct phy_device *phydev)
  34 +{
  35 +       int rc, val;
  36 +
  37 +       val = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
  38 +       val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
  39 +       rc = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
  40 +                              val);
  41 +       if (rc < 0)
  42 +               return rc;
  43 +
  44 +       val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
  45 +       val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
  46 +       val |= MII_BCM54XX_AUXCTL_MISC_WREN;
  47 +       rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
  48 +                                 val);
  49 +       if (rc < 0)
  50 +               return rc;
  51 +
  52 +       val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
  53 +       val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
  54 +       rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
  55 +       if (rc < 0)
  56 +               return rc;
  57 +
  58 +       return 0;
  59 +}
  60 +
  61  /* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
  62  static int bcm50610_a0_workaround(struct phy_device *phydev)
  63  {
  64 @@ -217,6 +245,12 @@ static int bcm54xx_config_init(struct ph
  65             (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
  66                 bcm54xx_adjust_rxrefclk(phydev);
  67
  68 +       if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
  69 +               err = bcm54810_config(phydev);
  70 +               if (err)
  71 +                       return err;
  72 +       }
  73 +
  74         bcm54xx_phydsp_config(phydev);
  75
  76         return 0;
  77 @@ -314,6 +348,7 @@ static int bcm5482_read_status(struct ph
  78
  79  static int bcm5481_config_aneg(struct phy_device *phydev)
  80  {
  81 +       struct device_node *np = phydev->mdio.dev.of_node;
  82         int ret;
  83
  84         /* Aneg firsly. */
  85 @@ -344,6 +379,14 @@ static int bcm5481_config_aneg(struct ph
  86                 phy_write(phydev, 0x18, reg);
  87         }
  88
  89 +       if (of_property_read_bool(np, "enet-phy-lane-swap")) {
  90 +               /* Lane Swap - Undocumented register...magic! */
  91 +               ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
  92 +                                       0x11B);
  93 +               if (ret < 0)
  94 +                       return ret;
  95 +       }
  96 +
  97         return ret;
  98  }
  99
 100 @@ -578,6 +621,18 @@ static struct phy_driver broadcom_driver
 101         .ack_interrupt  = bcm_phy_ack_intr,
 102         .config_intr    = bcm_phy_config_intr,
 103  }, {
 104 +       .phy_id         = PHY_ID_BCM54810,
 105 +       .phy_id_mask    = 0xfffffff0,
 106 +       .name           = "Broadcom BCM54810",
 107 +       .features       = PHY_GBIT_FEATURES |
 108 +                         SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 109 +       .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 110 +       .config_init    = bcm54xx_config_init,
 111 +       .config_aneg    = bcm5481_config_aneg,
 112 +       .read_status    = genphy_read_status,
 113 +       .ack_interrupt  = bcm_phy_ack_intr,
 114 +       .config_intr    = bcm_phy_config_intr,
 115 +}, {
 116         .phy_id         = PHY_ID_BCM5482,
 117         .phy_id_mask    = 0xfffffff0,
 118         .name           = "Broadcom BCM5482",
 119 @@ -661,6 +716,7 @@ static struct mdio_device_id __maybe_unu
 120         { PHY_ID_BCM54616S, 0xfffffff0 },
 121         { PHY_ID_BCM5464, 0xfffffff0 },
 122         { PHY_ID_BCM5481, 0xfffffff0 },
 123 +       { PHY_ID_BCM54810, 0xfffffff0 },
 124         { PHY_ID_BCM5482, 0xfffffff0 },
 125         { PHY_ID_BCM50610, 0xfffffff0 },
 126         { PHY_ID_BCM50610M, 0xfffffff0 },
 127 --- a/drivers/net/phy/Kconfig
 128 +++ b/drivers/net/phy/Kconfig
 129 @@ -204,7 +204,7 @@ config BROADCOM_PHY
 130         select BCM_NET_PHYLIB
 131         ---help---
 132           Currently supports the BCM5411, BCM5421, BCM5461, BCM54616S, BCM5464,
 133 -         BCM5481 and BCM5482 PHYs.
 134 +         BCM5481, BCM54810 and BCM5482 PHYs.
 135
 136  config CICADA_PHY
 137         tristate "Cicada PHYs"
 138 --- a/include/linux/brcmphy.h
 139 +++ b/include/linux/brcmphy.h
 140 @@ -13,6 +13,7 @@
 141  #define PHY_ID_BCM5241                 0x0143bc30
 142  #define PHY_ID_BCMAC131                        0x0143bc70
 143  #define PHY_ID_BCM5481                 0x0143bca0
 144 +#define PHY_ID_BCM54810                        0x03625d00
 145  #define PHY_ID_BCM5482                 0x0143bcb0
 146  #define PHY_ID_BCM5411                 0x00206070
 147  #define PHY_ID_BCM5421                 0x002060e0
 148 @@ -56,6 +57,7 @@
 149  #define PHY_BRCM_EXT_IBND_TX_ENABLE    0x00002000
 150  #define PHY_BRCM_CLEAR_RGMII_MODE      0x00004000
 151  #define PHY_BRCM_DIS_TXCRXC_NOENRGY    0x00008000
 152 +
 153  /* Broadcom BCM7xxx specific workarounds */
 154  #define PHY_BRCM_7XXX_REV(x)           (((x) >> 8) & 0xff)
 155  #define PHY_BRCM_7XXX_PATCH(x)         ((x) & 0xff)
 156 @@ -111,6 +113,7 @@
 157  #define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC     0x7000
 158  #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC        0x0007
 159  #define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT  12
 160 +#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN  (1 << 8)
 161
 162  #define MII_BCM54XX_AUXCTL_SHDWSEL_MASK        0x0007
 163
 164 @@ -192,6 +195,12 @@
 165  #define BCM5482_SSD_SGMII_SLAVE_EN     0x0002  /* Slave mode enable */
 166  #define BCM5482_SSD_SGMII_SLAVE_AD     0x0001  /* Slave auto-detection */
 167
 168 +/* BCM54810 Registers */
 169 +#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL   (MII_BCM54XX_EXP_SEL_ER + 0x90)
 170 +#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN        (1 << 0)
 171 +#define BCM54810_SHD_CLK_CTL                   0x3
 172 +#define BCM54810_SHD_CLK_CTL_GTXCLK_EN         (1 << 9)
 173 +
 174
 175  /*****************************************************************************/
 176  /* Fast Ethernet Transceiver definitions. */