target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h

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  64
  65 #ifndef __INCmvCtrlEnvSpech
  66 #define __INCmvCtrlEnvSpech
  67
  68 #include "mvDeviceId.h"
  69 #include "mvSysHwConfig.h"
  70
  71 #ifdef __cplusplus
  72 extern "C" {
  73 #endif /* __cplusplus */
  74
  75 #define MV_ARM_SOC
  76 #define SOC_NAME_PREFIX                 "MV88F"
  77
  78
  79 /* units base and port numbers */
  80 #ifdef MV_ASMLANGUAGE
  81 #define XOR_UNIT_BASE(unit)             0x60800
  82 #else
  83 #define MV_XOR_REG_BASE                 0x60000
  84 #define XOR_UNIT_BASE(unit)             ((unit)? 0x60900:0x60800)
  85 #endif
  86
  87 #define TDM_REG_BASE                    0xD0000
  88 #define USB_REG_BASE(dev)               0x50000
  89 #define AUDIO_REG_BASE                  0xA0000
  90 #define SATA_REG_BASE                   0x80000
  91 #define MV_CESA_REG_BASE                0x3D000
  92 #define MV_CESA_TDMA_REG_BASE           0x30000
  93 #define MV_SDIO_REG_BASE                0x90000
  94 #define MV_ETH_REG_BASE(port)           (((port) == 0) ? 0x72000 : 0x76000)
  95 #define MV_UART_CHAN_BASE(chanNum)      (0x12000 + (chanNum * 0x100))
  96 #define DRAM_BASE                       0x0
  97 #define CNTMR_BASE                      0x20300
  98 #define TWSI_SLAVE_BASE(chanNum)        0x11000
  99 #define PEX_IF_BASE(pexIf)              0x40000
 100 #define MPP_REG_BASE                    0x10000
 101 #define TSU_GLOBAL_REG_BASE             0xB4000
 102 #define MAX_AHB_TO_MBUS_REG_BASE        0x20000
 103
 104 #define INTER_REGS_SIZE                 _1M
 105 /* This define describes the TWSI interrupt bit and location */
 106 #define TWSI_CPU_MAIN_INT_CAUSE_REG             0x20200
 107 #define TWSI0_CPU_MAIN_INT_BIT                  (1<<29)
 108 #define TWSI_SPEED                              100000
 109
 110 #define MV_GPP_MAX_GROUP                2
 111 #define MV_CNTMR_MAX_COUNTER            2
 112 #define MV_UART_MAX_CHAN                2
 113 #define MV_XOR_MAX_UNIT                 2
 114 #define MV_XOR_MAX_CHAN                 4 /* total channels for all units together*/
 115 #define MV_XOR_MAX_CHAN_PER_UNIT        2 /* channels for units */
 116 #define MV_SATA_MAX_CHAN                2
 117
 118 #define MV_6281_MPP_MAX_MODULE          2
 119 #define MV_6192_MPP_MAX_MODULE          1
 120 #define MV_6190_MPP_MAX_MODULE          1
 121 #define MV_6180_MPP_MAX_MODULE          2
 122 #define MV_6281_MPP_MAX_GROUP           7
 123 #define MV_6192_MPP_MAX_GROUP           4
 124 #define MV_6190_MPP_MAX_GROUP           4
 125 #define MV_6180_MPP_MAX_GROUP           3
 126
 127 #define MV_DRAM_MAX_CS                  4
 128
 129 /* This define describes the maximum number of supported PCI\PCIX Interfaces*/
 130 #define MV_PCI_MAX_IF           0
 131 #define MV_PCI_START_IF         0
 132
 133 /* This define describes the maximum number of supported PEX Interfaces         */
 134 #define MV_INCLUDE_PEX0
 135 #define MV_DISABLE_PEX_DEVICE_BAR
 136 #define MV_PEX_MAX_IF           1
 137 #define MV_PEX_START_IF         MV_PCI_MAX_IF
 138
 139 /* This define describes the maximum number of supported PCI Interfaces         */
 140 #define MV_PCI_IF_MAX_IF        (MV_PEX_MAX_IF+MV_PCI_MAX_IF)
 141
 142 #define MV_ETH_MAX_PORTS                2
 143 #define MV_6281_ETH_MAX_PORTS           2
 144 #define MV_6192_ETH_MAX_PORTS           2
 145 #define MV_6190_ETH_MAX_PORTS           1
 146 #define MV_6180_ETH_MAX_PORTS           1
 147
 148 #define MV_IDMA_MAX_CHAN                0
 149
 150 #define MV_USB_MAX_PORTS                1
 151
 152 #define MV_USB_VERSION              1
 153
 154
 155 #define MV_6281_NAND                    1
 156 #define MV_6192_NAND                    1
 157 #define MV_6190_NAND                    1
 158 #define MV_6180_NAND                    0
 159
 160 #define MV_6281_SDIO                    1
 161 #define MV_6192_SDIO                    1
 162 #define MV_6190_SDIO                    1
 163 #define MV_6180_SDIO                    1
 164
 165 #define MV_6281_TS                      1
 166 #define MV_6192_TS                      1
 167 #define MV_6190_TS                      0
 168 #define MV_6180_TS                      0
 169
 170 #define MV_6281_AUDIO                   1
 171 #define MV_6192_AUDIO                   1
 172 #define MV_6190_AUDIO                   0
 173 #define MV_6180_AUDIO                   1
 174
 175 #define MV_6281_TDM                     1
 176 #define MV_6192_TDM                     1
 177 #define MV_6190_TDM                     0
 178 #define MV_6180_TDM                     0
 179
 180 #define MV_DEVICE_MAX_CS                4
 181
 182 /* Others */
 183 #define PEX_HOST_BUS_NUM(pciIf)         (pciIf)
 184 #define PEX_HOST_DEV_NUM(pciIf)         0
 185
 186 #define PCI_IO(pciIf)           (PEX0_IO)
 187 #define PCI_MEM(pciIf, memNum)  (PEX0_MEM0)
 188 /* CESA version #2: One channel, 2KB SRAM, TDMA */
 189 #if defined(MV_CESA_CHAIN_MODE_SUPPORT)
 190         #define MV_CESA_VERSION                 3
 191 #else
 192 #define MV_CESA_VERSION                 2
 193 #endif
 194 #define MV_CESA_SRAM_SIZE               2*1024
 195 /* This define describes the maximum number of supported Ethernet ports         */
 196 #define MV_ETH_VERSION                  4
 197 #define MV_ETH_MAX_RXQ                  8
 198 #define MV_ETH_MAX_TXQ                  8
 199 #define MV_ETH_PORT_SGMII               { MV_FALSE, MV_FALSE }
 200 /* This define describes the the support of USB         */
 201 #define MV_USB_VERSION                  1
 202
 203 #define MV_INCLUDE_SDRAM_CS0
 204 #define MV_INCLUDE_SDRAM_CS1
 205 #define MV_INCLUDE_SDRAM_CS2
 206 #define MV_INCLUDE_SDRAM_CS3
 207
 208 #define MV_INCLUDE_DEVICE_CS0
 209 #define MV_INCLUDE_DEVICE_CS1
 210 #define MV_INCLUDE_DEVICE_CS2
 211 #define MV_INCLUDE_DEVICE_CS3
 212
 213 #define MPP_GROUP_1_TYPE {\
 214         {0, 0, 0}, /* Reserved for AUTO */ \
 215         {0x22220000, 0x22222222, 0x2222}, /* TDM */ \
 216         {0x44440000, 0x00044444, 0x0000}, /* AUDIO */ \
 217         {0x33330000, 0x33003333, 0x0033}, /* RGMII */ \
 218         {0x33330000, 0x03333333, 0x0033}, /* GMII */ \
 219         {0x11110000, 0x11111111, 0x0001}, /* TS */ \
 220         {0x33330000, 0x33333333, 0x3333}  /* MII */ \
 221 }
 222
 223 #define MPP_GROUP_2_TYPE {\
 224         {0, 0, 0}, /* Reserved for AUTO */ \
 225         {0x22220000, 0x22222222, 0x22}, /* TDM */ \
 226         {0x44440000, 0x00044444, 0x0}, /* AUDIO */ \
 227         {0, 0, 0}, /* N_A */ \
 228         {0, 0, 0}, /* N_A */ \
 229         {0x11110000, 0x11111111, 0x01}  /* TS */ \
 230 }
 231
 232 #ifndef MV_ASMLANGUAGE
 233
 234 /* This enumerator defines the Marvell Units ID      */
 235 typedef enum _mvUnitId
 236 {
 237     DRAM_UNIT_ID,
 238     PEX_UNIT_ID,
 239     ETH_GIG_UNIT_ID,
 240     USB_UNIT_ID,
 241     IDMA_UNIT_ID,
 242     XOR_UNIT_ID,
 243     SATA_UNIT_ID,
 244     TDM_UNIT_ID,
 245     UART_UNIT_ID,
 246     CESA_UNIT_ID,
 247     SPI_UNIT_ID,
 248     AUDIO_UNIT_ID,
 249     SDIO_UNIT_ID,
 250     TS_UNIT_ID,
 251     MAX_UNITS_ID
 252
 253 }MV_UNIT_ID;
 254
 255 #endif
 256
 257 #endif /* __INCmvCtrlEnvSpech */