target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h

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  64
  65
  66 #ifndef __INCmvDramIfConfigh
  67 #define __INCmvDramIfConfigh
  68
  69 /* includes */
  70
  71 /* defines  */
  72
  73 /* registers defaults values */
  74
  75 #define SDRAM_CONFIG_DV                                 \
  76                 (SDRAM_PERR_WRITE                       |       \
  77                  SDRAM_SRMODE                           |       \
  78                  SDRAM_SRCLK_GATED)
  79
  80 #define SDRAM_DUNIT_CTRL_LOW_DV                 \
  81                 (SDRAM_CTRL_POS_RISE            |       \
  82                  SDRAM_CLK1DRV_NORMAL           |       \
  83                  SDRAM_LOCKEN_ENABLE)
  84
  85 #define SDRAM_ADDR_CTRL_DV          0
  86
  87 #define SDRAM_TIMING_CTRL_LOW_REG_DV    \
  88                 ((0x2 << SDRAM_TRCD_OFFS)       |       \
  89                  (0x2 << SDRAM_TRP_OFFS)        |       \
  90                  (0x1 << SDRAM_TWR_OFFS)        |       \
  91                  (0x0 << SDRAM_TWTR_OFFS)       |       \
  92                  (0x5 << SDRAM_TRAS_OFFS)       |       \
  93                  (0x1 << SDRAM_TRRD_OFFS))
  94 /* TRFC 0x27, TW2W 0x1 */
  95 #define SDRAM_TIMING_CTRL_HIGH_REG_DV   (( 0x7 << SDRAM_TRFC_OFFS )     |\
  96                                         ( 0x2 << SDRAM_TRFC_EXT_OFFS)   |\
  97                                         ( 0x1 << SDRAM_TW2W_OFFS))
  98
  99 #define SDRAM_OPEN_PAGES_CTRL_REG_DV    SDRAM_OPEN_PAGE_EN
 100
 101 /* DDR2 ODT default register values */
 102
 103 /* Presence          Ctrl Low    Ctrl High  Dunit Ctrl   Ext Mode     */
 104 /*      CS0              0x84210000  0x00000000  0x0000780F  0x00000440 */
 105 /*      CS0+CS1          0x84210000  0x00000000  0x0000780F  0x00000440 */
 106 /*      CS0+CS2          0x030C030C  0x00000000  0x0000740F  0x00000404 */
 107 /*      CS0+CS1+CS2      0x030C030C  0x00000000  0x0000740F  0x00000404 */
 108 /*      CS0+CS2+CS3      0x030C030C  0x00000000  0x0000740F  0x00000404 */
 109 /*      CS0+CS1+CS2+CS3  0x030C030C  0x00000000  0x0000740F  0x00000404 */
 110
 111 #define DDR2_ODT_CTRL_LOW_CS0_DV        0x84210000
 112 #define DDR2_ODT_CTRL_HIGH_CS0_DV       0x00000000
 113 #define DDR2_DUNIT_ODT_CTRL_CS0_DV      0x0000780F
 114 #define DDR_SDRAM_EXT_MODE_CS0_DV       0x00000440
 115
 116 #define DDR2_ODT_CTRL_LOW_CS0_CS2_DV    0x030C030C
 117 #define DDR2_ODT_CTRL_HIGH_CS0_CS2_DV   0x00000000
 118 #define DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV  0x0000740F
 119 #define DDR_SDRAM_EXT_MODE_CS0_CS2_DV   0x00000404
 120
 121
 122 /* DDR SDRAM Adderss/Control and Data Pads Calibration default values */
 123 #define DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV  \
 124                 (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS)
 125 #define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV  \
 126                 (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS)
 127
 128
 129 #define DDR1_DATA_PAD_STRENGTH_TYPICAL_DV               \
 130                 (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS)
 131 #define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV               \
 132                 (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS)
 133
 134 /* DDR SDRAM Mode Register default value */
 135 #define DDR1_MODE_REG_DV                        0x00000000
 136 #define DDR2_MODE_REG_DV                        0x00000400
 137
 138 /* DDR SDRAM Timing parameter default values */
 139 #define DDR1_TIMING_LOW_DV           0x11602220
 140 #define DDR1_TIMING_HIGH_DV          0x0000000d
 141
 142 #define DDR2_TIMING_LOW_DV           0x11812220
 143 #define DDR2_TIMING_HIGH_DV          0x0000030f
 144
 145 /* For Guideline (GL# MEM-4) DQS Reference Delay Tuning */
 146 #define FTDLL_DDR1_166MHZ           ((0x1 << 0)    | \
 147                                      (0x7F<< 12)   | \
 148                                      (0x1 << 22))
 149
 150 #define FTDLL_DDR1_133MHZ           FTDLL_DDR1_166MHZ
 151
 152 #define FTDLL_DDR1_200MHZ           ((0x1 << 0)    | \
 153                                      (0x1 << 12)   | \
 154                                      (0x3 << 14)   | \
 155                                      (0x1 << 18)   | \
 156                                      (0x1 << 22))
 157
 158
 159 #define FTDLL_DDR2_166MHZ           ((0x1 << 0)    | \
 160                                      (0x1 << 12)   | \
 161                                      (0x1 << 14)   | \
 162                                      (0x1 << 16)   | \
 163                                      (0x1 << 19)   | \
 164                                      (0xF << 20))
 165
 166 #define FTDLL_DDR2_133MHZ           FTDLL_DDR2_166MHZ
 167
 168 #define FTDLL_DDR2_200MHZ           ((0x1 << 0)    | \
 169                                      (0x1 << 12)   | \
 170                                      (0x1 << 14)   | \
 171                                      (0x1 << 16)   | \
 172                                      (0x1 << 19)   | \
 173                                      (0xF << 20))
 174
 175 #define FTDLL_DDR2_250MHZ            0x445001
 176
 177 /* Orion 1 B1 and above */
 178 #define FTDLL_DDR1_166MHZ_5181_B1    0x45D001
 179
 180 /* Orion nas */
 181 #define FTDLL_DDR2_166MHZ_5182       0x597001
 182
 183 /* Orion 2 D0 and above */
 184 #define FTDLL_DDR1_166MHZ_5281_D0    0x8D0001
 185 #define FTDLL_DDR1_200MHZ_5281_D0    0x8D0001
 186 #define FTDLL_DDR2_166MHZ_5281_D0    0x485001
 187 #define FTDLL_DDR2_200MHZ_5281_D0    0x485001
 188 #define FTDLL_DDR2_250MHZ_5281_D0    0x445001
 189 #define FTDLL_DDR2_200MHZ_5281_D1    0x995001
 190 #define FTDLL_DDR2_250MHZ_5281_D1    0x984801
 191
 192 #endif /* __INCmvDramIfh */