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63 *******************************************************************************/
65 #ifndef __INCmvDramIfRegsh
66 #define __INCmvDramIfRegsh
70 #endif /* __cplusplus */
72 /* DDR SDRAM Controller Address Decode Registers */
73 /* SDRAM CSn Base Address Register (SCBAR) */
74 #define SDRAM_BASE_ADDR_REG(cpu,csNum) (0x1500 + ((csNum) * 8) + ((cpu) * 0x70))
75 #define SCBAR_BASE_OFFS 16
76 #define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS)
77 #define SCBAR_BASE_ALIGNMENT 0x10000
79 /* SDRAM CSn Size Register (SCSR) */
80 #define SDRAM_SIZE_REG(cpu,csNum) (0x1504 + ((csNum) * 8) + ((cpu) * 0x70))
81 #define SCSR_SIZE_OFFS 24
82 #define SCSR_SIZE_MASK (0xff << SCSR_SIZE_OFFS)
83 #define SCSR_SIZE_ALIGNMENT 0x1000000
84 #define SCSR_WIN_EN BIT0
86 /* configuration register */
87 #define SDRAM_CONFIG_REG (DRAM_BASE + 0x1400)
88 #define SDRAM_REFRESH_OFFS 0
89 #define SDRAM_REFRESH_MAX 0x3FFF
90 #define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS)
91 #define SDRAM_DWIDTH_OFFS 15
92 #define SDRAM_DWIDTH_MASK (1 << SDRAM_DWIDTH_OFFS)
93 #define SDRAM_DWIDTH_32BIT (0 << SDRAM_DWIDTH_OFFS)
94 #define SDRAM_DWIDTH_64BIT (1 << SDRAM_DWIDTH_OFFS)
95 #define SDRAM_REGISTERED (1 << 17)
96 #define SDRAM_ECC_OFFS 18
97 #define SDRAM_ECC_MASK (1 << SDRAM_ECC_OFFS)
98 #define SDRAM_ECC_DIS (0 << SDRAM_ECC_OFFS)
99 #define SDRAM_ECC_EN (1 << SDRAM_ECC_OFFS)
100 #define SDRAM_IERR_OFFS 19
101 #define SDRAM_IERR_MASK (1 << SDRAM_IERR_OFFS)
102 #define SDRAM_IERR_REPORTE (0 << SDRAM_IERR_OFFS)
103 #define SDRAM_IERR_IGNORE (1 << SDRAM_IERR_OFFS)
104 #define SDRAM_SRMODE_OFFS 24
105 #define SDRAM_SRMODE_MASK (1 << SDRAM_SRMODE_OFFS)
106 #define SDRAM_SRMODE_POWER (0 << SDRAM_SRMODE_OFFS)
107 #define SDRAM_SRMODE_DRAM (1 << SDRAM_SRMODE_OFFS)
109 /* dunit control low register */
110 #define SDRAM_DUNIT_CTRL_REG (DRAM_BASE + 0x1404)
111 #define SDRAM_2T_OFFS 4
112 #define SDRAM_2T_MASK (1 << SDRAM_2T_OFFS)
113 #define SDRAM_2T_MODE (1 << SDRAM_2T_OFFS)
115 #define SDRAM_SRCLK_OFFS 5
116 #define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS)
117 #define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS)
118 #define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS)
119 #define SDRAM_CTRL_POS_OFFS 6
120 #define SDRAM_CTRL_POS_MASK (1 << SDRAM_CTRL_POS_OFFS)
121 #define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS)
122 #define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS)
123 #define SDRAM_CLK1DRV_OFFS 12
124 #define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS)
125 #define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS)
126 #define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS)
127 #define SDRAM_CLK2DRV_OFFS 13
128 #define SDRAM_CLK2DRV_MASK (1 << SDRAM_CLK2DRV_OFFS)
129 #define SDRAM_CLK2DRV_HIGH_Z (0 << SDRAM_CLK2DRV_OFFS)
130 #define SDRAM_CLK2DRV_NORMAL (1 << SDRAM_CLK2DRV_OFFS)
131 #define SDRAM_SB_OUT_DEL_OFFS 20
132 #define SDRAM_SB_OUT_DEL_MAX 0xf
133 #define SDRAM_SB_OUT_MASK (SDRAM_SB_OUT_DEL_MAX<<SDRAM_SB_OUT_DEL_OFFS)
134 #define SDRAM_SB_IN_DEL_OFFS 24
135 #define SDRAM_SB_IN_DEL_MAX 0xf
136 #define SDRAM_SB_IN_MASK (SDRAM_SB_IN_DEL_MAX<<SDRAM_SB_IN_DEL_OFFS)
138 /* dunit control hight register */
139 #define SDRAM_DUNIT_CTRL_HI_REG (DRAM_BASE + 0x1424)
140 #define SDRAM__D2P_OFFS 7
141 #define SDRAM__D2P_EN (1 << SDRAM__D2P_OFFS)
142 #define SDRAM__P2D_OFFS 8
143 #define SDRAM__P2D_EN (1 << SDRAM__P2D_OFFS)
144 #define SDRAM__ADD_HALF_FCC_OFFS 9
145 #define SDRAM__ADD_HALF_FCC_EN (1 << SDRAM__ADD_HALF_FCC_OFFS)
146 #define SDRAM__PUP_ZERO_SKEW_OFFS 10
147 #define SDRAM__PUP_ZERO_SKEW_EN (1 << SDRAM__PUP_ZERO_SKEW_OFFS)
148 #define SDRAM__WR_MESH_DELAY_OFFS 11
149 #define SDRAM__WR_MESH_DELAY_EN (1 << SDRAM__WR_MESH_DELAY_OFFS)
151 /* sdram timing control low register */
152 #define SDRAM_TIMING_CTRL_LOW_REG (DRAM_BASE + 0x1408)
153 #define SDRAM_TRCD_OFFS 4
154 #define SDRAM_TRCD_MASK (0xF << SDRAM_TRCD_OFFS)
155 #define SDRAM_TRP_OFFS 8
156 #define SDRAM_TRP_MASK (0xF << SDRAM_TRP_OFFS)
157 #define SDRAM_TWR_OFFS 12
158 #define SDRAM_TWR_MASK (0xF << SDRAM_TWR_OFFS)
159 #define SDRAM_TWTR_OFFS 16
160 #define SDRAM_TWTR_MASK (0xF << SDRAM_TWTR_OFFS)
161 #define SDRAM_TRAS_OFFS 0
162 #define SDRAM_TRAS_MASK (0xF << SDRAM_TRAS_OFFS)
163 #define SDRAM_EXT_TRAS_OFFS 20
164 #define SDRAM_EXT_TRAS_MASK (0x1 << SDRAM_EXT_TRAS_OFFS)
165 #define SDRAM_TRRD_OFFS 24
166 #define SDRAM_TRRD_MASK (0xF << SDRAM_TRRD_OFFS)
167 #define SDRAM_TRTP_OFFS 28
168 #define SDRAM_TRTP_MASK (0xF << SDRAM_TRTP_OFFS)
169 #define SDRAM_TRTP_DDR1 (0x1 << SDRAM_TRTP_OFFS)
171 /* sdram timing control high register */
172 #define SDRAM_TIMING_CTRL_HIGH_REG (DRAM_BASE + 0x140c)
173 #define SDRAM_TRFC_OFFS 0
174 #define SDRAM_TRFC_MASK (0x3F << SDRAM_TRFC_OFFS)
175 #define SDRAM_TR2R_OFFS 7
176 #define SDRAM_TR2R_MASK (0x3 << SDRAM_TR2R_OFFS)
177 #define SDRAM_TR2W_W2R_OFFS 9
178 #define SDRAM_TR2W_W2R_MASK (0x3 << SDRAM_TR2W_W2R_OFFS)
179 #define SDRAM_TW2W_OFFS 11
180 #define SDRAM_TW2W_MASK (0x3 << SDRAM_TW2W_OFFS)
182 /* sdram DDR2 timing low register (SD2TLR) */
183 #define SDRAM_DDR2_TIMING_LO_REG (DRAM_BASE + 0x1428)
184 #define SD2TLR_TODT_ON_RD_OFFS 4
185 #define SD2TLR_TODT_ON_RD_MASK (0xF << SD2TLR_TODT_ON_RD_OFFS)
186 #define SD2TLR_TODT_OFF_RD_OFFS 8
187 #define SD2TLR_TODT_OFF_RD_MASK (0xF << SD2TLR_TODT_OFF_RD_OFFS)
188 #define SD2TLR_TODT_ON_CTRL_RD_OFFS 12
189 #define SD2TLR_TODT_ON_CTRL_RD_MASK (0xF << SD2TLR_TODT_ON_CTRL_RD_OFFS)
190 #define SD2TLR_TODT_OFF_CTRL_RD_OFFS 16
191 #define SD2TLR_TODT_OFF_CTRL_RD_MASK (0xF << SD2TLR_TODT_OFF_CTRL_RD_OFFS)
193 /* sdram DDR2 timing high register (SD2TLR) */
194 #define SDRAM_DDR2_TIMING_HI_REG (DRAM_BASE + 0x147C)
195 #define SD2THR_TODT_ON_WR_OFFS 0
196 #define SD2THR_TODT_ON_WR_MASK (0xF << SD2THR_TODT_ON_WR_OFFS)
197 #define SD2THR_TODT_OFF_WR_OFFS 4
198 #define SD2THR_TODT_OFF_WR_MASK (0xF << SD2THR_TODT_OFF_WR_OFFS)
199 #define SD2THR_TODT_ON_CTRL_WR_OFFS 8
200 #define SD2THR_TODT_ON_CTRL_WR_MASK (0xF << SD2THR_TODT_ON_CTRL_WR_OFFS)
201 #define SD2THR_TODT_OFF_CTRL_WR_OFFS 12
202 #define SD2THR_TODT_OFF_CTRL_WR_MASK (0xF << SD2THR_TODT_OFF_CTRL_WR_OFFS)
204 /* address control register */
205 #define SDRAM_ADDR_CTRL_REG (DRAM_BASE + 0x1410)
206 #define SDRAM_ADDRSEL_OFFS(cs) (4 * (cs))
207 #define SDRAM_ADDRSEL_MASK(cs) (0x3 << SDRAM_ADDRSEL_OFFS(cs))
208 #define SDRAM_ADDRSEL_X8(cs) (0x0 << SDRAM_ADDRSEL_OFFS(cs))
209 #define SDRAM_ADDRSEL_X16(cs) (0x1 << SDRAM_ADDRSEL_OFFS(cs))
210 #define SDRAM_DSIZE_OFFS(cs) (2 + 4 * (cs))
211 #define SDRAM_DSIZE_MASK(cs) (0x3 << SDRAM_DSIZE_OFFS(cs))
212 #define SDRAM_DSIZE_256Mb(cs) (0x1 << SDRAM_DSIZE_OFFS(cs))
213 #define SDRAM_DSIZE_512Mb(cs) (0x2 << SDRAM_DSIZE_OFFS(cs))
214 #define SDRAM_DSIZE_1Gb(cs) (0x3 << SDRAM_DSIZE_OFFS(cs))
215 #define SDRAM_DSIZE_2Gb(cs) (0x0 << SDRAM_DSIZE_OFFS(cs))
217 /* SDRAM Open Pages Control registers */
218 #define SDRAM_OPEN_PAGE_CTRL_REG (DRAM_BASE + 0x1414)
219 #define SDRAM_OPEN_PAGE_EN (0 << 0)
220 #define SDRAM_OPEN_PAGE_DIS (1 << 0)
222 /* sdram opertion register */
223 #define SDRAM_OPERATION_REG (DRAM_BASE + 0x1418)
224 #define SDRAM_CMD_OFFS 0
225 #define SDRAM_CMD_MASK (0xF << SDRAM_CMD_OFFS)
226 #define SDRAM_CMD_NORMAL (0x0 << SDRAM_CMD_OFFS)
227 #define SDRAM_CMD_PRECHARGE_ALL (0x1 << SDRAM_CMD_OFFS)
228 #define SDRAM_CMD_REFRESH_ALL (0x2 << SDRAM_CMD_OFFS)
229 #define SDRAM_CMD_REG_SET_CMD (0x3 << SDRAM_CMD_OFFS)
230 #define SDRAM_CMD_EXT_MODE_SET (0x4 << SDRAM_CMD_OFFS)
231 #define SDRAM_CMD_NOP (0x5 << SDRAM_CMD_OFFS)
232 #define SDRAM_CMD_SLF_RFRSH (0x7 << SDRAM_CMD_OFFS)
233 #define SDRAM_CMD_EMRS2_CMD (0x8 << SDRAM_CMD_OFFS)
234 #define SDRAM_CMD_EMRS3_CMD (0x9 << SDRAM_CMD_OFFS)
236 /* sdram mode register */
237 #define SDRAM_MODE_REG (DRAM_BASE + 0x141c)
238 #define SDRAM_BURST_LEN_OFFS 0
239 #define SDRAM_BURST_LEN_MASK (0x7 << SDRAM_BURST_LEN_OFFS)
240 #define SDRAM_BURST_LEN_4 (0x2 << SDRAM_BURST_LEN_OFFS)
241 #define SDRAM_CL_OFFS 4
242 #define SDRAM_CL_MASK (0x7 << SDRAM_CL_OFFS)
243 #define SDRAM_DDR2_CL_3 (0x3 << SDRAM_CL_OFFS)
244 #define SDRAM_DDR2_CL_4 (0x4 << SDRAM_CL_OFFS)
245 #define SDRAM_DDR2_CL_5 (0x5 << SDRAM_CL_OFFS)
246 #define SDRAM_DDR2_CL_6 (0x6 << SDRAM_CL_OFFS)
248 #define SDRAM_TM_OFFS 7
249 #define SDRAM_TM_MASK (1 << SDRAM_TM_OFFS)
250 #define SDRAM_TM_NORMAL (0 << SDRAM_TM_OFFS)
251 #define SDRAM_TM_TEST_MODE (1 << SDRAM_TM_OFFS)
252 #define SDRAM_DLL_OFFS 8
253 #define SDRAM_DLL_MASK (1 << SDRAM_DLL_OFFS)
254 #define SDRAM_DLL_NORMAL (0 << SDRAM_DLL_OFFS)
255 #define SDRAM_DLL_RESET (1 << SDRAM_DLL_OFFS)
256 #define SDRAM_WR_OFFS 9
257 #define SDRAM_WR_MAX 7
258 #define SDRAM_WR_MASK (SDRAM_WR_MAX << SDRAM_WR_OFFS)
259 #define SDRAM_WR_2_CYC (1 << SDRAM_WR_OFFS)
260 #define SDRAM_WR_3_CYC (2 << SDRAM_WR_OFFS)
261 #define SDRAM_WR_4_CYC (3 << SDRAM_WR_OFFS)
262 #define SDRAM_WR_5_CYC (4 << SDRAM_WR_OFFS)
263 #define SDRAM_WR_6_CYC (5 << SDRAM_WR_OFFS)
264 #define SDRAM_PD_OFFS 12
265 #define SDRAM_PD_MASK (1 << SDRAM_PD_OFFS)
266 #define SDRAM_PD_FAST_EXIT (0 << SDRAM_PD_OFFS)
267 #define SDRAM_PD_SLOW_EXIT (1 << SDRAM_PD_OFFS)
269 /* DDR SDRAM Extended Mode register (DSEMR) */
270 #define SDRAM_EXTENDED_MODE_REG (DRAM_BASE + 0x1420)
271 #define DSEMR_DLL_ENABLE 0
272 #define DSEMR_DLL_DISABLE 1
273 #define DSEMR_DS_OFFS 1
274 #define DSEMR_DS_MASK (1 << DSEMR_DS_OFFS)
275 #define DSEMR_DS_NORMAL (0 << DSEMR_DS_OFFS)
276 #define DSEMR_DS_REDUCED (1 << DSEMR_DS_OFFS)
277 #define DSEMR_QOFF_OUTPUT_BUFF_EN (0 << 12)
278 #define DSEMR_RTT0_OFFS 2
279 #define DSEMR_RTT1_OFFS 6
280 #define DSEMR_RTT_ODT_DISABLE ((0 << DSEMR_RTT0_OFFS)||(0 << DSEMR_RTT1_OFFS))
281 #define DSEMR_RTT_ODT_75_OHM ((1 << DSEMR_RTT0_OFFS)||(0 << DSEMR_RTT1_OFFS))
282 #define DSEMR_RTT_ODT_150_OHM ((0 << DSEMR_RTT0_OFFS)||(1 << DSEMR_RTT1_OFFS))
283 #define DSEMR_RTT_ODT_50_OHM ((1 << DSEMR_RTT0_OFFS)||(1 << DSEMR_RTT1_OFFS))
284 #define DSEMR_DQS_OFFS 10
285 #define DSEMR_DQS_MASK (1 << DSEMR_DQS_OFFS)
286 #define DSEMR_DQS_DIFFERENTIAL (0 << DSEMR_DQS_OFFS)
287 #define DSEMR_DQS_SINGLE_ENDED (1 << DSEMR_DQS_OFFS)
288 #define DSEMR_RDQS_ENABLE (1 << 11)
289 #define DSEMR_QOFF_OUTPUT_BUFF_EN (0 << 12)
290 #define DSEMR_QOFF_OUTPUT_BUFF_DIS (1 << 12)
292 /* DDR SDRAM Operation Control Register */
293 #define SDRAM_OPERATION_CTRL_REG (DRAM_BASE + 0x142c)
295 /* Dunit FTDLL Configuration Register */
296 #define SDRAM_FTDLL_CONFIG_LEFT_REG (DRAM_BASE + 0x1484)
297 #define SDRAM_FTDLL_CONFIG_RIGHT_REG (DRAM_BASE + 0x161C)
298 #define SDRAM_FTDLL_CONFIG_UP_REG (DRAM_BASE + 0x1620)
300 /* Pads Calibration register */
301 #define SDRAM_ADDR_CTRL_PADS_CAL_REG (DRAM_BASE + 0x14c0)
302 #define SDRAM_DATA_PADS_CAL_REG (DRAM_BASE + 0x14c4)
303 #define SDRAM_DRVN_OFFS 0
304 #define SDRAM_DRVN_MASK (0x3F << SDRAM_DRVN_OFFS)
305 #define SDRAM_DRVP_OFFS 6
306 #define SDRAM_DRVP_MASK (0x3F << SDRAM_DRVP_OFFS)
307 #define SDRAM_PRE_DRIVER_STRENGTH_OFFS 12
308 #define SDRAM_PRE_DRIVER_STRENGTH_MASK (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS)
309 #define SDRAM_TUNE_EN BIT16
310 #define SDRAM_LOCKN_OFFS 17
311 #define SDRAM_LOCKN_MAKS (0x3F << SDRAM_LOCKN_OFFS)
312 #define SDRAM_LOCKP_OFFS 23
313 #define SDRAM_LOCKP_MAKS (0x3F << SDRAM_LOCKP_OFFS)
314 #define SDRAM_WR_EN (1 << 31)
316 /* DDR2 SDRAM ODT Control (Low) Register (DSOCLR) */
317 #define DDR2_SDRAM_ODT_CTRL_LOW_REG (DRAM_BASE + 0x1494)
318 #define DSOCLR_ODT_RD_OFFS(odtNum) (odtNum * 4)
319 #define DSOCLR_ODT_RD_MASK(odtNum) (0xf << DSOCLR_ODT_RD_OFFS(odtNum))
320 #define DSOCLR_ODT_RD(odtNum, bank) ((1 << bank) << DSOCLR_ODT_RD_OFFS(odtNum))
321 #define DSOCLR_ODT_WR_OFFS(odtNum) (16 + (odtNum * 4))
322 #define DSOCLR_ODT_WR_MASK(odtNum) (0xf << DSOCLR_ODT_WR_OFFS(odtNum))
323 #define DSOCLR_ODT_WR(odtNum, bank) ((1 << bank) << DSOCLR_ODT_WR_OFFS(odtNum))
325 /* DDR2 SDRAM ODT Control (High) Register (DSOCHR) */
326 #define DDR2_SDRAM_ODT_CTRL_HIGH_REG (DRAM_BASE + 0x1498)
327 /* Optional control values to DSOCHR_ODT_EN macro */
328 #define DDR2_ODT_CTRL_DUNIT 0
329 #define DDR2_ODT_CTRL_NEVER 1
330 #define DDR2_ODT_CTRL_ALWAYS 3
331 #define DSOCHR_ODT_EN_OFFS(odtNum) (odtNum * 2)
332 #define DSOCHR_ODT_EN_MASK(odtNum) (0x3 << DSOCHR_ODT_EN_OFFS(odtNum))
333 #define DSOCHR_ODT_EN(odtNum, ctrl) (ctrl << DSOCHR_ODT_EN_OFFS(odtNum))
335 /* DDR2 Dunit ODT Control Register (DDOCR)*/
336 #define DDR2_DUNIT_ODT_CONTROL_REG (DRAM_BASE + 0x149c)
337 #define DDOCR_ODT_RD_OFFS 0
338 #define DDOCR_ODT_RD_MASK (0xf << DDOCR_ODT_RD_OFFS)
339 #define DDOCR_ODT_RD(bank) ((1 << bank) << DDOCR_ODT_RD_OFFS)
340 #define DDOCR_ODT_WR_OFFS 4
341 #define DDOCR_ODT_WR_MASK (0xf << DDOCR_ODT_WR_OFFS)
342 #define DDOCR_ODT_WR(bank) ((1 << bank) << DDOCR_ODT_WR_OFFS)
343 #define DSOCR_ODT_EN_OFFS 8
344 #define DSOCR_ODT_EN_MASK (0x3 << DSOCR_ODT_EN_OFFS)
345 /* For ctrl parameters see DDR2 SDRAM ODT Control (High) Register (0x1498) above. */
346 #define DSOCR_ODT_EN(ctrl) (ctrl << DSOCR_ODT_EN_OFFS)
347 #define DSOCR_ODT_SEL_DISABLE 0
348 #define DSOCR_ODT_SEL_75_OHM 2
349 #define DSOCR_ODT_SEL_150_OHM 1
350 #define DSOCR_ODT_SEL_50_OHM 3
351 #define DSOCR_DQ_ODT_SEL_OFFS 10
352 #define DSOCR_DQ_ODT_SEL_MASK (0x3 << DSOCR_DQ_ODT_SEL_OFFS)
353 #define DSOCR_DQ_ODT_SEL(odtSel) (odtSel << DSOCR_DQ_ODT_SEL_OFFS)
354 #define DSOCR_ST_ODT_SEL_OFFS 12
355 #define DSOCR_ST_ODT_SEL_MASK (0x3 << DSOCR_ST_ODT_SEL_OFFS)
356 #define DSOCR_ST_ODT_SEL(odtSel) (odtSel << DSOCR_ST_ODT_SEL_OFFS)
357 #define DSOCR_ST_ODT_EN (1 << 14)
359 /* DDR SDRAM Initialization Control Register (DSICR) */
360 #define DDR_SDRAM_INIT_CTRL_REG (DRAM_BASE + 0x1480)
361 #define DSICR_INIT_EN (1 << 0)
362 #define DSICR_T200_SET (1 << 8)
364 /* sdram extended mode2 register (SEM2R) */
365 #define SDRAM_EXTENDED_MODE2_REG (DRAM_BASE + 0x148C)
366 #define SEM2R_EMRS2_DDR2_OFFS 0
367 #define SEM2R_EMRS2_DDR2_MASK (0x7FFF << SEM2R_EMRS2_DDR2_OFFS)
369 /* sdram extended mode3 register (SEM3R) */
370 #define SDRAM_EXTENDED_MODE3_REG (DRAM_BASE + 0x1490)
371 #define SEM3R_EMRS3_DDR2_OFFS 0
372 #define SEM3R_EMRS3_DDR2_MASK (0x7FFF << SEM3R_EMRS3_DDR2_OFFS)
374 /* sdram error registers */
375 #define SDRAM_ERROR_CAUSE_REG (DRAM_BASE + 0x14d0)
376 #define SDRAM_ERROR_MASK_REG (DRAM_BASE + 0x14d4)
377 #define SDRAM_ERROR_DATA_LOW_REG (DRAM_BASE + 0x1444)
378 #define SDRAM_ERROR_DATA_HIGH_REG (DRAM_BASE + 0x1440)
379 #define SDRAM_ERROR_ADDR_REG (DRAM_BASE + 0x1450)
380 #define SDRAM_ERROR_ECC_REG (DRAM_BASE + 0x1448)
381 #define SDRAM_CALC_ECC_REG (DRAM_BASE + 0x144c)
382 #define SDRAM_ECC_CONTROL_REG (DRAM_BASE + 0x1454)
383 #define SDRAM_SINGLE_BIT_ERR_CNTR_REG (DRAM_BASE + 0x1458)
384 #define SDRAM_DOUBLE_BIT_ERR_CNTR_REG (DRAM_BASE + 0x145c)
386 /* SDRAM Error Cause Register (SECR) */
387 #define SECR_SINGLE_BIT_ERR BIT0
388 #define SECR_DOUBLE_BIT_ERR BIT1
389 #define SECR_DATA_PATH_PARITY_ERR BIT2
390 /* SDRAM Error Address Register (SEAR) */
391 #define SEAR_ERR_TYPE_OFFS 0
392 #define SEAR_ERR_TYPE_MASK (1 << SEAR_ERR_TYPE_OFFS)
393 #define SEAR_ERR_TYPE_SINGLE 0
394 #define SEAR_ERR_TYPE_DOUBLE (1 << SEAR_ERR_TYPE_OFFS)
395 #define SEAR_ERR_CS_OFFS 1
396 #define SEAR_ERR_CS_MASK (3 << SEAR_ERR_CS_OFFS)
397 #define SEAR_ERR_CS(csNum) (csNum << SEAR_ERR_CS_OFFS)
398 #define SEAR_ERR_ADDR_OFFS 3
399 #define SEAR_ERR_ADDR_MASK (0x1FFFFFFF << SEAR_ERR_ADDR_OFFS)
401 /* SDRAM ECC Control Register (SECR) */
402 #define SECR_FORCEECC_OFFS 0
403 #define SECR_FORCEECC_MASK (0xFF << SECR_FORCEECC_OFFS)
404 #define SECR_FORCEEN_OFFS 8
405 #define SECR_FORCEEN_MASK (1 << SECR_FORCEEN_OFFS)
406 #define SECR_ECC_CALC_MASK (0 << SECR_FORCEEN_OFFS)
407 #define SECR_ECC_USER_MASK (1 << SECR_FORCEEN_OFFS)
408 #define SECR_PERRPROP_EN BIT9
409 #define SECR_CNTMODE_OFFS 10
410 #define SECR_CNTMODE_MASK (1 << SECR_CNTMODE_OFFS)
411 #define SECR_ALL_IN_CS0 (0 << SECR_CNTMODE_OFFS)
412 #define SECR_NORMAL_COUNTER (1 << SECR_CNTMODE_OFFS)
413 #define SECR_THRECC_OFFS 16
414 #define SECR_THRECC_MAX 0xFF
415 #define SECR_THRECC_MASK (SECR_THRECC_MAX << SECR_THRECC_OFFS)
416 #define SECR_THRECC(threshold) (threshold << SECR_THRECC_OFFS)
421 #endif /* __cplusplus */
423 #endif /* __INCmvDramIfRegsh */
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