target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h

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  64
  65 #ifndef __INCPCIIFREGSH
  66 #define __INCPCIIFREGSH
  67
  68
  69 /* defines */
  70 #define MAX_PCI_DEVICES         32
  71 #define MAX_PCI_FUNCS           8
  72 #define MAX_PCI_BUSSES          128
  73
  74 /***************************************/
  75 /* PCI Configuration registers */
  76 /***************************************/
  77
  78 /*********************************************/
  79 /* PCI Configuration, Function 0, Registers  */
  80 /*********************************************/
  81
  82
  83 /* Standard registers */
  84 #define PCI_DEVICE_AND_VENDOR_ID                                        0x000
  85 #define PCI_STATUS_AND_COMMAND                                          0x004
  86 #define PCI_CLASS_CODE_AND_REVISION_ID                      0x008
  87 #define PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE            0x00C
  88 #define PCI_MEMORY_BAR_BASE_ADDR(barNum)                        (0x010 + ((barNum) << 2))
  89 #define PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID                      0x02C
  90 #define PCI_EXPANSION_ROM_BASE_ADDR_REG                     0x030
  91 #define PCI_CAPABILTY_LIST_POINTER                              0x034
  92 #define PCI_INTERRUPT_PIN_AND_LINE                                      0x03C
  93
  94
  95 /* PCI Device and Vendor ID Register (PDVIR) */
  96 #define PDVIR_VEN_ID_OFFS                       0       /* Vendor ID */
  97 #define PDVIR_VEN_ID_MASK                       (0xffff << PDVIR_VEN_ID_OFFS)
  98
  99 #define PDVIR_DEV_ID_OFFS                       16      /* Device ID */
 100 #define PDVIR_DEV_ID_MASK                       (0xffff << PDVIR_DEV_ID_OFFS)
 101
 102 /* PCI Status and Command Register (PSCR) */
 103 #define PSCR_IO_EN                      BIT0    /* IO Enable                                                      */
 104 #define PSCR_MEM_EN                     BIT1    /* Memory Enable                                                  */
 105 #define PSCR_MASTER_EN          BIT2    /* Master Enable                                                  */
 106 #define PSCR_SPECIAL_EN         BIT3    /* Special Cycle Enable                                   */
 107 #define PSCR_MEM_WRI_INV        BIT4    /* Memory Write and Invalidate Enable     */
 108 #define PSCR_VGA                        BIT5    /* VGA Palette Snoops                                     */
 109 #define PSCR_PERR_EN            BIT6    /* Parity Errors Respond Enable                   */
 110 #define PSCR_ADDR_STEP          BIT7    /* Address Stepping Enable (Wait Cycle En)*/
 111 #define PSCR_SERR_EN            BIT8    /* Ability to assert SERR# line                   */
 112 #define PSCR_FAST_BTB_EN        BIT9    /* generate fast back-to-back transactions*/
 113 #define PSCR_CAP_LIST           BIT20   /* Capability List Support                                */
 114 #define PSCR_66MHZ_EN           BIT21   /* 66 MHz Capable                                                 */
 115 #define PSCR_UDF_EN                     BIT22   /* User definable features                                */
 116 #define PSCR_TAR_FAST_BB        BIT23   /* fast back-to-back transactions capable */
 117 #define PSCR_DATA_PERR          BIT24   /* Data Parity reported                                   */
 118
 119 #define PSCR_DEVSEL_TIM_OFFS    25  /* DEVSEL timing */
 120 #define PSCR_DEVSEL_TIM_MASK    (0x3 << PSCR_DEVSEL_TIM_OFFS)
 121 #define PSCR_DEVSEL_TIM_FAST    (0x0 << PSCR_DEVSEL_TIM_OFFS)
 122 #define PSCR_DEVSEL_TIM_MED     (0x1 << PSCR_DEVSEL_TIM_OFFS)
 123 #define PSCR_DEVSEL_TIM_SLOW    (0x2 << PSCR_DEVSEL_TIM_OFFS)
 124
 125 #define PSCR_SLAVE_TABORT       BIT27   /* Signalled Target Abort       */
 126 #define PSCR_MASTER_TABORT      BIT28   /* Recieved Target Abort        */
 127 #define PSCR_MABORT                     BIT29   /* Recieved Master Abort        */
 128 #define PSCR_SYSERR                     BIT30   /* Signalled system error       */
 129 #define PSCR_DET_PARERR         BIT31   /* Detect Parity Error          */
 130
 131 /*      PCI configuration register offset=0x08 fields
 132         (PCI_CLASS_CODE_AND_REVISION_ID)(PCCRI)                                 */
 133
 134 #define PCCRIR_REVID_OFFS               0               /* Revision ID */
 135 #define PCCRIR_REVID_MASK               (0xff << PCCRIR_REVID_OFFS)
 136
 137 #define PCCRIR_FULL_CLASS_OFFS  8               /* Full Class Code */
 138 #define PCCRIR_FULL_CLASS_MASK  (0xffffff << PCCRIR_FULL_CLASS_OFFS)
 139
 140 #define PCCRIR_PROGIF_OFFS              8               /* Prog .I/F*/
 141 #define PCCRIR_PROGIF_MASK              (0xff << PCCRIR_PROGIF_OFFS)
 142
 143 #define PCCRIR_SUB_CLASS_OFFS   16              /* Sub Class*/
 144 #define PCCRIR_SUB_CLASS_MASK   (0xff << PCCRIR_SUB_CLASS_OFFS)
 145
 146 #define PCCRIR_BASE_CLASS_OFFS  24              /* Base Class*/
 147 #define PCCRIR_BASE_CLASS_MASK  (0xff << PCCRIR_BASE_CLASS_OFFS)
 148
 149 /*      PCI configuration register offset=0x0C fields
 150         (PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE)(PBHTLTCL)                               */
 151
 152 #define PBHTLTCLR_CACHELINE_OFFS                0       /* Specifies the cache line size */
 153 #define PBHTLTCLR_CACHELINE_MASK                (0xff << PBHTLTCLR_CACHELINE_OFFS)
 154
 155 #define PBHTLTCLR_LATTIMER_OFFS                 8       /* latency timer */
 156 #define PBHTLTCLR_LATTIMER_MASK                 (0xff << PBHTLTCLR_LATTIMER_OFFS)
 157
 158 #define PBHTLTCLR_HEADTYPE_FULL_OFFS    16      /* Full Header Type */
 159 #define PBHTLTCLR_HEADTYPE_FULL_MASK    (0xff << PBHTLTCLR_HEADTYPE_FULL_OFFS)
 160
 161 #define PBHTLTCLR_MULTI_FUNC                    BIT23   /* Multi/Single function */
 162
 163 #define PBHTLTCLR_HEADER_OFFS                   16              /* Header type */
 164 #define PBHTLTCLR_HEADER_MASK                   (0x7f << PBHTLTCLR_HEADER_OFFS)
 165 #define PBHTLTCLR_HEADER_STANDARD               (0x0 << PBHTLTCLR_HEADER_OFFS)
 166 #define PBHTLTCLR_HEADER_PCI2PCI_BRIDGE (0x1 << PBHTLTCLR_HEADER_OFFS)
 167
 168
 169 #define PBHTLTCLR_BISTCOMP_OFFS         24      /* BIST Completion Code */
 170 #define PBHTLTCLR_BISTCOMP_MASK         (0xf << PBHTLTCLR_BISTCOMP_OFFS)
 171
 172 #define PBHTLTCLR_BISTACT                       BIT30   /* BIST Activate bit */
 173 #define PBHTLTCLR_BISTCAP                       BIT31   /* BIST Capable Bit */
 174
 175
 176 /* PCI Bar Base Low Register (PBBLR) */
 177 #define PBBLR_IOSPACE                   BIT0    /* Memory Space Indicator */
 178
 179 #define PBBLR_TYPE_OFFS                 1          /* BAR Type/Init Val. */
 180 #define PBBLR_TYPE_MASK                 (0x3 << PBBLR_TYPE_OFFS)
 181 #define PBBLR_TYPE_32BIT_ADDR   (0x0 << PBBLR_TYPE_OFFS)
 182 #define PBBLR_TYPE_64BIT_ADDR   (0x2 << PBBLR_TYPE_OFFS)
 183
 184 #define PBBLR_PREFETCH_EN               BIT3    /* Prefetch Enable */
 185
 186
 187 #define PBBLR_MEM_BASE_OFFS             4       /* Memory Bar Base address. Corresponds to
 188                                                                         address bits [31:4] */
 189 #define PBBLR_MEM_BASE_MASK             (0xfffffff << PBBLR_MEM_BASE_OFFS)
 190
 191 #define PBBLR_IO_BASE_OFFS              2       /* IO Bar Base address. Corresponds to
 192                                                                                 address bits [31:2] */
 193 #define PBBLR_IO_BASE_MASK              (0x3fffffff << PBBLR_IO_BASE_OFFS)
 194
 195
 196 #define PBBLR_BASE_OFFS                 12              /* Base address. Address bits [31:12] */
 197 #define PBBLR_BASE_MASK                 (0xfffff << PBBLR_BASE_OFFS)
 198 #define PBBLR_BASE_ALIGNMET             (1 << PBBLR_BASE_OFFS)
 199
 200
 201 /* PCI Bar Base High Fegister (PBBHR) */
 202 #define PBBHR_BASE_OFFS                 0               /* Base address. Address bits [31:12] */
 203 #define PBBHR_BASE_MASK                 (0xffffffff << PBBHR_BASE_OFFS)
 204
 205
 206 /*      PCI configuration register offset=0x2C fields
 207         (PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID)(PSISVI)                              */
 208
 209 #define PSISVIR_VENID_OFFS      0       /* Subsystem Manufacturer Vendor ID Number */
 210 #define PSISVIR_VENID_MASK      (0xffff << PSISVIR_VENID_OFFS)
 211
 212 #define PSISVIR_DEVID_OFFS      16      /* Subsystem Device ID Number */
 213 #define PSISVIR_DEVID_MASK      (0xffff << PSISVIR_DEVID_OFFS)
 214
 215 /*      PCI configuration register offset=0x30 fields
 216         (PCI_EXPANSION_ROM_BASE_ADDR_REG)(PERBA)                                */
 217
 218 #define PERBAR_EXPROMEN         BIT0    /* Expansion ROM Enable */
 219
 220 #define PERBAR_BASE_OFFS                12              /* Expansion ROM Base Address */
 221 #define PERBAR_BASE_MASK                (0xfffff << PERBAR_BASE_OFFS)
 222
 223 /*      PCI configuration register offset=0x34 fields
 224         (PCI_CAPABILTY_LIST_POINTER)(PCLP)                              */
 225
 226 #define PCLPR_CAPPTR_OFFS       0               /* Capability List Pointer */
 227 #define PCLPR_CAPPTR_MASK       (0xff << PCLPR_CAPPTR_OFFS)
 228
 229 /*      PCI configuration register offset=0x3C fields
 230         (PCI_INTERRUPT_PIN_AND_LINE)(PIPL)                              */
 231
 232 #define PIPLR_INTLINE_OFFS      0       /* Interrupt line (IRQ) */
 233 #define PIPLR_INTLINE_MASK      (0xff << PIPLR_INTLINE_OFFS)
 234
 235 #define PIPLR_INTPIN_OFFS       8       /* interrupt pin (A,B,C,D) */
 236 #define PIPLR_INTPIN_MASK       (0xff << PIPLR_INTPIN_OFFS)
 237
 238 #define PIPLR_MINGRANT_OFFS     16      /* Minimum Grant on 250 nano seconds units */
 239 #define PIPLR_MINGRANT_MASK     (0xff << PIPLR_MINGRANT_OFFS)
 240
 241 #define PIPLR_MAXLATEN_OFFS     24      /* Maximum latency on 250 nano seconds units */
 242 #define PIPLR_MAXLATEN_MASK     (0xff << PIPLR_MAXLATEN_OFFS)
 243
 244 #endif /* #ifndef __INCPCIIFREGSH */
 245