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0b0348bfdf8f4af59418bc4033c08b3ee425da34
[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/of_device.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_net.h>
29 #include <linux/bitops.h>
30 #include <net/genetlink.h>
31 #include <linux/switch.h>
32 #include <linux/delay.h>
33 #include <linux/phy.h>
34 #include <linux/etherdevice.h>
35 #include <linux/lockdep.h>
36 #include <linux/ar8216_platform.h>
37 #include <linux/workqueue.h>
38 #include <linux/version.h>
39
40 #include "ar8216.h"
41
42 extern const struct ar8xxx_chip ar8327_chip;
43 extern const struct ar8xxx_chip ar8337_chip;
44
45 #define MIB_DESC_BASIC(_s , _o, _n) \
46 { \
47 .size = (_s), \
48 .offset = (_o), \
49 .name = (_n), \
50 .type = AR8XXX_MIB_BASIC, \
51 }
52
53 #define MIB_DESC_EXT(_s , _o, _n) \
54 { \
55 .size = (_s), \
56 .offset = (_o), \
57 .name = (_n), \
58 .type = AR8XXX_MIB_EXTENDED, \
59 }
60
61 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
62 MIB_DESC_EXT(1, AR8216_STATS_RXBROAD, "RxBroad"),
63 MIB_DESC_EXT(1, AR8216_STATS_RXPAUSE, "RxPause"),
64 MIB_DESC_EXT(1, AR8216_STATS_RXMULTI, "RxMulti"),
65 MIB_DESC_EXT(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
66 MIB_DESC_EXT(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
67 MIB_DESC_EXT(1, AR8216_STATS_RXRUNT, "RxRunt"),
68 MIB_DESC_EXT(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
69 MIB_DESC_EXT(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
70 MIB_DESC_EXT(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
71 MIB_DESC_EXT(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
72 MIB_DESC_EXT(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
73 MIB_DESC_EXT(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
74 MIB_DESC_EXT(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
75 MIB_DESC_EXT(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
76 MIB_DESC_BASIC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
77 MIB_DESC_EXT(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
78 MIB_DESC_EXT(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
79 MIB_DESC_EXT(1, AR8216_STATS_FILTERED, "Filtered"),
80 MIB_DESC_EXT(1, AR8216_STATS_TXBROAD, "TxBroad"),
81 MIB_DESC_EXT(1, AR8216_STATS_TXPAUSE, "TxPause"),
82 MIB_DESC_EXT(1, AR8216_STATS_TXMULTI, "TxMulti"),
83 MIB_DESC_EXT(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
84 MIB_DESC_EXT(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
85 MIB_DESC_EXT(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
86 MIB_DESC_EXT(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
87 MIB_DESC_EXT(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
88 MIB_DESC_EXT(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
89 MIB_DESC_EXT(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
90 MIB_DESC_EXT(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
91 MIB_DESC_BASIC(2, AR8216_STATS_TXBYTE, "TxByte"),
92 MIB_DESC_EXT(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
93 MIB_DESC_EXT(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
94 MIB_DESC_EXT(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
95 MIB_DESC_EXT(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
96 MIB_DESC_EXT(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
97 MIB_DESC_EXT(1, AR8216_STATS_TXDEFER, "TxDefer"),
98 MIB_DESC_EXT(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
99 };
100
101 const struct ar8xxx_mib_desc ar8236_mibs[39] = {
102 MIB_DESC_EXT(1, AR8236_STATS_RXBROAD, "RxBroad"),
103 MIB_DESC_EXT(1, AR8236_STATS_RXPAUSE, "RxPause"),
104 MIB_DESC_EXT(1, AR8236_STATS_RXMULTI, "RxMulti"),
105 MIB_DESC_EXT(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
106 MIB_DESC_EXT(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
107 MIB_DESC_EXT(1, AR8236_STATS_RXRUNT, "RxRunt"),
108 MIB_DESC_EXT(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
109 MIB_DESC_EXT(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
110 MIB_DESC_EXT(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
111 MIB_DESC_EXT(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
112 MIB_DESC_EXT(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
113 MIB_DESC_EXT(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
114 MIB_DESC_EXT(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
115 MIB_DESC_EXT(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
116 MIB_DESC_EXT(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
117 MIB_DESC_BASIC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
118 MIB_DESC_EXT(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
119 MIB_DESC_EXT(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
120 MIB_DESC_EXT(1, AR8236_STATS_FILTERED, "Filtered"),
121 MIB_DESC_EXT(1, AR8236_STATS_TXBROAD, "TxBroad"),
122 MIB_DESC_EXT(1, AR8236_STATS_TXPAUSE, "TxPause"),
123 MIB_DESC_EXT(1, AR8236_STATS_TXMULTI, "TxMulti"),
124 MIB_DESC_EXT(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
125 MIB_DESC_EXT(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
126 MIB_DESC_EXT(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
127 MIB_DESC_EXT(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
128 MIB_DESC_EXT(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
129 MIB_DESC_EXT(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
130 MIB_DESC_EXT(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
131 MIB_DESC_EXT(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
132 MIB_DESC_EXT(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
133 MIB_DESC_BASIC(2, AR8236_STATS_TXBYTE, "TxByte"),
134 MIB_DESC_EXT(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
135 MIB_DESC_EXT(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
136 MIB_DESC_EXT(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
137 MIB_DESC_EXT(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
138 MIB_DESC_EXT(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
139 MIB_DESC_EXT(1, AR8236_STATS_TXDEFER, "TxDefer"),
140 MIB_DESC_EXT(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
141 };
142
143 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
144 static LIST_HEAD(ar8xxx_dev_list);
145
146 static void
147 ar8xxx_mib_start(struct ar8xxx_priv *priv);
148 static void
149 ar8xxx_mib_stop(struct ar8xxx_priv *priv);
150
151 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
152 static int
153 ar8xxx_phy_poll_reset(struct mii_bus *bus)
154 {
155 unsigned int sleep_msecs = 20;
156 int ret, elapsed, i;
157
158 for (elapsed = sleep_msecs; elapsed <= 600;
159 elapsed += sleep_msecs) {
160 msleep(sleep_msecs);
161 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
162 ret = mdiobus_read(bus, i, MII_BMCR);
163 if (ret < 0)
164 return ret;
165 if (ret & BMCR_RESET)
166 break;
167 if (i == AR8XXX_NUM_PHYS - 1) {
168 usleep_range(1000, 2000);
169 return 0;
170 }
171 }
172 }
173 return -ETIMEDOUT;
174 }
175
176 static int
177 ar8xxx_phy_check_aneg(struct phy_device *phydev)
178 {
179 int ret;
180
181 if (phydev->autoneg != AUTONEG_ENABLE)
182 return 0;
183 /*
184 * BMCR_ANENABLE might have been cleared
185 * by phy_init_hw in certain kernel versions
186 * therefore check for it
187 */
188 ret = phy_read(phydev, MII_BMCR);
189 if (ret < 0)
190 return ret;
191 if (ret & BMCR_ANENABLE)
192 return 0;
193
194 dev_info(&phydev->mdio.dev, "ANEG disabled, re-enabling ...\n");
195 ret |= BMCR_ANENABLE | BMCR_ANRESTART;
196 return phy_write(phydev, MII_BMCR, ret);
197 }
198
199 void
200 ar8xxx_phy_init(struct ar8xxx_priv *priv)
201 {
202 int i;
203 struct mii_bus *bus;
204
205 bus = priv->sw_mii_bus ?: priv->mii_bus;
206 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
207 if (priv->chip->phy_fixup)
208 priv->chip->phy_fixup(priv, i);
209
210 /* initialize the port itself */
211 mdiobus_write(bus, i, MII_ADVERTISE,
212 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
213 if (ar8xxx_has_gige(priv))
214 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
215 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
216 }
217
218 ar8xxx_phy_poll_reset(bus);
219 }
220
221 u32
222 ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
223 {
224 struct mii_bus *bus = priv->mii_bus;
225 u16 lo, hi;
226
227 lo = bus->read(bus, phy_id, regnum);
228 hi = bus->read(bus, phy_id, regnum + 1);
229
230 return (hi << 16) | lo;
231 }
232
233 void
234 ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
235 {
236 struct mii_bus *bus = priv->mii_bus;
237 u16 lo, hi;
238
239 lo = val & 0xffff;
240 hi = (u16) (val >> 16);
241
242 if (priv->chip->mii_lo_first)
243 {
244 bus->write(bus, phy_id, regnum, lo);
245 bus->write(bus, phy_id, regnum + 1, hi);
246 } else {
247 bus->write(bus, phy_id, regnum + 1, hi);
248 bus->write(bus, phy_id, regnum, lo);
249 }
250 }
251
252 u32
253 ar8xxx_read(struct ar8xxx_priv *priv, int reg)
254 {
255 struct mii_bus *bus = priv->mii_bus;
256 u16 r1, r2, page;
257 u32 val;
258
259 split_addr((u32) reg, &r1, &r2, &page);
260
261 mutex_lock(&bus->mdio_lock);
262
263 bus->write(bus, 0x18, 0, page);
264 wait_for_page_switch();
265 val = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
266
267 mutex_unlock(&bus->mdio_lock);
268
269 return val;
270 }
271
272 void
273 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
274 {
275 struct mii_bus *bus = priv->mii_bus;
276 u16 r1, r2, page;
277
278 split_addr((u32) reg, &r1, &r2, &page);
279
280 mutex_lock(&bus->mdio_lock);
281
282 bus->write(bus, 0x18, 0, page);
283 wait_for_page_switch();
284 ar8xxx_mii_write32(priv, 0x10 | r2, r1, val);
285
286 mutex_unlock(&bus->mdio_lock);
287 }
288
289 u32
290 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
291 {
292 struct mii_bus *bus = priv->mii_bus;
293 u16 r1, r2, page;
294 u32 ret;
295
296 split_addr((u32) reg, &r1, &r2, &page);
297
298 mutex_lock(&bus->mdio_lock);
299
300 bus->write(bus, 0x18, 0, page);
301 wait_for_page_switch();
302
303 ret = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
304 ret &= ~mask;
305 ret |= val;
306 ar8xxx_mii_write32(priv, 0x10 | r2, r1, ret);
307
308 mutex_unlock(&bus->mdio_lock);
309
310 return ret;
311 }
312 void
313 ar8xxx_phy_dbg_read(struct ar8xxx_priv *priv, int phy_addr,
314 u16 dbg_addr, u16 *dbg_data)
315 {
316 struct mii_bus *bus = priv->mii_bus;
317
318 mutex_lock(&bus->mdio_lock);
319 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
320 *dbg_data = bus->read(bus, phy_addr, MII_ATH_DBG_DATA);
321 mutex_unlock(&bus->mdio_lock);
322 }
323
324 void
325 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
326 u16 dbg_addr, u16 dbg_data)
327 {
328 struct mii_bus *bus = priv->mii_bus;
329
330 mutex_lock(&bus->mdio_lock);
331 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
332 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
333 mutex_unlock(&bus->mdio_lock);
334 }
335
336 static inline void
337 ar8xxx_phy_mmd_prep(struct mii_bus *bus, int phy_addr, u16 addr, u16 reg)
338 {
339 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
340 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, reg);
341 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr | 0x4000);
342 }
343
344 void
345 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data)
346 {
347 struct mii_bus *bus = priv->mii_bus;
348
349 mutex_lock(&bus->mdio_lock);
350 ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
351 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
352 mutex_unlock(&bus->mdio_lock);
353 }
354
355 u16
356 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg)
357 {
358 struct mii_bus *bus = priv->mii_bus;
359 u16 data;
360
361 mutex_lock(&bus->mdio_lock);
362 ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
363 data = bus->read(bus, phy_addr, MII_ATH_MMD_DATA);
364 mutex_unlock(&bus->mdio_lock);
365
366 return data;
367 }
368
369 static int
370 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
371 unsigned timeout)
372 {
373 int i;
374
375 for (i = 0; i < timeout; i++) {
376 u32 t;
377
378 t = ar8xxx_read(priv, reg);
379 if ((t & mask) == val)
380 return 0;
381
382 usleep_range(1000, 2000);
383 cond_resched();
384 }
385
386 return -ETIMEDOUT;
387 }
388
389 static int
390 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
391 {
392 unsigned mib_func = priv->chip->mib_func;
393 int ret;
394
395 lockdep_assert_held(&priv->mib_lock);
396
397 /* Capture the hardware statistics for all ports */
398 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
399
400 /* Wait for the capturing to complete. */
401 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
402 if (ret)
403 goto out;
404
405 ret = 0;
406
407 out:
408 return ret;
409 }
410
411 static int
412 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
413 {
414 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
415 }
416
417 static int
418 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
419 {
420 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
421 }
422
423 static void
424 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
425 {
426 unsigned int base;
427 u64 *mib_stats;
428 int i;
429
430 WARN_ON(port >= priv->dev.ports);
431
432 lockdep_assert_held(&priv->mib_lock);
433
434 base = priv->chip->reg_port_stats_start +
435 priv->chip->reg_port_stats_length * port;
436
437 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
438 for (i = 0; i < priv->chip->num_mibs; i++) {
439 const struct ar8xxx_mib_desc *mib;
440 u64 t;
441
442 mib = &priv->chip->mib_decs[i];
443 if (mib->type > priv->mib_type)
444 continue;
445 t = ar8xxx_read(priv, base + mib->offset);
446 if (mib->size == 2) {
447 u64 hi;
448
449 hi = ar8xxx_read(priv, base + mib->offset + 4);
450 t |= hi << 32;
451 }
452
453 if (flush)
454 mib_stats[i] = 0;
455 else
456 mib_stats[i] += t;
457 cond_resched();
458 }
459 }
460
461 static void
462 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
463 struct switch_port_link *link)
464 {
465 u32 status;
466 u32 speed;
467
468 memset(link, '\0', sizeof(*link));
469
470 status = priv->chip->read_port_status(priv, port);
471
472 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
473 if (link->aneg) {
474 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
475 } else {
476 link->link = true;
477
478 if (priv->get_port_link) {
479 int err;
480
481 err = priv->get_port_link(port);
482 if (err >= 0)
483 link->link = !!err;
484 }
485 }
486
487 if (!link->link)
488 return;
489
490 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
491 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
492 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
493
494 if (link->aneg && link->duplex && priv->chip->read_port_eee_status)
495 link->eee = priv->chip->read_port_eee_status(priv, port);
496
497 speed = (status & AR8216_PORT_STATUS_SPEED) >>
498 AR8216_PORT_STATUS_SPEED_S;
499
500 switch (speed) {
501 case AR8216_PORT_SPEED_10M:
502 link->speed = SWITCH_PORT_SPEED_10;
503 break;
504 case AR8216_PORT_SPEED_100M:
505 link->speed = SWITCH_PORT_SPEED_100;
506 break;
507 case AR8216_PORT_SPEED_1000M:
508 link->speed = SWITCH_PORT_SPEED_1000;
509 break;
510 default:
511 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
512 break;
513 }
514 }
515
516 static struct sk_buff *
517 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
518 {
519 struct ar8xxx_priv *priv = dev->phy_ptr;
520 unsigned char *buf;
521
522 if (unlikely(!priv))
523 goto error;
524
525 if (!priv->vlan)
526 goto send;
527
528 if (unlikely(skb_headroom(skb) < 2)) {
529 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
530 goto error;
531 }
532
533 buf = skb_push(skb, 2);
534 buf[0] = 0x10;
535 buf[1] = 0x80;
536
537 send:
538 return skb;
539
540 error:
541 dev_kfree_skb_any(skb);
542 return NULL;
543 }
544
545 static void
546 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
547 {
548 struct ar8xxx_priv *priv;
549 unsigned char *buf;
550 int port, vlan;
551
552 priv = dev->phy_ptr;
553 if (!priv)
554 return;
555
556 /* don't strip the header if vlan mode is disabled */
557 if (!priv->vlan)
558 return;
559
560 /* strip header, get vlan id */
561 buf = skb->data;
562 skb_pull(skb, 2);
563
564 /* check for vlan header presence */
565 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
566 return;
567
568 port = buf[0] & 0x7;
569
570 /* no need to fix up packets coming from a tagged source */
571 if (priv->vlan_tagged & (1 << port))
572 return;
573
574 /* lookup port vid from local table, the switch passes an invalid vlan id */
575 vlan = priv->vlan_id[priv->pvid[port]];
576
577 buf[14 + 2] &= 0xf0;
578 buf[14 + 2] |= vlan >> 8;
579 buf[15 + 2] = vlan & 0xff;
580 }
581
582 int
583 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
584 {
585 int timeout = 20;
586 u32 t = 0;
587
588 while (1) {
589 t = ar8xxx_read(priv, reg);
590 if ((t & mask) == val)
591 return 0;
592
593 if (timeout-- <= 0)
594 break;
595
596 udelay(10);
597 cond_resched();
598 }
599
600 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
601 (unsigned int) reg, t, mask, val);
602 return -ETIMEDOUT;
603 }
604
605 static void
606 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
607 {
608 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
609 return;
610 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
611 val &= AR8216_VTUDATA_MEMBER;
612 val |= AR8216_VTUDATA_VALID;
613 ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
614 }
615 op |= AR8216_VTU_ACTIVE;
616 ar8xxx_write(priv, AR8216_REG_VTU, op);
617 }
618
619 static void
620 ar8216_vtu_flush(struct ar8xxx_priv *priv)
621 {
622 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
623 }
624
625 static void
626 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
627 {
628 u32 op;
629
630 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
631 ar8216_vtu_op(priv, op, port_mask);
632 }
633
634 static int
635 ar8216_atu_flush(struct ar8xxx_priv *priv)
636 {
637 int ret;
638
639 ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
640 if (!ret)
641 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_OP_FLUSH |
642 AR8216_ATU_ACTIVE);
643
644 return ret;
645 }
646
647 static int
648 ar8216_atu_flush_port(struct ar8xxx_priv *priv, int port)
649 {
650 u32 t;
651 int ret;
652
653 ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
654 if (!ret) {
655 t = (port << AR8216_ATU_PORT_NUM_S) | AR8216_ATU_OP_FLUSH_PORT;
656 t |= AR8216_ATU_ACTIVE;
657 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, t);
658 }
659
660 return ret;
661 }
662
663 static u32
664 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
665 {
666 return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
667 }
668
669 static void
670 __ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members,
671 bool ath_hdr_en)
672 {
673 u32 header;
674 u32 egress, ingress;
675 u32 pvid;
676
677 if (priv->vlan) {
678 pvid = priv->vlan_id[priv->pvid[port]];
679 if (priv->vlan_tagged & (1 << port))
680 egress = AR8216_OUT_ADD_VLAN;
681 else
682 egress = AR8216_OUT_STRIP_VLAN;
683 ingress = AR8216_IN_SECURE;
684 } else {
685 pvid = port;
686 egress = AR8216_OUT_KEEP;
687 ingress = AR8216_IN_PORT_ONLY;
688 }
689
690 header = ath_hdr_en ? AR8216_PORT_CTRL_HEADER : 0;
691
692 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
693 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
694 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
695 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
696 AR8216_PORT_CTRL_LEARN | header |
697 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
698 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
699
700 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
701 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
702 AR8216_PORT_VLAN_DEFAULT_ID,
703 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
704 (ingress << AR8216_PORT_VLAN_MODE_S) |
705 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
706 }
707
708 static void
709 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
710 {
711 return __ar8216_setup_port(priv, port, members,
712 chip_is_ar8216(priv) && priv->vlan &&
713 port == AR8216_PORT_CPU);
714 }
715
716 static int
717 ar8216_hw_init(struct ar8xxx_priv *priv)
718 {
719 if (priv->initialized)
720 return 0;
721
722 ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);
723 ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);
724
725 ar8xxx_phy_init(priv);
726
727 priv->initialized = true;
728 return 0;
729 }
730
731 static void
732 ar8216_init_globals(struct ar8xxx_priv *priv)
733 {
734 /* standard atheros magic */
735 ar8xxx_write(priv, 0x38, 0xc000050e);
736
737 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
738 AR8216_GCTRL_MTU, 1518 + 8 + 2);
739 }
740
741 static void
742 __ar8216_init_port(struct ar8xxx_priv *priv, int port,
743 bool cpu_ge, bool flow_en)
744 {
745 /* Enable port learning and tx */
746 ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
747 AR8216_PORT_CTRL_LEARN |
748 (4 << AR8216_PORT_CTRL_STATE_S));
749
750 ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
751
752 if (port == AR8216_PORT_CPU) {
753 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
754 AR8216_PORT_STATUS_LINK_UP |
755 (cpu_ge ? AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
756 AR8216_PORT_STATUS_TXMAC |
757 AR8216_PORT_STATUS_RXMAC |
758 (flow_en ? AR8216_PORT_STATUS_RXFLOW : 0) |
759 (flow_en ? AR8216_PORT_STATUS_TXFLOW : 0) |
760 AR8216_PORT_STATUS_DUPLEX);
761 } else {
762 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
763 AR8216_PORT_STATUS_LINK_AUTO);
764 }
765 }
766
767 static void
768 ar8216_init_port(struct ar8xxx_priv *priv, int port)
769 {
770 __ar8216_init_port(priv, port, ar8xxx_has_gige(priv),
771 chip_is_ar8316(priv));
772 }
773
774 static void
775 ar8216_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
776 {
777 int timeout = 20;
778
779 while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout) {
780 udelay(10);
781 cond_resched();
782 }
783
784 if (!timeout)
785 pr_err("ar8216: timeout waiting for atu to become ready\n");
786 }
787
788 static void ar8216_get_arl_entry(struct ar8xxx_priv *priv,
789 struct arl_entry *a, u32 *status, enum arl_op op)
790 {
791 struct mii_bus *bus = priv->mii_bus;
792 u16 r2, page;
793 u16 r1_func0, r1_func1, r1_func2;
794 u32 t, val0, val1, val2;
795
796 split_addr(AR8216_REG_ATU_FUNC0, &r1_func0, &r2, &page);
797 r2 |= 0x10;
798
799 r1_func1 = (AR8216_REG_ATU_FUNC1 >> 1) & 0x1e;
800 r1_func2 = (AR8216_REG_ATU_FUNC2 >> 1) & 0x1e;
801
802 switch (op) {
803 case AR8XXX_ARL_INITIALIZE:
804 /* all ATU registers are on the same page
805 * therefore set page only once
806 */
807 bus->write(bus, 0x18, 0, page);
808 wait_for_page_switch();
809
810 ar8216_wait_atu_ready(priv, r2, r1_func0);
811
812 ar8xxx_mii_write32(priv, r2, r1_func0, AR8216_ATU_OP_GET_NEXT);
813 ar8xxx_mii_write32(priv, r2, r1_func1, 0);
814 ar8xxx_mii_write32(priv, r2, r1_func2, 0);
815 break;
816 case AR8XXX_ARL_GET_NEXT:
817 t = ar8xxx_mii_read32(priv, r2, r1_func0);
818 t |= AR8216_ATU_ACTIVE;
819 ar8xxx_mii_write32(priv, r2, r1_func0, t);
820 ar8216_wait_atu_ready(priv, r2, r1_func0);
821
822 val0 = ar8xxx_mii_read32(priv, r2, r1_func0);
823 val1 = ar8xxx_mii_read32(priv, r2, r1_func1);
824 val2 = ar8xxx_mii_read32(priv, r2, r1_func2);
825
826 *status = (val2 & AR8216_ATU_STATUS) >> AR8216_ATU_STATUS_S;
827 if (!*status)
828 break;
829
830 a->portmap = (val2 & AR8216_ATU_PORTS) >> AR8216_ATU_PORTS_S;
831 a->mac[0] = (val0 & AR8216_ATU_ADDR5) >> AR8216_ATU_ADDR5_S;
832 a->mac[1] = (val0 & AR8216_ATU_ADDR4) >> AR8216_ATU_ADDR4_S;
833 a->mac[2] = (val1 & AR8216_ATU_ADDR3) >> AR8216_ATU_ADDR3_S;
834 a->mac[3] = (val1 & AR8216_ATU_ADDR2) >> AR8216_ATU_ADDR2_S;
835 a->mac[4] = (val1 & AR8216_ATU_ADDR1) >> AR8216_ATU_ADDR1_S;
836 a->mac[5] = (val1 & AR8216_ATU_ADDR0) >> AR8216_ATU_ADDR0_S;
837 break;
838 }
839 }
840
841 static int
842 ar8216_phy_read(struct ar8xxx_priv *priv, int addr, int regnum)
843 {
844 u32 t, val = 0xffff;
845 int err;
846
847 if (addr >= AR8216_NUM_PORTS)
848 return 0xffff;
849 t = (regnum << AR8216_MDIO_CTRL_REG_ADDR_S) |
850 (addr << AR8216_MDIO_CTRL_PHY_ADDR_S) |
851 AR8216_MDIO_CTRL_MASTER_EN |
852 AR8216_MDIO_CTRL_BUSY |
853 AR8216_MDIO_CTRL_CMD_READ;
854
855 ar8xxx_write(priv, AR8216_REG_MDIO_CTRL, t);
856 err = ar8xxx_reg_wait(priv, AR8216_REG_MDIO_CTRL,
857 AR8216_MDIO_CTRL_BUSY, 0, 5);
858 if (!err)
859 val = ar8xxx_read(priv, AR8216_REG_MDIO_CTRL);
860
861 return val & AR8216_MDIO_CTRL_DATA_M;
862 }
863
864 static int
865 ar8216_phy_write(struct ar8xxx_priv *priv, int addr, int regnum, u16 val)
866 {
867 u32 t;
868 int ret;
869
870 if (addr >= AR8216_NUM_PORTS)
871 return -EINVAL;
872
873 t = (addr << AR8216_MDIO_CTRL_PHY_ADDR_S) |
874 (regnum << AR8216_MDIO_CTRL_REG_ADDR_S) |
875 AR8216_MDIO_CTRL_MASTER_EN |
876 AR8216_MDIO_CTRL_BUSY |
877 AR8216_MDIO_CTRL_CMD_WRITE |
878 val;
879
880 ar8xxx_write(priv, AR8216_REG_MDIO_CTRL, t);
881 ret = ar8xxx_reg_wait(priv, AR8216_REG_MDIO_CTRL,
882 AR8216_MDIO_CTRL_BUSY, 0, 5);
883
884 return ret;
885 }
886
887 static int
888 ar8229_hw_init(struct ar8xxx_priv *priv)
889 {
890 int phy_if_mode;
891
892 if (priv->initialized)
893 return 0;
894
895 ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);
896 ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);
897
898 phy_if_mode = of_get_phy_mode(priv->pdev->of_node);
899
900 if (phy_if_mode == PHY_INTERFACE_MODE_GMII) {
901 ar8xxx_write(priv, AR8229_REG_OPER_MODE0,
902 AR8229_OPER_MODE0_MAC_GMII_EN);
903 } else if (phy_if_mode == PHY_INTERFACE_MODE_MII) {
904 ar8xxx_write(priv, AR8229_REG_OPER_MODE0,
905 AR8229_OPER_MODE0_PHY_MII_EN);
906 } else {
907 pr_err("ar8229: unsupported mii mode\n");
908 return -EINVAL;
909 }
910
911 if (priv->port4_phy) {
912 ar8xxx_write(priv, AR8229_REG_OPER_MODE1,
913 AR8229_REG_OPER_MODE1_PHY4_MII_EN);
914 /* disable port5 to prevent mii conflict */
915 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(5), 0);
916 }
917
918 ar8xxx_phy_init(priv);
919
920 priv->initialized = true;
921 return 0;
922 }
923
924 static void
925 ar8229_init_globals(struct ar8xxx_priv *priv)
926 {
927
928 /* Enable CPU port, and disable mirror port */
929 ar8xxx_write(priv, AR8216_REG_GLOBAL_CPUPORT,
930 AR8216_GLOBAL_CPUPORT_EN |
931 (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
932
933 /* Setup TAG priority mapping */
934 ar8xxx_write(priv, AR8216_REG_TAG_PRIORITY, 0xfa50);
935
936 /* Enable aging, MAC replacing */
937 ar8xxx_write(priv, AR8216_REG_ATU_CTRL,
938 0x2b /* 5 min age time */ |
939 AR8216_ATU_CTRL_AGE_EN |
940 AR8216_ATU_CTRL_LEARN_CHANGE);
941
942 /* Enable ARP frame acknowledge */
943 ar8xxx_reg_set(priv, AR8229_REG_QM_CTRL,
944 AR8229_QM_CTRL_ARP_EN);
945
946 /*
947 * Enable Broadcast/unknown multicast and unicast frames
948 * transmitted to the CPU port.
949 */
950 ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
951 AR8229_FLOOD_MASK_BC_DP(0) |
952 AR8229_FLOOD_MASK_MC_DP(0) |
953 AR8229_FLOOD_MASK_UC_DP(0));
954
955 /* setup MTU */
956 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
957 AR8236_GCTRL_MTU, AR8236_GCTRL_MTU);
958
959 /* Enable MIB counters */
960 ar8xxx_reg_set(priv, AR8216_REG_MIB_FUNC,
961 AR8236_MIB_EN);
962
963 /* setup Service TAG */
964 ar8xxx_rmw(priv, AR8216_REG_SERVICE_TAG, AR8216_SERVICE_TAG_M, 0);
965 }
966
967 static void
968 ar8229_init_port(struct ar8xxx_priv *priv, int port)
969 {
970 __ar8216_init_port(priv, port, true, true);
971 }
972
973
974 static int
975 ar7240sw_hw_init(struct ar8xxx_priv *priv)
976 {
977 if (priv->initialized)
978 return 0;
979
980 ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);
981 ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);
982
983 priv->port4_phy = 1;
984 /* disable port5 to prevent mii conflict */
985 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(5), 0);
986
987 ar8xxx_phy_init(priv);
988
989 priv->initialized = true;
990 return 0;
991 }
992
993 static void
994 ar7240sw_init_globals(struct ar8xxx_priv *priv)
995 {
996
997 /* Enable CPU port, and disable mirror port */
998 ar8xxx_write(priv, AR8216_REG_GLOBAL_CPUPORT,
999 AR8216_GLOBAL_CPUPORT_EN |
1000 (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1001
1002 /* Setup TAG priority mapping */
1003 ar8xxx_write(priv, AR8216_REG_TAG_PRIORITY, 0xfa50);
1004
1005 /* Enable ARP frame acknowledge, aging, MAC replacing */
1006 ar8xxx_write(priv, AR8216_REG_ATU_CTRL,
1007 AR8216_ATU_CTRL_RESERVED |
1008 0x2b /* 5 min age time */ |
1009 AR8216_ATU_CTRL_AGE_EN |
1010 AR8216_ATU_CTRL_ARP_EN |
1011 AR8216_ATU_CTRL_LEARN_CHANGE);
1012
1013 /* Enable Broadcast frames transmitted to the CPU */
1014 ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
1015 AR8216_FM_CPU_BROADCAST_EN);
1016
1017 /* setup MTU */
1018 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1019 AR8216_GCTRL_MTU,
1020 AR8216_GCTRL_MTU);
1021
1022 /* setup Service TAG */
1023 ar8xxx_rmw(priv, AR8216_REG_SERVICE_TAG, AR8216_SERVICE_TAG_M, 0);
1024 }
1025
1026 static void
1027 ar7240sw_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1028 {
1029 return __ar8216_setup_port(priv, port, members, false);
1030 }
1031
1032 static void
1033 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1034 {
1035 u32 egress, ingress;
1036 u32 pvid;
1037
1038 if (priv->vlan) {
1039 pvid = priv->vlan_id[priv->pvid[port]];
1040 if (priv->vlan_tagged & (1 << port))
1041 egress = AR8216_OUT_ADD_VLAN;
1042 else
1043 egress = AR8216_OUT_STRIP_VLAN;
1044 ingress = AR8216_IN_SECURE;
1045 } else {
1046 pvid = port;
1047 egress = AR8216_OUT_KEEP;
1048 ingress = AR8216_IN_PORT_ONLY;
1049 }
1050
1051 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
1052 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
1053 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
1054 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
1055 AR8216_PORT_CTRL_LEARN |
1056 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
1057 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
1058
1059 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
1060 AR8236_PORT_VLAN_DEFAULT_ID,
1061 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
1062
1063 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
1064 AR8236_PORT_VLAN2_VLAN_MODE |
1065 AR8236_PORT_VLAN2_MEMBER,
1066 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
1067 (members << AR8236_PORT_VLAN2_MEMBER_S));
1068 }
1069
1070 static void
1071 ar8236_init_globals(struct ar8xxx_priv *priv)
1072 {
1073 /* enable jumbo frames */
1074 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1075 AR8316_GCTRL_MTU, 9018 + 8 + 2);
1076
1077 /* enable cpu port to receive arp frames */
1078 ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,
1079 AR8236_ATU_CTRL_RES);
1080
1081 /*
1082 * Enable Broadcast/unknown multicast and unicast frames
1083 * transmitted to the CPU port.
1084 */
1085 ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
1086 AR8229_FLOOD_MASK_BC_DP(0) |
1087 AR8229_FLOOD_MASK_MC_DP(0) |
1088 AR8229_FLOOD_MASK_UC_DP(0));
1089
1090 /* Enable MIB counters */
1091 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1092 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1093 AR8236_MIB_EN);
1094 }
1095
1096 static int
1097 ar8316_hw_init(struct ar8xxx_priv *priv)
1098 {
1099 u32 val, newval;
1100
1101 val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
1102
1103 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
1104 if (priv->port4_phy) {
1105 /* value taken from Ubiquiti RouterStation Pro */
1106 newval = 0x81461bea;
1107 pr_info("ar8316: Using port 4 as PHY\n");
1108 } else {
1109 newval = 0x01261be2;
1110 pr_info("ar8316: Using port 4 as switch port\n");
1111 }
1112 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
1113 /* value taken from AVM Fritz!Box 7390 sources */
1114 newval = 0x010e5b71;
1115 } else {
1116 /* no known value for phy interface */
1117 pr_err("ar8316: unsupported mii mode: %d.\n",
1118 priv->phy->interface);
1119 return -EINVAL;
1120 }
1121
1122 if (val == newval)
1123 goto out;
1124
1125 ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
1126
1127 if (priv->port4_phy &&
1128 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
1129 /* work around for phy4 rgmii mode */
1130 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
1131 /* rx delay */
1132 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
1133 /* tx delay */
1134 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
1135 msleep(1000);
1136 }
1137
1138 ar8xxx_phy_init(priv);
1139
1140 out:
1141 priv->initialized = true;
1142 return 0;
1143 }
1144
1145 static void
1146 ar8316_init_globals(struct ar8xxx_priv *priv)
1147 {
1148 /* standard atheros magic */
1149 ar8xxx_write(priv, 0x38, 0xc000050e);
1150
1151 /* enable cpu port to receive multicast and broadcast frames */
1152 ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
1153
1154 /* enable jumbo frames */
1155 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1156 AR8316_GCTRL_MTU, 9018 + 8 + 2);
1157
1158 /* Enable MIB counters */
1159 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1160 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1161 AR8236_MIB_EN);
1162 }
1163
1164 int
1165 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1166 struct switch_val *val)
1167 {
1168 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1169 priv->vlan = !!val->value.i;
1170 return 0;
1171 }
1172
1173 int
1174 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1175 struct switch_val *val)
1176 {
1177 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1178 val->value.i = priv->vlan;
1179 return 0;
1180 }
1181
1182
1183 int
1184 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1185 {
1186 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1187
1188 /* make sure no invalid PVIDs get set */
1189
1190 if (vlan < 0 || vlan >= dev->vlans ||
1191 port < 0 || port >= AR8X16_MAX_PORTS)
1192 return -EINVAL;
1193
1194 priv->pvid[port] = vlan;
1195 return 0;
1196 }
1197
1198 int
1199 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1200 {
1201 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1202
1203 if (port < 0 || port >= AR8X16_MAX_PORTS)
1204 return -EINVAL;
1205
1206 *vlan = priv->pvid[port];
1207 return 0;
1208 }
1209
1210 static int
1211 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1212 struct switch_val *val)
1213 {
1214 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1215
1216 if (val->port_vlan >= dev->vlans)
1217 return -EINVAL;
1218
1219 priv->vlan_id[val->port_vlan] = val->value.i;
1220 return 0;
1221 }
1222
1223 static int
1224 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1225 struct switch_val *val)
1226 {
1227 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1228 val->value.i = priv->vlan_id[val->port_vlan];
1229 return 0;
1230 }
1231
1232 int
1233 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1234 struct switch_port_link *link)
1235 {
1236 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1237
1238 ar8216_read_port_link(priv, port, link);
1239 return 0;
1240 }
1241
1242 static int
1243 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1244 {
1245 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1246 u8 ports;
1247 int i;
1248
1249 if (val->port_vlan >= dev->vlans)
1250 return -EINVAL;
1251
1252 ports = priv->vlan_table[val->port_vlan];
1253 val->len = 0;
1254 for (i = 0; i < dev->ports; i++) {
1255 struct switch_port *p;
1256
1257 if (!(ports & (1 << i)))
1258 continue;
1259
1260 p = &val->value.ports[val->len++];
1261 p->id = i;
1262 if (priv->vlan_tagged & (1 << i))
1263 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1264 else
1265 p->flags = 0;
1266 }
1267 return 0;
1268 }
1269
1270 static int
1271 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1272 {
1273 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1274 u8 *vt = &priv->vlan_table[val->port_vlan];
1275 int i, j;
1276
1277 *vt = 0;
1278 for (i = 0; i < val->len; i++) {
1279 struct switch_port *p = &val->value.ports[i];
1280
1281 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1282 priv->vlan_tagged |= (1 << p->id);
1283 } else {
1284 priv->vlan_tagged &= ~(1 << p->id);
1285 priv->pvid[p->id] = val->port_vlan;
1286
1287 /* make sure that an untagged port does not
1288 * appear in other vlans */
1289 for (j = 0; j < dev->vlans; j++) {
1290 if (j == val->port_vlan)
1291 continue;
1292 priv->vlan_table[j] &= ~(1 << p->id);
1293 }
1294 }
1295
1296 *vt |= 1 << p->id;
1297 }
1298 return 0;
1299 }
1300
1301 static void
1302 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
1303 {
1304 int port;
1305
1306 /* reset all mirror registers */
1307 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1308 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1309 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1310 for (port = 0; port < AR8216_NUM_PORTS; port++) {
1311 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1312 AR8216_PORT_CTRL_MIRROR_RX);
1313
1314 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1315 AR8216_PORT_CTRL_MIRROR_TX);
1316 }
1317
1318 /* now enable mirroring if necessary */
1319 if (priv->source_port >= AR8216_NUM_PORTS ||
1320 priv->monitor_port >= AR8216_NUM_PORTS ||
1321 priv->source_port == priv->monitor_port) {
1322 return;
1323 }
1324
1325 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1326 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1327 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1328
1329 if (priv->mirror_rx)
1330 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1331 AR8216_PORT_CTRL_MIRROR_RX);
1332
1333 if (priv->mirror_tx)
1334 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1335 AR8216_PORT_CTRL_MIRROR_TX);
1336 }
1337
1338 static inline u32
1339 ar8xxx_age_time_val(int age_time)
1340 {
1341 return (age_time + AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS / 2) /
1342 AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS;
1343 }
1344
1345 static inline void
1346 ar8xxx_set_age_time(struct ar8xxx_priv *priv, int reg)
1347 {
1348 u32 age_time = ar8xxx_age_time_val(priv->arl_age_time);
1349 ar8xxx_rmw(priv, reg, AR8216_ATU_CTRL_AGE_TIME, age_time << AR8216_ATU_CTRL_AGE_TIME_S);
1350 }
1351
1352 int
1353 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1354 {
1355 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1356 const struct ar8xxx_chip *chip = priv->chip;
1357 u8 portmask[AR8X16_MAX_PORTS];
1358 int i, j;
1359
1360 mutex_lock(&priv->reg_mutex);
1361 /* flush all vlan translation unit entries */
1362 priv->chip->vtu_flush(priv);
1363
1364 memset(portmask, 0, sizeof(portmask));
1365 if (!priv->init) {
1366 /* calculate the port destination masks and load vlans
1367 * into the vlan translation unit */
1368 for (j = 0; j < dev->vlans; j++) {
1369 u8 vp = priv->vlan_table[j];
1370
1371 if (!vp)
1372 continue;
1373
1374 for (i = 0; i < dev->ports; i++) {
1375 u8 mask = (1 << i);
1376 if (vp & mask)
1377 portmask[i] |= vp & ~mask;
1378 }
1379
1380 chip->vtu_load_vlan(priv, priv->vlan_id[j],
1381 priv->vlan_table[j]);
1382 }
1383 } else {
1384 /* vlan disabled:
1385 * isolate all ports, but connect them to the cpu port */
1386 for (i = 0; i < dev->ports; i++) {
1387 if (i == AR8216_PORT_CPU)
1388 continue;
1389
1390 portmask[i] = 1 << AR8216_PORT_CPU;
1391 portmask[AR8216_PORT_CPU] |= (1 << i);
1392 }
1393 }
1394
1395 /* update the port destination mask registers and tag settings */
1396 for (i = 0; i < dev->ports; i++) {
1397 chip->setup_port(priv, i, portmask[i]);
1398 }
1399
1400 chip->set_mirror_regs(priv);
1401
1402 /* set age time */
1403 if (chip->reg_arl_ctrl)
1404 ar8xxx_set_age_time(priv, chip->reg_arl_ctrl);
1405
1406 mutex_unlock(&priv->reg_mutex);
1407 return 0;
1408 }
1409
1410 int
1411 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1412 {
1413 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1414 const struct ar8xxx_chip *chip = priv->chip;
1415 int i;
1416
1417 mutex_lock(&priv->reg_mutex);
1418 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1419 offsetof(struct ar8xxx_priv, vlan));
1420
1421 for (i = 0; i < dev->vlans; i++)
1422 priv->vlan_id[i] = i;
1423
1424 /* Configure all ports */
1425 for (i = 0; i < dev->ports; i++)
1426 chip->init_port(priv, i);
1427
1428 priv->mirror_rx = false;
1429 priv->mirror_tx = false;
1430 priv->source_port = 0;
1431 priv->monitor_port = 0;
1432 priv->arl_age_time = AR8XXX_DEFAULT_ARL_AGE_TIME;
1433
1434 chip->init_globals(priv);
1435 chip->atu_flush(priv);
1436
1437 mutex_unlock(&priv->reg_mutex);
1438
1439 return chip->sw_hw_apply(dev);
1440 }
1441
1442 int
1443 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1444 const struct switch_attr *attr,
1445 struct switch_val *val)
1446 {
1447 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1448 unsigned int len;
1449 int ret;
1450
1451 if (!ar8xxx_has_mib_counters(priv))
1452 return -EOPNOTSUPP;
1453
1454 mutex_lock(&priv->mib_lock);
1455
1456 len = priv->dev.ports * priv->chip->num_mibs *
1457 sizeof(*priv->mib_stats);
1458 memset(priv->mib_stats, '\0', len);
1459 ret = ar8xxx_mib_flush(priv);
1460 if (ret)
1461 goto unlock;
1462
1463 ret = 0;
1464
1465 unlock:
1466 mutex_unlock(&priv->mib_lock);
1467 return ret;
1468 }
1469
1470 int
1471 ar8xxx_sw_set_mib_poll_interval(struct switch_dev *dev,
1472 const struct switch_attr *attr,
1473 struct switch_val *val)
1474 {
1475 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1476
1477 if (!ar8xxx_has_mib_counters(priv))
1478 return -EOPNOTSUPP;
1479
1480 ar8xxx_mib_stop(priv);
1481 priv->mib_poll_interval = val->value.i;
1482 ar8xxx_mib_start(priv);
1483
1484 return 0;
1485 }
1486
1487 int
1488 ar8xxx_sw_get_mib_poll_interval(struct switch_dev *dev,
1489 const struct switch_attr *attr,
1490 struct switch_val *val)
1491 {
1492 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1493
1494 if (!ar8xxx_has_mib_counters(priv))
1495 return -EOPNOTSUPP;
1496 val->value.i = priv->mib_poll_interval;
1497 return 0;
1498 }
1499
1500 int
1501 ar8xxx_sw_set_mib_type(struct switch_dev *dev,
1502 const struct switch_attr *attr,
1503 struct switch_val *val)
1504 {
1505 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1506
1507 if (!ar8xxx_has_mib_counters(priv))
1508 return -EOPNOTSUPP;
1509 priv->mib_type = val->value.i;
1510 return 0;
1511 }
1512
1513 int
1514 ar8xxx_sw_get_mib_type(struct switch_dev *dev,
1515 const struct switch_attr *attr,
1516 struct switch_val *val)
1517 {
1518 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1519
1520 if (!ar8xxx_has_mib_counters(priv))
1521 return -EOPNOTSUPP;
1522 val->value.i = priv->mib_type;
1523 return 0;
1524 }
1525
1526 int
1527 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1528 const struct switch_attr *attr,
1529 struct switch_val *val)
1530 {
1531 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1532
1533 mutex_lock(&priv->reg_mutex);
1534 priv->mirror_rx = !!val->value.i;
1535 priv->chip->set_mirror_regs(priv);
1536 mutex_unlock(&priv->reg_mutex);
1537
1538 return 0;
1539 }
1540
1541 int
1542 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1543 const struct switch_attr *attr,
1544 struct switch_val *val)
1545 {
1546 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1547 val->value.i = priv->mirror_rx;
1548 return 0;
1549 }
1550
1551 int
1552 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1553 const struct switch_attr *attr,
1554 struct switch_val *val)
1555 {
1556 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1557
1558 mutex_lock(&priv->reg_mutex);
1559 priv->mirror_tx = !!val->value.i;
1560 priv->chip->set_mirror_regs(priv);
1561 mutex_unlock(&priv->reg_mutex);
1562
1563 return 0;
1564 }
1565
1566 int
1567 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1568 const struct switch_attr *attr,
1569 struct switch_val *val)
1570 {
1571 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1572 val->value.i = priv->mirror_tx;
1573 return 0;
1574 }
1575
1576 int
1577 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1578 const struct switch_attr *attr,
1579 struct switch_val *val)
1580 {
1581 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1582
1583 mutex_lock(&priv->reg_mutex);
1584 priv->monitor_port = val->value.i;
1585 priv->chip->set_mirror_regs(priv);
1586 mutex_unlock(&priv->reg_mutex);
1587
1588 return 0;
1589 }
1590
1591 int
1592 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1593 const struct switch_attr *attr,
1594 struct switch_val *val)
1595 {
1596 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1597 val->value.i = priv->monitor_port;
1598 return 0;
1599 }
1600
1601 int
1602 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1603 const struct switch_attr *attr,
1604 struct switch_val *val)
1605 {
1606 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1607
1608 mutex_lock(&priv->reg_mutex);
1609 priv->source_port = val->value.i;
1610 priv->chip->set_mirror_regs(priv);
1611 mutex_unlock(&priv->reg_mutex);
1612
1613 return 0;
1614 }
1615
1616 int
1617 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1618 const struct switch_attr *attr,
1619 struct switch_val *val)
1620 {
1621 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1622 val->value.i = priv->source_port;
1623 return 0;
1624 }
1625
1626 int
1627 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1628 const struct switch_attr *attr,
1629 struct switch_val *val)
1630 {
1631 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1632 int port;
1633 int ret;
1634
1635 if (!ar8xxx_has_mib_counters(priv))
1636 return -EOPNOTSUPP;
1637
1638 port = val->port_vlan;
1639 if (port >= dev->ports)
1640 return -EINVAL;
1641
1642 mutex_lock(&priv->mib_lock);
1643 ret = ar8xxx_mib_capture(priv);
1644 if (ret)
1645 goto unlock;
1646
1647 ar8xxx_mib_fetch_port_stat(priv, port, true);
1648
1649 ret = 0;
1650
1651 unlock:
1652 mutex_unlock(&priv->mib_lock);
1653 return ret;
1654 }
1655
1656 static void
1657 ar8xxx_byte_to_str(char *buf, int len, u64 byte)
1658 {
1659 unsigned long b;
1660 const char *unit;
1661
1662 if (byte >= 0x40000000) { /* 1 GiB */
1663 b = byte * 10 / 0x40000000;
1664 unit = "GiB";
1665 } else if (byte >= 0x100000) { /* 1 MiB */
1666 b = byte * 10 / 0x100000;
1667 unit = "MiB";
1668 } else if (byte >= 0x400) { /* 1 KiB */
1669 b = byte * 10 / 0x400;
1670 unit = "KiB";
1671 } else {
1672 b = byte;
1673 unit = "Byte";
1674 }
1675 if (strcmp(unit, "Byte"))
1676 snprintf(buf, len, "%lu.%lu %s", b / 10, b % 10, unit);
1677 else
1678 snprintf(buf, len, "%lu %s", b, unit);
1679 }
1680
1681 int
1682 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1683 const struct switch_attr *attr,
1684 struct switch_val *val)
1685 {
1686 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1687 const struct ar8xxx_chip *chip = priv->chip;
1688 u64 *mib_stats, mib_data;
1689 unsigned int port;
1690 int ret;
1691 char *buf = priv->buf;
1692 char buf1[64];
1693 const char *mib_name;
1694 int i, len = 0;
1695 bool mib_stats_empty = true;
1696
1697 if (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval)
1698 return -EOPNOTSUPP;
1699
1700 port = val->port_vlan;
1701 if (port >= dev->ports)
1702 return -EINVAL;
1703
1704 mutex_lock(&priv->mib_lock);
1705 ret = ar8xxx_mib_capture(priv);
1706 if (ret)
1707 goto unlock;
1708
1709 ar8xxx_mib_fetch_port_stat(priv, port, false);
1710
1711 len += snprintf(buf + len, sizeof(priv->buf) - len,
1712 "MIB counters\n");
1713
1714 mib_stats = &priv->mib_stats[port * chip->num_mibs];
1715 for (i = 0; i < chip->num_mibs; i++) {
1716 if (chip->mib_decs[i].type > priv->mib_type)
1717 continue;
1718 mib_name = chip->mib_decs[i].name;
1719 mib_data = mib_stats[i];
1720 len += snprintf(buf + len, sizeof(priv->buf) - len,
1721 "%-12s: %llu\n", mib_name, mib_data);
1722 if ((!strcmp(mib_name, "TxByte") ||
1723 !strcmp(mib_name, "RxGoodByte")) &&
1724 mib_data >= 1024) {
1725 ar8xxx_byte_to_str(buf1, sizeof(buf1), mib_data);
1726 --len; /* discard newline at the end of buf */
1727 len += snprintf(buf + len, sizeof(priv->buf) - len,
1728 " (%s)\n", buf1);
1729 }
1730 if (mib_stats_empty && mib_data)
1731 mib_stats_empty = false;
1732 }
1733
1734 if (mib_stats_empty)
1735 len = snprintf(buf, sizeof(priv->buf), "No MIB data");
1736
1737 val->value.s = buf;
1738 val->len = len;
1739
1740 ret = 0;
1741
1742 unlock:
1743 mutex_unlock(&priv->mib_lock);
1744 return ret;
1745 }
1746
1747 int
1748 ar8xxx_sw_set_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1749 struct switch_val *val)
1750 {
1751 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1752 int age_time = val->value.i;
1753 u32 age_time_val;
1754
1755 if (age_time < 0)
1756 return -EINVAL;
1757
1758 age_time_val = ar8xxx_age_time_val(age_time);
1759 if (age_time_val == 0 || age_time_val > 0xffff)
1760 return -EINVAL;
1761
1762 priv->arl_age_time = age_time;
1763 return 0;
1764 }
1765
1766 int
1767 ar8xxx_sw_get_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1768 struct switch_val *val)
1769 {
1770 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1771 val->value.i = priv->arl_age_time;
1772 return 0;
1773 }
1774
1775 int
1776 ar8xxx_sw_get_arl_table(struct switch_dev *dev,
1777 const struct switch_attr *attr,
1778 struct switch_val *val)
1779 {
1780 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1781 struct mii_bus *bus = priv->mii_bus;
1782 const struct ar8xxx_chip *chip = priv->chip;
1783 char *buf = priv->arl_buf;
1784 int i, j, k, len = 0;
1785 struct arl_entry *a, *a1;
1786 u32 status;
1787
1788 if (!chip->get_arl_entry)
1789 return -EOPNOTSUPP;
1790
1791 mutex_lock(&priv->reg_mutex);
1792 mutex_lock(&bus->mdio_lock);
1793
1794 chip->get_arl_entry(priv, NULL, NULL, AR8XXX_ARL_INITIALIZE);
1795
1796 for(i = 0; i < AR8XXX_NUM_ARL_RECORDS; ++i) {
1797 a = &priv->arl_table[i];
1798 duplicate:
1799 chip->get_arl_entry(priv, a, &status, AR8XXX_ARL_GET_NEXT);
1800
1801 if (!status)
1802 break;
1803
1804 /* avoid duplicates
1805 * ARL table can include multiple valid entries
1806 * per MAC, just with differing status codes
1807 */
1808 for (j = 0; j < i; ++j) {
1809 a1 = &priv->arl_table[j];
1810 if (!memcmp(a->mac, a1->mac, sizeof(a->mac))) {
1811 /* ignore ports already seen in former entry */
1812 a->portmap &= ~a1->portmap;
1813 if (!a->portmap)
1814 goto duplicate;
1815 }
1816 }
1817 }
1818
1819 mutex_unlock(&bus->mdio_lock);
1820
1821 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1822 "address resolution table\n");
1823
1824 if (i == AR8XXX_NUM_ARL_RECORDS)
1825 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1826 "Too many entries found, displaying the first %d only!\n",
1827 AR8XXX_NUM_ARL_RECORDS);
1828
1829 for (j = 0; j < priv->dev.ports; ++j) {
1830 for (k = 0; k < i; ++k) {
1831 a = &priv->arl_table[k];
1832 if (!(a->portmap & BIT(j)))
1833 continue;
1834 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1835 "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1836 j,
1837 a->mac[5], a->mac[4], a->mac[3],
1838 a->mac[2], a->mac[1], a->mac[0]);
1839 }
1840 }
1841
1842 val->value.s = buf;
1843 val->len = len;
1844
1845 mutex_unlock(&priv->reg_mutex);
1846
1847 return 0;
1848 }
1849
1850 int
1851 ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev,
1852 const struct switch_attr *attr,
1853 struct switch_val *val)
1854 {
1855 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1856 int ret;
1857
1858 mutex_lock(&priv->reg_mutex);
1859 ret = priv->chip->atu_flush(priv);
1860 mutex_unlock(&priv->reg_mutex);
1861
1862 return ret;
1863 }
1864
1865 int
1866 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,
1867 const struct switch_attr *attr,
1868 struct switch_val *val)
1869 {
1870 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1871 int port, ret;
1872
1873 port = val->port_vlan;
1874 if (port >= dev->ports)
1875 return -EINVAL;
1876
1877 mutex_lock(&priv->reg_mutex);
1878 ret = priv->chip->atu_flush_port(priv, port);
1879 mutex_unlock(&priv->reg_mutex);
1880
1881 return ret;
1882 }
1883
1884 int
1885 ar8xxx_sw_get_port_stats(struct switch_dev *dev, int port,
1886 struct switch_port_stats *stats)
1887 {
1888 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1889 u64 *mib_stats;
1890
1891 if (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval)
1892 return -EOPNOTSUPP;
1893
1894 if (!(priv->chip->mib_rxb_id || priv->chip->mib_txb_id))
1895 return -EOPNOTSUPP;
1896
1897 if (port >= dev->ports)
1898 return -EINVAL;
1899
1900 mutex_lock(&priv->mib_lock);
1901
1902 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
1903
1904 stats->tx_bytes = mib_stats[priv->chip->mib_txb_id];
1905 stats->rx_bytes = mib_stats[priv->chip->mib_rxb_id];
1906
1907 mutex_unlock(&priv->mib_lock);
1908 return 0;
1909 }
1910
1911 static int
1912 ar8xxx_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr)
1913 {
1914 struct ar8xxx_priv *priv = bus->priv;
1915 return priv->chip->phy_read(priv, phy_addr, reg_addr);
1916 }
1917
1918 static int
1919 ar8xxx_phy_write(struct mii_bus *bus, int phy_addr, int reg_addr,
1920 u16 reg_val)
1921 {
1922 struct ar8xxx_priv *priv = bus->priv;
1923 return priv->chip->phy_write(priv, phy_addr, reg_addr, reg_val);
1924 }
1925
1926 static const struct switch_attr ar8xxx_sw_attr_globals[] = {
1927 {
1928 .type = SWITCH_TYPE_INT,
1929 .name = "enable_vlan",
1930 .description = "Enable VLAN mode",
1931 .set = ar8xxx_sw_set_vlan,
1932 .get = ar8xxx_sw_get_vlan,
1933 .max = 1
1934 },
1935 {
1936 .type = SWITCH_TYPE_NOVAL,
1937 .name = "reset_mibs",
1938 .description = "Reset all MIB counters",
1939 .set = ar8xxx_sw_set_reset_mibs,
1940 },
1941 {
1942 .type = SWITCH_TYPE_INT,
1943 .name = "ar8xxx_mib_poll_interval",
1944 .description = "MIB polling interval in msecs (0 to disable)",
1945 .set = ar8xxx_sw_set_mib_poll_interval,
1946 .get = ar8xxx_sw_get_mib_poll_interval
1947 },
1948 {
1949 .type = SWITCH_TYPE_INT,
1950 .name = "ar8xxx_mib_type",
1951 .description = "MIB type (0=basic 1=extended)",
1952 .set = ar8xxx_sw_set_mib_type,
1953 .get = ar8xxx_sw_get_mib_type
1954 },
1955 {
1956 .type = SWITCH_TYPE_INT,
1957 .name = "enable_mirror_rx",
1958 .description = "Enable mirroring of RX packets",
1959 .set = ar8xxx_sw_set_mirror_rx_enable,
1960 .get = ar8xxx_sw_get_mirror_rx_enable,
1961 .max = 1
1962 },
1963 {
1964 .type = SWITCH_TYPE_INT,
1965 .name = "enable_mirror_tx",
1966 .description = "Enable mirroring of TX packets",
1967 .set = ar8xxx_sw_set_mirror_tx_enable,
1968 .get = ar8xxx_sw_get_mirror_tx_enable,
1969 .max = 1
1970 },
1971 {
1972 .type = SWITCH_TYPE_INT,
1973 .name = "mirror_monitor_port",
1974 .description = "Mirror monitor port",
1975 .set = ar8xxx_sw_set_mirror_monitor_port,
1976 .get = ar8xxx_sw_get_mirror_monitor_port,
1977 .max = AR8216_NUM_PORTS - 1
1978 },
1979 {
1980 .type = SWITCH_TYPE_INT,
1981 .name = "mirror_source_port",
1982 .description = "Mirror source port",
1983 .set = ar8xxx_sw_set_mirror_source_port,
1984 .get = ar8xxx_sw_get_mirror_source_port,
1985 .max = AR8216_NUM_PORTS - 1
1986 },
1987 {
1988 .type = SWITCH_TYPE_STRING,
1989 .name = "arl_table",
1990 .description = "Get ARL table",
1991 .set = NULL,
1992 .get = ar8xxx_sw_get_arl_table,
1993 },
1994 {
1995 .type = SWITCH_TYPE_NOVAL,
1996 .name = "flush_arl_table",
1997 .description = "Flush ARL table",
1998 .set = ar8xxx_sw_set_flush_arl_table,
1999 },
2000 };
2001
2002 const struct switch_attr ar8xxx_sw_attr_port[] = {
2003 {
2004 .type = SWITCH_TYPE_NOVAL,
2005 .name = "reset_mib",
2006 .description = "Reset single port MIB counters",
2007 .set = ar8xxx_sw_set_port_reset_mib,
2008 },
2009 {
2010 .type = SWITCH_TYPE_STRING,
2011 .name = "mib",
2012 .description = "Get port's MIB counters",
2013 .set = NULL,
2014 .get = ar8xxx_sw_get_port_mib,
2015 },
2016 {
2017 .type = SWITCH_TYPE_NOVAL,
2018 .name = "flush_arl_table",
2019 .description = "Flush port's ARL table entries",
2020 .set = ar8xxx_sw_set_flush_port_arl_table,
2021 },
2022 };
2023
2024 const struct switch_attr ar8xxx_sw_attr_vlan[1] = {
2025 {
2026 .type = SWITCH_TYPE_INT,
2027 .name = "vid",
2028 .description = "VLAN ID (0-4094)",
2029 .set = ar8xxx_sw_set_vid,
2030 .get = ar8xxx_sw_get_vid,
2031 .max = 4094,
2032 },
2033 };
2034
2035 static const struct switch_dev_ops ar8xxx_sw_ops = {
2036 .attr_global = {
2037 .attr = ar8xxx_sw_attr_globals,
2038 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2039 },
2040 .attr_port = {
2041 .attr = ar8xxx_sw_attr_port,
2042 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2043 },
2044 .attr_vlan = {
2045 .attr = ar8xxx_sw_attr_vlan,
2046 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2047 },
2048 .get_port_pvid = ar8xxx_sw_get_pvid,
2049 .set_port_pvid = ar8xxx_sw_set_pvid,
2050 .get_vlan_ports = ar8xxx_sw_get_ports,
2051 .set_vlan_ports = ar8xxx_sw_set_ports,
2052 .apply_config = ar8xxx_sw_hw_apply,
2053 .reset_switch = ar8xxx_sw_reset_switch,
2054 .get_port_link = ar8xxx_sw_get_port_link,
2055 .get_port_stats = ar8xxx_sw_get_port_stats,
2056 };
2057
2058 static const struct ar8xxx_chip ar7240sw_chip = {
2059 .caps = AR8XXX_CAP_MIB_COUNTERS,
2060
2061 .reg_port_stats_start = 0x20000,
2062 .reg_port_stats_length = 0x100,
2063 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2064
2065 .name = "Atheros AR724X/AR933X built-in",
2066 .ports = AR7240SW_NUM_PORTS,
2067 .vlans = AR8216_NUM_VLANS,
2068 .swops = &ar8xxx_sw_ops,
2069
2070 .hw_init = ar7240sw_hw_init,
2071 .init_globals = ar7240sw_init_globals,
2072 .init_port = ar8229_init_port,
2073 .phy_read = ar8216_phy_read,
2074 .phy_write = ar8216_phy_write,
2075 .setup_port = ar7240sw_setup_port,
2076 .read_port_status = ar8216_read_port_status,
2077 .atu_flush = ar8216_atu_flush,
2078 .atu_flush_port = ar8216_atu_flush_port,
2079 .vtu_flush = ar8216_vtu_flush,
2080 .vtu_load_vlan = ar8216_vtu_load_vlan,
2081 .set_mirror_regs = ar8216_set_mirror_regs,
2082 .get_arl_entry = ar8216_get_arl_entry,
2083 .sw_hw_apply = ar8xxx_sw_hw_apply,
2084
2085 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2086 .mib_decs = ar8236_mibs,
2087 .mib_func = AR8216_REG_MIB_FUNC,
2088 .mib_rxb_id = AR8236_MIB_RXB_ID,
2089 .mib_txb_id = AR8236_MIB_TXB_ID,
2090 };
2091
2092 static const struct ar8xxx_chip ar8216_chip = {
2093 .caps = AR8XXX_CAP_MIB_COUNTERS,
2094
2095 .reg_port_stats_start = 0x19000,
2096 .reg_port_stats_length = 0xa0,
2097 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2098
2099 .name = "Atheros AR8216",
2100 .ports = AR8216_NUM_PORTS,
2101 .vlans = AR8216_NUM_VLANS,
2102 .swops = &ar8xxx_sw_ops,
2103
2104 .hw_init = ar8216_hw_init,
2105 .init_globals = ar8216_init_globals,
2106 .init_port = ar8216_init_port,
2107 .setup_port = ar8216_setup_port,
2108 .read_port_status = ar8216_read_port_status,
2109 .atu_flush = ar8216_atu_flush,
2110 .atu_flush_port = ar8216_atu_flush_port,
2111 .vtu_flush = ar8216_vtu_flush,
2112 .vtu_load_vlan = ar8216_vtu_load_vlan,
2113 .set_mirror_regs = ar8216_set_mirror_regs,
2114 .get_arl_entry = ar8216_get_arl_entry,
2115 .sw_hw_apply = ar8xxx_sw_hw_apply,
2116
2117 .num_mibs = ARRAY_SIZE(ar8216_mibs),
2118 .mib_decs = ar8216_mibs,
2119 .mib_func = AR8216_REG_MIB_FUNC,
2120 .mib_rxb_id = AR8216_MIB_RXB_ID,
2121 .mib_txb_id = AR8216_MIB_TXB_ID,
2122 };
2123
2124 static const struct ar8xxx_chip ar8229_chip = {
2125 .caps = AR8XXX_CAP_MIB_COUNTERS,
2126
2127 .reg_port_stats_start = 0x20000,
2128 .reg_port_stats_length = 0x100,
2129 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2130
2131 .name = "Atheros AR8229",
2132 .ports = AR8216_NUM_PORTS,
2133 .vlans = AR8216_NUM_VLANS,
2134 .swops = &ar8xxx_sw_ops,
2135
2136 .hw_init = ar8229_hw_init,
2137 .init_globals = ar8229_init_globals,
2138 .init_port = ar8229_init_port,
2139 .phy_read = ar8216_phy_read,
2140 .phy_write = ar8216_phy_write,
2141 .setup_port = ar8236_setup_port,
2142 .read_port_status = ar8216_read_port_status,
2143 .atu_flush = ar8216_atu_flush,
2144 .atu_flush_port = ar8216_atu_flush_port,
2145 .vtu_flush = ar8216_vtu_flush,
2146 .vtu_load_vlan = ar8216_vtu_load_vlan,
2147 .set_mirror_regs = ar8216_set_mirror_regs,
2148 .get_arl_entry = ar8216_get_arl_entry,
2149 .sw_hw_apply = ar8xxx_sw_hw_apply,
2150
2151 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2152 .mib_decs = ar8236_mibs,
2153 .mib_func = AR8216_REG_MIB_FUNC,
2154 .mib_rxb_id = AR8236_MIB_RXB_ID,
2155 .mib_txb_id = AR8236_MIB_TXB_ID,
2156 };
2157
2158 static const struct ar8xxx_chip ar8236_chip = {
2159 .caps = AR8XXX_CAP_MIB_COUNTERS,
2160
2161 .reg_port_stats_start = 0x20000,
2162 .reg_port_stats_length = 0x100,
2163 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2164
2165 .name = "Atheros AR8236",
2166 .ports = AR8216_NUM_PORTS,
2167 .vlans = AR8216_NUM_VLANS,
2168 .swops = &ar8xxx_sw_ops,
2169
2170 .hw_init = ar8216_hw_init,
2171 .init_globals = ar8236_init_globals,
2172 .init_port = ar8216_init_port,
2173 .setup_port = ar8236_setup_port,
2174 .read_port_status = ar8216_read_port_status,
2175 .atu_flush = ar8216_atu_flush,
2176 .atu_flush_port = ar8216_atu_flush_port,
2177 .vtu_flush = ar8216_vtu_flush,
2178 .vtu_load_vlan = ar8216_vtu_load_vlan,
2179 .set_mirror_regs = ar8216_set_mirror_regs,
2180 .get_arl_entry = ar8216_get_arl_entry,
2181 .sw_hw_apply = ar8xxx_sw_hw_apply,
2182
2183 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2184 .mib_decs = ar8236_mibs,
2185 .mib_func = AR8216_REG_MIB_FUNC,
2186 .mib_rxb_id = AR8236_MIB_RXB_ID,
2187 .mib_txb_id = AR8236_MIB_TXB_ID,
2188 };
2189
2190 static const struct ar8xxx_chip ar8316_chip = {
2191 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
2192
2193 .reg_port_stats_start = 0x20000,
2194 .reg_port_stats_length = 0x100,
2195 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2196
2197 .name = "Atheros AR8316",
2198 .ports = AR8216_NUM_PORTS,
2199 .vlans = AR8X16_MAX_VLANS,
2200 .swops = &ar8xxx_sw_ops,
2201
2202 .hw_init = ar8316_hw_init,
2203 .init_globals = ar8316_init_globals,
2204 .init_port = ar8216_init_port,
2205 .setup_port = ar8216_setup_port,
2206 .read_port_status = ar8216_read_port_status,
2207 .atu_flush = ar8216_atu_flush,
2208 .atu_flush_port = ar8216_atu_flush_port,
2209 .vtu_flush = ar8216_vtu_flush,
2210 .vtu_load_vlan = ar8216_vtu_load_vlan,
2211 .set_mirror_regs = ar8216_set_mirror_regs,
2212 .get_arl_entry = ar8216_get_arl_entry,
2213 .sw_hw_apply = ar8xxx_sw_hw_apply,
2214
2215 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2216 .mib_decs = ar8236_mibs,
2217 .mib_func = AR8216_REG_MIB_FUNC,
2218 .mib_rxb_id = AR8236_MIB_RXB_ID,
2219 .mib_txb_id = AR8236_MIB_TXB_ID,
2220 };
2221
2222 static int
2223 ar8xxx_read_id(struct ar8xxx_priv *priv)
2224 {
2225 u32 val;
2226 u16 id;
2227 int i;
2228
2229 val = ar8xxx_read(priv, AR8216_REG_CTRL);
2230 if (val == ~0)
2231 return -ENODEV;
2232
2233 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2234 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2235 u16 t;
2236
2237 val = ar8xxx_read(priv, AR8216_REG_CTRL);
2238 if (val == ~0)
2239 return -ENODEV;
2240
2241 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2242 if (t != id)
2243 return -ENODEV;
2244 }
2245
2246 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2247 priv->chip_rev = (id & AR8216_CTRL_REVISION);
2248 return 0;
2249 }
2250
2251 static int
2252 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2253 {
2254 int ret;
2255
2256 ret = ar8xxx_read_id(priv);
2257 if(ret)
2258 return ret;
2259
2260 switch (priv->chip_ver) {
2261 case AR8XXX_VER_AR8216:
2262 priv->chip = &ar8216_chip;
2263 break;
2264 case AR8XXX_VER_AR8236:
2265 priv->chip = &ar8236_chip;
2266 break;
2267 case AR8XXX_VER_AR8316:
2268 priv->chip = &ar8316_chip;
2269 break;
2270 case AR8XXX_VER_AR8327:
2271 priv->chip = &ar8327_chip;
2272 break;
2273 case AR8XXX_VER_AR8337:
2274 priv->chip = &ar8337_chip;
2275 break;
2276 default:
2277 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2278 priv->chip_ver, priv->chip_rev);
2279
2280 return -ENODEV;
2281 }
2282
2283 return 0;
2284 }
2285
2286 static void
2287 ar8xxx_mib_work_func(struct work_struct *work)
2288 {
2289 struct ar8xxx_priv *priv;
2290 int err, i;
2291
2292 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2293
2294 mutex_lock(&priv->mib_lock);
2295
2296 err = ar8xxx_mib_capture(priv);
2297 if (err)
2298 goto next_attempt;
2299
2300 for (i = 0; i < priv->dev.ports; i++)
2301 ar8xxx_mib_fetch_port_stat(priv, i, false);
2302
2303 next_attempt:
2304 mutex_unlock(&priv->mib_lock);
2305 schedule_delayed_work(&priv->mib_work,
2306 msecs_to_jiffies(priv->mib_poll_interval));
2307 }
2308
2309 static int
2310 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2311 {
2312 unsigned int len;
2313
2314 if (!ar8xxx_has_mib_counters(priv))
2315 return 0;
2316
2317 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2318
2319 len = priv->dev.ports * priv->chip->num_mibs *
2320 sizeof(*priv->mib_stats);
2321 priv->mib_stats = kzalloc(len, GFP_KERNEL);
2322
2323 if (!priv->mib_stats)
2324 return -ENOMEM;
2325
2326 return 0;
2327 }
2328
2329 static void
2330 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2331 {
2332 if (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval)
2333 return;
2334
2335 schedule_delayed_work(&priv->mib_work,
2336 msecs_to_jiffies(priv->mib_poll_interval));
2337 }
2338
2339 static void
2340 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2341 {
2342 if (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval)
2343 return;
2344
2345 cancel_delayed_work_sync(&priv->mib_work);
2346 }
2347
2348 static struct ar8xxx_priv *
2349 ar8xxx_create(void)
2350 {
2351 struct ar8xxx_priv *priv;
2352
2353 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2354 if (priv == NULL)
2355 return NULL;
2356
2357 mutex_init(&priv->reg_mutex);
2358 mutex_init(&priv->mib_lock);
2359 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2360
2361 return priv;
2362 }
2363
2364 static void
2365 ar8xxx_free(struct ar8xxx_priv *priv)
2366 {
2367 if (priv->chip && priv->chip->cleanup)
2368 priv->chip->cleanup(priv);
2369
2370 kfree(priv->chip_data);
2371 kfree(priv->mib_stats);
2372 kfree(priv);
2373 }
2374
2375 static int
2376 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2377 {
2378 const struct ar8xxx_chip *chip;
2379 struct switch_dev *swdev;
2380 int ret;
2381
2382 chip = priv->chip;
2383
2384 swdev = &priv->dev;
2385 swdev->cpu_port = AR8216_PORT_CPU;
2386 swdev->name = chip->name;
2387 swdev->vlans = chip->vlans;
2388 swdev->ports = chip->ports;
2389 swdev->ops = chip->swops;
2390
2391 ret = ar8xxx_mib_init(priv);
2392 if (ret)
2393 return ret;
2394
2395 return 0;
2396 }
2397
2398 static int
2399 ar8xxx_start(struct ar8xxx_priv *priv)
2400 {
2401 int ret;
2402
2403 priv->init = true;
2404
2405 ret = priv->chip->hw_init(priv);
2406 if (ret)
2407 return ret;
2408
2409 ret = ar8xxx_sw_reset_switch(&priv->dev);
2410 if (ret)
2411 return ret;
2412
2413 priv->init = false;
2414
2415 ar8xxx_mib_start(priv);
2416
2417 return 0;
2418 }
2419
2420 static int
2421 ar8xxx_phy_config_init(struct phy_device *phydev)
2422 {
2423 struct ar8xxx_priv *priv = phydev->priv;
2424 struct net_device *dev = phydev->attached_dev;
2425 int ret;
2426
2427 if (WARN_ON(!priv))
2428 return -ENODEV;
2429
2430 if (priv->chip->config_at_probe)
2431 return ar8xxx_phy_check_aneg(phydev);
2432
2433 priv->phy = phydev;
2434
2435 if (phydev->mdio.addr != 0) {
2436 if (chip_is_ar8316(priv)) {
2437 /* switch device has been initialized, reinit */
2438 priv->dev.ports = (AR8216_NUM_PORTS - 1);
2439 priv->initialized = false;
2440 priv->port4_phy = true;
2441 ar8316_hw_init(priv);
2442 return 0;
2443 }
2444
2445 return 0;
2446 }
2447
2448 ret = ar8xxx_start(priv);
2449 if (ret)
2450 return ret;
2451
2452 /* VID fixup only needed on ar8216 */
2453 if (chip_is_ar8216(priv)) {
2454 dev->phy_ptr = priv;
2455 dev->priv_flags |= IFF_NO_IP_ALIGN;
2456 dev->eth_mangle_rx = ar8216_mangle_rx;
2457 dev->eth_mangle_tx = ar8216_mangle_tx;
2458 }
2459
2460 return 0;
2461 }
2462
2463 static bool
2464 ar8xxx_check_link_states(struct ar8xxx_priv *priv)
2465 {
2466 bool link_new, changed = false;
2467 u32 status;
2468 int i;
2469
2470 mutex_lock(&priv->reg_mutex);
2471
2472 for (i = 0; i < priv->dev.ports; i++) {
2473 status = priv->chip->read_port_status(priv, i);
2474 link_new = !!(status & AR8216_PORT_STATUS_LINK_UP);
2475 if (link_new == priv->link_up[i])
2476 continue;
2477
2478 priv->link_up[i] = link_new;
2479 changed = true;
2480 /* flush ARL entries for this port if it went down*/
2481 if (!link_new)
2482 priv->chip->atu_flush_port(priv, i);
2483 dev_info(&priv->phy->mdio.dev, "Port %d is %s\n",
2484 i, link_new ? "up" : "down");
2485 }
2486
2487 mutex_unlock(&priv->reg_mutex);
2488
2489 return changed;
2490 }
2491
2492 static int
2493 ar8xxx_phy_read_status(struct phy_device *phydev)
2494 {
2495 struct ar8xxx_priv *priv = phydev->priv;
2496 struct switch_port_link link;
2497
2498 /* check for switch port link changes */
2499 ar8xxx_check_link_states(priv);
2500
2501 if (phydev->mdio.addr != 0)
2502 return genphy_read_status(phydev);
2503
2504 ar8216_read_port_link(priv, phydev->mdio.addr, &link);
2505 phydev->link = !!link.link;
2506 if (!phydev->link)
2507 return 0;
2508
2509 switch (link.speed) {
2510 case SWITCH_PORT_SPEED_10:
2511 phydev->speed = SPEED_10;
2512 break;
2513 case SWITCH_PORT_SPEED_100:
2514 phydev->speed = SPEED_100;
2515 break;
2516 case SWITCH_PORT_SPEED_1000:
2517 phydev->speed = SPEED_1000;
2518 break;
2519 default:
2520 phydev->speed = 0;
2521 }
2522 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2523
2524 phydev->state = PHY_RUNNING;
2525 netif_carrier_on(phydev->attached_dev);
2526 if (phydev->adjust_link)
2527 phydev->adjust_link(phydev->attached_dev);
2528
2529 return 0;
2530 }
2531
2532 static int
2533 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2534 {
2535 if (phydev->mdio.addr == 0)
2536 return 0;
2537
2538 return genphy_config_aneg(phydev);
2539 }
2540
2541 static const u32 ar8xxx_phy_ids[] = {
2542 0x004dd033,
2543 0x004dd034, /* AR8327 */
2544 0x004dd036, /* AR8337 */
2545 0x004dd041,
2546 0x004dd042,
2547 0x004dd043, /* AR8236 */
2548 };
2549
2550 static bool
2551 ar8xxx_phy_match(u32 phy_id)
2552 {
2553 int i;
2554
2555 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2556 if (phy_id == ar8xxx_phy_ids[i])
2557 return true;
2558
2559 return false;
2560 }
2561
2562 static bool
2563 ar8xxx_is_possible(struct mii_bus *bus)
2564 {
2565 unsigned int i, found_phys = 0;
2566
2567 for (i = 0; i < 5; i++) {
2568 u32 phy_id;
2569
2570 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2571 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2572 if (ar8xxx_phy_match(phy_id)) {
2573 found_phys++;
2574 } else if (phy_id) {
2575 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2576 dev_name(&bus->dev), i, phy_id);
2577 }
2578 }
2579 return !!found_phys;
2580 }
2581
2582 static int
2583 ar8xxx_phy_probe(struct phy_device *phydev)
2584 {
2585 struct ar8xxx_priv *priv;
2586 struct switch_dev *swdev;
2587 int ret;
2588
2589 /* skip PHYs at unused adresses */
2590 if (phydev->mdio.addr != 0 && phydev->mdio.addr != 3 && phydev->mdio.addr != 4)
2591 return -ENODEV;
2592
2593 if (!ar8xxx_is_possible(phydev->mdio.bus))
2594 return -ENODEV;
2595
2596 mutex_lock(&ar8xxx_dev_list_lock);
2597 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2598 if (priv->mii_bus == phydev->mdio.bus)
2599 goto found;
2600
2601 priv = ar8xxx_create();
2602 if (priv == NULL) {
2603 ret = -ENOMEM;
2604 goto unlock;
2605 }
2606
2607 priv->mii_bus = phydev->mdio.bus;
2608 priv->pdev = &phydev->mdio.dev;
2609
2610 ret = of_property_read_u32(priv->pdev->of_node, "qca,mib-poll-interval",
2611 &priv->mib_poll_interval);
2612 if (ret)
2613 priv->mib_poll_interval = 0;
2614
2615 ret = ar8xxx_id_chip(priv);
2616 if (ret)
2617 goto free_priv;
2618
2619 ret = ar8xxx_probe_switch(priv);
2620 if (ret)
2621 goto free_priv;
2622
2623 swdev = &priv->dev;
2624 swdev->alias = dev_name(&priv->mii_bus->dev);
2625 ret = register_switch(swdev, NULL);
2626 if (ret)
2627 goto free_priv;
2628
2629 pr_info("%s: %s rev. %u switch registered on %s\n",
2630 swdev->devname, swdev->name, priv->chip_rev,
2631 dev_name(&priv->mii_bus->dev));
2632
2633 list_add(&priv->list, &ar8xxx_dev_list);
2634
2635 found:
2636 priv->use_count++;
2637
2638 if (phydev->mdio.addr == 0) {
2639 linkmode_zero(phydev->supported);
2640 if (ar8xxx_has_gige(priv))
2641 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, phydev->supported);
2642 else
2643 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, phydev->supported);
2644 linkmode_copy(phydev->advertising, phydev->supported);
2645
2646 if (priv->chip->config_at_probe) {
2647 priv->phy = phydev;
2648
2649 ret = ar8xxx_start(priv);
2650 if (ret)
2651 goto err_unregister_switch;
2652 }
2653 } else {
2654 if (ar8xxx_has_gige(priv)) {
2655 linkmode_zero(phydev->supported);
2656 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, phydev->supported);
2657 linkmode_copy(phydev->advertising, phydev->supported);
2658 }
2659 if (priv->chip->phy_rgmii_set)
2660 priv->chip->phy_rgmii_set(priv, phydev);
2661 }
2662
2663 phydev->priv = priv;
2664
2665 mutex_unlock(&ar8xxx_dev_list_lock);
2666
2667 return 0;
2668
2669 err_unregister_switch:
2670 if (--priv->use_count)
2671 goto unlock;
2672
2673 unregister_switch(&priv->dev);
2674
2675 free_priv:
2676 ar8xxx_free(priv);
2677 unlock:
2678 mutex_unlock(&ar8xxx_dev_list_lock);
2679 return ret;
2680 }
2681
2682 static void
2683 ar8xxx_phy_detach(struct phy_device *phydev)
2684 {
2685 struct net_device *dev = phydev->attached_dev;
2686
2687 if (!dev)
2688 return;
2689
2690 dev->phy_ptr = NULL;
2691 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2692 dev->eth_mangle_rx = NULL;
2693 dev->eth_mangle_tx = NULL;
2694 }
2695
2696 static void
2697 ar8xxx_phy_remove(struct phy_device *phydev)
2698 {
2699 struct ar8xxx_priv *priv = phydev->priv;
2700
2701 if (WARN_ON(!priv))
2702 return;
2703
2704 phydev->priv = NULL;
2705
2706 mutex_lock(&ar8xxx_dev_list_lock);
2707
2708 if (--priv->use_count > 0) {
2709 mutex_unlock(&ar8xxx_dev_list_lock);
2710 return;
2711 }
2712
2713 list_del(&priv->list);
2714 mutex_unlock(&ar8xxx_dev_list_lock);
2715
2716 unregister_switch(&priv->dev);
2717 ar8xxx_mib_stop(priv);
2718 ar8xxx_free(priv);
2719 }
2720
2721 static int
2722 ar8xxx_phy_soft_reset(struct phy_device *phydev)
2723 {
2724 /* we don't need an extra reset */
2725 return 0;
2726 }
2727
2728 static struct phy_driver ar8xxx_phy_driver[] = {
2729 {
2730 .phy_id = 0x004d0000,
2731 .name = "Atheros AR8216/AR8236/AR8316",
2732 .phy_id_mask = 0xffff0000,
2733 .features = PHY_BASIC_FEATURES,
2734 .probe = ar8xxx_phy_probe,
2735 .remove = ar8xxx_phy_remove,
2736 .detach = ar8xxx_phy_detach,
2737 .config_init = ar8xxx_phy_config_init,
2738 .config_aneg = ar8xxx_phy_config_aneg,
2739 .read_status = ar8xxx_phy_read_status,
2740 .soft_reset = ar8xxx_phy_soft_reset,
2741 }
2742 };
2743
2744 static const struct of_device_id ar8xxx_mdiodev_of_match[] = {
2745 {
2746 .compatible = "qca,ar7240sw",
2747 .data = &ar7240sw_chip,
2748 }, {
2749 .compatible = "qca,ar8229",
2750 .data = &ar8229_chip,
2751 }, {
2752 .compatible = "qca,ar8236",
2753 .data = &ar8236_chip,
2754 }, {
2755 .compatible = "qca,ar8327",
2756 .data = &ar8327_chip,
2757 },
2758 { /* sentinel */ },
2759 };
2760
2761 static int
2762 ar8xxx_mdiodev_probe(struct mdio_device *mdiodev)
2763 {
2764 const struct of_device_id *match;
2765 struct ar8xxx_priv *priv;
2766 struct switch_dev *swdev;
2767 struct device_node *mdio_node;
2768 int ret;
2769
2770 match = of_match_device(ar8xxx_mdiodev_of_match, &mdiodev->dev);
2771 if (!match)
2772 return -EINVAL;
2773
2774 priv = ar8xxx_create();
2775 if (priv == NULL)
2776 return -ENOMEM;
2777
2778 priv->mii_bus = mdiodev->bus;
2779 priv->pdev = &mdiodev->dev;
2780 priv->chip = (const struct ar8xxx_chip *) match->data;
2781
2782 ret = of_property_read_u32(priv->pdev->of_node, "qca,mib-poll-interval",
2783 &priv->mib_poll_interval);
2784 if (ret)
2785 priv->mib_poll_interval = 0;
2786
2787 ret = ar8xxx_read_id(priv);
2788 if (ret)
2789 goto free_priv;
2790
2791 ret = ar8xxx_probe_switch(priv);
2792 if (ret)
2793 goto free_priv;
2794
2795 if (priv->chip->phy_read && priv->chip->phy_write) {
2796 priv->sw_mii_bus = devm_mdiobus_alloc(&mdiodev->dev);
2797 priv->sw_mii_bus->name = "ar8xxx-mdio";
2798 priv->sw_mii_bus->read = ar8xxx_phy_read;
2799 priv->sw_mii_bus->write = ar8xxx_phy_write;
2800 priv->sw_mii_bus->priv = priv;
2801 priv->sw_mii_bus->parent = &mdiodev->dev;
2802 snprintf(priv->sw_mii_bus->id, MII_BUS_ID_SIZE, "%s",
2803 dev_name(&mdiodev->dev));
2804 mdio_node = of_get_child_by_name(priv->pdev->of_node, "mdio-bus");
2805 ret = of_mdiobus_register(priv->sw_mii_bus, mdio_node);
2806 if (ret)
2807 goto free_priv;
2808 }
2809
2810 swdev = &priv->dev;
2811 swdev->alias = dev_name(&mdiodev->dev);
2812
2813 if (of_property_read_bool(priv->pdev->of_node, "qca,phy4-mii-enable")) {
2814 priv->port4_phy = true;
2815 swdev->ports--;
2816 }
2817
2818 ret = register_switch(swdev, NULL);
2819 if (ret)
2820 goto free_priv;
2821
2822 pr_info("%s: %s rev. %u switch registered on %s\n",
2823 swdev->devname, swdev->name, priv->chip_rev,
2824 dev_name(&priv->mii_bus->dev));
2825
2826 mutex_lock(&ar8xxx_dev_list_lock);
2827 list_add(&priv->list, &ar8xxx_dev_list);
2828 mutex_unlock(&ar8xxx_dev_list_lock);
2829
2830 priv->use_count++;
2831
2832 ret = ar8xxx_start(priv);
2833 if (ret)
2834 goto err_unregister_switch;
2835
2836 dev_set_drvdata(&mdiodev->dev, priv);
2837
2838 return 0;
2839
2840 err_unregister_switch:
2841 if (--priv->use_count)
2842 return ret;
2843
2844 unregister_switch(&priv->dev);
2845
2846 free_priv:
2847 ar8xxx_free(priv);
2848 return ret;
2849 }
2850
2851 static void
2852 ar8xxx_mdiodev_remove(struct mdio_device *mdiodev)
2853 {
2854 struct ar8xxx_priv *priv = dev_get_drvdata(&mdiodev->dev);
2855
2856 if (WARN_ON(!priv))
2857 return;
2858
2859 mutex_lock(&ar8xxx_dev_list_lock);
2860
2861 if (--priv->use_count > 0) {
2862 mutex_unlock(&ar8xxx_dev_list_lock);
2863 return;
2864 }
2865
2866 list_del(&priv->list);
2867 mutex_unlock(&ar8xxx_dev_list_lock);
2868
2869 unregister_switch(&priv->dev);
2870 ar8xxx_mib_stop(priv);
2871 if(priv->sw_mii_bus)
2872 mdiobus_unregister(priv->sw_mii_bus);
2873 ar8xxx_free(priv);
2874 }
2875
2876 static struct mdio_driver ar8xxx_mdio_driver = {
2877 .probe = ar8xxx_mdiodev_probe,
2878 .remove = ar8xxx_mdiodev_remove,
2879 .mdiodrv.driver = {
2880 .name = "ar8xxx-switch",
2881 .of_match_table = ar8xxx_mdiodev_of_match,
2882 },
2883 };
2884
2885 static int __init ar8216_init(void)
2886 {
2887 int ret;
2888
2889 ret = phy_drivers_register(ar8xxx_phy_driver,
2890 ARRAY_SIZE(ar8xxx_phy_driver),
2891 THIS_MODULE);
2892 if (ret)
2893 return ret;
2894
2895 ret = mdio_driver_register(&ar8xxx_mdio_driver);
2896 if (ret)
2897 phy_drivers_unregister(ar8xxx_phy_driver,
2898 ARRAY_SIZE(ar8xxx_phy_driver));
2899
2900 return ret;
2901 }
2902 module_init(ar8216_init);
2903
2904 static void __exit ar8216_exit(void)
2905 {
2906 mdio_driver_unregister(&ar8xxx_mdio_driver);
2907 phy_drivers_unregister(ar8xxx_phy_driver,
2908 ARRAY_SIZE(ar8xxx_phy_driver));
2909 }
2910 module_exit(ar8216_exit);
2911
2912 MODULE_LICENSE("GPL");
OpenWrt Source Repository