generic: ar8216: mdiodev: add qca,phy4-mii-enable option
[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/of_device.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_net.h>
29 #include <linux/bitops.h>
30 #include <net/genetlink.h>
31 #include <linux/switch.h>
32 #include <linux/delay.h>
33 #include <linux/phy.h>
34 #include <linux/etherdevice.h>
35 #include <linux/lockdep.h>
36 #include <linux/ar8216_platform.h>
37 #include <linux/workqueue.h>
38 #include <linux/version.h>
39
40 #include "ar8216.h"
41
42 extern const struct ar8xxx_chip ar8327_chip;
43 extern const struct ar8xxx_chip ar8337_chip;
44
45 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
46
47 #define MIB_DESC(_s , _o, _n) \
48 { \
49 .size = (_s), \
50 .offset = (_o), \
51 .name = (_n), \
52 }
53
54 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
55 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
56 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
57 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
58 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
59 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
60 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
61 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
62 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
63 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
64 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
65 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
66 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
67 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
68 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
69 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
70 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
71 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
72 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
73 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
74 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
75 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
76 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
77 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
78 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
79 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
80 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
81 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
82 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
83 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
84 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
85 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
86 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
87 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
88 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
89 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
90 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
91 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
92 };
93
94 const struct ar8xxx_mib_desc ar8236_mibs[39] = {
95 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
96 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
97 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
98 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
99 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
100 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
101 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
102 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
103 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
104 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
105 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
106 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
107 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
108 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
109 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
110 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
111 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
112 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
113 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
114 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
115 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
116 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
117 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
118 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
119 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
120 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
121 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
122 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
123 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
124 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
125 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
126 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
127 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
128 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
129 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
130 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
131 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
132 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
133 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
134 };
135
136 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
137 static LIST_HEAD(ar8xxx_dev_list);
138
139 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
140 static int
141 ar8xxx_phy_poll_reset(struct mii_bus *bus)
142 {
143 unsigned int sleep_msecs = 20;
144 int ret, elapsed, i;
145
146 for (elapsed = sleep_msecs; elapsed <= 600;
147 elapsed += sleep_msecs) {
148 msleep(sleep_msecs);
149 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
150 ret = mdiobus_read(bus, i, MII_BMCR);
151 if (ret < 0)
152 return ret;
153 if (ret & BMCR_RESET)
154 break;
155 if (i == AR8XXX_NUM_PHYS - 1) {
156 usleep_range(1000, 2000);
157 return 0;
158 }
159 }
160 }
161 return -ETIMEDOUT;
162 }
163
164 static int
165 ar8xxx_phy_check_aneg(struct phy_device *phydev)
166 {
167 int ret;
168
169 if (phydev->autoneg != AUTONEG_ENABLE)
170 return 0;
171 /*
172 * BMCR_ANENABLE might have been cleared
173 * by phy_init_hw in certain kernel versions
174 * therefore check for it
175 */
176 ret = phy_read(phydev, MII_BMCR);
177 if (ret < 0)
178 return ret;
179 if (ret & BMCR_ANENABLE)
180 return 0;
181
182 dev_info(&phydev->mdio.dev, "ANEG disabled, re-enabling ...\n");
183 ret |= BMCR_ANENABLE | BMCR_ANRESTART;
184 return phy_write(phydev, MII_BMCR, ret);
185 }
186
187 void
188 ar8xxx_phy_init(struct ar8xxx_priv *priv)
189 {
190 int i;
191 struct mii_bus *bus;
192
193 bus = priv->sw_mii_bus ?: priv->mii_bus;
194 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
195 if (priv->chip->phy_fixup)
196 priv->chip->phy_fixup(priv, i);
197
198 /* initialize the port itself */
199 mdiobus_write(bus, i, MII_ADVERTISE,
200 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
201 if (ar8xxx_has_gige(priv))
202 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
203 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
204 }
205
206 ar8xxx_phy_poll_reset(bus);
207 }
208
209 u32
210 ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
211 {
212 struct mii_bus *bus = priv->mii_bus;
213 u16 lo, hi;
214
215 lo = bus->read(bus, phy_id, regnum);
216 hi = bus->read(bus, phy_id, regnum + 1);
217
218 return (hi << 16) | lo;
219 }
220
221 void
222 ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
223 {
224 struct mii_bus *bus = priv->mii_bus;
225 u16 lo, hi;
226
227 lo = val & 0xffff;
228 hi = (u16) (val >> 16);
229
230 if (priv->chip->mii_lo_first)
231 {
232 bus->write(bus, phy_id, regnum, lo);
233 bus->write(bus, phy_id, regnum + 1, hi);
234 } else {
235 bus->write(bus, phy_id, regnum + 1, hi);
236 bus->write(bus, phy_id, regnum, lo);
237 }
238 }
239
240 u32
241 ar8xxx_read(struct ar8xxx_priv *priv, int reg)
242 {
243 struct mii_bus *bus = priv->mii_bus;
244 u16 r1, r2, page;
245 u32 val;
246
247 split_addr((u32) reg, &r1, &r2, &page);
248
249 mutex_lock(&bus->mdio_lock);
250
251 bus->write(bus, 0x18, 0, page);
252 wait_for_page_switch();
253 val = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
254
255 mutex_unlock(&bus->mdio_lock);
256
257 return val;
258 }
259
260 void
261 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
262 {
263 struct mii_bus *bus = priv->mii_bus;
264 u16 r1, r2, page;
265
266 split_addr((u32) reg, &r1, &r2, &page);
267
268 mutex_lock(&bus->mdio_lock);
269
270 bus->write(bus, 0x18, 0, page);
271 wait_for_page_switch();
272 ar8xxx_mii_write32(priv, 0x10 | r2, r1, val);
273
274 mutex_unlock(&bus->mdio_lock);
275 }
276
277 u32
278 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
279 {
280 struct mii_bus *bus = priv->mii_bus;
281 u16 r1, r2, page;
282 u32 ret;
283
284 split_addr((u32) reg, &r1, &r2, &page);
285
286 mutex_lock(&bus->mdio_lock);
287
288 bus->write(bus, 0x18, 0, page);
289 wait_for_page_switch();
290
291 ret = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
292 ret &= ~mask;
293 ret |= val;
294 ar8xxx_mii_write32(priv, 0x10 | r2, r1, ret);
295
296 mutex_unlock(&bus->mdio_lock);
297
298 return ret;
299 }
300 void
301 ar8xxx_phy_dbg_read(struct ar8xxx_priv *priv, int phy_addr,
302 u16 dbg_addr, u16 *dbg_data)
303 {
304 struct mii_bus *bus = priv->mii_bus;
305
306 mutex_lock(&bus->mdio_lock);
307 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
308 *dbg_data = bus->read(bus, phy_addr, MII_ATH_DBG_DATA);
309 mutex_unlock(&bus->mdio_lock);
310 }
311
312 void
313 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
314 u16 dbg_addr, u16 dbg_data)
315 {
316 struct mii_bus *bus = priv->mii_bus;
317
318 mutex_lock(&bus->mdio_lock);
319 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
320 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
321 mutex_unlock(&bus->mdio_lock);
322 }
323
324 static inline void
325 ar8xxx_phy_mmd_prep(struct mii_bus *bus, int phy_addr, u16 addr, u16 reg)
326 {
327 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
328 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, reg);
329 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr | 0x4000);
330 }
331
332 void
333 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data)
334 {
335 struct mii_bus *bus = priv->mii_bus;
336
337 mutex_lock(&bus->mdio_lock);
338 ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
339 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
340 mutex_unlock(&bus->mdio_lock);
341 }
342
343 u16
344 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg)
345 {
346 struct mii_bus *bus = priv->mii_bus;
347 u16 data;
348
349 mutex_lock(&bus->mdio_lock);
350 ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
351 data = bus->read(bus, phy_addr, MII_ATH_MMD_DATA);
352 mutex_unlock(&bus->mdio_lock);
353
354 return data;
355 }
356
357 static int
358 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
359 unsigned timeout)
360 {
361 int i;
362
363 for (i = 0; i < timeout; i++) {
364 u32 t;
365
366 t = ar8xxx_read(priv, reg);
367 if ((t & mask) == val)
368 return 0;
369
370 usleep_range(1000, 2000);
371 cond_resched();
372 }
373
374 return -ETIMEDOUT;
375 }
376
377 static int
378 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
379 {
380 unsigned mib_func = priv->chip->mib_func;
381 int ret;
382
383 lockdep_assert_held(&priv->mib_lock);
384
385 /* Capture the hardware statistics for all ports */
386 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
387
388 /* Wait for the capturing to complete. */
389 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
390 if (ret)
391 goto out;
392
393 ret = 0;
394
395 out:
396 return ret;
397 }
398
399 static int
400 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
401 {
402 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
403 }
404
405 static int
406 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
407 {
408 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
409 }
410
411 static void
412 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
413 {
414 unsigned int base;
415 u64 *mib_stats;
416 int i;
417
418 WARN_ON(port >= priv->dev.ports);
419
420 lockdep_assert_held(&priv->mib_lock);
421
422 base = priv->chip->reg_port_stats_start +
423 priv->chip->reg_port_stats_length * port;
424
425 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
426 for (i = 0; i < priv->chip->num_mibs; i++) {
427 const struct ar8xxx_mib_desc *mib;
428 u64 t;
429
430 mib = &priv->chip->mib_decs[i];
431 t = ar8xxx_read(priv, base + mib->offset);
432 if (mib->size == 2) {
433 u64 hi;
434
435 hi = ar8xxx_read(priv, base + mib->offset + 4);
436 t |= hi << 32;
437 }
438
439 if (flush)
440 mib_stats[i] = 0;
441 else
442 mib_stats[i] += t;
443 cond_resched();
444 }
445 }
446
447 static void
448 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
449 struct switch_port_link *link)
450 {
451 u32 status;
452 u32 speed;
453
454 memset(link, '\0', sizeof(*link));
455
456 status = priv->chip->read_port_status(priv, port);
457
458 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
459 if (link->aneg) {
460 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
461 } else {
462 link->link = true;
463
464 if (priv->get_port_link) {
465 int err;
466
467 err = priv->get_port_link(port);
468 if (err >= 0)
469 link->link = !!err;
470 }
471 }
472
473 if (!link->link)
474 return;
475
476 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
477 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
478 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
479
480 if (link->aneg && link->duplex && priv->chip->read_port_eee_status)
481 link->eee = priv->chip->read_port_eee_status(priv, port);
482
483 speed = (status & AR8216_PORT_STATUS_SPEED) >>
484 AR8216_PORT_STATUS_SPEED_S;
485
486 switch (speed) {
487 case AR8216_PORT_SPEED_10M:
488 link->speed = SWITCH_PORT_SPEED_10;
489 break;
490 case AR8216_PORT_SPEED_100M:
491 link->speed = SWITCH_PORT_SPEED_100;
492 break;
493 case AR8216_PORT_SPEED_1000M:
494 link->speed = SWITCH_PORT_SPEED_1000;
495 break;
496 default:
497 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
498 break;
499 }
500 }
501
502 static struct sk_buff *
503 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
504 {
505 struct ar8xxx_priv *priv = dev->phy_ptr;
506 unsigned char *buf;
507
508 if (unlikely(!priv))
509 goto error;
510
511 if (!priv->vlan)
512 goto send;
513
514 if (unlikely(skb_headroom(skb) < 2)) {
515 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
516 goto error;
517 }
518
519 buf = skb_push(skb, 2);
520 buf[0] = 0x10;
521 buf[1] = 0x80;
522
523 send:
524 return skb;
525
526 error:
527 dev_kfree_skb_any(skb);
528 return NULL;
529 }
530
531 static void
532 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
533 {
534 struct ar8xxx_priv *priv;
535 unsigned char *buf;
536 int port, vlan;
537
538 priv = dev->phy_ptr;
539 if (!priv)
540 return;
541
542 /* don't strip the header if vlan mode is disabled */
543 if (!priv->vlan)
544 return;
545
546 /* strip header, get vlan id */
547 buf = skb->data;
548 skb_pull(skb, 2);
549
550 /* check for vlan header presence */
551 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
552 return;
553
554 port = buf[0] & 0x7;
555
556 /* no need to fix up packets coming from a tagged source */
557 if (priv->vlan_tagged & (1 << port))
558 return;
559
560 /* lookup port vid from local table, the switch passes an invalid vlan id */
561 vlan = priv->vlan_id[priv->pvid[port]];
562
563 buf[14 + 2] &= 0xf0;
564 buf[14 + 2] |= vlan >> 8;
565 buf[15 + 2] = vlan & 0xff;
566 }
567
568 int
569 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
570 {
571 int timeout = 20;
572 u32 t = 0;
573
574 while (1) {
575 t = ar8xxx_read(priv, reg);
576 if ((t & mask) == val)
577 return 0;
578
579 if (timeout-- <= 0)
580 break;
581
582 udelay(10);
583 cond_resched();
584 }
585
586 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
587 (unsigned int) reg, t, mask, val);
588 return -ETIMEDOUT;
589 }
590
591 static void
592 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
593 {
594 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
595 return;
596 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
597 val &= AR8216_VTUDATA_MEMBER;
598 val |= AR8216_VTUDATA_VALID;
599 ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
600 }
601 op |= AR8216_VTU_ACTIVE;
602 ar8xxx_write(priv, AR8216_REG_VTU, op);
603 }
604
605 static void
606 ar8216_vtu_flush(struct ar8xxx_priv *priv)
607 {
608 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
609 }
610
611 static void
612 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
613 {
614 u32 op;
615
616 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
617 ar8216_vtu_op(priv, op, port_mask);
618 }
619
620 static int
621 ar8216_atu_flush(struct ar8xxx_priv *priv)
622 {
623 int ret;
624
625 ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
626 if (!ret)
627 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_OP_FLUSH |
628 AR8216_ATU_ACTIVE);
629
630 return ret;
631 }
632
633 static int
634 ar8216_atu_flush_port(struct ar8xxx_priv *priv, int port)
635 {
636 u32 t;
637 int ret;
638
639 ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
640 if (!ret) {
641 t = (port << AR8216_ATU_PORT_NUM_S) | AR8216_ATU_OP_FLUSH_PORT;
642 t |= AR8216_ATU_ACTIVE;
643 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, t);
644 }
645
646 return ret;
647 }
648
649 static u32
650 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
651 {
652 return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
653 }
654
655 static void
656 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
657 {
658 u32 header;
659 u32 egress, ingress;
660 u32 pvid;
661
662 if (priv->vlan) {
663 pvid = priv->vlan_id[priv->pvid[port]];
664 if (priv->vlan_tagged & (1 << port))
665 egress = AR8216_OUT_ADD_VLAN;
666 else
667 egress = AR8216_OUT_STRIP_VLAN;
668 ingress = AR8216_IN_SECURE;
669 } else {
670 pvid = port;
671 egress = AR8216_OUT_KEEP;
672 ingress = AR8216_IN_PORT_ONLY;
673 }
674
675 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
676 header = AR8216_PORT_CTRL_HEADER;
677 else
678 header = 0;
679
680 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
681 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
682 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
683 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
684 AR8216_PORT_CTRL_LEARN | header |
685 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
686 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
687
688 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
689 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
690 AR8216_PORT_VLAN_DEFAULT_ID,
691 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
692 (ingress << AR8216_PORT_VLAN_MODE_S) |
693 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
694 }
695
696 static int
697 ar8216_hw_init(struct ar8xxx_priv *priv)
698 {
699 if (priv->initialized)
700 return 0;
701
702 ar8xxx_phy_init(priv);
703
704 priv->initialized = true;
705 return 0;
706 }
707
708 static void
709 ar8216_init_globals(struct ar8xxx_priv *priv)
710 {
711 /* standard atheros magic */
712 ar8xxx_write(priv, 0x38, 0xc000050e);
713
714 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
715 AR8216_GCTRL_MTU, 1518 + 8 + 2);
716 }
717
718 static void
719 __ar8216_init_port(struct ar8xxx_priv *priv, int port,
720 bool cpu_ge, bool flow_en)
721 {
722 /* Enable port learning and tx */
723 ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
724 AR8216_PORT_CTRL_LEARN |
725 (4 << AR8216_PORT_CTRL_STATE_S));
726
727 ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
728
729 if (port == AR8216_PORT_CPU) {
730 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
731 AR8216_PORT_STATUS_LINK_UP |
732 (cpu_ge ? AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
733 AR8216_PORT_STATUS_TXMAC |
734 AR8216_PORT_STATUS_RXMAC |
735 (flow_en ? AR8216_PORT_STATUS_RXFLOW : 0) |
736 (flow_en ? AR8216_PORT_STATUS_TXFLOW : 0) |
737 AR8216_PORT_STATUS_DUPLEX);
738 } else {
739 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
740 AR8216_PORT_STATUS_LINK_AUTO);
741 }
742 }
743
744 static void
745 ar8216_init_port(struct ar8xxx_priv *priv, int port)
746 {
747 __ar8216_init_port(priv, port, ar8xxx_has_gige(priv),
748 chip_is_ar8316(priv));
749 }
750
751 static void
752 ar8216_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
753 {
754 int timeout = 20;
755
756 while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout) {
757 udelay(10);
758 cond_resched();
759 }
760
761 if (!timeout)
762 pr_err("ar8216: timeout waiting for atu to become ready\n");
763 }
764
765 static void ar8216_get_arl_entry(struct ar8xxx_priv *priv,
766 struct arl_entry *a, u32 *status, enum arl_op op)
767 {
768 struct mii_bus *bus = priv->mii_bus;
769 u16 r2, page;
770 u16 r1_func0, r1_func1, r1_func2;
771 u32 t, val0, val1, val2;
772
773 split_addr(AR8216_REG_ATU_FUNC0, &r1_func0, &r2, &page);
774 r2 |= 0x10;
775
776 r1_func1 = (AR8216_REG_ATU_FUNC1 >> 1) & 0x1e;
777 r1_func2 = (AR8216_REG_ATU_FUNC2 >> 1) & 0x1e;
778
779 switch (op) {
780 case AR8XXX_ARL_INITIALIZE:
781 /* all ATU registers are on the same page
782 * therefore set page only once
783 */
784 bus->write(bus, 0x18, 0, page);
785 wait_for_page_switch();
786
787 ar8216_wait_atu_ready(priv, r2, r1_func0);
788
789 ar8xxx_mii_write32(priv, r2, r1_func0, AR8216_ATU_OP_GET_NEXT);
790 ar8xxx_mii_write32(priv, r2, r1_func1, 0);
791 ar8xxx_mii_write32(priv, r2, r1_func2, 0);
792 break;
793 case AR8XXX_ARL_GET_NEXT:
794 t = ar8xxx_mii_read32(priv, r2, r1_func0);
795 t |= AR8216_ATU_ACTIVE;
796 ar8xxx_mii_write32(priv, r2, r1_func0, t);
797 ar8216_wait_atu_ready(priv, r2, r1_func0);
798
799 val0 = ar8xxx_mii_read32(priv, r2, r1_func0);
800 val1 = ar8xxx_mii_read32(priv, r2, r1_func1);
801 val2 = ar8xxx_mii_read32(priv, r2, r1_func2);
802
803 *status = (val2 & AR8216_ATU_STATUS) >> AR8216_ATU_STATUS_S;
804 if (!*status)
805 break;
806
807 a->portmap = (val2 & AR8216_ATU_PORTS) >> AR8216_ATU_PORTS_S;
808 a->mac[0] = (val0 & AR8216_ATU_ADDR5) >> AR8216_ATU_ADDR5_S;
809 a->mac[1] = (val0 & AR8216_ATU_ADDR4) >> AR8216_ATU_ADDR4_S;
810 a->mac[2] = (val1 & AR8216_ATU_ADDR3) >> AR8216_ATU_ADDR3_S;
811 a->mac[3] = (val1 & AR8216_ATU_ADDR2) >> AR8216_ATU_ADDR2_S;
812 a->mac[4] = (val1 & AR8216_ATU_ADDR1) >> AR8216_ATU_ADDR1_S;
813 a->mac[5] = (val1 & AR8216_ATU_ADDR0) >> AR8216_ATU_ADDR0_S;
814 break;
815 }
816 }
817
818 static int
819 ar8216_phy_read(struct ar8xxx_priv *priv, int addr, int regnum)
820 {
821 u32 t, val = 0xffff;
822 int err;
823
824 if (addr >= AR8216_NUM_PORTS)
825 return 0xffff;
826 t = (regnum << AR8216_MDIO_CTRL_REG_ADDR_S) |
827 (addr << AR8216_MDIO_CTRL_PHY_ADDR_S) |
828 AR8216_MDIO_CTRL_MASTER_EN |
829 AR8216_MDIO_CTRL_BUSY |
830 AR8216_MDIO_CTRL_CMD_READ;
831
832 ar8xxx_write(priv, AR8216_REG_MDIO_CTRL, t);
833 err = ar8xxx_reg_wait(priv, AR8216_REG_MDIO_CTRL,
834 AR8216_MDIO_CTRL_BUSY, 0, 5);
835 if (!err)
836 val = ar8xxx_read(priv, AR8216_REG_MDIO_CTRL);
837
838 return val & AR8216_MDIO_CTRL_DATA_M;
839 }
840
841 static int
842 ar8216_phy_write(struct ar8xxx_priv *priv, int addr, int regnum, u16 val)
843 {
844 u32 t;
845 int ret;
846
847 if (addr >= AR8216_NUM_PORTS)
848 return -EINVAL;
849
850 t = (addr << AR8216_MDIO_CTRL_PHY_ADDR_S) |
851 (regnum << AR8216_MDIO_CTRL_REG_ADDR_S) |
852 AR8216_MDIO_CTRL_MASTER_EN |
853 AR8216_MDIO_CTRL_BUSY |
854 AR8216_MDIO_CTRL_CMD_WRITE |
855 val;
856
857 ar8xxx_write(priv, AR8216_REG_MDIO_CTRL, t);
858 ret = ar8xxx_reg_wait(priv, AR8216_REG_MDIO_CTRL,
859 AR8216_MDIO_CTRL_BUSY, 0, 5);
860
861 return ret;
862 }
863
864 static int
865 ar8229_hw_init(struct ar8xxx_priv *priv)
866 {
867 int phy_if_mode;
868
869 if (priv->initialized)
870 return 0;
871
872 ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);
873 ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);
874
875 phy_if_mode = of_get_phy_mode(priv->pdev->of_node);
876
877 if (phy_if_mode == PHY_INTERFACE_MODE_GMII) {
878 ar8xxx_write(priv, AR8229_REG_OPER_MODE0,
879 AR8229_OPER_MODE0_MAC_GMII_EN);
880 } else if (phy_if_mode == PHY_INTERFACE_MODE_MII) {
881 ar8xxx_write(priv, AR8229_REG_OPER_MODE0,
882 AR8229_OPER_MODE0_PHY_MII_EN);
883 } else {
884 pr_err("ar8229: unsupported mii mode\n");
885 return -EINVAL;
886 }
887
888 if (priv->port4_phy)
889 ar8xxx_write(priv, AR8229_REG_OPER_MODE1,
890 AR8229_REG_OPER_MODE1_PHY4_MII_EN);
891
892 ar8xxx_phy_init(priv);
893
894 priv->initialized = true;
895 return 0;
896 }
897
898 static void
899 ar8229_init_globals(struct ar8xxx_priv *priv)
900 {
901
902 /* Enable CPU port, and disable mirror port */
903 ar8xxx_write(priv, AR8216_REG_GLOBAL_CPUPORT,
904 AR8216_GLOBAL_CPUPORT_EN |
905 (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
906
907 /* Setup TAG priority mapping */
908 ar8xxx_write(priv, AR8216_REG_TAG_PRIORITY, 0xfa50);
909
910 /* Enable aging, MAC replacing */
911 ar8xxx_write(priv, AR8216_REG_ATU_CTRL,
912 0x2b /* 5 min age time */ |
913 AR8216_ATU_CTRL_AGE_EN |
914 AR8216_ATU_CTRL_LEARN_CHANGE);
915
916 /* Enable ARP frame acknowledge */
917 ar8xxx_reg_set(priv, AR8229_REG_QM_CTRL,
918 AR8229_QM_CTRL_ARP_EN);
919
920 /* Enable Broadcast/Multicast frames transmitted to the CPU */
921 ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
922 AR8229_FLOOD_MASK_BC_DP(0) |
923 AR8229_FLOOD_MASK_MC_DP(0));
924
925 /* setup MTU */
926 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
927 AR8236_GCTRL_MTU, AR8236_GCTRL_MTU);
928
929 /* Enable MIB counters */
930 ar8xxx_reg_set(priv, AR8216_REG_MIB_FUNC,
931 AR8236_MIB_EN);
932
933 /* setup Service TAG */
934 ar8xxx_rmw(priv, AR8216_REG_SERVICE_TAG, AR8216_SERVICE_TAG_M, 0);
935 }
936
937 static void
938 ar8229_init_port(struct ar8xxx_priv *priv, int port)
939 {
940 __ar8216_init_port(priv, port, true, true);
941 }
942
943 static void
944 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
945 {
946 u32 egress, ingress;
947 u32 pvid;
948
949 if (priv->vlan) {
950 pvid = priv->vlan_id[priv->pvid[port]];
951 if (priv->vlan_tagged & (1 << port))
952 egress = AR8216_OUT_ADD_VLAN;
953 else
954 egress = AR8216_OUT_STRIP_VLAN;
955 ingress = AR8216_IN_SECURE;
956 } else {
957 pvid = port;
958 egress = AR8216_OUT_KEEP;
959 ingress = AR8216_IN_PORT_ONLY;
960 }
961
962 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
963 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
964 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
965 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
966 AR8216_PORT_CTRL_LEARN |
967 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
968 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
969
970 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
971 AR8236_PORT_VLAN_DEFAULT_ID,
972 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
973
974 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
975 AR8236_PORT_VLAN2_VLAN_MODE |
976 AR8236_PORT_VLAN2_MEMBER,
977 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
978 (members << AR8236_PORT_VLAN2_MEMBER_S));
979 }
980
981 static void
982 ar8236_init_globals(struct ar8xxx_priv *priv)
983 {
984 /* enable jumbo frames */
985 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
986 AR8316_GCTRL_MTU, 9018 + 8 + 2);
987
988 /* enable cpu port to receive arp frames */
989 ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,
990 AR8236_ATU_CTRL_RES);
991
992 /* enable cpu port to receive multicast and broadcast frames */
993 ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
994 AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
995
996 /* Enable MIB counters */
997 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
998 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
999 AR8236_MIB_EN);
1000 }
1001
1002 static int
1003 ar8316_hw_init(struct ar8xxx_priv *priv)
1004 {
1005 u32 val, newval;
1006
1007 val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
1008
1009 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
1010 if (priv->port4_phy) {
1011 /* value taken from Ubiquiti RouterStation Pro */
1012 newval = 0x81461bea;
1013 pr_info("ar8316: Using port 4 as PHY\n");
1014 } else {
1015 newval = 0x01261be2;
1016 pr_info("ar8316: Using port 4 as switch port\n");
1017 }
1018 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
1019 /* value taken from AVM Fritz!Box 7390 sources */
1020 newval = 0x010e5b71;
1021 } else {
1022 /* no known value for phy interface */
1023 pr_err("ar8316: unsupported mii mode: %d.\n",
1024 priv->phy->interface);
1025 return -EINVAL;
1026 }
1027
1028 if (val == newval)
1029 goto out;
1030
1031 ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
1032
1033 if (priv->port4_phy &&
1034 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
1035 /* work around for phy4 rgmii mode */
1036 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
1037 /* rx delay */
1038 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
1039 /* tx delay */
1040 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
1041 msleep(1000);
1042 }
1043
1044 ar8xxx_phy_init(priv);
1045
1046 out:
1047 priv->initialized = true;
1048 return 0;
1049 }
1050
1051 static void
1052 ar8316_init_globals(struct ar8xxx_priv *priv)
1053 {
1054 /* standard atheros magic */
1055 ar8xxx_write(priv, 0x38, 0xc000050e);
1056
1057 /* enable cpu port to receive multicast and broadcast frames */
1058 ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
1059
1060 /* enable jumbo frames */
1061 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1062 AR8316_GCTRL_MTU, 9018 + 8 + 2);
1063
1064 /* Enable MIB counters */
1065 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1066 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1067 AR8236_MIB_EN);
1068 }
1069
1070 int
1071 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1072 struct switch_val *val)
1073 {
1074 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1075 priv->vlan = !!val->value.i;
1076 return 0;
1077 }
1078
1079 int
1080 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1081 struct switch_val *val)
1082 {
1083 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1084 val->value.i = priv->vlan;
1085 return 0;
1086 }
1087
1088
1089 int
1090 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1091 {
1092 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1093
1094 /* make sure no invalid PVIDs get set */
1095
1096 if (vlan < 0 || vlan >= dev->vlans ||
1097 port < 0 || port >= AR8X16_MAX_PORTS)
1098 return -EINVAL;
1099
1100 priv->pvid[port] = vlan;
1101 return 0;
1102 }
1103
1104 int
1105 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1106 {
1107 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1108
1109 if (port < 0 || port >= AR8X16_MAX_PORTS)
1110 return -EINVAL;
1111
1112 *vlan = priv->pvid[port];
1113 return 0;
1114 }
1115
1116 static int
1117 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1118 struct switch_val *val)
1119 {
1120 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1121
1122 if (val->port_vlan >= AR8X16_MAX_VLANS)
1123 return -EINVAL;
1124
1125 priv->vlan_id[val->port_vlan] = val->value.i;
1126 return 0;
1127 }
1128
1129 static int
1130 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1131 struct switch_val *val)
1132 {
1133 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1134 val->value.i = priv->vlan_id[val->port_vlan];
1135 return 0;
1136 }
1137
1138 int
1139 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1140 struct switch_port_link *link)
1141 {
1142 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1143
1144 ar8216_read_port_link(priv, port, link);
1145 return 0;
1146 }
1147
1148 static int
1149 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1150 {
1151 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1152 u8 ports;
1153 int i;
1154
1155 if (val->port_vlan >= AR8X16_MAX_VLANS)
1156 return -EINVAL;
1157
1158 ports = priv->vlan_table[val->port_vlan];
1159 val->len = 0;
1160 for (i = 0; i < dev->ports; i++) {
1161 struct switch_port *p;
1162
1163 if (!(ports & (1 << i)))
1164 continue;
1165
1166 p = &val->value.ports[val->len++];
1167 p->id = i;
1168 if (priv->vlan_tagged & (1 << i))
1169 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1170 else
1171 p->flags = 0;
1172 }
1173 return 0;
1174 }
1175
1176 static int
1177 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1178 {
1179 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1180 u8 *vt = &priv->vlan_table[val->port_vlan];
1181 int i, j;
1182
1183 *vt = 0;
1184 for (i = 0; i < val->len; i++) {
1185 struct switch_port *p = &val->value.ports[i];
1186
1187 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1188 priv->vlan_tagged |= (1 << p->id);
1189 } else {
1190 priv->vlan_tagged &= ~(1 << p->id);
1191 priv->pvid[p->id] = val->port_vlan;
1192
1193 /* make sure that an untagged port does not
1194 * appear in other vlans */
1195 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1196 if (j == val->port_vlan)
1197 continue;
1198 priv->vlan_table[j] &= ~(1 << p->id);
1199 }
1200 }
1201
1202 *vt |= 1 << p->id;
1203 }
1204 return 0;
1205 }
1206
1207 static void
1208 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
1209 {
1210 int port;
1211
1212 /* reset all mirror registers */
1213 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1214 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1215 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1216 for (port = 0; port < AR8216_NUM_PORTS; port++) {
1217 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1218 AR8216_PORT_CTRL_MIRROR_RX);
1219
1220 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1221 AR8216_PORT_CTRL_MIRROR_TX);
1222 }
1223
1224 /* now enable mirroring if necessary */
1225 if (priv->source_port >= AR8216_NUM_PORTS ||
1226 priv->monitor_port >= AR8216_NUM_PORTS ||
1227 priv->source_port == priv->monitor_port) {
1228 return;
1229 }
1230
1231 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1232 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1233 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1234
1235 if (priv->mirror_rx)
1236 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1237 AR8216_PORT_CTRL_MIRROR_RX);
1238
1239 if (priv->mirror_tx)
1240 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1241 AR8216_PORT_CTRL_MIRROR_TX);
1242 }
1243
1244 static inline u32
1245 ar8xxx_age_time_val(int age_time)
1246 {
1247 return (age_time + AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS / 2) /
1248 AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS;
1249 }
1250
1251 static inline void
1252 ar8xxx_set_age_time(struct ar8xxx_priv *priv, int reg)
1253 {
1254 u32 age_time = ar8xxx_age_time_val(priv->arl_age_time);
1255 ar8xxx_rmw(priv, reg, AR8216_ATU_CTRL_AGE_TIME, age_time << AR8216_ATU_CTRL_AGE_TIME_S);
1256 }
1257
1258 int
1259 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1260 {
1261 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1262 const struct ar8xxx_chip *chip = priv->chip;
1263 u8 portmask[AR8X16_MAX_PORTS];
1264 int i, j;
1265
1266 mutex_lock(&priv->reg_mutex);
1267 /* flush all vlan translation unit entries */
1268 priv->chip->vtu_flush(priv);
1269
1270 memset(portmask, 0, sizeof(portmask));
1271 if (!priv->init) {
1272 /* calculate the port destination masks and load vlans
1273 * into the vlan translation unit */
1274 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1275 u8 vp = priv->vlan_table[j];
1276
1277 if (!vp)
1278 continue;
1279
1280 for (i = 0; i < dev->ports; i++) {
1281 u8 mask = (1 << i);
1282 if (vp & mask)
1283 portmask[i] |= vp & ~mask;
1284 }
1285
1286 chip->vtu_load_vlan(priv, priv->vlan_id[j],
1287 priv->vlan_table[j]);
1288 }
1289 } else {
1290 /* vlan disabled:
1291 * isolate all ports, but connect them to the cpu port */
1292 for (i = 0; i < dev->ports; i++) {
1293 if (i == AR8216_PORT_CPU)
1294 continue;
1295
1296 portmask[i] = 1 << AR8216_PORT_CPU;
1297 portmask[AR8216_PORT_CPU] |= (1 << i);
1298 }
1299 }
1300
1301 /* update the port destination mask registers and tag settings */
1302 for (i = 0; i < dev->ports; i++) {
1303 chip->setup_port(priv, i, portmask[i]);
1304 }
1305
1306 chip->set_mirror_regs(priv);
1307
1308 /* set age time */
1309 if (chip->reg_arl_ctrl)
1310 ar8xxx_set_age_time(priv, chip->reg_arl_ctrl);
1311
1312 mutex_unlock(&priv->reg_mutex);
1313 return 0;
1314 }
1315
1316 int
1317 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1318 {
1319 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1320 const struct ar8xxx_chip *chip = priv->chip;
1321 int i;
1322
1323 mutex_lock(&priv->reg_mutex);
1324 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1325 offsetof(struct ar8xxx_priv, vlan));
1326
1327 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1328 priv->vlan_id[i] = i;
1329
1330 /* Configure all ports */
1331 for (i = 0; i < dev->ports; i++)
1332 chip->init_port(priv, i);
1333
1334 priv->mirror_rx = false;
1335 priv->mirror_tx = false;
1336 priv->source_port = 0;
1337 priv->monitor_port = 0;
1338 priv->arl_age_time = AR8XXX_DEFAULT_ARL_AGE_TIME;
1339
1340 chip->init_globals(priv);
1341 chip->atu_flush(priv);
1342
1343 mutex_unlock(&priv->reg_mutex);
1344
1345 return chip->sw_hw_apply(dev);
1346 }
1347
1348 int
1349 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1350 const struct switch_attr *attr,
1351 struct switch_val *val)
1352 {
1353 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1354 unsigned int len;
1355 int ret;
1356
1357 if (!ar8xxx_has_mib_counters(priv))
1358 return -EOPNOTSUPP;
1359
1360 mutex_lock(&priv->mib_lock);
1361
1362 len = priv->dev.ports * priv->chip->num_mibs *
1363 sizeof(*priv->mib_stats);
1364 memset(priv->mib_stats, '\0', len);
1365 ret = ar8xxx_mib_flush(priv);
1366 if (ret)
1367 goto unlock;
1368
1369 ret = 0;
1370
1371 unlock:
1372 mutex_unlock(&priv->mib_lock);
1373 return ret;
1374 }
1375
1376 int
1377 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1378 const struct switch_attr *attr,
1379 struct switch_val *val)
1380 {
1381 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1382
1383 mutex_lock(&priv->reg_mutex);
1384 priv->mirror_rx = !!val->value.i;
1385 priv->chip->set_mirror_regs(priv);
1386 mutex_unlock(&priv->reg_mutex);
1387
1388 return 0;
1389 }
1390
1391 int
1392 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1393 const struct switch_attr *attr,
1394 struct switch_val *val)
1395 {
1396 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1397 val->value.i = priv->mirror_rx;
1398 return 0;
1399 }
1400
1401 int
1402 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1403 const struct switch_attr *attr,
1404 struct switch_val *val)
1405 {
1406 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1407
1408 mutex_lock(&priv->reg_mutex);
1409 priv->mirror_tx = !!val->value.i;
1410 priv->chip->set_mirror_regs(priv);
1411 mutex_unlock(&priv->reg_mutex);
1412
1413 return 0;
1414 }
1415
1416 int
1417 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1418 const struct switch_attr *attr,
1419 struct switch_val *val)
1420 {
1421 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1422 val->value.i = priv->mirror_tx;
1423 return 0;
1424 }
1425
1426 int
1427 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1428 const struct switch_attr *attr,
1429 struct switch_val *val)
1430 {
1431 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1432
1433 mutex_lock(&priv->reg_mutex);
1434 priv->monitor_port = val->value.i;
1435 priv->chip->set_mirror_regs(priv);
1436 mutex_unlock(&priv->reg_mutex);
1437
1438 return 0;
1439 }
1440
1441 int
1442 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1443 const struct switch_attr *attr,
1444 struct switch_val *val)
1445 {
1446 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1447 val->value.i = priv->monitor_port;
1448 return 0;
1449 }
1450
1451 int
1452 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1453 const struct switch_attr *attr,
1454 struct switch_val *val)
1455 {
1456 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1457
1458 mutex_lock(&priv->reg_mutex);
1459 priv->source_port = val->value.i;
1460 priv->chip->set_mirror_regs(priv);
1461 mutex_unlock(&priv->reg_mutex);
1462
1463 return 0;
1464 }
1465
1466 int
1467 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1468 const struct switch_attr *attr,
1469 struct switch_val *val)
1470 {
1471 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1472 val->value.i = priv->source_port;
1473 return 0;
1474 }
1475
1476 int
1477 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1478 const struct switch_attr *attr,
1479 struct switch_val *val)
1480 {
1481 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1482 int port;
1483 int ret;
1484
1485 if (!ar8xxx_has_mib_counters(priv))
1486 return -EOPNOTSUPP;
1487
1488 port = val->port_vlan;
1489 if (port >= dev->ports)
1490 return -EINVAL;
1491
1492 mutex_lock(&priv->mib_lock);
1493 ret = ar8xxx_mib_capture(priv);
1494 if (ret)
1495 goto unlock;
1496
1497 ar8xxx_mib_fetch_port_stat(priv, port, true);
1498
1499 ret = 0;
1500
1501 unlock:
1502 mutex_unlock(&priv->mib_lock);
1503 return ret;
1504 }
1505
1506 static void
1507 ar8xxx_byte_to_str(char *buf, int len, u64 byte)
1508 {
1509 unsigned long b;
1510 const char *unit;
1511
1512 if (byte >= 0x40000000) { /* 1 GiB */
1513 b = byte * 10 / 0x40000000;
1514 unit = "GiB";
1515 } else if (byte >= 0x100000) { /* 1 MiB */
1516 b = byte * 10 / 0x100000;
1517 unit = "MiB";
1518 } else if (byte >= 0x400) { /* 1 KiB */
1519 b = byte * 10 / 0x400;
1520 unit = "KiB";
1521 } else {
1522 b = byte;
1523 unit = "Byte";
1524 }
1525 if (strcmp(unit, "Byte"))
1526 snprintf(buf, len, "%lu.%lu %s", b / 10, b % 10, unit);
1527 else
1528 snprintf(buf, len, "%lu %s", b, unit);
1529 }
1530
1531 int
1532 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1533 const struct switch_attr *attr,
1534 struct switch_val *val)
1535 {
1536 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1537 const struct ar8xxx_chip *chip = priv->chip;
1538 u64 *mib_stats, mib_data;
1539 unsigned int port;
1540 int ret;
1541 char *buf = priv->buf;
1542 char buf1[64];
1543 const char *mib_name;
1544 int i, len = 0;
1545 bool mib_stats_empty = true;
1546
1547 if (!ar8xxx_has_mib_counters(priv))
1548 return -EOPNOTSUPP;
1549
1550 port = val->port_vlan;
1551 if (port >= dev->ports)
1552 return -EINVAL;
1553
1554 mutex_lock(&priv->mib_lock);
1555 ret = ar8xxx_mib_capture(priv);
1556 if (ret)
1557 goto unlock;
1558
1559 ar8xxx_mib_fetch_port_stat(priv, port, false);
1560
1561 len += snprintf(buf + len, sizeof(priv->buf) - len,
1562 "MIB counters\n");
1563
1564 mib_stats = &priv->mib_stats[port * chip->num_mibs];
1565 for (i = 0; i < chip->num_mibs; i++) {
1566 mib_name = chip->mib_decs[i].name;
1567 mib_data = mib_stats[i];
1568 len += snprintf(buf + len, sizeof(priv->buf) - len,
1569 "%-12s: %llu\n", mib_name, mib_data);
1570 if ((!strcmp(mib_name, "TxByte") ||
1571 !strcmp(mib_name, "RxGoodByte")) &&
1572 mib_data >= 1024) {
1573 ar8xxx_byte_to_str(buf1, sizeof(buf1), mib_data);
1574 --len; /* discard newline at the end of buf */
1575 len += snprintf(buf + len, sizeof(priv->buf) - len,
1576 " (%s)\n", buf1);
1577 }
1578 if (mib_stats_empty && mib_data)
1579 mib_stats_empty = false;
1580 }
1581
1582 if (mib_stats_empty)
1583 len = snprintf(buf, sizeof(priv->buf), "No MIB data");
1584
1585 val->value.s = buf;
1586 val->len = len;
1587
1588 ret = 0;
1589
1590 unlock:
1591 mutex_unlock(&priv->mib_lock);
1592 return ret;
1593 }
1594
1595 int
1596 ar8xxx_sw_set_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1597 struct switch_val *val)
1598 {
1599 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1600 int age_time = val->value.i;
1601 u32 age_time_val;
1602
1603 if (age_time < 0)
1604 return -EINVAL;
1605
1606 age_time_val = ar8xxx_age_time_val(age_time);
1607 if (age_time_val == 0 || age_time_val > 0xffff)
1608 return -EINVAL;
1609
1610 priv->arl_age_time = age_time;
1611 return 0;
1612 }
1613
1614 int
1615 ar8xxx_sw_get_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1616 struct switch_val *val)
1617 {
1618 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1619 val->value.i = priv->arl_age_time;
1620 return 0;
1621 }
1622
1623 int
1624 ar8xxx_sw_get_arl_table(struct switch_dev *dev,
1625 const struct switch_attr *attr,
1626 struct switch_val *val)
1627 {
1628 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1629 struct mii_bus *bus = priv->mii_bus;
1630 const struct ar8xxx_chip *chip = priv->chip;
1631 char *buf = priv->arl_buf;
1632 int i, j, k, len = 0;
1633 struct arl_entry *a, *a1;
1634 u32 status;
1635
1636 if (!chip->get_arl_entry)
1637 return -EOPNOTSUPP;
1638
1639 mutex_lock(&priv->reg_mutex);
1640 mutex_lock(&bus->mdio_lock);
1641
1642 chip->get_arl_entry(priv, NULL, NULL, AR8XXX_ARL_INITIALIZE);
1643
1644 for(i = 0; i < AR8XXX_NUM_ARL_RECORDS; ++i) {
1645 a = &priv->arl_table[i];
1646 duplicate:
1647 chip->get_arl_entry(priv, a, &status, AR8XXX_ARL_GET_NEXT);
1648
1649 if (!status)
1650 break;
1651
1652 /* avoid duplicates
1653 * ARL table can include multiple valid entries
1654 * per MAC, just with differing status codes
1655 */
1656 for (j = 0; j < i; ++j) {
1657 a1 = &priv->arl_table[j];
1658 if (!memcmp(a->mac, a1->mac, sizeof(a->mac))) {
1659 /* ignore ports already seen in former entry */
1660 a->portmap &= ~a1->portmap;
1661 if (!a->portmap)
1662 goto duplicate;
1663 }
1664 }
1665 }
1666
1667 mutex_unlock(&bus->mdio_lock);
1668
1669 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1670 "address resolution table\n");
1671
1672 if (i == AR8XXX_NUM_ARL_RECORDS)
1673 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1674 "Too many entries found, displaying the first %d only!\n",
1675 AR8XXX_NUM_ARL_RECORDS);
1676
1677 for (j = 0; j < priv->dev.ports; ++j) {
1678 for (k = 0; k < i; ++k) {
1679 a = &priv->arl_table[k];
1680 if (!(a->portmap & BIT(j)))
1681 continue;
1682 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1683 "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1684 j,
1685 a->mac[5], a->mac[4], a->mac[3],
1686 a->mac[2], a->mac[1], a->mac[0]);
1687 }
1688 }
1689
1690 val->value.s = buf;
1691 val->len = len;
1692
1693 mutex_unlock(&priv->reg_mutex);
1694
1695 return 0;
1696 }
1697
1698 int
1699 ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev,
1700 const struct switch_attr *attr,
1701 struct switch_val *val)
1702 {
1703 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1704 int ret;
1705
1706 mutex_lock(&priv->reg_mutex);
1707 ret = priv->chip->atu_flush(priv);
1708 mutex_unlock(&priv->reg_mutex);
1709
1710 return ret;
1711 }
1712
1713 int
1714 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,
1715 const struct switch_attr *attr,
1716 struct switch_val *val)
1717 {
1718 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1719 int port, ret;
1720
1721 port = val->port_vlan;
1722 if (port >= dev->ports)
1723 return -EINVAL;
1724
1725 mutex_lock(&priv->reg_mutex);
1726 ret = priv->chip->atu_flush_port(priv, port);
1727 mutex_unlock(&priv->reg_mutex);
1728
1729 return ret;
1730 }
1731
1732 static int
1733 ar8xxx_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr)
1734 {
1735 struct ar8xxx_priv *priv = bus->priv;
1736 return priv->chip->phy_read(priv, phy_addr, reg_addr);
1737 }
1738
1739 static int
1740 ar8xxx_phy_write(struct mii_bus *bus, int phy_addr, int reg_addr,
1741 u16 reg_val)
1742 {
1743 struct ar8xxx_priv *priv = bus->priv;
1744 return priv->chip->phy_write(priv, phy_addr, reg_addr, reg_val);
1745 }
1746
1747 static const struct switch_attr ar8xxx_sw_attr_globals[] = {
1748 {
1749 .type = SWITCH_TYPE_INT,
1750 .name = "enable_vlan",
1751 .description = "Enable VLAN mode",
1752 .set = ar8xxx_sw_set_vlan,
1753 .get = ar8xxx_sw_get_vlan,
1754 .max = 1
1755 },
1756 {
1757 .type = SWITCH_TYPE_NOVAL,
1758 .name = "reset_mibs",
1759 .description = "Reset all MIB counters",
1760 .set = ar8xxx_sw_set_reset_mibs,
1761 },
1762 {
1763 .type = SWITCH_TYPE_INT,
1764 .name = "enable_mirror_rx",
1765 .description = "Enable mirroring of RX packets",
1766 .set = ar8xxx_sw_set_mirror_rx_enable,
1767 .get = ar8xxx_sw_get_mirror_rx_enable,
1768 .max = 1
1769 },
1770 {
1771 .type = SWITCH_TYPE_INT,
1772 .name = "enable_mirror_tx",
1773 .description = "Enable mirroring of TX packets",
1774 .set = ar8xxx_sw_set_mirror_tx_enable,
1775 .get = ar8xxx_sw_get_mirror_tx_enable,
1776 .max = 1
1777 },
1778 {
1779 .type = SWITCH_TYPE_INT,
1780 .name = "mirror_monitor_port",
1781 .description = "Mirror monitor port",
1782 .set = ar8xxx_sw_set_mirror_monitor_port,
1783 .get = ar8xxx_sw_get_mirror_monitor_port,
1784 .max = AR8216_NUM_PORTS - 1
1785 },
1786 {
1787 .type = SWITCH_TYPE_INT,
1788 .name = "mirror_source_port",
1789 .description = "Mirror source port",
1790 .set = ar8xxx_sw_set_mirror_source_port,
1791 .get = ar8xxx_sw_get_mirror_source_port,
1792 .max = AR8216_NUM_PORTS - 1
1793 },
1794 {
1795 .type = SWITCH_TYPE_STRING,
1796 .name = "arl_table",
1797 .description = "Get ARL table",
1798 .set = NULL,
1799 .get = ar8xxx_sw_get_arl_table,
1800 },
1801 {
1802 .type = SWITCH_TYPE_NOVAL,
1803 .name = "flush_arl_table",
1804 .description = "Flush ARL table",
1805 .set = ar8xxx_sw_set_flush_arl_table,
1806 },
1807 };
1808
1809 const struct switch_attr ar8xxx_sw_attr_port[] = {
1810 {
1811 .type = SWITCH_TYPE_NOVAL,
1812 .name = "reset_mib",
1813 .description = "Reset single port MIB counters",
1814 .set = ar8xxx_sw_set_port_reset_mib,
1815 },
1816 {
1817 .type = SWITCH_TYPE_STRING,
1818 .name = "mib",
1819 .description = "Get port's MIB counters",
1820 .set = NULL,
1821 .get = ar8xxx_sw_get_port_mib,
1822 },
1823 {
1824 .type = SWITCH_TYPE_NOVAL,
1825 .name = "flush_arl_table",
1826 .description = "Flush port's ARL table entries",
1827 .set = ar8xxx_sw_set_flush_port_arl_table,
1828 },
1829 };
1830
1831 const struct switch_attr ar8xxx_sw_attr_vlan[1] = {
1832 {
1833 .type = SWITCH_TYPE_INT,
1834 .name = "vid",
1835 .description = "VLAN ID (0-4094)",
1836 .set = ar8xxx_sw_set_vid,
1837 .get = ar8xxx_sw_get_vid,
1838 .max = 4094,
1839 },
1840 };
1841
1842 static const struct switch_dev_ops ar8xxx_sw_ops = {
1843 .attr_global = {
1844 .attr = ar8xxx_sw_attr_globals,
1845 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
1846 },
1847 .attr_port = {
1848 .attr = ar8xxx_sw_attr_port,
1849 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
1850 },
1851 .attr_vlan = {
1852 .attr = ar8xxx_sw_attr_vlan,
1853 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1854 },
1855 .get_port_pvid = ar8xxx_sw_get_pvid,
1856 .set_port_pvid = ar8xxx_sw_set_pvid,
1857 .get_vlan_ports = ar8xxx_sw_get_ports,
1858 .set_vlan_ports = ar8xxx_sw_set_ports,
1859 .apply_config = ar8xxx_sw_hw_apply,
1860 .reset_switch = ar8xxx_sw_reset_switch,
1861 .get_port_link = ar8xxx_sw_get_port_link,
1862 /* The following op is disabled as it hogs the CPU and degrades performance.
1863 An implementation has been attempted in 4d8a66d but reading MIB data is slow
1864 on ar8xxx switches.
1865
1866 The high CPU load has been traced down to the ar8xxx_reg_wait() call in
1867 ar8xxx_mib_op(), which has to usleep_range() till the MIB busy flag set by
1868 the request to update the MIB counter is cleared. */
1869 #if 0
1870 .get_port_stats = ar8xxx_sw_get_port_stats,
1871 #endif
1872 };
1873
1874 static const struct ar8xxx_chip ar8216_chip = {
1875 .caps = AR8XXX_CAP_MIB_COUNTERS,
1876
1877 .reg_port_stats_start = 0x19000,
1878 .reg_port_stats_length = 0xa0,
1879 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1880
1881 .name = "Atheros AR8216",
1882 .ports = AR8216_NUM_PORTS,
1883 .vlans = AR8216_NUM_VLANS,
1884 .swops = &ar8xxx_sw_ops,
1885
1886 .hw_init = ar8216_hw_init,
1887 .init_globals = ar8216_init_globals,
1888 .init_port = ar8216_init_port,
1889 .setup_port = ar8216_setup_port,
1890 .read_port_status = ar8216_read_port_status,
1891 .atu_flush = ar8216_atu_flush,
1892 .atu_flush_port = ar8216_atu_flush_port,
1893 .vtu_flush = ar8216_vtu_flush,
1894 .vtu_load_vlan = ar8216_vtu_load_vlan,
1895 .set_mirror_regs = ar8216_set_mirror_regs,
1896 .get_arl_entry = ar8216_get_arl_entry,
1897 .sw_hw_apply = ar8xxx_sw_hw_apply,
1898
1899 .num_mibs = ARRAY_SIZE(ar8216_mibs),
1900 .mib_decs = ar8216_mibs,
1901 .mib_func = AR8216_REG_MIB_FUNC
1902 };
1903
1904 static const struct ar8xxx_chip ar8229_chip = {
1905 .caps = AR8XXX_CAP_MIB_COUNTERS,
1906
1907 .reg_port_stats_start = 0x20000,
1908 .reg_port_stats_length = 0x100,
1909 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1910
1911 .name = "Atheros AR8229",
1912 .ports = AR8216_NUM_PORTS,
1913 .vlans = AR8216_NUM_VLANS,
1914 .swops = &ar8xxx_sw_ops,
1915
1916 .hw_init = ar8229_hw_init,
1917 .init_globals = ar8229_init_globals,
1918 .init_port = ar8229_init_port,
1919 .phy_read = ar8216_phy_read,
1920 .phy_write = ar8216_phy_write,
1921 .setup_port = ar8236_setup_port,
1922 .read_port_status = ar8216_read_port_status,
1923 .atu_flush = ar8216_atu_flush,
1924 .atu_flush_port = ar8216_atu_flush_port,
1925 .vtu_flush = ar8216_vtu_flush,
1926 .vtu_load_vlan = ar8216_vtu_load_vlan,
1927 .set_mirror_regs = ar8216_set_mirror_regs,
1928 .get_arl_entry = ar8216_get_arl_entry,
1929 .sw_hw_apply = ar8xxx_sw_hw_apply,
1930
1931 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1932 .mib_decs = ar8236_mibs,
1933 .mib_func = AR8216_REG_MIB_FUNC
1934 };
1935
1936 static const struct ar8xxx_chip ar8236_chip = {
1937 .caps = AR8XXX_CAP_MIB_COUNTERS,
1938
1939 .reg_port_stats_start = 0x20000,
1940 .reg_port_stats_length = 0x100,
1941 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1942
1943 .name = "Atheros AR8236",
1944 .ports = AR8216_NUM_PORTS,
1945 .vlans = AR8216_NUM_VLANS,
1946 .swops = &ar8xxx_sw_ops,
1947
1948 .hw_init = ar8216_hw_init,
1949 .init_globals = ar8236_init_globals,
1950 .init_port = ar8216_init_port,
1951 .setup_port = ar8236_setup_port,
1952 .read_port_status = ar8216_read_port_status,
1953 .atu_flush = ar8216_atu_flush,
1954 .atu_flush_port = ar8216_atu_flush_port,
1955 .vtu_flush = ar8216_vtu_flush,
1956 .vtu_load_vlan = ar8216_vtu_load_vlan,
1957 .set_mirror_regs = ar8216_set_mirror_regs,
1958 .get_arl_entry = ar8216_get_arl_entry,
1959 .sw_hw_apply = ar8xxx_sw_hw_apply,
1960
1961 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1962 .mib_decs = ar8236_mibs,
1963 .mib_func = AR8216_REG_MIB_FUNC
1964 };
1965
1966 static const struct ar8xxx_chip ar8316_chip = {
1967 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1968
1969 .reg_port_stats_start = 0x20000,
1970 .reg_port_stats_length = 0x100,
1971 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1972
1973 .name = "Atheros AR8316",
1974 .ports = AR8216_NUM_PORTS,
1975 .vlans = AR8X16_MAX_VLANS,
1976 .swops = &ar8xxx_sw_ops,
1977
1978 .hw_init = ar8316_hw_init,
1979 .init_globals = ar8316_init_globals,
1980 .init_port = ar8216_init_port,
1981 .setup_port = ar8216_setup_port,
1982 .read_port_status = ar8216_read_port_status,
1983 .atu_flush = ar8216_atu_flush,
1984 .atu_flush_port = ar8216_atu_flush_port,
1985 .vtu_flush = ar8216_vtu_flush,
1986 .vtu_load_vlan = ar8216_vtu_load_vlan,
1987 .set_mirror_regs = ar8216_set_mirror_regs,
1988 .get_arl_entry = ar8216_get_arl_entry,
1989 .sw_hw_apply = ar8xxx_sw_hw_apply,
1990
1991 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1992 .mib_decs = ar8236_mibs,
1993 .mib_func = AR8216_REG_MIB_FUNC
1994 };
1995
1996 static int
1997 ar8xxx_read_id(struct ar8xxx_priv *priv)
1998 {
1999 u32 val;
2000 u16 id;
2001 int i;
2002
2003 val = ar8xxx_read(priv, AR8216_REG_CTRL);
2004 if (val == ~0)
2005 return -ENODEV;
2006
2007 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2008 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2009 u16 t;
2010
2011 val = ar8xxx_read(priv, AR8216_REG_CTRL);
2012 if (val == ~0)
2013 return -ENODEV;
2014
2015 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2016 if (t != id)
2017 return -ENODEV;
2018 }
2019
2020 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2021 priv->chip_rev = (id & AR8216_CTRL_REVISION);
2022 return 0;
2023 }
2024
2025 static int
2026 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2027 {
2028 int ret;
2029
2030 ret = ar8xxx_read_id(priv);
2031 if(ret)
2032 return ret;
2033
2034 switch (priv->chip_ver) {
2035 case AR8XXX_VER_AR8216:
2036 priv->chip = &ar8216_chip;
2037 break;
2038 case AR8XXX_VER_AR8236:
2039 priv->chip = &ar8236_chip;
2040 break;
2041 case AR8XXX_VER_AR8316:
2042 priv->chip = &ar8316_chip;
2043 break;
2044 case AR8XXX_VER_AR8327:
2045 priv->chip = &ar8327_chip;
2046 break;
2047 case AR8XXX_VER_AR8337:
2048 priv->chip = &ar8337_chip;
2049 break;
2050 default:
2051 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2052 priv->chip_ver, priv->chip_rev);
2053
2054 return -ENODEV;
2055 }
2056
2057 return 0;
2058 }
2059
2060 static void
2061 ar8xxx_mib_work_func(struct work_struct *work)
2062 {
2063 struct ar8xxx_priv *priv;
2064 int err;
2065
2066 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2067
2068 mutex_lock(&priv->mib_lock);
2069
2070 err = ar8xxx_mib_capture(priv);
2071 if (err)
2072 goto next_port;
2073
2074 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2075
2076 next_port:
2077 priv->mib_next_port++;
2078 if (priv->mib_next_port >= priv->dev.ports)
2079 priv->mib_next_port = 0;
2080
2081 mutex_unlock(&priv->mib_lock);
2082 schedule_delayed_work(&priv->mib_work,
2083 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2084 }
2085
2086 static int
2087 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2088 {
2089 unsigned int len;
2090
2091 if (!ar8xxx_has_mib_counters(priv))
2092 return 0;
2093
2094 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2095
2096 len = priv->dev.ports * priv->chip->num_mibs *
2097 sizeof(*priv->mib_stats);
2098 priv->mib_stats = kzalloc(len, GFP_KERNEL);
2099
2100 if (!priv->mib_stats)
2101 return -ENOMEM;
2102
2103 return 0;
2104 }
2105
2106 static void
2107 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2108 {
2109 if (!ar8xxx_has_mib_counters(priv))
2110 return;
2111
2112 schedule_delayed_work(&priv->mib_work,
2113 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2114 }
2115
2116 static void
2117 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2118 {
2119 if (!ar8xxx_has_mib_counters(priv))
2120 return;
2121
2122 cancel_delayed_work_sync(&priv->mib_work);
2123 }
2124
2125 static struct ar8xxx_priv *
2126 ar8xxx_create(void)
2127 {
2128 struct ar8xxx_priv *priv;
2129
2130 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2131 if (priv == NULL)
2132 return NULL;
2133
2134 mutex_init(&priv->reg_mutex);
2135 mutex_init(&priv->mib_lock);
2136 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2137
2138 return priv;
2139 }
2140
2141 static void
2142 ar8xxx_free(struct ar8xxx_priv *priv)
2143 {
2144 if (priv->chip && priv->chip->cleanup)
2145 priv->chip->cleanup(priv);
2146
2147 kfree(priv->chip_data);
2148 kfree(priv->mib_stats);
2149 kfree(priv);
2150 }
2151
2152 static int
2153 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2154 {
2155 const struct ar8xxx_chip *chip;
2156 struct switch_dev *swdev;
2157 int ret;
2158
2159 chip = priv->chip;
2160
2161 swdev = &priv->dev;
2162 swdev->cpu_port = AR8216_PORT_CPU;
2163 swdev->name = chip->name;
2164 swdev->vlans = chip->vlans;
2165 swdev->ports = chip->ports;
2166 swdev->ops = chip->swops;
2167
2168 ret = ar8xxx_mib_init(priv);
2169 if (ret)
2170 return ret;
2171
2172 return 0;
2173 }
2174
2175 static int
2176 ar8xxx_start(struct ar8xxx_priv *priv)
2177 {
2178 int ret;
2179
2180 priv->init = true;
2181
2182 ret = priv->chip->hw_init(priv);
2183 if (ret)
2184 return ret;
2185
2186 ret = ar8xxx_sw_reset_switch(&priv->dev);
2187 if (ret)
2188 return ret;
2189
2190 priv->init = false;
2191
2192 ar8xxx_mib_start(priv);
2193
2194 return 0;
2195 }
2196
2197 static int
2198 ar8xxx_phy_config_init(struct phy_device *phydev)
2199 {
2200 struct ar8xxx_priv *priv = phydev->priv;
2201 struct net_device *dev = phydev->attached_dev;
2202 int ret;
2203
2204 if (WARN_ON(!priv))
2205 return -ENODEV;
2206
2207 if (priv->chip->config_at_probe)
2208 return ar8xxx_phy_check_aneg(phydev);
2209
2210 priv->phy = phydev;
2211
2212 if (phydev->mdio.addr != 0) {
2213 if (chip_is_ar8316(priv)) {
2214 /* switch device has been initialized, reinit */
2215 priv->dev.ports = (AR8216_NUM_PORTS - 1);
2216 priv->initialized = false;
2217 priv->port4_phy = true;
2218 ar8316_hw_init(priv);
2219 return 0;
2220 }
2221
2222 return 0;
2223 }
2224
2225 ret = ar8xxx_start(priv);
2226 if (ret)
2227 return ret;
2228
2229 /* VID fixup only needed on ar8216 */
2230 if (chip_is_ar8216(priv)) {
2231 dev->phy_ptr = priv;
2232 dev->priv_flags |= IFF_NO_IP_ALIGN;
2233 dev->eth_mangle_rx = ar8216_mangle_rx;
2234 dev->eth_mangle_tx = ar8216_mangle_tx;
2235 }
2236
2237 return 0;
2238 }
2239
2240 static bool
2241 ar8xxx_check_link_states(struct ar8xxx_priv *priv)
2242 {
2243 bool link_new, changed = false;
2244 u32 status;
2245 int i;
2246
2247 mutex_lock(&priv->reg_mutex);
2248
2249 for (i = 0; i < priv->dev.ports; i++) {
2250 status = priv->chip->read_port_status(priv, i);
2251 link_new = !!(status & AR8216_PORT_STATUS_LINK_UP);
2252 if (link_new == priv->link_up[i])
2253 continue;
2254
2255 priv->link_up[i] = link_new;
2256 changed = true;
2257 /* flush ARL entries for this port if it went down*/
2258 if (!link_new)
2259 priv->chip->atu_flush_port(priv, i);
2260 dev_info(&priv->phy->mdio.dev, "Port %d is %s\n",
2261 i, link_new ? "up" : "down");
2262 }
2263
2264 mutex_unlock(&priv->reg_mutex);
2265
2266 return changed;
2267 }
2268
2269 static int
2270 ar8xxx_phy_read_status(struct phy_device *phydev)
2271 {
2272 struct ar8xxx_priv *priv = phydev->priv;
2273 struct switch_port_link link;
2274
2275 /* check for switch port link changes */
2276 if (phydev->state == PHY_CHANGELINK)
2277 ar8xxx_check_link_states(priv);
2278
2279 if (phydev->mdio.addr != 0)
2280 return genphy_read_status(phydev);
2281
2282 ar8216_read_port_link(priv, phydev->mdio.addr, &link);
2283 phydev->link = !!link.link;
2284 if (!phydev->link)
2285 return 0;
2286
2287 switch (link.speed) {
2288 case SWITCH_PORT_SPEED_10:
2289 phydev->speed = SPEED_10;
2290 break;
2291 case SWITCH_PORT_SPEED_100:
2292 phydev->speed = SPEED_100;
2293 break;
2294 case SWITCH_PORT_SPEED_1000:
2295 phydev->speed = SPEED_1000;
2296 break;
2297 default:
2298 phydev->speed = 0;
2299 }
2300 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2301
2302 phydev->state = PHY_RUNNING;
2303 netif_carrier_on(phydev->attached_dev);
2304 if (phydev->adjust_link)
2305 phydev->adjust_link(phydev->attached_dev);
2306
2307 return 0;
2308 }
2309
2310 static int
2311 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2312 {
2313 if (phydev->mdio.addr == 0)
2314 return 0;
2315
2316 return genphy_config_aneg(phydev);
2317 }
2318
2319 static const u32 ar8xxx_phy_ids[] = {
2320 0x004dd033,
2321 0x004dd034, /* AR8327 */
2322 0x004dd036, /* AR8337 */
2323 0x004dd041,
2324 0x004dd042,
2325 0x004dd043, /* AR8236 */
2326 };
2327
2328 static bool
2329 ar8xxx_phy_match(u32 phy_id)
2330 {
2331 int i;
2332
2333 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2334 if (phy_id == ar8xxx_phy_ids[i])
2335 return true;
2336
2337 return false;
2338 }
2339
2340 static bool
2341 ar8xxx_is_possible(struct mii_bus *bus)
2342 {
2343 unsigned int i, found_phys = 0;
2344
2345 for (i = 0; i < 5; i++) {
2346 u32 phy_id;
2347
2348 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2349 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2350 if (ar8xxx_phy_match(phy_id)) {
2351 found_phys++;
2352 } else if (phy_id) {
2353 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2354 dev_name(&bus->dev), i, phy_id);
2355 }
2356 }
2357 return !!found_phys;
2358 }
2359
2360 static int
2361 ar8xxx_phy_probe(struct phy_device *phydev)
2362 {
2363 struct ar8xxx_priv *priv;
2364 struct switch_dev *swdev;
2365 int ret;
2366
2367 /* skip PHYs at unused adresses */
2368 if (phydev->mdio.addr != 0 && phydev->mdio.addr != 3 && phydev->mdio.addr != 4)
2369 return -ENODEV;
2370
2371 if (!ar8xxx_is_possible(phydev->mdio.bus))
2372 return -ENODEV;
2373
2374 mutex_lock(&ar8xxx_dev_list_lock);
2375 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2376 if (priv->mii_bus == phydev->mdio.bus)
2377 goto found;
2378
2379 priv = ar8xxx_create();
2380 if (priv == NULL) {
2381 ret = -ENOMEM;
2382 goto unlock;
2383 }
2384
2385 priv->mii_bus = phydev->mdio.bus;
2386 priv->pdev = &phydev->mdio.dev;
2387
2388 ret = ar8xxx_id_chip(priv);
2389 if (ret)
2390 goto free_priv;
2391
2392 ret = ar8xxx_probe_switch(priv);
2393 if (ret)
2394 goto free_priv;
2395
2396 swdev = &priv->dev;
2397 swdev->alias = dev_name(&priv->mii_bus->dev);
2398 ret = register_switch(swdev, NULL);
2399 if (ret)
2400 goto free_priv;
2401
2402 pr_info("%s: %s rev. %u switch registered on %s\n",
2403 swdev->devname, swdev->name, priv->chip_rev,
2404 dev_name(&priv->mii_bus->dev));
2405
2406 list_add(&priv->list, &ar8xxx_dev_list);
2407
2408 found:
2409 priv->use_count++;
2410
2411 if (phydev->mdio.addr == 0) {
2412 if (ar8xxx_has_gige(priv)) {
2413 phydev->supported = SUPPORTED_1000baseT_Full;
2414 phydev->advertising = ADVERTISED_1000baseT_Full;
2415 } else {
2416 phydev->supported = SUPPORTED_100baseT_Full;
2417 phydev->advertising = ADVERTISED_100baseT_Full;
2418 }
2419
2420 if (priv->chip->config_at_probe) {
2421 priv->phy = phydev;
2422
2423 ret = ar8xxx_start(priv);
2424 if (ret)
2425 goto err_unregister_switch;
2426 }
2427 } else {
2428 if (ar8xxx_has_gige(priv)) {
2429 phydev->supported |= SUPPORTED_1000baseT_Full;
2430 phydev->advertising |= ADVERTISED_1000baseT_Full;
2431 }
2432 if (priv->chip->phy_rgmii_set)
2433 priv->chip->phy_rgmii_set(priv, phydev);
2434 }
2435
2436 phydev->priv = priv;
2437
2438 mutex_unlock(&ar8xxx_dev_list_lock);
2439
2440 return 0;
2441
2442 err_unregister_switch:
2443 if (--priv->use_count)
2444 goto unlock;
2445
2446 unregister_switch(&priv->dev);
2447
2448 free_priv:
2449 ar8xxx_free(priv);
2450 unlock:
2451 mutex_unlock(&ar8xxx_dev_list_lock);
2452 return ret;
2453 }
2454
2455 static void
2456 ar8xxx_phy_detach(struct phy_device *phydev)
2457 {
2458 struct net_device *dev = phydev->attached_dev;
2459
2460 if (!dev)
2461 return;
2462
2463 dev->phy_ptr = NULL;
2464 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2465 dev->eth_mangle_rx = NULL;
2466 dev->eth_mangle_tx = NULL;
2467 }
2468
2469 static void
2470 ar8xxx_phy_remove(struct phy_device *phydev)
2471 {
2472 struct ar8xxx_priv *priv = phydev->priv;
2473
2474 if (WARN_ON(!priv))
2475 return;
2476
2477 phydev->priv = NULL;
2478
2479 mutex_lock(&ar8xxx_dev_list_lock);
2480
2481 if (--priv->use_count > 0) {
2482 mutex_unlock(&ar8xxx_dev_list_lock);
2483 return;
2484 }
2485
2486 list_del(&priv->list);
2487 mutex_unlock(&ar8xxx_dev_list_lock);
2488
2489 unregister_switch(&priv->dev);
2490 ar8xxx_mib_stop(priv);
2491 ar8xxx_free(priv);
2492 }
2493
2494 static int
2495 ar8xxx_phy_soft_reset(struct phy_device *phydev)
2496 {
2497 /* we don't need an extra reset */
2498 return 0;
2499 }
2500
2501 static struct phy_driver ar8xxx_phy_driver[] = {
2502 {
2503 .phy_id = 0x004d0000,
2504 .name = "Atheros AR8216/AR8236/AR8316",
2505 .phy_id_mask = 0xffff0000,
2506 .features = PHY_BASIC_FEATURES,
2507 .probe = ar8xxx_phy_probe,
2508 .remove = ar8xxx_phy_remove,
2509 .detach = ar8xxx_phy_detach,
2510 .config_init = ar8xxx_phy_config_init,
2511 .config_aneg = ar8xxx_phy_config_aneg,
2512 .read_status = ar8xxx_phy_read_status,
2513 .soft_reset = ar8xxx_phy_soft_reset,
2514 }
2515 };
2516
2517 static const struct of_device_id ar8xxx_mdiodev_of_match[] = {
2518 {
2519 .compatible = "qca,ar8229",
2520 .data = &ar8229_chip,
2521 }, {
2522 .compatible = "qca,ar8236",
2523 .data = &ar8236_chip,
2524 }, {
2525 .compatible = "qca,ar8327",
2526 .data = &ar8327_chip,
2527 },
2528 { /* sentinel */ },
2529 };
2530
2531 static int
2532 ar8xxx_mdiodev_probe(struct mdio_device *mdiodev)
2533 {
2534 const struct of_device_id *match;
2535 struct ar8xxx_priv *priv;
2536 struct switch_dev *swdev;
2537 struct device_node *mdio_node;
2538 int ret;
2539
2540 match = of_match_device(ar8xxx_mdiodev_of_match, &mdiodev->dev);
2541 if (!match)
2542 return -EINVAL;
2543
2544 priv = ar8xxx_create();
2545 if (priv == NULL)
2546 return -ENOMEM;
2547
2548 priv->mii_bus = mdiodev->bus;
2549 priv->pdev = &mdiodev->dev;
2550 priv->chip = (const struct ar8xxx_chip *) match->data;
2551
2552 ret = ar8xxx_read_id(priv);
2553 if (ret)
2554 goto free_priv;
2555
2556 ret = ar8xxx_probe_switch(priv);
2557 if (ret)
2558 goto free_priv;
2559
2560 if (priv->chip->phy_read && priv->chip->phy_write) {
2561 priv->sw_mii_bus = devm_mdiobus_alloc(&mdiodev->dev);
2562 priv->sw_mii_bus->name = "ar8xxx-mdio";
2563 priv->sw_mii_bus->read = ar8xxx_phy_read;
2564 priv->sw_mii_bus->write = ar8xxx_phy_write;
2565 priv->sw_mii_bus->priv = priv;
2566 priv->sw_mii_bus->parent = &mdiodev->dev;
2567 snprintf(priv->sw_mii_bus->id, MII_BUS_ID_SIZE, "%s",
2568 dev_name(&mdiodev->dev));
2569 mdio_node = of_get_child_by_name(priv->pdev->of_node, "mdio-bus");
2570 ret = of_mdiobus_register(priv->sw_mii_bus, mdio_node);
2571 if (ret)
2572 goto free_priv;
2573 }
2574
2575 swdev = &priv->dev;
2576 swdev->alias = dev_name(&mdiodev->dev);
2577
2578 if (of_property_read_bool(priv->pdev->of_node, "qca,phy4-mii-enable")) {
2579 priv->port4_phy = true;
2580 swdev->ports--;
2581 }
2582
2583 ret = register_switch(swdev, NULL);
2584 if (ret)
2585 goto free_priv;
2586
2587 pr_info("%s: %s rev. %u switch registered on %s\n",
2588 swdev->devname, swdev->name, priv->chip_rev,
2589 dev_name(&priv->mii_bus->dev));
2590
2591 mutex_lock(&ar8xxx_dev_list_lock);
2592 list_add(&priv->list, &ar8xxx_dev_list);
2593 mutex_unlock(&ar8xxx_dev_list_lock);
2594
2595 priv->use_count++;
2596
2597 ret = ar8xxx_start(priv);
2598 if (ret)
2599 goto err_unregister_switch;
2600
2601 dev_set_drvdata(&mdiodev->dev, priv);
2602
2603 return 0;
2604
2605 err_unregister_switch:
2606 if (--priv->use_count)
2607 return ret;
2608
2609 unregister_switch(&priv->dev);
2610
2611 free_priv:
2612 ar8xxx_free(priv);
2613 return ret;
2614 }
2615
2616 static void
2617 ar8xxx_mdiodev_remove(struct mdio_device *mdiodev)
2618 {
2619 struct ar8xxx_priv *priv = dev_get_drvdata(&mdiodev->dev);
2620
2621 if (WARN_ON(!priv))
2622 return;
2623
2624 mutex_lock(&ar8xxx_dev_list_lock);
2625
2626 if (--priv->use_count > 0) {
2627 mutex_unlock(&ar8xxx_dev_list_lock);
2628 return;
2629 }
2630
2631 list_del(&priv->list);
2632 mutex_unlock(&ar8xxx_dev_list_lock);
2633
2634 unregister_switch(&priv->dev);
2635 ar8xxx_mib_stop(priv);
2636 if(priv->sw_mii_bus)
2637 mdiobus_unregister(priv->sw_mii_bus);
2638 ar8xxx_free(priv);
2639 }
2640
2641 static struct mdio_driver ar8xxx_mdio_driver = {
2642 .probe = ar8xxx_mdiodev_probe,
2643 .remove = ar8xxx_mdiodev_remove,
2644 .mdiodrv.driver = {
2645 .name = "ar8xxx-switch",
2646 .of_match_table = ar8xxx_mdiodev_of_match,
2647 },
2648 };
2649
2650 static int __init ar8216_init(void)
2651 {
2652 int ret;
2653
2654 ret = phy_drivers_register(ar8xxx_phy_driver,
2655 ARRAY_SIZE(ar8xxx_phy_driver),
2656 THIS_MODULE);
2657 if (ret)
2658 return ret;
2659
2660 ret = mdio_driver_register(&ar8xxx_mdio_driver);
2661 if (ret)
2662 phy_drivers_unregister(ar8xxx_phy_driver,
2663 ARRAY_SIZE(ar8xxx_phy_driver));
2664
2665 return ret;
2666 }
2667 module_init(ar8216_init);
2668
2669 static void __exit ar8216_exit(void)
2670 {
2671 mdio_driver_unregister(&ar8xxx_mdio_driver);
2672 phy_drivers_unregister(ar8xxx_phy_driver,
2673 ARRAY_SIZE(ar8xxx_phy_driver));
2674 }
2675 module_exit(ar8216_exit);
2676
2677 MODULE_LICENSE("GPL");