ar8216: add ARL table flushing per port
[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / ar8216.h
1 /*
2 * ar8216.h: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #ifndef __AR8216_H
18 #define __AR8216_H
19
20 #define BITS(_s, _n) (((1UL << (_n)) - 1) << _s)
21
22 #define AR8XXX_CAP_GIGE BIT(0)
23 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
24
25 #define AR8XXX_NUM_PHYS 5
26 #define AR8216_PORT_CPU 0
27 #define AR8216_NUM_PORTS 6
28 #define AR8216_NUM_VLANS 16
29 #define AR8316_NUM_VLANS 4096
30
31 /* size of the vlan table */
32 #define AR8X16_MAX_VLANS 128
33 #define AR8X16_PROBE_RETRIES 10
34 #define AR8X16_MAX_PORTS 8
35
36 /* Atheros specific MII registers */
37 #define MII_ATH_MMD_ADDR 0x0d
38 #define MII_ATH_MMD_DATA 0x0e
39 #define MII_ATH_DBG_ADDR 0x1d
40 #define MII_ATH_DBG_DATA 0x1e
41
42 #define AR8216_REG_CTRL 0x0000
43 #define AR8216_CTRL_REVISION BITS(0, 8)
44 #define AR8216_CTRL_REVISION_S 0
45 #define AR8216_CTRL_VERSION BITS(8, 8)
46 #define AR8216_CTRL_VERSION_S 8
47 #define AR8216_CTRL_RESET BIT(31)
48
49 #define AR8216_REG_FLOOD_MASK 0x002C
50 #define AR8216_FM_UNI_DEST_PORTS BITS(0, 6)
51 #define AR8216_FM_MULTI_DEST_PORTS BITS(16, 6)
52 #define AR8236_FM_CPU_BROADCAST_EN BIT(26)
53 #define AR8236_FM_CPU_BCAST_FWD_EN BIT(25)
54
55 #define AR8216_REG_GLOBAL_CTRL 0x0030
56 #define AR8216_GCTRL_MTU BITS(0, 11)
57 #define AR8236_GCTRL_MTU BITS(0, 14)
58 #define AR8316_GCTRL_MTU BITS(0, 14)
59
60 #define AR8216_REG_VTU 0x0040
61 #define AR8216_VTU_OP BITS(0, 3)
62 #define AR8216_VTU_OP_NOOP 0x0
63 #define AR8216_VTU_OP_FLUSH 0x1
64 #define AR8216_VTU_OP_LOAD 0x2
65 #define AR8216_VTU_OP_PURGE 0x3
66 #define AR8216_VTU_OP_REMOVE_PORT 0x4
67 #define AR8216_VTU_ACTIVE BIT(3)
68 #define AR8216_VTU_FULL BIT(4)
69 #define AR8216_VTU_PORT BITS(8, 4)
70 #define AR8216_VTU_PORT_S 8
71 #define AR8216_VTU_VID BITS(16, 12)
72 #define AR8216_VTU_VID_S 16
73 #define AR8216_VTU_PRIO BITS(28, 3)
74 #define AR8216_VTU_PRIO_S 28
75 #define AR8216_VTU_PRIO_EN BIT(31)
76
77 #define AR8216_REG_VTU_DATA 0x0044
78 #define AR8216_VTUDATA_MEMBER BITS(0, 10)
79 #define AR8236_VTUDATA_MEMBER BITS(0, 7)
80 #define AR8216_VTUDATA_VALID BIT(11)
81
82 #define AR8216_REG_ATU_FUNC0 0x0050
83 #define AR8216_ATU_OP BITS(0, 3)
84 #define AR8216_ATU_OP_NOOP 0x0
85 #define AR8216_ATU_OP_FLUSH 0x1
86 #define AR8216_ATU_OP_LOAD 0x2
87 #define AR8216_ATU_OP_PURGE 0x3
88 #define AR8216_ATU_OP_FLUSH_UNLOCKED 0x4
89 #define AR8216_ATU_OP_FLUSH_PORT 0x5
90 #define AR8216_ATU_OP_GET_NEXT 0x6
91 #define AR8216_ATU_ACTIVE BIT(3)
92 #define AR8216_ATU_PORT_NUM BITS(8, 4)
93 #define AR8216_ATU_PORT_NUM_S 8
94 #define AR8216_ATU_FULL_VIO BIT(12)
95 #define AR8216_ATU_ADDR5 BITS(16, 8)
96 #define AR8216_ATU_ADDR5_S 16
97 #define AR8216_ATU_ADDR4 BITS(24, 8)
98 #define AR8216_ATU_ADDR4_S 24
99
100 #define AR8216_REG_ATU_FUNC1 0x0054
101 #define AR8216_ATU_ADDR3 BITS(0, 8)
102 #define AR8216_ATU_ADDR3_S 0
103 #define AR8216_ATU_ADDR2 BITS(8, 8)
104 #define AR8216_ATU_ADDR2_S 8
105 #define AR8216_ATU_ADDR1 BITS(16, 8)
106 #define AR8216_ATU_ADDR1_S 16
107 #define AR8216_ATU_ADDR0 BITS(24, 8)
108 #define AR8216_ATU_ADDR0_S 24
109
110 #define AR8216_REG_ATU_FUNC2 0x0058
111 #define AR8216_ATU_PORTS BITS(0, 6)
112 #define AR8216_ATU_PORT0 BIT(0)
113 #define AR8216_ATU_PORT1 BIT(1)
114 #define AR8216_ATU_PORT2 BIT(2)
115 #define AR8216_ATU_PORT3 BIT(3)
116 #define AR8216_ATU_PORT4 BIT(4)
117 #define AR8216_ATU_PORT5 BIT(5)
118 #define AR8216_ATU_STATUS BITS(16, 4)
119 #define AR8216_ATU_STATUS_S 16
120
121 #define AR8216_REG_ATU_CTRL 0x005C
122 #define AR8216_ATU_CTRL_AGE_EN BIT(17)
123 #define AR8216_ATU_CTRL_AGE_TIME BITS(0, 16)
124 #define AR8216_ATU_CTRL_AGE_TIME_S 0
125 #define AR8236_ATU_CTRL_RES BIT(20)
126
127 #define AR8216_REG_MIB_FUNC 0x0080
128 #define AR8216_MIB_TIMER BITS(0, 16)
129 #define AR8216_MIB_AT_HALF_EN BIT(16)
130 #define AR8216_MIB_BUSY BIT(17)
131 #define AR8216_MIB_FUNC BITS(24, 3)
132 #define AR8216_MIB_FUNC_S 24
133 #define AR8216_MIB_FUNC_NO_OP 0x0
134 #define AR8216_MIB_FUNC_FLUSH 0x1
135 #define AR8216_MIB_FUNC_CAPTURE 0x3
136 #define AR8236_MIB_EN BIT(30)
137
138 #define AR8216_REG_GLOBAL_CPUPORT 0x0078
139 #define AR8216_GLOBAL_CPUPORT_MIRROR_PORT BITS(4, 4)
140 #define AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S 4
141
142 #define AR8216_PORT_OFFSET(_i) (0x0100 * (_i + 1))
143 #define AR8216_REG_PORT_STATUS(_i) (AR8216_PORT_OFFSET(_i) + 0x0000)
144 #define AR8216_PORT_STATUS_SPEED BITS(0,2)
145 #define AR8216_PORT_STATUS_SPEED_S 0
146 #define AR8216_PORT_STATUS_TXMAC BIT(2)
147 #define AR8216_PORT_STATUS_RXMAC BIT(3)
148 #define AR8216_PORT_STATUS_TXFLOW BIT(4)
149 #define AR8216_PORT_STATUS_RXFLOW BIT(5)
150 #define AR8216_PORT_STATUS_DUPLEX BIT(6)
151 #define AR8216_PORT_STATUS_LINK_UP BIT(8)
152 #define AR8216_PORT_STATUS_LINK_AUTO BIT(9)
153 #define AR8216_PORT_STATUS_LINK_PAUSE BIT(10)
154
155 #define AR8216_REG_PORT_CTRL(_i) (AR8216_PORT_OFFSET(_i) + 0x0004)
156
157 /* port forwarding state */
158 #define AR8216_PORT_CTRL_STATE BITS(0, 3)
159 #define AR8216_PORT_CTRL_STATE_S 0
160
161 #define AR8216_PORT_CTRL_LEARN_LOCK BIT(7)
162
163 /* egress 802.1q mode */
164 #define AR8216_PORT_CTRL_VLAN_MODE BITS(8, 2)
165 #define AR8216_PORT_CTRL_VLAN_MODE_S 8
166
167 #define AR8216_PORT_CTRL_IGMP_SNOOP BIT(10)
168 #define AR8216_PORT_CTRL_HEADER BIT(11)
169 #define AR8216_PORT_CTRL_MAC_LOOP BIT(12)
170 #define AR8216_PORT_CTRL_SINGLE_VLAN BIT(13)
171 #define AR8216_PORT_CTRL_LEARN BIT(14)
172 #define AR8216_PORT_CTRL_MIRROR_TX BIT(16)
173 #define AR8216_PORT_CTRL_MIRROR_RX BIT(17)
174
175 #define AR8216_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET(_i) + 0x0008)
176
177 #define AR8216_PORT_VLAN_DEFAULT_ID BITS(0, 12)
178 #define AR8216_PORT_VLAN_DEFAULT_ID_S 0
179
180 #define AR8216_PORT_VLAN_DEST_PORTS BITS(16, 9)
181 #define AR8216_PORT_VLAN_DEST_PORTS_S 16
182
183 /* bit0 added to the priority field of egress frames */
184 #define AR8216_PORT_VLAN_TX_PRIO BIT(27)
185
186 /* port default priority */
187 #define AR8216_PORT_VLAN_PRIORITY BITS(28, 2)
188 #define AR8216_PORT_VLAN_PRIORITY_S 28
189
190 /* ingress 802.1q mode */
191 #define AR8216_PORT_VLAN_MODE BITS(30, 2)
192 #define AR8216_PORT_VLAN_MODE_S 30
193
194 #define AR8216_REG_PORT_RATE(_i) (AR8216_PORT_OFFSET(_i) + 0x000c)
195 #define AR8216_REG_PORT_PRIO(_i) (AR8216_PORT_OFFSET(_i) + 0x0010)
196
197 #define AR8216_STATS_RXBROAD 0x00
198 #define AR8216_STATS_RXPAUSE 0x04
199 #define AR8216_STATS_RXMULTI 0x08
200 #define AR8216_STATS_RXFCSERR 0x0c
201 #define AR8216_STATS_RXALIGNERR 0x10
202 #define AR8216_STATS_RXRUNT 0x14
203 #define AR8216_STATS_RXFRAGMENT 0x18
204 #define AR8216_STATS_RX64BYTE 0x1c
205 #define AR8216_STATS_RX128BYTE 0x20
206 #define AR8216_STATS_RX256BYTE 0x24
207 #define AR8216_STATS_RX512BYTE 0x28
208 #define AR8216_STATS_RX1024BYTE 0x2c
209 #define AR8216_STATS_RXMAXBYTE 0x30
210 #define AR8216_STATS_RXTOOLONG 0x34
211 #define AR8216_STATS_RXGOODBYTE 0x38
212 #define AR8216_STATS_RXBADBYTE 0x40
213 #define AR8216_STATS_RXOVERFLOW 0x48
214 #define AR8216_STATS_FILTERED 0x4c
215 #define AR8216_STATS_TXBROAD 0x50
216 #define AR8216_STATS_TXPAUSE 0x54
217 #define AR8216_STATS_TXMULTI 0x58
218 #define AR8216_STATS_TXUNDERRUN 0x5c
219 #define AR8216_STATS_TX64BYTE 0x60
220 #define AR8216_STATS_TX128BYTE 0x64
221 #define AR8216_STATS_TX256BYTE 0x68
222 #define AR8216_STATS_TX512BYTE 0x6c
223 #define AR8216_STATS_TX1024BYTE 0x70
224 #define AR8216_STATS_TXMAXBYTE 0x74
225 #define AR8216_STATS_TXOVERSIZE 0x78
226 #define AR8216_STATS_TXBYTE 0x7c
227 #define AR8216_STATS_TXCOLLISION 0x84
228 #define AR8216_STATS_TXABORTCOL 0x88
229 #define AR8216_STATS_TXMULTICOL 0x8c
230 #define AR8216_STATS_TXSINGLECOL 0x90
231 #define AR8216_STATS_TXEXCDEFER 0x94
232 #define AR8216_STATS_TXDEFER 0x98
233 #define AR8216_STATS_TXLATECOL 0x9c
234
235 #define AR8236_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET((_i)) + 0x0008)
236 #define AR8236_PORT_VLAN_DEFAULT_ID BITS(16, 12)
237 #define AR8236_PORT_VLAN_DEFAULT_ID_S 16
238 #define AR8236_PORT_VLAN_PRIORITY BITS(29, 3)
239 #define AR8236_PORT_VLAN_PRIORITY_S 28
240
241 #define AR8236_REG_PORT_VLAN2(_i) (AR8216_PORT_OFFSET((_i)) + 0x000c)
242 #define AR8236_PORT_VLAN2_MEMBER BITS(16, 7)
243 #define AR8236_PORT_VLAN2_MEMBER_S 16
244 #define AR8236_PORT_VLAN2_TX_PRIO BIT(23)
245 #define AR8236_PORT_VLAN2_VLAN_MODE BITS(30, 2)
246 #define AR8236_PORT_VLAN2_VLAN_MODE_S 30
247
248 #define AR8236_STATS_RXBROAD 0x00
249 #define AR8236_STATS_RXPAUSE 0x04
250 #define AR8236_STATS_RXMULTI 0x08
251 #define AR8236_STATS_RXFCSERR 0x0c
252 #define AR8236_STATS_RXALIGNERR 0x10
253 #define AR8236_STATS_RXRUNT 0x14
254 #define AR8236_STATS_RXFRAGMENT 0x18
255 #define AR8236_STATS_RX64BYTE 0x1c
256 #define AR8236_STATS_RX128BYTE 0x20
257 #define AR8236_STATS_RX256BYTE 0x24
258 #define AR8236_STATS_RX512BYTE 0x28
259 #define AR8236_STATS_RX1024BYTE 0x2c
260 #define AR8236_STATS_RX1518BYTE 0x30
261 #define AR8236_STATS_RXMAXBYTE 0x34
262 #define AR8236_STATS_RXTOOLONG 0x38
263 #define AR8236_STATS_RXGOODBYTE 0x3c
264 #define AR8236_STATS_RXBADBYTE 0x44
265 #define AR8236_STATS_RXOVERFLOW 0x4c
266 #define AR8236_STATS_FILTERED 0x50
267 #define AR8236_STATS_TXBROAD 0x54
268 #define AR8236_STATS_TXPAUSE 0x58
269 #define AR8236_STATS_TXMULTI 0x5c
270 #define AR8236_STATS_TXUNDERRUN 0x60
271 #define AR8236_STATS_TX64BYTE 0x64
272 #define AR8236_STATS_TX128BYTE 0x68
273 #define AR8236_STATS_TX256BYTE 0x6c
274 #define AR8236_STATS_TX512BYTE 0x70
275 #define AR8236_STATS_TX1024BYTE 0x74
276 #define AR8236_STATS_TX1518BYTE 0x78
277 #define AR8236_STATS_TXMAXBYTE 0x7c
278 #define AR8236_STATS_TXOVERSIZE 0x80
279 #define AR8236_STATS_TXBYTE 0x84
280 #define AR8236_STATS_TXCOLLISION 0x8c
281 #define AR8236_STATS_TXABORTCOL 0x90
282 #define AR8236_STATS_TXMULTICOL 0x94
283 #define AR8236_STATS_TXSINGLECOL 0x98
284 #define AR8236_STATS_TXEXCDEFER 0x9c
285 #define AR8236_STATS_TXDEFER 0xa0
286 #define AR8236_STATS_TXLATECOL 0xa4
287
288 #define AR8316_REG_POSTRIP 0x0008
289 #define AR8316_POSTRIP_MAC0_GMII_EN BIT(0)
290 #define AR8316_POSTRIP_MAC0_RGMII_EN BIT(1)
291 #define AR8316_POSTRIP_PHY4_GMII_EN BIT(2)
292 #define AR8316_POSTRIP_PHY4_RGMII_EN BIT(3)
293 #define AR8316_POSTRIP_MAC0_MAC_MODE BIT(4)
294 #define AR8316_POSTRIP_RTL_MODE BIT(5)
295 #define AR8316_POSTRIP_RGMII_RXCLK_DELAY_EN BIT(6)
296 #define AR8316_POSTRIP_RGMII_TXCLK_DELAY_EN BIT(7)
297 #define AR8316_POSTRIP_SERDES_EN BIT(8)
298 #define AR8316_POSTRIP_SEL_ANA_RST BIT(9)
299 #define AR8316_POSTRIP_GATE_25M_EN BIT(10)
300 #define AR8316_POSTRIP_SEL_CLK25M BIT(11)
301 #define AR8316_POSTRIP_HIB_PULSE_HW BIT(12)
302 #define AR8316_POSTRIP_DBG_MODE_I BIT(13)
303 #define AR8316_POSTRIP_MAC5_MAC_MODE BIT(14)
304 #define AR8316_POSTRIP_MAC5_PHY_MODE BIT(15)
305 #define AR8316_POSTRIP_POWER_DOWN_HW BIT(16)
306 #define AR8316_POSTRIP_LPW_STATE_EN BIT(17)
307 #define AR8316_POSTRIP_MAN_EN BIT(18)
308 #define AR8316_POSTRIP_PHY_PLL_ON BIT(19)
309 #define AR8316_POSTRIP_LPW_EXIT BIT(20)
310 #define AR8316_POSTRIP_TXDELAY_S0 BIT(21)
311 #define AR8316_POSTRIP_TXDELAY_S1 BIT(22)
312 #define AR8316_POSTRIP_RXDELAY_S0 BIT(23)
313 #define AR8316_POSTRIP_LED_OPEN_EN BIT(24)
314 #define AR8316_POSTRIP_SPI_EN BIT(25)
315 #define AR8316_POSTRIP_RXDELAY_S1 BIT(26)
316 #define AR8316_POSTRIP_POWER_ON_SEL BIT(31)
317
318 /* port speed */
319 enum {
320 AR8216_PORT_SPEED_10M = 0,
321 AR8216_PORT_SPEED_100M = 1,
322 AR8216_PORT_SPEED_1000M = 2,
323 AR8216_PORT_SPEED_ERR = 3,
324 };
325
326 /* ingress 802.1q mode */
327 enum {
328 AR8216_IN_PORT_ONLY = 0,
329 AR8216_IN_PORT_FALLBACK = 1,
330 AR8216_IN_VLAN_ONLY = 2,
331 AR8216_IN_SECURE = 3
332 };
333
334 /* egress 802.1q mode */
335 enum {
336 AR8216_OUT_KEEP = 0,
337 AR8216_OUT_STRIP_VLAN = 1,
338 AR8216_OUT_ADD_VLAN = 2
339 };
340
341 /* port forwarding state */
342 enum {
343 AR8216_PORT_STATE_DISABLED = 0,
344 AR8216_PORT_STATE_BLOCK = 1,
345 AR8216_PORT_STATE_LISTEN = 2,
346 AR8216_PORT_STATE_LEARN = 3,
347 AR8216_PORT_STATE_FORWARD = 4
348 };
349
350 enum {
351 AR8XXX_VER_AR8216 = 0x01,
352 AR8XXX_VER_AR8236 = 0x03,
353 AR8XXX_VER_AR8316 = 0x10,
354 AR8XXX_VER_AR8327 = 0x12,
355 AR8XXX_VER_AR8337 = 0x13,
356 };
357
358 #define AR8XXX_NUM_ARL_RECORDS 100
359
360 enum arl_op {
361 AR8XXX_ARL_INITIALIZE,
362 AR8XXX_ARL_GET_NEXT
363 };
364
365 struct arl_entry {
366 u8 port;
367 u8 mac[6];
368 };
369
370 struct ar8xxx_priv;
371
372 struct ar8xxx_mib_desc {
373 unsigned int size;
374 unsigned int offset;
375 const char *name;
376 };
377
378 struct ar8xxx_chip {
379 unsigned long caps;
380 bool config_at_probe;
381 bool mii_lo_first;
382
383 /* parameters to calculate REG_PORT_STATS_BASE */
384 unsigned reg_port_stats_start;
385 unsigned reg_port_stats_length;
386
387 int (*hw_init)(struct ar8xxx_priv *priv);
388 void (*cleanup)(struct ar8xxx_priv *priv);
389
390 const char *name;
391 int vlans;
392 int ports;
393 const struct switch_dev_ops *swops;
394
395 void (*init_globals)(struct ar8xxx_priv *priv);
396 void (*init_port)(struct ar8xxx_priv *priv, int port);
397 void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
398 u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
399 u32 (*read_port_eee_status)(struct ar8xxx_priv *priv, int port);
400 int (*atu_flush)(struct ar8xxx_priv *priv);
401 int (*atu_flush_port)(struct ar8xxx_priv *priv, int port);
402 void (*vtu_flush)(struct ar8xxx_priv *priv);
403 void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
404 void (*phy_fixup)(struct ar8xxx_priv *priv, int phy);
405 void (*set_mirror_regs)(struct ar8xxx_priv *priv);
406 void (*get_arl_entry)(struct ar8xxx_priv *priv, struct arl_entry *a,
407 u32 *status, enum arl_op op);
408 int (*sw_hw_apply)(struct switch_dev *dev);
409
410 const struct ar8xxx_mib_desc *mib_decs;
411 unsigned num_mibs;
412 unsigned mib_func;
413 };
414
415 struct ar8xxx_priv {
416 struct switch_dev dev;
417 struct mii_bus *mii_bus;
418 struct phy_device *phy;
419
420 int (*get_port_link)(unsigned port);
421
422 const struct net_device_ops *ndo_old;
423 struct net_device_ops ndo;
424 struct mutex reg_mutex;
425 u8 chip_ver;
426 u8 chip_rev;
427 const struct ar8xxx_chip *chip;
428 void *chip_data;
429 bool initialized;
430 bool port4_phy;
431 char buf[2048];
432 struct arl_entry arl_table[AR8XXX_NUM_ARL_RECORDS];
433 char arl_buf[AR8XXX_NUM_ARL_RECORDS * 32 + 256];
434 bool link_up[AR8X16_MAX_PORTS];
435
436 bool init;
437
438 struct mutex mib_lock;
439 struct delayed_work mib_work;
440 int mib_next_port;
441 u64 *mib_stats;
442
443 struct list_head list;
444 unsigned int use_count;
445
446 /* all fields below are cleared on reset */
447 bool vlan;
448 u16 vlan_id[AR8X16_MAX_VLANS];
449 u8 vlan_table[AR8X16_MAX_VLANS];
450 u8 vlan_tagged;
451 u16 pvid[AR8X16_MAX_PORTS];
452
453 /* mirroring */
454 bool mirror_rx;
455 bool mirror_tx;
456 int source_port;
457 int monitor_port;
458 };
459
460 u32
461 ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum);
462 void
463 ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val);
464 u32
465 ar8xxx_read(struct ar8xxx_priv *priv, int reg);
466 void
467 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val);
468 u32
469 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
470
471 void
472 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
473 u16 dbg_addr, u16 dbg_data);
474 void
475 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data);
476 u16
477 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr);
478 void
479 ar8xxx_phy_init(struct ar8xxx_priv *priv);
480 int
481 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
482 struct switch_val *val);
483 int
484 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
485 struct switch_val *val);
486 int
487 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
488 const struct switch_attr *attr,
489 struct switch_val *val);
490 int
491 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
492 const struct switch_attr *attr,
493 struct switch_val *val);
494 int
495 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
496 const struct switch_attr *attr,
497 struct switch_val *val);
498 int
499 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
500 const struct switch_attr *attr,
501 struct switch_val *val);
502 int
503 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
504 const struct switch_attr *attr,
505 struct switch_val *val);
506 int
507 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
508 const struct switch_attr *attr,
509 struct switch_val *val);
510 int
511 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
512 const struct switch_attr *attr,
513 struct switch_val *val);
514 int
515 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
516 const struct switch_attr *attr,
517 struct switch_val *val);
518 int
519 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
520 const struct switch_attr *attr,
521 struct switch_val *val);
522 int
523 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan);
524 int
525 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan);
526 int
527 ar8xxx_sw_hw_apply(struct switch_dev *dev);
528 int
529 ar8xxx_sw_reset_switch(struct switch_dev *dev);
530 int
531 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
532 struct switch_port_link *link);
533 int
534 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
535 const struct switch_attr *attr,
536 struct switch_val *val);
537 int
538 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
539 const struct switch_attr *attr,
540 struct switch_val *val);
541 int
542 ar8xxx_sw_get_arl_table(struct switch_dev *dev,
543 const struct switch_attr *attr,
544 struct switch_val *val);
545 int
546 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
547
548 static inline struct ar8xxx_priv *
549 swdev_to_ar8xxx(struct switch_dev *swdev)
550 {
551 return container_of(swdev, struct ar8xxx_priv, dev);
552 }
553
554 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
555 {
556 return priv->chip->caps & AR8XXX_CAP_GIGE;
557 }
558
559 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
560 {
561 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
562 }
563
564 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
565 {
566 return priv->chip_ver == AR8XXX_VER_AR8216;
567 }
568
569 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
570 {
571 return priv->chip_ver == AR8XXX_VER_AR8236;
572 }
573
574 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
575 {
576 return priv->chip_ver == AR8XXX_VER_AR8316;
577 }
578
579 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
580 {
581 return priv->chip_ver == AR8XXX_VER_AR8327;
582 }
583
584 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
585 {
586 return priv->chip_ver == AR8XXX_VER_AR8337;
587 }
588
589 static inline void
590 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
591 {
592 ar8xxx_rmw(priv, reg, 0, val);
593 }
594
595 static inline void
596 ar8xxx_reg_clear(struct ar8xxx_priv *priv, int reg, u32 val)
597 {
598 ar8xxx_rmw(priv, reg, val, 0);
599 }
600
601 static inline void
602 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
603 {
604 regaddr >>= 1;
605 *r1 = regaddr & 0x1e;
606
607 regaddr >>= 5;
608 *r2 = regaddr & 0x7;
609
610 regaddr >>= 3;
611 *page = regaddr & 0x1ff;
612 }
613
614 static inline void
615 wait_for_page_switch(void)
616 {
617 udelay(5);
618 }
619
620 #endif