projects / openwrt / openwrt.git / blob
? search:


d9508b9ff83c4c3d75978ae86546705660661a7f
[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / ar8216.h
1 /*
2 * ar8216.h: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #ifndef __AR8216_H
18 #define __AR8216_H
19
20 #define BITS(_s, _n) (((1UL << (_n)) - 1) << _s)
21
22 #define AR8XXX_CAP_GIGE BIT(0)
23 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
24
25 #define AR8XXX_NUM_PHYS 5
26 #define AR8216_PORT_CPU 0
27 #define AR8216_NUM_PORTS 6
28 #define AR8216_NUM_VLANS 16
29 #define AR8316_NUM_VLANS 4096
30
31 /* size of the vlan table */
32 #define AR8X16_MAX_VLANS 128
33 #define AR8X16_PROBE_RETRIES 10
34 #define AR8X16_MAX_PORTS 8
35
36 #define AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS 7
37 #define AR8XXX_DEFAULT_ARL_AGE_TIME 300
38
39 /* Atheros specific MII registers */
40 #define MII_ATH_MMD_ADDR 0x0d
41 #define MII_ATH_MMD_DATA 0x0e
42 #define MII_ATH_DBG_ADDR 0x1d
43 #define MII_ATH_DBG_DATA 0x1e
44
45 #define AR8216_REG_CTRL 0x0000
46 #define AR8216_CTRL_REVISION BITS(0, 8)
47 #define AR8216_CTRL_REVISION_S 0
48 #define AR8216_CTRL_VERSION BITS(8, 8)
49 #define AR8216_CTRL_VERSION_S 8
50 #define AR8216_CTRL_RESET BIT(31)
51
52 #define AR8216_REG_FLOOD_MASK 0x002C
53 #define AR8216_FM_UNI_DEST_PORTS BITS(0, 6)
54 #define AR8216_FM_MULTI_DEST_PORTS BITS(16, 6)
55 #define AR8236_FM_CPU_BROADCAST_EN BIT(26)
56 #define AR8236_FM_CPU_BCAST_FWD_EN BIT(25)
57
58 #define AR8216_REG_GLOBAL_CTRL 0x0030
59 #define AR8216_GCTRL_MTU BITS(0, 11)
60 #define AR8236_GCTRL_MTU BITS(0, 14)
61 #define AR8316_GCTRL_MTU BITS(0, 14)
62
63 #define AR8216_REG_VTU 0x0040
64 #define AR8216_VTU_OP BITS(0, 3)
65 #define AR8216_VTU_OP_NOOP 0x0
66 #define AR8216_VTU_OP_FLUSH 0x1
67 #define AR8216_VTU_OP_LOAD 0x2
68 #define AR8216_VTU_OP_PURGE 0x3
69 #define AR8216_VTU_OP_REMOVE_PORT 0x4
70 #define AR8216_VTU_ACTIVE BIT(3)
71 #define AR8216_VTU_FULL BIT(4)
72 #define AR8216_VTU_PORT BITS(8, 4)
73 #define AR8216_VTU_PORT_S 8
74 #define AR8216_VTU_VID BITS(16, 12)
75 #define AR8216_VTU_VID_S 16
76 #define AR8216_VTU_PRIO BITS(28, 3)
77 #define AR8216_VTU_PRIO_S 28
78 #define AR8216_VTU_PRIO_EN BIT(31)
79
80 #define AR8216_REG_VTU_DATA 0x0044
81 #define AR8216_VTUDATA_MEMBER BITS(0, 10)
82 #define AR8236_VTUDATA_MEMBER BITS(0, 7)
83 #define AR8216_VTUDATA_VALID BIT(11)
84
85 #define AR8216_REG_ATU_FUNC0 0x0050
86 #define AR8216_ATU_OP BITS(0, 3)
87 #define AR8216_ATU_OP_NOOP 0x0
88 #define AR8216_ATU_OP_FLUSH 0x1
89 #define AR8216_ATU_OP_LOAD 0x2
90 #define AR8216_ATU_OP_PURGE 0x3
91 #define AR8216_ATU_OP_FLUSH_UNLOCKED 0x4
92 #define AR8216_ATU_OP_FLUSH_PORT 0x5
93 #define AR8216_ATU_OP_GET_NEXT 0x6
94 #define AR8216_ATU_ACTIVE BIT(3)
95 #define AR8216_ATU_PORT_NUM BITS(8, 4)
96 #define AR8216_ATU_PORT_NUM_S 8
97 #define AR8216_ATU_FULL_VIO BIT(12)
98 #define AR8216_ATU_ADDR5 BITS(16, 8)
99 #define AR8216_ATU_ADDR5_S 16
100 #define AR8216_ATU_ADDR4 BITS(24, 8)
101 #define AR8216_ATU_ADDR4_S 24
102
103 #define AR8216_REG_ATU_FUNC1 0x0054
104 #define AR8216_ATU_ADDR3 BITS(0, 8)
105 #define AR8216_ATU_ADDR3_S 0
106 #define AR8216_ATU_ADDR2 BITS(8, 8)
107 #define AR8216_ATU_ADDR2_S 8
108 #define AR8216_ATU_ADDR1 BITS(16, 8)
109 #define AR8216_ATU_ADDR1_S 16
110 #define AR8216_ATU_ADDR0 BITS(24, 8)
111 #define AR8216_ATU_ADDR0_S 24
112
113 #define AR8216_REG_ATU_FUNC2 0x0058
114 #define AR8216_ATU_PORTS BITS(0, 6)
115 #define AR8216_ATU_PORT0 BIT(0)
116 #define AR8216_ATU_PORT1 BIT(1)
117 #define AR8216_ATU_PORT2 BIT(2)
118 #define AR8216_ATU_PORT3 BIT(3)
119 #define AR8216_ATU_PORT4 BIT(4)
120 #define AR8216_ATU_PORT5 BIT(5)
121 #define AR8216_ATU_STATUS BITS(16, 4)
122 #define AR8216_ATU_STATUS_S 16
123
124 #define AR8216_REG_ATU_CTRL 0x005C
125 #define AR8216_ATU_CTRL_AGE_EN BIT(17)
126 #define AR8216_ATU_CTRL_AGE_TIME BITS(0, 16)
127 #define AR8216_ATU_CTRL_AGE_TIME_S 0
128 #define AR8236_ATU_CTRL_RES BIT(20)
129
130 #define AR8216_REG_MIB_FUNC 0x0080
131 #define AR8216_MIB_TIMER BITS(0, 16)
132 #define AR8216_MIB_AT_HALF_EN BIT(16)
133 #define AR8216_MIB_BUSY BIT(17)
134 #define AR8216_MIB_FUNC BITS(24, 3)
135 #define AR8216_MIB_FUNC_S 24
136 #define AR8216_MIB_FUNC_NO_OP 0x0
137 #define AR8216_MIB_FUNC_FLUSH 0x1
138 #define AR8216_MIB_FUNC_CAPTURE 0x3
139 #define AR8236_MIB_EN BIT(30)
140
141 #define AR8216_REG_GLOBAL_CPUPORT 0x0078
142 #define AR8216_GLOBAL_CPUPORT_MIRROR_PORT BITS(4, 4)
143 #define AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S 4
144
145 #define AR8216_PORT_OFFSET(_i) (0x0100 * (_i + 1))
146 #define AR8216_REG_PORT_STATUS(_i) (AR8216_PORT_OFFSET(_i) + 0x0000)
147 #define AR8216_PORT_STATUS_SPEED BITS(0,2)
148 #define AR8216_PORT_STATUS_SPEED_S 0
149 #define AR8216_PORT_STATUS_TXMAC BIT(2)
150 #define AR8216_PORT_STATUS_RXMAC BIT(3)
151 #define AR8216_PORT_STATUS_TXFLOW BIT(4)
152 #define AR8216_PORT_STATUS_RXFLOW BIT(5)
153 #define AR8216_PORT_STATUS_DUPLEX BIT(6)
154 #define AR8216_PORT_STATUS_LINK_UP BIT(8)
155 #define AR8216_PORT_STATUS_LINK_AUTO BIT(9)
156 #define AR8216_PORT_STATUS_LINK_PAUSE BIT(10)
157 #define AR8216_PORT_STATUS_FLOW_CONTROL BIT(12)
158
159 #define AR8216_REG_PORT_CTRL(_i) (AR8216_PORT_OFFSET(_i) + 0x0004)
160
161 /* port forwarding state */
162 #define AR8216_PORT_CTRL_STATE BITS(0, 3)
163 #define AR8216_PORT_CTRL_STATE_S 0
164
165 #define AR8216_PORT_CTRL_LEARN_LOCK BIT(7)
166
167 /* egress 802.1q mode */
168 #define AR8216_PORT_CTRL_VLAN_MODE BITS(8, 2)
169 #define AR8216_PORT_CTRL_VLAN_MODE_S 8
170
171 #define AR8216_PORT_CTRL_IGMP_SNOOP BIT(10)
172 #define AR8216_PORT_CTRL_HEADER BIT(11)
173 #define AR8216_PORT_CTRL_MAC_LOOP BIT(12)
174 #define AR8216_PORT_CTRL_SINGLE_VLAN BIT(13)
175 #define AR8216_PORT_CTRL_LEARN BIT(14)
176 #define AR8216_PORT_CTRL_MIRROR_TX BIT(16)
177 #define AR8216_PORT_CTRL_MIRROR_RX BIT(17)
178
179 #define AR8216_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET(_i) + 0x0008)
180
181 #define AR8216_PORT_VLAN_DEFAULT_ID BITS(0, 12)
182 #define AR8216_PORT_VLAN_DEFAULT_ID_S 0
183
184 #define AR8216_PORT_VLAN_DEST_PORTS BITS(16, 9)
185 #define AR8216_PORT_VLAN_DEST_PORTS_S 16
186
187 /* bit0 added to the priority field of egress frames */
188 #define AR8216_PORT_VLAN_TX_PRIO BIT(27)
189
190 /* port default priority */
191 #define AR8216_PORT_VLAN_PRIORITY BITS(28, 2)
192 #define AR8216_PORT_VLAN_PRIORITY_S 28
193
194 /* ingress 802.1q mode */
195 #define AR8216_PORT_VLAN_MODE BITS(30, 2)
196 #define AR8216_PORT_VLAN_MODE_S 30
197
198 #define AR8216_REG_PORT_RATE(_i) (AR8216_PORT_OFFSET(_i) + 0x000c)
199 #define AR8216_REG_PORT_PRIO(_i) (AR8216_PORT_OFFSET(_i) + 0x0010)
200
201 #define AR8216_STATS_RXBROAD 0x00
202 #define AR8216_STATS_RXPAUSE 0x04
203 #define AR8216_STATS_RXMULTI 0x08
204 #define AR8216_STATS_RXFCSERR 0x0c
205 #define AR8216_STATS_RXALIGNERR 0x10
206 #define AR8216_STATS_RXRUNT 0x14
207 #define AR8216_STATS_RXFRAGMENT 0x18
208 #define AR8216_STATS_RX64BYTE 0x1c
209 #define AR8216_STATS_RX128BYTE 0x20
210 #define AR8216_STATS_RX256BYTE 0x24
211 #define AR8216_STATS_RX512BYTE 0x28
212 #define AR8216_STATS_RX1024BYTE 0x2c
213 #define AR8216_STATS_RXMAXBYTE 0x30
214 #define AR8216_STATS_RXTOOLONG 0x34
215 #define AR8216_STATS_RXGOODBYTE 0x38
216 #define AR8216_STATS_RXBADBYTE 0x40
217 #define AR8216_STATS_RXOVERFLOW 0x48
218 #define AR8216_STATS_FILTERED 0x4c
219 #define AR8216_STATS_TXBROAD 0x50
220 #define AR8216_STATS_TXPAUSE 0x54
221 #define AR8216_STATS_TXMULTI 0x58
222 #define AR8216_STATS_TXUNDERRUN 0x5c
223 #define AR8216_STATS_TX64BYTE 0x60
224 #define AR8216_STATS_TX128BYTE 0x64
225 #define AR8216_STATS_TX256BYTE 0x68
226 #define AR8216_STATS_TX512BYTE 0x6c
227 #define AR8216_STATS_TX1024BYTE 0x70
228 #define AR8216_STATS_TXMAXBYTE 0x74
229 #define AR8216_STATS_TXOVERSIZE 0x78
230 #define AR8216_STATS_TXBYTE 0x7c
231 #define AR8216_STATS_TXCOLLISION 0x84
232 #define AR8216_STATS_TXABORTCOL 0x88
233 #define AR8216_STATS_TXMULTICOL 0x8c
234 #define AR8216_STATS_TXSINGLECOL 0x90
235 #define AR8216_STATS_TXEXCDEFER 0x94
236 #define AR8216_STATS_TXDEFER 0x98
237 #define AR8216_STATS_TXLATECOL 0x9c
238
239 #define AR8236_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET((_i)) + 0x0008)
240 #define AR8236_PORT_VLAN_DEFAULT_ID BITS(16, 12)
241 #define AR8236_PORT_VLAN_DEFAULT_ID_S 16
242 #define AR8236_PORT_VLAN_PRIORITY BITS(29, 3)
243 #define AR8236_PORT_VLAN_PRIORITY_S 28
244
245 #define AR8236_REG_PORT_VLAN2(_i) (AR8216_PORT_OFFSET((_i)) + 0x000c)
246 #define AR8236_PORT_VLAN2_MEMBER BITS(16, 7)
247 #define AR8236_PORT_VLAN2_MEMBER_S 16
248 #define AR8236_PORT_VLAN2_TX_PRIO BIT(23)
249 #define AR8236_PORT_VLAN2_VLAN_MODE BITS(30, 2)
250 #define AR8236_PORT_VLAN2_VLAN_MODE_S 30
251
252 #define AR8236_STATS_RXBROAD 0x00
253 #define AR8236_STATS_RXPAUSE 0x04
254 #define AR8236_STATS_RXMULTI 0x08
255 #define AR8236_STATS_RXFCSERR 0x0c
256 #define AR8236_STATS_RXALIGNERR 0x10
257 #define AR8236_STATS_RXRUNT 0x14
258 #define AR8236_STATS_RXFRAGMENT 0x18
259 #define AR8236_STATS_RX64BYTE 0x1c
260 #define AR8236_STATS_RX128BYTE 0x20
261 #define AR8236_STATS_RX256BYTE 0x24
262 #define AR8236_STATS_RX512BYTE 0x28
263 #define AR8236_STATS_RX1024BYTE 0x2c
264 #define AR8236_STATS_RX1518BYTE 0x30
265 #define AR8236_STATS_RXMAXBYTE 0x34
266 #define AR8236_STATS_RXTOOLONG 0x38
267 #define AR8236_STATS_RXGOODBYTE 0x3c
268 #define AR8236_STATS_RXBADBYTE 0x44
269 #define AR8236_STATS_RXOVERFLOW 0x4c
270 #define AR8236_STATS_FILTERED 0x50
271 #define AR8236_STATS_TXBROAD 0x54
272 #define AR8236_STATS_TXPAUSE 0x58
273 #define AR8236_STATS_TXMULTI 0x5c
274 #define AR8236_STATS_TXUNDERRUN 0x60
275 #define AR8236_STATS_TX64BYTE 0x64
276 #define AR8236_STATS_TX128BYTE 0x68
277 #define AR8236_STATS_TX256BYTE 0x6c
278 #define AR8236_STATS_TX512BYTE 0x70
279 #define AR8236_STATS_TX1024BYTE 0x74
280 #define AR8236_STATS_TX1518BYTE 0x78
281 #define AR8236_STATS_TXMAXBYTE 0x7c
282 #define AR8236_STATS_TXOVERSIZE 0x80
283 #define AR8236_STATS_TXBYTE 0x84
284 #define AR8236_STATS_TXCOLLISION 0x8c
285 #define AR8236_STATS_TXABORTCOL 0x90
286 #define AR8236_STATS_TXMULTICOL 0x94
287 #define AR8236_STATS_TXSINGLECOL 0x98
288 #define AR8236_STATS_TXEXCDEFER 0x9c
289 #define AR8236_STATS_TXDEFER 0xa0
290 #define AR8236_STATS_TXLATECOL 0xa4
291
292 #define AR8316_REG_POSTRIP 0x0008
293 #define AR8316_POSTRIP_MAC0_GMII_EN BIT(0)
294 #define AR8316_POSTRIP_MAC0_RGMII_EN BIT(1)
295 #define AR8316_POSTRIP_PHY4_GMII_EN BIT(2)
296 #define AR8316_POSTRIP_PHY4_RGMII_EN BIT(3)
297 #define AR8316_POSTRIP_MAC0_MAC_MODE BIT(4)
298 #define AR8316_POSTRIP_RTL_MODE BIT(5)
299 #define AR8316_POSTRIP_RGMII_RXCLK_DELAY_EN BIT(6)
300 #define AR8316_POSTRIP_RGMII_TXCLK_DELAY_EN BIT(7)
301 #define AR8316_POSTRIP_SERDES_EN BIT(8)
302 #define AR8316_POSTRIP_SEL_ANA_RST BIT(9)
303 #define AR8316_POSTRIP_GATE_25M_EN BIT(10)
304 #define AR8316_POSTRIP_SEL_CLK25M BIT(11)
305 #define AR8316_POSTRIP_HIB_PULSE_HW BIT(12)
306 #define AR8316_POSTRIP_DBG_MODE_I BIT(13)
307 #define AR8316_POSTRIP_MAC5_MAC_MODE BIT(14)
308 #define AR8316_POSTRIP_MAC5_PHY_MODE BIT(15)
309 #define AR8316_POSTRIP_POWER_DOWN_HW BIT(16)
310 #define AR8316_POSTRIP_LPW_STATE_EN BIT(17)
311 #define AR8316_POSTRIP_MAN_EN BIT(18)
312 #define AR8316_POSTRIP_PHY_PLL_ON BIT(19)
313 #define AR8316_POSTRIP_LPW_EXIT BIT(20)
314 #define AR8316_POSTRIP_TXDELAY_S0 BIT(21)
315 #define AR8316_POSTRIP_TXDELAY_S1 BIT(22)
316 #define AR8316_POSTRIP_RXDELAY_S0 BIT(23)
317 #define AR8316_POSTRIP_LED_OPEN_EN BIT(24)
318 #define AR8316_POSTRIP_SPI_EN BIT(25)
319 #define AR8316_POSTRIP_RXDELAY_S1 BIT(26)
320 #define AR8316_POSTRIP_POWER_ON_SEL BIT(31)
321
322 /* port speed */
323 enum {
324 AR8216_PORT_SPEED_10M = 0,
325 AR8216_PORT_SPEED_100M = 1,
326 AR8216_PORT_SPEED_1000M = 2,
327 AR8216_PORT_SPEED_ERR = 3,
328 };
329
330 /* ingress 802.1q mode */
331 enum {
332 AR8216_IN_PORT_ONLY = 0,
333 AR8216_IN_PORT_FALLBACK = 1,
334 AR8216_IN_VLAN_ONLY = 2,
335 AR8216_IN_SECURE = 3
336 };
337
338 /* egress 802.1q mode */
339 enum {
340 AR8216_OUT_KEEP = 0,
341 AR8216_OUT_STRIP_VLAN = 1,
342 AR8216_OUT_ADD_VLAN = 2
343 };
344
345 /* port forwarding state */
346 enum {
347 AR8216_PORT_STATE_DISABLED = 0,
348 AR8216_PORT_STATE_BLOCK = 1,
349 AR8216_PORT_STATE_LISTEN = 2,
350 AR8216_PORT_STATE_LEARN = 3,
351 AR8216_PORT_STATE_FORWARD = 4
352 };
353
354 enum {
355 AR8XXX_VER_AR8216 = 0x01,
356 AR8XXX_VER_AR8236 = 0x03,
357 AR8XXX_VER_AR8316 = 0x10,
358 AR8XXX_VER_AR8327 = 0x12,
359 AR8XXX_VER_AR8337 = 0x13,
360 };
361
362 #define AR8XXX_NUM_ARL_RECORDS 100
363
364 enum arl_op {
365 AR8XXX_ARL_INITIALIZE,
366 AR8XXX_ARL_GET_NEXT
367 };
368
369 struct arl_entry {
370 u8 port;
371 u8 mac[6];
372 };
373
374 struct ar8xxx_priv;
375
376 struct ar8xxx_mib_desc {
377 unsigned int size;
378 unsigned int offset;
379 const char *name;
380 };
381
382 struct ar8xxx_chip {
383 unsigned long caps;
384 bool config_at_probe;
385 bool mii_lo_first;
386
387 /* parameters to calculate REG_PORT_STATS_BASE */
388 unsigned reg_port_stats_start;
389 unsigned reg_port_stats_length;
390
391 unsigned reg_arl_ctrl;
392
393 int (*hw_init)(struct ar8xxx_priv *priv);
394 void (*cleanup)(struct ar8xxx_priv *priv);
395
396 const char *name;
397 int vlans;
398 int ports;
399 const struct switch_dev_ops *swops;
400
401 void (*init_globals)(struct ar8xxx_priv *priv);
402 void (*init_port)(struct ar8xxx_priv *priv, int port);
403 void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
404 u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
405 u32 (*read_port_eee_status)(struct ar8xxx_priv *priv, int port);
406 int (*atu_flush)(struct ar8xxx_priv *priv);
407 int (*atu_flush_port)(struct ar8xxx_priv *priv, int port);
408 void (*vtu_flush)(struct ar8xxx_priv *priv);
409 void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
410 void (*phy_fixup)(struct ar8xxx_priv *priv, int phy);
411 void (*set_mirror_regs)(struct ar8xxx_priv *priv);
412 void (*get_arl_entry)(struct ar8xxx_priv *priv, struct arl_entry *a,
413 u32 *status, enum arl_op op);
414 int (*sw_hw_apply)(struct switch_dev *dev);
415
416 const struct ar8xxx_mib_desc *mib_decs;
417 unsigned num_mibs;
418 unsigned mib_func;
419 };
420
421 struct ar8xxx_priv {
422 struct switch_dev dev;
423 struct mii_bus *mii_bus;
424 struct phy_device *phy;
425
426 int (*get_port_link)(unsigned port);
427
428 const struct net_device_ops *ndo_old;
429 struct net_device_ops ndo;
430 struct mutex reg_mutex;
431 u8 chip_ver;
432 u8 chip_rev;
433 const struct ar8xxx_chip *chip;
434 void *chip_data;
435 bool initialized;
436 bool port4_phy;
437 char buf[2048];
438 struct arl_entry arl_table[AR8XXX_NUM_ARL_RECORDS];
439 char arl_buf[AR8XXX_NUM_ARL_RECORDS * 32 + 256];
440 bool link_up[AR8X16_MAX_PORTS];
441
442 bool init;
443
444 struct mutex mib_lock;
445 struct delayed_work mib_work;
446 int mib_next_port;
447 u64 *mib_stats;
448
449 struct list_head list;
450 unsigned int use_count;
451
452 /* all fields below are cleared on reset */
453 bool vlan;
454 u16 vlan_id[AR8X16_MAX_VLANS];
455 u8 vlan_table[AR8X16_MAX_VLANS];
456 u8 vlan_tagged;
457 u16 pvid[AR8X16_MAX_PORTS];
458 int arl_age_time;
459
460 /* mirroring */
461 bool mirror_rx;
462 bool mirror_tx;
463 int source_port;
464 int monitor_port;
465 };
466
467 u32
468 ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum);
469 void
470 ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val);
471 u32
472 ar8xxx_read(struct ar8xxx_priv *priv, int reg);
473 void
474 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val);
475 u32
476 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
477
478 void
479 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
480 u16 dbg_addr, u16 dbg_data);
481 void
482 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data);
483 u16
484 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg);
485 void
486 ar8xxx_phy_init(struct ar8xxx_priv *priv);
487 int
488 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
489 struct switch_val *val);
490 int
491 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
492 struct switch_val *val);
493 int
494 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
495 const struct switch_attr *attr,
496 struct switch_val *val);
497 int
498 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
499 const struct switch_attr *attr,
500 struct switch_val *val);
501 int
502 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
503 const struct switch_attr *attr,
504 struct switch_val *val);
505 int
506 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
507 const struct switch_attr *attr,
508 struct switch_val *val);
509 int
510 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
511 const struct switch_attr *attr,
512 struct switch_val *val);
513 int
514 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
515 const struct switch_attr *attr,
516 struct switch_val *val);
517 int
518 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
519 const struct switch_attr *attr,
520 struct switch_val *val);
521 int
522 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
523 const struct switch_attr *attr,
524 struct switch_val *val);
525 int
526 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
527 const struct switch_attr *attr,
528 struct switch_val *val);
529 int
530 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan);
531 int
532 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan);
533 int
534 ar8xxx_sw_hw_apply(struct switch_dev *dev);
535 int
536 ar8xxx_sw_reset_switch(struct switch_dev *dev);
537 int
538 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
539 struct switch_port_link *link);
540 int
541 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
542 const struct switch_attr *attr,
543 struct switch_val *val);
544 int
545 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
546 const struct switch_attr *attr,
547 struct switch_val *val);
548 int
549 ar8xxx_sw_get_arl_age_time(struct switch_dev *dev,
550 const struct switch_attr *attr,
551 struct switch_val *val);
552 int
553 ar8xxx_sw_set_arl_age_time(struct switch_dev *dev,
554 const struct switch_attr *attr,
555 struct switch_val *val);
556 int
557 ar8xxx_sw_get_arl_table(struct switch_dev *dev,
558 const struct switch_attr *attr,
559 struct switch_val *val);
560 int
561 ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev,
562 const struct switch_attr *attr,
563 struct switch_val *val);
564 int
565 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,
566 const struct switch_attr *attr,
567 struct switch_val *val);
568 int
569 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
570
571 static inline struct ar8xxx_priv *
572 swdev_to_ar8xxx(struct switch_dev *swdev)
573 {
574 return container_of(swdev, struct ar8xxx_priv, dev);
575 }
576
577 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
578 {
579 return priv->chip->caps & AR8XXX_CAP_GIGE;
580 }
581
582 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
583 {
584 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
585 }
586
587 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
588 {
589 return priv->chip_ver == AR8XXX_VER_AR8216;
590 }
591
592 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
593 {
594 return priv->chip_ver == AR8XXX_VER_AR8236;
595 }
596
597 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
598 {
599 return priv->chip_ver == AR8XXX_VER_AR8316;
600 }
601
602 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
603 {
604 return priv->chip_ver == AR8XXX_VER_AR8327;
605 }
606
607 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
608 {
609 return priv->chip_ver == AR8XXX_VER_AR8337;
610 }
611
612 static inline void
613 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
614 {
615 ar8xxx_rmw(priv, reg, 0, val);
616 }
617
618 static inline void
619 ar8xxx_reg_clear(struct ar8xxx_priv *priv, int reg, u32 val)
620 {
621 ar8xxx_rmw(priv, reg, val, 0);
622 }
623
624 static inline void
625 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
626 {
627 regaddr >>= 1;
628 *r1 = regaddr & 0x1e;
629
630 regaddr >>= 5;
631 *r2 = regaddr & 0x7;
632
633 regaddr >>= 3;
634 *page = regaddr & 0x1ff;
635 }
636
637 static inline void
638 wait_for_page_switch(void)
639 {
640 udelay(5);
641 }
642
643 #endif
OpenWrt Source Repository