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generic: ar8216: add support for separated mdio bus for phy access
[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / ar8216.h
1 /*
2 * ar8216.h: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #ifndef __AR8216_H
18 #define __AR8216_H
19
20 #define BITS(_s, _n) (((1UL << (_n)) - 1) << _s)
21
22 #define AR8XXX_CAP_GIGE BIT(0)
23 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
24
25 #define AR8XXX_NUM_PHYS 5
26 #define AR8216_PORT_CPU 0
27 #define AR8216_NUM_PORTS 6
28 #define AR8216_NUM_VLANS 16
29 #define AR8316_NUM_VLANS 4096
30
31 /* size of the vlan table */
32 #define AR8X16_MAX_VLANS 128
33 #define AR8X16_PROBE_RETRIES 10
34 #define AR8X16_MAX_PORTS 8
35
36 #define AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS 7
37 #define AR8XXX_DEFAULT_ARL_AGE_TIME 300
38
39 /* Atheros specific MII registers */
40 #define MII_ATH_MMD_ADDR 0x0d
41 #define MII_ATH_MMD_DATA 0x0e
42 #define MII_ATH_DBG_ADDR 0x1d
43 #define MII_ATH_DBG_DATA 0x1e
44
45 #define AR8216_REG_CTRL 0x0000
46 #define AR8216_CTRL_REVISION BITS(0, 8)
47 #define AR8216_CTRL_REVISION_S 0
48 #define AR8216_CTRL_VERSION BITS(8, 8)
49 #define AR8216_CTRL_VERSION_S 8
50 #define AR8216_CTRL_RESET BIT(31)
51
52 #define AR8216_REG_FLOOD_MASK 0x002C
53 #define AR8216_FM_UNI_DEST_PORTS BITS(0, 6)
54 #define AR8216_FM_MULTI_DEST_PORTS BITS(16, 6)
55 #define AR8229_FLOOD_MASK_MC_DP(_p) BIT(16 + (_p))
56 #define AR8229_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p))
57 #define AR8236_FM_CPU_BROADCAST_EN BIT(26)
58 #define AR8236_FM_CPU_BCAST_FWD_EN BIT(25)
59
60 #define AR8216_REG_GLOBAL_CTRL 0x0030
61 #define AR8216_GCTRL_MTU BITS(0, 11)
62 #define AR8236_GCTRL_MTU BITS(0, 14)
63 #define AR8316_GCTRL_MTU BITS(0, 14)
64
65 #define AR8216_REG_VTU 0x0040
66 #define AR8216_VTU_OP BITS(0, 3)
67 #define AR8216_VTU_OP_NOOP 0x0
68 #define AR8216_VTU_OP_FLUSH 0x1
69 #define AR8216_VTU_OP_LOAD 0x2
70 #define AR8216_VTU_OP_PURGE 0x3
71 #define AR8216_VTU_OP_REMOVE_PORT 0x4
72 #define AR8216_VTU_ACTIVE BIT(3)
73 #define AR8216_VTU_FULL BIT(4)
74 #define AR8216_VTU_PORT BITS(8, 4)
75 #define AR8216_VTU_PORT_S 8
76 #define AR8216_VTU_VID BITS(16, 12)
77 #define AR8216_VTU_VID_S 16
78 #define AR8216_VTU_PRIO BITS(28, 3)
79 #define AR8216_VTU_PRIO_S 28
80 #define AR8216_VTU_PRIO_EN BIT(31)
81
82 #define AR8216_REG_VTU_DATA 0x0044
83 #define AR8216_VTUDATA_MEMBER BITS(0, 10)
84 #define AR8236_VTUDATA_MEMBER BITS(0, 7)
85 #define AR8216_VTUDATA_VALID BIT(11)
86
87 #define AR8216_REG_ATU_FUNC0 0x0050
88 #define AR8216_ATU_OP BITS(0, 3)
89 #define AR8216_ATU_OP_NOOP 0x0
90 #define AR8216_ATU_OP_FLUSH 0x1
91 #define AR8216_ATU_OP_LOAD 0x2
92 #define AR8216_ATU_OP_PURGE 0x3
93 #define AR8216_ATU_OP_FLUSH_UNLOCKED 0x4
94 #define AR8216_ATU_OP_FLUSH_PORT 0x5
95 #define AR8216_ATU_OP_GET_NEXT 0x6
96 #define AR8216_ATU_ACTIVE BIT(3)
97 #define AR8216_ATU_PORT_NUM BITS(8, 4)
98 #define AR8216_ATU_PORT_NUM_S 8
99 #define AR8216_ATU_FULL_VIO BIT(12)
100 #define AR8216_ATU_ADDR5 BITS(16, 8)
101 #define AR8216_ATU_ADDR5_S 16
102 #define AR8216_ATU_ADDR4 BITS(24, 8)
103 #define AR8216_ATU_ADDR4_S 24
104
105 #define AR8216_REG_ATU_FUNC1 0x0054
106 #define AR8216_ATU_ADDR3 BITS(0, 8)
107 #define AR8216_ATU_ADDR3_S 0
108 #define AR8216_ATU_ADDR2 BITS(8, 8)
109 #define AR8216_ATU_ADDR2_S 8
110 #define AR8216_ATU_ADDR1 BITS(16, 8)
111 #define AR8216_ATU_ADDR1_S 16
112 #define AR8216_ATU_ADDR0 BITS(24, 8)
113 #define AR8216_ATU_ADDR0_S 24
114
115 #define AR8216_REG_ATU_FUNC2 0x0058
116 #define AR8216_ATU_PORTS BITS(0, 6)
117 #define AR8216_ATU_PORTS_S 0
118 #define AR8216_ATU_PORT0 BIT(0)
119 #define AR8216_ATU_PORT1 BIT(1)
120 #define AR8216_ATU_PORT2 BIT(2)
121 #define AR8216_ATU_PORT3 BIT(3)
122 #define AR8216_ATU_PORT4 BIT(4)
123 #define AR8216_ATU_PORT5 BIT(5)
124 #define AR8216_ATU_STATUS BITS(16, 4)
125 #define AR8216_ATU_STATUS_S 16
126
127 #define AR8216_REG_ATU_CTRL 0x005C
128 #define AR8216_ATU_CTRL_AGE_EN BIT(17)
129 #define AR8216_ATU_CTRL_AGE_TIME BITS(0, 16)
130 #define AR8216_ATU_CTRL_AGE_TIME_S 0
131 #define AR8236_ATU_CTRL_RES BIT(20)
132 #define AR8216_ATU_CTRL_LEARN_CHANGE BIT(18)
133
134 #define AR8216_REG_TAG_PRIORITY 0x0070
135
136 #define AR8216_REG_SERVICE_TAG 0x0074
137 #define AR8216_SERVICE_TAG_M BITS(0, 16)
138
139 #define AR8216_REG_MIB_FUNC 0x0080
140 #define AR8216_MIB_TIMER BITS(0, 16)
141 #define AR8216_MIB_AT_HALF_EN BIT(16)
142 #define AR8216_MIB_BUSY BIT(17)
143 #define AR8216_MIB_FUNC BITS(24, 3)
144 #define AR8216_MIB_FUNC_S 24
145 #define AR8216_MIB_FUNC_NO_OP 0x0
146 #define AR8216_MIB_FUNC_FLUSH 0x1
147 #define AR8216_MIB_FUNC_CAPTURE 0x3
148 #define AR8236_MIB_EN BIT(30)
149
150 #define AR8216_REG_GLOBAL_CPUPORT 0x0078
151 #define AR8216_GLOBAL_CPUPORT_MIRROR_PORT BITS(4, 4)
152 #define AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S 4
153 #define AR8216_GLOBAL_CPUPORT_EN BIT(8)
154
155 #define AR8216_PORT_OFFSET(_i) (0x0100 * (_i + 1))
156 #define AR8216_REG_PORT_STATUS(_i) (AR8216_PORT_OFFSET(_i) + 0x0000)
157 #define AR8216_PORT_STATUS_SPEED BITS(0,2)
158 #define AR8216_PORT_STATUS_SPEED_S 0
159 #define AR8216_PORT_STATUS_TXMAC BIT(2)
160 #define AR8216_PORT_STATUS_RXMAC BIT(3)
161 #define AR8216_PORT_STATUS_TXFLOW BIT(4)
162 #define AR8216_PORT_STATUS_RXFLOW BIT(5)
163 #define AR8216_PORT_STATUS_DUPLEX BIT(6)
164 #define AR8216_PORT_STATUS_LINK_UP BIT(8)
165 #define AR8216_PORT_STATUS_LINK_AUTO BIT(9)
166 #define AR8216_PORT_STATUS_LINK_PAUSE BIT(10)
167 #define AR8216_PORT_STATUS_FLOW_CONTROL BIT(12)
168
169 #define AR8216_REG_PORT_CTRL(_i) (AR8216_PORT_OFFSET(_i) + 0x0004)
170
171 /* port forwarding state */
172 #define AR8216_PORT_CTRL_STATE BITS(0, 3)
173 #define AR8216_PORT_CTRL_STATE_S 0
174
175 #define AR8216_PORT_CTRL_LEARN_LOCK BIT(7)
176
177 /* egress 802.1q mode */
178 #define AR8216_PORT_CTRL_VLAN_MODE BITS(8, 2)
179 #define AR8216_PORT_CTRL_VLAN_MODE_S 8
180
181 #define AR8216_PORT_CTRL_IGMP_SNOOP BIT(10)
182 #define AR8216_PORT_CTRL_HEADER BIT(11)
183 #define AR8216_PORT_CTRL_MAC_LOOP BIT(12)
184 #define AR8216_PORT_CTRL_SINGLE_VLAN BIT(13)
185 #define AR8216_PORT_CTRL_LEARN BIT(14)
186 #define AR8216_PORT_CTRL_MIRROR_TX BIT(16)
187 #define AR8216_PORT_CTRL_MIRROR_RX BIT(17)
188
189 #define AR8216_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET(_i) + 0x0008)
190
191 #define AR8216_PORT_VLAN_DEFAULT_ID BITS(0, 12)
192 #define AR8216_PORT_VLAN_DEFAULT_ID_S 0
193
194 #define AR8216_PORT_VLAN_DEST_PORTS BITS(16, 9)
195 #define AR8216_PORT_VLAN_DEST_PORTS_S 16
196
197 /* bit0 added to the priority field of egress frames */
198 #define AR8216_PORT_VLAN_TX_PRIO BIT(27)
199
200 /* port default priority */
201 #define AR8216_PORT_VLAN_PRIORITY BITS(28, 2)
202 #define AR8216_PORT_VLAN_PRIORITY_S 28
203
204 /* ingress 802.1q mode */
205 #define AR8216_PORT_VLAN_MODE BITS(30, 2)
206 #define AR8216_PORT_VLAN_MODE_S 30
207
208 #define AR8216_REG_PORT_RATE(_i) (AR8216_PORT_OFFSET(_i) + 0x000c)
209 #define AR8216_REG_PORT_PRIO(_i) (AR8216_PORT_OFFSET(_i) + 0x0010)
210
211 #define AR8216_STATS_RXBROAD 0x00
212 #define AR8216_STATS_RXPAUSE 0x04
213 #define AR8216_STATS_RXMULTI 0x08
214 #define AR8216_STATS_RXFCSERR 0x0c
215 #define AR8216_STATS_RXALIGNERR 0x10
216 #define AR8216_STATS_RXRUNT 0x14
217 #define AR8216_STATS_RXFRAGMENT 0x18
218 #define AR8216_STATS_RX64BYTE 0x1c
219 #define AR8216_STATS_RX128BYTE 0x20
220 #define AR8216_STATS_RX256BYTE 0x24
221 #define AR8216_STATS_RX512BYTE 0x28
222 #define AR8216_STATS_RX1024BYTE 0x2c
223 #define AR8216_STATS_RXMAXBYTE 0x30
224 #define AR8216_STATS_RXTOOLONG 0x34
225 #define AR8216_STATS_RXGOODBYTE 0x38
226 #define AR8216_STATS_RXBADBYTE 0x40
227 #define AR8216_STATS_RXOVERFLOW 0x48
228 #define AR8216_STATS_FILTERED 0x4c
229 #define AR8216_STATS_TXBROAD 0x50
230 #define AR8216_STATS_TXPAUSE 0x54
231 #define AR8216_STATS_TXMULTI 0x58
232 #define AR8216_STATS_TXUNDERRUN 0x5c
233 #define AR8216_STATS_TX64BYTE 0x60
234 #define AR8216_STATS_TX128BYTE 0x64
235 #define AR8216_STATS_TX256BYTE 0x68
236 #define AR8216_STATS_TX512BYTE 0x6c
237 #define AR8216_STATS_TX1024BYTE 0x70
238 #define AR8216_STATS_TXMAXBYTE 0x74
239 #define AR8216_STATS_TXOVERSIZE 0x78
240 #define AR8216_STATS_TXBYTE 0x7c
241 #define AR8216_STATS_TXCOLLISION 0x84
242 #define AR8216_STATS_TXABORTCOL 0x88
243 #define AR8216_STATS_TXMULTICOL 0x8c
244 #define AR8216_STATS_TXSINGLECOL 0x90
245 #define AR8216_STATS_TXEXCDEFER 0x94
246 #define AR8216_STATS_TXDEFER 0x98
247 #define AR8216_STATS_TXLATECOL 0x9c
248
249 #define AR8229_REG_OPER_MODE0 0x04
250 #define AR8229_OPER_MODE0_MAC_GMII_EN BIT(6)
251 #define AR8229_OPER_MODE0_PHY_MII_EN BIT(10)
252
253 #define AR8229_REG_OPER_MODE1 0x08
254 #define AR8229_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
255
256 #define AR8229_REG_QM_CTRL 0x3c
257 #define AR8229_QM_CTRL_ARP_EN BIT(15)
258
259 #define AR8236_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET((_i)) + 0x0008)
260 #define AR8236_PORT_VLAN_DEFAULT_ID BITS(16, 12)
261 #define AR8236_PORT_VLAN_DEFAULT_ID_S 16
262 #define AR8236_PORT_VLAN_PRIORITY BITS(29, 3)
263 #define AR8236_PORT_VLAN_PRIORITY_S 28
264
265 #define AR8236_REG_PORT_VLAN2(_i) (AR8216_PORT_OFFSET((_i)) + 0x000c)
266 #define AR8236_PORT_VLAN2_MEMBER BITS(16, 7)
267 #define AR8236_PORT_VLAN2_MEMBER_S 16
268 #define AR8236_PORT_VLAN2_TX_PRIO BIT(23)
269 #define AR8236_PORT_VLAN2_VLAN_MODE BITS(30, 2)
270 #define AR8236_PORT_VLAN2_VLAN_MODE_S 30
271
272 #define AR8236_STATS_RXBROAD 0x00
273 #define AR8236_STATS_RXPAUSE 0x04
274 #define AR8236_STATS_RXMULTI 0x08
275 #define AR8236_STATS_RXFCSERR 0x0c
276 #define AR8236_STATS_RXALIGNERR 0x10
277 #define AR8236_STATS_RXRUNT 0x14
278 #define AR8236_STATS_RXFRAGMENT 0x18
279 #define AR8236_STATS_RX64BYTE 0x1c
280 #define AR8236_STATS_RX128BYTE 0x20
281 #define AR8236_STATS_RX256BYTE 0x24
282 #define AR8236_STATS_RX512BYTE 0x28
283 #define AR8236_STATS_RX1024BYTE 0x2c
284 #define AR8236_STATS_RX1518BYTE 0x30
285 #define AR8236_STATS_RXMAXBYTE 0x34
286 #define AR8236_STATS_RXTOOLONG 0x38
287 #define AR8236_STATS_RXGOODBYTE 0x3c
288 #define AR8236_STATS_RXBADBYTE 0x44
289 #define AR8236_STATS_RXOVERFLOW 0x4c
290 #define AR8236_STATS_FILTERED 0x50
291 #define AR8236_STATS_TXBROAD 0x54
292 #define AR8236_STATS_TXPAUSE 0x58
293 #define AR8236_STATS_TXMULTI 0x5c
294 #define AR8236_STATS_TXUNDERRUN 0x60
295 #define AR8236_STATS_TX64BYTE 0x64
296 #define AR8236_STATS_TX128BYTE 0x68
297 #define AR8236_STATS_TX256BYTE 0x6c
298 #define AR8236_STATS_TX512BYTE 0x70
299 #define AR8236_STATS_TX1024BYTE 0x74
300 #define AR8236_STATS_TX1518BYTE 0x78
301 #define AR8236_STATS_TXMAXBYTE 0x7c
302 #define AR8236_STATS_TXOVERSIZE 0x80
303 #define AR8236_STATS_TXBYTE 0x84
304 #define AR8236_STATS_TXCOLLISION 0x8c
305 #define AR8236_STATS_TXABORTCOL 0x90
306 #define AR8236_STATS_TXMULTICOL 0x94
307 #define AR8236_STATS_TXSINGLECOL 0x98
308 #define AR8236_STATS_TXEXCDEFER 0x9c
309 #define AR8236_STATS_TXDEFER 0xa0
310 #define AR8236_STATS_TXLATECOL 0xa4
311
312 #define AR8316_REG_POSTRIP 0x0008
313 #define AR8316_POSTRIP_MAC0_GMII_EN BIT(0)
314 #define AR8316_POSTRIP_MAC0_RGMII_EN BIT(1)
315 #define AR8316_POSTRIP_PHY4_GMII_EN BIT(2)
316 #define AR8316_POSTRIP_PHY4_RGMII_EN BIT(3)
317 #define AR8316_POSTRIP_MAC0_MAC_MODE BIT(4)
318 #define AR8316_POSTRIP_RTL_MODE BIT(5)
319 #define AR8316_POSTRIP_RGMII_RXCLK_DELAY_EN BIT(6)
320 #define AR8316_POSTRIP_RGMII_TXCLK_DELAY_EN BIT(7)
321 #define AR8316_POSTRIP_SERDES_EN BIT(8)
322 #define AR8316_POSTRIP_SEL_ANA_RST BIT(9)
323 #define AR8316_POSTRIP_GATE_25M_EN BIT(10)
324 #define AR8316_POSTRIP_SEL_CLK25M BIT(11)
325 #define AR8316_POSTRIP_HIB_PULSE_HW BIT(12)
326 #define AR8316_POSTRIP_DBG_MODE_I BIT(13)
327 #define AR8316_POSTRIP_MAC5_MAC_MODE BIT(14)
328 #define AR8316_POSTRIP_MAC5_PHY_MODE BIT(15)
329 #define AR8316_POSTRIP_POWER_DOWN_HW BIT(16)
330 #define AR8316_POSTRIP_LPW_STATE_EN BIT(17)
331 #define AR8316_POSTRIP_MAN_EN BIT(18)
332 #define AR8316_POSTRIP_PHY_PLL_ON BIT(19)
333 #define AR8316_POSTRIP_LPW_EXIT BIT(20)
334 #define AR8316_POSTRIP_TXDELAY_S0 BIT(21)
335 #define AR8316_POSTRIP_TXDELAY_S1 BIT(22)
336 #define AR8316_POSTRIP_RXDELAY_S0 BIT(23)
337 #define AR8316_POSTRIP_LED_OPEN_EN BIT(24)
338 #define AR8316_POSTRIP_SPI_EN BIT(25)
339 #define AR8316_POSTRIP_RXDELAY_S1 BIT(26)
340 #define AR8316_POSTRIP_POWER_ON_SEL BIT(31)
341
342 /* port speed */
343 enum {
344 AR8216_PORT_SPEED_10M = 0,
345 AR8216_PORT_SPEED_100M = 1,
346 AR8216_PORT_SPEED_1000M = 2,
347 AR8216_PORT_SPEED_ERR = 3,
348 };
349
350 /* ingress 802.1q mode */
351 enum {
352 AR8216_IN_PORT_ONLY = 0,
353 AR8216_IN_PORT_FALLBACK = 1,
354 AR8216_IN_VLAN_ONLY = 2,
355 AR8216_IN_SECURE = 3
356 };
357
358 /* egress 802.1q mode */
359 enum {
360 AR8216_OUT_KEEP = 0,
361 AR8216_OUT_STRIP_VLAN = 1,
362 AR8216_OUT_ADD_VLAN = 2
363 };
364
365 /* port forwarding state */
366 enum {
367 AR8216_PORT_STATE_DISABLED = 0,
368 AR8216_PORT_STATE_BLOCK = 1,
369 AR8216_PORT_STATE_LISTEN = 2,
370 AR8216_PORT_STATE_LEARN = 3,
371 AR8216_PORT_STATE_FORWARD = 4
372 };
373
374 enum {
375 AR8XXX_VER_AR8216 = 0x01,
376 AR8XXX_VER_AR8236 = 0x03,
377 AR8XXX_VER_AR8316 = 0x10,
378 AR8XXX_VER_AR8327 = 0x12,
379 AR8XXX_VER_AR8337 = 0x13,
380 };
381
382 #define AR8XXX_NUM_ARL_RECORDS 100
383
384 enum arl_op {
385 AR8XXX_ARL_INITIALIZE,
386 AR8XXX_ARL_GET_NEXT
387 };
388
389 struct arl_entry {
390 u16 portmap;
391 u8 mac[6];
392 };
393
394 struct ar8xxx_priv;
395
396 struct ar8xxx_mib_desc {
397 unsigned int size;
398 unsigned int offset;
399 const char *name;
400 };
401
402 struct ar8xxx_chip {
403 unsigned long caps;
404 bool config_at_probe;
405 bool mii_lo_first;
406
407 /* parameters to calculate REG_PORT_STATS_BASE */
408 unsigned reg_port_stats_start;
409 unsigned reg_port_stats_length;
410
411 unsigned reg_arl_ctrl;
412
413 int (*hw_init)(struct ar8xxx_priv *priv);
414 void (*cleanup)(struct ar8xxx_priv *priv);
415
416 const char *name;
417 int vlans;
418 int ports;
419 const struct switch_dev_ops *swops;
420
421 void (*init_globals)(struct ar8xxx_priv *priv);
422 void (*init_port)(struct ar8xxx_priv *priv, int port);
423 void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
424 u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
425 u32 (*read_port_eee_status)(struct ar8xxx_priv *priv, int port);
426 int (*atu_flush)(struct ar8xxx_priv *priv);
427 int (*atu_flush_port)(struct ar8xxx_priv *priv, int port);
428 void (*vtu_flush)(struct ar8xxx_priv *priv);
429 void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
430 void (*phy_fixup)(struct ar8xxx_priv *priv, int phy);
431 void (*set_mirror_regs)(struct ar8xxx_priv *priv);
432 void (*get_arl_entry)(struct ar8xxx_priv *priv, struct arl_entry *a,
433 u32 *status, enum arl_op op);
434 int (*sw_hw_apply)(struct switch_dev *dev);
435 void (*phy_rgmii_set)(struct ar8xxx_priv *priv, struct phy_device *phydev);
436 int (*phy_read)(struct ar8xxx_priv *priv, int addr, int regnum);
437 int (*phy_write)(struct ar8xxx_priv *priv, int addr, int regnum, u16 val);
438
439 const struct ar8xxx_mib_desc *mib_decs;
440 unsigned num_mibs;
441 unsigned mib_func;
442 };
443
444 struct ar8xxx_priv {
445 struct switch_dev dev;
446 struct mii_bus *mii_bus;
447 struct mii_bus *sw_mii_bus;
448 struct phy_device *phy;
449 struct device *pdev;
450
451 int (*get_port_link)(unsigned port);
452
453 const struct net_device_ops *ndo_old;
454 struct net_device_ops ndo;
455 struct mutex reg_mutex;
456 u8 chip_ver;
457 u8 chip_rev;
458 const struct ar8xxx_chip *chip;
459 void *chip_data;
460 bool initialized;
461 bool port4_phy;
462 char buf[2048];
463 struct arl_entry arl_table[AR8XXX_NUM_ARL_RECORDS];
464 char arl_buf[AR8XXX_NUM_ARL_RECORDS * 32 + 256];
465 bool link_up[AR8X16_MAX_PORTS];
466
467 bool init;
468
469 struct mutex mib_lock;
470 struct delayed_work mib_work;
471 int mib_next_port;
472 u64 *mib_stats;
473
474 struct list_head list;
475 unsigned int use_count;
476
477 /* all fields below are cleared on reset */
478 bool vlan;
479 u16 vlan_id[AR8X16_MAX_VLANS];
480 u8 vlan_table[AR8X16_MAX_VLANS];
481 u8 vlan_tagged;
482 u16 pvid[AR8X16_MAX_PORTS];
483 int arl_age_time;
484
485 /* mirroring */
486 bool mirror_rx;
487 bool mirror_tx;
488 int source_port;
489 int monitor_port;
490 u8 port_vlan_prio[AR8X16_MAX_PORTS];
491 };
492
493 u32
494 ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum);
495 void
496 ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val);
497 u32
498 ar8xxx_read(struct ar8xxx_priv *priv, int reg);
499 void
500 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val);
501 u32
502 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
503
504 void
505 ar8xxx_phy_dbg_read(struct ar8xxx_priv *priv, int phy_addr,
506 u16 dbg_addr, u16 *dbg_data);
507 void
508 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
509 u16 dbg_addr, u16 dbg_data);
510 void
511 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data);
512 u16
513 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg);
514 void
515 ar8xxx_phy_init(struct ar8xxx_priv *priv);
516 int
517 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
518 struct switch_val *val);
519 int
520 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
521 struct switch_val *val);
522 int
523 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
524 const struct switch_attr *attr,
525 struct switch_val *val);
526 int
527 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
528 const struct switch_attr *attr,
529 struct switch_val *val);
530 int
531 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
532 const struct switch_attr *attr,
533 struct switch_val *val);
534 int
535 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
536 const struct switch_attr *attr,
537 struct switch_val *val);
538 int
539 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
540 const struct switch_attr *attr,
541 struct switch_val *val);
542 int
543 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
544 const struct switch_attr *attr,
545 struct switch_val *val);
546 int
547 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
548 const struct switch_attr *attr,
549 struct switch_val *val);
550 int
551 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
552 const struct switch_attr *attr,
553 struct switch_val *val);
554 int
555 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
556 const struct switch_attr *attr,
557 struct switch_val *val);
558 int
559 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan);
560 int
561 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan);
562 int
563 ar8xxx_sw_hw_apply(struct switch_dev *dev);
564 int
565 ar8xxx_sw_reset_switch(struct switch_dev *dev);
566 int
567 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
568 struct switch_port_link *link);
569 int
570 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
571 const struct switch_attr *attr,
572 struct switch_val *val);
573 int
574 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
575 const struct switch_attr *attr,
576 struct switch_val *val);
577 int
578 ar8xxx_sw_get_arl_age_time(struct switch_dev *dev,
579 const struct switch_attr *attr,
580 struct switch_val *val);
581 int
582 ar8xxx_sw_set_arl_age_time(struct switch_dev *dev,
583 const struct switch_attr *attr,
584 struct switch_val *val);
585 int
586 ar8xxx_sw_get_arl_table(struct switch_dev *dev,
587 const struct switch_attr *attr,
588 struct switch_val *val);
589 int
590 ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev,
591 const struct switch_attr *attr,
592 struct switch_val *val);
593 int
594 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,
595 const struct switch_attr *attr,
596 struct switch_val *val);
597 int
598 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
599
600 static inline struct ar8xxx_priv *
601 swdev_to_ar8xxx(struct switch_dev *swdev)
602 {
603 return container_of(swdev, struct ar8xxx_priv, dev);
604 }
605
606 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
607 {
608 return priv->chip->caps & AR8XXX_CAP_GIGE;
609 }
610
611 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
612 {
613 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
614 }
615
616 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
617 {
618 return priv->chip_ver == AR8XXX_VER_AR8216;
619 }
620
621 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
622 {
623 return priv->chip_ver == AR8XXX_VER_AR8236;
624 }
625
626 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
627 {
628 return priv->chip_ver == AR8XXX_VER_AR8316;
629 }
630
631 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
632 {
633 return priv->chip_ver == AR8XXX_VER_AR8327;
634 }
635
636 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
637 {
638 return priv->chip_ver == AR8XXX_VER_AR8337;
639 }
640
641 static inline void
642 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
643 {
644 ar8xxx_rmw(priv, reg, 0, val);
645 }
646
647 static inline void
648 ar8xxx_reg_clear(struct ar8xxx_priv *priv, int reg, u32 val)
649 {
650 ar8xxx_rmw(priv, reg, val, 0);
651 }
652
653 static inline void
654 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
655 {
656 regaddr >>= 1;
657 *r1 = regaddr & 0x1e;
658
659 regaddr >>= 5;
660 *r2 = regaddr & 0x7;
661
662 regaddr >>= 3;
663 *page = regaddr & 0x1ff;
664 }
665
666 static inline void
667 wait_for_page_switch(void)
668 {
669 udelay(5);
670 }
671
672 #endif
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