projects / openwrt / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
kernel: update phy drivers for 4.9
[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / ar8327.c
1 /*
2 * ar8327.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/list.h>
19 #include <linux/bitops.h>
20 #include <linux/switch.h>
21 #include <linux/delay.h>
22 #include <linux/phy.h>
23 #include <linux/lockdep.h>
24 #include <linux/ar8216_platform.h>
25 #include <linux/workqueue.h>
26 #include <linux/of_device.h>
27 #include <linux/leds.h>
28 #include <linux/mdio.h>
29
30 #include "ar8216.h"
31 #include "ar8327.h"
32
33 extern const struct ar8xxx_mib_desc ar8236_mibs[39];
34 extern const struct switch_attr ar8xxx_sw_attr_vlan[1];
35
36 static u32
37 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
38 {
39 u32 t;
40
41 if (!cfg)
42 return 0;
43
44 t = 0;
45 switch (cfg->mode) {
46 case AR8327_PAD_NC:
47 break;
48
49 case AR8327_PAD_MAC2MAC_MII:
50 t = AR8327_PAD_MAC_MII_EN;
51 if (cfg->rxclk_sel)
52 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
53 if (cfg->txclk_sel)
54 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
55 break;
56
57 case AR8327_PAD_MAC2MAC_GMII:
58 t = AR8327_PAD_MAC_GMII_EN;
59 if (cfg->rxclk_sel)
60 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
61 if (cfg->txclk_sel)
62 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
63 break;
64
65 case AR8327_PAD_MAC_SGMII:
66 t = AR8327_PAD_SGMII_EN;
67
68 /*
69 * WAR for the QUalcomm Atheros AP136 board.
70 * It seems that RGMII TX/RX delay settings needs to be
71 * applied for SGMII mode as well, The ethernet is not
72 * reliable without this.
73 */
74 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
75 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
76 if (cfg->rxclk_delay_en)
77 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
78 if (cfg->txclk_delay_en)
79 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
80
81 if (cfg->sgmii_delay_en)
82 t |= AR8327_PAD_SGMII_DELAY_EN;
83
84 break;
85
86 case AR8327_PAD_MAC2PHY_MII:
87 t = AR8327_PAD_PHY_MII_EN;
88 if (cfg->rxclk_sel)
89 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
90 if (cfg->txclk_sel)
91 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
92 break;
93
94 case AR8327_PAD_MAC2PHY_GMII:
95 t = AR8327_PAD_PHY_GMII_EN;
96 if (cfg->pipe_rxclk_sel)
97 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
98 if (cfg->rxclk_sel)
99 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
100 if (cfg->txclk_sel)
101 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
102 break;
103
104 case AR8327_PAD_MAC_RGMII:
105 t = AR8327_PAD_RGMII_EN;
106 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
107 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
108 if (cfg->rxclk_delay_en)
109 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
110 if (cfg->txclk_delay_en)
111 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
112 break;
113
114 case AR8327_PAD_PHY_GMII:
115 t = AR8327_PAD_PHYX_GMII_EN;
116 break;
117
118 case AR8327_PAD_PHY_RGMII:
119 t = AR8327_PAD_PHYX_RGMII_EN;
120 break;
121
122 case AR8327_PAD_PHY_MII:
123 t = AR8327_PAD_PHYX_MII_EN;
124 break;
125 }
126
127 return t;
128 }
129
130 static void
131 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
132 {
133 switch (priv->chip_rev) {
134 case 1:
135 /* For 100M waveform */
136 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
137 /* Turn on Gigabit clock */
138 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
139 break;
140
141 case 2:
142 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c, 0x0);
143 /* fallthrough */
144 case 4:
145 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d, 0x803f);
146 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
147 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
148 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
149 break;
150 }
151 }
152
153 static u32
154 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
155 {
156 u32 t;
157
158 if (!cfg->force_link)
159 return AR8216_PORT_STATUS_LINK_AUTO;
160
161 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
162 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
163 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
164 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
165
166 switch (cfg->speed) {
167 case AR8327_PORT_SPEED_10:
168 t |= AR8216_PORT_SPEED_10M;
169 break;
170 case AR8327_PORT_SPEED_100:
171 t |= AR8216_PORT_SPEED_100M;
172 break;
173 case AR8327_PORT_SPEED_1000:
174 t |= AR8216_PORT_SPEED_1000M;
175 break;
176 }
177
178 return t;
179 }
180
181 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
182 [_num] = { .reg = (_reg), .shift = (_shift) }
183
184 static const struct ar8327_led_entry
185 ar8327_led_map[AR8327_NUM_LEDS] = {
186 AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
187 AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
188 AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
189
190 AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
191 AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
192 AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
193
194 AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
195 AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
196 AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
197
198 AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
199 AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
200 AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
201
202 AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
203 AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
204 AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
205 };
206
207 static void
208 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
209 enum ar8327_led_pattern pattern)
210 {
211 const struct ar8327_led_entry *entry;
212
213 entry = &ar8327_led_map[led_num];
214 ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
215 (3 << entry->shift), pattern << entry->shift);
216 }
217
218 static void
219 ar8327_led_work_func(struct work_struct *work)
220 {
221 struct ar8327_led *aled;
222 u8 pattern;
223
224 aled = container_of(work, struct ar8327_led, led_work);
225
226 pattern = aled->pattern;
227
228 ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
229 pattern);
230 }
231
232 static void
233 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
234 {
235 if (aled->pattern == pattern)
236 return;
237
238 aled->pattern = pattern;
239 schedule_work(&aled->led_work);
240 }
241
242 static inline struct ar8327_led *
243 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
244 {
245 return container_of(led_cdev, struct ar8327_led, cdev);
246 }
247
248 static int
249 ar8327_led_blink_set(struct led_classdev *led_cdev,
250 unsigned long *delay_on,
251 unsigned long *delay_off)
252 {
253 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
254
255 if (*delay_on == 0 && *delay_off == 0) {
256 *delay_on = 125;
257 *delay_off = 125;
258 }
259
260 if (*delay_on != 125 || *delay_off != 125) {
261 /*
262 * The hardware only supports blinking at 4Hz. Fall back
263 * to software implementation in other cases.
264 */
265 return -EINVAL;
266 }
267
268 spin_lock(&aled->lock);
269
270 aled->enable_hw_mode = false;
271 ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
272
273 spin_unlock(&aled->lock);
274
275 return 0;
276 }
277
278 static void
279 ar8327_led_set_brightness(struct led_classdev *led_cdev,
280 enum led_brightness brightness)
281 {
282 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
283 u8 pattern;
284 bool active;
285
286 active = (brightness != LED_OFF);
287 active ^= aled->active_low;
288
289 pattern = (active) ? AR8327_LED_PATTERN_ON :
290 AR8327_LED_PATTERN_OFF;
291
292 spin_lock(&aled->lock);
293
294 aled->enable_hw_mode = false;
295 ar8327_led_schedule_change(aled, pattern);
296
297 spin_unlock(&aled->lock);
298 }
299
300 static ssize_t
301 ar8327_led_enable_hw_mode_show(struct device *dev,
302 struct device_attribute *attr,
303 char *buf)
304 {
305 struct led_classdev *led_cdev = dev_get_drvdata(dev);
306 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
307 ssize_t ret = 0;
308
309 ret += scnprintf(buf, PAGE_SIZE, "%d\n", aled->enable_hw_mode);
310
311 return ret;
312 }
313
314 static ssize_t
315 ar8327_led_enable_hw_mode_store(struct device *dev,
316 struct device_attribute *attr,
317 const char *buf,
318 size_t size)
319 {
320 struct led_classdev *led_cdev = dev_get_drvdata(dev);
321 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
322 u8 pattern;
323 u8 value;
324 int ret;
325
326 ret = kstrtou8(buf, 10, &value);
327 if (ret < 0)
328 return -EINVAL;
329
330 spin_lock(&aled->lock);
331
332 aled->enable_hw_mode = !!value;
333 if (aled->enable_hw_mode)
334 pattern = AR8327_LED_PATTERN_RULE;
335 else
336 pattern = AR8327_LED_PATTERN_OFF;
337
338 ar8327_led_schedule_change(aled, pattern);
339
340 spin_unlock(&aled->lock);
341
342 return size;
343 }
344
345 static DEVICE_ATTR(enable_hw_mode, S_IRUGO | S_IWUSR,
346 ar8327_led_enable_hw_mode_show,
347 ar8327_led_enable_hw_mode_store);
348
349 static int
350 ar8327_led_register(struct ar8327_led *aled)
351 {
352 int ret;
353
354 ret = led_classdev_register(NULL, &aled->cdev);
355 if (ret < 0)
356 return ret;
357
358 if (aled->mode == AR8327_LED_MODE_HW) {
359 ret = device_create_file(aled->cdev.dev,
360 &dev_attr_enable_hw_mode);
361 if (ret)
362 goto err_unregister;
363 }
364
365 return 0;
366
367 err_unregister:
368 led_classdev_unregister(&aled->cdev);
369 return ret;
370 }
371
372 static void
373 ar8327_led_unregister(struct ar8327_led *aled)
374 {
375 if (aled->mode == AR8327_LED_MODE_HW)
376 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
377
378 led_classdev_unregister(&aled->cdev);
379 cancel_work_sync(&aled->led_work);
380 }
381
382 static int
383 ar8327_led_create(struct ar8xxx_priv *priv,
384 const struct ar8327_led_info *led_info)
385 {
386 struct ar8327_data *data = priv->chip_data;
387 struct ar8327_led *aled;
388 int ret;
389
390 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
391 return 0;
392
393 if (!led_info->name)
394 return -EINVAL;
395
396 if (led_info->led_num >= AR8327_NUM_LEDS)
397 return -EINVAL;
398
399 aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
400 GFP_KERNEL);
401 if (!aled)
402 return -ENOMEM;
403
404 aled->sw_priv = priv;
405 aled->led_num = led_info->led_num;
406 aled->active_low = led_info->active_low;
407 aled->mode = led_info->mode;
408
409 if (aled->mode == AR8327_LED_MODE_HW)
410 aled->enable_hw_mode = true;
411
412 aled->name = (char *)(aled + 1);
413 strcpy(aled->name, led_info->name);
414
415 aled->cdev.name = aled->name;
416 aled->cdev.brightness_set = ar8327_led_set_brightness;
417 aled->cdev.blink_set = ar8327_led_blink_set;
418 aled->cdev.default_trigger = led_info->default_trigger;
419
420 spin_lock_init(&aled->lock);
421 mutex_init(&aled->mutex);
422 INIT_WORK(&aled->led_work, ar8327_led_work_func);
423
424 ret = ar8327_led_register(aled);
425 if (ret)
426 goto err_free;
427
428 data->leds[data->num_leds++] = aled;
429
430 return 0;
431
432 err_free:
433 kfree(aled);
434 return ret;
435 }
436
437 static void
438 ar8327_led_destroy(struct ar8327_led *aled)
439 {
440 ar8327_led_unregister(aled);
441 kfree(aled);
442 }
443
444 static void
445 ar8327_leds_init(struct ar8xxx_priv *priv)
446 {
447 struct ar8327_data *data = priv->chip_data;
448 unsigned i;
449
450 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
451 return;
452
453 for (i = 0; i < data->num_leds; i++) {
454 struct ar8327_led *aled;
455
456 aled = data->leds[i];
457
458 if (aled->enable_hw_mode)
459 aled->pattern = AR8327_LED_PATTERN_RULE;
460 else
461 aled->pattern = AR8327_LED_PATTERN_OFF;
462
463 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
464 }
465 }
466
467 static void
468 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
469 {
470 struct ar8327_data *data = priv->chip_data;
471 unsigned i;
472
473 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
474 return;
475
476 for (i = 0; i < data->num_leds; i++) {
477 struct ar8327_led *aled;
478
479 aled = data->leds[i];
480 ar8327_led_destroy(aled);
481 }
482
483 kfree(data->leds);
484 }
485
486 static int
487 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
488 struct ar8327_platform_data *pdata)
489 {
490 struct ar8327_led_cfg *led_cfg;
491 struct ar8327_data *data = priv->chip_data;
492 u32 pos, new_pos;
493 u32 t;
494
495 if (!pdata)
496 return -EINVAL;
497
498 priv->get_port_link = pdata->get_port_link;
499
500 data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
501 data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
502
503 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
504 if (chip_is_ar8337(priv) && !pdata->pad0_cfg->mac06_exchange_dis)
505 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
506 ar8xxx_write(priv, AR8327_REG_PAD0_MODE, t);
507
508 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
509 ar8xxx_write(priv, AR8327_REG_PAD5_MODE, t);
510 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
511 ar8xxx_write(priv, AR8327_REG_PAD6_MODE, t);
512
513 pos = ar8xxx_read(priv, AR8327_REG_POWER_ON_STRIP);
514 new_pos = pos;
515
516 led_cfg = pdata->led_cfg;
517 if (led_cfg) {
518 if (led_cfg->open_drain)
519 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
520 else
521 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
522
523 ar8xxx_write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
524 ar8xxx_write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
525 ar8xxx_write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
526 ar8xxx_write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
527
528 if (new_pos != pos)
529 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
530 }
531
532 if (pdata->sgmii_cfg) {
533 t = pdata->sgmii_cfg->sgmii_ctrl;
534 if (priv->chip_rev == 1)
535 t |= AR8327_SGMII_CTRL_EN_PLL |
536 AR8327_SGMII_CTRL_EN_RX |
537 AR8327_SGMII_CTRL_EN_TX;
538 else
539 t &= ~(AR8327_SGMII_CTRL_EN_PLL |
540 AR8327_SGMII_CTRL_EN_RX |
541 AR8327_SGMII_CTRL_EN_TX);
542
543 ar8xxx_write(priv, AR8327_REG_SGMII_CTRL, t);
544
545 if (pdata->sgmii_cfg->serdes_aen)
546 new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
547 else
548 new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
549 }
550
551 ar8xxx_write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
552
553 if (pdata->leds && pdata->num_leds) {
554 int i;
555
556 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
557 GFP_KERNEL);
558 if (!data->leds)
559 return -ENOMEM;
560
561 for (i = 0; i < pdata->num_leds; i++)
562 ar8327_led_create(priv, &pdata->leds[i]);
563 }
564
565 return 0;
566 }
567
568 #ifdef CONFIG_OF
569 static int
570 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
571 {
572 struct ar8327_data *data = priv->chip_data;
573 const __be32 *paddr;
574 int len;
575 int i;
576
577 paddr = of_get_property(np, "qca,ar8327-initvals", &len);
578 if (!paddr || len < (2 * sizeof(*paddr)))
579 return -EINVAL;
580
581 len /= sizeof(*paddr);
582
583 for (i = 0; i < len - 1; i += 2) {
584 u32 reg;
585 u32 val;
586
587 reg = be32_to_cpup(paddr + i);
588 val = be32_to_cpup(paddr + i + 1);
589
590 switch (reg) {
591 case AR8327_REG_PORT_STATUS(0):
592 data->port0_status = val;
593 break;
594 case AR8327_REG_PORT_STATUS(6):
595 data->port6_status = val;
596 break;
597 default:
598 ar8xxx_write(priv, reg, val);
599 break;
600 }
601 }
602
603 return 0;
604 }
605 #else
606 static inline int
607 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
608 {
609 return -EINVAL;
610 }
611 #endif
612
613 static int
614 ar8327_hw_init(struct ar8xxx_priv *priv)
615 {
616 int ret;
617
618 priv->chip_data = kzalloc(sizeof(struct ar8327_data), GFP_KERNEL);
619 if (!priv->chip_data)
620 return -ENOMEM;
621
622 if (priv->phy->mdio.dev.of_node)
623 ret = ar8327_hw_config_of(priv, priv->phy->mdio.dev.of_node);
624 else
625 ret = ar8327_hw_config_pdata(priv,
626 priv->phy->mdio.dev.platform_data);
627
628 if (ret)
629 return ret;
630
631 ar8327_leds_init(priv);
632
633 ar8xxx_phy_init(priv);
634
635 return 0;
636 }
637
638 static void
639 ar8327_cleanup(struct ar8xxx_priv *priv)
640 {
641 ar8327_leds_cleanup(priv);
642 }
643
644 static void
645 ar8327_init_globals(struct ar8xxx_priv *priv)
646 {
647 struct ar8327_data *data = priv->chip_data;
648 u32 t;
649 int i;
650
651 /* enable CPU port and disable mirror port */
652 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
653 AR8327_FWD_CTRL0_MIRROR_PORT;
654 ar8xxx_write(priv, AR8327_REG_FWD_CTRL0, t);
655
656 /* forward multicast and broadcast frames to CPU */
657 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
658 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
659 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
660 ar8xxx_write(priv, AR8327_REG_FWD_CTRL1, t);
661
662 /* enable jumbo frames */
663 ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
664 AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
665
666 /* Enable MIB counters */
667 ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
668 AR8327_MODULE_EN_MIB);
669
670 /* Disable EEE on all phy's due to stability issues */
671 for (i = 0; i < AR8XXX_NUM_PHYS; i++)
672 data->eee[i] = false;
673 }
674
675 static void
676 ar8327_init_port(struct ar8xxx_priv *priv, int port)
677 {
678 struct ar8327_data *data = priv->chip_data;
679 u32 t;
680
681 if (port == AR8216_PORT_CPU)
682 t = data->port0_status;
683 else if (port == 6)
684 t = data->port6_status;
685 else
686 t = AR8216_PORT_STATUS_LINK_AUTO;
687
688 if (port != AR8216_PORT_CPU && port != 6) {
689 /*hw limitation:if configure mac when there is traffic,
690 port MAC may work abnormal. Need disable lan&wan mac at fisrt*/
691 ar8xxx_write(priv, AR8327_REG_PORT_STATUS(port), 0);
692 msleep(100);
693 t |= AR8216_PORT_STATUS_FLOW_CONTROL;
694 ar8xxx_write(priv, AR8327_REG_PORT_STATUS(port), t);
695 } else {
696 ar8xxx_write(priv, AR8327_REG_PORT_STATUS(port), t);
697 }
698
699 ar8xxx_write(priv, AR8327_REG_PORT_HEADER(port), 0);
700
701 ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), 0);
702
703 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
704 ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t);
705
706 t = AR8327_PORT_LOOKUP_LEARN;
707 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
708 ar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t);
709 }
710
711 static u32
712 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
713 {
714 u32 t;
715
716 t = ar8xxx_read(priv, AR8327_REG_PORT_STATUS(port));
717 /* map the flow control autoneg result bits to the flow control bits
718 * used in forced mode to allow ar8216_read_port_link detect
719 * flow control properly if autoneg is used
720 */
721 if (t & AR8216_PORT_STATUS_LINK_UP &&
722 t & AR8216_PORT_STATUS_LINK_AUTO) {
723 t &= ~(AR8216_PORT_STATUS_TXFLOW | AR8216_PORT_STATUS_RXFLOW);
724 if (t & AR8327_PORT_STATUS_TXFLOW_AUTO)
725 t |= AR8216_PORT_STATUS_TXFLOW;
726 if (t & AR8327_PORT_STATUS_RXFLOW_AUTO)
727 t |= AR8216_PORT_STATUS_RXFLOW;
728 }
729
730 return t;
731 }
732
733 static u32
734 ar8327_read_port_eee_status(struct ar8xxx_priv *priv, int port)
735 {
736 int phy;
737 u16 t;
738
739 if (port >= priv->dev.ports)
740 return 0;
741
742 if (port == 0 || port == 6)
743 return 0;
744
745 phy = port - 1;
746
747 /* EEE Ability Auto-negotiation Result */
748 t = ar8xxx_phy_mmd_read(priv, phy, 0x7, 0x8000);
749
750 return mmd_eee_adv_to_ethtool_adv_t(t);
751 }
752
753 static int
754 ar8327_atu_flush(struct ar8xxx_priv *priv)
755 {
756 int ret;
757
758 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
759 AR8327_ATU_FUNC_BUSY, 0);
760 if (!ret)
761 ar8xxx_write(priv, AR8327_REG_ATU_FUNC,
762 AR8327_ATU_FUNC_OP_FLUSH |
763 AR8327_ATU_FUNC_BUSY);
764
765 return ret;
766 }
767
768 static int
769 ar8327_atu_flush_port(struct ar8xxx_priv *priv, int port)
770 {
771 u32 t;
772 int ret;
773
774 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
775 AR8327_ATU_FUNC_BUSY, 0);
776 if (!ret) {
777 t = (port << AR8327_ATU_PORT_NUM_S);
778 t |= AR8327_ATU_FUNC_OP_FLUSH_PORT;
779 t |= AR8327_ATU_FUNC_BUSY;
780 ar8xxx_write(priv, AR8327_REG_ATU_FUNC, t);
781 }
782
783 return ret;
784 }
785
786 static int
787 ar8327_get_port_igmp(struct ar8xxx_priv *priv, int port)
788 {
789 u32 fwd_ctrl, frame_ack;
790
791 fwd_ctrl = (BIT(port) << AR8327_FWD_CTRL1_IGMP_S);
792 frame_ack = ((AR8327_FRAME_ACK_CTRL_IGMP_MLD |
793 AR8327_FRAME_ACK_CTRL_IGMP_JOIN |
794 AR8327_FRAME_ACK_CTRL_IGMP_LEAVE) <<
795 AR8327_FRAME_ACK_CTRL_S(port));
796
797 return (ar8xxx_read(priv, AR8327_REG_FWD_CTRL1) &
798 fwd_ctrl) == fwd_ctrl &&
799 (ar8xxx_read(priv, AR8327_REG_FRAME_ACK_CTRL(port)) &
800 frame_ack) == frame_ack;
801 }
802
803 static void
804 ar8327_set_port_igmp(struct ar8xxx_priv *priv, int port, int enable)
805 {
806 int reg_frame_ack = AR8327_REG_FRAME_ACK_CTRL(port);
807 u32 val_frame_ack = (AR8327_FRAME_ACK_CTRL_IGMP_MLD |
808 AR8327_FRAME_ACK_CTRL_IGMP_JOIN |
809 AR8327_FRAME_ACK_CTRL_IGMP_LEAVE) <<
810 AR8327_FRAME_ACK_CTRL_S(port);
811
812 if (enable) {
813 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL1,
814 BIT(port) << AR8327_FWD_CTRL1_MC_FLOOD_S,
815 BIT(port) << AR8327_FWD_CTRL1_IGMP_S);
816 ar8xxx_reg_set(priv, reg_frame_ack, val_frame_ack);
817 } else {
818 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL1,
819 BIT(port) << AR8327_FWD_CTRL1_IGMP_S,
820 BIT(port) << AR8327_FWD_CTRL1_MC_FLOOD_S);
821 ar8xxx_reg_clear(priv, reg_frame_ack, val_frame_ack);
822 }
823 }
824
825 static void
826 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
827 {
828 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
829 AR8327_VTU_FUNC1_BUSY, 0))
830 return;
831
832 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
833 ar8xxx_write(priv, AR8327_REG_VTU_FUNC0, val);
834
835 op |= AR8327_VTU_FUNC1_BUSY;
836 ar8xxx_write(priv, AR8327_REG_VTU_FUNC1, op);
837 }
838
839 static void
840 ar8327_vtu_flush(struct ar8xxx_priv *priv)
841 {
842 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
843 }
844
845 static void
846 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
847 {
848 u32 op;
849 u32 val;
850 int i;
851
852 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
853 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
854 for (i = 0; i < AR8327_NUM_PORTS; i++) {
855 u32 mode;
856
857 if ((port_mask & BIT(i)) == 0)
858 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
859 else if (priv->vlan == 0)
860 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
861 else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))
862 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
863 else
864 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
865
866 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
867 }
868 ar8327_vtu_op(priv, op, val);
869 }
870
871 static void
872 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
873 {
874 u32 t;
875 u32 egress, ingress;
876 u32 pvid = priv->vlan_id[priv->pvid[port]];
877
878 if (priv->vlan) {
879 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
880 ingress = AR8216_IN_SECURE;
881 } else {
882 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
883 ingress = AR8216_IN_PORT_ONLY;
884 }
885
886 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
887 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
888 ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), t);
889
890 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
891 t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
892 ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t);
893
894 t = members;
895 t |= AR8327_PORT_LOOKUP_LEARN;
896 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
897 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
898 ar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t);
899 }
900
901 static int
902 ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
903 {
904 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
905 u8 ports = priv->vlan_table[val->port_vlan];
906 int i;
907
908 val->len = 0;
909 for (i = 0; i < dev->ports; i++) {
910 struct switch_port *p;
911
912 if (!(ports & (1 << i)))
913 continue;
914
915 p = &val->value.ports[val->len++];
916 p->id = i;
917 if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))
918 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
919 else
920 p->flags = 0;
921 }
922 return 0;
923 }
924
925 static int
926 ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
927 {
928 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
929 u8 *vt = &priv->vlan_table[val->port_vlan];
930 int i;
931
932 *vt = 0;
933 for (i = 0; i < val->len; i++) {
934 struct switch_port *p = &val->value.ports[i];
935
936 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
937 if (val->port_vlan == priv->pvid[p->id]) {
938 priv->vlan_tagged |= (1 << p->id);
939 }
940 } else {
941 priv->vlan_tagged &= ~(1 << p->id);
942 priv->pvid[p->id] = val->port_vlan;
943 }
944
945 *vt |= 1 << p->id;
946 }
947 return 0;
948 }
949
950 static void
951 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
952 {
953 int port;
954
955 /* reset all mirror registers */
956 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
957 AR8327_FWD_CTRL0_MIRROR_PORT,
958 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
959 for (port = 0; port < AR8327_NUM_PORTS; port++) {
960 ar8xxx_reg_clear(priv, AR8327_REG_PORT_LOOKUP(port),
961 AR8327_PORT_LOOKUP_ING_MIRROR_EN);
962
963 ar8xxx_reg_clear(priv, AR8327_REG_PORT_HOL_CTRL1(port),
964 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
965 }
966
967 /* now enable mirroring if necessary */
968 if (priv->source_port >= AR8327_NUM_PORTS ||
969 priv->monitor_port >= AR8327_NUM_PORTS ||
970 priv->source_port == priv->monitor_port) {
971 return;
972 }
973
974 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
975 AR8327_FWD_CTRL0_MIRROR_PORT,
976 (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
977
978 if (priv->mirror_rx)
979 ar8xxx_reg_set(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
980 AR8327_PORT_LOOKUP_ING_MIRROR_EN);
981
982 if (priv->mirror_tx)
983 ar8xxx_reg_set(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
984 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
985 }
986
987 static int
988 ar8327_sw_set_eee(struct switch_dev *dev,
989 const struct switch_attr *attr,
990 struct switch_val *val)
991 {
992 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
993 struct ar8327_data *data = priv->chip_data;
994 int port = val->port_vlan;
995 int phy;
996
997 if (port >= dev->ports)
998 return -EINVAL;
999 if (port == 0 || port == 6)
1000 return -EOPNOTSUPP;
1001
1002 phy = port - 1;
1003
1004 data->eee[phy] = !!(val->value.i);
1005
1006 return 0;
1007 }
1008
1009 static int
1010 ar8327_sw_get_eee(struct switch_dev *dev,
1011 const struct switch_attr *attr,
1012 struct switch_val *val)
1013 {
1014 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1015 const struct ar8327_data *data = priv->chip_data;
1016 int port = val->port_vlan;
1017 int phy;
1018
1019 if (port >= dev->ports)
1020 return -EINVAL;
1021 if (port == 0 || port == 6)
1022 return -EOPNOTSUPP;
1023
1024 phy = port - 1;
1025
1026 val->value.i = data->eee[phy];
1027
1028 return 0;
1029 }
1030
1031 #if 0
1032 static void
1033 ar8327_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
1034 {
1035 int timeout = 20;
1036
1037 while (ar8xxx_mii_read32(priv, r2, r1) & AR8327_ATU_FUNC_BUSY && --timeout)
1038 udelay(10);
1039
1040 if (!timeout)
1041 pr_err("ar8327: timeout waiting for atu to become ready\n");
1042 }
1043
1044 static void ar8327_get_arl_entry(struct ar8xxx_priv *priv,
1045 struct arl_entry *a, u32 *status, enum arl_op op)
1046 {
1047 struct mii_bus *bus = priv->mii_bus;
1048 u16 r2, page;
1049 u16 r1_data0, r1_data1, r1_data2, r1_func;
1050 u32 t, val0, val1, val2;
1051 int i;
1052
1053 split_addr(AR8327_REG_ATU_DATA0, &r1_data0, &r2, &page);
1054 r2 |= 0x10;
1055
1056 r1_data1 = (AR8327_REG_ATU_DATA1 >> 1) & 0x1e;
1057 r1_data2 = (AR8327_REG_ATU_DATA2 >> 1) & 0x1e;
1058 r1_func = (AR8327_REG_ATU_FUNC >> 1) & 0x1e;
1059
1060 switch (op) {
1061 case AR8XXX_ARL_INITIALIZE:
1062 /* all ATU registers are on the same page
1063 * therefore set page only once
1064 */
1065 bus->write(bus, 0x18, 0, page);
1066 wait_for_page_switch();
1067
1068 ar8327_wait_atu_ready(priv, r2, r1_func);
1069
1070 ar8xxx_mii_write32(priv, r2, r1_data0, 0);
1071 ar8xxx_mii_write32(priv, r2, r1_data1, 0);
1072 ar8xxx_mii_write32(priv, r2, r1_data2, 0);
1073 break;
1074 case AR8XXX_ARL_GET_NEXT:
1075 ar8xxx_mii_write32(priv, r2, r1_func,
1076 AR8327_ATU_FUNC_OP_GET_NEXT |
1077 AR8327_ATU_FUNC_BUSY);
1078 ar8327_wait_atu_ready(priv, r2, r1_func);
1079
1080 val0 = ar8xxx_mii_read32(priv, r2, r1_data0);
1081 val1 = ar8xxx_mii_read32(priv, r2, r1_data1);
1082 val2 = ar8xxx_mii_read32(priv, r2, r1_data2);
1083
1084 *status = val2 & AR8327_ATU_STATUS;
1085 if (!*status)
1086 break;
1087
1088 i = 0;
1089 t = AR8327_ATU_PORT0;
1090 while (!(val1 & t) && ++i < AR8327_NUM_PORTS)
1091 t <<= 1;
1092
1093 a->port = i;
1094 a->mac[0] = (val0 & AR8327_ATU_ADDR0) >> AR8327_ATU_ADDR0_S;
1095 a->mac[1] = (val0 & AR8327_ATU_ADDR1) >> AR8327_ATU_ADDR1_S;
1096 a->mac[2] = (val0 & AR8327_ATU_ADDR2) >> AR8327_ATU_ADDR2_S;
1097 a->mac[3] = (val0 & AR8327_ATU_ADDR3) >> AR8327_ATU_ADDR3_S;
1098 a->mac[4] = (val1 & AR8327_ATU_ADDR4) >> AR8327_ATU_ADDR4_S;
1099 a->mac[5] = (val1 & AR8327_ATU_ADDR5) >> AR8327_ATU_ADDR5_S;
1100 break;
1101 }
1102 }
1103 #endif
1104
1105 static int
1106 ar8327_sw_hw_apply(struct switch_dev *dev)
1107 {
1108 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1109 const struct ar8327_data *data = priv->chip_data;
1110 int ret, i;
1111
1112 ret = ar8xxx_sw_hw_apply(dev);
1113 if (ret)
1114 return ret;
1115
1116 for (i=0; i < AR8XXX_NUM_PHYS; i++) {
1117 if (data->eee[i])
1118 ar8xxx_reg_clear(priv, AR8327_REG_EEE_CTRL,
1119 AR8327_EEE_CTRL_DISABLE_PHY(i));
1120 else
1121 ar8xxx_reg_set(priv, AR8327_REG_EEE_CTRL,
1122 AR8327_EEE_CTRL_DISABLE_PHY(i));
1123 }
1124
1125 return 0;
1126 }
1127
1128 int
1129 ar8327_sw_get_port_igmp_snooping(struct switch_dev *dev,
1130 const struct switch_attr *attr,
1131 struct switch_val *val)
1132 {
1133 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1134 int port = val->port_vlan;
1135
1136 if (port >= dev->ports)
1137 return -EINVAL;
1138
1139 mutex_lock(&priv->reg_mutex);
1140 val->value.i = ar8327_get_port_igmp(priv, port);
1141 mutex_unlock(&priv->reg_mutex);
1142
1143 return 0;
1144 }
1145
1146 int
1147 ar8327_sw_set_port_igmp_snooping(struct switch_dev *dev,
1148 const struct switch_attr *attr,
1149 struct switch_val *val)
1150 {
1151 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1152 int port = val->port_vlan;
1153
1154 if (port >= dev->ports)
1155 return -EINVAL;
1156
1157 mutex_lock(&priv->reg_mutex);
1158 ar8327_set_port_igmp(priv, port, val->value.i);
1159 mutex_unlock(&priv->reg_mutex);
1160
1161 return 0;
1162 }
1163
1164 int
1165 ar8327_sw_get_igmp_snooping(struct switch_dev *dev,
1166 const struct switch_attr *attr,
1167 struct switch_val *val)
1168 {
1169 int port;
1170
1171 for (port = 0; port < dev->ports; port++) {
1172 val->port_vlan = port;
1173 if (ar8327_sw_get_port_igmp_snooping(dev, attr, val) ||
1174 !val->value.i)
1175 break;
1176 }
1177
1178 return 0;
1179 }
1180
1181 int
1182 ar8327_sw_set_igmp_snooping(struct switch_dev *dev,
1183 const struct switch_attr *attr,
1184 struct switch_val *val)
1185 {
1186 int port;
1187
1188 for (port = 0; port < dev->ports; port++) {
1189 val->port_vlan = port;
1190 if (ar8327_sw_set_port_igmp_snooping(dev, attr, val))
1191 break;
1192 }
1193
1194 return 0;
1195 }
1196
1197 int
1198 ar8327_sw_get_igmp_v3(struct switch_dev *dev,
1199 const struct switch_attr *attr,
1200 struct switch_val *val)
1201 {
1202 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1203 u32 val_reg;
1204
1205 mutex_lock(&priv->reg_mutex);
1206 val_reg = ar8xxx_read(priv, AR8327_REG_FRAME_ACK_CTRL1);
1207 val->value.i = ((val_reg & AR8327_FRAME_ACK_CTRL_IGMP_V3_EN) != 0);
1208 mutex_unlock(&priv->reg_mutex);
1209
1210 return 0;
1211 }
1212
1213 int
1214 ar8327_sw_set_igmp_v3(struct switch_dev *dev,
1215 const struct switch_attr *attr,
1216 struct switch_val *val)
1217 {
1218 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1219
1220 mutex_lock(&priv->reg_mutex);
1221 if (val->value.i)
1222 ar8xxx_reg_set(priv, AR8327_REG_FRAME_ACK_CTRL1,
1223 AR8327_FRAME_ACK_CTRL_IGMP_V3_EN);
1224 else
1225 ar8xxx_reg_clear(priv, AR8327_REG_FRAME_ACK_CTRL1,
1226 AR8327_FRAME_ACK_CTRL_IGMP_V3_EN);
1227 mutex_unlock(&priv->reg_mutex);
1228
1229 return 0;
1230 }
1231
1232 static const struct switch_attr ar8327_sw_attr_globals[] = {
1233 {
1234 .type = SWITCH_TYPE_INT,
1235 .name = "enable_vlan",
1236 .description = "Enable VLAN mode",
1237 .set = ar8xxx_sw_set_vlan,
1238 .get = ar8xxx_sw_get_vlan,
1239 .max = 1
1240 },
1241 {
1242 .type = SWITCH_TYPE_NOVAL,
1243 .name = "reset_mibs",
1244 .description = "Reset all MIB counters",
1245 .set = ar8xxx_sw_set_reset_mibs,
1246 },
1247 {
1248 .type = SWITCH_TYPE_INT,
1249 .name = "enable_mirror_rx",
1250 .description = "Enable mirroring of RX packets",
1251 .set = ar8xxx_sw_set_mirror_rx_enable,
1252 .get = ar8xxx_sw_get_mirror_rx_enable,
1253 .max = 1
1254 },
1255 {
1256 .type = SWITCH_TYPE_INT,
1257 .name = "enable_mirror_tx",
1258 .description = "Enable mirroring of TX packets",
1259 .set = ar8xxx_sw_set_mirror_tx_enable,
1260 .get = ar8xxx_sw_get_mirror_tx_enable,
1261 .max = 1
1262 },
1263 {
1264 .type = SWITCH_TYPE_INT,
1265 .name = "mirror_monitor_port",
1266 .description = "Mirror monitor port",
1267 .set = ar8xxx_sw_set_mirror_monitor_port,
1268 .get = ar8xxx_sw_get_mirror_monitor_port,
1269 .max = AR8327_NUM_PORTS - 1
1270 },
1271 {
1272 .type = SWITCH_TYPE_INT,
1273 .name = "mirror_source_port",
1274 .description = "Mirror source port",
1275 .set = ar8xxx_sw_set_mirror_source_port,
1276 .get = ar8xxx_sw_get_mirror_source_port,
1277 .max = AR8327_NUM_PORTS - 1
1278 },
1279 {
1280 .type = SWITCH_TYPE_INT,
1281 .name = "arl_age_time",
1282 .description = "ARL age time (secs)",
1283 .set = ar8xxx_sw_set_arl_age_time,
1284 .get = ar8xxx_sw_get_arl_age_time,
1285 },
1286 {
1287 .type = SWITCH_TYPE_STRING,
1288 .name = "arl_table",
1289 .description = "Get ARL table",
1290 .set = NULL,
1291 .get = ar8xxx_sw_get_arl_table,
1292 },
1293 {
1294 .type = SWITCH_TYPE_NOVAL,
1295 .name = "flush_arl_table",
1296 .description = "Flush ARL table",
1297 .set = ar8xxx_sw_set_flush_arl_table,
1298 },
1299 {
1300 .type = SWITCH_TYPE_INT,
1301 .name = "igmp_snooping",
1302 .description = "Enable IGMP Snooping",
1303 .set = ar8327_sw_set_igmp_snooping,
1304 .get = ar8327_sw_get_igmp_snooping,
1305 .max = 1
1306 },
1307 {
1308 .type = SWITCH_TYPE_INT,
1309 .name = "igmp_v3",
1310 .description = "Enable IGMPv3 support",
1311 .set = ar8327_sw_set_igmp_v3,
1312 .get = ar8327_sw_get_igmp_v3,
1313 .max = 1
1314 },
1315 };
1316
1317 static const struct switch_attr ar8327_sw_attr_port[] = {
1318 {
1319 .type = SWITCH_TYPE_NOVAL,
1320 .name = "reset_mib",
1321 .description = "Reset single port MIB counters",
1322 .set = ar8xxx_sw_set_port_reset_mib,
1323 },
1324 {
1325 .type = SWITCH_TYPE_STRING,
1326 .name = "mib",
1327 .description = "Get port's MIB counters",
1328 .set = NULL,
1329 .get = ar8xxx_sw_get_port_mib,
1330 },
1331 {
1332 .type = SWITCH_TYPE_INT,
1333 .name = "enable_eee",
1334 .description = "Enable EEE PHY sleep mode",
1335 .set = ar8327_sw_set_eee,
1336 .get = ar8327_sw_get_eee,
1337 .max = 1,
1338 },
1339 {
1340 .type = SWITCH_TYPE_NOVAL,
1341 .name = "flush_arl_table",
1342 .description = "Flush port's ARL table entries",
1343 .set = ar8xxx_sw_set_flush_port_arl_table,
1344 },
1345 {
1346 .type = SWITCH_TYPE_INT,
1347 .name = "igmp_snooping",
1348 .description = "Enable port's IGMP Snooping",
1349 .set = ar8327_sw_set_port_igmp_snooping,
1350 .get = ar8327_sw_get_port_igmp_snooping,
1351 .max = 1
1352 },
1353 };
1354
1355 static const struct switch_dev_ops ar8327_sw_ops = {
1356 .attr_global = {
1357 .attr = ar8327_sw_attr_globals,
1358 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
1359 },
1360 .attr_port = {
1361 .attr = ar8327_sw_attr_port,
1362 .n_attr = ARRAY_SIZE(ar8327_sw_attr_port),
1363 },
1364 .attr_vlan = {
1365 .attr = ar8xxx_sw_attr_vlan,
1366 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1367 },
1368 .get_port_pvid = ar8xxx_sw_get_pvid,
1369 .set_port_pvid = ar8xxx_sw_set_pvid,
1370 .get_vlan_ports = ar8327_sw_get_ports,
1371 .set_vlan_ports = ar8327_sw_set_ports,
1372 .apply_config = ar8327_sw_hw_apply,
1373 .reset_switch = ar8xxx_sw_reset_switch,
1374 .get_port_link = ar8xxx_sw_get_port_link,
1375 };
1376
1377 const struct ar8xxx_chip ar8327_chip = {
1378 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1379 .config_at_probe = true,
1380 .mii_lo_first = true,
1381
1382 .name = "Atheros AR8327",
1383 .ports = AR8327_NUM_PORTS,
1384 .vlans = AR8X16_MAX_VLANS,
1385 .swops = &ar8327_sw_ops,
1386
1387 .reg_port_stats_start = 0x1000,
1388 .reg_port_stats_length = 0x100,
1389 .reg_arl_ctrl = AR8327_REG_ARL_CTRL,
1390
1391 .hw_init = ar8327_hw_init,
1392 .cleanup = ar8327_cleanup,
1393 .init_globals = ar8327_init_globals,
1394 .init_port = ar8327_init_port,
1395 .setup_port = ar8327_setup_port,
1396 .read_port_status = ar8327_read_port_status,
1397 .read_port_eee_status = ar8327_read_port_eee_status,
1398 .atu_flush = ar8327_atu_flush,
1399 .atu_flush_port = ar8327_atu_flush_port,
1400 .vtu_flush = ar8327_vtu_flush,
1401 .vtu_load_vlan = ar8327_vtu_load_vlan,
1402 .phy_fixup = ar8327_phy_fixup,
1403 .set_mirror_regs = ar8327_set_mirror_regs,
1404 #if 0
1405 .get_arl_entry = ar8327_get_arl_entry,
1406 #endif
1407 .sw_hw_apply = ar8327_sw_hw_apply,
1408
1409 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1410 .mib_decs = ar8236_mibs,
1411 .mib_func = AR8327_REG_MIB_FUNC
1412 };
1413
1414 const struct ar8xxx_chip ar8337_chip = {
1415 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1416 .config_at_probe = true,
1417 .mii_lo_first = true,
1418
1419 .name = "Atheros AR8337",
1420 .ports = AR8327_NUM_PORTS,
1421 .vlans = AR8X16_MAX_VLANS,
1422 .swops = &ar8327_sw_ops,
1423
1424 .reg_port_stats_start = 0x1000,
1425 .reg_port_stats_length = 0x100,
1426 .reg_arl_ctrl = AR8327_REG_ARL_CTRL,
1427
1428 .hw_init = ar8327_hw_init,
1429 .cleanup = ar8327_cleanup,
1430 .init_globals = ar8327_init_globals,
1431 .init_port = ar8327_init_port,
1432 .setup_port = ar8327_setup_port,
1433 .read_port_status = ar8327_read_port_status,
1434 .read_port_eee_status = ar8327_read_port_eee_status,
1435 .atu_flush = ar8327_atu_flush,
1436 .atu_flush_port = ar8327_atu_flush_port,
1437 .vtu_flush = ar8327_vtu_flush,
1438 .vtu_load_vlan = ar8327_vtu_load_vlan,
1439 .phy_fixup = ar8327_phy_fixup,
1440 .set_mirror_regs = ar8327_set_mirror_regs,
1441 #if 0
1442 .get_arl_entry = ar8327_get_arl_entry,
1443 #endif
1444 .sw_hw_apply = ar8327_sw_hw_apply,
1445
1446 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1447 .mib_decs = ar8236_mibs,
1448 .mib_func = AR8327_REG_MIB_FUNC
1449 };
OpenWrt Source Repository