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ar8327: add IGMP Snooping support
[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / ar8327.c
1 /*
2 * ar8327.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/list.h>
19 #include <linux/bitops.h>
20 #include <linux/switch.h>
21 #include <linux/delay.h>
22 #include <linux/phy.h>
23 #include <linux/lockdep.h>
24 #include <linux/ar8216_platform.h>
25 #include <linux/workqueue.h>
26 #include <linux/of_device.h>
27 #include <linux/leds.h>
28 #include <linux/mdio.h>
29
30 #include "ar8216.h"
31 #include "ar8327.h"
32
33 extern const struct ar8xxx_mib_desc ar8236_mibs[39];
34 extern const struct switch_attr ar8xxx_sw_attr_vlan[1];
35
36 static u32
37 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
38 {
39 u32 t;
40
41 if (!cfg)
42 return 0;
43
44 t = 0;
45 switch (cfg->mode) {
46 case AR8327_PAD_NC:
47 break;
48
49 case AR8327_PAD_MAC2MAC_MII:
50 t = AR8327_PAD_MAC_MII_EN;
51 if (cfg->rxclk_sel)
52 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
53 if (cfg->txclk_sel)
54 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
55 break;
56
57 case AR8327_PAD_MAC2MAC_GMII:
58 t = AR8327_PAD_MAC_GMII_EN;
59 if (cfg->rxclk_sel)
60 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
61 if (cfg->txclk_sel)
62 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
63 break;
64
65 case AR8327_PAD_MAC_SGMII:
66 t = AR8327_PAD_SGMII_EN;
67
68 /*
69 * WAR for the QUalcomm Atheros AP136 board.
70 * It seems that RGMII TX/RX delay settings needs to be
71 * applied for SGMII mode as well, The ethernet is not
72 * reliable without this.
73 */
74 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
75 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
76 if (cfg->rxclk_delay_en)
77 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
78 if (cfg->txclk_delay_en)
79 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
80
81 if (cfg->sgmii_delay_en)
82 t |= AR8327_PAD_SGMII_DELAY_EN;
83
84 break;
85
86 case AR8327_PAD_MAC2PHY_MII:
87 t = AR8327_PAD_PHY_MII_EN;
88 if (cfg->rxclk_sel)
89 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
90 if (cfg->txclk_sel)
91 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
92 break;
93
94 case AR8327_PAD_MAC2PHY_GMII:
95 t = AR8327_PAD_PHY_GMII_EN;
96 if (cfg->pipe_rxclk_sel)
97 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
98 if (cfg->rxclk_sel)
99 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
100 if (cfg->txclk_sel)
101 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
102 break;
103
104 case AR8327_PAD_MAC_RGMII:
105 t = AR8327_PAD_RGMII_EN;
106 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
107 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
108 if (cfg->rxclk_delay_en)
109 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
110 if (cfg->txclk_delay_en)
111 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
112 break;
113
114 case AR8327_PAD_PHY_GMII:
115 t = AR8327_PAD_PHYX_GMII_EN;
116 break;
117
118 case AR8327_PAD_PHY_RGMII:
119 t = AR8327_PAD_PHYX_RGMII_EN;
120 break;
121
122 case AR8327_PAD_PHY_MII:
123 t = AR8327_PAD_PHYX_MII_EN;
124 break;
125 }
126
127 return t;
128 }
129
130 static void
131 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
132 {
133 switch (priv->chip_rev) {
134 case 1:
135 /* For 100M waveform */
136 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
137 /* Turn on Gigabit clock */
138 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
139 break;
140
141 case 2:
142 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
143 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
144 /* fallthrough */
145 case 4:
146 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
147 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
148
149 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
150 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
151 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
152 break;
153 }
154 }
155
156 static u32
157 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
158 {
159 u32 t;
160
161 if (!cfg->force_link)
162 return AR8216_PORT_STATUS_LINK_AUTO;
163
164 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
165 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
166 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
167 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
168
169 switch (cfg->speed) {
170 case AR8327_PORT_SPEED_10:
171 t |= AR8216_PORT_SPEED_10M;
172 break;
173 case AR8327_PORT_SPEED_100:
174 t |= AR8216_PORT_SPEED_100M;
175 break;
176 case AR8327_PORT_SPEED_1000:
177 t |= AR8216_PORT_SPEED_1000M;
178 break;
179 }
180
181 return t;
182 }
183
184 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
185 [_num] = { .reg = (_reg), .shift = (_shift) }
186
187 static const struct ar8327_led_entry
188 ar8327_led_map[AR8327_NUM_LEDS] = {
189 AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
190 AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
191 AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
192
193 AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
194 AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
195 AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
196
197 AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
198 AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
199 AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
200
201 AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
202 AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
203 AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
204
205 AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
206 AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
207 AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
208 };
209
210 static void
211 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
212 enum ar8327_led_pattern pattern)
213 {
214 const struct ar8327_led_entry *entry;
215
216 entry = &ar8327_led_map[led_num];
217 ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
218 (3 << entry->shift), pattern << entry->shift);
219 }
220
221 static void
222 ar8327_led_work_func(struct work_struct *work)
223 {
224 struct ar8327_led *aled;
225 u8 pattern;
226
227 aled = container_of(work, struct ar8327_led, led_work);
228
229 spin_lock(&aled->lock);
230 pattern = aled->pattern;
231 spin_unlock(&aled->lock);
232
233 ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
234 pattern);
235 }
236
237 static void
238 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
239 {
240 if (aled->pattern == pattern)
241 return;
242
243 aled->pattern = pattern;
244 schedule_work(&aled->led_work);
245 }
246
247 static inline struct ar8327_led *
248 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
249 {
250 return container_of(led_cdev, struct ar8327_led, cdev);
251 }
252
253 static int
254 ar8327_led_blink_set(struct led_classdev *led_cdev,
255 unsigned long *delay_on,
256 unsigned long *delay_off)
257 {
258 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
259
260 if (*delay_on == 0 && *delay_off == 0) {
261 *delay_on = 125;
262 *delay_off = 125;
263 }
264
265 if (*delay_on != 125 || *delay_off != 125) {
266 /*
267 * The hardware only supports blinking at 4Hz. Fall back
268 * to software implementation in other cases.
269 */
270 return -EINVAL;
271 }
272
273 spin_lock(&aled->lock);
274
275 aled->enable_hw_mode = false;
276 ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
277
278 spin_unlock(&aled->lock);
279
280 return 0;
281 }
282
283 static void
284 ar8327_led_set_brightness(struct led_classdev *led_cdev,
285 enum led_brightness brightness)
286 {
287 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
288 u8 pattern;
289 bool active;
290
291 active = (brightness != LED_OFF);
292 active ^= aled->active_low;
293
294 pattern = (active) ? AR8327_LED_PATTERN_ON :
295 AR8327_LED_PATTERN_OFF;
296
297 spin_lock(&aled->lock);
298
299 aled->enable_hw_mode = false;
300 ar8327_led_schedule_change(aled, pattern);
301
302 spin_unlock(&aled->lock);
303 }
304
305 static ssize_t
306 ar8327_led_enable_hw_mode_show(struct device *dev,
307 struct device_attribute *attr,
308 char *buf)
309 {
310 struct led_classdev *led_cdev = dev_get_drvdata(dev);
311 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
312 ssize_t ret = 0;
313
314 spin_lock(&aled->lock);
315 ret += sprintf(buf, "%d\n", aled->enable_hw_mode);
316 spin_unlock(&aled->lock);
317
318 return ret;
319 }
320
321 static ssize_t
322 ar8327_led_enable_hw_mode_store(struct device *dev,
323 struct device_attribute *attr,
324 const char *buf,
325 size_t size)
326 {
327 struct led_classdev *led_cdev = dev_get_drvdata(dev);
328 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
329 u8 pattern;
330 u8 value;
331 int ret;
332
333 ret = kstrtou8(buf, 10, &value);
334 if (ret < 0)
335 return -EINVAL;
336
337 spin_lock(&aled->lock);
338
339 aled->enable_hw_mode = !!value;
340 if (aled->enable_hw_mode)
341 pattern = AR8327_LED_PATTERN_RULE;
342 else
343 pattern = AR8327_LED_PATTERN_OFF;
344
345 ar8327_led_schedule_change(aled, pattern);
346
347 spin_unlock(&aled->lock);
348
349 return size;
350 }
351
352 static DEVICE_ATTR(enable_hw_mode, S_IRUGO | S_IWUSR,
353 ar8327_led_enable_hw_mode_show,
354 ar8327_led_enable_hw_mode_store);
355
356 static int
357 ar8327_led_register(struct ar8327_led *aled)
358 {
359 int ret;
360
361 ret = led_classdev_register(NULL, &aled->cdev);
362 if (ret < 0)
363 return ret;
364
365 if (aled->mode == AR8327_LED_MODE_HW) {
366 ret = device_create_file(aled->cdev.dev,
367 &dev_attr_enable_hw_mode);
368 if (ret)
369 goto err_unregister;
370 }
371
372 return 0;
373
374 err_unregister:
375 led_classdev_unregister(&aled->cdev);
376 return ret;
377 }
378
379 static void
380 ar8327_led_unregister(struct ar8327_led *aled)
381 {
382 if (aled->mode == AR8327_LED_MODE_HW)
383 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
384
385 led_classdev_unregister(&aled->cdev);
386 cancel_work_sync(&aled->led_work);
387 }
388
389 static int
390 ar8327_led_create(struct ar8xxx_priv *priv,
391 const struct ar8327_led_info *led_info)
392 {
393 struct ar8327_data *data = priv->chip_data;
394 struct ar8327_led *aled;
395 int ret;
396
397 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
398 return 0;
399
400 if (!led_info->name)
401 return -EINVAL;
402
403 if (led_info->led_num >= AR8327_NUM_LEDS)
404 return -EINVAL;
405
406 aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
407 GFP_KERNEL);
408 if (!aled)
409 return -ENOMEM;
410
411 aled->sw_priv = priv;
412 aled->led_num = led_info->led_num;
413 aled->active_low = led_info->active_low;
414 aled->mode = led_info->mode;
415
416 if (aled->mode == AR8327_LED_MODE_HW)
417 aled->enable_hw_mode = true;
418
419 aled->name = (char *)(aled + 1);
420 strcpy(aled->name, led_info->name);
421
422 aled->cdev.name = aled->name;
423 aled->cdev.brightness_set = ar8327_led_set_brightness;
424 aled->cdev.blink_set = ar8327_led_blink_set;
425 aled->cdev.default_trigger = led_info->default_trigger;
426
427 spin_lock_init(&aled->lock);
428 mutex_init(&aled->mutex);
429 INIT_WORK(&aled->led_work, ar8327_led_work_func);
430
431 ret = ar8327_led_register(aled);
432 if (ret)
433 goto err_free;
434
435 data->leds[data->num_leds++] = aled;
436
437 return 0;
438
439 err_free:
440 kfree(aled);
441 return ret;
442 }
443
444 static void
445 ar8327_led_destroy(struct ar8327_led *aled)
446 {
447 ar8327_led_unregister(aled);
448 kfree(aled);
449 }
450
451 static void
452 ar8327_leds_init(struct ar8xxx_priv *priv)
453 {
454 struct ar8327_data *data = priv->chip_data;
455 unsigned i;
456
457 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
458 return;
459
460 for (i = 0; i < data->num_leds; i++) {
461 struct ar8327_led *aled;
462
463 aled = data->leds[i];
464
465 if (aled->enable_hw_mode)
466 aled->pattern = AR8327_LED_PATTERN_RULE;
467 else
468 aled->pattern = AR8327_LED_PATTERN_OFF;
469
470 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
471 }
472 }
473
474 static void
475 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
476 {
477 struct ar8327_data *data = priv->chip_data;
478 unsigned i;
479
480 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
481 return;
482
483 for (i = 0; i < data->num_leds; i++) {
484 struct ar8327_led *aled;
485
486 aled = data->leds[i];
487 ar8327_led_destroy(aled);
488 }
489
490 kfree(data->leds);
491 }
492
493 static int
494 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
495 struct ar8327_platform_data *pdata)
496 {
497 struct ar8327_led_cfg *led_cfg;
498 struct ar8327_data *data = priv->chip_data;
499 u32 pos, new_pos;
500 u32 t;
501
502 if (!pdata)
503 return -EINVAL;
504
505 priv->get_port_link = pdata->get_port_link;
506
507 data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
508 data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
509
510 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
511 if (chip_is_ar8337(priv) && !pdata->pad0_cfg->mac06_exchange_dis)
512 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
513 ar8xxx_write(priv, AR8327_REG_PAD0_MODE, t);
514
515 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
516 ar8xxx_write(priv, AR8327_REG_PAD5_MODE, t);
517 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
518 ar8xxx_write(priv, AR8327_REG_PAD6_MODE, t);
519
520 pos = ar8xxx_read(priv, AR8327_REG_POWER_ON_STRIP);
521 new_pos = pos;
522
523 led_cfg = pdata->led_cfg;
524 if (led_cfg) {
525 if (led_cfg->open_drain)
526 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
527 else
528 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
529
530 ar8xxx_write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
531 ar8xxx_write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
532 ar8xxx_write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
533 ar8xxx_write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
534
535 if (new_pos != pos)
536 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
537 }
538
539 if (pdata->sgmii_cfg) {
540 t = pdata->sgmii_cfg->sgmii_ctrl;
541 if (priv->chip_rev == 1)
542 t |= AR8327_SGMII_CTRL_EN_PLL |
543 AR8327_SGMII_CTRL_EN_RX |
544 AR8327_SGMII_CTRL_EN_TX;
545 else
546 t &= ~(AR8327_SGMII_CTRL_EN_PLL |
547 AR8327_SGMII_CTRL_EN_RX |
548 AR8327_SGMII_CTRL_EN_TX);
549
550 ar8xxx_write(priv, AR8327_REG_SGMII_CTRL, t);
551
552 if (pdata->sgmii_cfg->serdes_aen)
553 new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
554 else
555 new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
556 }
557
558 ar8xxx_write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
559
560 if (pdata->leds && pdata->num_leds) {
561 int i;
562
563 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
564 GFP_KERNEL);
565 if (!data->leds)
566 return -ENOMEM;
567
568 for (i = 0; i < pdata->num_leds; i++)
569 ar8327_led_create(priv, &pdata->leds[i]);
570 }
571
572 return 0;
573 }
574
575 #ifdef CONFIG_OF
576 static int
577 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
578 {
579 struct ar8327_data *data = priv->chip_data;
580 const __be32 *paddr;
581 int len;
582 int i;
583
584 paddr = of_get_property(np, "qca,ar8327-initvals", &len);
585 if (!paddr || len < (2 * sizeof(*paddr)))
586 return -EINVAL;
587
588 len /= sizeof(*paddr);
589
590 for (i = 0; i < len - 1; i += 2) {
591 u32 reg;
592 u32 val;
593
594 reg = be32_to_cpup(paddr + i);
595 val = be32_to_cpup(paddr + i + 1);
596
597 switch (reg) {
598 case AR8327_REG_PORT_STATUS(0):
599 data->port0_status = val;
600 break;
601 case AR8327_REG_PORT_STATUS(6):
602 data->port6_status = val;
603 break;
604 default:
605 ar8xxx_write(priv, reg, val);
606 break;
607 }
608 }
609
610 return 0;
611 }
612 #else
613 static inline int
614 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
615 {
616 return -EINVAL;
617 }
618 #endif
619
620 static int
621 ar8327_hw_init(struct ar8xxx_priv *priv)
622 {
623 int ret;
624
625 priv->chip_data = kzalloc(sizeof(struct ar8327_data), GFP_KERNEL);
626 if (!priv->chip_data)
627 return -ENOMEM;
628
629 if (priv->phy->dev.of_node)
630 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
631 else
632 ret = ar8327_hw_config_pdata(priv,
633 priv->phy->dev.platform_data);
634
635 if (ret)
636 return ret;
637
638 ar8327_leds_init(priv);
639
640 ar8xxx_phy_init(priv);
641
642 return 0;
643 }
644
645 static void
646 ar8327_cleanup(struct ar8xxx_priv *priv)
647 {
648 ar8327_leds_cleanup(priv);
649 }
650
651 static void
652 ar8327_init_globals(struct ar8xxx_priv *priv)
653 {
654 struct ar8327_data *data = priv->chip_data;
655 u32 t;
656 int i;
657
658 /* enable CPU port and disable mirror port */
659 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
660 AR8327_FWD_CTRL0_MIRROR_PORT;
661 ar8xxx_write(priv, AR8327_REG_FWD_CTRL0, t);
662
663 /* forward multicast and broadcast frames to CPU */
664 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
665 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
666 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
667 ar8xxx_write(priv, AR8327_REG_FWD_CTRL1, t);
668
669 /* enable jumbo frames */
670 ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
671 AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
672
673 /* Enable MIB counters */
674 ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
675 AR8327_MODULE_EN_MIB);
676
677 /* Disable EEE on all phy's due to stability issues */
678 for (i = 0; i < AR8XXX_NUM_PHYS; i++)
679 data->eee[i] = false;
680 }
681
682 static void
683 ar8327_init_port(struct ar8xxx_priv *priv, int port)
684 {
685 struct ar8327_data *data = priv->chip_data;
686 u32 t;
687
688 if (port == AR8216_PORT_CPU)
689 t = data->port0_status;
690 else if (port == 6)
691 t = data->port6_status;
692 else
693 t = AR8216_PORT_STATUS_LINK_AUTO;
694
695 ar8xxx_write(priv, AR8327_REG_PORT_STATUS(port), t);
696 ar8xxx_write(priv, AR8327_REG_PORT_HEADER(port), 0);
697
698 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
699 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
700 ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), t);
701
702 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
703 ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t);
704
705 t = AR8327_PORT_LOOKUP_LEARN;
706 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
707 ar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t);
708 }
709
710 static u32
711 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
712 {
713 u32 t;
714
715 t = ar8xxx_read(priv, AR8327_REG_PORT_STATUS(port));
716 /* map the flow control autoneg result bits to the flow control bits
717 * used in forced mode to allow ar8216_read_port_link detect
718 * flow control properly if autoneg is used
719 */
720 if (t & AR8216_PORT_STATUS_LINK_UP &&
721 t & AR8216_PORT_STATUS_LINK_AUTO) {
722 t &= ~(AR8216_PORT_STATUS_TXFLOW | AR8216_PORT_STATUS_RXFLOW);
723 if (t & AR8327_PORT_STATUS_TXFLOW_AUTO)
724 t |= AR8216_PORT_STATUS_TXFLOW;
725 if (t & AR8327_PORT_STATUS_RXFLOW_AUTO)
726 t |= AR8216_PORT_STATUS_RXFLOW;
727 }
728
729 return t;
730 }
731
732 static u32
733 ar8327_read_port_eee_status(struct ar8xxx_priv *priv, int port)
734 {
735 int phy;
736 u16 t;
737
738 if (port >= priv->dev.ports)
739 return 0;
740
741 if (port == 0 || port == 6)
742 return 0;
743
744 phy = port - 1;
745
746 /* EEE Ability Auto-negotiation Result */
747 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x8000);
748 t = ar8xxx_phy_mmd_read(priv, phy, 0x4007);
749
750 return mmd_eee_adv_to_ethtool_adv_t(t);
751 }
752
753 static int
754 ar8327_atu_flush(struct ar8xxx_priv *priv)
755 {
756 int ret;
757
758 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
759 AR8327_ATU_FUNC_BUSY, 0);
760 if (!ret)
761 ar8xxx_write(priv, AR8327_REG_ATU_FUNC,
762 AR8327_ATU_FUNC_OP_FLUSH |
763 AR8327_ATU_FUNC_BUSY);
764
765 return ret;
766 }
767
768 static int
769 ar8327_atu_flush_port(struct ar8xxx_priv *priv, int port)
770 {
771 u32 t;
772 int ret;
773
774 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
775 AR8327_ATU_FUNC_BUSY, 0);
776 if (!ret) {
777 t = (port << AR8327_ATU_PORT_NUM_S);
778 t |= AR8327_ATU_FUNC_OP_FLUSH_PORT;
779 t |= AR8327_ATU_FUNC_BUSY;
780 ar8xxx_write(priv, AR8327_REG_ATU_FUNC, t);
781 }
782
783 return ret;
784 }
785
786 static int
787 ar8327_get_port_igmp(struct ar8xxx_priv *priv, int port)
788 {
789 u32 fwd_ctrl, frame_ack;
790
791 fwd_ctrl = (BIT(port) << AR8327_FWD_CTRL1_IGMP_S);
792 frame_ack = ((AR8327_FRAME_ACK_CTRL_IGMP_MLD |
793 AR8327_FRAME_ACK_CTRL_IGMP_JOIN |
794 AR8327_FRAME_ACK_CTRL_IGMP_LEAVE) <<
795 AR8327_FRAME_ACK_CTRL_S(port));
796
797 return (ar8xxx_read(priv, AR8327_REG_FWD_CTRL1) &
798 fwd_ctrl) == fwd_ctrl &&
799 (ar8xxx_read(priv, AR8327_REG_FRAME_ACK_CTRL(port)) &
800 frame_ack) == frame_ack;
801 }
802
803 static void
804 ar8327_set_port_igmp(struct ar8xxx_priv *priv, int port, int enable)
805 {
806 int reg_frame_ack = AR8327_REG_FRAME_ACK_CTRL(port);
807 u32 val_frame_ack = (AR8327_FRAME_ACK_CTRL_IGMP_MLD |
808 AR8327_FRAME_ACK_CTRL_IGMP_JOIN |
809 AR8327_FRAME_ACK_CTRL_IGMP_LEAVE) <<
810 AR8327_FRAME_ACK_CTRL_S(port);
811
812 if (enable) {
813 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL1,
814 BIT(port) << AR8327_FWD_CTRL1_MC_FLOOD_S,
815 BIT(port) << AR8327_FWD_CTRL1_IGMP_S);
816 ar8xxx_reg_set(priv, reg_frame_ack, val_frame_ack);
817 } else {
818 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL1,
819 BIT(port) << AR8327_FWD_CTRL1_IGMP_S,
820 BIT(port) << AR8327_FWD_CTRL1_MC_FLOOD_S);
821 ar8xxx_reg_clear(priv, reg_frame_ack, val_frame_ack);
822 }
823 }
824
825 static void
826 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
827 {
828 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
829 AR8327_VTU_FUNC1_BUSY, 0))
830 return;
831
832 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
833 ar8xxx_write(priv, AR8327_REG_VTU_FUNC0, val);
834
835 op |= AR8327_VTU_FUNC1_BUSY;
836 ar8xxx_write(priv, AR8327_REG_VTU_FUNC1, op);
837 }
838
839 static void
840 ar8327_vtu_flush(struct ar8xxx_priv *priv)
841 {
842 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
843 }
844
845 static void
846 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
847 {
848 u32 op;
849 u32 val;
850 int i;
851
852 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
853 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
854 for (i = 0; i < AR8327_NUM_PORTS; i++) {
855 u32 mode;
856
857 if ((port_mask & BIT(i)) == 0)
858 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
859 else if (priv->vlan == 0)
860 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
861 else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))
862 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
863 else
864 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
865
866 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
867 }
868 ar8327_vtu_op(priv, op, val);
869 }
870
871 static void
872 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
873 {
874 u32 t;
875 u32 egress, ingress;
876 u32 pvid = priv->vlan_id[priv->pvid[port]];
877
878 if (priv->vlan) {
879 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
880 ingress = AR8216_IN_SECURE;
881 } else {
882 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
883 ingress = AR8216_IN_PORT_ONLY;
884 }
885
886 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
887 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
888 ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), t);
889
890 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
891 t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
892 ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t);
893
894 t = members;
895 t |= AR8327_PORT_LOOKUP_LEARN;
896 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
897 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
898 ar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t);
899 }
900
901 static int
902 ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
903 {
904 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
905 u8 ports = priv->vlan_table[val->port_vlan];
906 int i;
907
908 val->len = 0;
909 for (i = 0; i < dev->ports; i++) {
910 struct switch_port *p;
911
912 if (!(ports & (1 << i)))
913 continue;
914
915 p = &val->value.ports[val->len++];
916 p->id = i;
917 if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))
918 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
919 else
920 p->flags = 0;
921 }
922 return 0;
923 }
924
925 static int
926 ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
927 {
928 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
929 u8 *vt = &priv->vlan_table[val->port_vlan];
930 int i;
931
932 *vt = 0;
933 for (i = 0; i < val->len; i++) {
934 struct switch_port *p = &val->value.ports[i];
935
936 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
937 if (val->port_vlan == priv->pvid[p->id]) {
938 priv->vlan_tagged |= (1 << p->id);
939 }
940 } else {
941 priv->vlan_tagged &= ~(1 << p->id);
942 priv->pvid[p->id] = val->port_vlan;
943 }
944
945 *vt |= 1 << p->id;
946 }
947 return 0;
948 }
949
950 static void
951 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
952 {
953 int port;
954
955 /* reset all mirror registers */
956 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
957 AR8327_FWD_CTRL0_MIRROR_PORT,
958 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
959 for (port = 0; port < AR8327_NUM_PORTS; port++) {
960 ar8xxx_reg_clear(priv, AR8327_REG_PORT_LOOKUP(port),
961 AR8327_PORT_LOOKUP_ING_MIRROR_EN);
962
963 ar8xxx_reg_clear(priv, AR8327_REG_PORT_HOL_CTRL1(port),
964 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
965 }
966
967 /* now enable mirroring if necessary */
968 if (priv->source_port >= AR8327_NUM_PORTS ||
969 priv->monitor_port >= AR8327_NUM_PORTS ||
970 priv->source_port == priv->monitor_port) {
971 return;
972 }
973
974 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
975 AR8327_FWD_CTRL0_MIRROR_PORT,
976 (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
977
978 if (priv->mirror_rx)
979 ar8xxx_reg_set(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
980 AR8327_PORT_LOOKUP_ING_MIRROR_EN);
981
982 if (priv->mirror_tx)
983 ar8xxx_reg_set(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
984 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
985 }
986
987 static int
988 ar8327_sw_set_eee(struct switch_dev *dev,
989 const struct switch_attr *attr,
990 struct switch_val *val)
991 {
992 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
993 struct ar8327_data *data = priv->chip_data;
994 int port = val->port_vlan;
995 int phy;
996
997 if (port >= dev->ports)
998 return -EINVAL;
999 if (port == 0 || port == 6)
1000 return -EOPNOTSUPP;
1001
1002 phy = port - 1;
1003
1004 data->eee[phy] = !!(val->value.i);
1005
1006 return 0;
1007 }
1008
1009 static int
1010 ar8327_sw_get_eee(struct switch_dev *dev,
1011 const struct switch_attr *attr,
1012 struct switch_val *val)
1013 {
1014 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1015 const struct ar8327_data *data = priv->chip_data;
1016 int port = val->port_vlan;
1017 int phy;
1018
1019 if (port >= dev->ports)
1020 return -EINVAL;
1021 if (port == 0 || port == 6)
1022 return -EOPNOTSUPP;
1023
1024 phy = port - 1;
1025
1026 val->value.i = data->eee[phy];
1027
1028 return 0;
1029 }
1030
1031 static void
1032 ar8327_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
1033 {
1034 int timeout = 20;
1035
1036 while (ar8xxx_mii_read32(priv, r2, r1) & AR8327_ATU_FUNC_BUSY && --timeout)
1037 udelay(10);
1038
1039 if (!timeout)
1040 pr_err("ar8327: timeout waiting for atu to become ready\n");
1041 }
1042
1043 static void ar8327_get_arl_entry(struct ar8xxx_priv *priv,
1044 struct arl_entry *a, u32 *status, enum arl_op op)
1045 {
1046 struct mii_bus *bus = priv->mii_bus;
1047 u16 r2, page;
1048 u16 r1_data0, r1_data1, r1_data2, r1_func;
1049 u32 t, val0, val1, val2;
1050 int i;
1051
1052 split_addr(AR8327_REG_ATU_DATA0, &r1_data0, &r2, &page);
1053 r2 |= 0x10;
1054
1055 r1_data1 = (AR8327_REG_ATU_DATA1 >> 1) & 0x1e;
1056 r1_data2 = (AR8327_REG_ATU_DATA2 >> 1) & 0x1e;
1057 r1_func = (AR8327_REG_ATU_FUNC >> 1) & 0x1e;
1058
1059 switch (op) {
1060 case AR8XXX_ARL_INITIALIZE:
1061 /* all ATU registers are on the same page
1062 * therefore set page only once
1063 */
1064 bus->write(bus, 0x18, 0, page);
1065 wait_for_page_switch();
1066
1067 ar8327_wait_atu_ready(priv, r2, r1_func);
1068
1069 ar8xxx_mii_write32(priv, r2, r1_data0, 0);
1070 ar8xxx_mii_write32(priv, r2, r1_data1, 0);
1071 ar8xxx_mii_write32(priv, r2, r1_data2, 0);
1072 break;
1073 case AR8XXX_ARL_GET_NEXT:
1074 ar8xxx_mii_write32(priv, r2, r1_func,
1075 AR8327_ATU_FUNC_OP_GET_NEXT |
1076 AR8327_ATU_FUNC_BUSY);
1077 ar8327_wait_atu_ready(priv, r2, r1_func);
1078
1079 val0 = ar8xxx_mii_read32(priv, r2, r1_data0);
1080 val1 = ar8xxx_mii_read32(priv, r2, r1_data1);
1081 val2 = ar8xxx_mii_read32(priv, r2, r1_data2);
1082
1083 *status = val2 & AR8327_ATU_STATUS;
1084 if (!*status)
1085 break;
1086
1087 i = 0;
1088 t = AR8327_ATU_PORT0;
1089 while (!(val1 & t) && ++i < AR8327_NUM_PORTS)
1090 t <<= 1;
1091
1092 a->port = i;
1093 a->mac[0] = (val0 & AR8327_ATU_ADDR0) >> AR8327_ATU_ADDR0_S;
1094 a->mac[1] = (val0 & AR8327_ATU_ADDR1) >> AR8327_ATU_ADDR1_S;
1095 a->mac[2] = (val0 & AR8327_ATU_ADDR2) >> AR8327_ATU_ADDR2_S;
1096 a->mac[3] = (val0 & AR8327_ATU_ADDR3) >> AR8327_ATU_ADDR3_S;
1097 a->mac[4] = (val1 & AR8327_ATU_ADDR4) >> AR8327_ATU_ADDR4_S;
1098 a->mac[5] = (val1 & AR8327_ATU_ADDR5) >> AR8327_ATU_ADDR5_S;
1099 break;
1100 }
1101 }
1102
1103 static int
1104 ar8327_sw_hw_apply(struct switch_dev *dev)
1105 {
1106 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1107 const struct ar8327_data *data = priv->chip_data;
1108 int ret, i;
1109
1110 ret = ar8xxx_sw_hw_apply(dev);
1111 if (ret)
1112 return ret;
1113
1114 for (i=0; i < AR8XXX_NUM_PHYS; i++) {
1115 if (data->eee[i])
1116 ar8xxx_reg_clear(priv, AR8327_REG_EEE_CTRL,
1117 AR8327_EEE_CTRL_DISABLE_PHY(i));
1118 else
1119 ar8xxx_reg_set(priv, AR8327_REG_EEE_CTRL,
1120 AR8327_EEE_CTRL_DISABLE_PHY(i));
1121 }
1122
1123 return 0;
1124 }
1125
1126 int
1127 ar8327_sw_get_port_igmp_snooping(struct switch_dev *dev,
1128 const struct switch_attr *attr,
1129 struct switch_val *val)
1130 {
1131 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1132 int port = val->port_vlan;
1133
1134 if (port >= dev->ports)
1135 return -EINVAL;
1136
1137 mutex_lock(&priv->reg_mutex);
1138 val->value.i = ar8327_get_port_igmp(priv, port);
1139 mutex_unlock(&priv->reg_mutex);
1140
1141 return 0;
1142 }
1143
1144 int
1145 ar8327_sw_set_port_igmp_snooping(struct switch_dev *dev,
1146 const struct switch_attr *attr,
1147 struct switch_val *val)
1148 {
1149 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1150 int port = val->port_vlan;
1151
1152 if (port >= dev->ports)
1153 return -EINVAL;
1154
1155 mutex_lock(&priv->reg_mutex);
1156 ar8327_set_port_igmp(priv, port, val->value.i);
1157 mutex_unlock(&priv->reg_mutex);
1158
1159 return 0;
1160 }
1161
1162 int
1163 ar8327_sw_get_igmp_snooping(struct switch_dev *dev,
1164 const struct switch_attr *attr,
1165 struct switch_val *val)
1166 {
1167 int port;
1168
1169 for (port = 0; port < dev->ports; port++) {
1170 val->port_vlan = port;
1171 if (ar8327_sw_get_port_igmp_snooping(dev, attr, val) ||
1172 !val->value.i)
1173 break;
1174 }
1175
1176 return 0;
1177 }
1178
1179 int
1180 ar8327_sw_set_igmp_snooping(struct switch_dev *dev,
1181 const struct switch_attr *attr,
1182 struct switch_val *val)
1183 {
1184 int port;
1185
1186 for (port = 0; port < dev->ports; port++) {
1187 val->port_vlan = port;
1188 if (ar8327_sw_set_port_igmp_snooping(dev, attr, val))
1189 break;
1190 }
1191
1192 return 0;
1193 }
1194
1195 int
1196 ar8327_sw_get_igmp_v3(struct switch_dev *dev,
1197 const struct switch_attr *attr,
1198 struct switch_val *val)
1199 {
1200 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1201 u32 val_reg;
1202
1203 mutex_lock(&priv->reg_mutex);
1204 val_reg = ar8xxx_read(priv, AR8327_REG_FRAME_ACK_CTRL1);
1205 val->value.i = ((val_reg & AR8327_FRAME_ACK_CTRL_IGMP_V3_EN) != 0);
1206 mutex_unlock(&priv->reg_mutex);
1207
1208 return 0;
1209 }
1210
1211 int
1212 ar8327_sw_set_igmp_v3(struct switch_dev *dev,
1213 const struct switch_attr *attr,
1214 struct switch_val *val)
1215 {
1216 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1217
1218 mutex_lock(&priv->reg_mutex);
1219 if (val->value.i)
1220 ar8xxx_reg_set(priv, AR8327_REG_FRAME_ACK_CTRL1,
1221 AR8327_FRAME_ACK_CTRL_IGMP_V3_EN);
1222 else
1223 ar8xxx_reg_clear(priv, AR8327_REG_FRAME_ACK_CTRL1,
1224 AR8327_FRAME_ACK_CTRL_IGMP_V3_EN);
1225 mutex_unlock(&priv->reg_mutex);
1226
1227 return 0;
1228 }
1229
1230 static const struct switch_attr ar8327_sw_attr_globals[] = {
1231 {
1232 .type = SWITCH_TYPE_INT,
1233 .name = "enable_vlan",
1234 .description = "Enable VLAN mode",
1235 .set = ar8xxx_sw_set_vlan,
1236 .get = ar8xxx_sw_get_vlan,
1237 .max = 1
1238 },
1239 {
1240 .type = SWITCH_TYPE_NOVAL,
1241 .name = "reset_mibs",
1242 .description = "Reset all MIB counters",
1243 .set = ar8xxx_sw_set_reset_mibs,
1244 },
1245 {
1246 .type = SWITCH_TYPE_INT,
1247 .name = "enable_mirror_rx",
1248 .description = "Enable mirroring of RX packets",
1249 .set = ar8xxx_sw_set_mirror_rx_enable,
1250 .get = ar8xxx_sw_get_mirror_rx_enable,
1251 .max = 1
1252 },
1253 {
1254 .type = SWITCH_TYPE_INT,
1255 .name = "enable_mirror_tx",
1256 .description = "Enable mirroring of TX packets",
1257 .set = ar8xxx_sw_set_mirror_tx_enable,
1258 .get = ar8xxx_sw_get_mirror_tx_enable,
1259 .max = 1
1260 },
1261 {
1262 .type = SWITCH_TYPE_INT,
1263 .name = "mirror_monitor_port",
1264 .description = "Mirror monitor port",
1265 .set = ar8xxx_sw_set_mirror_monitor_port,
1266 .get = ar8xxx_sw_get_mirror_monitor_port,
1267 .max = AR8327_NUM_PORTS - 1
1268 },
1269 {
1270 .type = SWITCH_TYPE_INT,
1271 .name = "mirror_source_port",
1272 .description = "Mirror source port",
1273 .set = ar8xxx_sw_set_mirror_source_port,
1274 .get = ar8xxx_sw_get_mirror_source_port,
1275 .max = AR8327_NUM_PORTS - 1
1276 },
1277 {
1278 .type = SWITCH_TYPE_STRING,
1279 .name = "arl_table",
1280 .description = "Get ARL table",
1281 .set = NULL,
1282 .get = ar8xxx_sw_get_arl_table,
1283 },
1284 {
1285 .type = SWITCH_TYPE_NOVAL,
1286 .name = "flush_arl_table",
1287 .description = "Flush ARL table",
1288 .set = ar8xxx_sw_set_flush_arl_table,
1289 },
1290 {
1291 .type = SWITCH_TYPE_INT,
1292 .name = "igmp_snooping",
1293 .description = "Enable IGMP Snooping",
1294 .set = ar8327_sw_set_igmp_snooping,
1295 .get = ar8327_sw_get_igmp_snooping,
1296 .max = 1
1297 },
1298 {
1299 .type = SWITCH_TYPE_INT,
1300 .name = "igmp_v3",
1301 .description = "Enable IGMPv3 support",
1302 .set = ar8327_sw_set_igmp_v3,
1303 .get = ar8327_sw_get_igmp_v3,
1304 .max = 1
1305 },
1306 };
1307
1308 static const struct switch_attr ar8327_sw_attr_port[] = {
1309 {
1310 .type = SWITCH_TYPE_NOVAL,
1311 .name = "reset_mib",
1312 .description = "Reset single port MIB counters",
1313 .set = ar8xxx_sw_set_port_reset_mib,
1314 },
1315 {
1316 .type = SWITCH_TYPE_STRING,
1317 .name = "mib",
1318 .description = "Get port's MIB counters",
1319 .set = NULL,
1320 .get = ar8xxx_sw_get_port_mib,
1321 },
1322 {
1323 .type = SWITCH_TYPE_INT,
1324 .name = "enable_eee",
1325 .description = "Enable EEE PHY sleep mode",
1326 .set = ar8327_sw_set_eee,
1327 .get = ar8327_sw_get_eee,
1328 .max = 1,
1329 },
1330 {
1331 .type = SWITCH_TYPE_NOVAL,
1332 .name = "flush_arl_table",
1333 .description = "Flush port's ARL table entries",
1334 .set = ar8xxx_sw_set_flush_port_arl_table,
1335 },
1336 {
1337 .type = SWITCH_TYPE_INT,
1338 .name = "igmp_snooping",
1339 .description = "Enable port's IGMP Snooping",
1340 .set = ar8327_sw_set_port_igmp_snooping,
1341 .get = ar8327_sw_get_port_igmp_snooping,
1342 .max = 1
1343 },
1344 };
1345
1346 static const struct switch_dev_ops ar8327_sw_ops = {
1347 .attr_global = {
1348 .attr = ar8327_sw_attr_globals,
1349 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
1350 },
1351 .attr_port = {
1352 .attr = ar8327_sw_attr_port,
1353 .n_attr = ARRAY_SIZE(ar8327_sw_attr_port),
1354 },
1355 .attr_vlan = {
1356 .attr = ar8xxx_sw_attr_vlan,
1357 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1358 },
1359 .get_port_pvid = ar8xxx_sw_get_pvid,
1360 .set_port_pvid = ar8xxx_sw_set_pvid,
1361 .get_vlan_ports = ar8327_sw_get_ports,
1362 .set_vlan_ports = ar8327_sw_set_ports,
1363 .apply_config = ar8327_sw_hw_apply,
1364 .reset_switch = ar8xxx_sw_reset_switch,
1365 .get_port_link = ar8xxx_sw_get_port_link,
1366 };
1367
1368 const struct ar8xxx_chip ar8327_chip = {
1369 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1370 .config_at_probe = true,
1371 .mii_lo_first = true,
1372
1373 .name = "Atheros AR8327",
1374 .ports = AR8327_NUM_PORTS,
1375 .vlans = AR8X16_MAX_VLANS,
1376 .swops = &ar8327_sw_ops,
1377
1378 .reg_port_stats_start = 0x1000,
1379 .reg_port_stats_length = 0x100,
1380
1381 .hw_init = ar8327_hw_init,
1382 .cleanup = ar8327_cleanup,
1383 .init_globals = ar8327_init_globals,
1384 .init_port = ar8327_init_port,
1385 .setup_port = ar8327_setup_port,
1386 .read_port_status = ar8327_read_port_status,
1387 .read_port_eee_status = ar8327_read_port_eee_status,
1388 .atu_flush = ar8327_atu_flush,
1389 .atu_flush_port = ar8327_atu_flush_port,
1390 .vtu_flush = ar8327_vtu_flush,
1391 .vtu_load_vlan = ar8327_vtu_load_vlan,
1392 .phy_fixup = ar8327_phy_fixup,
1393 .set_mirror_regs = ar8327_set_mirror_regs,
1394 .get_arl_entry = ar8327_get_arl_entry,
1395 .sw_hw_apply = ar8327_sw_hw_apply,
1396
1397 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1398 .mib_decs = ar8236_mibs,
1399 .mib_func = AR8327_REG_MIB_FUNC
1400 };
1401
1402 const struct ar8xxx_chip ar8337_chip = {
1403 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1404 .config_at_probe = true,
1405 .mii_lo_first = true,
1406
1407 .name = "Atheros AR8337",
1408 .ports = AR8327_NUM_PORTS,
1409 .vlans = AR8X16_MAX_VLANS,
1410 .swops = &ar8327_sw_ops,
1411
1412 .reg_port_stats_start = 0x1000,
1413 .reg_port_stats_length = 0x100,
1414
1415 .hw_init = ar8327_hw_init,
1416 .cleanup = ar8327_cleanup,
1417 .init_globals = ar8327_init_globals,
1418 .init_port = ar8327_init_port,
1419 .setup_port = ar8327_setup_port,
1420 .read_port_status = ar8327_read_port_status,
1421 .read_port_eee_status = ar8327_read_port_eee_status,
1422 .atu_flush = ar8327_atu_flush,
1423 .atu_flush_port = ar8327_atu_flush_port,
1424 .vtu_flush = ar8327_vtu_flush,
1425 .vtu_load_vlan = ar8327_vtu_load_vlan,
1426 .phy_fixup = ar8327_phy_fixup,
1427 .set_mirror_regs = ar8327_set_mirror_regs,
1428 .get_arl_entry = ar8327_get_arl_entry,
1429 .sw_hw_apply = ar8327_sw_hw_apply,
1430
1431 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1432 .mib_decs = ar8236_mibs,
1433 .mib_func = AR8327_REG_MIB_FUNC
1434 };
1435
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