b53: fix memory out of bounds access on 64 bit targets
[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / b53 / b53_common.c
1 /*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
21 #include <linux/delay.h>
22 #include <linux/export.h>
23 #include <linux/gpio.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/switch.h>
27 #include <linux/platform_data/b53.h>
28
29 #include "b53_regs.h"
30 #include "b53_priv.h"
31
32 /* buffer size needed for displaying all MIBs with max'd values */
33 #define B53_BUF_SIZE 1188
34
35 struct b53_mib_desc {
36 u8 size;
37 u8 offset;
38 const char *name;
39 };
40
41
42 /* BCM5365 MIB counters */
43 static const struct b53_mib_desc b53_mibs_65[] = {
44 { 8, 0x00, "TxOctets" },
45 { 4, 0x08, "TxDropPkts" },
46 { 4, 0x10, "TxBroadcastPkts" },
47 { 4, 0x14, "TxMulticastPkts" },
48 { 4, 0x18, "TxUnicastPkts" },
49 { 4, 0x1c, "TxCollisions" },
50 { 4, 0x20, "TxSingleCollision" },
51 { 4, 0x24, "TxMultipleCollision" },
52 { 4, 0x28, "TxDeferredTransmit" },
53 { 4, 0x2c, "TxLateCollision" },
54 { 4, 0x30, "TxExcessiveCollision" },
55 { 4, 0x38, "TxPausePkts" },
56 { 8, 0x44, "RxOctets" },
57 { 4, 0x4c, "RxUndersizePkts" },
58 { 4, 0x50, "RxPausePkts" },
59 { 4, 0x54, "Pkts64Octets" },
60 { 4, 0x58, "Pkts65to127Octets" },
61 { 4, 0x5c, "Pkts128to255Octets" },
62 { 4, 0x60, "Pkts256to511Octets" },
63 { 4, 0x64, "Pkts512to1023Octets" },
64 { 4, 0x68, "Pkts1024to1522Octets" },
65 { 4, 0x6c, "RxOversizePkts" },
66 { 4, 0x70, "RxJabbers" },
67 { 4, 0x74, "RxAlignmentErrors" },
68 { 4, 0x78, "RxFCSErrors" },
69 { 8, 0x7c, "RxGoodOctets" },
70 { 4, 0x84, "RxDropPkts" },
71 { 4, 0x88, "RxUnicastPkts" },
72 { 4, 0x8c, "RxMulticastPkts" },
73 { 4, 0x90, "RxBroadcastPkts" },
74 { 4, 0x94, "RxSAChanges" },
75 { 4, 0x98, "RxFragments" },
76 { },
77 };
78
79 /* BCM63xx MIB counters */
80 static const struct b53_mib_desc b53_mibs_63xx[] = {
81 { 8, 0x00, "TxOctets" },
82 { 4, 0x08, "TxDropPkts" },
83 { 4, 0x0c, "TxQoSPkts" },
84 { 4, 0x10, "TxBroadcastPkts" },
85 { 4, 0x14, "TxMulticastPkts" },
86 { 4, 0x18, "TxUnicastPkts" },
87 { 4, 0x1c, "TxCollisions" },
88 { 4, 0x20, "TxSingleCollision" },
89 { 4, 0x24, "TxMultipleCollision" },
90 { 4, 0x28, "TxDeferredTransmit" },
91 { 4, 0x2c, "TxLateCollision" },
92 { 4, 0x30, "TxExcessiveCollision" },
93 { 4, 0x38, "TxPausePkts" },
94 { 8, 0x3c, "TxQoSOctets" },
95 { 8, 0x44, "RxOctets" },
96 { 4, 0x4c, "RxUndersizePkts" },
97 { 4, 0x50, "RxPausePkts" },
98 { 4, 0x54, "Pkts64Octets" },
99 { 4, 0x58, "Pkts65to127Octets" },
100 { 4, 0x5c, "Pkts128to255Octets" },
101 { 4, 0x60, "Pkts256to511Octets" },
102 { 4, 0x64, "Pkts512to1023Octets" },
103 { 4, 0x68, "Pkts1024to1522Octets" },
104 { 4, 0x6c, "RxOversizePkts" },
105 { 4, 0x70, "RxJabbers" },
106 { 4, 0x74, "RxAlignmentErrors" },
107 { 4, 0x78, "RxFCSErrors" },
108 { 8, 0x7c, "RxGoodOctets" },
109 { 4, 0x84, "RxDropPkts" },
110 { 4, 0x88, "RxUnicastPkts" },
111 { 4, 0x8c, "RxMulticastPkts" },
112 { 4, 0x90, "RxBroadcastPkts" },
113 { 4, 0x94, "RxSAChanges" },
114 { 4, 0x98, "RxFragments" },
115 { 4, 0xa0, "RxSymbolErrors" },
116 { 4, 0xa4, "RxQoSPkts" },
117 { 8, 0xa8, "RxQoSOctets" },
118 { 4, 0xb0, "Pkts1523to2047Octets" },
119 { 4, 0xb4, "Pkts2048to4095Octets" },
120 { 4, 0xb8, "Pkts4096to8191Octets" },
121 { 4, 0xbc, "Pkts8192to9728Octets" },
122 { 4, 0xc0, "RxDiscarded" },
123 { }
124 };
125
126 /* MIB counters */
127 static const struct b53_mib_desc b53_mibs[] = {
128 { 8, 0x00, "TxOctets" },
129 { 4, 0x08, "TxDropPkts" },
130 { 4, 0x10, "TxBroadcastPkts" },
131 { 4, 0x14, "TxMulticastPkts" },
132 { 4, 0x18, "TxUnicastPkts" },
133 { 4, 0x1c, "TxCollisions" },
134 { 4, 0x20, "TxSingleCollision" },
135 { 4, 0x24, "TxMultipleCollision" },
136 { 4, 0x28, "TxDeferredTransmit" },
137 { 4, 0x2c, "TxLateCollision" },
138 { 4, 0x30, "TxExcessiveCollision" },
139 { 4, 0x38, "TxPausePkts" },
140 { 8, 0x50, "RxOctets" },
141 { 4, 0x58, "RxUndersizePkts" },
142 { 4, 0x5c, "RxPausePkts" },
143 { 4, 0x60, "Pkts64Octets" },
144 { 4, 0x64, "Pkts65to127Octets" },
145 { 4, 0x68, "Pkts128to255Octets" },
146 { 4, 0x6c, "Pkts256to511Octets" },
147 { 4, 0x70, "Pkts512to1023Octets" },
148 { 4, 0x74, "Pkts1024to1522Octets" },
149 { 4, 0x78, "RxOversizePkts" },
150 { 4, 0x7c, "RxJabbers" },
151 { 4, 0x80, "RxAlignmentErrors" },
152 { 4, 0x84, "RxFCSErrors" },
153 { 8, 0x88, "RxGoodOctets" },
154 { 4, 0x90, "RxDropPkts" },
155 { 4, 0x94, "RxUnicastPkts" },
156 { 4, 0x98, "RxMulticastPkts" },
157 { 4, 0x9c, "RxBroadcastPkts" },
158 { 4, 0xa0, "RxSAChanges" },
159 { 4, 0xa4, "RxFragments" },
160 { 4, 0xa8, "RxJumboPkts" },
161 { 4, 0xac, "RxSymbolErrors" },
162 { 4, 0xc0, "RxDiscarded" },
163 { }
164 };
165
166 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
167 {
168 unsigned int i;
169
170 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
171
172 for (i = 0; i < 10; i++) {
173 u8 vta;
174
175 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
176 if (!(vta & VTA_START_CMD))
177 return 0;
178
179 usleep_range(100, 200);
180 }
181
182 return -EIO;
183 }
184
185 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, u16 members,
186 u16 untag)
187 {
188 if (is5325(dev)) {
189 u32 entry = 0;
190
191 if (members) {
192 entry = ((untag & VA_UNTAG_MASK_25) << VA_UNTAG_S_25) |
193 members;
194 if (dev->core_rev >= 3)
195 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
196 else
197 entry |= VA_VALID_25;
198 }
199
200 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
201 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
202 VTA_RW_STATE_WR | VTA_RW_OP_EN);
203 } else if (is5365(dev)) {
204 u16 entry = 0;
205
206 if (members)
207 entry = ((untag & VA_UNTAG_MASK_65) << VA_UNTAG_S_65) |
208 members | VA_VALID_65;
209
210 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
211 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
212 VTA_RW_STATE_WR | VTA_RW_OP_EN);
213 } else {
214 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
215 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
216 (untag << VTE_UNTAG_S) | members);
217
218 b53_do_vlan_op(dev, VTA_CMD_WRITE);
219 }
220 }
221
222 void b53_set_forwarding(struct b53_device *dev, int enable)
223 {
224 u8 mgmt;
225
226 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
227
228 if (enable)
229 mgmt |= SM_SW_FWD_EN;
230 else
231 mgmt &= ~SM_SW_FWD_EN;
232
233 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
234 }
235
236 static void b53_enable_vlan(struct b53_device *dev, int enable)
237 {
238 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
239
240 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
241 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
242 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
243
244 if (is5325(dev) || is5365(dev)) {
245 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
246 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
247 } else if (is63xx(dev)) {
248 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
249 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
250 } else {
251 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
252 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
253 }
254
255 mgmt &= ~SM_SW_FWD_MODE;
256
257 if (enable) {
258 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
259 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
260 vc4 &= ~VC4_ING_VID_CHECK_MASK;
261 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
262 vc5 |= VC5_DROP_VTABLE_MISS;
263
264 if (is5325(dev))
265 vc0 &= ~VC0_RESERVED_1;
266
267 if (is5325(dev) || is5365(dev))
268 vc1 |= VC1_RX_MCST_TAG_EN;
269
270 if (!is5325(dev) && !is5365(dev)) {
271 if (dev->allow_vid_4095)
272 vc5 |= VC5_VID_FFF_EN;
273 else
274 vc5 &= ~VC5_VID_FFF_EN;
275 }
276 } else {
277 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
278 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
279 vc4 &= ~VC4_ING_VID_CHECK_MASK;
280 vc5 &= ~VC5_DROP_VTABLE_MISS;
281
282 if (is5325(dev) || is5365(dev))
283 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
284 else
285 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
286
287 if (is5325(dev) || is5365(dev))
288 vc1 &= ~VC1_RX_MCST_TAG_EN;
289
290 if (!is5325(dev) && !is5365(dev))
291 vc5 &= ~VC5_VID_FFF_EN;
292 }
293
294 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
295 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
296
297 if (is5325(dev) || is5365(dev)) {
298 /* enable the high 8 bit vid check on 5325 */
299 if (is5325(dev) && enable)
300 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
301 VC3_HIGH_8BIT_EN);
302 else
303 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
304
305 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
306 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
307 } else if (is63xx(dev)) {
308 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
309 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
310 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
311 } else {
312 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
313 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
314 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
315 }
316
317 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
318 }
319
320 static int b53_set_jumbo(struct b53_device *dev, int enable, int allow_10_100)
321 {
322 u32 port_mask = 0;
323 u16 max_size = JMS_MIN_SIZE;
324
325 if (is5325(dev) || is5365(dev))
326 return -EINVAL;
327
328 if (enable) {
329 port_mask = dev->enabled_ports;
330 max_size = JMS_MAX_SIZE;
331 if (allow_10_100)
332 port_mask |= JPM_10_100_JUMBO_EN;
333 }
334
335 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
336 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
337 }
338
339 static int b53_flush_arl(struct b53_device *dev)
340 {
341 unsigned int i;
342
343 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
344 FAST_AGE_DONE | FAST_AGE_DYNAMIC | FAST_AGE_STATIC);
345
346 for (i = 0; i < 10; i++) {
347 u8 fast_age_ctrl;
348
349 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
350 &fast_age_ctrl);
351
352 if (!(fast_age_ctrl & FAST_AGE_DONE))
353 return 0;
354
355 mdelay(1);
356 }
357
358 pr_warn("time out while flushing ARL\n");
359
360 return -EINVAL;
361 }
362
363 static void b53_enable_ports(struct b53_device *dev)
364 {
365 unsigned i;
366
367 b53_for_each_port(dev, i) {
368 u8 port_ctrl;
369 u16 pvlan_mask;
370
371 /*
372 * prevent leaking packets between wan and lan in unmanaged
373 * mode through port vlans.
374 */
375 if (dev->enable_vlan || is_cpu_port(dev, i))
376 pvlan_mask = 0x1ff;
377 else if (is531x5(dev) || is5301x(dev))
378 /* BCM53115 may use a different port as cpu port */
379 pvlan_mask = BIT(dev->sw_dev.cpu_port);
380 else
381 pvlan_mask = BIT(B53_CPU_PORT);
382
383 /* BCM5325 CPU port is at 8 */
384 if ((is5325(dev) || is5365(dev)) && i == B53_CPU_PORT_25)
385 i = B53_CPU_PORT;
386
387 if (dev->chip_id == BCM5398_DEVICE_ID && (i == 6 || i == 7))
388 /* disable unused ports 6 & 7 */
389 port_ctrl = PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
390 else if (i == B53_CPU_PORT)
391 port_ctrl = PORT_CTRL_RX_BCST_EN |
392 PORT_CTRL_RX_MCST_EN |
393 PORT_CTRL_RX_UCST_EN;
394 else
395 port_ctrl = 0;
396
397 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i),
398 pvlan_mask);
399
400 /* port state is handled by bcm63xx_enet driver */
401 if (!is63xx(dev) && !(is5301x(dev) && i == 6))
402 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(i),
403 port_ctrl);
404 }
405 }
406
407 static void b53_enable_mib(struct b53_device *dev)
408 {
409 u8 gc;
410
411 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
412
413 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
414
415 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
416 }
417
418 static int b53_apply(struct b53_device *dev)
419 {
420 int i;
421
422 /* clear all vlan entries */
423 if (is5325(dev) || is5365(dev)) {
424 for (i = 1; i < dev->sw_dev.vlans; i++)
425 b53_set_vlan_entry(dev, i, 0, 0);
426 } else {
427 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
428 }
429
430 b53_enable_vlan(dev, dev->enable_vlan);
431
432 /* fill VLAN table */
433 if (dev->enable_vlan) {
434 for (i = 0; i < dev->sw_dev.vlans; i++) {
435 struct b53_vlan *vlan = &dev->vlans[i];
436
437 if (!vlan->members)
438 continue;
439
440 b53_set_vlan_entry(dev, i, vlan->members, vlan->untag);
441 }
442
443 b53_for_each_port(dev, i)
444 b53_write16(dev, B53_VLAN_PAGE,
445 B53_VLAN_PORT_DEF_TAG(i),
446 dev->ports[i].pvid);
447 } else {
448 b53_for_each_port(dev, i)
449 b53_write16(dev, B53_VLAN_PAGE,
450 B53_VLAN_PORT_DEF_TAG(i), 1);
451
452 }
453
454 b53_enable_ports(dev);
455
456 if (!is5325(dev) && !is5365(dev))
457 b53_set_jumbo(dev, dev->enable_jumbo, 1);
458
459 return 0;
460 }
461
462 static void b53_switch_reset_gpio(struct b53_device *dev)
463 {
464 int gpio = dev->reset_gpio;
465
466 if (gpio < 0)
467 return;
468
469 /*
470 * Reset sequence: RESET low(50ms)->high(20ms)
471 */
472 gpio_set_value(gpio, 0);
473 mdelay(50);
474
475 gpio_set_value(gpio, 1);
476 mdelay(20);
477
478 dev->current_page = 0xff;
479 }
480
481 static int b53_switch_reset(struct b53_device *dev)
482 {
483 u8 cpu_port = dev->sw_dev.cpu_port;
484 u8 mgmt;
485
486 b53_switch_reset_gpio(dev);
487
488 if (is539x(dev)) {
489 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
490 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
491 }
492
493 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
494
495 if (!(mgmt & SM_SW_FWD_EN)) {
496 mgmt &= ~SM_SW_FWD_MODE;
497 mgmt |= SM_SW_FWD_EN;
498
499 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
500 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
501
502 if (!(mgmt & SM_SW_FWD_EN)) {
503 pr_err("Failed to enable switch!\n");
504 return -EINVAL;
505 }
506 }
507
508 /* enable all ports */
509 b53_enable_ports(dev);
510
511 /* configure MII port if necessary */
512 if (is5325(dev)) {
513 u8 mii_port_override;
514
515 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
516 &mii_port_override);
517 /* reverse mii needs to be enabled */
518 if (!(mii_port_override & PORT_OVERRIDE_RV_MII_25)) {
519 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
520 mii_port_override | PORT_OVERRIDE_RV_MII_25);
521 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
522 &mii_port_override);
523
524 if (!(mii_port_override & PORT_OVERRIDE_RV_MII_25)) {
525 pr_err("Failed to enable reverse MII mode\n");
526 return -EINVAL;
527 }
528 }
529 } else if (is531x5(dev) && cpu_port == B53_CPU_PORT) {
530 u8 mii_port_override;
531
532 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
533 &mii_port_override);
534 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
535 mii_port_override | PORT_OVERRIDE_EN |
536 PORT_OVERRIDE_LINK);
537 } else if (is5301x(dev)) {
538 if (cpu_port == 8) {
539 u8 mii_port_override;
540
541 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
542 &mii_port_override);
543 mii_port_override |= PORT_OVERRIDE_LINK |
544 PORT_OVERRIDE_RX_FLOW |
545 PORT_OVERRIDE_TX_FLOW |
546 PORT_OVERRIDE_SPEED_2000M |
547 PORT_OVERRIDE_EN;
548 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
549 mii_port_override);
550
551 /* TODO: Ports 5 & 7 require some extra handling */
552 } else {
553 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(cpu_port);
554 u8 gmii_po;
555
556 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
557 gmii_po |= GMII_PO_LINK |
558 GMII_PO_RX_FLOW |
559 GMII_PO_TX_FLOW |
560 GMII_PO_EN |
561 GMII_PO_SPEED_2000M;
562 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
563 }
564 }
565
566 b53_enable_mib(dev);
567
568 return b53_flush_arl(dev);
569 }
570
571 /*
572 * Swconfig glue functions
573 */
574
575 static int b53_global_get_vlan_enable(struct switch_dev *dev,
576 const struct switch_attr *attr,
577 struct switch_val *val)
578 {
579 struct b53_device *priv = sw_to_b53(dev);
580
581 val->value.i = priv->enable_vlan;
582
583 return 0;
584 }
585
586 static int b53_global_set_vlan_enable(struct switch_dev *dev,
587 const struct switch_attr *attr,
588 struct switch_val *val)
589 {
590 struct b53_device *priv = sw_to_b53(dev);
591
592 priv->enable_vlan = val->value.i;
593
594 return 0;
595 }
596
597 static int b53_global_get_jumbo_enable(struct switch_dev *dev,
598 const struct switch_attr *attr,
599 struct switch_val *val)
600 {
601 struct b53_device *priv = sw_to_b53(dev);
602
603 val->value.i = priv->enable_jumbo;
604
605 return 0;
606 }
607
608 static int b53_global_set_jumbo_enable(struct switch_dev *dev,
609 const struct switch_attr *attr,
610 struct switch_val *val)
611 {
612 struct b53_device *priv = sw_to_b53(dev);
613
614 priv->enable_jumbo = val->value.i;
615
616 return 0;
617 }
618
619 static int b53_global_get_4095_enable(struct switch_dev *dev,
620 const struct switch_attr *attr,
621 struct switch_val *val)
622 {
623 struct b53_device *priv = sw_to_b53(dev);
624
625 val->value.i = priv->allow_vid_4095;
626
627 return 0;
628 }
629
630 static int b53_global_set_4095_enable(struct switch_dev *dev,
631 const struct switch_attr *attr,
632 struct switch_val *val)
633 {
634 struct b53_device *priv = sw_to_b53(dev);
635
636 priv->allow_vid_4095 = val->value.i;
637
638 return 0;
639 }
640
641 static int b53_global_get_ports(struct switch_dev *dev,
642 const struct switch_attr *attr,
643 struct switch_val *val)
644 {
645 struct b53_device *priv = sw_to_b53(dev);
646
647 val->len = snprintf(priv->buf, B53_BUF_SIZE, "0x%04x",
648 priv->enabled_ports);
649 val->value.s = priv->buf;
650
651 return 0;
652 }
653
654 static int b53_port_get_pvid(struct switch_dev *dev, int port, int *val)
655 {
656 struct b53_device *priv = sw_to_b53(dev);
657
658 *val = priv->ports[port].pvid;
659
660 return 0;
661 }
662
663 static int b53_port_set_pvid(struct switch_dev *dev, int port, int val)
664 {
665 struct b53_device *priv = sw_to_b53(dev);
666
667 if (val > 15 && is5325(priv))
668 return -EINVAL;
669 if (val == 4095 && !priv->allow_vid_4095)
670 return -EINVAL;
671
672 priv->ports[port].pvid = val;
673
674 return 0;
675 }
676
677 static int b53_vlan_get_ports(struct switch_dev *dev, struct switch_val *val)
678 {
679 struct b53_device *priv = sw_to_b53(dev);
680 struct switch_port *port = &val->value.ports[0];
681 struct b53_vlan *vlan = &priv->vlans[val->port_vlan];
682 int i;
683
684 val->len = 0;
685
686 if (!vlan->members)
687 return 0;
688
689 for (i = 0; i < dev->ports; i++) {
690 if (!(vlan->members & BIT(i)))
691 continue;
692
693
694 if (!(vlan->untag & BIT(i)))
695 port->flags = BIT(SWITCH_PORT_FLAG_TAGGED);
696 else
697 port->flags = 0;
698
699 port->id = i;
700 val->len++;
701 port++;
702 }
703
704 return 0;
705 }
706
707 static int b53_vlan_set_ports(struct switch_dev *dev, struct switch_val *val)
708 {
709 struct b53_device *priv = sw_to_b53(dev);
710 struct switch_port *port;
711 struct b53_vlan *vlan = &priv->vlans[val->port_vlan];
712 int i;
713
714 /* only BCM5325 and BCM5365 supports VID 0 */
715 if (val->port_vlan == 0 && !is5325(priv) && !is5365(priv))
716 return -EINVAL;
717
718 /* VLAN 4095 needs special handling */
719 if (val->port_vlan == 4095 && !priv->allow_vid_4095)
720 return -EINVAL;
721
722 port = &val->value.ports[0];
723 vlan->members = 0;
724 vlan->untag = 0;
725 for (i = 0; i < val->len; i++, port++) {
726 vlan->members |= BIT(port->id);
727
728 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED))) {
729 vlan->untag |= BIT(port->id);
730 priv->ports[port->id].pvid = val->port_vlan;
731 };
732 }
733
734 /* ignore disabled ports */
735 vlan->members &= priv->enabled_ports;
736 vlan->untag &= priv->enabled_ports;
737
738 return 0;
739 }
740
741 static int b53_port_get_link(struct switch_dev *dev, int port,
742 struct switch_port_link *link)
743 {
744 struct b53_device *priv = sw_to_b53(dev);
745
746 if (is_cpu_port(priv, port)) {
747 link->link = 1;
748 link->duplex = 1;
749 link->speed = is5325(priv) || is5365(priv) ?
750 SWITCH_PORT_SPEED_100 : SWITCH_PORT_SPEED_1000;
751 link->aneg = 0;
752 } else if (priv->enabled_ports & BIT(port)) {
753 u32 speed;
754 u16 lnk, duplex;
755
756 b53_read16(priv, B53_STAT_PAGE, B53_LINK_STAT, &lnk);
757 b53_read16(priv, B53_STAT_PAGE, priv->duplex_reg, &duplex);
758
759 lnk = (lnk >> port) & 1;
760 duplex = (duplex >> port) & 1;
761
762 if (is5325(priv) || is5365(priv)) {
763 u16 tmp;
764
765 b53_read16(priv, B53_STAT_PAGE, B53_SPEED_STAT, &tmp);
766 speed = SPEED_PORT_FE(tmp, port);
767 } else {
768 b53_read32(priv, B53_STAT_PAGE, B53_SPEED_STAT, &speed);
769 speed = SPEED_PORT_GE(speed, port);
770 }
771
772 link->link = lnk;
773 if (lnk) {
774 link->duplex = duplex;
775 switch (speed) {
776 case SPEED_STAT_10M:
777 link->speed = SWITCH_PORT_SPEED_10;
778 break;
779 case SPEED_STAT_100M:
780 link->speed = SWITCH_PORT_SPEED_100;
781 break;
782 case SPEED_STAT_1000M:
783 link->speed = SWITCH_PORT_SPEED_1000;
784 break;
785 }
786 }
787
788 link->aneg = 1;
789 } else {
790 link->link = 0;
791 }
792
793 return 0;
794
795 }
796
797 static int b53_global_reset_switch(struct switch_dev *dev)
798 {
799 struct b53_device *priv = sw_to_b53(dev);
800
801 /* reset vlans */
802 priv->enable_vlan = 0;
803 priv->enable_jumbo = 0;
804 priv->allow_vid_4095 = 0;
805
806 memset(priv->vlans, 0, sizeof(*priv->vlans) * dev->vlans);
807 memset(priv->ports, 0, sizeof(*priv->ports) * dev->ports);
808
809 return b53_switch_reset(priv);
810 }
811
812 static int b53_global_apply_config(struct switch_dev *dev)
813 {
814 struct b53_device *priv = sw_to_b53(dev);
815
816 /* disable switching */
817 b53_set_forwarding(priv, 0);
818
819 b53_apply(priv);
820
821 /* enable switching */
822 b53_set_forwarding(priv, 1);
823
824 return 0;
825 }
826
827
828 static int b53_global_reset_mib(struct switch_dev *dev,
829 const struct switch_attr *attr,
830 struct switch_val *val)
831 {
832 struct b53_device *priv = sw_to_b53(dev);
833 u8 gc;
834
835 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
836
837 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
838 mdelay(1);
839 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
840 mdelay(1);
841
842 return 0;
843 }
844
845 static int b53_port_get_mib(struct switch_dev *sw_dev,
846 const struct switch_attr *attr,
847 struct switch_val *val)
848 {
849 struct b53_device *dev = sw_to_b53(sw_dev);
850 const struct b53_mib_desc *mibs;
851 int port = val->port_vlan;
852 int len = 0;
853
854 if (!(BIT(port) & dev->enabled_ports))
855 return -1;
856
857 if (is5365(dev)) {
858 if (port == 5)
859 port = 8;
860
861 mibs = b53_mibs_65;
862 } else if (is63xx(dev)) {
863 mibs = b53_mibs_63xx;
864 } else {
865 mibs = b53_mibs;
866 }
867
868 dev->buf[0] = 0;
869
870 for (; mibs->size > 0; mibs++) {
871 u64 val;
872
873 if (mibs->size == 8) {
874 b53_read64(dev, B53_MIB_PAGE(port), mibs->offset, &val);
875 } else {
876 u32 val32;
877
878 b53_read32(dev, B53_MIB_PAGE(port), mibs->offset,
879 &val32);
880 val = val32;
881 }
882
883 len += snprintf(dev->buf + len, B53_BUF_SIZE - len,
884 "%-20s: %llu\n", mibs->name, val);
885 }
886
887 val->len = len;
888 val->value.s = dev->buf;
889
890 return 0;
891 }
892
893 static struct switch_attr b53_global_ops_25[] = {
894 {
895 .type = SWITCH_TYPE_INT,
896 .name = "enable_vlan",
897 .description = "Enable VLAN mode",
898 .set = b53_global_set_vlan_enable,
899 .get = b53_global_get_vlan_enable,
900 .max = 1,
901 },
902 {
903 .type = SWITCH_TYPE_STRING,
904 .name = "ports",
905 .description = "Available ports (as bitmask)",
906 .get = b53_global_get_ports,
907 },
908 };
909
910 static struct switch_attr b53_global_ops_65[] = {
911 {
912 .type = SWITCH_TYPE_INT,
913 .name = "enable_vlan",
914 .description = "Enable VLAN mode",
915 .set = b53_global_set_vlan_enable,
916 .get = b53_global_get_vlan_enable,
917 .max = 1,
918 },
919 {
920 .type = SWITCH_TYPE_STRING,
921 .name = "ports",
922 .description = "Available ports (as bitmask)",
923 .get = b53_global_get_ports,
924 },
925 {
926 .type = SWITCH_TYPE_INT,
927 .name = "reset_mib",
928 .description = "Reset MIB counters",
929 .set = b53_global_reset_mib,
930 },
931 };
932
933 static struct switch_attr b53_global_ops[] = {
934 {
935 .type = SWITCH_TYPE_INT,
936 .name = "enable_vlan",
937 .description = "Enable VLAN mode",
938 .set = b53_global_set_vlan_enable,
939 .get = b53_global_get_vlan_enable,
940 .max = 1,
941 },
942 {
943 .type = SWITCH_TYPE_STRING,
944 .name = "ports",
945 .description = "Available Ports (as bitmask)",
946 .get = b53_global_get_ports,
947 },
948 {
949 .type = SWITCH_TYPE_INT,
950 .name = "reset_mib",
951 .description = "Reset MIB counters",
952 .set = b53_global_reset_mib,
953 },
954 {
955 .type = SWITCH_TYPE_INT,
956 .name = "enable_jumbo",
957 .description = "Enable Jumbo Frames",
958 .set = b53_global_set_jumbo_enable,
959 .get = b53_global_get_jumbo_enable,
960 .max = 1,
961 },
962 {
963 .type = SWITCH_TYPE_INT,
964 .name = "allow_vid_4095",
965 .description = "Allow VID 4095",
966 .set = b53_global_set_4095_enable,
967 .get = b53_global_get_4095_enable,
968 .max = 1,
969 },
970 };
971
972 static struct switch_attr b53_port_ops[] = {
973 {
974 .type = SWITCH_TYPE_STRING,
975 .name = "mib",
976 .description = "Get port's MIB counters",
977 .get = b53_port_get_mib,
978 },
979 };
980
981 static struct switch_attr b53_no_ops[] = {
982 };
983
984 static const struct switch_dev_ops b53_switch_ops_25 = {
985 .attr_global = {
986 .attr = b53_global_ops_25,
987 .n_attr = ARRAY_SIZE(b53_global_ops_25),
988 },
989 .attr_port = {
990 .attr = b53_no_ops,
991 .n_attr = ARRAY_SIZE(b53_no_ops),
992 },
993 .attr_vlan = {
994 .attr = b53_no_ops,
995 .n_attr = ARRAY_SIZE(b53_no_ops),
996 },
997
998 .get_vlan_ports = b53_vlan_get_ports,
999 .set_vlan_ports = b53_vlan_set_ports,
1000 .get_port_pvid = b53_port_get_pvid,
1001 .set_port_pvid = b53_port_set_pvid,
1002 .apply_config = b53_global_apply_config,
1003 .reset_switch = b53_global_reset_switch,
1004 .get_port_link = b53_port_get_link,
1005 };
1006
1007 static const struct switch_dev_ops b53_switch_ops_65 = {
1008 .attr_global = {
1009 .attr = b53_global_ops_65,
1010 .n_attr = ARRAY_SIZE(b53_global_ops_65),
1011 },
1012 .attr_port = {
1013 .attr = b53_port_ops,
1014 .n_attr = ARRAY_SIZE(b53_port_ops),
1015 },
1016 .attr_vlan = {
1017 .attr = b53_no_ops,
1018 .n_attr = ARRAY_SIZE(b53_no_ops),
1019 },
1020
1021 .get_vlan_ports = b53_vlan_get_ports,
1022 .set_vlan_ports = b53_vlan_set_ports,
1023 .get_port_pvid = b53_port_get_pvid,
1024 .set_port_pvid = b53_port_set_pvid,
1025 .apply_config = b53_global_apply_config,
1026 .reset_switch = b53_global_reset_switch,
1027 .get_port_link = b53_port_get_link,
1028 };
1029
1030 static const struct switch_dev_ops b53_switch_ops = {
1031 .attr_global = {
1032 .attr = b53_global_ops,
1033 .n_attr = ARRAY_SIZE(b53_global_ops),
1034 },
1035 .attr_port = {
1036 .attr = b53_port_ops,
1037 .n_attr = ARRAY_SIZE(b53_port_ops),
1038 },
1039 .attr_vlan = {
1040 .attr = b53_no_ops,
1041 .n_attr = ARRAY_SIZE(b53_no_ops),
1042 },
1043
1044 .get_vlan_ports = b53_vlan_get_ports,
1045 .set_vlan_ports = b53_vlan_set_ports,
1046 .get_port_pvid = b53_port_get_pvid,
1047 .set_port_pvid = b53_port_set_pvid,
1048 .apply_config = b53_global_apply_config,
1049 .reset_switch = b53_global_reset_switch,
1050 .get_port_link = b53_port_get_link,
1051 };
1052
1053 struct b53_chip_data {
1054 u32 chip_id;
1055 const char *dev_name;
1056 const char *alias;
1057 u16 vlans;
1058 u16 enabled_ports;
1059 u8 cpu_port;
1060 u8 vta_regs[3];
1061 u8 duplex_reg;
1062 u8 jumbo_pm_reg;
1063 u8 jumbo_size_reg;
1064 const struct switch_dev_ops *sw_ops;
1065 };
1066
1067 #define B53_VTA_REGS \
1068 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1069 #define B53_VTA_REGS_9798 \
1070 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1071 #define B53_VTA_REGS_63XX \
1072 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1073
1074 static const struct b53_chip_data b53_switch_chips[] = {
1075 {
1076 .chip_id = BCM5325_DEVICE_ID,
1077 .dev_name = "BCM5325",
1078 .alias = "bcm5325",
1079 .vlans = 16,
1080 .enabled_ports = 0x1f,
1081 .cpu_port = B53_CPU_PORT_25,
1082 .duplex_reg = B53_DUPLEX_STAT_FE,
1083 .sw_ops = &b53_switch_ops_25,
1084 },
1085 {
1086 .chip_id = BCM5365_DEVICE_ID,
1087 .dev_name = "BCM5365",
1088 .alias = "bcm5365",
1089 .vlans = 256,
1090 .enabled_ports = 0x1f,
1091 .cpu_port = B53_CPU_PORT_25,
1092 .duplex_reg = B53_DUPLEX_STAT_FE,
1093 .sw_ops = &b53_switch_ops_65,
1094 },
1095 {
1096 .chip_id = BCM5395_DEVICE_ID,
1097 .dev_name = "BCM5395",
1098 .alias = "bcm5395",
1099 .vlans = 4096,
1100 .enabled_ports = 0x1f,
1101 .cpu_port = B53_CPU_PORT,
1102 .vta_regs = B53_VTA_REGS,
1103 .duplex_reg = B53_DUPLEX_STAT_GE,
1104 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1105 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1106 .sw_ops = &b53_switch_ops,
1107 },
1108 {
1109 .chip_id = BCM5397_DEVICE_ID,
1110 .dev_name = "BCM5397",
1111 .alias = "bcm5397",
1112 .vlans = 4096,
1113 .enabled_ports = 0x1f,
1114 .cpu_port = B53_CPU_PORT,
1115 .vta_regs = B53_VTA_REGS_9798,
1116 .duplex_reg = B53_DUPLEX_STAT_GE,
1117 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1118 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1119 .sw_ops = &b53_switch_ops,
1120 },
1121 {
1122 .chip_id = BCM5398_DEVICE_ID,
1123 .dev_name = "BCM5398",
1124 .alias = "bcm5398",
1125 .vlans = 4096,
1126 .enabled_ports = 0x7f,
1127 .cpu_port = B53_CPU_PORT,
1128 .vta_regs = B53_VTA_REGS_9798,
1129 .duplex_reg = B53_DUPLEX_STAT_GE,
1130 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1131 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1132 .sw_ops = &b53_switch_ops,
1133 },
1134 {
1135 .chip_id = BCM53115_DEVICE_ID,
1136 .dev_name = "BCM53115",
1137 .alias = "bcm53115",
1138 .vlans = 4096,
1139 .enabled_ports = 0x1f,
1140 .vta_regs = B53_VTA_REGS,
1141 .cpu_port = B53_CPU_PORT,
1142 .duplex_reg = B53_DUPLEX_STAT_GE,
1143 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1144 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1145 .sw_ops = &b53_switch_ops,
1146 },
1147 {
1148 .chip_id = BCM53125_DEVICE_ID,
1149 .dev_name = "BCM53125",
1150 .alias = "bcm53125",
1151 .vlans = 4096,
1152 .enabled_ports = 0x1f,
1153 .cpu_port = B53_CPU_PORT,
1154 .vta_regs = B53_VTA_REGS,
1155 .duplex_reg = B53_DUPLEX_STAT_GE,
1156 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1157 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1158 .sw_ops = &b53_switch_ops,
1159 },
1160 {
1161 .chip_id = BCM53128_DEVICE_ID,
1162 .dev_name = "BCM53128",
1163 .alias = "bcm53128",
1164 .vlans = 4096,
1165 .enabled_ports = 0x1ff,
1166 .cpu_port = B53_CPU_PORT,
1167 .vta_regs = B53_VTA_REGS,
1168 .duplex_reg = B53_DUPLEX_STAT_GE,
1169 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1170 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1171 .sw_ops = &b53_switch_ops,
1172 },
1173 {
1174 .chip_id = BCM63XX_DEVICE_ID,
1175 .dev_name = "BCM63xx",
1176 .alias = "bcm63xx",
1177 .vlans = 4096,
1178 .enabled_ports = 0, /* pdata must provide them */
1179 .cpu_port = B53_CPU_PORT,
1180 .vta_regs = B53_VTA_REGS_63XX,
1181 .duplex_reg = B53_DUPLEX_STAT_63XX,
1182 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1183 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1184 .sw_ops = &b53_switch_ops,
1185 },
1186 {
1187 .chip_id = BCM53010_DEVICE_ID,
1188 .dev_name = "BCM53010",
1189 .alias = "bcm53011",
1190 .vlans = 4096,
1191 .enabled_ports = 0x1f,
1192 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1193 .vta_regs = B53_VTA_REGS,
1194 .duplex_reg = B53_DUPLEX_STAT_GE,
1195 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1196 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1197 .sw_ops = &b53_switch_ops,
1198 },
1199 {
1200 .chip_id = BCM53011_DEVICE_ID,
1201 .dev_name = "BCM53011",
1202 .alias = "bcm53011",
1203 .vlans = 4096,
1204 .enabled_ports = 0x1f,
1205 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1206 .vta_regs = B53_VTA_REGS,
1207 .duplex_reg = B53_DUPLEX_STAT_GE,
1208 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1209 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1210 .sw_ops = &b53_switch_ops,
1211 },
1212 {
1213 .chip_id = BCM53012_DEVICE_ID,
1214 .dev_name = "BCM53012",
1215 .alias = "bcm53011",
1216 .vlans = 4096,
1217 .enabled_ports = 0x1bf,
1218 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1219 .vta_regs = B53_VTA_REGS,
1220 .duplex_reg = B53_DUPLEX_STAT_GE,
1221 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1222 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1223 .sw_ops = &b53_switch_ops,
1224 },
1225 {
1226 .chip_id = BCM53018_DEVICE_ID,
1227 .dev_name = "BCM53018",
1228 .alias = "bcm53018",
1229 .vlans = 4096,
1230 .enabled_ports = 0x1f,
1231 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1232 .vta_regs = B53_VTA_REGS,
1233 .duplex_reg = B53_DUPLEX_STAT_GE,
1234 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1235 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1236 .sw_ops = &b53_switch_ops,
1237 },
1238 {
1239 .chip_id = BCM53019_DEVICE_ID,
1240 .dev_name = "BCM53019",
1241 .alias = "bcm53019",
1242 .vlans = 4096,
1243 .enabled_ports = 0x1f,
1244 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1245 .vta_regs = B53_VTA_REGS,
1246 .duplex_reg = B53_DUPLEX_STAT_GE,
1247 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1248 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1249 .sw_ops = &b53_switch_ops,
1250 },
1251 };
1252
1253 static int b53_switch_init(struct b53_device *dev)
1254 {
1255 struct switch_dev *sw_dev = &dev->sw_dev;
1256 unsigned i;
1257 int ret;
1258
1259 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1260 const struct b53_chip_data *chip = &b53_switch_chips[i];
1261
1262 if (chip->chip_id == dev->chip_id) {
1263 sw_dev->name = chip->dev_name;
1264 if (!sw_dev->alias)
1265 sw_dev->alias = chip->alias;
1266 if (!dev->enabled_ports)
1267 dev->enabled_ports = chip->enabled_ports;
1268 dev->duplex_reg = chip->duplex_reg;
1269 dev->vta_regs[0] = chip->vta_regs[0];
1270 dev->vta_regs[1] = chip->vta_regs[1];
1271 dev->vta_regs[2] = chip->vta_regs[2];
1272 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1273 sw_dev->ops = chip->sw_ops;
1274 sw_dev->cpu_port = chip->cpu_port;
1275 sw_dev->vlans = chip->vlans;
1276 break;
1277 }
1278 }
1279
1280 if (!sw_dev->name)
1281 return -EINVAL;
1282
1283 /* check which BCM5325x version we have */
1284 if (is5325(dev)) {
1285 u8 vc4;
1286
1287 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1288
1289 /* check reserved bits */
1290 switch (vc4 & 3) {
1291 case 1:
1292 /* BCM5325E */
1293 break;
1294 case 3:
1295 /* BCM5325F - do not use port 4 */
1296 dev->enabled_ports &= ~BIT(4);
1297 break;
1298 default:
1299 /* On the BCM47XX SoCs this is the supported internal switch.*/
1300 #ifndef CONFIG_BCM47XX
1301 /* BCM5325M */
1302 return -EINVAL;
1303 #else
1304 break;
1305 #endif
1306 }
1307 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1308 u64 strap_value;
1309
1310 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1311 /* use second IMP port if GMII is enabled */
1312 if (strap_value & SV_GMII_CTRL_115)
1313 sw_dev->cpu_port = 5;
1314 }
1315
1316 /* cpu port is always last */
1317 sw_dev->ports = sw_dev->cpu_port + 1;
1318 dev->enabled_ports |= BIT(sw_dev->cpu_port);
1319
1320 dev->ports = devm_kzalloc(dev->dev,
1321 sizeof(struct b53_port) * sw_dev->ports,
1322 GFP_KERNEL);
1323 if (!dev->ports)
1324 return -ENOMEM;
1325
1326 dev->vlans = devm_kzalloc(dev->dev,
1327 sizeof(struct b53_vlan) * sw_dev->vlans,
1328 GFP_KERNEL);
1329 if (!dev->vlans)
1330 return -ENOMEM;
1331
1332 dev->buf = devm_kzalloc(dev->dev, B53_BUF_SIZE, GFP_KERNEL);
1333 if (!dev->buf)
1334 return -ENOMEM;
1335
1336 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1337 if (dev->reset_gpio >= 0) {
1338 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1339 GPIOF_OUT_INIT_HIGH, "robo_reset");
1340 if (ret)
1341 return ret;
1342 }
1343
1344 return b53_switch_reset(dev);
1345 }
1346
1347 struct b53_device *b53_switch_alloc(struct device *base, struct b53_io_ops *ops,
1348 void *priv)
1349 {
1350 struct b53_device *dev;
1351
1352 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
1353 if (!dev)
1354 return NULL;
1355
1356 dev->dev = base;
1357 dev->ops = ops;
1358 dev->priv = priv;
1359 mutex_init(&dev->reg_mutex);
1360
1361 return dev;
1362 }
1363 EXPORT_SYMBOL(b53_switch_alloc);
1364
1365 int b53_switch_detect(struct b53_device *dev)
1366 {
1367 u32 id32;
1368 u16 tmp;
1369 u8 id8;
1370 int ret;
1371
1372 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1373 if (ret)
1374 return ret;
1375
1376 switch (id8) {
1377 case 0:
1378 /*
1379 * BCM5325 and BCM5365 do not have this register so reads
1380 * return 0. But the read operation did succeed, so assume
1381 * this is one of them.
1382 *
1383 * Next check if we can write to the 5325's VTA register; for
1384 * 5365 it is read only.
1385 */
1386
1387 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1388 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
1389
1390 if (tmp == 0xf)
1391 dev->chip_id = BCM5325_DEVICE_ID;
1392 else
1393 dev->chip_id = BCM5365_DEVICE_ID;
1394 break;
1395 case BCM5395_DEVICE_ID:
1396 case BCM5397_DEVICE_ID:
1397 case BCM5398_DEVICE_ID:
1398 dev->chip_id = id8;
1399 break;
1400 default:
1401 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
1402 if (ret)
1403 return ret;
1404
1405 switch (id32) {
1406 case BCM53115_DEVICE_ID:
1407 case BCM53125_DEVICE_ID:
1408 case BCM53128_DEVICE_ID:
1409 case BCM53010_DEVICE_ID:
1410 case BCM53011_DEVICE_ID:
1411 case BCM53012_DEVICE_ID:
1412 case BCM53018_DEVICE_ID:
1413 case BCM53019_DEVICE_ID:
1414 dev->chip_id = id32;
1415 break;
1416 default:
1417 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1418 id8, id32);
1419 return -ENODEV;
1420 }
1421 }
1422
1423 if (dev->chip_id == BCM5325_DEVICE_ID)
1424 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
1425 &dev->core_rev);
1426 else
1427 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
1428 &dev->core_rev);
1429 }
1430 EXPORT_SYMBOL(b53_switch_detect);
1431
1432 int b53_switch_register(struct b53_device *dev)
1433 {
1434 int ret;
1435
1436 if (dev->pdata) {
1437 dev->chip_id = dev->pdata->chip_id;
1438 dev->enabled_ports = dev->pdata->enabled_ports;
1439 dev->sw_dev.alias = dev->pdata->alias;
1440 }
1441
1442 if (!dev->chip_id && b53_switch_detect(dev))
1443 return -EINVAL;
1444
1445 ret = b53_switch_init(dev);
1446 if (ret)
1447 return ret;
1448
1449 pr_info("found switch: %s, rev %i\n", dev->sw_dev.name, dev->core_rev);
1450
1451 return register_switch(&dev->sw_dev, NULL);
1452 }
1453 EXPORT_SYMBOL(b53_switch_register);
1454
1455 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1456 MODULE_DESCRIPTION("B53 switch library");
1457 MODULE_LICENSE("Dual BSD/GPL");